1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
10 CPL_SGE_EGR_UPDATE = 0xA5,
13 CPL_TX_PKT_LSO = 0xED,
17 enum { /* TX_PKT_XT checksum types */
30 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
49 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW)
50 #define RSS_HDR struct rss_header rss_hdr
56 struct work_request_hdr {
62 #define WR_HDR struct work_request_hdr wr
63 #define WR_HDR_SIZE sizeof(struct work_request_hdr)
76 struct cpl_tx_pkt_core {
85 struct cpl_tx_pkt_core c;
88 /* cpl_tx_pkt_core.ctrl0 fields */
90 #define M_TXPKT_PF 0x7
91 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)
92 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF)
94 #define S_TXPKT_INTF 16
95 #define M_TXPKT_INTF 0xF
96 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
97 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
99 #define S_TXPKT_OPCODE 24
100 #define M_TXPKT_OPCODE 0xFF
101 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
102 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
104 /* cpl_tx_pkt_core.ctrl1 fields */
105 #define S_TXPKT_IPHDR_LEN 20
106 #define M_TXPKT_IPHDR_LEN 0x3FFF
107 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
108 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)
110 #define S_TXPKT_ETHHDR_LEN 34
111 #define M_TXPKT_ETHHDR_LEN 0x3F
112 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
113 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)
115 #define S_T6_TXPKT_ETHHDR_LEN 32
116 #define M_T6_TXPKT_ETHHDR_LEN 0xFF
117 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN)
118 #define G_T6_TXPKT_ETHHDR_LEN(x) \
119 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN)
121 #define S_TXPKT_CSUM_TYPE 40
122 #define M_TXPKT_CSUM_TYPE 0xF
123 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
124 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE)
126 #define S_TXPKT_VLAN 44
127 #define M_TXPKT_VLAN 0xFFFF
128 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)
129 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
131 #define S_TXPKT_VLAN_VLD 60
132 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)
133 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL)
135 #define S_TXPKT_IPCSUM_DIS 62
136 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)
137 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL)
139 #define S_TXPKT_L4CSUM_DIS 63
140 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
141 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL)
143 struct cpl_tx_pkt_lso_core {
149 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
152 struct cpl_tx_pkt_lso {
154 struct cpl_tx_pkt_lso_core c;
155 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
158 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
159 #define S_LSO_TCPHDR_LEN 0
160 #define M_LSO_TCPHDR_LEN 0xF
161 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)
162 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN)
164 #define S_LSO_IPHDR_LEN 4
165 #define M_LSO_IPHDR_LEN 0xFFF
166 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)
167 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN)
169 #define S_LSO_ETHHDR_LEN 16
170 #define M_LSO_ETHHDR_LEN 0xF
171 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)
172 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN)
174 #define S_LSO_IPV6 20
175 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
176 #define F_LSO_IPV6 V_LSO_IPV6(1U)
178 #define S_LSO_LAST_SLICE 22
179 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)
180 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U)
182 #define S_LSO_FIRST_SLICE 23
183 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
184 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
186 #define S_LSO_OPCODE 24
187 #define M_LSO_OPCODE 0xFF
188 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
189 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
191 #define S_LSO_T5_XFER_SIZE 0
192 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF
193 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE)
194 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE)
199 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
220 /* rx_pkt.l2info fields */
222 #define V_RXF_UDP(x) ((x) << S_RXF_UDP)
223 #define F_RXF_UDP V_RXF_UDP(1U)
226 #define V_RXF_TCP(x) ((x) << S_RXF_TCP)
227 #define F_RXF_TCP V_RXF_TCP(1U)
230 #define V_RXF_IP(x) ((x) << S_RXF_IP)
231 #define F_RXF_IP V_RXF_IP(1U)
234 #define V_RXF_IP6(x) ((x) << S_RXF_IP6)
235 #define F_RXF_IP6 V_RXF_IP6(1U)
237 /* rx_pkt.err_vec fields */
238 /* In T6, rx_pkt.err_vec indicates
239 * RxError Error vector (16b) or
240 * Encapsulating header length (8b),
241 * Outer encapsulation type (2b) and
242 * compressed error vector (6b) if CRxPktEnc is
243 * enabled in TP_OUT_CONFIG
245 #define S_T6_COMPR_RXERR_VEC 0
246 #define M_T6_COMPR_RXERR_VEC 0x3F
247 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC)
248 #define G_T6_COMPR_RXERR_VEC(x) \
249 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC)
251 /* cpl_fw*.type values */
275 ULP_TX_SC_IMM = 0x81,
276 ULP_TX_SC_DSGL = 0x82,
277 ULP_TX_SC_ISGL = 0x83
280 #define S_ULPTX_CMD 24
281 #define M_ULPTX_CMD 0xFF
282 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
284 #define S_ULP_TX_SC_MORE 23
285 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)
286 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U)
288 struct ulptx_sge_pair {
298 #if !(defined C99_NOT_SUPPORTED)
299 struct ulptx_sge_pair sge[0];
309 #define S_ULPTX_NSGE 0
310 #define M_ULPTX_NSGE 0xFFFF
311 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
318 /* ulp_txpkt.cmd_dest fields */
319 #define S_ULP_TXPKT_DEST 16
320 #define M_ULP_TXPKT_DEST 0x3
321 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
323 #define S_ULP_TXPKT_FID 4
324 #define M_ULP_TXPKT_FID 0x7ff
325 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
327 #define S_ULP_TXPKT_RO 3
328 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
329 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
331 #endif /* T4_MSG_H */