1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_ethdev_pci.h>
33 #include <rte_malloc.h>
34 #include <rte_random.h>
38 #include "cxgbe_pfvf.h"
39 #include "cxgbe_flow.h"
44 * Macros needed to support the PCI Device ID Table ...
46 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
47 static const struct rte_pci_id cxgb4_pci_tbl[] = {
48 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
50 #define PCI_VENDOR_ID_CHELSIO 0x1425
52 #define CH_PCI_ID_TABLE_ENTRY(devid) \
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
55 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
60 *... and the PCI ID Table itself ...
62 #include "base/t4_pci_id_tbl.h"
64 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
67 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
68 uint16_t pkts_sent, pkts_remain;
69 uint16_t total_sent = 0;
73 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
74 __func__, txq, tx_pkts, nb_pkts);
76 t4_os_lock(&txq->txq_lock);
77 /* free up desc from already completed tx */
78 reclaim_completed_tx(&txq->q);
79 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *));
80 while (total_sent < nb_pkts) {
81 pkts_remain = nb_pkts - total_sent;
83 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
84 idx = total_sent + pkts_sent;
85 if ((idx + 1) < nb_pkts)
86 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1],
88 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts);
94 total_sent += pkts_sent;
95 /* reclaim as much as possible */
96 reclaim_completed_tx(&txq->q);
99 t4_os_unlock(&txq->txq_lock);
103 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
106 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
107 unsigned int work_done;
109 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
110 __func__, rxq->rspq.cntxt_id, nb_pkts);
112 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
113 dev_err(adapter, "error in cxgbe poll\n");
115 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
119 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
120 struct rte_eth_dev_info *device_info)
122 struct port_info *pi = eth_dev->data->dev_private;
123 struct adapter *adapter = pi->adapter;
124 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
126 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
127 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
128 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
132 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
133 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
134 device_info->max_rx_queues = max_queues;
135 device_info->max_tx_queues = max_queues;
136 device_info->max_mac_addrs = 1;
137 /* XXX: For now we support one MAC/port */
138 device_info->max_vfs = adapter->params.arch.vfcount;
139 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
141 device_info->rx_queue_offload_capa = 0UL;
142 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
144 device_info->tx_queue_offload_capa = 0UL;
145 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
147 device_info->reta_size = pi->rss_size;
148 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
149 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
151 device_info->rx_desc_lim = cxgbe_desc_lim;
152 device_info->tx_desc_lim = cxgbe_desc_lim;
153 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
158 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
160 struct port_info *pi = eth_dev->data->dev_private;
161 struct adapter *adapter = pi->adapter;
163 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
164 1, -1, 1, -1, false);
167 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
169 struct port_info *pi = eth_dev->data->dev_private;
170 struct adapter *adapter = pi->adapter;
172 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
173 0, -1, 1, -1, false);
176 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
178 struct port_info *pi = eth_dev->data->dev_private;
179 struct adapter *adapter = pi->adapter;
181 /* TODO: address filters ?? */
183 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
184 -1, 1, 1, -1, false);
187 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
189 struct port_info *pi = eth_dev->data->dev_private;
190 struct adapter *adapter = pi->adapter;
192 /* TODO: address filters ?? */
194 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
195 -1, 0, 1, -1, false);
198 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
199 int wait_to_complete)
201 struct port_info *pi = eth_dev->data->dev_private;
202 struct adapter *adapter = pi->adapter;
203 struct sge *s = &adapter->sge;
204 struct rte_eth_link new_link = { 0 };
205 unsigned int i, work_done, budget = 32;
206 u8 old_link = pi->link_cfg.link_ok;
208 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
209 if (!s->fw_evtq.desc)
212 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
214 /* Exit if link status changed or always forced up */
215 if (pi->link_cfg.link_ok != old_link ||
216 cxgbe_force_linkup(adapter))
219 if (!wait_to_complete)
222 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
225 new_link.link_status = cxgbe_force_linkup(adapter) ?
226 ETH_LINK_UP : pi->link_cfg.link_ok;
227 new_link.link_autoneg = pi->link_cfg.autoneg;
228 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
229 new_link.link_speed = pi->link_cfg.speed;
231 return rte_eth_linkstatus_set(eth_dev, &new_link);
235 * Set device link up.
237 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
239 struct port_info *pi = dev->data->dev_private;
240 struct adapter *adapter = pi->adapter;
241 unsigned int work_done, budget = 32;
242 struct sge *s = &adapter->sge;
245 if (!s->fw_evtq.desc)
248 /* Flush all link events */
249 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
251 /* If link already up, nothing to do */
252 if (pi->link_cfg.link_ok)
255 ret = cxgbe_set_link_status(pi, true);
259 cxgbe_dev_link_update(dev, 1);
264 * Set device link down.
266 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
268 struct port_info *pi = dev->data->dev_private;
269 struct adapter *adapter = pi->adapter;
270 unsigned int work_done, budget = 32;
271 struct sge *s = &adapter->sge;
274 if (!s->fw_evtq.desc)
277 /* Flush all link events */
278 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
280 /* If link already down, nothing to do */
281 if (!pi->link_cfg.link_ok)
284 ret = cxgbe_set_link_status(pi, false);
288 cxgbe_dev_link_update(dev, 0);
292 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
294 struct port_info *pi = eth_dev->data->dev_private;
295 struct adapter *adapter = pi->adapter;
296 struct rte_eth_dev_info dev_info;
298 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
300 err = cxgbe_dev_info_get(eth_dev, &dev_info);
304 /* Must accommodate at least RTE_ETHER_MIN_MTU */
305 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen)
308 /* set to jumbo mode if needed */
309 if (new_mtu > RTE_ETHER_MAX_LEN)
310 eth_dev->data->dev_conf.rxmode.offloads |=
311 DEV_RX_OFFLOAD_JUMBO_FRAME;
313 eth_dev->data->dev_conf.rxmode.offloads &=
314 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
316 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
319 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
327 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
329 struct port_info *pi = eth_dev->data->dev_private;
330 struct adapter *adapter = pi->adapter;
334 if (!(adapter->flags & FULL_INIT_DONE))
340 * We clear queues only if both tx and rx path of the port
343 t4_sge_eth_clear_queues(pi);
347 * It returns 0 on success.
349 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
351 struct port_info *pi = eth_dev->data->dev_private;
352 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode;
353 struct adapter *adapter = pi->adapter;
359 * If we don't have a connection to the firmware there's nothing we
362 if (!(adapter->flags & FW_OK)) {
367 if (!(adapter->flags & FULL_INIT_DONE)) {
368 err = cxgbe_up(adapter);
373 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
374 eth_dev->data->scattered_rx = 1;
376 eth_dev->data->scattered_rx = 0;
378 cxgbe_enable_rx_queues(pi);
380 err = cxgbe_setup_rss(pi);
384 for (i = 0; i < pi->n_tx_qsets; i++) {
385 err = cxgbe_dev_tx_queue_start(eth_dev, i);
390 for (i = 0; i < pi->n_rx_qsets; i++) {
391 err = cxgbe_dev_rx_queue_start(eth_dev, i);
396 err = cxgbe_link_start(pi);
405 * Stop device: disable rx and tx functions to allow for reconfiguring.
407 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
409 struct port_info *pi = eth_dev->data->dev_private;
410 struct adapter *adapter = pi->adapter;
414 if (!(adapter->flags & FULL_INIT_DONE))
420 * We clear queues only if both tx and rx path of the port
423 t4_sge_eth_clear_queues(pi);
424 eth_dev->data->scattered_rx = 0;
427 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
429 struct port_info *pi = eth_dev->data->dev_private;
430 struct adapter *adapter = pi->adapter;
435 if (!(adapter->flags & FW_QUEUE_BOUND)) {
436 err = cxgbe_setup_sge_fwevtq(adapter);
439 adapter->flags |= FW_QUEUE_BOUND;
440 if (is_pf4(adapter)) {
441 err = cxgbe_setup_sge_ctrl_txq(adapter);
447 err = cxgbe_cfg_queue_count(eth_dev);
454 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
457 struct sge_eth_txq *txq = (struct sge_eth_txq *)
458 (eth_dev->data->tx_queues[tx_queue_id]);
460 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
462 ret = t4_sge_eth_txq_start(txq);
464 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
469 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
472 struct sge_eth_txq *txq = (struct sge_eth_txq *)
473 (eth_dev->data->tx_queues[tx_queue_id]);
475 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
477 ret = t4_sge_eth_txq_stop(txq);
479 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
484 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
485 uint16_t queue_idx, uint16_t nb_desc,
486 unsigned int socket_id,
487 const struct rte_eth_txconf *tx_conf __rte_unused)
489 struct port_info *pi = eth_dev->data->dev_private;
490 struct adapter *adapter = pi->adapter;
491 struct sge *s = &adapter->sge;
492 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
494 unsigned int temp_nb_desc;
496 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
497 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
498 socket_id, pi->first_qset);
500 /* Free up the existing queue */
501 if (eth_dev->data->tx_queues[queue_idx]) {
502 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
503 eth_dev->data->tx_queues[queue_idx] = NULL;
506 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
510 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
512 temp_nb_desc = nb_desc;
513 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
514 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
515 __func__, CXGBE_MIN_RING_DESC_SIZE,
516 CXGBE_DEFAULT_TX_DESC_SIZE);
517 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
518 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
519 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
520 __func__, CXGBE_MIN_RING_DESC_SIZE,
521 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
525 txq->q.size = temp_nb_desc;
527 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
528 s->fw_evtq.cntxt_id, socket_id);
530 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
531 __func__, txq->q.cntxt_id, txq->q.abs_id, err);
535 void cxgbe_dev_tx_queue_release(void *q)
537 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
540 struct port_info *pi = (struct port_info *)
541 (txq->eth_dev->data->dev_private);
542 struct adapter *adap = pi->adapter;
544 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
545 __func__, pi->port_id, txq->q.cntxt_id);
547 t4_sge_eth_txq_release(adap, txq);
551 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
554 struct port_info *pi = eth_dev->data->dev_private;
555 struct adapter *adap = pi->adapter;
558 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
559 __func__, pi->port_id, rx_queue_id);
561 q = eth_dev->data->rx_queues[rx_queue_id];
563 ret = t4_sge_eth_rxq_start(adap, q);
565 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
570 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
573 struct port_info *pi = eth_dev->data->dev_private;
574 struct adapter *adap = pi->adapter;
577 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
578 __func__, pi->port_id, rx_queue_id);
580 q = eth_dev->data->rx_queues[rx_queue_id];
581 ret = t4_sge_eth_rxq_stop(adap, q);
583 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
588 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
589 uint16_t queue_idx, uint16_t nb_desc,
590 unsigned int socket_id,
591 const struct rte_eth_rxconf *rx_conf __rte_unused,
592 struct rte_mempool *mp)
594 struct port_info *pi = eth_dev->data->dev_private;
595 struct adapter *adapter = pi->adapter;
596 struct sge *s = &adapter->sge;
597 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
600 unsigned int temp_nb_desc;
601 struct rte_eth_dev_info dev_info;
602 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
604 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
605 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
608 err = cxgbe_dev_info_get(eth_dev, &dev_info);
610 dev_err(adap, "%s: error during getting ethernet device info",
615 /* Must accommodate at least RTE_ETHER_MIN_MTU */
616 if ((pkt_len < dev_info.min_rx_bufsize) ||
617 (pkt_len > dev_info.max_rx_pktlen)) {
618 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
619 __func__, dev_info.min_rx_bufsize,
620 dev_info.max_rx_pktlen);
624 /* Free up the existing queue */
625 if (eth_dev->data->rx_queues[queue_idx]) {
626 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
627 eth_dev->data->rx_queues[queue_idx] = NULL;
630 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
634 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
636 temp_nb_desc = nb_desc;
637 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
638 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
639 __func__, CXGBE_MIN_RING_DESC_SIZE,
640 CXGBE_DEFAULT_RX_DESC_SIZE);
641 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
642 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
643 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
644 __func__, CXGBE_MIN_RING_DESC_SIZE,
645 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
649 rxq->rspq.size = temp_nb_desc;
650 if ((&rxq->fl) != NULL)
651 rxq->fl.size = temp_nb_desc;
653 /* Set to jumbo mode if necessary */
654 if (pkt_len > RTE_ETHER_MAX_LEN)
655 eth_dev->data->dev_conf.rxmode.offloads |=
656 DEV_RX_OFFLOAD_JUMBO_FRAME;
658 eth_dev->data->dev_conf.rxmode.offloads &=
659 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
661 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
664 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
665 queue_idx, socket_id);
667 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
668 __func__, err, pi->port_id, rxq->rspq.cntxt_id,
673 void cxgbe_dev_rx_queue_release(void *q)
675 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
676 struct sge_rspq *rq = &rxq->rspq;
679 struct port_info *pi = (struct port_info *)
680 (rq->eth_dev->data->dev_private);
681 struct adapter *adap = pi->adapter;
683 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
684 __func__, pi->port_id, rxq->rspq.cntxt_id);
686 t4_sge_eth_rxq_release(adap, rxq);
691 * Get port statistics.
693 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
694 struct rte_eth_stats *eth_stats)
696 struct port_info *pi = eth_dev->data->dev_private;
697 struct adapter *adapter = pi->adapter;
698 struct sge *s = &adapter->sge;
699 struct port_stats ps;
702 cxgbe_stats_get(pi, &ps);
705 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
706 ps.rx_ovflow2 + ps.rx_ovflow3 +
707 ps.rx_trunc0 + ps.rx_trunc1 +
708 ps.rx_trunc2 + ps.rx_trunc3;
709 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
710 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
714 eth_stats->opackets = ps.tx_frames;
715 eth_stats->obytes = ps.tx_octets;
716 eth_stats->oerrors = ps.tx_error_frames;
718 for (i = 0; i < pi->n_rx_qsets; i++) {
719 struct sge_eth_rxq *rxq =
720 &s->ethrxq[pi->first_qset + i];
722 eth_stats->q_ipackets[i] = rxq->stats.pkts;
723 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
724 eth_stats->ipackets += eth_stats->q_ipackets[i];
725 eth_stats->ibytes += eth_stats->q_ibytes[i];
728 for (i = 0; i < pi->n_tx_qsets; i++) {
729 struct sge_eth_txq *txq =
730 &s->ethtxq[pi->first_qset + i];
732 eth_stats->q_opackets[i] = txq->stats.pkts;
733 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
739 * Reset port statistics.
741 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
743 struct port_info *pi = eth_dev->data->dev_private;
744 struct adapter *adapter = pi->adapter;
745 struct sge *s = &adapter->sge;
748 cxgbe_stats_reset(pi);
749 for (i = 0; i < pi->n_rx_qsets; i++) {
750 struct sge_eth_rxq *rxq =
751 &s->ethrxq[pi->first_qset + i];
754 rxq->stats.rx_bytes = 0;
756 for (i = 0; i < pi->n_tx_qsets; i++) {
757 struct sge_eth_txq *txq =
758 &s->ethtxq[pi->first_qset + i];
761 txq->stats.tx_bytes = 0;
762 txq->stats.mapping_err = 0;
768 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
769 struct rte_eth_fc_conf *fc_conf)
771 struct port_info *pi = eth_dev->data->dev_private;
772 struct link_config *lc = &pi->link_cfg;
773 int rx_pause, tx_pause;
775 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
776 rx_pause = lc->fc & PAUSE_RX;
777 tx_pause = lc->fc & PAUSE_TX;
779 if (rx_pause && tx_pause)
780 fc_conf->mode = RTE_FC_FULL;
782 fc_conf->mode = RTE_FC_RX_PAUSE;
784 fc_conf->mode = RTE_FC_TX_PAUSE;
786 fc_conf->mode = RTE_FC_NONE;
790 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
791 struct rte_eth_fc_conf *fc_conf)
793 struct port_info *pi = eth_dev->data->dev_private;
794 struct adapter *adapter = pi->adapter;
795 struct link_config *lc = &pi->link_cfg;
797 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
798 if (fc_conf->autoneg)
799 lc->requested_fc |= PAUSE_AUTONEG;
801 lc->requested_fc &= ~PAUSE_AUTONEG;
804 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
805 (fc_conf->mode & RTE_FC_RX_PAUSE))
806 lc->requested_fc |= PAUSE_RX;
808 lc->requested_fc &= ~PAUSE_RX;
810 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
811 (fc_conf->mode & RTE_FC_TX_PAUSE))
812 lc->requested_fc |= PAUSE_TX;
814 lc->requested_fc &= ~PAUSE_TX;
816 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
821 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
823 static const uint32_t ptypes[] = {
829 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
834 /* Update RSS hash configuration
836 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
837 struct rte_eth_rss_conf *rss_conf)
839 struct port_info *pi = dev->data->dev_private;
840 struct adapter *adapter = pi->adapter;
843 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
847 pi->rss_hf = rss_conf->rss_hf;
849 if (rss_conf->rss_key) {
850 u32 key[10], mod_key[10];
853 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
855 for (i = 9, j = 0; i >= 0; i--, j++)
856 mod_key[j] = cpu_to_be32(key[i]);
858 t4_write_rss_key(adapter, mod_key, -1);
864 /* Get RSS hash configuration
866 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
867 struct rte_eth_rss_conf *rss_conf)
869 struct port_info *pi = dev->data->dev_private;
870 struct adapter *adapter = pi->adapter;
875 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
881 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
882 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
883 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
884 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
887 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
888 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
890 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
891 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
892 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
893 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
896 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
897 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
899 rss_conf->rss_hf = rss_hf;
901 if (rss_conf->rss_key) {
902 u32 key[10], mod_key[10];
905 t4_read_rss_key(adapter, key);
907 for (i = 9, j = 0; i >= 0; i--, j++)
908 mod_key[j] = be32_to_cpu(key[i]);
910 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
916 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
923 * eeprom_ptov - translate a physical EEPROM address to virtual
924 * @phys_addr: the physical EEPROM address
925 * @fn: the PCI function number
926 * @sz: size of function-specific area
928 * Translate a physical EEPROM address to virtual. The first 1K is
929 * accessed through virtual addresses starting at 31K, the rest is
930 * accessed through virtual addresses starting at 0.
932 * The mapping is as follows:
933 * [0..1K) -> [31K..32K)
934 * [1K..1K+A) -> [31K-A..31K)
935 * [1K+A..ES) -> [0..ES-A-1K)
937 * where A = @fn * @sz, and ES = EEPROM size.
939 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
942 if (phys_addr < 1024)
943 return phys_addr + (31 << 10);
944 if (phys_addr < 1024 + fn)
945 return fn + phys_addr - 1024;
946 if (phys_addr < EEPROMSIZE)
947 return phys_addr - 1024 - fn;
948 if (phys_addr < EEPROMVSIZE)
949 return phys_addr - 1024;
953 /* The next two routines implement eeprom read/write from physical addresses.
955 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
957 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
960 vaddr = t4_seeprom_read(adap, vaddr, v);
961 return vaddr < 0 ? vaddr : 0;
964 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
966 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
969 vaddr = t4_seeprom_write(adap, vaddr, v);
970 return vaddr < 0 ? vaddr : 0;
973 #define EEPROM_MAGIC 0x38E2F10C
975 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
976 struct rte_dev_eeprom_info *e)
978 struct port_info *pi = dev->data->dev_private;
979 struct adapter *adapter = pi->adapter;
981 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
986 e->magic = EEPROM_MAGIC;
987 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
988 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
991 rte_memcpy(e->data, buf + e->offset, e->length);
996 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
997 struct rte_dev_eeprom_info *eeprom)
999 struct port_info *pi = dev->data->dev_private;
1000 struct adapter *adapter = pi->adapter;
1003 u32 aligned_offset, aligned_len, *p;
1005 if (eeprom->magic != EEPROM_MAGIC)
1008 aligned_offset = eeprom->offset & ~3;
1009 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
1011 if (adapter->pf > 0) {
1012 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1014 if (aligned_offset < start ||
1015 aligned_offset + aligned_len > start + EEPROMPFSIZE)
1019 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
1020 /* RMW possibly needed for first or last words.
1022 buf = rte_zmalloc(NULL, aligned_len, 0);
1025 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1026 if (!err && aligned_len > 4)
1027 err = eeprom_rd_phys(adapter,
1028 aligned_offset + aligned_len - 4,
1029 (u32 *)&buf[aligned_len - 4]);
1032 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1038 err = t4_seeprom_wp(adapter, false);
1042 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1043 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1044 aligned_offset += 4;
1048 err = t4_seeprom_wp(adapter, true);
1050 if (buf != eeprom->data)
1055 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1057 struct port_info *pi = eth_dev->data->dev_private;
1058 struct adapter *adapter = pi->adapter;
1060 return t4_get_regs_len(adapter) / sizeof(uint32_t);
1063 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1064 struct rte_dev_reg_info *regs)
1066 struct port_info *pi = eth_dev->data->dev_private;
1067 struct adapter *adapter = pi->adapter;
1069 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1070 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1073 if (regs->data == NULL) {
1074 regs->length = cxgbe_get_regs_len(eth_dev);
1075 regs->width = sizeof(uint32_t);
1080 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1085 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
1087 struct port_info *pi = dev->data->dev_private;
1090 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr);
1092 dev_err(adapter, "failed to set mac addr; err = %d\n",
1096 pi->xact_addr_filt = ret;
1100 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1101 .dev_start = cxgbe_dev_start,
1102 .dev_stop = cxgbe_dev_stop,
1103 .dev_close = cxgbe_dev_close,
1104 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
1105 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
1106 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
1107 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
1108 .dev_configure = cxgbe_dev_configure,
1109 .dev_infos_get = cxgbe_dev_info_get,
1110 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1111 .link_update = cxgbe_dev_link_update,
1112 .dev_set_link_up = cxgbe_dev_set_link_up,
1113 .dev_set_link_down = cxgbe_dev_set_link_down,
1114 .mtu_set = cxgbe_dev_mtu_set,
1115 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
1116 .tx_queue_start = cxgbe_dev_tx_queue_start,
1117 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
1118 .tx_queue_release = cxgbe_dev_tx_queue_release,
1119 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
1120 .rx_queue_start = cxgbe_dev_rx_queue_start,
1121 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
1122 .rx_queue_release = cxgbe_dev_rx_queue_release,
1123 .filter_ctrl = cxgbe_dev_filter_ctrl,
1124 .stats_get = cxgbe_dev_stats_get,
1125 .stats_reset = cxgbe_dev_stats_reset,
1126 .flow_ctrl_get = cxgbe_flow_ctrl_get,
1127 .flow_ctrl_set = cxgbe_flow_ctrl_set,
1128 .get_eeprom_length = cxgbe_get_eeprom_length,
1129 .get_eeprom = cxgbe_get_eeprom,
1130 .set_eeprom = cxgbe_set_eeprom,
1131 .get_reg = cxgbe_get_regs,
1132 .rss_hash_update = cxgbe_dev_rss_hash_update,
1133 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get,
1134 .mac_addr_set = cxgbe_mac_addr_set,
1139 * It returns 0 on success.
1141 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1143 struct rte_pci_device *pci_dev;
1144 struct port_info *pi = eth_dev->data->dev_private;
1145 struct adapter *adapter = NULL;
1146 char name[RTE_ETH_NAME_MAX_LEN];
1151 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1152 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1153 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1154 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1156 /* for secondary processes, we attach to ethdevs allocated by primary
1157 * and do minimal initialization.
1159 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1162 for (i = 1; i < MAX_NPORTS; i++) {
1163 struct rte_eth_dev *rest_eth_dev;
1164 char namei[RTE_ETH_NAME_MAX_LEN];
1166 snprintf(namei, sizeof(namei), "%s_%d",
1167 pci_dev->device.name, i);
1168 rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1170 rest_eth_dev->device = &pci_dev->device;
1171 rest_eth_dev->dev_ops =
1173 rest_eth_dev->rx_pkt_burst =
1174 eth_dev->rx_pkt_burst;
1175 rest_eth_dev->tx_pkt_burst =
1176 eth_dev->tx_pkt_burst;
1177 rte_eth_dev_probing_finish(rest_eth_dev);
1183 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1184 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1188 adapter->use_unpacked_mode = 1;
1189 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1190 if (!adapter->regs) {
1191 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1193 goto out_free_adapter;
1195 adapter->pdev = pci_dev;
1196 adapter->eth_dev = eth_dev;
1197 pi->adapter = adapter;
1199 err = cxgbe_probe(adapter);
1201 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1203 goto out_free_adapter;
1213 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1215 struct port_info *pi = eth_dev->data->dev_private;
1216 struct adapter *adap = pi->adapter;
1218 /* Free up other ports and all resources */
1223 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1224 struct rte_pci_device *pci_dev)
1226 return rte_eth_dev_pci_generic_probe(pci_dev,
1227 sizeof(struct port_info), eth_cxgbe_dev_init);
1230 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1232 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1235 static struct rte_pci_driver rte_cxgbe_pmd = {
1236 .id_table = cxgb4_pci_tbl,
1237 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1238 .probe = eth_cxgbe_pci_probe,
1239 .remove = eth_cxgbe_pci_remove,
1242 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1243 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1244 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1245 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1246 CXGBE_DEVARG_KEEP_OVLAN "=<0|1> "
1247 CXGBE_DEVARG_FORCE_LINK_UP "=<0|1> ");
1249 RTE_INIT(cxgbe_init_log)
1251 cxgbe_logtype = rte_log_register("pmd.net.cxgbe");
1252 if (cxgbe_logtype >= 0)
1253 rte_log_set_level(cxgbe_logtype, RTE_LOG_NOTICE);