1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_ethdev_pci.h>
33 #include <rte_malloc.h>
34 #include <rte_random.h>
38 #include "cxgbe_pfvf.h"
39 #include "cxgbe_flow.h"
42 * Macros needed to support the PCI Device ID Table ...
44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
45 static const struct rte_pci_id cxgb4_pci_tbl[] = {
46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
48 #define PCI_VENDOR_ID_CHELSIO 0x1425
50 #define CH_PCI_ID_TABLE_ENTRY(devid) \
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
58 *... and the PCI ID Table itself ...
60 #include "t4_pci_id_tbl.h"
62 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\
63 DEV_TX_OFFLOAD_IPV4_CKSUM |\
64 DEV_TX_OFFLOAD_UDP_CKSUM |\
65 DEV_TX_OFFLOAD_TCP_CKSUM |\
66 DEV_TX_OFFLOAD_TCP_TSO)
68 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\
69 DEV_RX_OFFLOAD_CRC_STRIP |\
70 DEV_RX_OFFLOAD_IPV4_CKSUM |\
71 DEV_RX_OFFLOAD_JUMBO_FRAME |\
72 DEV_RX_OFFLOAD_UDP_CKSUM |\
73 DEV_RX_OFFLOAD_TCP_CKSUM)
75 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
78 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
79 uint16_t pkts_sent, pkts_remain;
80 uint16_t total_sent = 0;
83 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
84 __func__, txq, tx_pkts, nb_pkts);
86 t4_os_lock(&txq->txq_lock);
87 /* free up desc from already completed tx */
88 reclaim_completed_tx(&txq->q);
89 while (total_sent < nb_pkts) {
90 pkts_remain = nb_pkts - total_sent;
92 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
93 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
100 total_sent += pkts_sent;
101 /* reclaim as much as possible */
102 reclaim_completed_tx(&txq->q);
105 t4_os_unlock(&txq->txq_lock);
109 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
112 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
113 unsigned int work_done;
115 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
116 __func__, rxq->rspq.cntxt_id, nb_pkts);
118 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
119 dev_err(adapter, "error in cxgbe poll\n");
121 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
125 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
126 struct rte_eth_dev_info *device_info)
128 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
129 struct adapter *adapter = pi->adapter;
130 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
132 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
133 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
134 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
138 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
139 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
140 device_info->max_rx_queues = max_queues;
141 device_info->max_tx_queues = max_queues;
142 device_info->max_mac_addrs = 1;
143 /* XXX: For now we support one MAC/port */
144 device_info->max_vfs = adapter->params.arch.vfcount;
145 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
147 device_info->rx_queue_offload_capa = 0UL;
148 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
150 device_info->tx_queue_offload_capa = 0UL;
151 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
153 device_info->reta_size = pi->rss_size;
154 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
155 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
157 device_info->rx_desc_lim = cxgbe_desc_lim;
158 device_info->tx_desc_lim = cxgbe_desc_lim;
159 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
162 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
164 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
165 struct adapter *adapter = pi->adapter;
167 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
168 1, -1, 1, -1, false);
171 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
173 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
174 struct adapter *adapter = pi->adapter;
176 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
177 0, -1, 1, -1, false);
180 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
182 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
183 struct adapter *adapter = pi->adapter;
185 /* TODO: address filters ?? */
187 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
188 -1, 1, 1, -1, false);
191 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
193 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
194 struct adapter *adapter = pi->adapter;
196 /* TODO: address filters ?? */
198 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
199 -1, 0, 1, -1, false);
202 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
203 __rte_unused int wait_to_complete)
205 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
206 struct adapter *adapter = pi->adapter;
207 struct sge *s = &adapter->sge;
208 struct rte_eth_link new_link = { 0 };
209 unsigned int work_done, budget = 4;
211 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
213 new_link.link_status = force_linkup(adapter) ?
214 ETH_LINK_UP : pi->link_cfg.link_ok;
215 new_link.link_autoneg = pi->link_cfg.autoneg;
216 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
217 new_link.link_speed = pi->link_cfg.speed;
219 return rte_eth_linkstatus_set(eth_dev, &new_link);
222 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
224 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
225 struct adapter *adapter = pi->adapter;
226 struct rte_eth_dev_info dev_info;
228 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
230 cxgbe_dev_info_get(eth_dev, &dev_info);
232 /* Must accommodate at least ETHER_MIN_MTU */
233 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
236 /* set to jumbo mode if needed */
237 if (new_mtu > ETHER_MAX_LEN)
238 eth_dev->data->dev_conf.rxmode.offloads |=
239 DEV_RX_OFFLOAD_JUMBO_FRAME;
241 eth_dev->data->dev_conf.rxmode.offloads &=
242 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
244 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
247 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
255 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
257 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
258 struct adapter *adapter = pi->adapter;
262 if (!(adapter->flags & FULL_INIT_DONE))
268 * We clear queues only if both tx and rx path of the port
271 t4_sge_eth_clear_queues(pi);
275 * It returns 0 on success.
277 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
279 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
280 struct adapter *adapter = pi->adapter;
286 * If we don't have a connection to the firmware there's nothing we
289 if (!(adapter->flags & FW_OK)) {
294 if (!(adapter->flags & FULL_INIT_DONE)) {
295 err = cxgbe_up(adapter);
300 cxgbe_enable_rx_queues(pi);
306 for (i = 0; i < pi->n_tx_qsets; i++) {
307 err = cxgbe_dev_tx_queue_start(eth_dev, i);
312 for (i = 0; i < pi->n_rx_qsets; i++) {
313 err = cxgbe_dev_rx_queue_start(eth_dev, i);
318 err = link_start(pi);
327 * Stop device: disable rx and tx functions to allow for reconfiguring.
329 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
331 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
332 struct adapter *adapter = pi->adapter;
336 if (!(adapter->flags & FULL_INIT_DONE))
342 * We clear queues only if both tx and rx path of the port
345 t4_sge_eth_clear_queues(pi);
348 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
350 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
351 struct adapter *adapter = pi->adapter;
352 uint64_t configured_offloads;
356 configured_offloads = eth_dev->data->dev_conf.rxmode.offloads;
358 /* KEEP_CRC offload flag is not supported by PMD
359 * can remove the below block when DEV_RX_OFFLOAD_CRC_STRIP removed
361 if (rte_eth_dev_must_keep_crc(configured_offloads)) {
362 dev_info(adapter, "can't disable hw crc strip\n");
363 eth_dev->data->dev_conf.rxmode.offloads |=
364 DEV_RX_OFFLOAD_CRC_STRIP;
367 if (!(adapter->flags & FW_QUEUE_BOUND)) {
368 err = setup_sge_fwevtq(adapter);
371 adapter->flags |= FW_QUEUE_BOUND;
372 err = setup_sge_ctrl_txq(adapter);
377 err = cfg_queue_count(eth_dev);
384 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
387 struct sge_eth_txq *txq = (struct sge_eth_txq *)
388 (eth_dev->data->tx_queues[tx_queue_id]);
390 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
392 ret = t4_sge_eth_txq_start(txq);
394 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
399 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
402 struct sge_eth_txq *txq = (struct sge_eth_txq *)
403 (eth_dev->data->tx_queues[tx_queue_id]);
405 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
407 ret = t4_sge_eth_txq_stop(txq);
409 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
414 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
415 uint16_t queue_idx, uint16_t nb_desc,
416 unsigned int socket_id,
417 const struct rte_eth_txconf *tx_conf __rte_unused)
419 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
420 struct adapter *adapter = pi->adapter;
421 struct sge *s = &adapter->sge;
422 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
424 unsigned int temp_nb_desc;
426 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
427 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
428 socket_id, pi->first_qset);
430 /* Free up the existing queue */
431 if (eth_dev->data->tx_queues[queue_idx]) {
432 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
433 eth_dev->data->tx_queues[queue_idx] = NULL;
436 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
440 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
442 temp_nb_desc = nb_desc;
443 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
444 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
445 __func__, CXGBE_MIN_RING_DESC_SIZE,
446 CXGBE_DEFAULT_TX_DESC_SIZE);
447 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
448 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
449 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
450 __func__, CXGBE_MIN_RING_DESC_SIZE,
451 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
455 txq->q.size = temp_nb_desc;
457 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
458 s->fw_evtq.cntxt_id, socket_id);
460 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
461 __func__, txq->q.cntxt_id, txq->q.abs_id, err);
465 void cxgbe_dev_tx_queue_release(void *q)
467 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
470 struct port_info *pi = (struct port_info *)
471 (txq->eth_dev->data->dev_private);
472 struct adapter *adap = pi->adapter;
474 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
475 __func__, pi->port_id, txq->q.cntxt_id);
477 t4_sge_eth_txq_release(adap, txq);
481 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
484 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
485 struct adapter *adap = pi->adapter;
488 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
489 __func__, pi->port_id, rx_queue_id);
491 q = eth_dev->data->rx_queues[rx_queue_id];
493 ret = t4_sge_eth_rxq_start(adap, q);
495 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
500 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
503 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
504 struct adapter *adap = pi->adapter;
507 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
508 __func__, pi->port_id, rx_queue_id);
510 q = eth_dev->data->rx_queues[rx_queue_id];
511 ret = t4_sge_eth_rxq_stop(adap, q);
513 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
518 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
519 uint16_t queue_idx, uint16_t nb_desc,
520 unsigned int socket_id,
521 const struct rte_eth_rxconf *rx_conf __rte_unused,
522 struct rte_mempool *mp)
524 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
525 struct adapter *adapter = pi->adapter;
526 struct sge *s = &adapter->sge;
527 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
530 unsigned int temp_nb_desc;
531 struct rte_eth_dev_info dev_info;
532 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
534 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
535 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
538 cxgbe_dev_info_get(eth_dev, &dev_info);
540 /* Must accommodate at least ETHER_MIN_MTU */
541 if ((pkt_len < dev_info.min_rx_bufsize) ||
542 (pkt_len > dev_info.max_rx_pktlen)) {
543 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
544 __func__, dev_info.min_rx_bufsize,
545 dev_info.max_rx_pktlen);
549 /* Free up the existing queue */
550 if (eth_dev->data->rx_queues[queue_idx]) {
551 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
552 eth_dev->data->rx_queues[queue_idx] = NULL;
555 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
559 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
561 temp_nb_desc = nb_desc;
562 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
563 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
564 __func__, CXGBE_MIN_RING_DESC_SIZE,
565 CXGBE_DEFAULT_RX_DESC_SIZE);
566 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
567 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
568 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
569 __func__, CXGBE_MIN_RING_DESC_SIZE,
570 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
574 rxq->rspq.size = temp_nb_desc;
575 if ((&rxq->fl) != NULL)
576 rxq->fl.size = temp_nb_desc;
578 /* Set to jumbo mode if necessary */
579 if (pkt_len > ETHER_MAX_LEN)
580 eth_dev->data->dev_conf.rxmode.offloads |=
581 DEV_RX_OFFLOAD_JUMBO_FRAME;
583 eth_dev->data->dev_conf.rxmode.offloads &=
584 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
586 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
587 &rxq->fl, t4_ethrx_handler,
589 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
590 queue_idx, socket_id);
592 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
593 __func__, err, pi->port_id, rxq->rspq.cntxt_id,
598 void cxgbe_dev_rx_queue_release(void *q)
600 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
601 struct sge_rspq *rq = &rxq->rspq;
604 struct port_info *pi = (struct port_info *)
605 (rq->eth_dev->data->dev_private);
606 struct adapter *adap = pi->adapter;
608 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
609 __func__, pi->port_id, rxq->rspq.cntxt_id);
611 t4_sge_eth_rxq_release(adap, rxq);
616 * Get port statistics.
618 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
619 struct rte_eth_stats *eth_stats)
621 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
622 struct adapter *adapter = pi->adapter;
623 struct sge *s = &adapter->sge;
624 struct port_stats ps;
627 cxgbe_stats_get(pi, &ps);
630 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
631 ps.rx_ovflow2 + ps.rx_ovflow3 +
632 ps.rx_trunc0 + ps.rx_trunc1 +
633 ps.rx_trunc2 + ps.rx_trunc3;
634 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
635 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
639 eth_stats->opackets = ps.tx_frames;
640 eth_stats->obytes = ps.tx_octets;
641 eth_stats->oerrors = ps.tx_error_frames;
643 for (i = 0; i < pi->n_rx_qsets; i++) {
644 struct sge_eth_rxq *rxq =
645 &s->ethrxq[pi->first_qset + i];
647 eth_stats->q_ipackets[i] = rxq->stats.pkts;
648 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
649 eth_stats->ipackets += eth_stats->q_ipackets[i];
650 eth_stats->ibytes += eth_stats->q_ibytes[i];
653 for (i = 0; i < pi->n_tx_qsets; i++) {
654 struct sge_eth_txq *txq =
655 &s->ethtxq[pi->first_qset + i];
657 eth_stats->q_opackets[i] = txq->stats.pkts;
658 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
659 eth_stats->q_errors[i] = txq->stats.mapping_err;
665 * Reset port statistics.
667 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
669 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
670 struct adapter *adapter = pi->adapter;
671 struct sge *s = &adapter->sge;
674 cxgbe_stats_reset(pi);
675 for (i = 0; i < pi->n_rx_qsets; i++) {
676 struct sge_eth_rxq *rxq =
677 &s->ethrxq[pi->first_qset + i];
680 rxq->stats.rx_bytes = 0;
682 for (i = 0; i < pi->n_tx_qsets; i++) {
683 struct sge_eth_txq *txq =
684 &s->ethtxq[pi->first_qset + i];
687 txq->stats.tx_bytes = 0;
688 txq->stats.mapping_err = 0;
692 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
693 struct rte_eth_fc_conf *fc_conf)
695 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
696 struct link_config *lc = &pi->link_cfg;
697 int rx_pause, tx_pause;
699 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
700 rx_pause = lc->fc & PAUSE_RX;
701 tx_pause = lc->fc & PAUSE_TX;
703 if (rx_pause && tx_pause)
704 fc_conf->mode = RTE_FC_FULL;
706 fc_conf->mode = RTE_FC_RX_PAUSE;
708 fc_conf->mode = RTE_FC_TX_PAUSE;
710 fc_conf->mode = RTE_FC_NONE;
714 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
715 struct rte_eth_fc_conf *fc_conf)
717 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
718 struct adapter *adapter = pi->adapter;
719 struct link_config *lc = &pi->link_cfg;
721 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
722 if (fc_conf->autoneg)
723 lc->requested_fc |= PAUSE_AUTONEG;
725 lc->requested_fc &= ~PAUSE_AUTONEG;
728 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
729 (fc_conf->mode & RTE_FC_RX_PAUSE))
730 lc->requested_fc |= PAUSE_RX;
732 lc->requested_fc &= ~PAUSE_RX;
734 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
735 (fc_conf->mode & RTE_FC_TX_PAUSE))
736 lc->requested_fc |= PAUSE_TX;
738 lc->requested_fc &= ~PAUSE_TX;
740 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
745 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
747 static const uint32_t ptypes[] = {
753 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
758 /* Update RSS hash configuration
760 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
761 struct rte_eth_rss_conf *rss_conf)
763 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
764 struct adapter *adapter = pi->adapter;
767 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
771 pi->rss_hf = rss_conf->rss_hf;
773 if (rss_conf->rss_key) {
774 u32 key[10], mod_key[10];
777 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
779 for (i = 9, j = 0; i >= 0; i--, j++)
780 mod_key[j] = cpu_to_be32(key[i]);
782 t4_write_rss_key(adapter, mod_key, -1);
788 /* Get RSS hash configuration
790 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
791 struct rte_eth_rss_conf *rss_conf)
793 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
794 struct adapter *adapter = pi->adapter;
799 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
805 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
806 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
807 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
808 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
811 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
812 rss_hf |= ETH_RSS_IPV6;
814 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
815 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
816 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
817 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
820 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
821 rss_hf |= ETH_RSS_IPV4;
823 rss_conf->rss_hf = rss_hf;
825 if (rss_conf->rss_key) {
826 u32 key[10], mod_key[10];
829 t4_read_rss_key(adapter, key);
831 for (i = 9, j = 0; i >= 0; i--, j++)
832 mod_key[j] = be32_to_cpu(key[i]);
834 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
840 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
847 * eeprom_ptov - translate a physical EEPROM address to virtual
848 * @phys_addr: the physical EEPROM address
849 * @fn: the PCI function number
850 * @sz: size of function-specific area
852 * Translate a physical EEPROM address to virtual. The first 1K is
853 * accessed through virtual addresses starting at 31K, the rest is
854 * accessed through virtual addresses starting at 0.
856 * The mapping is as follows:
857 * [0..1K) -> [31K..32K)
858 * [1K..1K+A) -> [31K-A..31K)
859 * [1K+A..ES) -> [0..ES-A-1K)
861 * where A = @fn * @sz, and ES = EEPROM size.
863 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
866 if (phys_addr < 1024)
867 return phys_addr + (31 << 10);
868 if (phys_addr < 1024 + fn)
869 return fn + phys_addr - 1024;
870 if (phys_addr < EEPROMSIZE)
871 return phys_addr - 1024 - fn;
872 if (phys_addr < EEPROMVSIZE)
873 return phys_addr - 1024;
877 /* The next two routines implement eeprom read/write from physical addresses.
879 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
881 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
884 vaddr = t4_seeprom_read(adap, vaddr, v);
885 return vaddr < 0 ? vaddr : 0;
888 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
890 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
893 vaddr = t4_seeprom_write(adap, vaddr, v);
894 return vaddr < 0 ? vaddr : 0;
897 #define EEPROM_MAGIC 0x38E2F10C
899 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
900 struct rte_dev_eeprom_info *e)
902 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
903 struct adapter *adapter = pi->adapter;
905 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
910 e->magic = EEPROM_MAGIC;
911 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
912 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
915 rte_memcpy(e->data, buf + e->offset, e->length);
920 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
921 struct rte_dev_eeprom_info *eeprom)
923 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
924 struct adapter *adapter = pi->adapter;
927 u32 aligned_offset, aligned_len, *p;
929 if (eeprom->magic != EEPROM_MAGIC)
932 aligned_offset = eeprom->offset & ~3;
933 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
935 if (adapter->pf > 0) {
936 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
938 if (aligned_offset < start ||
939 aligned_offset + aligned_len > start + EEPROMPFSIZE)
943 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
944 /* RMW possibly needed for first or last words.
946 buf = rte_zmalloc(NULL, aligned_len, 0);
949 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
950 if (!err && aligned_len > 4)
951 err = eeprom_rd_phys(adapter,
952 aligned_offset + aligned_len - 4,
953 (u32 *)&buf[aligned_len - 4]);
956 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
962 err = t4_seeprom_wp(adapter, false);
966 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
967 err = eeprom_wr_phys(adapter, aligned_offset, *p);
972 err = t4_seeprom_wp(adapter, true);
974 if (buf != eeprom->data)
979 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
981 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
982 struct adapter *adapter = pi->adapter;
984 return t4_get_regs_len(adapter) / sizeof(uint32_t);
987 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
988 struct rte_dev_reg_info *regs)
990 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
991 struct adapter *adapter = pi->adapter;
993 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
994 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
997 if (regs->data == NULL) {
998 regs->length = cxgbe_get_regs_len(eth_dev);
999 regs->width = sizeof(uint32_t);
1004 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1009 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1011 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1012 struct adapter *adapter = pi->adapter;
1015 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1016 pi->xact_addr_filt, (u8 *)addr, true, true);
1018 dev_err(adapter, "failed to set mac addr; err = %d\n",
1022 pi->xact_addr_filt = ret;
1026 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1027 .dev_start = cxgbe_dev_start,
1028 .dev_stop = cxgbe_dev_stop,
1029 .dev_close = cxgbe_dev_close,
1030 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
1031 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
1032 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
1033 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
1034 .dev_configure = cxgbe_dev_configure,
1035 .dev_infos_get = cxgbe_dev_info_get,
1036 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1037 .link_update = cxgbe_dev_link_update,
1038 .mtu_set = cxgbe_dev_mtu_set,
1039 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
1040 .tx_queue_start = cxgbe_dev_tx_queue_start,
1041 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
1042 .tx_queue_release = cxgbe_dev_tx_queue_release,
1043 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
1044 .rx_queue_start = cxgbe_dev_rx_queue_start,
1045 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
1046 .rx_queue_release = cxgbe_dev_rx_queue_release,
1047 .filter_ctrl = cxgbe_dev_filter_ctrl,
1048 .stats_get = cxgbe_dev_stats_get,
1049 .stats_reset = cxgbe_dev_stats_reset,
1050 .flow_ctrl_get = cxgbe_flow_ctrl_get,
1051 .flow_ctrl_set = cxgbe_flow_ctrl_set,
1052 .get_eeprom_length = cxgbe_get_eeprom_length,
1053 .get_eeprom = cxgbe_get_eeprom,
1054 .set_eeprom = cxgbe_set_eeprom,
1055 .get_reg = cxgbe_get_regs,
1056 .rss_hash_update = cxgbe_dev_rss_hash_update,
1057 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get,
1058 .mac_addr_set = cxgbe_mac_addr_set,
1063 * It returns 0 on success.
1065 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1067 struct rte_pci_device *pci_dev;
1068 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1069 struct adapter *adapter = NULL;
1070 char name[RTE_ETH_NAME_MAX_LEN];
1075 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1076 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1077 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1078 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1080 /* for secondary processes, we attach to ethdevs allocated by primary
1081 * and do minimal initialization.
1083 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1086 for (i = 1; i < MAX_NPORTS; i++) {
1087 struct rte_eth_dev *rest_eth_dev;
1088 char namei[RTE_ETH_NAME_MAX_LEN];
1090 snprintf(namei, sizeof(namei), "%s_%d",
1091 pci_dev->device.name, i);
1092 rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1094 rest_eth_dev->device = &pci_dev->device;
1095 rest_eth_dev->dev_ops =
1097 rest_eth_dev->rx_pkt_burst =
1098 eth_dev->rx_pkt_burst;
1099 rest_eth_dev->tx_pkt_burst =
1100 eth_dev->tx_pkt_burst;
1101 rte_eth_dev_probing_finish(rest_eth_dev);
1107 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1108 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1112 adapter->use_unpacked_mode = 1;
1113 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1114 if (!adapter->regs) {
1115 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1117 goto out_free_adapter;
1119 adapter->pdev = pci_dev;
1120 adapter->eth_dev = eth_dev;
1121 pi->adapter = adapter;
1123 err = cxgbe_probe(adapter);
1125 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1127 goto out_free_adapter;
1137 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1139 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1140 struct adapter *adap = pi->adapter;
1142 /* Free up other ports and all resources */
1147 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1148 struct rte_pci_device *pci_dev)
1150 return rte_eth_dev_pci_generic_probe(pci_dev,
1151 sizeof(struct port_info), eth_cxgbe_dev_init);
1154 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1156 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1159 static struct rte_pci_driver rte_cxgbe_pmd = {
1160 .id_table = cxgb4_pci_tbl,
1161 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1162 .probe = eth_cxgbe_pci_probe,
1163 .remove = eth_cxgbe_pci_remove,
1166 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1167 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1168 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1169 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1170 CXGBE_DEVARG_KEEP_OVLAN "=<0|1> "
1171 CXGBE_DEVARG_FORCE_LINK_UP "=<0|1> ");