1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2017-2020 NXP
15 #include <sys/types.h>
16 #include <sys/syscall.h>
18 #include <rte_string_fns.h>
19 #include <rte_byteorder.h>
20 #include <rte_common.h>
21 #include <rte_interrupts.h>
23 #include <rte_debug.h>
25 #include <rte_atomic.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_memory.h>
28 #include <rte_tailq.h>
30 #include <rte_alarm.h>
31 #include <rte_ether.h>
32 #include <rte_ethdev_driver.h>
33 #include <rte_malloc.h>
36 #include <rte_dpaa_bus.h>
37 #include <rte_dpaa_logs.h>
38 #include <dpaa_mempool.h>
40 #include <dpaa_ethdev.h>
41 #include <dpaa_rxtx.h>
42 #include <rte_pmd_dpaa.h>
50 /* Supported Rx offloads */
51 static uint64_t dev_rx_offloads_sup =
52 DEV_RX_OFFLOAD_JUMBO_FRAME |
53 DEV_RX_OFFLOAD_SCATTER;
55 /* Rx offloads which cannot be disabled */
56 static uint64_t dev_rx_offloads_nodis =
57 DEV_RX_OFFLOAD_IPV4_CKSUM |
58 DEV_RX_OFFLOAD_UDP_CKSUM |
59 DEV_RX_OFFLOAD_TCP_CKSUM |
60 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
61 DEV_RX_OFFLOAD_RSS_HASH;
63 /* Supported Tx offloads */
64 static uint64_t dev_tx_offloads_sup =
65 DEV_TX_OFFLOAD_MT_LOCKFREE |
66 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
68 /* Tx offloads which cannot be disabled */
69 static uint64_t dev_tx_offloads_nodis =
70 DEV_TX_OFFLOAD_IPV4_CKSUM |
71 DEV_TX_OFFLOAD_UDP_CKSUM |
72 DEV_TX_OFFLOAD_TCP_CKSUM |
73 DEV_TX_OFFLOAD_SCTP_CKSUM |
74 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
75 DEV_TX_OFFLOAD_MULTI_SEGS;
77 /* Keep track of whether QMAN and BMAN have been globally initialized */
78 static int is_global_init;
79 static int default_q; /* use default queue - FMC is not executed*/
80 /* At present we only allow up to 4 push mode queues as default - as each of
81 * this queue need dedicated portal and we are short of portals.
83 #define DPAA_MAX_PUSH_MODE_QUEUE 8
84 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
86 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
87 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
90 /* Per RX FQ Taildrop in frame count */
91 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
93 /* Per TX FQ Taildrop in frame count, disabled by default */
94 static unsigned int td_tx_threshold;
96 struct rte_dpaa_xstats_name_off {
97 char name[RTE_ETH_XSTATS_NAME_SIZE];
101 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
103 offsetof(struct dpaa_if_stats, raln)},
105 offsetof(struct dpaa_if_stats, rxpf)},
107 offsetof(struct dpaa_if_stats, rfcs)},
109 offsetof(struct dpaa_if_stats, rvlan)},
111 offsetof(struct dpaa_if_stats, rerr)},
113 offsetof(struct dpaa_if_stats, rdrp)},
115 offsetof(struct dpaa_if_stats, rund)},
117 offsetof(struct dpaa_if_stats, rovr)},
119 offsetof(struct dpaa_if_stats, rfrg)},
121 offsetof(struct dpaa_if_stats, txpf)},
123 offsetof(struct dpaa_if_stats, terr)},
125 offsetof(struct dpaa_if_stats, tvlan)},
127 offsetof(struct dpaa_if_stats, tund)},
130 static struct rte_dpaa_driver rte_dpaa_pmd;
133 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
135 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
136 int wait_to_complete __rte_unused);
138 static void dpaa_interrupt_handler(void *param);
141 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
143 memset(opts, 0, sizeof(struct qm_mcc_initfq));
144 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
145 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
146 QM_FQCTRL_PREFERINCACHE;
147 opts->fqd.context_a.stashing.exclusive = 0;
148 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
149 opts->fqd.context_a.stashing.annotation_cl =
150 DPAA_IF_RX_ANNOTATION_STASH;
151 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
152 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
156 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
158 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
160 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
162 PMD_INIT_FUNC_TRACE();
164 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
167 * Refuse mtu that requires the support of scattered packets
168 * when this feature has not been enabled before.
170 if (dev->data->min_rx_buf_size &&
171 !dev->data->scattered_rx && frame_size > buffsz) {
172 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
176 /* check <seg size> * <max_seg> >= max_frame */
177 if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
178 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
179 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
180 buffsz * DPAA_SGT_MAX_ENTRIES);
184 if (frame_size > RTE_ETHER_MAX_LEN)
185 dev->data->dev_conf.rxmode.offloads |=
186 DEV_RX_OFFLOAD_JUMBO_FRAME;
188 dev->data->dev_conf.rxmode.offloads &=
189 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
191 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
193 fman_if_set_maxfrm(dev->process_private, frame_size);
199 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
201 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
202 uint64_t rx_offloads = eth_conf->rxmode.offloads;
203 uint64_t tx_offloads = eth_conf->txmode.offloads;
204 struct rte_device *rdev = dev->device;
205 struct rte_dpaa_device *dpaa_dev;
206 struct fman_if *fif = dev->process_private;
207 struct __fman_if *__fif;
208 struct rte_intr_handle *intr_handle;
211 PMD_INIT_FUNC_TRACE();
213 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
214 intr_handle = &dpaa_dev->intr_handle;
215 __fif = container_of(fif, struct __fman_if, __if);
217 /* Rx offloads which are enabled by default */
218 if (dev_rx_offloads_nodis & ~rx_offloads) {
220 "Some of rx offloads enabled by default - requested 0x%" PRIx64
221 " fixed are 0x%" PRIx64,
222 rx_offloads, dev_rx_offloads_nodis);
225 /* Tx offloads which are enabled by default */
226 if (dev_tx_offloads_nodis & ~tx_offloads) {
228 "Some of tx offloads enabled by default - requested 0x%" PRIx64
229 " fixed are 0x%" PRIx64,
230 tx_offloads, dev_tx_offloads_nodis);
233 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
236 DPAA_PMD_DEBUG("enabling jumbo");
238 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
240 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
242 DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
244 dev->data->dev_conf.rxmode.max_rx_pkt_len,
245 DPAA_MAX_RX_PKT_LEN);
246 max_len = DPAA_MAX_RX_PKT_LEN;
249 fman_if_set_maxfrm(dev->process_private, max_len);
250 dev->data->mtu = max_len
251 - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
254 if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
255 DPAA_PMD_DEBUG("enabling scatter mode");
256 fman_if_set_sg(dev->process_private, 1);
257 dev->data->scattered_rx = 1;
260 /* if the interrupts were configured on this devices*/
261 if (intr_handle && intr_handle->fd) {
262 if (dev->data->dev_conf.intr_conf.lsc != 0)
263 rte_intr_callback_register(intr_handle,
264 dpaa_interrupt_handler,
267 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
269 if (dev->data->dev_conf.intr_conf.lsc != 0) {
270 rte_intr_callback_unregister(intr_handle,
271 dpaa_interrupt_handler,
274 printf("Failed to enable interrupt: Not Supported\n");
276 printf("Failed to enable interrupt\n");
278 dev->data->dev_conf.intr_conf.lsc = 0;
279 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
285 static const uint32_t *
286 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
288 static const uint32_t ptypes[] = {
290 RTE_PTYPE_L2_ETHER_VLAN,
291 RTE_PTYPE_L2_ETHER_ARP,
292 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
293 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
303 PMD_INIT_FUNC_TRACE();
305 if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
310 static void dpaa_interrupt_handler(void *param)
312 struct rte_eth_dev *dev = param;
313 struct rte_device *rdev = dev->device;
314 struct rte_dpaa_device *dpaa_dev;
315 struct rte_intr_handle *intr_handle;
319 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
320 intr_handle = &dpaa_dev->intr_handle;
322 bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
324 DPAA_PMD_ERR("Error reading eventfd\n");
325 dpaa_eth_link_update(dev, 0);
326 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
329 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
331 struct dpaa_if *dpaa_intf = dev->data->dev_private;
333 PMD_INIT_FUNC_TRACE();
335 /* Change tx callback to the real one */
336 if (dpaa_intf->cgr_tx)
337 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
339 dev->tx_pkt_burst = dpaa_eth_queue_tx;
341 fman_if_enable_rx(dev->process_private);
346 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
348 struct fman_if *fif = dev->process_private;
350 PMD_INIT_FUNC_TRACE();
352 fman_if_disable_rx(fif);
353 dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
356 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
358 struct fman_if *fif = dev->process_private;
359 struct __fman_if *__fif;
360 struct rte_device *rdev = dev->device;
361 struct rte_dpaa_device *dpaa_dev;
362 struct rte_intr_handle *intr_handle;
364 PMD_INIT_FUNC_TRACE();
366 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
367 intr_handle = &dpaa_dev->intr_handle;
368 __fif = container_of(fif, struct __fman_if, __if);
370 dpaa_eth_dev_stop(dev);
372 if (intr_handle && intr_handle->fd &&
373 dev->data->dev_conf.intr_conf.lsc != 0) {
374 dpaa_intr_disable(__fif->node_name);
375 rte_intr_callback_unregister(intr_handle,
376 dpaa_interrupt_handler,
382 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
387 FILE *svr_file = NULL;
388 unsigned int svr_ver = 0;
390 PMD_INIT_FUNC_TRACE();
392 svr_file = fopen(DPAA_SOC_ID_FILE, "r");
394 DPAA_PMD_ERR("Unable to open SoC device");
395 return -ENOTSUP; /* Not supported on this infra */
397 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
398 dpaa_svr_family = svr_ver & SVR_MASK;
400 DPAA_PMD_ERR("Unable to read SoC device");
404 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
405 svr_ver, fman_ip_rev);
406 ret += 1; /* add the size of '\0' */
408 if (fw_size < (uint32_t)ret)
414 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
415 struct rte_eth_dev_info *dev_info)
417 struct dpaa_if *dpaa_intf = dev->data->dev_private;
418 struct fman_if *fif = dev->process_private;
420 DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
422 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
423 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
424 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
425 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
426 dev_info->max_hash_mac_addrs = 0;
427 dev_info->max_vfs = 0;
428 dev_info->max_vmdq_pools = ETH_16_POOLS;
429 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
431 if (fif->mac_type == fman_mac_1g) {
432 dev_info->speed_capa = ETH_LINK_SPEED_1G;
433 } else if (fif->mac_type == fman_mac_2_5g) {
434 dev_info->speed_capa = ETH_LINK_SPEED_1G
435 | ETH_LINK_SPEED_2_5G;
436 } else if (fif->mac_type == fman_mac_10g) {
437 dev_info->speed_capa = ETH_LINK_SPEED_1G
438 | ETH_LINK_SPEED_2_5G
439 | ETH_LINK_SPEED_10G;
441 DPAA_PMD_ERR("invalid link_speed: %s, %d",
442 dpaa_intf->name, fif->mac_type);
446 dev_info->rx_offload_capa = dev_rx_offloads_sup |
447 dev_rx_offloads_nodis;
448 dev_info->tx_offload_capa = dev_tx_offloads_sup |
449 dev_tx_offloads_nodis;
450 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
451 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
452 dev_info->default_rxportconf.nb_queues = 1;
453 dev_info->default_txportconf.nb_queues = 1;
454 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
455 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
460 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
461 int wait_to_complete __rte_unused)
463 struct dpaa_if *dpaa_intf = dev->data->dev_private;
464 struct rte_eth_link *link = &dev->data->dev_link;
465 struct fman_if *fif = dev->process_private;
466 struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
469 PMD_INIT_FUNC_TRACE();
471 if (fif->mac_type == fman_mac_1g)
472 link->link_speed = ETH_SPEED_NUM_1G;
473 else if (fif->mac_type == fman_mac_2_5g)
474 link->link_speed = ETH_SPEED_NUM_2_5G;
475 else if (fif->mac_type == fman_mac_10g)
476 link->link_speed = ETH_SPEED_NUM_10G;
478 DPAA_PMD_ERR("invalid link_speed: %s, %d",
479 dpaa_intf->name, fif->mac_type);
481 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
482 ret = dpaa_get_link_status(__fif->node_name);
485 link->link_status = ret;
487 link->link_status = dpaa_intf->valid;
490 link->link_duplex = ETH_LINK_FULL_DUPLEX;
491 link->link_autoneg = ETH_LINK_AUTONEG;
493 DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
494 link->link_status ? "Up" : "Down");
498 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
499 struct rte_eth_stats *stats)
501 PMD_INIT_FUNC_TRACE();
503 fman_if_stats_get(dev->process_private, stats);
507 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
509 PMD_INIT_FUNC_TRACE();
511 fman_if_stats_reset(dev->process_private);
517 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
520 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
521 uint64_t values[sizeof(struct dpaa_if_stats) / 8];
529 fman_if_stats_get_all(dev->process_private, values,
530 sizeof(struct dpaa_if_stats) / 8);
532 for (i = 0; i < num; i++) {
534 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
540 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
541 struct rte_eth_xstat_name *xstats_names,
544 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
546 if (limit < stat_cnt)
549 if (xstats_names != NULL)
550 for (i = 0; i < stat_cnt; i++)
551 strlcpy(xstats_names[i].name,
552 dpaa_xstats_strings[i].name,
553 sizeof(xstats_names[i].name));
559 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
560 uint64_t *values, unsigned int n)
562 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
563 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
572 fman_if_stats_get_all(dev->process_private, values_copy,
573 sizeof(struct dpaa_if_stats) / 8);
575 for (i = 0; i < stat_cnt; i++)
577 values_copy[dpaa_xstats_strings[i].offset / 8];
582 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
584 for (i = 0; i < n; i++) {
585 if (ids[i] >= stat_cnt) {
586 DPAA_PMD_ERR("id value isn't valid");
589 values[i] = values_copy[ids[i]];
595 dpaa_xstats_get_names_by_id(
596 struct rte_eth_dev *dev,
597 struct rte_eth_xstat_name *xstats_names,
601 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
602 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
605 return dpaa_xstats_get_names(dev, xstats_names, limit);
607 dpaa_xstats_get_names(dev, xstats_names_copy, limit);
609 for (i = 0; i < limit; i++) {
610 if (ids[i] >= stat_cnt) {
611 DPAA_PMD_ERR("id value isn't valid");
614 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
619 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
621 PMD_INIT_FUNC_TRACE();
623 fman_if_promiscuous_enable(dev->process_private);
628 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
630 PMD_INIT_FUNC_TRACE();
632 fman_if_promiscuous_disable(dev->process_private);
637 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
639 PMD_INIT_FUNC_TRACE();
641 fman_if_set_mcast_filter_table(dev->process_private);
646 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
648 PMD_INIT_FUNC_TRACE();
650 fman_if_reset_mcast_filter_table(dev->process_private);
656 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
658 unsigned int socket_id __rte_unused,
659 const struct rte_eth_rxconf *rx_conf __rte_unused,
660 struct rte_mempool *mp)
662 struct dpaa_if *dpaa_intf = dev->data->dev_private;
663 struct fman_if *fif = dev->process_private;
664 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
665 struct qm_mcc_initfq opts = {0};
668 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
670 PMD_INIT_FUNC_TRACE();
672 if (queue_idx >= dev->data->nb_rx_queues) {
673 rte_errno = EOVERFLOW;
674 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
675 (void *)dev, queue_idx, dev->data->nb_rx_queues);
679 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
680 queue_idx, rxq->fqid);
682 /* Max packet can fit in single buffer */
683 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
685 } else if (dev->data->dev_conf.rxmode.offloads &
686 DEV_RX_OFFLOAD_SCATTER) {
687 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
688 buffsz * DPAA_SGT_MAX_ENTRIES) {
689 DPAA_PMD_ERR("max RxPkt size %d too big to fit "
691 dev->data->dev_conf.rxmode.max_rx_pkt_len,
692 buffsz * DPAA_SGT_MAX_ENTRIES);
693 rte_errno = EOVERFLOW;
697 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
698 " larger than a single mbuf (%u) and scattered"
699 " mode has not been requested",
700 dev->data->dev_conf.rxmode.max_rx_pkt_len,
701 buffsz - RTE_PKTMBUF_HEADROOM);
704 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
705 struct fman_if_ic_params icp;
709 if (!mp->pool_data) {
710 DPAA_PMD_ERR("Not an offloaded buffer pool!");
713 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
715 memset(&icp, 0, sizeof(icp));
716 /* set ICEOF for to the default value , which is 0*/
717 icp.iciof = DEFAULT_ICIOF;
718 icp.iceof = DEFAULT_RX_ICEOF;
719 icp.icsz = DEFAULT_ICSZ;
720 fman_if_set_ic_params(fif, &icp);
722 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
723 fman_if_set_fdoff(fif, fd_offset);
725 /* Buffer pool size should be equal to Dataroom Size*/
726 bp_size = rte_pktmbuf_data_room_size(mp);
727 fman_if_set_bp(fif, mp->size,
728 dpaa_intf->bp_info->bpid, bp_size);
729 dpaa_intf->valid = 1;
730 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d",
731 dpaa_intf->name, fd_offset,
732 fman_if_get_fdoff(fif));
734 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
735 fman_if_get_sg_enable(fif),
736 dev->data->dev_conf.rxmode.max_rx_pkt_len);
737 /* checking if push mode only, no error check for now */
738 if (!rxq->is_static &&
739 dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
740 struct qman_portal *qp;
743 dpaa_push_queue_idx++;
744 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
745 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
746 QM_FQCTRL_CTXASTASHING |
747 QM_FQCTRL_PREFERINCACHE;
748 opts.fqd.context_a.stashing.exclusive = 0;
749 /* In muticore scenario stashing becomes a bottleneck on LS1046.
750 * So do not enable stashing in this case
752 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
753 opts.fqd.context_a.stashing.annotation_cl =
754 DPAA_IF_RX_ANNOTATION_STASH;
755 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
756 opts.fqd.context_a.stashing.context_cl =
757 DPAA_IF_RX_CONTEXT_STASH;
759 /*Create a channel and associate given queue with the channel*/
760 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
761 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
762 opts.fqd.dest.channel = rxq->ch_id;
763 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
764 flags = QMAN_INITFQ_FLAG_SCHED;
766 /* Configure tail drop */
767 if (dpaa_intf->cgr_rx) {
768 opts.we_mask |= QM_INITFQ_WE_CGID;
769 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
770 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
772 ret = qman_init_fq(rxq, flags, &opts);
774 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
775 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
778 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
779 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
781 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
782 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
785 rxq->is_static = true;
787 /* Allocate qman specific portals */
788 qp = fsl_qman_fq_portal_create(&q_fd);
790 DPAA_PMD_ERR("Unable to alloc fq portal");
795 /* Set up the device interrupt handler */
796 if (!dev->intr_handle) {
797 struct rte_dpaa_device *dpaa_dev;
798 struct rte_device *rdev = dev->device;
800 dpaa_dev = container_of(rdev, struct rte_dpaa_device,
802 dev->intr_handle = &dpaa_dev->intr_handle;
803 dev->intr_handle->intr_vec = rte_zmalloc(NULL,
804 dpaa_push_mode_max_queue, 0);
805 if (!dev->intr_handle->intr_vec) {
806 DPAA_PMD_ERR("intr_vec alloc failed");
809 dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
810 dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
813 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
814 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
815 dev->intr_handle->efds[queue_idx] = q_fd;
818 rxq->bp_array = rte_dpaa_bpid_info;
819 dev->data->rx_queues[queue_idx] = rxq;
821 /* configure the CGR size as per the desc size */
822 if (dpaa_intf->cgr_rx) {
823 struct qm_mcc_initcgr cgr_opts = {0};
825 /* Enable tail drop with cgr on this queue */
826 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
827 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
830 "rx taildrop modify fail on fqid %d (ret=%d)",
839 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
842 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
846 struct dpaa_if *dpaa_intf = dev->data->dev_private;
847 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
848 struct qm_mcc_initfq opts = {0};
850 if (dpaa_push_mode_max_queue)
851 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
852 "PUSH mode already enabled for first %d queues.\n"
853 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
854 dpaa_push_mode_max_queue);
856 dpaa_poll_queue_default_config(&opts);
858 switch (queue_conf->ev.sched_type) {
859 case RTE_SCHED_TYPE_ATOMIC:
860 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
861 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
862 * configuration with HOLD_ACTIVE setting
864 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
865 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
867 case RTE_SCHED_TYPE_ORDERED:
868 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
871 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
872 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
876 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
877 opts.fqd.dest.channel = ch_id;
878 opts.fqd.dest.wq = queue_conf->ev.priority;
880 if (dpaa_intf->cgr_rx) {
881 opts.we_mask |= QM_INITFQ_WE_CGID;
882 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
883 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
886 flags = QMAN_INITFQ_FLAG_SCHED;
888 ret = qman_init_fq(rxq, flags, &opts);
890 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
891 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
895 /* copy configuration which needs to be filled during dequeue */
896 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
897 dev->data->rx_queues[eth_rx_queue_id] = rxq;
903 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
906 struct qm_mcc_initfq opts;
909 struct dpaa_if *dpaa_intf = dev->data->dev_private;
910 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
912 dpaa_poll_queue_default_config(&opts);
914 if (dpaa_intf->cgr_rx) {
915 opts.we_mask |= QM_INITFQ_WE_CGID;
916 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
917 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
920 ret = qman_init_fq(rxq, flags, &opts);
922 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
926 rxq->cb.dqrr_dpdk_cb = NULL;
927 dev->data->rx_queues[eth_rx_queue_id] = NULL;
933 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
935 PMD_INIT_FUNC_TRACE();
939 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
940 uint16_t nb_desc __rte_unused,
941 unsigned int socket_id __rte_unused,
942 const struct rte_eth_txconf *tx_conf __rte_unused)
944 struct dpaa_if *dpaa_intf = dev->data->dev_private;
946 PMD_INIT_FUNC_TRACE();
948 if (queue_idx >= dev->data->nb_tx_queues) {
949 rte_errno = EOVERFLOW;
950 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
951 (void *)dev, queue_idx, dev->data->nb_tx_queues);
955 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
956 queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
957 dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
962 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
964 PMD_INIT_FUNC_TRACE();
968 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
970 struct dpaa_if *dpaa_intf = dev->data->dev_private;
971 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
974 PMD_INIT_FUNC_TRACE();
976 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
977 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
978 rx_queue_id, frm_cnt);
983 static int dpaa_link_down(struct rte_eth_dev *dev)
985 struct fman_if *fif = dev->process_private;
986 struct __fman_if *__fif;
988 PMD_INIT_FUNC_TRACE();
990 __fif = container_of(fif, struct __fman_if, __if);
992 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
993 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN);
995 dpaa_eth_dev_stop(dev);
999 static int dpaa_link_up(struct rte_eth_dev *dev)
1001 struct fman_if *fif = dev->process_private;
1002 struct __fman_if *__fif;
1004 PMD_INIT_FUNC_TRACE();
1006 __fif = container_of(fif, struct __fman_if, __if);
1008 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1009 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP);
1011 dpaa_eth_dev_start(dev);
1016 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1017 struct rte_eth_fc_conf *fc_conf)
1019 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1020 struct rte_eth_fc_conf *net_fc;
1022 PMD_INIT_FUNC_TRACE();
1024 if (!(dpaa_intf->fc_conf)) {
1025 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1026 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1027 if (!dpaa_intf->fc_conf) {
1028 DPAA_PMD_ERR("unable to save flow control info");
1032 net_fc = dpaa_intf->fc_conf;
1034 if (fc_conf->high_water < fc_conf->low_water) {
1035 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1039 if (fc_conf->mode == RTE_FC_NONE) {
1041 } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
1042 fc_conf->mode == RTE_FC_FULL) {
1043 fman_if_set_fc_threshold(dev->process_private,
1044 fc_conf->high_water,
1046 dpaa_intf->bp_info->bpid);
1047 if (fc_conf->pause_time)
1048 fman_if_set_fc_quanta(dev->process_private,
1049 fc_conf->pause_time);
1052 /* Save the information in dpaa device */
1053 net_fc->pause_time = fc_conf->pause_time;
1054 net_fc->high_water = fc_conf->high_water;
1055 net_fc->low_water = fc_conf->low_water;
1056 net_fc->send_xon = fc_conf->send_xon;
1057 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1058 net_fc->mode = fc_conf->mode;
1059 net_fc->autoneg = fc_conf->autoneg;
1065 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1066 struct rte_eth_fc_conf *fc_conf)
1068 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1069 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1072 PMD_INIT_FUNC_TRACE();
1075 fc_conf->pause_time = net_fc->pause_time;
1076 fc_conf->high_water = net_fc->high_water;
1077 fc_conf->low_water = net_fc->low_water;
1078 fc_conf->send_xon = net_fc->send_xon;
1079 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1080 fc_conf->mode = net_fc->mode;
1081 fc_conf->autoneg = net_fc->autoneg;
1084 ret = fman_if_get_fc_threshold(dev->process_private);
1086 fc_conf->mode = RTE_FC_TX_PAUSE;
1087 fc_conf->pause_time =
1088 fman_if_get_fc_quanta(dev->process_private);
1090 fc_conf->mode = RTE_FC_NONE;
1097 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1098 struct rte_ether_addr *addr,
1100 __rte_unused uint32_t pool)
1104 PMD_INIT_FUNC_TRACE();
1106 ret = fman_if_add_mac_addr(dev->process_private,
1107 addr->addr_bytes, index);
1110 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1115 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1118 PMD_INIT_FUNC_TRACE();
1120 fman_if_clear_mac_addr(dev->process_private, index);
1124 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1125 struct rte_ether_addr *addr)
1129 PMD_INIT_FUNC_TRACE();
1131 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1133 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1138 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1141 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1142 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1144 if (!rxq->is_static)
1147 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1150 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1153 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1154 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1158 if (!rxq->is_static)
1161 qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1163 temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1164 if (temp1 != sizeof(temp))
1165 DPAA_PMD_ERR("irq read error");
1167 qman_fq_portal_thread_irq(rxq->qp);
1172 static struct eth_dev_ops dpaa_devops = {
1173 .dev_configure = dpaa_eth_dev_configure,
1174 .dev_start = dpaa_eth_dev_start,
1175 .dev_stop = dpaa_eth_dev_stop,
1176 .dev_close = dpaa_eth_dev_close,
1177 .dev_infos_get = dpaa_eth_dev_info,
1178 .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1180 .rx_queue_setup = dpaa_eth_rx_queue_setup,
1181 .tx_queue_setup = dpaa_eth_tx_queue_setup,
1182 .rx_queue_release = dpaa_eth_rx_queue_release,
1183 .tx_queue_release = dpaa_eth_tx_queue_release,
1184 .rx_queue_count = dpaa_dev_rx_queue_count,
1186 .flow_ctrl_get = dpaa_flow_ctrl_get,
1187 .flow_ctrl_set = dpaa_flow_ctrl_set,
1189 .link_update = dpaa_eth_link_update,
1190 .stats_get = dpaa_eth_stats_get,
1191 .xstats_get = dpaa_dev_xstats_get,
1192 .xstats_get_by_id = dpaa_xstats_get_by_id,
1193 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id,
1194 .xstats_get_names = dpaa_xstats_get_names,
1195 .xstats_reset = dpaa_eth_stats_reset,
1196 .stats_reset = dpaa_eth_stats_reset,
1197 .promiscuous_enable = dpaa_eth_promiscuous_enable,
1198 .promiscuous_disable = dpaa_eth_promiscuous_disable,
1199 .allmulticast_enable = dpaa_eth_multicast_enable,
1200 .allmulticast_disable = dpaa_eth_multicast_disable,
1201 .mtu_set = dpaa_mtu_set,
1202 .dev_set_link_down = dpaa_link_down,
1203 .dev_set_link_up = dpaa_link_up,
1204 .mac_addr_add = dpaa_dev_add_mac_addr,
1205 .mac_addr_remove = dpaa_dev_remove_mac_addr,
1206 .mac_addr_set = dpaa_dev_set_mac_addr,
1208 .fw_version_get = dpaa_fw_version_get,
1210 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable,
1211 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable,
1215 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1217 if (strcmp(dev->device->driver->name,
1225 is_dpaa_supported(struct rte_eth_dev *dev)
1227 return is_device_supported(dev, &rte_dpaa_pmd);
1231 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1233 struct rte_eth_dev *dev;
1235 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1237 dev = &rte_eth_devices[port];
1239 if (!is_dpaa_supported(dev))
1243 fman_if_loopback_enable(dev->process_private);
1245 fman_if_loopback_disable(dev->process_private);
1250 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1251 struct fman_if *fman_intf)
1253 struct rte_eth_fc_conf *fc_conf;
1256 PMD_INIT_FUNC_TRACE();
1258 if (!(dpaa_intf->fc_conf)) {
1259 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1260 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1261 if (!dpaa_intf->fc_conf) {
1262 DPAA_PMD_ERR("unable to save flow control info");
1266 fc_conf = dpaa_intf->fc_conf;
1267 ret = fman_if_get_fc_threshold(fman_intf);
1269 fc_conf->mode = RTE_FC_TX_PAUSE;
1270 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1272 fc_conf->mode = RTE_FC_NONE;
1278 /* Initialise an Rx FQ */
1279 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1282 struct qm_mcc_initfq opts = {0};
1284 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1285 struct qm_mcc_initcgr cgr_opts = {
1286 .we_mask = QM_CGR_WE_CS_THRES |
1290 .cstd_en = QM_CGR_EN,
1291 .mode = QMAN_CGR_MODE_FRAME
1296 ret = qman_reserve_fqid(fqid);
1298 DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1303 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1305 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1306 ret = qman_create_fq(fqid, flags, fq);
1308 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1312 fq->is_static = false;
1314 dpaa_poll_queue_default_config(&opts);
1317 /* Enable tail drop with cgr on this queue */
1318 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1320 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1324 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1328 opts.we_mask |= QM_INITFQ_WE_CGID;
1329 opts.fqd.cgid = cgr_rx->cgrid;
1330 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1333 ret = qman_init_fq(fq, 0, &opts);
1335 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1339 /* Initialise a Tx FQ */
1340 static int dpaa_tx_queue_init(struct qman_fq *fq,
1341 struct fman_if *fman_intf,
1342 struct qman_cgr *cgr_tx)
1344 struct qm_mcc_initfq opts = {0};
1345 struct qm_mcc_initcgr cgr_opts = {
1346 .we_mask = QM_CGR_WE_CS_THRES |
1350 .cstd_en = QM_CGR_EN,
1351 .mode = QMAN_CGR_MODE_FRAME
1356 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1357 QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1359 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1362 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1363 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1364 opts.fqd.dest.channel = fman_intf->tx_channel_id;
1365 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1366 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1367 opts.fqd.context_b = 0;
1368 /* no tx-confirmation */
1369 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1370 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1371 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1374 /* Enable tail drop with cgr on this queue */
1375 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1376 td_tx_threshold, 0);
1378 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1382 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1386 opts.we_mask |= QM_INITFQ_WE_CGID;
1387 opts.fqd.cgid = cgr_tx->cgrid;
1388 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1389 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1393 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1395 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1399 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1400 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1401 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1403 struct qm_mcc_initfq opts = {0};
1406 PMD_INIT_FUNC_TRACE();
1408 ret = qman_reserve_fqid(fqid);
1410 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1414 /* "map" this Rx FQ to one of the interfaces Tx FQID */
1415 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1416 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1418 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1422 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1423 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1424 ret = qman_init_fq(fq, 0, &opts);
1426 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1432 /* Initialise a network interface */
1434 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1436 struct rte_dpaa_device *dpaa_device;
1437 struct fm_eth_port_cfg *cfg;
1438 struct dpaa_if *dpaa_intf;
1439 struct fman_if *fman_intf;
1442 PMD_INIT_FUNC_TRACE();
1444 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1445 dev_id = dpaa_device->id.dev_id;
1446 cfg = dpaa_get_eth_port_cfg(dev_id);
1447 fman_intf = cfg->fman_if;
1448 eth_dev->process_private = fman_intf;
1450 /* Plugging of UCODE burst API not supported in Secondary */
1451 dpaa_intf = eth_dev->data->dev_private;
1452 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1453 if (dpaa_intf->cgr_tx)
1454 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1456 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1457 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1458 qman_set_fq_lookup_table(
1459 dpaa_intf->rx_queues->qman_fq_lookup_table);
1465 /* Initialise a network interface */
1467 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1469 int num_rx_fqs, fqid;
1472 struct rte_dpaa_device *dpaa_device;
1473 struct dpaa_if *dpaa_intf;
1474 struct fm_eth_port_cfg *cfg;
1475 struct fman_if *fman_intf;
1476 struct fman_if_bpool *bp, *tmp_bp;
1477 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1478 uint32_t cgrid_tx[MAX_DPAA_CORES];
1479 char eth_buf[RTE_ETHER_ADDR_FMT_SIZE];
1481 PMD_INIT_FUNC_TRACE();
1483 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1484 dev_id = dpaa_device->id.dev_id;
1485 dpaa_intf = eth_dev->data->dev_private;
1486 cfg = dpaa_get_eth_port_cfg(dev_id);
1487 fman_intf = cfg->fman_if;
1489 dpaa_intf->name = dpaa_device->name;
1491 /* save fman_if & cfg in the interface struture */
1492 eth_dev->process_private = fman_intf;
1493 dpaa_intf->ifid = dev_id;
1494 dpaa_intf->cfg = cfg;
1496 /* Initialize Rx FQ's */
1498 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1500 if (getenv("DPAA_NUM_RX_QUEUES"))
1501 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1503 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1507 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1510 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1511 DPAA_PMD_ERR("Invalid number of RX queues\n");
1515 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1516 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1517 if (!dpaa_intf->rx_queues) {
1518 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1522 memset(cgrid, 0, sizeof(cgrid));
1523 memset(cgrid_tx, 0, sizeof(cgrid_tx));
1525 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1526 * Tx tail drop is disabled.
1528 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1529 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1530 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1532 /* if a very large value is being configured */
1533 if (td_tx_threshold > UINT16_MAX)
1534 td_tx_threshold = CGR_RX_PERFQ_THRESH;
1537 /* If congestion control is enabled globally*/
1539 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1540 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1541 if (!dpaa_intf->cgr_rx) {
1542 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1547 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1548 if (ret != num_rx_fqs) {
1549 DPAA_PMD_WARN("insufficient CGRIDs available");
1554 dpaa_intf->cgr_rx = NULL;
1557 for (loop = 0; loop < num_rx_fqs; loop++) {
1561 fqid = DPAA_PCD_FQID_START + fman_intf->mac_idx *
1562 DPAA_PCD_FQID_MULTIPLIER + loop;
1564 if (dpaa_intf->cgr_rx)
1565 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1567 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1568 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1572 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1574 dpaa_intf->nb_rx_queues = num_rx_fqs;
1576 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1577 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1578 MAX_DPAA_CORES, MAX_CACHELINE);
1579 if (!dpaa_intf->tx_queues) {
1580 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1585 /* If congestion control is enabled globally*/
1586 if (td_tx_threshold) {
1587 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1588 sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1590 if (!dpaa_intf->cgr_tx) {
1591 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1596 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
1598 if (ret != MAX_DPAA_CORES) {
1599 DPAA_PMD_WARN("insufficient CGRIDs available");
1604 dpaa_intf->cgr_tx = NULL;
1608 for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1609 if (dpaa_intf->cgr_tx)
1610 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
1612 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1614 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
1617 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1619 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1621 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1622 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1623 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1624 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1625 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1626 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1627 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1630 DPAA_PMD_DEBUG("All frame queues created");
1632 /* Get the initial configuration for flow control */
1633 dpaa_fc_set_default(dpaa_intf, fman_intf);
1635 /* reset bpool list, initialize bpool dynamically */
1636 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1637 list_del(&bp->node);
1641 /* Populate ethdev structure */
1642 eth_dev->dev_ops = &dpaa_devops;
1643 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1644 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1646 /* Allocate memory for storing MAC addresses */
1647 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1648 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1649 if (eth_dev->data->mac_addrs == NULL) {
1650 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1651 "store MAC addresses",
1652 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1657 /* copy the primary mac address */
1658 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]);
1659 rte_ether_format_addr(eth_buf, sizeof(eth_buf), &fman_intf->mac_addr);
1661 DPAA_PMD_INFO("net: dpaa: %s: %s", dpaa_device->name, eth_buf);
1663 /* Disable RX mode */
1664 fman_if_discard_rx_errors(fman_intf);
1665 fman_if_disable_rx(fman_intf);
1666 /* Disable promiscuous mode */
1667 fman_if_promiscuous_disable(fman_intf);
1668 /* Disable multicast */
1669 fman_if_reset_mcast_filter_table(fman_intf);
1670 /* Reset interface statistics */
1671 fman_if_stats_reset(fman_intf);
1672 /* Disable SG by default */
1673 fman_if_set_sg(fman_intf, 0);
1674 fman_if_set_maxfrm(fman_intf, RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1679 rte_free(dpaa_intf->tx_queues);
1680 dpaa_intf->tx_queues = NULL;
1681 dpaa_intf->nb_tx_queues = 0;
1684 rte_free(dpaa_intf->cgr_rx);
1685 rte_free(dpaa_intf->cgr_tx);
1686 rte_free(dpaa_intf->rx_queues);
1687 dpaa_intf->rx_queues = NULL;
1688 dpaa_intf->nb_rx_queues = 0;
1693 dpaa_dev_uninit(struct rte_eth_dev *dev)
1695 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1698 PMD_INIT_FUNC_TRACE();
1700 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1704 DPAA_PMD_WARN("Already closed or not started");
1708 dpaa_eth_dev_close(dev);
1710 /* release configuration memory */
1711 if (dpaa_intf->fc_conf)
1712 rte_free(dpaa_intf->fc_conf);
1714 /* Release RX congestion Groups */
1715 if (dpaa_intf->cgr_rx) {
1716 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1717 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1719 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1720 dpaa_intf->nb_rx_queues);
1723 rte_free(dpaa_intf->cgr_rx);
1724 dpaa_intf->cgr_rx = NULL;
1726 /* Release TX congestion Groups */
1727 if (dpaa_intf->cgr_tx) {
1728 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
1729 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
1731 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
1733 rte_free(dpaa_intf->cgr_tx);
1734 dpaa_intf->cgr_tx = NULL;
1737 rte_free(dpaa_intf->rx_queues);
1738 dpaa_intf->rx_queues = NULL;
1740 rte_free(dpaa_intf->tx_queues);
1741 dpaa_intf->tx_queues = NULL;
1743 dev->dev_ops = NULL;
1744 dev->rx_pkt_burst = NULL;
1745 dev->tx_pkt_burst = NULL;
1751 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1752 struct rte_dpaa_device *dpaa_dev)
1756 struct rte_eth_dev *eth_dev;
1758 PMD_INIT_FUNC_TRACE();
1760 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
1761 RTE_PKTMBUF_HEADROOM) {
1763 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
1764 RTE_PKTMBUF_HEADROOM,
1765 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
1770 /* In case of secondary process, the device is already configured
1771 * and no further action is required, except portal initialization
1772 * and verifying secondary attachment to port name.
1774 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1775 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1778 eth_dev->device = &dpaa_dev->device;
1779 eth_dev->dev_ops = &dpaa_devops;
1781 ret = dpaa_dev_init_secondary(eth_dev);
1783 RTE_LOG(ERR, PMD, "secondary dev init failed\n");
1787 rte_eth_dev_probing_finish(eth_dev);
1791 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
1792 if (access("/tmp/fmc.bin", F_OK) == -1) {
1793 DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
1797 /* disabling the default push mode for LS1043 */
1798 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1799 dpaa_push_mode_max_queue = 0;
1801 /* if push mode queues to be enabled. Currenly we are allowing
1802 * only one queue per thread.
1804 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1805 dpaa_push_mode_max_queue =
1806 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1807 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1808 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1814 if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
1815 ret = rte_dpaa_portal_init((void *)1);
1817 DPAA_PMD_ERR("Unable to initialize portal");
1822 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1826 eth_dev->data->dev_private =
1827 rte_zmalloc("ethdev private structure",
1828 sizeof(struct dpaa_if),
1829 RTE_CACHE_LINE_SIZE);
1830 if (!eth_dev->data->dev_private) {
1831 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1832 rte_eth_dev_release_port(eth_dev);
1836 eth_dev->device = &dpaa_dev->device;
1837 dpaa_dev->eth_dev = eth_dev;
1839 qman_ern_register_cb(dpaa_free_mbuf);
1841 if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
1842 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
1844 /* Invoke PMD device initialization function */
1845 diag = dpaa_dev_init(eth_dev);
1847 rte_eth_dev_probing_finish(eth_dev);
1851 rte_eth_dev_release_port(eth_dev);
1856 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1858 struct rte_eth_dev *eth_dev;
1860 PMD_INIT_FUNC_TRACE();
1862 eth_dev = dpaa_dev->eth_dev;
1863 dpaa_dev_uninit(eth_dev);
1865 rte_eth_dev_release_port(eth_dev);
1870 static struct rte_dpaa_driver rte_dpaa_pmd = {
1871 .drv_flags = RTE_DPAA_DRV_INTR_LSC,
1872 .drv_type = FSL_DPAA_ETH,
1873 .probe = rte_dpaa_probe,
1874 .remove = rte_dpaa_remove,
1877 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
1878 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);