1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
15 #include <sys/types.h>
16 #include <sys/syscall.h>
18 #include <rte_string_fns.h>
19 #include <rte_byteorder.h>
20 #include <rte_common.h>
21 #include <rte_interrupts.h>
23 #include <rte_debug.h>
25 #include <rte_atomic.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_memory.h>
28 #include <rte_tailq.h>
30 #include <rte_alarm.h>
31 #include <rte_ether.h>
32 #include <rte_ethdev_driver.h>
33 #include <rte_malloc.h>
36 #include <rte_dpaa_bus.h>
37 #include <rte_dpaa_logs.h>
38 #include <dpaa_mempool.h>
40 #include <dpaa_ethdev.h>
41 #include <dpaa_rxtx.h>
42 #include <rte_pmd_dpaa.h>
49 /* Supported Rx offloads */
50 static uint64_t dev_rx_offloads_sup =
51 DEV_RX_OFFLOAD_JUMBO_FRAME |
52 DEV_RX_OFFLOAD_SCATTER;
54 /* Rx offloads which cannot be disabled */
55 static uint64_t dev_rx_offloads_nodis =
56 DEV_RX_OFFLOAD_IPV4_CKSUM |
57 DEV_RX_OFFLOAD_UDP_CKSUM |
58 DEV_RX_OFFLOAD_TCP_CKSUM |
59 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
61 /* Supported Tx offloads */
62 static uint64_t dev_tx_offloads_sup;
64 /* Tx offloads which cannot be disabled */
65 static uint64_t dev_tx_offloads_nodis =
66 DEV_TX_OFFLOAD_IPV4_CKSUM |
67 DEV_TX_OFFLOAD_UDP_CKSUM |
68 DEV_TX_OFFLOAD_TCP_CKSUM |
69 DEV_TX_OFFLOAD_SCTP_CKSUM |
70 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
71 DEV_TX_OFFLOAD_MULTI_SEGS |
72 DEV_TX_OFFLOAD_MT_LOCKFREE |
73 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
75 /* Keep track of whether QMAN and BMAN have been globally initialized */
76 static int is_global_init;
77 static int default_q; /* use default queue - FMC is not executed*/
78 /* At present we only allow up to 4 push mode queues as default - as each of
79 * this queue need dedicated portal and we are short of portals.
81 #define DPAA_MAX_PUSH_MODE_QUEUE 8
82 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
84 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
85 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
88 /* Per FQ Taildrop in frame count */
89 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
91 struct rte_dpaa_xstats_name_off {
92 char name[RTE_ETH_XSTATS_NAME_SIZE];
96 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
98 offsetof(struct dpaa_if_stats, raln)},
100 offsetof(struct dpaa_if_stats, rxpf)},
102 offsetof(struct dpaa_if_stats, rfcs)},
104 offsetof(struct dpaa_if_stats, rvlan)},
106 offsetof(struct dpaa_if_stats, rerr)},
108 offsetof(struct dpaa_if_stats, rdrp)},
110 offsetof(struct dpaa_if_stats, rund)},
112 offsetof(struct dpaa_if_stats, rovr)},
114 offsetof(struct dpaa_if_stats, rfrg)},
116 offsetof(struct dpaa_if_stats, txpf)},
118 offsetof(struct dpaa_if_stats, terr)},
120 offsetof(struct dpaa_if_stats, tvlan)},
122 offsetof(struct dpaa_if_stats, tund)},
125 static struct rte_dpaa_driver rte_dpaa_pmd;
128 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
131 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
133 memset(opts, 0, sizeof(struct qm_mcc_initfq));
134 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
135 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
136 QM_FQCTRL_PREFERINCACHE;
137 opts->fqd.context_a.stashing.exclusive = 0;
138 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
139 opts->fqd.context_a.stashing.annotation_cl =
140 DPAA_IF_RX_ANNOTATION_STASH;
141 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
142 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
146 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
148 struct dpaa_if *dpaa_intf = dev->data->dev_private;
149 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
151 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
153 PMD_INIT_FUNC_TRACE();
155 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
158 * Refuse mtu that requires the support of scattered packets
159 * when this feature has not been enabled before.
161 if (dev->data->min_rx_buf_size &&
162 !dev->data->scattered_rx && frame_size > buffsz) {
163 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
167 /* check <seg size> * <max_seg> >= max_frame */
168 if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
169 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
170 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
171 buffsz * DPAA_SGT_MAX_ENTRIES);
175 if (frame_size > RTE_ETHER_MAX_LEN)
176 dev->data->dev_conf.rxmode.offloads &=
177 DEV_RX_OFFLOAD_JUMBO_FRAME;
179 dev->data->dev_conf.rxmode.offloads &=
180 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
182 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
184 fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
190 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
192 struct dpaa_if *dpaa_intf = dev->data->dev_private;
193 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
194 uint64_t rx_offloads = eth_conf->rxmode.offloads;
195 uint64_t tx_offloads = eth_conf->txmode.offloads;
197 PMD_INIT_FUNC_TRACE();
199 /* Rx offloads validation */
200 if (dev_rx_offloads_nodis & ~rx_offloads) {
202 "Rx offloads non configurable - requested 0x%" PRIx64
203 " ignored 0x%" PRIx64,
204 rx_offloads, dev_rx_offloads_nodis);
207 /* Tx offloads validation */
208 if (dev_tx_offloads_nodis & ~tx_offloads) {
210 "Tx offloads non configurable - requested 0x%" PRIx64
211 " ignored 0x%" PRIx64,
212 tx_offloads, dev_tx_offloads_nodis);
215 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
218 DPAA_PMD_DEBUG("enabling jumbo");
220 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
222 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
224 DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
226 dev->data->dev_conf.rxmode.max_rx_pkt_len,
227 DPAA_MAX_RX_PKT_LEN);
228 max_len = DPAA_MAX_RX_PKT_LEN;
231 fman_if_set_maxfrm(dpaa_intf->fif, max_len);
232 dev->data->mtu = max_len
233 - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
236 if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
237 DPAA_PMD_DEBUG("enabling scatter mode");
238 fman_if_set_sg(dpaa_intf->fif, 1);
239 dev->data->scattered_rx = 1;
245 static const uint32_t *
246 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
248 static const uint32_t ptypes[] = {
250 RTE_PTYPE_L2_ETHER_VLAN,
251 RTE_PTYPE_L2_ETHER_ARP,
252 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
253 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
263 PMD_INIT_FUNC_TRACE();
265 if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
270 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
272 struct dpaa_if *dpaa_intf = dev->data->dev_private;
274 PMD_INIT_FUNC_TRACE();
276 /* Change tx callback to the real one */
277 dev->tx_pkt_burst = dpaa_eth_queue_tx;
278 fman_if_enable_rx(dpaa_intf->fif);
283 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
285 struct dpaa_if *dpaa_intf = dev->data->dev_private;
287 PMD_INIT_FUNC_TRACE();
289 fman_if_disable_rx(dpaa_intf->fif);
290 dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
293 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
295 PMD_INIT_FUNC_TRACE();
297 dpaa_eth_dev_stop(dev);
301 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
306 FILE *svr_file = NULL;
307 unsigned int svr_ver = 0;
309 PMD_INIT_FUNC_TRACE();
311 svr_file = fopen(DPAA_SOC_ID_FILE, "r");
313 DPAA_PMD_ERR("Unable to open SoC device");
314 return -ENOTSUP; /* Not supported on this infra */
316 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
317 dpaa_svr_family = svr_ver & SVR_MASK;
319 DPAA_PMD_ERR("Unable to read SoC device");
323 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
324 svr_ver, fman_ip_rev);
325 ret += 1; /* add the size of '\0' */
327 if (fw_size < (uint32_t)ret)
333 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
334 struct rte_eth_dev_info *dev_info)
336 struct dpaa_if *dpaa_intf = dev->data->dev_private;
338 PMD_INIT_FUNC_TRACE();
340 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
341 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
342 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
343 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
344 dev_info->max_hash_mac_addrs = 0;
345 dev_info->max_vfs = 0;
346 dev_info->max_vmdq_pools = ETH_16_POOLS;
347 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
349 if (dpaa_intf->fif->mac_type == fman_mac_1g) {
350 dev_info->speed_capa = ETH_LINK_SPEED_1G;
351 } else if (dpaa_intf->fif->mac_type == fman_mac_10g) {
352 dev_info->speed_capa = (ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G);
354 DPAA_PMD_ERR("invalid link_speed: %s, %d",
355 dpaa_intf->name, dpaa_intf->fif->mac_type);
359 dev_info->rx_offload_capa = dev_rx_offloads_sup |
360 dev_rx_offloads_nodis;
361 dev_info->tx_offload_capa = dev_tx_offloads_sup |
362 dev_tx_offloads_nodis;
363 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
364 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
369 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
370 int wait_to_complete __rte_unused)
372 struct dpaa_if *dpaa_intf = dev->data->dev_private;
373 struct rte_eth_link *link = &dev->data->dev_link;
375 PMD_INIT_FUNC_TRACE();
377 if (dpaa_intf->fif->mac_type == fman_mac_1g)
378 link->link_speed = ETH_SPEED_NUM_1G;
379 else if (dpaa_intf->fif->mac_type == fman_mac_10g)
380 link->link_speed = ETH_SPEED_NUM_10G;
382 DPAA_PMD_ERR("invalid link_speed: %s, %d",
383 dpaa_intf->name, dpaa_intf->fif->mac_type);
385 link->link_status = dpaa_intf->valid;
386 link->link_duplex = ETH_LINK_FULL_DUPLEX;
387 link->link_autoneg = ETH_LINK_AUTONEG;
391 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
392 struct rte_eth_stats *stats)
394 struct dpaa_if *dpaa_intf = dev->data->dev_private;
396 PMD_INIT_FUNC_TRACE();
398 fman_if_stats_get(dpaa_intf->fif, stats);
402 static void dpaa_eth_stats_reset(struct rte_eth_dev *dev)
404 struct dpaa_if *dpaa_intf = dev->data->dev_private;
406 PMD_INIT_FUNC_TRACE();
408 fman_if_stats_reset(dpaa_intf->fif);
412 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
415 struct dpaa_if *dpaa_intf = dev->data->dev_private;
416 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
417 uint64_t values[sizeof(struct dpaa_if_stats) / 8];
425 fman_if_stats_get_all(dpaa_intf->fif, values,
426 sizeof(struct dpaa_if_stats) / 8);
428 for (i = 0; i < num; i++) {
430 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
436 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
437 struct rte_eth_xstat_name *xstats_names,
440 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
442 if (limit < stat_cnt)
445 if (xstats_names != NULL)
446 for (i = 0; i < stat_cnt; i++)
447 strlcpy(xstats_names[i].name,
448 dpaa_xstats_strings[i].name,
449 sizeof(xstats_names[i].name));
455 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
456 uint64_t *values, unsigned int n)
458 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
459 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
462 struct dpaa_if *dpaa_intf = dev->data->dev_private;
470 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
471 sizeof(struct dpaa_if_stats) / 8);
473 for (i = 0; i < stat_cnt; i++)
475 values_copy[dpaa_xstats_strings[i].offset / 8];
480 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
482 for (i = 0; i < n; i++) {
483 if (ids[i] >= stat_cnt) {
484 DPAA_PMD_ERR("id value isn't valid");
487 values[i] = values_copy[ids[i]];
493 dpaa_xstats_get_names_by_id(
494 struct rte_eth_dev *dev,
495 struct rte_eth_xstat_name *xstats_names,
499 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
500 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
503 return dpaa_xstats_get_names(dev, xstats_names, limit);
505 dpaa_xstats_get_names(dev, xstats_names_copy, limit);
507 for (i = 0; i < limit; i++) {
508 if (ids[i] >= stat_cnt) {
509 DPAA_PMD_ERR("id value isn't valid");
512 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
517 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
519 struct dpaa_if *dpaa_intf = dev->data->dev_private;
521 PMD_INIT_FUNC_TRACE();
523 fman_if_promiscuous_enable(dpaa_intf->fif);
528 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
530 struct dpaa_if *dpaa_intf = dev->data->dev_private;
532 PMD_INIT_FUNC_TRACE();
534 fman_if_promiscuous_disable(dpaa_intf->fif);
539 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
541 struct dpaa_if *dpaa_intf = dev->data->dev_private;
543 PMD_INIT_FUNC_TRACE();
545 fman_if_set_mcast_filter_table(dpaa_intf->fif);
548 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
550 struct dpaa_if *dpaa_intf = dev->data->dev_private;
552 PMD_INIT_FUNC_TRACE();
554 fman_if_reset_mcast_filter_table(dpaa_intf->fif);
558 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
560 unsigned int socket_id __rte_unused,
561 const struct rte_eth_rxconf *rx_conf __rte_unused,
562 struct rte_mempool *mp)
564 struct dpaa_if *dpaa_intf = dev->data->dev_private;
565 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
566 struct qm_mcc_initfq opts = {0};
569 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
571 PMD_INIT_FUNC_TRACE();
573 if (queue_idx >= dev->data->nb_rx_queues) {
574 rte_errno = EOVERFLOW;
575 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
576 (void *)dev, queue_idx, dev->data->nb_rx_queues);
580 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
581 queue_idx, rxq->fqid);
583 /* Max packet can fit in single buffer */
584 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
586 } else if (dev->data->dev_conf.rxmode.offloads &
587 DEV_RX_OFFLOAD_SCATTER) {
588 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
589 buffsz * DPAA_SGT_MAX_ENTRIES) {
590 DPAA_PMD_ERR("max RxPkt size %d too big to fit "
592 dev->data->dev_conf.rxmode.max_rx_pkt_len,
593 buffsz * DPAA_SGT_MAX_ENTRIES);
594 rte_errno = EOVERFLOW;
598 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
599 " larger than a single mbuf (%u) and scattered"
600 " mode has not been requested",
601 dev->data->dev_conf.rxmode.max_rx_pkt_len,
602 buffsz - RTE_PKTMBUF_HEADROOM);
605 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
606 struct fman_if_ic_params icp;
610 if (!mp->pool_data) {
611 DPAA_PMD_ERR("Not an offloaded buffer pool!");
614 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
616 memset(&icp, 0, sizeof(icp));
617 /* set ICEOF for to the default value , which is 0*/
618 icp.iciof = DEFAULT_ICIOF;
619 icp.iceof = DEFAULT_RX_ICEOF;
620 icp.icsz = DEFAULT_ICSZ;
621 fman_if_set_ic_params(dpaa_intf->fif, &icp);
623 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
624 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
626 /* Buffer pool size should be equal to Dataroom Size*/
627 bp_size = rte_pktmbuf_data_room_size(mp);
628 fman_if_set_bp(dpaa_intf->fif, mp->size,
629 dpaa_intf->bp_info->bpid, bp_size);
630 dpaa_intf->valid = 1;
631 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d",
632 dpaa_intf->name, fd_offset,
633 fman_if_get_fdoff(dpaa_intf->fif));
635 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
636 fman_if_get_sg_enable(dpaa_intf->fif),
637 dev->data->dev_conf.rxmode.max_rx_pkt_len);
638 /* checking if push mode only, no error check for now */
639 if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
640 dpaa_push_queue_idx++;
641 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
642 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
643 QM_FQCTRL_CTXASTASHING |
644 QM_FQCTRL_PREFERINCACHE;
645 opts.fqd.context_a.stashing.exclusive = 0;
646 /* In muticore scenario stashing becomes a bottleneck on LS1046.
647 * So do not enable stashing in this case
649 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
650 opts.fqd.context_a.stashing.annotation_cl =
651 DPAA_IF_RX_ANNOTATION_STASH;
652 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
653 opts.fqd.context_a.stashing.context_cl =
654 DPAA_IF_RX_CONTEXT_STASH;
656 /*Create a channel and associate given queue with the channel*/
657 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
658 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
659 opts.fqd.dest.channel = rxq->ch_id;
660 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
661 flags = QMAN_INITFQ_FLAG_SCHED;
663 /* Configure tail drop */
664 if (dpaa_intf->cgr_rx) {
665 opts.we_mask |= QM_INITFQ_WE_CGID;
666 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
667 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
669 ret = qman_init_fq(rxq, flags, &opts);
671 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
672 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
675 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
676 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
678 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
679 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
682 rxq->is_static = true;
684 rxq->bp_array = rte_dpaa_bpid_info;
685 dev->data->rx_queues[queue_idx] = rxq;
687 /* configure the CGR size as per the desc size */
688 if (dpaa_intf->cgr_rx) {
689 struct qm_mcc_initcgr cgr_opts = {0};
691 /* Enable tail drop with cgr on this queue */
692 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
693 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
696 "rx taildrop modify fail on fqid %d (ret=%d)",
705 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
708 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
712 struct dpaa_if *dpaa_intf = dev->data->dev_private;
713 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
714 struct qm_mcc_initfq opts = {0};
716 if (dpaa_push_mode_max_queue)
717 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
718 "PUSH mode already enabled for first %d queues.\n"
719 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
720 dpaa_push_mode_max_queue);
722 dpaa_poll_queue_default_config(&opts);
724 switch (queue_conf->ev.sched_type) {
725 case RTE_SCHED_TYPE_ATOMIC:
726 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
727 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
728 * configuration with HOLD_ACTIVE setting
730 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
731 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
733 case RTE_SCHED_TYPE_ORDERED:
734 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
737 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
738 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
742 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
743 opts.fqd.dest.channel = ch_id;
744 opts.fqd.dest.wq = queue_conf->ev.priority;
746 if (dpaa_intf->cgr_rx) {
747 opts.we_mask |= QM_INITFQ_WE_CGID;
748 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
749 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
752 flags = QMAN_INITFQ_FLAG_SCHED;
754 ret = qman_init_fq(rxq, flags, &opts);
756 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
757 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
761 /* copy configuration which needs to be filled during dequeue */
762 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
763 dev->data->rx_queues[eth_rx_queue_id] = rxq;
769 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
772 struct qm_mcc_initfq opts;
775 struct dpaa_if *dpaa_intf = dev->data->dev_private;
776 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
778 dpaa_poll_queue_default_config(&opts);
780 if (dpaa_intf->cgr_rx) {
781 opts.we_mask |= QM_INITFQ_WE_CGID;
782 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
783 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
786 ret = qman_init_fq(rxq, flags, &opts);
788 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
792 rxq->cb.dqrr_dpdk_cb = NULL;
793 dev->data->rx_queues[eth_rx_queue_id] = NULL;
799 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
801 PMD_INIT_FUNC_TRACE();
805 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
806 uint16_t nb_desc __rte_unused,
807 unsigned int socket_id __rte_unused,
808 const struct rte_eth_txconf *tx_conf __rte_unused)
810 struct dpaa_if *dpaa_intf = dev->data->dev_private;
812 PMD_INIT_FUNC_TRACE();
814 if (queue_idx >= dev->data->nb_tx_queues) {
815 rte_errno = EOVERFLOW;
816 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
817 (void *)dev, queue_idx, dev->data->nb_tx_queues);
821 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
822 queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
823 dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
827 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
829 PMD_INIT_FUNC_TRACE();
833 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
835 struct dpaa_if *dpaa_intf = dev->data->dev_private;
836 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
839 PMD_INIT_FUNC_TRACE();
841 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
842 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n",
843 rx_queue_id, frm_cnt);
848 static int dpaa_link_down(struct rte_eth_dev *dev)
850 PMD_INIT_FUNC_TRACE();
852 dpaa_eth_dev_stop(dev);
856 static int dpaa_link_up(struct rte_eth_dev *dev)
858 PMD_INIT_FUNC_TRACE();
860 dpaa_eth_dev_start(dev);
865 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
866 struct rte_eth_fc_conf *fc_conf)
868 struct dpaa_if *dpaa_intf = dev->data->dev_private;
869 struct rte_eth_fc_conf *net_fc;
871 PMD_INIT_FUNC_TRACE();
873 if (!(dpaa_intf->fc_conf)) {
874 dpaa_intf->fc_conf = rte_zmalloc(NULL,
875 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
876 if (!dpaa_intf->fc_conf) {
877 DPAA_PMD_ERR("unable to save flow control info");
881 net_fc = dpaa_intf->fc_conf;
883 if (fc_conf->high_water < fc_conf->low_water) {
884 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
888 if (fc_conf->mode == RTE_FC_NONE) {
890 } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
891 fc_conf->mode == RTE_FC_FULL) {
892 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
894 dpaa_intf->bp_info->bpid);
895 if (fc_conf->pause_time)
896 fman_if_set_fc_quanta(dpaa_intf->fif,
897 fc_conf->pause_time);
900 /* Save the information in dpaa device */
901 net_fc->pause_time = fc_conf->pause_time;
902 net_fc->high_water = fc_conf->high_water;
903 net_fc->low_water = fc_conf->low_water;
904 net_fc->send_xon = fc_conf->send_xon;
905 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
906 net_fc->mode = fc_conf->mode;
907 net_fc->autoneg = fc_conf->autoneg;
913 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
914 struct rte_eth_fc_conf *fc_conf)
916 struct dpaa_if *dpaa_intf = dev->data->dev_private;
917 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
920 PMD_INIT_FUNC_TRACE();
923 fc_conf->pause_time = net_fc->pause_time;
924 fc_conf->high_water = net_fc->high_water;
925 fc_conf->low_water = net_fc->low_water;
926 fc_conf->send_xon = net_fc->send_xon;
927 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
928 fc_conf->mode = net_fc->mode;
929 fc_conf->autoneg = net_fc->autoneg;
932 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
934 fc_conf->mode = RTE_FC_TX_PAUSE;
935 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
937 fc_conf->mode = RTE_FC_NONE;
944 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
945 struct rte_ether_addr *addr,
947 __rte_unused uint32_t pool)
950 struct dpaa_if *dpaa_intf = dev->data->dev_private;
952 PMD_INIT_FUNC_TRACE();
954 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
957 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:"
963 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
966 struct dpaa_if *dpaa_intf = dev->data->dev_private;
968 PMD_INIT_FUNC_TRACE();
970 fman_if_clear_mac_addr(dpaa_intf->fif, index);
974 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
975 struct rte_ether_addr *addr)
978 struct dpaa_if *dpaa_intf = dev->data->dev_private;
980 PMD_INIT_FUNC_TRACE();
982 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
984 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret);
989 static struct eth_dev_ops dpaa_devops = {
990 .dev_configure = dpaa_eth_dev_configure,
991 .dev_start = dpaa_eth_dev_start,
992 .dev_stop = dpaa_eth_dev_stop,
993 .dev_close = dpaa_eth_dev_close,
994 .dev_infos_get = dpaa_eth_dev_info,
995 .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
997 .rx_queue_setup = dpaa_eth_rx_queue_setup,
998 .tx_queue_setup = dpaa_eth_tx_queue_setup,
999 .rx_queue_release = dpaa_eth_rx_queue_release,
1000 .tx_queue_release = dpaa_eth_tx_queue_release,
1001 .rx_queue_count = dpaa_dev_rx_queue_count,
1003 .flow_ctrl_get = dpaa_flow_ctrl_get,
1004 .flow_ctrl_set = dpaa_flow_ctrl_set,
1006 .link_update = dpaa_eth_link_update,
1007 .stats_get = dpaa_eth_stats_get,
1008 .xstats_get = dpaa_dev_xstats_get,
1009 .xstats_get_by_id = dpaa_xstats_get_by_id,
1010 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id,
1011 .xstats_get_names = dpaa_xstats_get_names,
1012 .xstats_reset = dpaa_eth_stats_reset,
1013 .stats_reset = dpaa_eth_stats_reset,
1014 .promiscuous_enable = dpaa_eth_promiscuous_enable,
1015 .promiscuous_disable = dpaa_eth_promiscuous_disable,
1016 .allmulticast_enable = dpaa_eth_multicast_enable,
1017 .allmulticast_disable = dpaa_eth_multicast_disable,
1018 .mtu_set = dpaa_mtu_set,
1019 .dev_set_link_down = dpaa_link_down,
1020 .dev_set_link_up = dpaa_link_up,
1021 .mac_addr_add = dpaa_dev_add_mac_addr,
1022 .mac_addr_remove = dpaa_dev_remove_mac_addr,
1023 .mac_addr_set = dpaa_dev_set_mac_addr,
1025 .fw_version_get = dpaa_fw_version_get,
1029 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1031 if (strcmp(dev->device->driver->name,
1039 is_dpaa_supported(struct rte_eth_dev *dev)
1041 return is_device_supported(dev, &rte_dpaa_pmd);
1045 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1047 struct rte_eth_dev *dev;
1048 struct dpaa_if *dpaa_intf;
1050 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1052 dev = &rte_eth_devices[port];
1054 if (!is_dpaa_supported(dev))
1057 dpaa_intf = dev->data->dev_private;
1060 fman_if_loopback_enable(dpaa_intf->fif);
1062 fman_if_loopback_disable(dpaa_intf->fif);
1067 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
1069 struct rte_eth_fc_conf *fc_conf;
1072 PMD_INIT_FUNC_TRACE();
1074 if (!(dpaa_intf->fc_conf)) {
1075 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1076 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1077 if (!dpaa_intf->fc_conf) {
1078 DPAA_PMD_ERR("unable to save flow control info");
1082 fc_conf = dpaa_intf->fc_conf;
1083 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
1085 fc_conf->mode = RTE_FC_TX_PAUSE;
1086 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
1088 fc_conf->mode = RTE_FC_NONE;
1094 /* Initialise an Rx FQ */
1095 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1098 struct qm_mcc_initfq opts = {0};
1100 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1101 struct qm_mcc_initcgr cgr_opts = {
1102 .we_mask = QM_CGR_WE_CS_THRES |
1106 .cstd_en = QM_CGR_EN,
1107 .mode = QMAN_CGR_MODE_FRAME
1111 PMD_INIT_FUNC_TRACE();
1114 ret = qman_reserve_fqid(fqid);
1116 DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1121 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1123 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1124 ret = qman_create_fq(fqid, flags, fq);
1126 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1130 fq->is_static = false;
1132 dpaa_poll_queue_default_config(&opts);
1135 /* Enable tail drop with cgr on this queue */
1136 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1138 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1142 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1146 opts.we_mask |= QM_INITFQ_WE_CGID;
1147 opts.fqd.cgid = cgr_rx->cgrid;
1148 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1151 ret = qman_init_fq(fq, 0, &opts);
1153 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1157 /* Initialise a Tx FQ */
1158 static int dpaa_tx_queue_init(struct qman_fq *fq,
1159 struct fman_if *fman_intf)
1161 struct qm_mcc_initfq opts = {0};
1164 PMD_INIT_FUNC_TRACE();
1166 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1167 QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1169 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1172 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1173 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1174 opts.fqd.dest.channel = fman_intf->tx_channel_id;
1175 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1176 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1177 opts.fqd.context_b = 0;
1178 /* no tx-confirmation */
1179 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1180 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1181 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1182 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1184 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1188 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1189 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1190 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1192 struct qm_mcc_initfq opts = {0};
1195 PMD_INIT_FUNC_TRACE();
1197 ret = qman_reserve_fqid(fqid);
1199 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1203 /* "map" this Rx FQ to one of the interfaces Tx FQID */
1204 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1205 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1207 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1211 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1212 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1213 ret = qman_init_fq(fq, 0, &opts);
1215 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1221 /* Initialise a network interface */
1223 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1225 int num_rx_fqs, fqid;
1228 struct rte_dpaa_device *dpaa_device;
1229 struct dpaa_if *dpaa_intf;
1230 struct fm_eth_port_cfg *cfg;
1231 struct fman_if *fman_intf;
1232 struct fman_if_bpool *bp, *tmp_bp;
1233 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1235 PMD_INIT_FUNC_TRACE();
1237 dpaa_intf = eth_dev->data->dev_private;
1238 /* For secondary processes, the primary has done all the work */
1239 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1240 eth_dev->dev_ops = &dpaa_devops;
1241 /* Plugging of UCODE burst API not supported in Secondary */
1242 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1243 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1244 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1245 qman_set_fq_lookup_table(
1246 dpaa_intf->rx_queues->qman_fq_lookup_table);
1251 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1252 dev_id = dpaa_device->id.dev_id;
1253 dpaa_intf = eth_dev->data->dev_private;
1254 cfg = &dpaa_netcfg->port_cfg[dev_id];
1255 fman_intf = cfg->fman_if;
1257 dpaa_intf->name = dpaa_device->name;
1259 /* save fman_if & cfg in the interface struture */
1260 dpaa_intf->fif = fman_intf;
1261 dpaa_intf->ifid = dev_id;
1262 dpaa_intf->cfg = cfg;
1264 /* Initialize Rx FQ's */
1266 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1268 if (getenv("DPAA_NUM_RX_QUEUES"))
1269 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1271 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1275 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1278 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1279 DPAA_PMD_ERR("Invalid number of RX queues\n");
1283 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1284 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1285 if (!dpaa_intf->rx_queues) {
1286 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1290 /* If congestion control is enabled globally*/
1292 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1293 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1294 if (!dpaa_intf->cgr_rx) {
1295 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1300 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1301 if (ret != num_rx_fqs) {
1302 DPAA_PMD_WARN("insufficient CGRIDs available");
1307 dpaa_intf->cgr_rx = NULL;
1310 for (loop = 0; loop < num_rx_fqs; loop++) {
1314 fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx *
1315 DPAA_PCD_FQID_MULTIPLIER + loop;
1317 if (dpaa_intf->cgr_rx)
1318 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1320 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1321 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1325 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1327 dpaa_intf->nb_rx_queues = num_rx_fqs;
1329 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1330 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1331 MAX_DPAA_CORES, MAX_CACHELINE);
1332 if (!dpaa_intf->tx_queues) {
1333 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1338 for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1339 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1343 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1345 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1347 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1348 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1349 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1350 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1351 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1352 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1353 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1356 DPAA_PMD_DEBUG("All frame queues created");
1358 /* Get the initial configuration for flow control */
1359 dpaa_fc_set_default(dpaa_intf);
1361 /* reset bpool list, initialize bpool dynamically */
1362 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1363 list_del(&bp->node);
1367 /* Populate ethdev structure */
1368 eth_dev->dev_ops = &dpaa_devops;
1369 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1370 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1372 /* Allocate memory for storing MAC addresses */
1373 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1374 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1375 if (eth_dev->data->mac_addrs == NULL) {
1376 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1377 "store MAC addresses",
1378 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1383 /* copy the primary mac address */
1384 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]);
1386 RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1388 fman_intf->mac_addr.addr_bytes[0],
1389 fman_intf->mac_addr.addr_bytes[1],
1390 fman_intf->mac_addr.addr_bytes[2],
1391 fman_intf->mac_addr.addr_bytes[3],
1392 fman_intf->mac_addr.addr_bytes[4],
1393 fman_intf->mac_addr.addr_bytes[5]);
1395 /* Disable RX mode */
1396 fman_if_discard_rx_errors(fman_intf);
1397 fman_if_disable_rx(fman_intf);
1398 /* Disable promiscuous mode */
1399 fman_if_promiscuous_disable(fman_intf);
1400 /* Disable multicast */
1401 fman_if_reset_mcast_filter_table(fman_intf);
1402 /* Reset interface statistics */
1403 fman_if_stats_reset(fman_intf);
1404 /* Disable SG by default */
1405 fman_if_set_sg(fman_intf, 0);
1406 fman_if_set_maxfrm(fman_intf, RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1411 rte_free(dpaa_intf->tx_queues);
1412 dpaa_intf->tx_queues = NULL;
1413 dpaa_intf->nb_tx_queues = 0;
1416 rte_free(dpaa_intf->cgr_rx);
1417 rte_free(dpaa_intf->rx_queues);
1418 dpaa_intf->rx_queues = NULL;
1419 dpaa_intf->nb_rx_queues = 0;
1424 dpaa_dev_uninit(struct rte_eth_dev *dev)
1426 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1429 PMD_INIT_FUNC_TRACE();
1431 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1435 DPAA_PMD_WARN("Already closed or not started");
1439 dpaa_eth_dev_close(dev);
1441 /* release configuration memory */
1442 if (dpaa_intf->fc_conf)
1443 rte_free(dpaa_intf->fc_conf);
1445 /* Release RX congestion Groups */
1446 if (dpaa_intf->cgr_rx) {
1447 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1448 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1450 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1451 dpaa_intf->nb_rx_queues);
1454 rte_free(dpaa_intf->cgr_rx);
1455 dpaa_intf->cgr_rx = NULL;
1457 rte_free(dpaa_intf->rx_queues);
1458 dpaa_intf->rx_queues = NULL;
1460 rte_free(dpaa_intf->tx_queues);
1461 dpaa_intf->tx_queues = NULL;
1463 dev->dev_ops = NULL;
1464 dev->rx_pkt_burst = NULL;
1465 dev->tx_pkt_burst = NULL;
1471 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1472 struct rte_dpaa_device *dpaa_dev)
1476 struct rte_eth_dev *eth_dev;
1478 PMD_INIT_FUNC_TRACE();
1480 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
1481 RTE_PKTMBUF_HEADROOM) {
1483 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
1484 RTE_PKTMBUF_HEADROOM,
1485 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
1490 /* In case of secondary process, the device is already configured
1491 * and no further action is required, except portal initialization
1492 * and verifying secondary attachment to port name.
1494 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1495 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1498 eth_dev->device = &dpaa_dev->device;
1499 eth_dev->dev_ops = &dpaa_devops;
1500 rte_eth_dev_probing_finish(eth_dev);
1504 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
1505 /* One time load of Qman/Bman drivers */
1506 ret = qman_global_init();
1508 DPAA_PMD_ERR("QMAN initialization failed: %d",
1512 ret = bman_global_init();
1514 DPAA_PMD_ERR("BMAN initialization failed: %d",
1519 if (access("/tmp/fmc.bin", F_OK) == -1) {
1521 "* FMC not configured.Enabling default mode\n");
1525 /* disabling the default push mode for LS1043 */
1526 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1527 dpaa_push_mode_max_queue = 0;
1529 /* if push mode queues to be enabled. Currenly we are allowing
1530 * only one queue per thread.
1532 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1533 dpaa_push_mode_max_queue =
1534 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1535 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1536 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1542 if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1543 ret = rte_dpaa_portal_init((void *)1);
1545 DPAA_PMD_ERR("Unable to initialize portal");
1550 /* In case of secondary process, the device is already configured
1551 * and no further action is required, except portal initialization
1552 * and verifying secondary attachment to port name.
1554 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1555 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1559 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1560 if (eth_dev == NULL)
1563 eth_dev->data->dev_private = rte_zmalloc(
1564 "ethdev private structure",
1565 sizeof(struct dpaa_if),
1566 RTE_CACHE_LINE_SIZE);
1567 if (!eth_dev->data->dev_private) {
1568 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1569 rte_eth_dev_release_port(eth_dev);
1573 eth_dev->device = &dpaa_dev->device;
1574 dpaa_dev->eth_dev = eth_dev;
1576 /* Invoke PMD device initialization function */
1577 diag = dpaa_dev_init(eth_dev);
1579 rte_eth_dev_probing_finish(eth_dev);
1583 rte_eth_dev_release_port(eth_dev);
1588 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1590 struct rte_eth_dev *eth_dev;
1592 PMD_INIT_FUNC_TRACE();
1594 eth_dev = dpaa_dev->eth_dev;
1595 dpaa_dev_uninit(eth_dev);
1597 rte_eth_dev_release_port(eth_dev);
1602 static struct rte_dpaa_driver rte_dpaa_pmd = {
1603 .drv_type = FSL_DPAA_ETH,
1604 .probe = rte_dpaa_probe,
1605 .remove = rte_dpaa_remove,
1608 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);