1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
15 #include <sys/types.h>
16 #include <sys/syscall.h>
18 #include <rte_byteorder.h>
19 #include <rte_common.h>
20 #include <rte_interrupts.h>
22 #include <rte_debug.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_malloc.h>
35 #include <rte_dpaa_bus.h>
36 #include <rte_dpaa_logs.h>
37 #include <dpaa_mempool.h>
39 #include <dpaa_ethdev.h>
40 #include <dpaa_rxtx.h>
41 #include <rte_pmd_dpaa.h>
48 /* Supported Rx offloads */
49 static uint64_t dev_rx_offloads_sup =
50 DEV_RX_OFFLOAD_JUMBO_FRAME |
51 DEV_RX_OFFLOAD_SCATTER;
53 /* Rx offloads which cannot be disabled */
54 static uint64_t dev_rx_offloads_nodis =
55 DEV_RX_OFFLOAD_IPV4_CKSUM |
56 DEV_RX_OFFLOAD_UDP_CKSUM |
57 DEV_RX_OFFLOAD_TCP_CKSUM |
58 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
60 /* Supported Tx offloads */
61 static uint64_t dev_tx_offloads_sup;
63 /* Tx offloads which cannot be disabled */
64 static uint64_t dev_tx_offloads_nodis =
65 DEV_TX_OFFLOAD_IPV4_CKSUM |
66 DEV_TX_OFFLOAD_UDP_CKSUM |
67 DEV_TX_OFFLOAD_TCP_CKSUM |
68 DEV_TX_OFFLOAD_SCTP_CKSUM |
69 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
70 DEV_TX_OFFLOAD_MULTI_SEGS |
71 DEV_TX_OFFLOAD_MT_LOCKFREE |
72 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
74 /* Keep track of whether QMAN and BMAN have been globally initialized */
75 static int is_global_init;
76 static int default_q; /* use default queue - FMC is not executed*/
77 /* At present we only allow up to 4 push mode queues as default - as each of
78 * this queue need dedicated portal and we are short of portals.
80 #define DPAA_MAX_PUSH_MODE_QUEUE 8
81 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
83 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
84 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
87 /* Per FQ Taildrop in frame count */
88 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
90 struct rte_dpaa_xstats_name_off {
91 char name[RTE_ETH_XSTATS_NAME_SIZE];
95 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
97 offsetof(struct dpaa_if_stats, raln)},
99 offsetof(struct dpaa_if_stats, rxpf)},
101 offsetof(struct dpaa_if_stats, rfcs)},
103 offsetof(struct dpaa_if_stats, rvlan)},
105 offsetof(struct dpaa_if_stats, rerr)},
107 offsetof(struct dpaa_if_stats, rdrp)},
109 offsetof(struct dpaa_if_stats, rund)},
111 offsetof(struct dpaa_if_stats, rovr)},
113 offsetof(struct dpaa_if_stats, rfrg)},
115 offsetof(struct dpaa_if_stats, txpf)},
117 offsetof(struct dpaa_if_stats, terr)},
119 offsetof(struct dpaa_if_stats, tvlan)},
121 offsetof(struct dpaa_if_stats, tund)},
124 static struct rte_dpaa_driver rte_dpaa_pmd;
127 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
130 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
132 memset(opts, 0, sizeof(struct qm_mcc_initfq));
133 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
134 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
135 QM_FQCTRL_PREFERINCACHE;
136 opts->fqd.context_a.stashing.exclusive = 0;
137 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
138 opts->fqd.context_a.stashing.annotation_cl =
139 DPAA_IF_RX_ANNOTATION_STASH;
140 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
141 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
145 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
147 struct dpaa_if *dpaa_intf = dev->data->dev_private;
148 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
150 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
152 PMD_INIT_FUNC_TRACE();
154 if (mtu < ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
157 * Refuse mtu that requires the support of scattered packets
158 * when this feature has not been enabled before.
160 if (dev->data->min_rx_buf_size &&
161 !dev->data->scattered_rx && frame_size > buffsz) {
162 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
166 /* check <seg size> * <max_seg> >= max_frame */
167 if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
168 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
169 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
170 buffsz * DPAA_SGT_MAX_ENTRIES);
174 if (frame_size > ETHER_MAX_LEN)
175 dev->data->dev_conf.rxmode.offloads &=
176 DEV_RX_OFFLOAD_JUMBO_FRAME;
178 dev->data->dev_conf.rxmode.offloads &=
179 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
181 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
183 fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
189 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
191 struct dpaa_if *dpaa_intf = dev->data->dev_private;
192 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
193 uint64_t rx_offloads = eth_conf->rxmode.offloads;
194 uint64_t tx_offloads = eth_conf->txmode.offloads;
196 PMD_INIT_FUNC_TRACE();
198 /* Rx offloads validation */
199 if (dev_rx_offloads_nodis & ~rx_offloads) {
201 "Rx offloads non configurable - requested 0x%" PRIx64
202 " ignored 0x%" PRIx64,
203 rx_offloads, dev_rx_offloads_nodis);
206 /* Tx offloads validation */
207 if (dev_tx_offloads_nodis & ~tx_offloads) {
209 "Tx offloads non configurable - requested 0x%" PRIx64
210 " ignored 0x%" PRIx64,
211 tx_offloads, dev_tx_offloads_nodis);
214 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
217 DPAA_PMD_DEBUG("enabling jumbo");
219 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
221 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
223 DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
225 dev->data->dev_conf.rxmode.max_rx_pkt_len,
226 DPAA_MAX_RX_PKT_LEN);
227 max_len = DPAA_MAX_RX_PKT_LEN;
230 fman_if_set_maxfrm(dpaa_intf->fif, max_len);
231 dev->data->mtu = max_len
232 - ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
235 if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
236 DPAA_PMD_DEBUG("enabling scatter mode");
237 fman_if_set_sg(dpaa_intf->fif, 1);
238 dev->data->scattered_rx = 1;
244 static const uint32_t *
245 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
247 static const uint32_t ptypes[] = {
248 /*todo -= add more types */
251 RTE_PTYPE_L3_IPV4_EXT,
253 RTE_PTYPE_L3_IPV6_EXT,
259 PMD_INIT_FUNC_TRACE();
261 if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
266 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
268 struct dpaa_if *dpaa_intf = dev->data->dev_private;
270 PMD_INIT_FUNC_TRACE();
272 /* Change tx callback to the real one */
273 dev->tx_pkt_burst = dpaa_eth_queue_tx;
274 fman_if_enable_rx(dpaa_intf->fif);
279 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
281 struct dpaa_if *dpaa_intf = dev->data->dev_private;
283 PMD_INIT_FUNC_TRACE();
285 fman_if_disable_rx(dpaa_intf->fif);
286 dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
289 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
291 PMD_INIT_FUNC_TRACE();
293 dpaa_eth_dev_stop(dev);
297 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
302 FILE *svr_file = NULL;
303 unsigned int svr_ver = 0;
305 PMD_INIT_FUNC_TRACE();
307 svr_file = fopen(DPAA_SOC_ID_FILE, "r");
309 DPAA_PMD_ERR("Unable to open SoC device");
310 return -ENOTSUP; /* Not supported on this infra */
312 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
313 dpaa_svr_family = svr_ver & SVR_MASK;
315 DPAA_PMD_ERR("Unable to read SoC device");
319 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
320 svr_ver, fman_ip_rev);
321 ret += 1; /* add the size of '\0' */
323 if (fw_size < (uint32_t)ret)
329 static void dpaa_eth_dev_info(struct rte_eth_dev *dev,
330 struct rte_eth_dev_info *dev_info)
332 struct dpaa_if *dpaa_intf = dev->data->dev_private;
334 PMD_INIT_FUNC_TRACE();
336 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
337 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
338 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
339 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
340 dev_info->max_hash_mac_addrs = 0;
341 dev_info->max_vfs = 0;
342 dev_info->max_vmdq_pools = ETH_16_POOLS;
343 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
345 if (dpaa_intf->fif->mac_type == fman_mac_1g)
346 dev_info->speed_capa = ETH_LINK_SPEED_1G;
347 else if (dpaa_intf->fif->mac_type == fman_mac_10g)
348 dev_info->speed_capa = (ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G);
350 DPAA_PMD_ERR("invalid link_speed: %s, %d",
351 dpaa_intf->name, dpaa_intf->fif->mac_type);
353 dev_info->rx_offload_capa = dev_rx_offloads_sup |
354 dev_rx_offloads_nodis;
355 dev_info->tx_offload_capa = dev_tx_offloads_sup |
356 dev_tx_offloads_nodis;
357 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
358 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
361 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
362 int wait_to_complete __rte_unused)
364 struct dpaa_if *dpaa_intf = dev->data->dev_private;
365 struct rte_eth_link *link = &dev->data->dev_link;
367 PMD_INIT_FUNC_TRACE();
369 if (dpaa_intf->fif->mac_type == fman_mac_1g)
370 link->link_speed = ETH_SPEED_NUM_1G;
371 else if (dpaa_intf->fif->mac_type == fman_mac_10g)
372 link->link_speed = ETH_SPEED_NUM_10G;
374 DPAA_PMD_ERR("invalid link_speed: %s, %d",
375 dpaa_intf->name, dpaa_intf->fif->mac_type);
377 link->link_status = dpaa_intf->valid;
378 link->link_duplex = ETH_LINK_FULL_DUPLEX;
379 link->link_autoneg = ETH_LINK_AUTONEG;
383 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
384 struct rte_eth_stats *stats)
386 struct dpaa_if *dpaa_intf = dev->data->dev_private;
388 PMD_INIT_FUNC_TRACE();
390 fman_if_stats_get(dpaa_intf->fif, stats);
394 static void dpaa_eth_stats_reset(struct rte_eth_dev *dev)
396 struct dpaa_if *dpaa_intf = dev->data->dev_private;
398 PMD_INIT_FUNC_TRACE();
400 fman_if_stats_reset(dpaa_intf->fif);
404 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
407 struct dpaa_if *dpaa_intf = dev->data->dev_private;
408 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
409 uint64_t values[sizeof(struct dpaa_if_stats) / 8];
417 fman_if_stats_get_all(dpaa_intf->fif, values,
418 sizeof(struct dpaa_if_stats) / 8);
420 for (i = 0; i < num; i++) {
422 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
428 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
429 struct rte_eth_xstat_name *xstats_names,
432 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
434 if (limit < stat_cnt)
437 if (xstats_names != NULL)
438 for (i = 0; i < stat_cnt; i++)
439 snprintf(xstats_names[i].name,
440 sizeof(xstats_names[i].name),
442 dpaa_xstats_strings[i].name);
448 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
449 uint64_t *values, unsigned int n)
451 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
452 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
455 struct dpaa_if *dpaa_intf = dev->data->dev_private;
463 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
464 sizeof(struct dpaa_if_stats) / 8);
466 for (i = 0; i < stat_cnt; i++)
468 values_copy[dpaa_xstats_strings[i].offset / 8];
473 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
475 for (i = 0; i < n; i++) {
476 if (ids[i] >= stat_cnt) {
477 DPAA_PMD_ERR("id value isn't valid");
480 values[i] = values_copy[ids[i]];
486 dpaa_xstats_get_names_by_id(
487 struct rte_eth_dev *dev,
488 struct rte_eth_xstat_name *xstats_names,
492 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
493 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
496 return dpaa_xstats_get_names(dev, xstats_names, limit);
498 dpaa_xstats_get_names(dev, xstats_names_copy, limit);
500 for (i = 0; i < limit; i++) {
501 if (ids[i] >= stat_cnt) {
502 DPAA_PMD_ERR("id value isn't valid");
505 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
510 static void dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
512 struct dpaa_if *dpaa_intf = dev->data->dev_private;
514 PMD_INIT_FUNC_TRACE();
516 fman_if_promiscuous_enable(dpaa_intf->fif);
519 static void dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
521 struct dpaa_if *dpaa_intf = dev->data->dev_private;
523 PMD_INIT_FUNC_TRACE();
525 fman_if_promiscuous_disable(dpaa_intf->fif);
528 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
530 struct dpaa_if *dpaa_intf = dev->data->dev_private;
532 PMD_INIT_FUNC_TRACE();
534 fman_if_set_mcast_filter_table(dpaa_intf->fif);
537 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
539 struct dpaa_if *dpaa_intf = dev->data->dev_private;
541 PMD_INIT_FUNC_TRACE();
543 fman_if_reset_mcast_filter_table(dpaa_intf->fif);
547 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
549 unsigned int socket_id __rte_unused,
550 const struct rte_eth_rxconf *rx_conf __rte_unused,
551 struct rte_mempool *mp)
553 struct dpaa_if *dpaa_intf = dev->data->dev_private;
554 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
555 struct qm_mcc_initfq opts = {0};
558 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
560 PMD_INIT_FUNC_TRACE();
562 if (queue_idx >= dev->data->nb_rx_queues) {
563 rte_errno = EOVERFLOW;
564 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
565 (void *)dev, queue_idx, dev->data->nb_rx_queues);
569 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
570 queue_idx, rxq->fqid);
572 /* Max packet can fit in single buffer */
573 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
575 } else if (dev->data->dev_conf.rxmode.offloads &
576 DEV_RX_OFFLOAD_SCATTER) {
577 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
578 buffsz * DPAA_SGT_MAX_ENTRIES) {
579 DPAA_PMD_ERR("max RxPkt size %d too big to fit "
581 dev->data->dev_conf.rxmode.max_rx_pkt_len,
582 buffsz * DPAA_SGT_MAX_ENTRIES);
583 rte_errno = EOVERFLOW;
587 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
588 " larger than a single mbuf (%u) and scattered"
589 " mode has not been requested",
590 dev->data->dev_conf.rxmode.max_rx_pkt_len,
591 buffsz - RTE_PKTMBUF_HEADROOM);
594 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
595 struct fman_if_ic_params icp;
599 if (!mp->pool_data) {
600 DPAA_PMD_ERR("Not an offloaded buffer pool!");
603 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
605 memset(&icp, 0, sizeof(icp));
606 /* set ICEOF for to the default value , which is 0*/
607 icp.iciof = DEFAULT_ICIOF;
608 icp.iceof = DEFAULT_RX_ICEOF;
609 icp.icsz = DEFAULT_ICSZ;
610 fman_if_set_ic_params(dpaa_intf->fif, &icp);
612 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
613 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
615 /* Buffer pool size should be equal to Dataroom Size*/
616 bp_size = rte_pktmbuf_data_room_size(mp);
617 fman_if_set_bp(dpaa_intf->fif, mp->size,
618 dpaa_intf->bp_info->bpid, bp_size);
619 dpaa_intf->valid = 1;
620 DPAA_PMD_INFO("if =%s - fd_offset = %d offset = %d",
621 dpaa_intf->name, fd_offset,
622 fman_if_get_fdoff(dpaa_intf->fif));
624 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
625 fman_if_get_sg_enable(dpaa_intf->fif),
626 dev->data->dev_conf.rxmode.max_rx_pkt_len);
627 /* checking if push mode only, no error check for now */
628 if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
629 dpaa_push_queue_idx++;
630 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
631 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
632 QM_FQCTRL_CTXASTASHING |
633 QM_FQCTRL_PREFERINCACHE;
634 opts.fqd.context_a.stashing.exclusive = 0;
635 /* In muticore scenario stashing becomes a bottleneck on LS1046.
636 * So do not enable stashing in this case
638 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
639 opts.fqd.context_a.stashing.annotation_cl =
640 DPAA_IF_RX_ANNOTATION_STASH;
641 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
642 opts.fqd.context_a.stashing.context_cl =
643 DPAA_IF_RX_CONTEXT_STASH;
645 /*Create a channel and associate given queue with the channel*/
646 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
647 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
648 opts.fqd.dest.channel = rxq->ch_id;
649 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
650 flags = QMAN_INITFQ_FLAG_SCHED;
652 /* Configure tail drop */
653 if (dpaa_intf->cgr_rx) {
654 opts.we_mask |= QM_INITFQ_WE_CGID;
655 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
656 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
658 ret = qman_init_fq(rxq, flags, &opts);
660 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
661 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
664 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
665 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
666 rxq->is_static = true;
668 dev->data->rx_queues[queue_idx] = rxq;
670 /* configure the CGR size as per the desc size */
671 if (dpaa_intf->cgr_rx) {
672 struct qm_mcc_initcgr cgr_opts = {0};
674 /* Enable tail drop with cgr on this queue */
675 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
676 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
679 "rx taildrop modify fail on fqid %d (ret=%d)",
688 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
691 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
695 struct dpaa_if *dpaa_intf = dev->data->dev_private;
696 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
697 struct qm_mcc_initfq opts = {0};
699 if (dpaa_push_mode_max_queue)
700 DPAA_PMD_WARN("PUSH mode already enabled for first %d queues.\n"
701 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
702 dpaa_push_mode_max_queue);
704 dpaa_poll_queue_default_config(&opts);
706 switch (queue_conf->ev.sched_type) {
707 case RTE_SCHED_TYPE_ATOMIC:
708 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
709 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
710 * configuration with HOLD_ACTIVE setting
712 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
713 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
715 case RTE_SCHED_TYPE_ORDERED:
716 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
719 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
720 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
724 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
725 opts.fqd.dest.channel = ch_id;
726 opts.fqd.dest.wq = queue_conf->ev.priority;
728 if (dpaa_intf->cgr_rx) {
729 opts.we_mask |= QM_INITFQ_WE_CGID;
730 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
731 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
734 flags = QMAN_INITFQ_FLAG_SCHED;
736 ret = qman_init_fq(rxq, flags, &opts);
738 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
739 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
743 /* copy configuration which needs to be filled during dequeue */
744 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
745 dev->data->rx_queues[eth_rx_queue_id] = rxq;
751 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
754 struct qm_mcc_initfq opts;
757 struct dpaa_if *dpaa_intf = dev->data->dev_private;
758 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
760 dpaa_poll_queue_default_config(&opts);
762 if (dpaa_intf->cgr_rx) {
763 opts.we_mask |= QM_INITFQ_WE_CGID;
764 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
765 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
768 ret = qman_init_fq(rxq, flags, &opts);
770 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
774 rxq->cb.dqrr_dpdk_cb = NULL;
775 dev->data->rx_queues[eth_rx_queue_id] = NULL;
781 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
783 PMD_INIT_FUNC_TRACE();
787 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
788 uint16_t nb_desc __rte_unused,
789 unsigned int socket_id __rte_unused,
790 const struct rte_eth_txconf *tx_conf __rte_unused)
792 struct dpaa_if *dpaa_intf = dev->data->dev_private;
794 PMD_INIT_FUNC_TRACE();
796 if (queue_idx >= dev->data->nb_tx_queues) {
797 rte_errno = EOVERFLOW;
798 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
799 (void *)dev, queue_idx, dev->data->nb_tx_queues);
803 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
804 queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
805 dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
809 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
811 PMD_INIT_FUNC_TRACE();
815 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
817 struct dpaa_if *dpaa_intf = dev->data->dev_private;
818 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
821 PMD_INIT_FUNC_TRACE();
823 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
824 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n",
825 rx_queue_id, frm_cnt);
830 static int dpaa_link_down(struct rte_eth_dev *dev)
832 PMD_INIT_FUNC_TRACE();
834 dpaa_eth_dev_stop(dev);
838 static int dpaa_link_up(struct rte_eth_dev *dev)
840 PMD_INIT_FUNC_TRACE();
842 dpaa_eth_dev_start(dev);
847 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
848 struct rte_eth_fc_conf *fc_conf)
850 struct dpaa_if *dpaa_intf = dev->data->dev_private;
851 struct rte_eth_fc_conf *net_fc;
853 PMD_INIT_FUNC_TRACE();
855 if (!(dpaa_intf->fc_conf)) {
856 dpaa_intf->fc_conf = rte_zmalloc(NULL,
857 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
858 if (!dpaa_intf->fc_conf) {
859 DPAA_PMD_ERR("unable to save flow control info");
863 net_fc = dpaa_intf->fc_conf;
865 if (fc_conf->high_water < fc_conf->low_water) {
866 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
870 if (fc_conf->mode == RTE_FC_NONE) {
872 } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
873 fc_conf->mode == RTE_FC_FULL) {
874 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
876 dpaa_intf->bp_info->bpid);
877 if (fc_conf->pause_time)
878 fman_if_set_fc_quanta(dpaa_intf->fif,
879 fc_conf->pause_time);
882 /* Save the information in dpaa device */
883 net_fc->pause_time = fc_conf->pause_time;
884 net_fc->high_water = fc_conf->high_water;
885 net_fc->low_water = fc_conf->low_water;
886 net_fc->send_xon = fc_conf->send_xon;
887 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
888 net_fc->mode = fc_conf->mode;
889 net_fc->autoneg = fc_conf->autoneg;
895 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
896 struct rte_eth_fc_conf *fc_conf)
898 struct dpaa_if *dpaa_intf = dev->data->dev_private;
899 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
902 PMD_INIT_FUNC_TRACE();
905 fc_conf->pause_time = net_fc->pause_time;
906 fc_conf->high_water = net_fc->high_water;
907 fc_conf->low_water = net_fc->low_water;
908 fc_conf->send_xon = net_fc->send_xon;
909 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
910 fc_conf->mode = net_fc->mode;
911 fc_conf->autoneg = net_fc->autoneg;
914 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
916 fc_conf->mode = RTE_FC_TX_PAUSE;
917 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
919 fc_conf->mode = RTE_FC_NONE;
926 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
927 struct ether_addr *addr,
929 __rte_unused uint32_t pool)
932 struct dpaa_if *dpaa_intf = dev->data->dev_private;
934 PMD_INIT_FUNC_TRACE();
936 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
939 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:"
945 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
948 struct dpaa_if *dpaa_intf = dev->data->dev_private;
950 PMD_INIT_FUNC_TRACE();
952 fman_if_clear_mac_addr(dpaa_intf->fif, index);
956 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
957 struct ether_addr *addr)
960 struct dpaa_if *dpaa_intf = dev->data->dev_private;
962 PMD_INIT_FUNC_TRACE();
964 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
966 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret);
971 static struct eth_dev_ops dpaa_devops = {
972 .dev_configure = dpaa_eth_dev_configure,
973 .dev_start = dpaa_eth_dev_start,
974 .dev_stop = dpaa_eth_dev_stop,
975 .dev_close = dpaa_eth_dev_close,
976 .dev_infos_get = dpaa_eth_dev_info,
977 .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
979 .rx_queue_setup = dpaa_eth_rx_queue_setup,
980 .tx_queue_setup = dpaa_eth_tx_queue_setup,
981 .rx_queue_release = dpaa_eth_rx_queue_release,
982 .tx_queue_release = dpaa_eth_tx_queue_release,
983 .rx_queue_count = dpaa_dev_rx_queue_count,
985 .flow_ctrl_get = dpaa_flow_ctrl_get,
986 .flow_ctrl_set = dpaa_flow_ctrl_set,
988 .link_update = dpaa_eth_link_update,
989 .stats_get = dpaa_eth_stats_get,
990 .xstats_get = dpaa_dev_xstats_get,
991 .xstats_get_by_id = dpaa_xstats_get_by_id,
992 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id,
993 .xstats_get_names = dpaa_xstats_get_names,
994 .xstats_reset = dpaa_eth_stats_reset,
995 .stats_reset = dpaa_eth_stats_reset,
996 .promiscuous_enable = dpaa_eth_promiscuous_enable,
997 .promiscuous_disable = dpaa_eth_promiscuous_disable,
998 .allmulticast_enable = dpaa_eth_multicast_enable,
999 .allmulticast_disable = dpaa_eth_multicast_disable,
1000 .mtu_set = dpaa_mtu_set,
1001 .dev_set_link_down = dpaa_link_down,
1002 .dev_set_link_up = dpaa_link_up,
1003 .mac_addr_add = dpaa_dev_add_mac_addr,
1004 .mac_addr_remove = dpaa_dev_remove_mac_addr,
1005 .mac_addr_set = dpaa_dev_set_mac_addr,
1007 .fw_version_get = dpaa_fw_version_get,
1011 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1013 if (strcmp(dev->device->driver->name,
1021 is_dpaa_supported(struct rte_eth_dev *dev)
1023 return is_device_supported(dev, &rte_dpaa_pmd);
1027 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1029 struct rte_eth_dev *dev;
1030 struct dpaa_if *dpaa_intf;
1032 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1034 dev = &rte_eth_devices[port];
1036 if (!is_dpaa_supported(dev))
1039 dpaa_intf = dev->data->dev_private;
1042 fman_if_loopback_enable(dpaa_intf->fif);
1044 fman_if_loopback_disable(dpaa_intf->fif);
1049 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
1051 struct rte_eth_fc_conf *fc_conf;
1054 PMD_INIT_FUNC_TRACE();
1056 if (!(dpaa_intf->fc_conf)) {
1057 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1058 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1059 if (!dpaa_intf->fc_conf) {
1060 DPAA_PMD_ERR("unable to save flow control info");
1064 fc_conf = dpaa_intf->fc_conf;
1065 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
1067 fc_conf->mode = RTE_FC_TX_PAUSE;
1068 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
1070 fc_conf->mode = RTE_FC_NONE;
1076 /* Initialise an Rx FQ */
1077 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1080 struct qm_mcc_initfq opts = {0};
1082 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1083 struct qm_mcc_initcgr cgr_opts = {
1084 .we_mask = QM_CGR_WE_CS_THRES |
1088 .cstd_en = QM_CGR_EN,
1089 .mode = QMAN_CGR_MODE_FRAME
1093 PMD_INIT_FUNC_TRACE();
1096 ret = qman_reserve_fqid(fqid);
1098 DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1103 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1105 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1106 ret = qman_create_fq(fqid, flags, fq);
1108 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1112 fq->is_static = false;
1114 dpaa_poll_queue_default_config(&opts);
1117 /* Enable tail drop with cgr on this queue */
1118 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1120 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1124 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1128 opts.we_mask |= QM_INITFQ_WE_CGID;
1129 opts.fqd.cgid = cgr_rx->cgrid;
1130 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1133 ret = qman_init_fq(fq, 0, &opts);
1135 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1139 /* Initialise a Tx FQ */
1140 static int dpaa_tx_queue_init(struct qman_fq *fq,
1141 struct fman_if *fman_intf)
1143 struct qm_mcc_initfq opts = {0};
1146 PMD_INIT_FUNC_TRACE();
1148 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1149 QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1151 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1154 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1155 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1156 opts.fqd.dest.channel = fman_intf->tx_channel_id;
1157 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1158 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1159 opts.fqd.context_b = 0;
1160 /* no tx-confirmation */
1161 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1162 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1163 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1164 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1166 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1170 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1171 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1172 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1174 struct qm_mcc_initfq opts = {0};
1177 PMD_INIT_FUNC_TRACE();
1179 ret = qman_reserve_fqid(fqid);
1181 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1185 /* "map" this Rx FQ to one of the interfaces Tx FQID */
1186 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1187 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1189 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1193 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1194 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1195 ret = qman_init_fq(fq, 0, &opts);
1197 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1203 /* Initialise a network interface */
1205 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1207 int num_cores, num_rx_fqs, fqid;
1210 struct rte_dpaa_device *dpaa_device;
1211 struct dpaa_if *dpaa_intf;
1212 struct fm_eth_port_cfg *cfg;
1213 struct fman_if *fman_intf;
1214 struct fman_if_bpool *bp, *tmp_bp;
1215 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1217 PMD_INIT_FUNC_TRACE();
1219 /* For secondary processes, the primary has done all the work */
1220 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1223 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1224 dev_id = dpaa_device->id.dev_id;
1225 dpaa_intf = eth_dev->data->dev_private;
1226 cfg = &dpaa_netcfg->port_cfg[dev_id];
1227 fman_intf = cfg->fman_if;
1229 dpaa_intf->name = dpaa_device->name;
1231 /* save fman_if & cfg in the interface struture */
1232 dpaa_intf->fif = fman_intf;
1233 dpaa_intf->ifid = dev_id;
1234 dpaa_intf->cfg = cfg;
1236 /* Initialize Rx FQ's */
1238 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1240 if (getenv("DPAA_NUM_RX_QUEUES"))
1241 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1243 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1247 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1250 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1251 DPAA_PMD_ERR("Invalid number of RX queues\n");
1255 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1256 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1257 if (!dpaa_intf->rx_queues) {
1258 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1262 /* If congestion control is enabled globally*/
1264 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1265 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1266 if (!dpaa_intf->cgr_rx) {
1267 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1272 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1273 if (ret != num_rx_fqs) {
1274 DPAA_PMD_WARN("insufficient CGRIDs available");
1279 dpaa_intf->cgr_rx = NULL;
1282 for (loop = 0; loop < num_rx_fqs; loop++) {
1286 fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx *
1287 DPAA_PCD_FQID_MULTIPLIER + loop;
1289 if (dpaa_intf->cgr_rx)
1290 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1292 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1293 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1297 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1299 dpaa_intf->nb_rx_queues = num_rx_fqs;
1301 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1302 num_cores = rte_lcore_count();
1303 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1304 num_cores, MAX_CACHELINE);
1305 if (!dpaa_intf->tx_queues) {
1306 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1311 for (loop = 0; loop < num_cores; loop++) {
1312 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1316 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1318 dpaa_intf->nb_tx_queues = num_cores;
1320 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1321 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1322 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1323 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1324 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1325 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1326 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1329 DPAA_PMD_DEBUG("All frame queues created");
1331 /* Get the initial configuration for flow control */
1332 dpaa_fc_set_default(dpaa_intf);
1334 /* reset bpool list, initialize bpool dynamically */
1335 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1336 list_del(&bp->node);
1340 /* Populate ethdev structure */
1341 eth_dev->dev_ops = &dpaa_devops;
1342 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1343 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1345 /* Allocate memory for storing MAC addresses */
1346 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1347 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1348 if (eth_dev->data->mac_addrs == NULL) {
1349 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1350 "store MAC addresses",
1351 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1356 /* copy the primary mac address */
1357 ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]);
1359 RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1361 fman_intf->mac_addr.addr_bytes[0],
1362 fman_intf->mac_addr.addr_bytes[1],
1363 fman_intf->mac_addr.addr_bytes[2],
1364 fman_intf->mac_addr.addr_bytes[3],
1365 fman_intf->mac_addr.addr_bytes[4],
1366 fman_intf->mac_addr.addr_bytes[5]);
1368 /* Disable RX mode */
1369 fman_if_discard_rx_errors(fman_intf);
1370 fman_if_disable_rx(fman_intf);
1371 /* Disable promiscuous mode */
1372 fman_if_promiscuous_disable(fman_intf);
1373 /* Disable multicast */
1374 fman_if_reset_mcast_filter_table(fman_intf);
1375 /* Reset interface statistics */
1376 fman_if_stats_reset(fman_intf);
1377 /* Disable SG by default */
1378 fman_if_set_sg(fman_intf, 0);
1379 fman_if_set_maxfrm(fman_intf, ETHER_MAX_LEN + VLAN_TAG_SIZE);
1384 rte_free(dpaa_intf->tx_queues);
1385 dpaa_intf->tx_queues = NULL;
1386 dpaa_intf->nb_tx_queues = 0;
1389 rte_free(dpaa_intf->cgr_rx);
1390 rte_free(dpaa_intf->rx_queues);
1391 dpaa_intf->rx_queues = NULL;
1392 dpaa_intf->nb_rx_queues = 0;
1397 dpaa_dev_uninit(struct rte_eth_dev *dev)
1399 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1402 PMD_INIT_FUNC_TRACE();
1404 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1408 DPAA_PMD_WARN("Already closed or not started");
1412 dpaa_eth_dev_close(dev);
1414 /* release configuration memory */
1415 if (dpaa_intf->fc_conf)
1416 rte_free(dpaa_intf->fc_conf);
1418 /* Release RX congestion Groups */
1419 if (dpaa_intf->cgr_rx) {
1420 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1421 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1423 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1424 dpaa_intf->nb_rx_queues);
1427 rte_free(dpaa_intf->cgr_rx);
1428 dpaa_intf->cgr_rx = NULL;
1430 rte_free(dpaa_intf->rx_queues);
1431 dpaa_intf->rx_queues = NULL;
1433 rte_free(dpaa_intf->tx_queues);
1434 dpaa_intf->tx_queues = NULL;
1436 /* free memory for storing MAC addresses */
1437 rte_free(dev->data->mac_addrs);
1438 dev->data->mac_addrs = NULL;
1440 dev->dev_ops = NULL;
1441 dev->rx_pkt_burst = NULL;
1442 dev->tx_pkt_burst = NULL;
1448 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1449 struct rte_dpaa_device *dpaa_dev)
1453 struct rte_eth_dev *eth_dev;
1455 PMD_INIT_FUNC_TRACE();
1457 /* In case of secondary process, the device is already configured
1458 * and no further action is required, except portal initialization
1459 * and verifying secondary attachment to port name.
1461 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1462 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1465 eth_dev->device = &dpaa_dev->device;
1466 eth_dev->dev_ops = &dpaa_devops;
1467 rte_eth_dev_probing_finish(eth_dev);
1471 if (!is_global_init) {
1472 /* One time load of Qman/Bman drivers */
1473 ret = qman_global_init();
1475 DPAA_PMD_ERR("QMAN initialization failed: %d",
1479 ret = bman_global_init();
1481 DPAA_PMD_ERR("BMAN initialization failed: %d",
1486 if (access("/tmp/fmc.bin", F_OK) == -1) {
1488 "* FMC not configured.Enabling default mode\n");
1492 /* disabling the default push mode for LS1043 */
1493 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1494 dpaa_push_mode_max_queue = 0;
1496 /* if push mode queues to be enabled. Currenly we are allowing
1497 * only one queue per thread.
1499 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1500 dpaa_push_mode_max_queue =
1501 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1502 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1503 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1509 if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1510 ret = rte_dpaa_portal_init((void *)1);
1512 DPAA_PMD_ERR("Unable to initialize portal");
1517 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1518 if (eth_dev == NULL)
1521 eth_dev->data->dev_private = rte_zmalloc(
1522 "ethdev private structure",
1523 sizeof(struct dpaa_if),
1524 RTE_CACHE_LINE_SIZE);
1525 if (!eth_dev->data->dev_private) {
1526 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1527 rte_eth_dev_release_port(eth_dev);
1531 eth_dev->device = &dpaa_dev->device;
1532 dpaa_dev->eth_dev = eth_dev;
1534 /* Invoke PMD device initialization function */
1535 diag = dpaa_dev_init(eth_dev);
1537 rte_eth_dev_probing_finish(eth_dev);
1541 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1542 rte_free(eth_dev->data->dev_private);
1544 rte_eth_dev_release_port(eth_dev);
1549 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1551 struct rte_eth_dev *eth_dev;
1553 PMD_INIT_FUNC_TRACE();
1555 eth_dev = dpaa_dev->eth_dev;
1556 dpaa_dev_uninit(eth_dev);
1558 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1559 rte_free(eth_dev->data->dev_private);
1561 rte_eth_dev_release_port(eth_dev);
1566 static struct rte_dpaa_driver rte_dpaa_pmd = {
1567 .drv_type = FSL_DPAA_ETH,
1568 .probe = rte_dpaa_probe,
1569 .remove = rte_dpaa_remove,
1572 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);