1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_common.h>
12 #include <rte_interrupts.h>
13 #include <rte_byteorder.h>
15 #include <rte_debug.h>
17 #include <rte_bus_pci.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_memory.h>
23 #include <rte_malloc.h>
26 #include "e1000_logs.h"
27 #include "base/e1000_api.h"
28 #include "e1000_ethdev.h"
30 #define EM_EIAC 0x000DC
32 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
35 static int eth_em_configure(struct rte_eth_dev *dev);
36 static int eth_em_start(struct rte_eth_dev *dev);
37 static void eth_em_stop(struct rte_eth_dev *dev);
38 static void eth_em_close(struct rte_eth_dev *dev);
39 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
40 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
41 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
42 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
43 static int eth_em_link_update(struct rte_eth_dev *dev,
44 int wait_to_complete);
45 static int eth_em_stats_get(struct rte_eth_dev *dev,
46 struct rte_eth_stats *rte_stats);
47 static void eth_em_stats_reset(struct rte_eth_dev *dev);
48 static void eth_em_infos_get(struct rte_eth_dev *dev,
49 struct rte_eth_dev_info *dev_info);
50 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
51 struct rte_eth_fc_conf *fc_conf);
52 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
53 struct rte_eth_fc_conf *fc_conf);
54 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
55 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
56 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
57 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
58 struct rte_intr_handle *handle);
59 static void eth_em_interrupt_handler(void *param);
61 static int em_hw_init(struct e1000_hw *hw);
62 static int em_hardware_init(struct e1000_hw *hw);
63 static void em_hw_control_acquire(struct e1000_hw *hw);
64 static void em_hw_control_release(struct e1000_hw *hw);
65 static void em_init_manageability(struct e1000_hw *hw);
66 static void em_release_manageability(struct e1000_hw *hw);
68 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
70 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
71 uint16_t vlan_id, int on);
72 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
73 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
74 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
75 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
76 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
79 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
80 uint16_t vlan_id, int on);
83 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
84 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
85 static void em_lsc_intr_disable(struct e1000_hw *hw);
86 static void em_rxq_intr_enable(struct e1000_hw *hw);
87 static void em_rxq_intr_disable(struct e1000_hw *hw);
89 static int eth_em_led_on(struct rte_eth_dev *dev);
90 static int eth_em_led_off(struct rte_eth_dev *dev);
92 static int em_get_rx_buffer_size(struct e1000_hw *hw);
93 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
94 uint32_t index, uint32_t pool);
95 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
96 static void eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
97 struct ether_addr *addr);
99 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
100 struct ether_addr *mc_addr_set,
101 uint32_t nb_mc_addr);
103 #define EM_FC_PAUSE_TIME 0x0680
104 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
105 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
107 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
109 int e1000_logtype_init;
110 int e1000_logtype_driver;
113 * The set of PCI devices this driver supports
115 static const struct rte_pci_id pci_id_em_map[] = {
116 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
117 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
118 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
119 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
120 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
121 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
122 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
123 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
124 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
125 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
126 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
127 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
128 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
129 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
130 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
131 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
132 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
133 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
134 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
135 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
136 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
137 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
138 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
139 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
140 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
141 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
158 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
159 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
160 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
161 { .vendor_id = 0, /* sentinel */ },
164 static const struct eth_dev_ops eth_em_ops = {
165 .dev_configure = eth_em_configure,
166 .dev_start = eth_em_start,
167 .dev_stop = eth_em_stop,
168 .dev_close = eth_em_close,
169 .promiscuous_enable = eth_em_promiscuous_enable,
170 .promiscuous_disable = eth_em_promiscuous_disable,
171 .allmulticast_enable = eth_em_allmulticast_enable,
172 .allmulticast_disable = eth_em_allmulticast_disable,
173 .link_update = eth_em_link_update,
174 .stats_get = eth_em_stats_get,
175 .stats_reset = eth_em_stats_reset,
176 .dev_infos_get = eth_em_infos_get,
177 .mtu_set = eth_em_mtu_set,
178 .vlan_filter_set = eth_em_vlan_filter_set,
179 .vlan_offload_set = eth_em_vlan_offload_set,
180 .rx_queue_setup = eth_em_rx_queue_setup,
181 .rx_queue_release = eth_em_rx_queue_release,
182 .rx_queue_count = eth_em_rx_queue_count,
183 .rx_descriptor_done = eth_em_rx_descriptor_done,
184 .rx_descriptor_status = eth_em_rx_descriptor_status,
185 .tx_descriptor_status = eth_em_tx_descriptor_status,
186 .tx_queue_setup = eth_em_tx_queue_setup,
187 .tx_queue_release = eth_em_tx_queue_release,
188 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
189 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
190 .dev_led_on = eth_em_led_on,
191 .dev_led_off = eth_em_led_off,
192 .flow_ctrl_get = eth_em_flow_ctrl_get,
193 .flow_ctrl_set = eth_em_flow_ctrl_set,
194 .mac_addr_set = eth_em_default_mac_addr_set,
195 .mac_addr_add = eth_em_rar_set,
196 .mac_addr_remove = eth_em_rar_clear,
197 .set_mc_addr_list = eth_em_set_mc_addr_list,
198 .rxq_info_get = em_rxq_info_get,
199 .txq_info_get = em_txq_info_get,
204 * eth_em_dev_is_ich8 - Check for ICH8 device
205 * @hw: pointer to the HW structure
207 * return TRUE for ICH8, otherwise FALSE
210 eth_em_dev_is_ich8(struct e1000_hw *hw)
212 DEBUGFUNC("eth_em_dev_is_ich8");
214 switch (hw->device_id) {
215 case E1000_DEV_ID_PCH2_LV_LM:
216 case E1000_DEV_ID_PCH_LPT_I217_LM:
217 case E1000_DEV_ID_PCH_LPT_I217_V:
218 case E1000_DEV_ID_PCH_LPTLP_I218_LM:
219 case E1000_DEV_ID_PCH_LPTLP_I218_V:
220 case E1000_DEV_ID_PCH_I218_V2:
221 case E1000_DEV_ID_PCH_I218_LM2:
222 case E1000_DEV_ID_PCH_I218_V3:
223 case E1000_DEV_ID_PCH_I218_LM3:
224 case E1000_DEV_ID_PCH_SPT_I219_LM:
225 case E1000_DEV_ID_PCH_SPT_I219_V:
226 case E1000_DEV_ID_PCH_SPT_I219_LM2:
227 case E1000_DEV_ID_PCH_SPT_I219_V2:
228 case E1000_DEV_ID_PCH_LBG_I219_LM3:
229 case E1000_DEV_ID_PCH_SPT_I219_LM4:
230 case E1000_DEV_ID_PCH_SPT_I219_V4:
231 case E1000_DEV_ID_PCH_SPT_I219_LM5:
232 case E1000_DEV_ID_PCH_SPT_I219_V5:
233 case E1000_DEV_ID_PCH_CNP_I219_LM6:
234 case E1000_DEV_ID_PCH_CNP_I219_V6:
235 case E1000_DEV_ID_PCH_CNP_I219_LM7:
236 case E1000_DEV_ID_PCH_CNP_I219_V7:
244 eth_em_dev_init(struct rte_eth_dev *eth_dev)
246 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
247 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
248 struct e1000_adapter *adapter =
249 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
250 struct e1000_hw *hw =
251 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
252 struct e1000_vfta * shadow_vfta =
253 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
255 eth_dev->dev_ops = ð_em_ops;
256 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
257 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
258 eth_dev->tx_pkt_prepare = (eth_tx_prep_t)ð_em_prep_pkts;
260 /* for secondary processes, we don't initialise any further as primary
261 * has already done this work. Only check we don't need a different
263 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
264 if (eth_dev->data->scattered_rx)
265 eth_dev->rx_pkt_burst =
266 (eth_rx_burst_t)ð_em_recv_scattered_pkts;
270 rte_eth_copy_pci_info(eth_dev, pci_dev);
272 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
273 hw->device_id = pci_dev->id.device_id;
274 adapter->stopped = 0;
276 /* For ICH8 support we'll need to map the flash memory BAR */
277 if (eth_em_dev_is_ich8(hw))
278 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
280 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
281 em_hw_init(hw) != 0) {
282 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
284 eth_dev->data->port_id, pci_dev->id.vendor_id,
285 pci_dev->id.device_id);
289 /* Allocate memory for storing MAC addresses */
290 eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
291 hw->mac.rar_entry_count, 0);
292 if (eth_dev->data->mac_addrs == NULL) {
293 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
294 "store MAC addresses",
295 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
299 /* Copy the permanent MAC address */
300 ether_addr_copy((struct ether_addr *) hw->mac.addr,
301 eth_dev->data->mac_addrs);
303 /* initialize the vfta */
304 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
306 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
307 eth_dev->data->port_id, pci_dev->id.vendor_id,
308 pci_dev->id.device_id);
310 rte_intr_callback_register(intr_handle,
311 eth_em_interrupt_handler, eth_dev);
317 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
319 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
320 struct e1000_adapter *adapter =
321 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
322 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
324 PMD_INIT_FUNC_TRACE();
326 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
329 if (adapter->stopped == 0)
330 eth_em_close(eth_dev);
332 eth_dev->dev_ops = NULL;
333 eth_dev->rx_pkt_burst = NULL;
334 eth_dev->tx_pkt_burst = NULL;
336 rte_free(eth_dev->data->mac_addrs);
337 eth_dev->data->mac_addrs = NULL;
339 /* disable uio intr before callback unregister */
340 rte_intr_disable(intr_handle);
341 rte_intr_callback_unregister(intr_handle,
342 eth_em_interrupt_handler, eth_dev);
347 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
348 struct rte_pci_device *pci_dev)
350 return rte_eth_dev_pci_generic_probe(pci_dev,
351 sizeof(struct e1000_adapter), eth_em_dev_init);
354 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
356 return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
359 static struct rte_pci_driver rte_em_pmd = {
360 .id_table = pci_id_em_map,
361 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
362 RTE_PCI_DRV_IOVA_AS_VA,
363 .probe = eth_em_pci_probe,
364 .remove = eth_em_pci_remove,
368 em_hw_init(struct e1000_hw *hw)
372 diag = hw->mac.ops.init_params(hw);
374 PMD_INIT_LOG(ERR, "MAC Initialization Error");
377 diag = hw->nvm.ops.init_params(hw);
379 PMD_INIT_LOG(ERR, "NVM Initialization Error");
382 diag = hw->phy.ops.init_params(hw);
384 PMD_INIT_LOG(ERR, "PHY Initialization Error");
387 (void) e1000_get_bus_info(hw);
390 hw->phy.autoneg_wait_to_complete = 0;
391 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
393 e1000_init_script_state_82541(hw, TRUE);
394 e1000_set_tbi_compatibility_82543(hw, TRUE);
397 if (hw->phy.media_type == e1000_media_type_copper) {
398 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
399 hw->phy.disable_polarity_correction = 0;
400 hw->phy.ms_type = e1000_ms_hw_default;
404 * Start from a known state, this is important in reading the nvm
409 /* Make sure we have a good EEPROM before we read from it */
410 if (e1000_validate_nvm_checksum(hw) < 0) {
412 * Some PCI-E parts fail the first check due to
413 * the link being in sleep state, call it again,
414 * if it fails a second time its a real issue.
416 diag = e1000_validate_nvm_checksum(hw);
418 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
423 /* Read the permanent MAC address out of the EEPROM */
424 diag = e1000_read_mac_addr(hw);
426 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
430 /* Now initialize the hardware */
431 diag = em_hardware_init(hw);
433 PMD_INIT_LOG(ERR, "Hardware initialization failed");
437 hw->mac.get_link_status = 1;
439 /* Indicate SOL/IDER usage */
440 diag = e1000_check_reset_block(hw);
442 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
448 em_hw_control_release(hw);
453 eth_em_configure(struct rte_eth_dev *dev)
455 struct e1000_interrupt *intr =
456 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
457 struct rte_eth_dev_info dev_info;
458 uint64_t rx_offloads;
459 uint64_t tx_offloads;
461 PMD_INIT_FUNC_TRACE();
462 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
464 eth_em_infos_get(dev, &dev_info);
465 rx_offloads = dev->data->dev_conf.rxmode.offloads;
466 if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
467 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
468 "requested 0x%" PRIx64 " supported 0x%" PRIx64,
469 rx_offloads, dev_info.rx_offload_capa);
472 tx_offloads = dev->data->dev_conf.txmode.offloads;
473 if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
474 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
475 "requested 0x%" PRIx64 " supported 0x%" PRIx64,
476 tx_offloads, dev_info.tx_offload_capa);
480 PMD_INIT_FUNC_TRACE();
486 em_set_pba(struct e1000_hw *hw)
491 * Packet Buffer Allocation (PBA)
492 * Writing PBA sets the receive portion of the buffer
493 * the remainder is used for the transmit buffer.
494 * Devices before the 82547 had a Packet Buffer of 64K.
495 * After the 82547 the buffer was reduced to 40K.
497 switch (hw->mac.type) {
499 case e1000_82547_rev_2:
500 /* 82547: Total Packet Buffer is 40K */
501 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
505 case e1000_80003es2lan:
506 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
508 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
509 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
513 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
530 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
533 E1000_WRITE_REG(hw, E1000_PBA, pba);
537 eth_em_rxtx_control(struct rte_eth_dev *dev,
540 struct e1000_hw *hw =
541 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
544 tctl = E1000_READ_REG(hw, E1000_TCTL);
545 rctl = E1000_READ_REG(hw, E1000_RCTL);
548 tctl |= E1000_TCTL_EN;
549 rctl |= E1000_RCTL_EN;
552 tctl &= ~E1000_TCTL_EN;
553 rctl &= ~E1000_RCTL_EN;
555 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
556 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
557 E1000_WRITE_FLUSH(hw);
561 eth_em_start(struct rte_eth_dev *dev)
563 struct e1000_adapter *adapter =
564 E1000_DEV_PRIVATE(dev->data->dev_private);
565 struct e1000_hw *hw =
566 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
567 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
568 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
570 uint32_t intr_vector = 0;
575 PMD_INIT_FUNC_TRACE();
579 e1000_power_up_phy(hw);
581 /* Set default PBA value */
584 /* Put the address into the Receive Address Array */
585 e1000_rar_set(hw, hw->mac.addr, 0);
588 * With the 82571 adapter, RAR[0] may be overwritten
589 * when the other port is reset, we make a duplicate
590 * in RAR[14] for that eventuality, this assures
591 * the interface continues to function.
593 if (hw->mac.type == e1000_82571) {
594 e1000_set_laa_state_82571(hw, TRUE);
595 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
598 /* Initialize the hardware */
599 if (em_hardware_init(hw)) {
600 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
604 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
606 /* Configure for OS presence */
607 em_init_manageability(hw);
609 if (dev->data->dev_conf.intr_conf.rxq != 0) {
610 intr_vector = dev->data->nb_rx_queues;
611 if (rte_intr_efd_enable(intr_handle, intr_vector))
615 if (rte_intr_dp_is_en(intr_handle)) {
616 intr_handle->intr_vec =
617 rte_zmalloc("intr_vec",
618 dev->data->nb_rx_queues * sizeof(int), 0);
619 if (intr_handle->intr_vec == NULL) {
620 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
621 " intr_vec", dev->data->nb_rx_queues);
625 /* enable rx interrupt */
626 em_rxq_intr_enable(hw);
631 ret = eth_em_rx_init(dev);
633 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
634 em_dev_clear_queues(dev);
638 e1000_clear_hw_cntrs_base_generic(hw);
640 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
641 ETH_VLAN_EXTEND_MASK;
642 ret = eth_em_vlan_offload_set(dev, mask);
644 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
645 em_dev_clear_queues(dev);
649 /* Set Interrupt Throttling Rate to maximum allowed value. */
650 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
652 /* Setup link speed and duplex */
653 speeds = &dev->data->dev_conf.link_speeds;
654 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
655 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
659 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
662 hw->phy.autoneg_advertised = 0;
664 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
665 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
666 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
668 goto error_invalid_config;
670 if (*speeds & ETH_LINK_SPEED_10M_HD) {
671 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
674 if (*speeds & ETH_LINK_SPEED_10M) {
675 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
678 if (*speeds & ETH_LINK_SPEED_100M_HD) {
679 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
682 if (*speeds & ETH_LINK_SPEED_100M) {
683 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
686 if (*speeds & ETH_LINK_SPEED_1G) {
687 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
690 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
691 goto error_invalid_config;
693 /* Set/reset the mac.autoneg based on the link speed,
698 hw->mac.forced_speed_duplex =
699 hw->phy.autoneg_advertised;
705 e1000_setup_link(hw);
707 if (rte_intr_allow_others(intr_handle)) {
708 /* check if lsc interrupt is enabled */
709 if (dev->data->dev_conf.intr_conf.lsc != 0) {
710 ret = eth_em_interrupt_setup(dev);
712 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
713 em_dev_clear_queues(dev);
718 rte_intr_callback_unregister(intr_handle,
719 eth_em_interrupt_handler,
721 if (dev->data->dev_conf.intr_conf.lsc != 0)
722 PMD_INIT_LOG(INFO, "lsc won't enable because of"
723 " no intr multiplexn");
725 /* check if rxq interrupt is enabled */
726 if (dev->data->dev_conf.intr_conf.rxq != 0)
727 eth_em_rxq_interrupt_setup(dev);
729 rte_intr_enable(intr_handle);
731 adapter->stopped = 0;
733 eth_em_rxtx_control(dev, true);
734 eth_em_link_update(dev, 0);
736 PMD_INIT_LOG(DEBUG, "<<");
740 error_invalid_config:
741 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
742 dev->data->dev_conf.link_speeds, dev->data->port_id);
743 em_dev_clear_queues(dev);
747 /*********************************************************************
749 * This routine disables all traffic on the adapter by issuing a
750 * global reset on the MAC.
752 **********************************************************************/
754 eth_em_stop(struct rte_eth_dev *dev)
756 struct rte_eth_link link;
757 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
758 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
759 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
761 eth_em_rxtx_control(dev, false);
762 em_rxq_intr_disable(hw);
763 em_lsc_intr_disable(hw);
766 if (hw->mac.type >= e1000_82544)
767 E1000_WRITE_REG(hw, E1000_WUC, 0);
769 /* Power down the phy. Needed to make the link go down */
770 e1000_power_down_phy(hw);
772 em_dev_clear_queues(dev);
774 /* clear the recorded link status */
775 memset(&link, 0, sizeof(link));
776 rte_eth_linkstatus_set(dev, &link);
778 if (!rte_intr_allow_others(intr_handle))
779 /* resume to the default handler */
780 rte_intr_callback_register(intr_handle,
781 eth_em_interrupt_handler,
784 /* Clean datapath event and queue/vec mapping */
785 rte_intr_efd_disable(intr_handle);
786 if (intr_handle->intr_vec != NULL) {
787 rte_free(intr_handle->intr_vec);
788 intr_handle->intr_vec = NULL;
793 eth_em_close(struct rte_eth_dev *dev)
795 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
796 struct e1000_adapter *adapter =
797 E1000_DEV_PRIVATE(dev->data->dev_private);
800 adapter->stopped = 1;
801 em_dev_free_queues(dev);
802 e1000_phy_hw_reset(hw);
803 em_release_manageability(hw);
804 em_hw_control_release(hw);
808 em_get_rx_buffer_size(struct e1000_hw *hw)
810 uint32_t rx_buf_size;
812 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
816 /*********************************************************************
818 * Initialize the hardware
820 **********************************************************************/
822 em_hardware_init(struct e1000_hw *hw)
824 uint32_t rx_buf_size;
827 /* Issue a global reset */
830 /* Let the firmware know the OS is in control */
831 em_hw_control_acquire(hw);
834 * These parameters control the automatic generation (Tx) and
835 * response (Rx) to Ethernet PAUSE frames.
836 * - High water mark should allow for at least two standard size (1518)
837 * frames to be received after sending an XOFF.
838 * - Low water mark works best when it is very near the high water mark.
839 * This allows the receiver to restart by sending XON when it has
840 * drained a bit. Here we use an arbitrary value of 1500 which will
841 * restart after one full frame is pulled from the buffer. There
842 * could be several smaller frames in the buffer and if so they will
843 * not trigger the XON until their total number reduces the buffer
845 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
847 rx_buf_size = em_get_rx_buffer_size(hw);
849 hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
850 hw->fc.low_water = hw->fc.high_water - 1500;
852 if (hw->mac.type == e1000_80003es2lan)
853 hw->fc.pause_time = UINT16_MAX;
855 hw->fc.pause_time = EM_FC_PAUSE_TIME;
859 /* Set Flow control, use the tunable location if sane */
860 if (em_fc_setting <= e1000_fc_full)
861 hw->fc.requested_mode = em_fc_setting;
863 hw->fc.requested_mode = e1000_fc_none;
865 /* Workaround: no TX flow ctrl for PCH */
866 if (hw->mac.type == e1000_pchlan)
867 hw->fc.requested_mode = e1000_fc_rx_pause;
869 /* Override - settings for PCH2LAN, ya its magic :) */
870 if (hw->mac.type == e1000_pch2lan) {
871 hw->fc.high_water = 0x5C20;
872 hw->fc.low_water = 0x5048;
873 hw->fc.pause_time = 0x0650;
874 hw->fc.refresh_time = 0x0400;
875 } else if (hw->mac.type == e1000_pch_lpt ||
876 hw->mac.type == e1000_pch_spt ||
877 hw->mac.type == e1000_pch_cnp) {
878 hw->fc.requested_mode = e1000_fc_full;
881 diag = e1000_init_hw(hw);
884 e1000_check_for_link(hw);
888 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
890 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
892 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
893 struct e1000_hw_stats *stats =
894 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
897 if(hw->phy.media_type == e1000_media_type_copper ||
898 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
899 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
900 stats->sec += E1000_READ_REG(hw, E1000_SEC);
903 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
904 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
905 stats->scc += E1000_READ_REG(hw, E1000_SCC);
906 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
908 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
909 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
910 stats->colc += E1000_READ_REG(hw, E1000_COLC);
911 stats->dc += E1000_READ_REG(hw, E1000_DC);
912 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
913 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
914 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
917 * For watchdog management we need to know if we have been
918 * paused during the last interval, so capture that here.
920 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
921 stats->xoffrxc += pause_frames;
922 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
923 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
924 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
925 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
926 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
927 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
928 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
929 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
930 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
931 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
932 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
933 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
936 * For the 64-bit byte counters the low dword must be read first.
937 * Both registers clear on the read of the high dword.
940 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
941 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
942 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
943 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
945 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
946 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
947 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
948 stats->roc += E1000_READ_REG(hw, E1000_ROC);
949 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
951 stats->tor += E1000_READ_REG(hw, E1000_TORH);
952 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
954 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
955 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
956 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
957 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
958 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
959 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
960 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
961 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
962 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
963 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
965 /* Interrupt Counts */
967 if (hw->mac.type >= e1000_82571) {
968 stats->iac += E1000_READ_REG(hw, E1000_IAC);
969 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
970 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
971 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
972 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
973 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
974 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
975 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
976 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
979 if (hw->mac.type >= e1000_82543) {
980 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
981 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
982 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
983 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
984 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
985 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
988 if (rte_stats == NULL)
992 rte_stats->imissed = stats->mpc;
993 rte_stats->ierrors = stats->crcerrs +
994 stats->rlec + stats->ruc + stats->roc +
995 stats->rxerrc + stats->algnerrc + stats->cexterr;
998 rte_stats->oerrors = stats->ecol + stats->latecol;
1000 rte_stats->ipackets = stats->gprc;
1001 rte_stats->opackets = stats->gptc;
1002 rte_stats->ibytes = stats->gorc;
1003 rte_stats->obytes = stats->gotc;
1008 eth_em_stats_reset(struct rte_eth_dev *dev)
1010 struct e1000_hw_stats *hw_stats =
1011 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1013 /* HW registers are cleared on read */
1014 eth_em_stats_get(dev, NULL);
1016 /* Reset software totals */
1017 memset(hw_stats, 0, sizeof(*hw_stats));
1021 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1023 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1025 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1027 em_rxq_intr_enable(hw);
1028 rte_intr_enable(intr_handle);
1034 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1036 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038 em_rxq_intr_disable(hw);
1044 em_get_max_pktlen(struct rte_eth_dev *dev)
1046 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1048 switch (hw->mac.type) {
1052 case e1000_ich10lan:
1058 case e1000_80003es2lan: /* 9K Jumbo Frame size */
1063 /* Adapters that do not support jumbo frames */
1065 return ETHER_MAX_LEN;
1067 return MAX_JUMBO_FRAME_SIZE;
1072 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1074 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1076 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1077 dev_info->max_rx_pktlen = em_get_max_pktlen(dev);
1078 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1081 * Starting with 631xESB hw supports 2 TX/RX queues per port.
1082 * Unfortunatelly, all these nics have just one TX context.
1083 * So we have few choises for TX:
1084 * - Use just one TX queue.
1085 * - Allow cksum offload only for one TX queue.
1086 * - Don't allow TX cksum offload at all.
1087 * For now, option #1 was chosen.
1088 * To use second RX queue we have to use extended RX descriptor
1089 * (Multiple Receive Queues are mutually exclusive with UDP
1090 * fragmentation and are not supported when a legacy receive
1091 * descriptor format is used).
1092 * Which means separate RX routinies - as legacy nics (82540, 82545)
1093 * don't support extended RXD.
1094 * To avoid it we support just one RX queue for now (no RSS).
1097 dev_info->max_rx_queues = 1;
1098 dev_info->max_tx_queues = 1;
1100 dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(dev);
1101 dev_info->rx_offload_capa = em_get_rx_port_offloads_capa(dev) |
1102 dev_info->rx_queue_offload_capa;
1103 dev_info->tx_queue_offload_capa = em_get_tx_queue_offloads_capa(dev);
1104 dev_info->tx_offload_capa = em_get_tx_port_offloads_capa(dev) |
1105 dev_info->tx_queue_offload_capa;
1107 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1108 .nb_max = E1000_MAX_RING_DESC,
1109 .nb_min = E1000_MIN_RING_DESC,
1110 .nb_align = EM_RXD_ALIGN,
1113 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1114 .nb_max = E1000_MAX_RING_DESC,
1115 .nb_min = E1000_MIN_RING_DESC,
1116 .nb_align = EM_TXD_ALIGN,
1117 .nb_seg_max = EM_TX_MAX_SEG,
1118 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1121 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1122 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1126 /* return 0 means link status changed, -1 means not changed */
1128 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1130 struct e1000_hw *hw =
1131 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1132 struct rte_eth_link link;
1133 int link_check, count;
1136 hw->mac.get_link_status = 1;
1138 /* possible wait-to-complete in up to 9 seconds */
1139 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1140 /* Read the real link status */
1141 switch (hw->phy.media_type) {
1142 case e1000_media_type_copper:
1143 /* Do the work to read phy */
1144 e1000_check_for_link(hw);
1145 link_check = !hw->mac.get_link_status;
1148 case e1000_media_type_fiber:
1149 e1000_check_for_link(hw);
1150 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1154 case e1000_media_type_internal_serdes:
1155 e1000_check_for_link(hw);
1156 link_check = hw->mac.serdes_has_link;
1162 if (link_check || wait_to_complete == 0)
1164 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1166 memset(&link, 0, sizeof(link));
1168 /* Now we check if a transition has happened */
1169 if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1170 uint16_t duplex, speed;
1171 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1172 link.link_duplex = (duplex == FULL_DUPLEX) ?
1173 ETH_LINK_FULL_DUPLEX :
1174 ETH_LINK_HALF_DUPLEX;
1175 link.link_speed = speed;
1176 link.link_status = ETH_LINK_UP;
1177 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1178 ETH_LINK_SPEED_FIXED);
1179 } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1180 link.link_speed = 0;
1181 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1182 link.link_status = ETH_LINK_DOWN;
1183 link.link_autoneg = ETH_LINK_FIXED;
1186 return rte_eth_linkstatus_set(dev, &link);
1190 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1191 * For ASF and Pass Through versions of f/w this means
1192 * that the driver is loaded. For AMT version type f/w
1193 * this means that the network i/f is open.
1196 em_hw_control_acquire(struct e1000_hw *hw)
1198 uint32_t ctrl_ext, swsm;
1200 /* Let firmware know the driver has taken over */
1201 if (hw->mac.type == e1000_82573) {
1202 swsm = E1000_READ_REG(hw, E1000_SWSM);
1203 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1206 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1207 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1208 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1213 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1214 * For ASF and Pass Through versions of f/w this means that the
1215 * driver is no longer loaded. For AMT versions of the
1216 * f/w this means that the network i/f is closed.
1219 em_hw_control_release(struct e1000_hw *hw)
1221 uint32_t ctrl_ext, swsm;
1223 /* Let firmware taken over control of h/w */
1224 if (hw->mac.type == e1000_82573) {
1225 swsm = E1000_READ_REG(hw, E1000_SWSM);
1226 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1228 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1229 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1230 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1235 * Bit of a misnomer, what this really means is
1236 * to enable OS management of the system... aka
1237 * to disable special hardware management features.
1240 em_init_manageability(struct e1000_hw *hw)
1242 if (e1000_enable_mng_pass_thru(hw)) {
1243 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1244 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1246 /* disable hardware interception of ARP */
1247 manc &= ~(E1000_MANC_ARP_EN);
1249 /* enable receiving management packets to the host */
1250 manc |= E1000_MANC_EN_MNG2HOST;
1251 manc2h |= 1 << 5; /* Mng Port 623 */
1252 manc2h |= 1 << 6; /* Mng Port 664 */
1253 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1254 E1000_WRITE_REG(hw, E1000_MANC, manc);
1259 * Give control back to hardware management
1260 * controller if there is one.
1263 em_release_manageability(struct e1000_hw *hw)
1267 if (e1000_enable_mng_pass_thru(hw)) {
1268 manc = E1000_READ_REG(hw, E1000_MANC);
1270 /* re-enable hardware interception of ARP */
1271 manc |= E1000_MANC_ARP_EN;
1272 manc &= ~E1000_MANC_EN_MNG2HOST;
1274 E1000_WRITE_REG(hw, E1000_MANC, manc);
1279 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1281 struct e1000_hw *hw =
1282 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285 rctl = E1000_READ_REG(hw, E1000_RCTL);
1286 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1287 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1291 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1293 struct e1000_hw *hw =
1294 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1297 rctl = E1000_READ_REG(hw, E1000_RCTL);
1298 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1299 if (dev->data->all_multicast == 1)
1300 rctl |= E1000_RCTL_MPE;
1302 rctl &= (~E1000_RCTL_MPE);
1303 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1307 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1309 struct e1000_hw *hw =
1310 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1313 rctl = E1000_READ_REG(hw, E1000_RCTL);
1314 rctl |= E1000_RCTL_MPE;
1315 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1319 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1321 struct e1000_hw *hw =
1322 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1325 if (dev->data->promiscuous == 1)
1326 return; /* must remain in all_multicast mode */
1327 rctl = E1000_READ_REG(hw, E1000_RCTL);
1328 rctl &= (~E1000_RCTL_MPE);
1329 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1333 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1335 struct e1000_hw *hw =
1336 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1337 struct e1000_vfta * shadow_vfta =
1338 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1343 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1344 E1000_VFTA_ENTRY_MASK);
1345 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1346 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1351 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1353 /* update local VFTA copy */
1354 shadow_vfta->vfta[vid_idx] = vfta;
1360 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1362 struct e1000_hw *hw =
1363 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1366 /* Filter Table Disable */
1367 reg = E1000_READ_REG(hw, E1000_RCTL);
1368 reg &= ~E1000_RCTL_CFIEN;
1369 reg &= ~E1000_RCTL_VFE;
1370 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1374 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1376 struct e1000_hw *hw =
1377 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378 struct e1000_vfta * shadow_vfta =
1379 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1383 /* Filter Table Enable, CFI not used for packet acceptance */
1384 reg = E1000_READ_REG(hw, E1000_RCTL);
1385 reg &= ~E1000_RCTL_CFIEN;
1386 reg |= E1000_RCTL_VFE;
1387 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1389 /* restore vfta from local copy */
1390 for (i = 0; i < IGB_VFTA_SIZE; i++)
1391 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1395 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1397 struct e1000_hw *hw =
1398 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1401 /* VLAN Mode Disable */
1402 reg = E1000_READ_REG(hw, E1000_CTRL);
1403 reg &= ~E1000_CTRL_VME;
1404 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1409 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1411 struct e1000_hw *hw =
1412 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1415 /* VLAN Mode Enable */
1416 reg = E1000_READ_REG(hw, E1000_CTRL);
1417 reg |= E1000_CTRL_VME;
1418 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1422 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1424 struct rte_eth_rxmode *rxmode;
1426 rxmode = &dev->data->dev_conf.rxmode;
1427 if(mask & ETH_VLAN_STRIP_MASK){
1428 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1429 em_vlan_hw_strip_enable(dev);
1431 em_vlan_hw_strip_disable(dev);
1434 if(mask & ETH_VLAN_FILTER_MASK){
1435 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1436 em_vlan_hw_filter_enable(dev);
1438 em_vlan_hw_filter_disable(dev);
1445 * It enables the interrupt mask and then enable the interrupt.
1448 * Pointer to struct rte_eth_dev.
1451 * - On success, zero.
1452 * - On failure, a negative value.
1455 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1458 struct e1000_hw *hw =
1459 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461 /* clear interrupt */
1462 E1000_READ_REG(hw, E1000_ICR);
1463 regval = E1000_READ_REG(hw, E1000_IMS);
1464 E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1469 * It clears the interrupt causes and enables the interrupt.
1470 * It will be called once only during nic initialized.
1473 * Pointer to struct rte_eth_dev.
1476 * - On success, zero.
1477 * - On failure, a negative value.
1480 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1482 struct e1000_hw *hw =
1483 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1485 E1000_READ_REG(hw, E1000_ICR);
1486 em_rxq_intr_enable(hw);
1491 * It enable receive packet interrupt.
1493 * Pointer to struct e1000_hw
1498 em_rxq_intr_enable(struct e1000_hw *hw)
1500 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1501 E1000_WRITE_FLUSH(hw);
1505 * It disabled lsc interrupt.
1507 * Pointer to struct e1000_hw
1512 em_lsc_intr_disable(struct e1000_hw *hw)
1514 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1515 E1000_WRITE_FLUSH(hw);
1519 * It disabled receive packet interrupt.
1521 * Pointer to struct e1000_hw
1526 em_rxq_intr_disable(struct e1000_hw *hw)
1528 E1000_READ_REG(hw, E1000_ICR);
1529 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1530 E1000_WRITE_FLUSH(hw);
1534 * It reads ICR and gets interrupt causes, check it and set a bit flag
1535 * to update link status.
1538 * Pointer to struct rte_eth_dev.
1541 * - On success, zero.
1542 * - On failure, a negative value.
1545 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1548 struct e1000_hw *hw =
1549 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1550 struct e1000_interrupt *intr =
1551 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1553 /* read-on-clear nic registers here */
1554 icr = E1000_READ_REG(hw, E1000_ICR);
1555 if (icr & E1000_ICR_LSC) {
1556 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1563 * It executes link_update after knowing an interrupt is prsent.
1566 * Pointer to struct rte_eth_dev.
1569 * - On success, zero.
1570 * - On failure, a negative value.
1573 eth_em_interrupt_action(struct rte_eth_dev *dev,
1574 struct rte_intr_handle *intr_handle)
1576 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1577 struct e1000_hw *hw =
1578 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1579 struct e1000_interrupt *intr =
1580 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1581 struct rte_eth_link link;
1584 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1587 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1588 rte_intr_enable(intr_handle);
1590 /* set get_link_status to check register later */
1591 hw->mac.get_link_status = 1;
1592 ret = eth_em_link_update(dev, 0);
1594 /* check if link has changed */
1598 rte_eth_linkstatus_get(dev, &link);
1600 if (link.link_status) {
1601 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1602 dev->data->port_id, link.link_speed,
1603 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1604 "full-duplex" : "half-duplex");
1606 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1608 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1609 pci_dev->addr.domain, pci_dev->addr.bus,
1610 pci_dev->addr.devid, pci_dev->addr.function);
1616 * Interrupt handler which shall be registered at first.
1619 * Pointer to interrupt handle.
1621 * The address of parameter (struct rte_eth_dev *) regsitered before.
1627 eth_em_interrupt_handler(void *param)
1629 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1631 eth_em_interrupt_get_status(dev);
1632 eth_em_interrupt_action(dev, dev->intr_handle);
1633 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1637 eth_em_led_on(struct rte_eth_dev *dev)
1639 struct e1000_hw *hw;
1641 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1642 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1646 eth_em_led_off(struct rte_eth_dev *dev)
1648 struct e1000_hw *hw;
1650 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1651 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1655 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1657 struct e1000_hw *hw;
1662 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663 fc_conf->pause_time = hw->fc.pause_time;
1664 fc_conf->high_water = hw->fc.high_water;
1665 fc_conf->low_water = hw->fc.low_water;
1666 fc_conf->send_xon = hw->fc.send_xon;
1667 fc_conf->autoneg = hw->mac.autoneg;
1670 * Return rx_pause and tx_pause status according to actual setting of
1671 * the TFCE and RFCE bits in the CTRL register.
1673 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1674 if (ctrl & E1000_CTRL_TFCE)
1679 if (ctrl & E1000_CTRL_RFCE)
1684 if (rx_pause && tx_pause)
1685 fc_conf->mode = RTE_FC_FULL;
1687 fc_conf->mode = RTE_FC_RX_PAUSE;
1689 fc_conf->mode = RTE_FC_TX_PAUSE;
1691 fc_conf->mode = RTE_FC_NONE;
1697 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1699 struct e1000_hw *hw;
1701 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1707 uint32_t rx_buf_size;
1708 uint32_t max_high_water;
1711 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1712 if (fc_conf->autoneg != hw->mac.autoneg)
1714 rx_buf_size = em_get_rx_buffer_size(hw);
1715 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1717 /* At least reserve one Ethernet frame for watermark */
1718 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1719 if ((fc_conf->high_water > max_high_water) ||
1720 (fc_conf->high_water < fc_conf->low_water)) {
1721 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1722 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1726 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1727 hw->fc.pause_time = fc_conf->pause_time;
1728 hw->fc.high_water = fc_conf->high_water;
1729 hw->fc.low_water = fc_conf->low_water;
1730 hw->fc.send_xon = fc_conf->send_xon;
1732 err = e1000_setup_link_generic(hw);
1733 if (err == E1000_SUCCESS) {
1735 /* check if we want to forward MAC frames - driver doesn't have native
1736 * capability to do that, so we'll write the registers ourselves */
1738 rctl = E1000_READ_REG(hw, E1000_RCTL);
1740 /* set or clear MFLCN.PMCF bit depending on configuration */
1741 if (fc_conf->mac_ctrl_frame_fwd != 0)
1742 rctl |= E1000_RCTL_PMCF;
1744 rctl &= ~E1000_RCTL_PMCF;
1746 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1747 E1000_WRITE_FLUSH(hw);
1752 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1757 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1758 uint32_t index, __rte_unused uint32_t pool)
1760 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1762 return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1766 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1768 uint8_t addr[ETHER_ADDR_LEN];
1769 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1771 memset(addr, 0, sizeof(addr));
1773 e1000_rar_set(hw, addr, index);
1777 eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
1778 struct ether_addr *addr)
1780 eth_em_rar_clear(dev, 0);
1782 eth_em_rar_set(dev, (void *)addr, 0, 0);
1786 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1788 struct rte_eth_dev_info dev_info;
1789 struct e1000_hw *hw;
1790 uint32_t frame_size;
1793 eth_em_infos_get(dev, &dev_info);
1794 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1796 /* check that mtu is within the allowed range */
1797 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1800 /* refuse mtu that requires the support of scattered packets when this
1801 * feature has not been enabled before. */
1802 if (!dev->data->scattered_rx &&
1803 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1806 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1807 rctl = E1000_READ_REG(hw, E1000_RCTL);
1809 /* switch to jumbo mode if needed */
1810 if (frame_size > ETHER_MAX_LEN) {
1811 dev->data->dev_conf.rxmode.offloads |=
1812 DEV_RX_OFFLOAD_JUMBO_FRAME;
1813 rctl |= E1000_RCTL_LPE;
1815 dev->data->dev_conf.rxmode.offloads &=
1816 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1817 rctl &= ~E1000_RCTL_LPE;
1819 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1821 /* update max frame size */
1822 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1827 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1828 struct ether_addr *mc_addr_set,
1829 uint32_t nb_mc_addr)
1831 struct e1000_hw *hw;
1833 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1834 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1838 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1839 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1840 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1842 RTE_INIT(e1000_init_log);
1844 e1000_init_log(void)
1846 e1000_logtype_init = rte_log_register("pmd.net.e1000.init");
1847 if (e1000_logtype_init >= 0)
1848 rte_log_set_level(e1000_logtype_init, RTE_LOG_NOTICE);
1849 e1000_logtype_driver = rte_log_register("pmd.net.e1000.driver");
1850 if (e1000_logtype_driver >= 0)
1851 rte_log_set_level(e1000_logtype_driver, RTE_LOG_NOTICE);