1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_common.h>
12 #include <rte_interrupts.h>
13 #include <rte_byteorder.h>
15 #include <rte_debug.h>
17 #include <rte_bus_pci.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_memory.h>
23 #include <rte_atomic.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 #define IGB_HKEY_MAX_INDEX 10
47 /* Bit shift and mask */
48 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
49 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
50 #define IGB_8_BIT_WIDTH CHAR_BIT
51 #define IGB_8_BIT_MASK UINT8_MAX
53 /* Additional timesync values. */
54 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
55 #define E1000_ETQF_FILTER_1588 3
56 #define IGB_82576_TSYNC_SHIFT 16
57 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
58 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
59 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
61 #define E1000_VTIVAR_MISC 0x01740
62 #define E1000_VTIVAR_MISC_MASK 0xFF
63 #define E1000_VTIVAR_VALID 0x80
64 #define E1000_VTIVAR_MISC_MAILBOX 0
65 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
67 /* External VLAN Enable bit mask */
68 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
70 /* External VLAN Ether Type bit mask and shift */
71 #define E1000_VET_VET_EXT 0xFFFF0000
72 #define E1000_VET_VET_EXT_SHIFT 16
74 static int eth_igb_configure(struct rte_eth_dev *dev);
75 static int eth_igb_start(struct rte_eth_dev *dev);
76 static void eth_igb_stop(struct rte_eth_dev *dev);
77 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
79 static void eth_igb_close(struct rte_eth_dev *dev);
80 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
81 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
82 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
83 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
84 static int eth_igb_link_update(struct rte_eth_dev *dev,
85 int wait_to_complete);
86 static int eth_igb_stats_get(struct rte_eth_dev *dev,
87 struct rte_eth_stats *rte_stats);
88 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
89 struct rte_eth_xstat *xstats, unsigned n);
90 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
92 uint64_t *values, unsigned int n);
93 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
94 struct rte_eth_xstat_name *xstats_names,
96 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
97 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
99 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
100 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
101 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
102 char *fw_version, size_t fw_size);
103 static void eth_igb_infos_get(struct rte_eth_dev *dev,
104 struct rte_eth_dev_info *dev_info);
105 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
106 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
107 struct rte_eth_dev_info *dev_info);
108 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
109 struct rte_eth_fc_conf *fc_conf);
110 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
113 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
114 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
115 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
116 struct rte_intr_handle *handle);
117 static void eth_igb_interrupt_handler(void *param);
118 static int igb_hardware_init(struct e1000_hw *hw);
119 static void igb_hw_control_acquire(struct e1000_hw *hw);
120 static void igb_hw_control_release(struct e1000_hw *hw);
121 static void igb_init_manageability(struct e1000_hw *hw);
122 static void igb_release_manageability(struct e1000_hw *hw);
124 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
126 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
127 uint16_t vlan_id, int on);
128 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
129 enum rte_vlan_type vlan_type,
131 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
133 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
134 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
135 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
140 static int eth_igb_led_on(struct rte_eth_dev *dev);
141 static int eth_igb_led_off(struct rte_eth_dev *dev);
143 static void igb_intr_disable(struct e1000_hw *hw);
144 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
145 static int eth_igb_rar_set(struct rte_eth_dev *dev,
146 struct ether_addr *mac_addr,
147 uint32_t index, uint32_t pool);
148 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
149 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
150 struct ether_addr *addr);
152 static void igbvf_intr_disable(struct e1000_hw *hw);
153 static int igbvf_dev_configure(struct rte_eth_dev *dev);
154 static int igbvf_dev_start(struct rte_eth_dev *dev);
155 static void igbvf_dev_stop(struct rte_eth_dev *dev);
156 static void igbvf_dev_close(struct rte_eth_dev *dev);
157 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
158 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
159 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
160 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
161 static int eth_igbvf_link_update(struct e1000_hw *hw);
162 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
163 struct rte_eth_stats *rte_stats);
164 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
165 struct rte_eth_xstat *xstats, unsigned n);
166 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
167 struct rte_eth_xstat_name *xstats_names,
169 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
170 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
171 uint16_t vlan_id, int on);
172 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
173 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
174 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
175 struct ether_addr *addr);
176 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
177 static int igbvf_get_regs(struct rte_eth_dev *dev,
178 struct rte_dev_reg_info *regs);
180 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
181 struct rte_eth_rss_reta_entry64 *reta_conf,
183 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
184 struct rte_eth_rss_reta_entry64 *reta_conf,
187 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
188 struct rte_eth_syn_filter *filter);
189 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
190 enum rte_filter_op filter_op,
192 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
193 struct rte_eth_ntuple_filter *ntuple_filter);
194 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
195 struct rte_eth_ntuple_filter *ntuple_filter);
196 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
197 struct rte_eth_flex_filter *filter);
198 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
199 enum rte_filter_op filter_op,
201 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
202 struct rte_eth_ntuple_filter *ntuple_filter);
203 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
204 struct rte_eth_ntuple_filter *ntuple_filter);
205 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
206 struct rte_eth_ntuple_filter *filter);
207 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
208 enum rte_filter_op filter_op,
210 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
211 enum rte_filter_op filter_op,
213 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
214 struct rte_eth_ethertype_filter *filter);
215 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
216 enum rte_filter_type filter_type,
217 enum rte_filter_op filter_op,
219 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
220 static int eth_igb_get_regs(struct rte_eth_dev *dev,
221 struct rte_dev_reg_info *regs);
222 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
223 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
224 struct rte_dev_eeprom_info *eeprom);
225 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
226 struct rte_dev_eeprom_info *eeprom);
227 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
228 struct ether_addr *mc_addr_set,
229 uint32_t nb_mc_addr);
230 static int igb_timesync_enable(struct rte_eth_dev *dev);
231 static int igb_timesync_disable(struct rte_eth_dev *dev);
232 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
233 struct timespec *timestamp,
235 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
236 struct timespec *timestamp);
237 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
238 static int igb_timesync_read_time(struct rte_eth_dev *dev,
239 struct timespec *timestamp);
240 static int igb_timesync_write_time(struct rte_eth_dev *dev,
241 const struct timespec *timestamp);
242 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
244 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
246 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
247 uint8_t queue, uint8_t msix_vector);
248 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
249 uint8_t index, uint8_t offset);
250 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
251 static void eth_igbvf_interrupt_handler(void *param);
252 static void igbvf_mbx_process(struct rte_eth_dev *dev);
253 static int igb_filter_restore(struct rte_eth_dev *dev);
256 * Define VF Stats MACRO for Non "cleared on read" register
258 #define UPDATE_VF_STAT(reg, last, cur) \
260 u32 latest = E1000_READ_REG(hw, reg); \
261 cur += (latest - last) & UINT_MAX; \
265 #define IGB_FC_PAUSE_TIME 0x0680
266 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
267 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
269 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
271 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
274 * The set of PCI devices this driver supports
276 static const struct rte_pci_id pci_id_igb_map[] = {
277 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
278 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
279 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
280 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
281 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
282 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
291 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
295 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
302 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
304 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
305 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
318 { .vendor_id = 0, /* sentinel */ },
322 * The set of PCI devices this driver supports (for 82576&I350 VF)
324 static const struct rte_pci_id pci_id_igbvf_map[] = {
325 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
326 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
328 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
329 { .vendor_id = 0, /* sentinel */ },
332 static const struct rte_eth_desc_lim rx_desc_lim = {
333 .nb_max = E1000_MAX_RING_DESC,
334 .nb_min = E1000_MIN_RING_DESC,
335 .nb_align = IGB_RXD_ALIGN,
338 static const struct rte_eth_desc_lim tx_desc_lim = {
339 .nb_max = E1000_MAX_RING_DESC,
340 .nb_min = E1000_MIN_RING_DESC,
341 .nb_align = IGB_RXD_ALIGN,
342 .nb_seg_max = IGB_TX_MAX_SEG,
343 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
346 static const struct eth_dev_ops eth_igb_ops = {
347 .dev_configure = eth_igb_configure,
348 .dev_start = eth_igb_start,
349 .dev_stop = eth_igb_stop,
350 .dev_set_link_up = eth_igb_dev_set_link_up,
351 .dev_set_link_down = eth_igb_dev_set_link_down,
352 .dev_close = eth_igb_close,
353 .promiscuous_enable = eth_igb_promiscuous_enable,
354 .promiscuous_disable = eth_igb_promiscuous_disable,
355 .allmulticast_enable = eth_igb_allmulticast_enable,
356 .allmulticast_disable = eth_igb_allmulticast_disable,
357 .link_update = eth_igb_link_update,
358 .stats_get = eth_igb_stats_get,
359 .xstats_get = eth_igb_xstats_get,
360 .xstats_get_by_id = eth_igb_xstats_get_by_id,
361 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
362 .xstats_get_names = eth_igb_xstats_get_names,
363 .stats_reset = eth_igb_stats_reset,
364 .xstats_reset = eth_igb_xstats_reset,
365 .fw_version_get = eth_igb_fw_version_get,
366 .dev_infos_get = eth_igb_infos_get,
367 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
368 .mtu_set = eth_igb_mtu_set,
369 .vlan_filter_set = eth_igb_vlan_filter_set,
370 .vlan_tpid_set = eth_igb_vlan_tpid_set,
371 .vlan_offload_set = eth_igb_vlan_offload_set,
372 .rx_queue_setup = eth_igb_rx_queue_setup,
373 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
374 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
375 .rx_queue_release = eth_igb_rx_queue_release,
376 .rx_queue_count = eth_igb_rx_queue_count,
377 .rx_descriptor_done = eth_igb_rx_descriptor_done,
378 .rx_descriptor_status = eth_igb_rx_descriptor_status,
379 .tx_descriptor_status = eth_igb_tx_descriptor_status,
380 .tx_queue_setup = eth_igb_tx_queue_setup,
381 .tx_queue_release = eth_igb_tx_queue_release,
382 .tx_done_cleanup = eth_igb_tx_done_cleanup,
383 .dev_led_on = eth_igb_led_on,
384 .dev_led_off = eth_igb_led_off,
385 .flow_ctrl_get = eth_igb_flow_ctrl_get,
386 .flow_ctrl_set = eth_igb_flow_ctrl_set,
387 .mac_addr_add = eth_igb_rar_set,
388 .mac_addr_remove = eth_igb_rar_clear,
389 .mac_addr_set = eth_igb_default_mac_addr_set,
390 .reta_update = eth_igb_rss_reta_update,
391 .reta_query = eth_igb_rss_reta_query,
392 .rss_hash_update = eth_igb_rss_hash_update,
393 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
394 .filter_ctrl = eth_igb_filter_ctrl,
395 .set_mc_addr_list = eth_igb_set_mc_addr_list,
396 .rxq_info_get = igb_rxq_info_get,
397 .txq_info_get = igb_txq_info_get,
398 .timesync_enable = igb_timesync_enable,
399 .timesync_disable = igb_timesync_disable,
400 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
401 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
402 .get_reg = eth_igb_get_regs,
403 .get_eeprom_length = eth_igb_get_eeprom_length,
404 .get_eeprom = eth_igb_get_eeprom,
405 .set_eeprom = eth_igb_set_eeprom,
406 .timesync_adjust_time = igb_timesync_adjust_time,
407 .timesync_read_time = igb_timesync_read_time,
408 .timesync_write_time = igb_timesync_write_time,
412 * dev_ops for virtual function, bare necessities for basic vf
413 * operation have been implemented
415 static const struct eth_dev_ops igbvf_eth_dev_ops = {
416 .dev_configure = igbvf_dev_configure,
417 .dev_start = igbvf_dev_start,
418 .dev_stop = igbvf_dev_stop,
419 .dev_close = igbvf_dev_close,
420 .promiscuous_enable = igbvf_promiscuous_enable,
421 .promiscuous_disable = igbvf_promiscuous_disable,
422 .allmulticast_enable = igbvf_allmulticast_enable,
423 .allmulticast_disable = igbvf_allmulticast_disable,
424 .link_update = eth_igb_link_update,
425 .stats_get = eth_igbvf_stats_get,
426 .xstats_get = eth_igbvf_xstats_get,
427 .xstats_get_names = eth_igbvf_xstats_get_names,
428 .stats_reset = eth_igbvf_stats_reset,
429 .xstats_reset = eth_igbvf_stats_reset,
430 .vlan_filter_set = igbvf_vlan_filter_set,
431 .dev_infos_get = eth_igbvf_infos_get,
432 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
433 .rx_queue_setup = eth_igb_rx_queue_setup,
434 .rx_queue_release = eth_igb_rx_queue_release,
435 .tx_queue_setup = eth_igb_tx_queue_setup,
436 .tx_queue_release = eth_igb_tx_queue_release,
437 .set_mc_addr_list = eth_igb_set_mc_addr_list,
438 .rxq_info_get = igb_rxq_info_get,
439 .txq_info_get = igb_txq_info_get,
440 .mac_addr_set = igbvf_default_mac_addr_set,
441 .get_reg = igbvf_get_regs,
444 /* store statistics names and its offset in stats structure */
445 struct rte_igb_xstats_name_off {
446 char name[RTE_ETH_XSTATS_NAME_SIZE];
450 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
451 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
452 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
453 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
454 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
455 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
456 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
457 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
459 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
460 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
461 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
462 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
463 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
464 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
465 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
466 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
467 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
468 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
469 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
471 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
472 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
473 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
474 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
475 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
477 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
479 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
480 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
481 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
482 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
483 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
484 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
485 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
486 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
487 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
488 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
489 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
490 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
491 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
492 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
493 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
494 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
495 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
496 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
498 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
500 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
501 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
502 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
503 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
504 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
505 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
506 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
508 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
511 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
512 sizeof(rte_igb_stats_strings[0]))
514 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
515 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
516 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
517 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
518 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
519 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
522 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
523 sizeof(rte_igbvf_stats_strings[0]))
526 * Atomically reads the link status information from global
527 * structure rte_eth_dev.
530 * - Pointer to the structure rte_eth_dev to read from.
531 * - Pointer to the buffer to be saved with the link status.
534 * - On success, zero.
535 * - On failure, negative value.
538 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
539 struct rte_eth_link *link)
541 struct rte_eth_link *dst = link;
542 struct rte_eth_link *src = &(dev->data->dev_link);
544 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
545 *(uint64_t *)src) == 0)
552 * Atomically writes the link status information into global
553 * structure rte_eth_dev.
556 * - Pointer to the structure rte_eth_dev to read from.
557 * - Pointer to the buffer to be saved with the link status.
560 * - On success, zero.
561 * - On failure, negative value.
564 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
565 struct rte_eth_link *link)
567 struct rte_eth_link *dst = &(dev->data->dev_link);
568 struct rte_eth_link *src = link;
570 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
571 *(uint64_t *)src) == 0)
578 igb_intr_enable(struct rte_eth_dev *dev)
580 struct e1000_interrupt *intr =
581 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
582 struct e1000_hw *hw =
583 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
585 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
586 E1000_WRITE_FLUSH(hw);
590 igb_intr_disable(struct e1000_hw *hw)
592 E1000_WRITE_REG(hw, E1000_IMC, ~0);
593 E1000_WRITE_FLUSH(hw);
597 igbvf_intr_enable(struct rte_eth_dev *dev)
599 struct e1000_hw *hw =
600 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
602 /* only for mailbox */
603 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
604 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
605 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
606 E1000_WRITE_FLUSH(hw);
609 /* only for mailbox now. If RX/TX needed, should extend this function. */
611 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
616 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
617 tmp |= E1000_VTIVAR_VALID;
618 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
622 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
624 struct e1000_hw *hw =
625 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
627 /* Configure VF other cause ivar */
628 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
631 static inline int32_t
632 igb_pf_reset_hw(struct e1000_hw *hw)
637 status = e1000_reset_hw(hw);
639 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
640 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
641 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
642 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
643 E1000_WRITE_FLUSH(hw);
649 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
651 struct e1000_hw *hw =
652 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
655 hw->vendor_id = pci_dev->id.vendor_id;
656 hw->device_id = pci_dev->id.device_id;
657 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
658 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
660 e1000_set_mac_type(hw);
662 /* need to check if it is a vf device below */
666 igb_reset_swfw_lock(struct e1000_hw *hw)
671 * Do mac ops initialization manually here, since we will need
672 * some function pointers set by this call.
674 ret_val = e1000_init_mac_params(hw);
679 * SMBI lock should not fail in this early stage. If this is the case,
680 * it is due to an improper exit of the application.
681 * So force the release of the faulty lock.
683 if (e1000_get_hw_semaphore_generic(hw) < 0) {
684 PMD_DRV_LOG(DEBUG, "SMBI lock released");
686 e1000_put_hw_semaphore_generic(hw);
688 if (hw->mac.ops.acquire_swfw_sync != NULL) {
692 * Phy lock should not fail in this early stage. If this is the case,
693 * it is due to an improper exit of the application.
694 * So force the release of the faulty lock.
696 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
697 if (hw->bus.func > E1000_FUNC_1)
699 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
700 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
703 hw->mac.ops.release_swfw_sync(hw, mask);
706 * This one is more tricky since it is common to all ports; but
707 * swfw_sync retries last long enough (1s) to be almost sure that if
708 * lock can not be taken it is due to an improper lock of the
711 mask = E1000_SWFW_EEP_SM;
712 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
713 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
715 hw->mac.ops.release_swfw_sync(hw, mask);
718 return E1000_SUCCESS;
721 /* Remove all ntuple filters of the device */
722 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
724 struct e1000_filter_info *filter_info =
725 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
726 struct e1000_5tuple_filter *p_5tuple;
727 struct e1000_2tuple_filter *p_2tuple;
729 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
730 TAILQ_REMOVE(&filter_info->fivetuple_list,
734 filter_info->fivetuple_mask = 0;
735 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
736 TAILQ_REMOVE(&filter_info->twotuple_list,
740 filter_info->twotuple_mask = 0;
745 /* Remove all flex filters of the device */
746 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
748 struct e1000_filter_info *filter_info =
749 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
750 struct e1000_flex_filter *p_flex;
752 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
753 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
756 filter_info->flex_mask = 0;
762 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
765 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
766 struct e1000_hw *hw =
767 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
768 struct e1000_vfta * shadow_vfta =
769 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
770 struct e1000_filter_info *filter_info =
771 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
772 struct e1000_adapter *adapter =
773 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
777 eth_dev->dev_ops = ð_igb_ops;
778 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
779 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
780 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
782 /* for secondary processes, we don't initialise any further as primary
783 * has already done this work. Only check we don't need a different
785 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
786 if (eth_dev->data->scattered_rx)
787 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
791 rte_eth_copy_pci_info(eth_dev, pci_dev);
793 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
795 igb_identify_hardware(eth_dev, pci_dev);
796 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
801 e1000_get_bus_info(hw);
803 /* Reset any pending lock */
804 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
809 /* Finish initialization */
810 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
816 hw->phy.autoneg_wait_to_complete = 0;
817 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
820 if (hw->phy.media_type == e1000_media_type_copper) {
821 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
822 hw->phy.disable_polarity_correction = 0;
823 hw->phy.ms_type = e1000_ms_hw_default;
827 * Start from a known state, this is important in reading the nvm
832 /* Make sure we have a good EEPROM before we read from it */
833 if (e1000_validate_nvm_checksum(hw) < 0) {
835 * Some PCI-E parts fail the first check due to
836 * the link being in sleep state, call it again,
837 * if it fails a second time its a real issue.
839 if (e1000_validate_nvm_checksum(hw) < 0) {
840 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
846 /* Read the permanent MAC address out of the EEPROM */
847 if (e1000_read_mac_addr(hw) != 0) {
848 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
853 /* Allocate memory for storing MAC addresses */
854 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
855 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
856 if (eth_dev->data->mac_addrs == NULL) {
857 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
858 "store MAC addresses",
859 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
864 /* Copy the permanent MAC address */
865 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
867 /* initialize the vfta */
868 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
870 /* Now initialize the hardware */
871 if (igb_hardware_init(hw) != 0) {
872 PMD_INIT_LOG(ERR, "Hardware initialization failed");
873 rte_free(eth_dev->data->mac_addrs);
874 eth_dev->data->mac_addrs = NULL;
878 hw->mac.get_link_status = 1;
879 adapter->stopped = 0;
881 /* Indicate SOL/IDER usage */
882 if (e1000_check_reset_block(hw) < 0) {
883 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
887 /* initialize PF if max_vfs not zero */
888 igb_pf_host_init(eth_dev);
890 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
891 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
892 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
893 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
894 E1000_WRITE_FLUSH(hw);
896 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
897 eth_dev->data->port_id, pci_dev->id.vendor_id,
898 pci_dev->id.device_id);
900 rte_intr_callback_register(&pci_dev->intr_handle,
901 eth_igb_interrupt_handler,
904 /* enable uio/vfio intr/eventfd mapping */
905 rte_intr_enable(&pci_dev->intr_handle);
907 /* enable support intr */
908 igb_intr_enable(eth_dev);
910 /* initialize filter info */
911 memset(filter_info, 0,
912 sizeof(struct e1000_filter_info));
914 TAILQ_INIT(&filter_info->flex_list);
915 TAILQ_INIT(&filter_info->twotuple_list);
916 TAILQ_INIT(&filter_info->fivetuple_list);
918 TAILQ_INIT(&igb_filter_ntuple_list);
919 TAILQ_INIT(&igb_filter_ethertype_list);
920 TAILQ_INIT(&igb_filter_syn_list);
921 TAILQ_INIT(&igb_filter_flex_list);
922 TAILQ_INIT(&igb_filter_rss_list);
923 TAILQ_INIT(&igb_flow_list);
928 igb_hw_control_release(hw);
934 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
936 struct rte_pci_device *pci_dev;
937 struct rte_intr_handle *intr_handle;
939 struct e1000_adapter *adapter =
940 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
941 struct e1000_filter_info *filter_info =
942 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
944 PMD_INIT_FUNC_TRACE();
946 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
949 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
950 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
951 intr_handle = &pci_dev->intr_handle;
953 if (adapter->stopped == 0)
954 eth_igb_close(eth_dev);
956 eth_dev->dev_ops = NULL;
957 eth_dev->rx_pkt_burst = NULL;
958 eth_dev->tx_pkt_burst = NULL;
960 /* Reset any pending lock */
961 igb_reset_swfw_lock(hw);
963 rte_free(eth_dev->data->mac_addrs);
964 eth_dev->data->mac_addrs = NULL;
966 /* uninitialize PF if max_vfs not zero */
967 igb_pf_host_uninit(eth_dev);
969 /* disable uio intr before callback unregister */
970 rte_intr_disable(intr_handle);
971 rte_intr_callback_unregister(intr_handle,
972 eth_igb_interrupt_handler, eth_dev);
974 /* clear the SYN filter info */
975 filter_info->syn_info = 0;
977 /* clear the ethertype filters info */
978 filter_info->ethertype_mask = 0;
979 memset(filter_info->ethertype_filters, 0,
980 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
982 /* clear the rss filter info */
983 memset(&filter_info->rss_info, 0,
984 sizeof(struct igb_rte_flow_rss_conf));
986 /* remove all ntuple filters of the device */
987 igb_ntuple_filter_uninit(eth_dev);
989 /* remove all flex filters of the device */
990 igb_flex_filter_uninit(eth_dev);
992 /* clear all the filters list */
993 igb_filterlist_flush(eth_dev);
999 * Virtual Function device init
1002 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1004 struct rte_pci_device *pci_dev;
1005 struct rte_intr_handle *intr_handle;
1006 struct e1000_adapter *adapter =
1007 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1008 struct e1000_hw *hw =
1009 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1011 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1013 PMD_INIT_FUNC_TRACE();
1015 eth_dev->dev_ops = &igbvf_eth_dev_ops;
1016 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
1017 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
1018 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
1020 /* for secondary processes, we don't initialise any further as primary
1021 * has already done this work. Only check we don't need a different
1023 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1024 if (eth_dev->data->scattered_rx)
1025 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
1029 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1030 rte_eth_copy_pci_info(eth_dev, pci_dev);
1032 hw->device_id = pci_dev->id.device_id;
1033 hw->vendor_id = pci_dev->id.vendor_id;
1034 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1035 adapter->stopped = 0;
1037 /* Initialize the shared code (base driver) */
1038 diag = e1000_setup_init_funcs(hw, TRUE);
1040 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1045 /* init_mailbox_params */
1046 hw->mbx.ops.init_params(hw);
1048 /* Disable the interrupts for VF */
1049 igbvf_intr_disable(hw);
1051 diag = hw->mac.ops.reset_hw(hw);
1053 /* Allocate memory for storing MAC addresses */
1054 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1055 hw->mac.rar_entry_count, 0);
1056 if (eth_dev->data->mac_addrs == NULL) {
1058 "Failed to allocate %d bytes needed to store MAC "
1060 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1064 /* Generate a random MAC address, if none was assigned by PF. */
1065 if (is_zero_ether_addr(perm_addr)) {
1066 eth_random_addr(perm_addr->addr_bytes);
1067 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1068 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1069 "%02x:%02x:%02x:%02x:%02x:%02x",
1070 perm_addr->addr_bytes[0],
1071 perm_addr->addr_bytes[1],
1072 perm_addr->addr_bytes[2],
1073 perm_addr->addr_bytes[3],
1074 perm_addr->addr_bytes[4],
1075 perm_addr->addr_bytes[5]);
1078 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1080 rte_free(eth_dev->data->mac_addrs);
1081 eth_dev->data->mac_addrs = NULL;
1084 /* Copy the permanent MAC address */
1085 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1086 ð_dev->data->mac_addrs[0]);
1088 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1090 eth_dev->data->port_id, pci_dev->id.vendor_id,
1091 pci_dev->id.device_id, "igb_mac_82576_vf");
1093 intr_handle = &pci_dev->intr_handle;
1094 rte_intr_callback_register(intr_handle,
1095 eth_igbvf_interrupt_handler, eth_dev);
1101 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1103 struct e1000_adapter *adapter =
1104 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1105 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1107 PMD_INIT_FUNC_TRACE();
1109 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1112 if (adapter->stopped == 0)
1113 igbvf_dev_close(eth_dev);
1115 eth_dev->dev_ops = NULL;
1116 eth_dev->rx_pkt_burst = NULL;
1117 eth_dev->tx_pkt_burst = NULL;
1119 rte_free(eth_dev->data->mac_addrs);
1120 eth_dev->data->mac_addrs = NULL;
1122 /* disable uio intr before callback unregister */
1123 rte_intr_disable(&pci_dev->intr_handle);
1124 rte_intr_callback_unregister(&pci_dev->intr_handle,
1125 eth_igbvf_interrupt_handler,
1131 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1132 struct rte_pci_device *pci_dev)
1134 return rte_eth_dev_pci_generic_probe(pci_dev,
1135 sizeof(struct e1000_adapter), eth_igb_dev_init);
1138 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1140 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1143 static struct rte_pci_driver rte_igb_pmd = {
1144 .id_table = pci_id_igb_map,
1145 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1146 RTE_PCI_DRV_IOVA_AS_VA,
1147 .probe = eth_igb_pci_probe,
1148 .remove = eth_igb_pci_remove,
1152 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1153 struct rte_pci_device *pci_dev)
1155 return rte_eth_dev_pci_generic_probe(pci_dev,
1156 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1159 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1161 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1165 * virtual function driver struct
1167 static struct rte_pci_driver rte_igbvf_pmd = {
1168 .id_table = pci_id_igbvf_map,
1169 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1170 .probe = eth_igbvf_pci_probe,
1171 .remove = eth_igbvf_pci_remove,
1175 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1177 struct e1000_hw *hw =
1178 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1179 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1180 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1181 rctl |= E1000_RCTL_VFE;
1182 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1186 igb_check_mq_mode(struct rte_eth_dev *dev)
1188 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1189 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1190 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1191 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1193 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1194 tx_mq_mode == ETH_MQ_TX_DCB ||
1195 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1196 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1199 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1200 /* Check multi-queue mode.
1201 * To no break software we accept ETH_MQ_RX_NONE as this might
1202 * be used to turn off VLAN filter.
1205 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1206 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1207 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1208 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1210 /* Only support one queue on VFs.
1211 * RSS together with SRIOV is not supported.
1213 PMD_INIT_LOG(ERR, "SRIOV is active,"
1214 " wrong mq_mode rx %d.",
1218 /* TX mode is not used here, so mode might be ignored.*/
1219 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1220 /* SRIOV only works in VMDq enable mode */
1221 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1222 " TX mode %d is not supported. "
1223 " Driver will behave as %d mode.",
1224 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1227 /* check valid queue number */
1228 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1229 PMD_INIT_LOG(ERR, "SRIOV is active,"
1230 " only support one queue on VFs.");
1234 /* To no break software that set invalid mode, only display
1235 * warning if invalid mode is used.
1237 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1238 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1239 rx_mq_mode != ETH_MQ_RX_RSS) {
1240 /* RSS together with VMDq not supported*/
1241 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1246 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1247 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1248 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1249 " Due to txmode is meaningless in this"
1250 " driver, just ignore.",
1258 eth_igb_configure(struct rte_eth_dev *dev)
1260 struct e1000_interrupt *intr =
1261 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1264 PMD_INIT_FUNC_TRACE();
1266 /* multipe queue mode checking */
1267 ret = igb_check_mq_mode(dev);
1269 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1274 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1275 PMD_INIT_FUNC_TRACE();
1281 eth_igb_start(struct rte_eth_dev *dev)
1283 struct e1000_hw *hw =
1284 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285 struct e1000_adapter *adapter =
1286 E1000_DEV_PRIVATE(dev->data->dev_private);
1287 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1288 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1290 uint32_t intr_vector = 0;
1296 PMD_INIT_FUNC_TRACE();
1298 /* disable uio/vfio intr/eventfd mapping */
1299 rte_intr_disable(intr_handle);
1301 /* Power up the phy. Needed to make the link go Up */
1302 eth_igb_dev_set_link_up(dev);
1305 * Packet Buffer Allocation (PBA)
1306 * Writing PBA sets the receive portion of the buffer
1307 * the remainder is used for the transmit buffer.
1309 if (hw->mac.type == e1000_82575) {
1312 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1313 E1000_WRITE_REG(hw, E1000_PBA, pba);
1316 /* Put the address into the Receive Address Array */
1317 e1000_rar_set(hw, hw->mac.addr, 0);
1319 /* Initialize the hardware */
1320 if (igb_hardware_init(hw)) {
1321 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1324 adapter->stopped = 0;
1326 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1328 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1329 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1330 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1331 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1332 E1000_WRITE_FLUSH(hw);
1334 /* configure PF module if SRIOV enabled */
1335 igb_pf_host_configure(dev);
1337 /* check and configure queue intr-vector mapping */
1338 if ((rte_intr_cap_multiple(intr_handle) ||
1339 !RTE_ETH_DEV_SRIOV(dev).active) &&
1340 dev->data->dev_conf.intr_conf.rxq != 0) {
1341 intr_vector = dev->data->nb_rx_queues;
1342 if (rte_intr_efd_enable(intr_handle, intr_vector))
1346 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1347 intr_handle->intr_vec =
1348 rte_zmalloc("intr_vec",
1349 dev->data->nb_rx_queues * sizeof(int), 0);
1350 if (intr_handle->intr_vec == NULL) {
1351 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1352 " intr_vec", dev->data->nb_rx_queues);
1357 /* confiugre msix for rx interrupt */
1358 eth_igb_configure_msix_intr(dev);
1360 /* Configure for OS presence */
1361 igb_init_manageability(hw);
1363 eth_igb_tx_init(dev);
1365 /* This can fail when allocating mbufs for descriptor rings */
1366 ret = eth_igb_rx_init(dev);
1368 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1369 igb_dev_clear_queues(dev);
1373 e1000_clear_hw_cntrs_base_generic(hw);
1376 * VLAN Offload Settings
1378 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1379 ETH_VLAN_EXTEND_MASK;
1380 ret = eth_igb_vlan_offload_set(dev, mask);
1382 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1383 igb_dev_clear_queues(dev);
1387 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1388 /* Enable VLAN filter since VMDq always use VLAN filter */
1389 igb_vmdq_vlan_hw_filter_enable(dev);
1392 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1393 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1394 (hw->mac.type == e1000_i211)) {
1395 /* Configure EITR with the maximum possible value (0xFFFF) */
1396 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1399 /* Setup link speed and duplex */
1400 speeds = &dev->data->dev_conf.link_speeds;
1401 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1402 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1403 hw->mac.autoneg = 1;
1406 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1409 hw->phy.autoneg_advertised = 0;
1411 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1412 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1413 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1415 goto error_invalid_config;
1417 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1418 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1421 if (*speeds & ETH_LINK_SPEED_10M) {
1422 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1425 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1426 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1429 if (*speeds & ETH_LINK_SPEED_100M) {
1430 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1433 if (*speeds & ETH_LINK_SPEED_1G) {
1434 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1437 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1438 goto error_invalid_config;
1440 /* Set/reset the mac.autoneg based on the link speed,
1444 hw->mac.autoneg = 0;
1445 hw->mac.forced_speed_duplex =
1446 hw->phy.autoneg_advertised;
1448 hw->mac.autoneg = 1;
1452 e1000_setup_link(hw);
1454 if (rte_intr_allow_others(intr_handle)) {
1455 /* check if lsc interrupt is enabled */
1456 if (dev->data->dev_conf.intr_conf.lsc != 0)
1457 eth_igb_lsc_interrupt_setup(dev, TRUE);
1459 eth_igb_lsc_interrupt_setup(dev, FALSE);
1461 rte_intr_callback_unregister(intr_handle,
1462 eth_igb_interrupt_handler,
1464 if (dev->data->dev_conf.intr_conf.lsc != 0)
1465 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1466 " no intr multiplex");
1469 /* check if rxq interrupt is enabled */
1470 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1471 rte_intr_dp_is_en(intr_handle))
1472 eth_igb_rxq_interrupt_setup(dev);
1474 /* enable uio/vfio intr/eventfd mapping */
1475 rte_intr_enable(intr_handle);
1477 /* resume enabled intr since hw reset */
1478 igb_intr_enable(dev);
1480 /* restore all types filter */
1481 igb_filter_restore(dev);
1483 PMD_INIT_LOG(DEBUG, "<<");
1487 error_invalid_config:
1488 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1489 dev->data->dev_conf.link_speeds, dev->data->port_id);
1490 igb_dev_clear_queues(dev);
1494 /*********************************************************************
1496 * This routine disables all traffic on the adapter by issuing a
1497 * global reset on the MAC.
1499 **********************************************************************/
1501 eth_igb_stop(struct rte_eth_dev *dev)
1503 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1504 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1505 struct rte_eth_link link;
1506 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1508 igb_intr_disable(hw);
1510 /* disable intr eventfd mapping */
1511 rte_intr_disable(intr_handle);
1513 igb_pf_reset_hw(hw);
1514 E1000_WRITE_REG(hw, E1000_WUC, 0);
1516 /* Set bit for Go Link disconnect */
1517 if (hw->mac.type >= e1000_82580) {
1520 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1521 phpm_reg |= E1000_82580_PM_GO_LINKD;
1522 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1525 /* Power down the phy. Needed to make the link go Down */
1526 eth_igb_dev_set_link_down(dev);
1528 igb_dev_clear_queues(dev);
1530 /* clear the recorded link status */
1531 memset(&link, 0, sizeof(link));
1532 rte_igb_dev_atomic_write_link_status(dev, &link);
1534 if (!rte_intr_allow_others(intr_handle))
1535 /* resume to the default handler */
1536 rte_intr_callback_register(intr_handle,
1537 eth_igb_interrupt_handler,
1540 /* Clean datapath event and queue/vec mapping */
1541 rte_intr_efd_disable(intr_handle);
1542 if (intr_handle->intr_vec != NULL) {
1543 rte_free(intr_handle->intr_vec);
1544 intr_handle->intr_vec = NULL;
1549 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1551 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1553 if (hw->phy.media_type == e1000_media_type_copper)
1554 e1000_power_up_phy(hw);
1556 e1000_power_up_fiber_serdes_link(hw);
1562 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1564 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566 if (hw->phy.media_type == e1000_media_type_copper)
1567 e1000_power_down_phy(hw);
1569 e1000_shutdown_fiber_serdes_link(hw);
1575 eth_igb_close(struct rte_eth_dev *dev)
1577 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578 struct e1000_adapter *adapter =
1579 E1000_DEV_PRIVATE(dev->data->dev_private);
1580 struct rte_eth_link link;
1581 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1582 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1585 adapter->stopped = 1;
1587 e1000_phy_hw_reset(hw);
1588 igb_release_manageability(hw);
1589 igb_hw_control_release(hw);
1591 /* Clear bit for Go Link disconnect */
1592 if (hw->mac.type >= e1000_82580) {
1595 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1596 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1597 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1600 igb_dev_free_queues(dev);
1602 if (intr_handle->intr_vec) {
1603 rte_free(intr_handle->intr_vec);
1604 intr_handle->intr_vec = NULL;
1607 memset(&link, 0, sizeof(link));
1608 rte_igb_dev_atomic_write_link_status(dev, &link);
1612 igb_get_rx_buffer_size(struct e1000_hw *hw)
1614 uint32_t rx_buf_size;
1615 if (hw->mac.type == e1000_82576) {
1616 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1617 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1618 /* PBS needs to be translated according to a lookup table */
1619 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1620 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1621 rx_buf_size = (rx_buf_size << 10);
1622 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1623 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1625 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1631 /*********************************************************************
1633 * Initialize the hardware
1635 **********************************************************************/
1637 igb_hardware_init(struct e1000_hw *hw)
1639 uint32_t rx_buf_size;
1642 /* Let the firmware know the OS is in control */
1643 igb_hw_control_acquire(hw);
1646 * These parameters control the automatic generation (Tx) and
1647 * response (Rx) to Ethernet PAUSE frames.
1648 * - High water mark should allow for at least two standard size (1518)
1649 * frames to be received after sending an XOFF.
1650 * - Low water mark works best when it is very near the high water mark.
1651 * This allows the receiver to restart by sending XON when it has
1652 * drained a bit. Here we use an arbitrary value of 1500 which will
1653 * restart after one full frame is pulled from the buffer. There
1654 * could be several smaller frames in the buffer and if so they will
1655 * not trigger the XON until their total number reduces the buffer
1657 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1659 rx_buf_size = igb_get_rx_buffer_size(hw);
1661 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1662 hw->fc.low_water = hw->fc.high_water - 1500;
1663 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1664 hw->fc.send_xon = 1;
1666 /* Set Flow control, use the tunable location if sane */
1667 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1668 hw->fc.requested_mode = igb_fc_setting;
1670 hw->fc.requested_mode = e1000_fc_none;
1672 /* Issue a global reset */
1673 igb_pf_reset_hw(hw);
1674 E1000_WRITE_REG(hw, E1000_WUC, 0);
1676 diag = e1000_init_hw(hw);
1680 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1681 e1000_get_phy_info(hw);
1682 e1000_check_for_link(hw);
1687 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1689 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1693 uint64_t old_gprc = stats->gprc;
1694 uint64_t old_gptc = stats->gptc;
1695 uint64_t old_tpr = stats->tpr;
1696 uint64_t old_tpt = stats->tpt;
1697 uint64_t old_rpthc = stats->rpthc;
1698 uint64_t old_hgptc = stats->hgptc;
1700 if(hw->phy.media_type == e1000_media_type_copper ||
1701 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1703 E1000_READ_REG(hw,E1000_SYMERRS);
1704 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1707 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1708 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1709 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1710 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1712 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1713 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1714 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1715 stats->dc += E1000_READ_REG(hw, E1000_DC);
1716 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1717 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1718 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1720 ** For watchdog management we need to know if we have been
1721 ** paused during the last interval, so capture that here.
1723 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1724 stats->xoffrxc += pause_frames;
1725 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1726 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1727 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1728 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1729 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1730 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1731 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1732 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1733 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1734 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1735 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1736 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1738 /* For the 64-bit byte counters the low dword must be read first. */
1739 /* Both registers clear on the read of the high dword */
1741 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1742 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1743 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1744 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1745 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1746 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1747 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1749 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1750 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1751 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1752 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1753 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1755 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1756 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1758 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1759 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1760 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1761 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1762 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1763 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1765 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1766 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1767 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1768 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1769 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1770 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1771 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1772 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1774 /* Interrupt Counts */
1776 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1777 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1778 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1779 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1780 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1781 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1782 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1783 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1784 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1786 /* Host to Card Statistics */
1788 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1789 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1790 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1791 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1792 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1793 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1794 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1795 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1796 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1797 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1798 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1799 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1800 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1801 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1802 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1803 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1805 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1806 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1807 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1808 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1809 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1810 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1814 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1816 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1817 struct e1000_hw_stats *stats =
1818 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1820 igb_read_stats_registers(hw, stats);
1822 if (rte_stats == NULL)
1826 rte_stats->imissed = stats->mpc;
1827 rte_stats->ierrors = stats->crcerrs +
1828 stats->rlec + stats->ruc + stats->roc +
1829 stats->rxerrc + stats->algnerrc + stats->cexterr;
1832 rte_stats->oerrors = stats->ecol + stats->latecol;
1834 rte_stats->ipackets = stats->gprc;
1835 rte_stats->opackets = stats->gptc;
1836 rte_stats->ibytes = stats->gorc;
1837 rte_stats->obytes = stats->gotc;
1842 eth_igb_stats_reset(struct rte_eth_dev *dev)
1844 struct e1000_hw_stats *hw_stats =
1845 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1847 /* HW registers are cleared on read */
1848 eth_igb_stats_get(dev, NULL);
1850 /* Reset software totals */
1851 memset(hw_stats, 0, sizeof(*hw_stats));
1855 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1857 struct e1000_hw_stats *stats =
1858 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1860 /* HW registers are cleared on read */
1861 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1863 /* Reset software totals */
1864 memset(stats, 0, sizeof(*stats));
1867 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1868 struct rte_eth_xstat_name *xstats_names,
1869 __rte_unused unsigned int size)
1873 if (xstats_names == NULL)
1874 return IGB_NB_XSTATS;
1876 /* Note: limit checked in rte_eth_xstats_names() */
1878 for (i = 0; i < IGB_NB_XSTATS; i++) {
1879 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1880 "%s", rte_igb_stats_strings[i].name);
1883 return IGB_NB_XSTATS;
1886 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1887 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1893 if (xstats_names == NULL)
1894 return IGB_NB_XSTATS;
1896 for (i = 0; i < IGB_NB_XSTATS; i++)
1897 snprintf(xstats_names[i].name,
1898 sizeof(xstats_names[i].name),
1899 "%s", rte_igb_stats_strings[i].name);
1901 return IGB_NB_XSTATS;
1904 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1906 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1909 for (i = 0; i < limit; i++) {
1910 if (ids[i] >= IGB_NB_XSTATS) {
1911 PMD_INIT_LOG(ERR, "id value isn't valid");
1914 strcpy(xstats_names[i].name,
1915 xstats_names_copy[ids[i]].name);
1922 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1925 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926 struct e1000_hw_stats *hw_stats =
1927 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1930 if (n < IGB_NB_XSTATS)
1931 return IGB_NB_XSTATS;
1933 igb_read_stats_registers(hw, hw_stats);
1935 /* If this is a reset xstats is NULL, and we have cleared the
1936 * registers by reading them.
1941 /* Extended stats */
1942 for (i = 0; i < IGB_NB_XSTATS; i++) {
1944 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1945 rte_igb_stats_strings[i].offset);
1948 return IGB_NB_XSTATS;
1952 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1953 uint64_t *values, unsigned int n)
1958 struct e1000_hw *hw =
1959 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1960 struct e1000_hw_stats *hw_stats =
1961 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1963 if (n < IGB_NB_XSTATS)
1964 return IGB_NB_XSTATS;
1966 igb_read_stats_registers(hw, hw_stats);
1968 /* If this is a reset xstats is NULL, and we have cleared the
1969 * registers by reading them.
1974 /* Extended stats */
1975 for (i = 0; i < IGB_NB_XSTATS; i++)
1976 values[i] = *(uint64_t *)(((char *)hw_stats) +
1977 rte_igb_stats_strings[i].offset);
1979 return IGB_NB_XSTATS;
1982 uint64_t values_copy[IGB_NB_XSTATS];
1984 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1987 for (i = 0; i < n; i++) {
1988 if (ids[i] >= IGB_NB_XSTATS) {
1989 PMD_INIT_LOG(ERR, "id value isn't valid");
1992 values[i] = values_copy[ids[i]];
1999 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2001 /* Good Rx packets, include VF loopback */
2002 UPDATE_VF_STAT(E1000_VFGPRC,
2003 hw_stats->last_gprc, hw_stats->gprc);
2005 /* Good Rx octets, include VF loopback */
2006 UPDATE_VF_STAT(E1000_VFGORC,
2007 hw_stats->last_gorc, hw_stats->gorc);
2009 /* Good Tx packets, include VF loopback */
2010 UPDATE_VF_STAT(E1000_VFGPTC,
2011 hw_stats->last_gptc, hw_stats->gptc);
2013 /* Good Tx octets, include VF loopback */
2014 UPDATE_VF_STAT(E1000_VFGOTC,
2015 hw_stats->last_gotc, hw_stats->gotc);
2017 /* Rx Multicst packets */
2018 UPDATE_VF_STAT(E1000_VFMPRC,
2019 hw_stats->last_mprc, hw_stats->mprc);
2021 /* Good Rx loopback packets */
2022 UPDATE_VF_STAT(E1000_VFGPRLBC,
2023 hw_stats->last_gprlbc, hw_stats->gprlbc);
2025 /* Good Rx loopback octets */
2026 UPDATE_VF_STAT(E1000_VFGORLBC,
2027 hw_stats->last_gorlbc, hw_stats->gorlbc);
2029 /* Good Tx loopback packets */
2030 UPDATE_VF_STAT(E1000_VFGPTLBC,
2031 hw_stats->last_gptlbc, hw_stats->gptlbc);
2033 /* Good Tx loopback octets */
2034 UPDATE_VF_STAT(E1000_VFGOTLBC,
2035 hw_stats->last_gotlbc, hw_stats->gotlbc);
2038 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2039 struct rte_eth_xstat_name *xstats_names,
2040 __rte_unused unsigned limit)
2044 if (xstats_names != NULL)
2045 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2046 snprintf(xstats_names[i].name,
2047 sizeof(xstats_names[i].name), "%s",
2048 rte_igbvf_stats_strings[i].name);
2050 return IGBVF_NB_XSTATS;
2054 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2057 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2058 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2059 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2062 if (n < IGBVF_NB_XSTATS)
2063 return IGBVF_NB_XSTATS;
2065 igbvf_read_stats_registers(hw, hw_stats);
2070 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2072 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2073 rte_igbvf_stats_strings[i].offset);
2076 return IGBVF_NB_XSTATS;
2080 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2082 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2084 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2086 igbvf_read_stats_registers(hw, hw_stats);
2088 if (rte_stats == NULL)
2091 rte_stats->ipackets = hw_stats->gprc;
2092 rte_stats->ibytes = hw_stats->gorc;
2093 rte_stats->opackets = hw_stats->gptc;
2094 rte_stats->obytes = hw_stats->gotc;
2099 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2101 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2102 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2104 /* Sync HW register to the last stats */
2105 eth_igbvf_stats_get(dev, NULL);
2107 /* reset HW current stats*/
2108 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2109 offsetof(struct e1000_vf_stats, gprc));
2113 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2116 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2117 struct e1000_fw_version fw;
2120 e1000_get_fw_version(hw, &fw);
2122 switch (hw->mac.type) {
2125 if (!(e1000_get_flash_presence_i210(hw))) {
2126 ret = snprintf(fw_version, fw_size,
2128 fw.invm_major, fw.invm_minor,
2134 /* if option rom is valid, display its version too */
2136 ret = snprintf(fw_version, fw_size,
2137 "%d.%d, 0x%08x, %d.%d.%d",
2138 fw.eep_major, fw.eep_minor, fw.etrack_id,
2139 fw.or_major, fw.or_build, fw.or_patch);
2142 if (fw.etrack_id != 0X0000) {
2143 ret = snprintf(fw_version, fw_size,
2145 fw.eep_major, fw.eep_minor,
2148 ret = snprintf(fw_version, fw_size,
2150 fw.eep_major, fw.eep_minor,
2157 ret += 1; /* add the size of '\0' */
2158 if (fw_size < (u32)ret)
2165 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2167 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2170 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2171 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2172 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2173 dev_info->rx_offload_capa =
2174 DEV_RX_OFFLOAD_VLAN_STRIP |
2175 DEV_RX_OFFLOAD_IPV4_CKSUM |
2176 DEV_RX_OFFLOAD_UDP_CKSUM |
2177 DEV_RX_OFFLOAD_TCP_CKSUM;
2178 dev_info->tx_offload_capa =
2179 DEV_TX_OFFLOAD_VLAN_INSERT |
2180 DEV_TX_OFFLOAD_IPV4_CKSUM |
2181 DEV_TX_OFFLOAD_UDP_CKSUM |
2182 DEV_TX_OFFLOAD_TCP_CKSUM |
2183 DEV_TX_OFFLOAD_SCTP_CKSUM |
2184 DEV_TX_OFFLOAD_TCP_TSO;
2186 switch (hw->mac.type) {
2188 dev_info->max_rx_queues = 4;
2189 dev_info->max_tx_queues = 4;
2190 dev_info->max_vmdq_pools = 0;
2194 dev_info->max_rx_queues = 16;
2195 dev_info->max_tx_queues = 16;
2196 dev_info->max_vmdq_pools = ETH_8_POOLS;
2197 dev_info->vmdq_queue_num = 16;
2201 dev_info->max_rx_queues = 8;
2202 dev_info->max_tx_queues = 8;
2203 dev_info->max_vmdq_pools = ETH_8_POOLS;
2204 dev_info->vmdq_queue_num = 8;
2208 dev_info->max_rx_queues = 8;
2209 dev_info->max_tx_queues = 8;
2210 dev_info->max_vmdq_pools = ETH_8_POOLS;
2211 dev_info->vmdq_queue_num = 8;
2215 dev_info->max_rx_queues = 8;
2216 dev_info->max_tx_queues = 8;
2220 dev_info->max_rx_queues = 4;
2221 dev_info->max_tx_queues = 4;
2222 dev_info->max_vmdq_pools = 0;
2226 dev_info->max_rx_queues = 2;
2227 dev_info->max_tx_queues = 2;
2228 dev_info->max_vmdq_pools = 0;
2232 /* Should not happen */
2235 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2236 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2237 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2239 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2241 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2242 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2243 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2245 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2249 dev_info->default_txconf = (struct rte_eth_txconf) {
2251 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2252 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2253 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2258 dev_info->rx_desc_lim = rx_desc_lim;
2259 dev_info->tx_desc_lim = tx_desc_lim;
2261 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2262 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2266 static const uint32_t *
2267 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2269 static const uint32_t ptypes[] = {
2270 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2273 RTE_PTYPE_L3_IPV4_EXT,
2275 RTE_PTYPE_L3_IPV6_EXT,
2279 RTE_PTYPE_TUNNEL_IP,
2280 RTE_PTYPE_INNER_L3_IPV6,
2281 RTE_PTYPE_INNER_L3_IPV6_EXT,
2282 RTE_PTYPE_INNER_L4_TCP,
2283 RTE_PTYPE_INNER_L4_UDP,
2287 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2288 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2294 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2296 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2298 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2299 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2300 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2301 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2302 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2303 DEV_RX_OFFLOAD_IPV4_CKSUM |
2304 DEV_RX_OFFLOAD_UDP_CKSUM |
2305 DEV_RX_OFFLOAD_TCP_CKSUM;
2306 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2307 DEV_TX_OFFLOAD_IPV4_CKSUM |
2308 DEV_TX_OFFLOAD_UDP_CKSUM |
2309 DEV_TX_OFFLOAD_TCP_CKSUM |
2310 DEV_TX_OFFLOAD_SCTP_CKSUM |
2311 DEV_TX_OFFLOAD_TCP_TSO;
2312 switch (hw->mac.type) {
2314 dev_info->max_rx_queues = 2;
2315 dev_info->max_tx_queues = 2;
2317 case e1000_vfadapt_i350:
2318 dev_info->max_rx_queues = 1;
2319 dev_info->max_tx_queues = 1;
2322 /* Should not happen */
2326 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2328 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2329 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2330 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2332 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2336 dev_info->default_txconf = (struct rte_eth_txconf) {
2338 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2339 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2340 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2345 dev_info->rx_desc_lim = rx_desc_lim;
2346 dev_info->tx_desc_lim = tx_desc_lim;
2349 /* return 0 means link status changed, -1 means not changed */
2351 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2353 struct e1000_hw *hw =
2354 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2355 struct rte_eth_link link, old;
2356 int link_check, count;
2359 hw->mac.get_link_status = 1;
2361 /* possible wait-to-complete in up to 9 seconds */
2362 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2363 /* Read the real link status */
2364 switch (hw->phy.media_type) {
2365 case e1000_media_type_copper:
2366 /* Do the work to read phy */
2367 e1000_check_for_link(hw);
2368 link_check = !hw->mac.get_link_status;
2371 case e1000_media_type_fiber:
2372 e1000_check_for_link(hw);
2373 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2377 case e1000_media_type_internal_serdes:
2378 e1000_check_for_link(hw);
2379 link_check = hw->mac.serdes_has_link;
2382 /* VF device is type_unknown */
2383 case e1000_media_type_unknown:
2384 eth_igbvf_link_update(hw);
2385 link_check = !hw->mac.get_link_status;
2391 if (link_check || wait_to_complete == 0)
2393 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2395 memset(&link, 0, sizeof(link));
2396 rte_igb_dev_atomic_read_link_status(dev, &link);
2399 /* Now we check if a transition has happened */
2401 uint16_t duplex, speed;
2402 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2403 link.link_duplex = (duplex == FULL_DUPLEX) ?
2404 ETH_LINK_FULL_DUPLEX :
2405 ETH_LINK_HALF_DUPLEX;
2406 link.link_speed = speed;
2407 link.link_status = ETH_LINK_UP;
2408 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2409 ETH_LINK_SPEED_FIXED);
2410 } else if (!link_check) {
2411 link.link_speed = 0;
2412 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2413 link.link_status = ETH_LINK_DOWN;
2414 link.link_autoneg = ETH_LINK_FIXED;
2416 rte_igb_dev_atomic_write_link_status(dev, &link);
2419 if (old.link_status == link.link_status)
2427 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2428 * For ASF and Pass Through versions of f/w this means
2429 * that the driver is loaded.
2432 igb_hw_control_acquire(struct e1000_hw *hw)
2436 /* Let firmware know the driver has taken over */
2437 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2438 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2442 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2443 * For ASF and Pass Through versions of f/w this means that the
2444 * driver is no longer loaded.
2447 igb_hw_control_release(struct e1000_hw *hw)
2451 /* Let firmware taken over control of h/w */
2452 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2453 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2454 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2458 * Bit of a misnomer, what this really means is
2459 * to enable OS management of the system... aka
2460 * to disable special hardware management features.
2463 igb_init_manageability(struct e1000_hw *hw)
2465 if (e1000_enable_mng_pass_thru(hw)) {
2466 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2467 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2469 /* disable hardware interception of ARP */
2470 manc &= ~(E1000_MANC_ARP_EN);
2472 /* enable receiving management packets to the host */
2473 manc |= E1000_MANC_EN_MNG2HOST;
2474 manc2h |= 1 << 5; /* Mng Port 623 */
2475 manc2h |= 1 << 6; /* Mng Port 664 */
2476 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2477 E1000_WRITE_REG(hw, E1000_MANC, manc);
2482 igb_release_manageability(struct e1000_hw *hw)
2484 if (e1000_enable_mng_pass_thru(hw)) {
2485 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2487 manc |= E1000_MANC_ARP_EN;
2488 manc &= ~E1000_MANC_EN_MNG2HOST;
2490 E1000_WRITE_REG(hw, E1000_MANC, manc);
2495 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2497 struct e1000_hw *hw =
2498 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2501 rctl = E1000_READ_REG(hw, E1000_RCTL);
2502 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2503 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2507 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2509 struct e1000_hw *hw =
2510 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513 rctl = E1000_READ_REG(hw, E1000_RCTL);
2514 rctl &= (~E1000_RCTL_UPE);
2515 if (dev->data->all_multicast == 1)
2516 rctl |= E1000_RCTL_MPE;
2518 rctl &= (~E1000_RCTL_MPE);
2519 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2523 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2525 struct e1000_hw *hw =
2526 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2529 rctl = E1000_READ_REG(hw, E1000_RCTL);
2530 rctl |= E1000_RCTL_MPE;
2531 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2535 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2537 struct e1000_hw *hw =
2538 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541 if (dev->data->promiscuous == 1)
2542 return; /* must remain in all_multicast mode */
2543 rctl = E1000_READ_REG(hw, E1000_RCTL);
2544 rctl &= (~E1000_RCTL_MPE);
2545 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2549 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2551 struct e1000_hw *hw =
2552 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2553 struct e1000_vfta * shadow_vfta =
2554 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2559 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2560 E1000_VFTA_ENTRY_MASK);
2561 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2562 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2567 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2569 /* update local VFTA copy */
2570 shadow_vfta->vfta[vid_idx] = vfta;
2576 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2577 enum rte_vlan_type vlan_type,
2580 struct e1000_hw *hw =
2581 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2585 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2587 /* only outer TPID of double VLAN can be configured*/
2588 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2589 reg = E1000_READ_REG(hw, E1000_VET);
2590 reg = (reg & (~E1000_VET_VET_EXT)) |
2591 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2592 E1000_WRITE_REG(hw, E1000_VET, reg);
2597 /* all other TPID values are read-only*/
2598 PMD_DRV_LOG(ERR, "Not supported");
2604 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2606 struct e1000_hw *hw =
2607 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2610 /* Filter Table Disable */
2611 reg = E1000_READ_REG(hw, E1000_RCTL);
2612 reg &= ~E1000_RCTL_CFIEN;
2613 reg &= ~E1000_RCTL_VFE;
2614 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2618 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2620 struct e1000_hw *hw =
2621 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2622 struct e1000_vfta * shadow_vfta =
2623 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2627 /* Filter Table Enable, CFI not used for packet acceptance */
2628 reg = E1000_READ_REG(hw, E1000_RCTL);
2629 reg &= ~E1000_RCTL_CFIEN;
2630 reg |= E1000_RCTL_VFE;
2631 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2633 /* restore VFTA table */
2634 for (i = 0; i < IGB_VFTA_SIZE; i++)
2635 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2639 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2641 struct e1000_hw *hw =
2642 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2645 /* VLAN Mode Disable */
2646 reg = E1000_READ_REG(hw, E1000_CTRL);
2647 reg &= ~E1000_CTRL_VME;
2648 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2652 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2654 struct e1000_hw *hw =
2655 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2658 /* VLAN Mode Enable */
2659 reg = E1000_READ_REG(hw, E1000_CTRL);
2660 reg |= E1000_CTRL_VME;
2661 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2665 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2667 struct e1000_hw *hw =
2668 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2671 /* CTRL_EXT: Extended VLAN */
2672 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2673 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2674 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2676 /* Update maximum packet length */
2677 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2678 E1000_WRITE_REG(hw, E1000_RLPML,
2679 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2684 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2686 struct e1000_hw *hw =
2687 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2690 /* CTRL_EXT: Extended VLAN */
2691 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2692 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2693 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2695 /* Update maximum packet length */
2696 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2697 E1000_WRITE_REG(hw, E1000_RLPML,
2698 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2703 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2705 if(mask & ETH_VLAN_STRIP_MASK){
2706 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2707 igb_vlan_hw_strip_enable(dev);
2709 igb_vlan_hw_strip_disable(dev);
2712 if(mask & ETH_VLAN_FILTER_MASK){
2713 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2714 igb_vlan_hw_filter_enable(dev);
2716 igb_vlan_hw_filter_disable(dev);
2719 if(mask & ETH_VLAN_EXTEND_MASK){
2720 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2721 igb_vlan_hw_extend_enable(dev);
2723 igb_vlan_hw_extend_disable(dev);
2731 * It enables the interrupt mask and then enable the interrupt.
2734 * Pointer to struct rte_eth_dev.
2739 * - On success, zero.
2740 * - On failure, a negative value.
2743 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2745 struct e1000_interrupt *intr =
2746 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2749 intr->mask |= E1000_ICR_LSC;
2751 intr->mask &= ~E1000_ICR_LSC;
2756 /* It clears the interrupt causes and enables the interrupt.
2757 * It will be called once only during nic initialized.
2760 * Pointer to struct rte_eth_dev.
2763 * - On success, zero.
2764 * - On failure, a negative value.
2766 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2768 uint32_t mask, regval;
2769 struct e1000_hw *hw =
2770 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2771 struct rte_eth_dev_info dev_info;
2773 memset(&dev_info, 0, sizeof(dev_info));
2774 eth_igb_infos_get(dev, &dev_info);
2776 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2777 regval = E1000_READ_REG(hw, E1000_EIMS);
2778 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2784 * It reads ICR and gets interrupt causes, check it and set a bit flag
2785 * to update link status.
2788 * Pointer to struct rte_eth_dev.
2791 * - On success, zero.
2792 * - On failure, a negative value.
2795 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2798 struct e1000_hw *hw =
2799 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2800 struct e1000_interrupt *intr =
2801 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2803 igb_intr_disable(hw);
2805 /* read-on-clear nic registers here */
2806 icr = E1000_READ_REG(hw, E1000_ICR);
2809 if (icr & E1000_ICR_LSC) {
2810 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2813 if (icr & E1000_ICR_VMMB)
2814 intr->flags |= E1000_FLAG_MAILBOX;
2820 * It executes link_update after knowing an interrupt is prsent.
2823 * Pointer to struct rte_eth_dev.
2826 * - On success, zero.
2827 * - On failure, a negative value.
2830 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2831 struct rte_intr_handle *intr_handle)
2833 struct e1000_hw *hw =
2834 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2835 struct e1000_interrupt *intr =
2836 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2837 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2838 uint32_t tctl, rctl;
2839 struct rte_eth_link link;
2842 if (intr->flags & E1000_FLAG_MAILBOX) {
2843 igb_pf_mbx_process(dev);
2844 intr->flags &= ~E1000_FLAG_MAILBOX;
2847 igb_intr_enable(dev);
2848 rte_intr_enable(intr_handle);
2850 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2851 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2853 /* set get_link_status to check register later */
2854 hw->mac.get_link_status = 1;
2855 ret = eth_igb_link_update(dev, 0);
2857 /* check if link has changed */
2861 memset(&link, 0, sizeof(link));
2862 rte_igb_dev_atomic_read_link_status(dev, &link);
2863 if (link.link_status) {
2865 " Port %d: Link Up - speed %u Mbps - %s",
2867 (unsigned)link.link_speed,
2868 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2869 "full-duplex" : "half-duplex");
2871 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2872 dev->data->port_id);
2875 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2876 pci_dev->addr.domain,
2878 pci_dev->addr.devid,
2879 pci_dev->addr.function);
2880 tctl = E1000_READ_REG(hw, E1000_TCTL);
2881 rctl = E1000_READ_REG(hw, E1000_RCTL);
2882 if (link.link_status) {
2884 tctl |= E1000_TCTL_EN;
2885 rctl |= E1000_RCTL_EN;
2888 tctl &= ~E1000_TCTL_EN;
2889 rctl &= ~E1000_RCTL_EN;
2891 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2892 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2893 E1000_WRITE_FLUSH(hw);
2894 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2902 * Interrupt handler which shall be registered at first.
2905 * Pointer to interrupt handle.
2907 * The address of parameter (struct rte_eth_dev *) regsitered before.
2913 eth_igb_interrupt_handler(void *param)
2915 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2917 eth_igb_interrupt_get_status(dev);
2918 eth_igb_interrupt_action(dev, dev->intr_handle);
2922 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2925 struct e1000_hw *hw =
2926 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2927 struct e1000_interrupt *intr =
2928 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2930 igbvf_intr_disable(hw);
2932 /* read-on-clear nic registers here */
2933 eicr = E1000_READ_REG(hw, E1000_EICR);
2936 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2937 intr->flags |= E1000_FLAG_MAILBOX;
2942 void igbvf_mbx_process(struct rte_eth_dev *dev)
2944 struct e1000_hw *hw =
2945 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2946 struct e1000_mbx_info *mbx = &hw->mbx;
2949 if (mbx->ops.read(hw, &in_msg, 1, 0))
2952 /* PF reset VF event */
2953 if (in_msg == E1000_PF_CONTROL_MSG)
2954 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2959 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2961 struct e1000_interrupt *intr =
2962 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2964 if (intr->flags & E1000_FLAG_MAILBOX) {
2965 igbvf_mbx_process(dev);
2966 intr->flags &= ~E1000_FLAG_MAILBOX;
2969 igbvf_intr_enable(dev);
2970 rte_intr_enable(intr_handle);
2976 eth_igbvf_interrupt_handler(void *param)
2978 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2980 eth_igbvf_interrupt_get_status(dev);
2981 eth_igbvf_interrupt_action(dev, dev->intr_handle);
2985 eth_igb_led_on(struct rte_eth_dev *dev)
2987 struct e1000_hw *hw;
2989 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2990 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2994 eth_igb_led_off(struct rte_eth_dev *dev)
2996 struct e1000_hw *hw;
2998 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2999 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3003 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3005 struct e1000_hw *hw;
3010 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3011 fc_conf->pause_time = hw->fc.pause_time;
3012 fc_conf->high_water = hw->fc.high_water;
3013 fc_conf->low_water = hw->fc.low_water;
3014 fc_conf->send_xon = hw->fc.send_xon;
3015 fc_conf->autoneg = hw->mac.autoneg;
3018 * Return rx_pause and tx_pause status according to actual setting of
3019 * the TFCE and RFCE bits in the CTRL register.
3021 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3022 if (ctrl & E1000_CTRL_TFCE)
3027 if (ctrl & E1000_CTRL_RFCE)
3032 if (rx_pause && tx_pause)
3033 fc_conf->mode = RTE_FC_FULL;
3035 fc_conf->mode = RTE_FC_RX_PAUSE;
3037 fc_conf->mode = RTE_FC_TX_PAUSE;
3039 fc_conf->mode = RTE_FC_NONE;
3045 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3047 struct e1000_hw *hw;
3049 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3055 uint32_t rx_buf_size;
3056 uint32_t max_high_water;
3059 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3060 if (fc_conf->autoneg != hw->mac.autoneg)
3062 rx_buf_size = igb_get_rx_buffer_size(hw);
3063 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3065 /* At least reserve one Ethernet frame for watermark */
3066 max_high_water = rx_buf_size - ETHER_MAX_LEN;
3067 if ((fc_conf->high_water > max_high_water) ||
3068 (fc_conf->high_water < fc_conf->low_water)) {
3069 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3070 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3074 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3075 hw->fc.pause_time = fc_conf->pause_time;
3076 hw->fc.high_water = fc_conf->high_water;
3077 hw->fc.low_water = fc_conf->low_water;
3078 hw->fc.send_xon = fc_conf->send_xon;
3080 err = e1000_setup_link_generic(hw);
3081 if (err == E1000_SUCCESS) {
3083 /* check if we want to forward MAC frames - driver doesn't have native
3084 * capability to do that, so we'll write the registers ourselves */
3086 rctl = E1000_READ_REG(hw, E1000_RCTL);
3088 /* set or clear MFLCN.PMCF bit depending on configuration */
3089 if (fc_conf->mac_ctrl_frame_fwd != 0)
3090 rctl |= E1000_RCTL_PMCF;
3092 rctl &= ~E1000_RCTL_PMCF;
3094 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3095 E1000_WRITE_FLUSH(hw);
3100 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3104 #define E1000_RAH_POOLSEL_SHIFT (18)
3106 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3107 uint32_t index, uint32_t pool)
3109 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3112 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3113 rah = E1000_READ_REG(hw, E1000_RAH(index));
3114 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3115 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3120 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3122 uint8_t addr[ETHER_ADDR_LEN];
3123 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3125 memset(addr, 0, sizeof(addr));
3127 e1000_rar_set(hw, addr, index);
3131 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3132 struct ether_addr *addr)
3134 eth_igb_rar_clear(dev, 0);
3136 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3139 * Virtual Function operations
3142 igbvf_intr_disable(struct e1000_hw *hw)
3144 PMD_INIT_FUNC_TRACE();
3146 /* Clear interrupt mask to stop from interrupts being generated */
3147 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3149 E1000_WRITE_FLUSH(hw);
3153 igbvf_stop_adapter(struct rte_eth_dev *dev)
3157 struct rte_eth_dev_info dev_info;
3158 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3160 memset(&dev_info, 0, sizeof(dev_info));
3161 eth_igbvf_infos_get(dev, &dev_info);
3163 /* Clear interrupt mask to stop from interrupts being generated */
3164 igbvf_intr_disable(hw);
3166 /* Clear any pending interrupts, flush previous writes */
3167 E1000_READ_REG(hw, E1000_EICR);
3169 /* Disable the transmit unit. Each queue must be disabled. */
3170 for (i = 0; i < dev_info.max_tx_queues; i++)
3171 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3173 /* Disable the receive unit by stopping each queue */
3174 for (i = 0; i < dev_info.max_rx_queues; i++) {
3175 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3176 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3177 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3178 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3182 /* flush all queues disables */
3183 E1000_WRITE_FLUSH(hw);
3187 static int eth_igbvf_link_update(struct e1000_hw *hw)
3189 struct e1000_mbx_info *mbx = &hw->mbx;
3190 struct e1000_mac_info *mac = &hw->mac;
3191 int ret_val = E1000_SUCCESS;
3193 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3196 * We only want to run this if there has been a rst asserted.
3197 * in this case that could mean a link change, device reset,
3198 * or a virtual function reset
3201 /* If we were hit with a reset or timeout drop the link */
3202 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3203 mac->get_link_status = TRUE;
3205 if (!mac->get_link_status)
3208 /* if link status is down no point in checking to see if pf is up */
3209 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3212 /* if we passed all the tests above then the link is up and we no
3213 * longer need to check for link */
3214 mac->get_link_status = FALSE;
3222 igbvf_dev_configure(struct rte_eth_dev *dev)
3224 struct rte_eth_conf* conf = &dev->data->dev_conf;
3226 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3227 dev->data->port_id);
3230 * VF has no ability to enable/disable HW CRC
3231 * Keep the persistent behavior the same as Host PF
3233 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3234 if (!conf->rxmode.hw_strip_crc) {
3235 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3236 conf->rxmode.hw_strip_crc = 1;
3239 if (conf->rxmode.hw_strip_crc) {
3240 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3241 conf->rxmode.hw_strip_crc = 0;
3249 igbvf_dev_start(struct rte_eth_dev *dev)
3251 struct e1000_hw *hw =
3252 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3253 struct e1000_adapter *adapter =
3254 E1000_DEV_PRIVATE(dev->data->dev_private);
3255 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3256 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3258 uint32_t intr_vector = 0;
3260 PMD_INIT_FUNC_TRACE();
3262 hw->mac.ops.reset_hw(hw);
3263 adapter->stopped = 0;
3266 igbvf_set_vfta_all(dev,1);
3268 eth_igbvf_tx_init(dev);
3270 /* This can fail when allocating mbufs for descriptor rings */
3271 ret = eth_igbvf_rx_init(dev);
3273 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3274 igb_dev_clear_queues(dev);
3278 /* check and configure queue intr-vector mapping */
3279 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3280 intr_vector = dev->data->nb_rx_queues;
3281 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3286 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3287 intr_handle->intr_vec =
3288 rte_zmalloc("intr_vec",
3289 dev->data->nb_rx_queues * sizeof(int), 0);
3290 if (!intr_handle->intr_vec) {
3291 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3292 " intr_vec", dev->data->nb_rx_queues);
3297 eth_igbvf_configure_msix_intr(dev);
3299 /* enable uio/vfio intr/eventfd mapping */
3300 rte_intr_enable(intr_handle);
3302 /* resume enabled intr since hw reset */
3303 igbvf_intr_enable(dev);
3309 igbvf_dev_stop(struct rte_eth_dev *dev)
3311 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3312 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3314 PMD_INIT_FUNC_TRACE();
3316 igbvf_stop_adapter(dev);
3319 * Clear what we set, but we still keep shadow_vfta to
3320 * restore after device starts
3322 igbvf_set_vfta_all(dev,0);
3324 igb_dev_clear_queues(dev);
3326 /* disable intr eventfd mapping */
3327 rte_intr_disable(intr_handle);
3329 /* Clean datapath event and queue/vec mapping */
3330 rte_intr_efd_disable(intr_handle);
3331 if (intr_handle->intr_vec) {
3332 rte_free(intr_handle->intr_vec);
3333 intr_handle->intr_vec = NULL;
3338 igbvf_dev_close(struct rte_eth_dev *dev)
3340 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3341 struct e1000_adapter *adapter =
3342 E1000_DEV_PRIVATE(dev->data->dev_private);
3343 struct ether_addr addr;
3345 PMD_INIT_FUNC_TRACE();
3349 igbvf_dev_stop(dev);
3350 adapter->stopped = 1;
3351 igb_dev_free_queues(dev);
3354 * reprogram the RAR with a zero mac address,
3355 * to ensure that the VF traffic goes to the PF
3356 * after stop, close and detach of the VF.
3359 memset(&addr, 0, sizeof(addr));
3360 igbvf_default_mac_addr_set(dev, &addr);
3364 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3366 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3368 /* Set both unicast and multicast promisc */
3369 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3373 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3375 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3377 /* If in allmulticast mode leave multicast promisc */
3378 if (dev->data->all_multicast == 1)
3379 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3381 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3385 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3387 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3389 /* In promiscuous mode multicast promisc already set */
3390 if (dev->data->promiscuous == 0)
3391 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3395 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3397 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3399 /* In promiscuous mode leave multicast promisc enabled */
3400 if (dev->data->promiscuous == 0)
3401 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3404 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3406 struct e1000_mbx_info *mbx = &hw->mbx;
3410 /* After set vlan, vlan strip will also be enabled in igb driver*/
3411 msgbuf[0] = E1000_VF_SET_VLAN;
3413 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3415 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3417 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3421 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3425 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3426 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3433 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3435 struct e1000_hw *hw =
3436 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3437 struct e1000_vfta * shadow_vfta =
3438 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3439 int i = 0, j = 0, vfta = 0, mask = 1;
3441 for (i = 0; i < IGB_VFTA_SIZE; i++){
3442 vfta = shadow_vfta->vfta[i];
3445 for (j = 0; j < 32; j++){
3448 (uint16_t)((i<<5)+j), on);
3457 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3459 struct e1000_hw *hw =
3460 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3461 struct e1000_vfta * shadow_vfta =
3462 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3463 uint32_t vid_idx = 0;
3464 uint32_t vid_bit = 0;
3467 PMD_INIT_FUNC_TRACE();
3469 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3470 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3472 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3475 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3476 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3478 /*Save what we set and retore it after device reset*/
3480 shadow_vfta->vfta[vid_idx] |= vid_bit;
3482 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3488 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3490 struct e1000_hw *hw =
3491 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3493 /* index is not used by rar_set() */
3494 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3499 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3500 struct rte_eth_rss_reta_entry64 *reta_conf,
3505 uint16_t idx, shift;
3506 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3508 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3509 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3510 "(%d) doesn't match the number hardware can supported "
3511 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3515 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3516 idx = i / RTE_RETA_GROUP_SIZE;
3517 shift = i % RTE_RETA_GROUP_SIZE;
3518 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3522 if (mask == IGB_4_BIT_MASK)
3525 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3526 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3527 if (mask & (0x1 << j))
3528 reta |= reta_conf[idx].reta[shift + j] <<
3531 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3533 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3540 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3541 struct rte_eth_rss_reta_entry64 *reta_conf,
3546 uint16_t idx, shift;
3547 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3549 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3550 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3551 "(%d) doesn't match the number hardware can supported "
3552 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3556 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3557 idx = i / RTE_RETA_GROUP_SIZE;
3558 shift = i % RTE_RETA_GROUP_SIZE;
3559 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3563 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3564 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3565 if (mask & (0x1 << j))
3566 reta_conf[idx].reta[shift + j] =
3567 ((reta >> (CHAR_BIT * j)) &
3576 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3577 struct rte_eth_syn_filter *filter,
3580 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3581 struct e1000_filter_info *filter_info =
3582 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3583 uint32_t synqf, rfctl;
3585 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3588 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3591 if (synqf & E1000_SYN_FILTER_ENABLE)
3594 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3595 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3597 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3598 if (filter->hig_pri)
3599 rfctl |= E1000_RFCTL_SYNQFP;
3601 rfctl &= ~E1000_RFCTL_SYNQFP;
3603 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3605 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3610 filter_info->syn_info = synqf;
3611 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3612 E1000_WRITE_FLUSH(hw);
3617 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3618 struct rte_eth_syn_filter *filter)
3620 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3621 uint32_t synqf, rfctl;
3623 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3624 if (synqf & E1000_SYN_FILTER_ENABLE) {
3625 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3626 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3627 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3628 E1000_SYN_FILTER_QUEUE_SHIFT);
3636 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3637 enum rte_filter_op filter_op,
3640 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3643 MAC_TYPE_FILTER_SUP(hw->mac.type);
3645 if (filter_op == RTE_ETH_FILTER_NOP)
3649 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3654 switch (filter_op) {
3655 case RTE_ETH_FILTER_ADD:
3656 ret = eth_igb_syn_filter_set(dev,
3657 (struct rte_eth_syn_filter *)arg,
3660 case RTE_ETH_FILTER_DELETE:
3661 ret = eth_igb_syn_filter_set(dev,
3662 (struct rte_eth_syn_filter *)arg,
3665 case RTE_ETH_FILTER_GET:
3666 ret = eth_igb_syn_filter_get(dev,
3667 (struct rte_eth_syn_filter *)arg);
3670 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3678 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3680 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3681 struct e1000_2tuple_filter_info *filter_info)
3683 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3685 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3686 return -EINVAL; /* filter index is out of range. */
3687 if (filter->tcp_flags > TCP_FLAG_ALL)
3688 return -EINVAL; /* flags is invalid. */
3690 switch (filter->dst_port_mask) {
3692 filter_info->dst_port_mask = 0;
3693 filter_info->dst_port = filter->dst_port;
3696 filter_info->dst_port_mask = 1;
3699 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3703 switch (filter->proto_mask) {
3705 filter_info->proto_mask = 0;
3706 filter_info->proto = filter->proto;
3709 filter_info->proto_mask = 1;
3712 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3716 filter_info->priority = (uint8_t)filter->priority;
3717 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3718 filter_info->tcp_flags = filter->tcp_flags;
3720 filter_info->tcp_flags = 0;
3725 static inline struct e1000_2tuple_filter *
3726 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3727 struct e1000_2tuple_filter_info *key)
3729 struct e1000_2tuple_filter *it;
3731 TAILQ_FOREACH(it, filter_list, entries) {
3732 if (memcmp(key, &it->filter_info,
3733 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3740 /* inject a igb 2tuple filter to HW */
3742 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3743 struct e1000_2tuple_filter *filter)
3745 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3746 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3747 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3751 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3752 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3753 imir |= E1000_IMIR_PORT_BP;
3755 imir &= ~E1000_IMIR_PORT_BP;
3757 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3759 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3760 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3761 ttqf |= (uint32_t)(filter->filter_info.proto &
3762 E1000_TTQF_PROTOCOL_MASK);
3763 if (filter->filter_info.proto_mask == 0)
3764 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3766 /* tcp flags bits setting. */
3767 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3768 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3769 imir_ext |= E1000_IMIREXT_CTRL_URG;
3770 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3771 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3772 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3773 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3774 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3775 imir_ext |= E1000_IMIREXT_CTRL_RST;
3776 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3777 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3778 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3779 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3781 imir_ext |= E1000_IMIREXT_CTRL_BP;
3783 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3784 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3785 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3789 * igb_add_2tuple_filter - add a 2tuple filter
3792 * dev: Pointer to struct rte_eth_dev.
3793 * ntuple_filter: ponter to the filter that will be added.
3796 * - On success, zero.
3797 * - On failure, a negative value.
3800 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3801 struct rte_eth_ntuple_filter *ntuple_filter)
3803 struct e1000_filter_info *filter_info =
3804 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3805 struct e1000_2tuple_filter *filter;
3808 filter = rte_zmalloc("e1000_2tuple_filter",
3809 sizeof(struct e1000_2tuple_filter), 0);
3813 ret = ntuple_filter_to_2tuple(ntuple_filter,
3814 &filter->filter_info);
3819 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3820 &filter->filter_info) != NULL) {
3821 PMD_DRV_LOG(ERR, "filter exists.");
3825 filter->queue = ntuple_filter->queue;
3828 * look for an unused 2tuple filter index,
3829 * and insert the filter to list.
3831 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3832 if (!(filter_info->twotuple_mask & (1 << i))) {
3833 filter_info->twotuple_mask |= 1 << i;
3835 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3841 if (i >= E1000_MAX_TTQF_FILTERS) {
3842 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3847 igb_inject_2uple_filter(dev, filter);
3852 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3853 struct e1000_2tuple_filter *filter)
3855 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3856 struct e1000_filter_info *filter_info =
3857 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3859 filter_info->twotuple_mask &= ~(1 << filter->index);
3860 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3863 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3864 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3865 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3870 * igb_remove_2tuple_filter - remove a 2tuple filter
3873 * dev: Pointer to struct rte_eth_dev.
3874 * ntuple_filter: ponter to the filter that will be removed.
3877 * - On success, zero.
3878 * - On failure, a negative value.
3881 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3882 struct rte_eth_ntuple_filter *ntuple_filter)
3884 struct e1000_filter_info *filter_info =
3885 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3886 struct e1000_2tuple_filter_info filter_2tuple;
3887 struct e1000_2tuple_filter *filter;
3890 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3891 ret = ntuple_filter_to_2tuple(ntuple_filter,
3896 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3898 if (filter == NULL) {
3899 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3903 igb_delete_2tuple_filter(dev, filter);
3908 /* inject a igb flex filter to HW */
3910 igb_inject_flex_filter(struct rte_eth_dev *dev,
3911 struct e1000_flex_filter *filter)
3913 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3914 uint32_t wufc, queueing;
3918 wufc = E1000_READ_REG(hw, E1000_WUFC);
3919 if (filter->index < E1000_MAX_FHFT)
3920 reg_off = E1000_FHFT(filter->index);
3922 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3924 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3925 (E1000_WUFC_FLX0 << filter->index));
3926 queueing = filter->filter_info.len |
3927 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3928 (filter->filter_info.priority <<
3929 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3930 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3933 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3934 E1000_WRITE_REG(hw, reg_off,
3935 filter->filter_info.dwords[j]);
3936 reg_off += sizeof(uint32_t);
3937 E1000_WRITE_REG(hw, reg_off,
3938 filter->filter_info.dwords[++j]);
3939 reg_off += sizeof(uint32_t);
3940 E1000_WRITE_REG(hw, reg_off,
3941 (uint32_t)filter->filter_info.mask[i]);
3942 reg_off += sizeof(uint32_t) * 2;
3947 static inline struct e1000_flex_filter *
3948 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3949 struct e1000_flex_filter_info *key)
3951 struct e1000_flex_filter *it;
3953 TAILQ_FOREACH(it, filter_list, entries) {
3954 if (memcmp(key, &it->filter_info,
3955 sizeof(struct e1000_flex_filter_info)) == 0)
3962 /* remove a flex byte filter
3964 * dev: Pointer to struct rte_eth_dev.
3965 * filter: the pointer of the filter will be removed.
3968 igb_remove_flex_filter(struct rte_eth_dev *dev,
3969 struct e1000_flex_filter *filter)
3971 struct e1000_filter_info *filter_info =
3972 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3973 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3977 wufc = E1000_READ_REG(hw, E1000_WUFC);
3978 if (filter->index < E1000_MAX_FHFT)
3979 reg_off = E1000_FHFT(filter->index);
3981 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3983 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3984 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3986 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3987 (~(E1000_WUFC_FLX0 << filter->index)));
3989 filter_info->flex_mask &= ~(1 << filter->index);
3990 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3995 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3996 struct rte_eth_flex_filter *filter,
3999 struct e1000_filter_info *filter_info =
4000 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4001 struct e1000_flex_filter *flex_filter, *it;
4005 flex_filter = rte_zmalloc("e1000_flex_filter",
4006 sizeof(struct e1000_flex_filter), 0);
4007 if (flex_filter == NULL)
4010 flex_filter->filter_info.len = filter->len;
4011 flex_filter->filter_info.priority = filter->priority;
4012 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4013 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4015 /* reverse bits in flex filter's mask*/
4016 for (shift = 0; shift < CHAR_BIT; shift++) {
4017 if (filter->mask[i] & (0x01 << shift))
4018 mask |= (0x80 >> shift);
4020 flex_filter->filter_info.mask[i] = mask;
4023 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4024 &flex_filter->filter_info);
4025 if (it == NULL && !add) {
4026 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4027 rte_free(flex_filter);
4030 if (it != NULL && add) {
4031 PMD_DRV_LOG(ERR, "filter exists.");
4032 rte_free(flex_filter);
4037 flex_filter->queue = filter->queue;
4039 * look for an unused flex filter index
4040 * and insert the filter into the list.
4042 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4043 if (!(filter_info->flex_mask & (1 << i))) {
4044 filter_info->flex_mask |= 1 << i;
4045 flex_filter->index = i;
4046 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4052 if (i >= E1000_MAX_FLEX_FILTERS) {
4053 PMD_DRV_LOG(ERR, "flex filters are full.");
4054 rte_free(flex_filter);
4058 igb_inject_flex_filter(dev, flex_filter);
4061 igb_remove_flex_filter(dev, it);
4062 rte_free(flex_filter);
4069 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4070 struct rte_eth_flex_filter *filter)
4072 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4073 struct e1000_filter_info *filter_info =
4074 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4075 struct e1000_flex_filter flex_filter, *it;
4076 uint32_t wufc, queueing, wufc_en = 0;
4078 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4079 flex_filter.filter_info.len = filter->len;
4080 flex_filter.filter_info.priority = filter->priority;
4081 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4082 memcpy(flex_filter.filter_info.mask, filter->mask,
4083 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4085 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4086 &flex_filter.filter_info);
4088 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4092 wufc = E1000_READ_REG(hw, E1000_WUFC);
4093 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4095 if ((wufc & wufc_en) == wufc_en) {
4096 uint32_t reg_off = 0;
4097 if (it->index < E1000_MAX_FHFT)
4098 reg_off = E1000_FHFT(it->index);
4100 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4102 queueing = E1000_READ_REG(hw,
4103 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4104 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4105 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4106 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4107 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4108 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4115 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4116 enum rte_filter_op filter_op,
4119 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4120 struct rte_eth_flex_filter *filter;
4123 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4125 if (filter_op == RTE_ETH_FILTER_NOP)
4129 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4134 filter = (struct rte_eth_flex_filter *)arg;
4135 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4136 || filter->len % sizeof(uint64_t) != 0) {
4137 PMD_DRV_LOG(ERR, "filter's length is out of range");
4140 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4141 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4145 switch (filter_op) {
4146 case RTE_ETH_FILTER_ADD:
4147 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4149 case RTE_ETH_FILTER_DELETE:
4150 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4152 case RTE_ETH_FILTER_GET:
4153 ret = eth_igb_get_flex_filter(dev, filter);
4156 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4164 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4166 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4167 struct e1000_5tuple_filter_info *filter_info)
4169 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4171 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4172 return -EINVAL; /* filter index is out of range. */
4173 if (filter->tcp_flags > TCP_FLAG_ALL)
4174 return -EINVAL; /* flags is invalid. */
4176 switch (filter->dst_ip_mask) {
4178 filter_info->dst_ip_mask = 0;
4179 filter_info->dst_ip = filter->dst_ip;
4182 filter_info->dst_ip_mask = 1;
4185 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4189 switch (filter->src_ip_mask) {
4191 filter_info->src_ip_mask = 0;
4192 filter_info->src_ip = filter->src_ip;
4195 filter_info->src_ip_mask = 1;
4198 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4202 switch (filter->dst_port_mask) {
4204 filter_info->dst_port_mask = 0;
4205 filter_info->dst_port = filter->dst_port;
4208 filter_info->dst_port_mask = 1;
4211 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4215 switch (filter->src_port_mask) {
4217 filter_info->src_port_mask = 0;
4218 filter_info->src_port = filter->src_port;
4221 filter_info->src_port_mask = 1;
4224 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4228 switch (filter->proto_mask) {
4230 filter_info->proto_mask = 0;
4231 filter_info->proto = filter->proto;
4234 filter_info->proto_mask = 1;
4237 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4241 filter_info->priority = (uint8_t)filter->priority;
4242 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4243 filter_info->tcp_flags = filter->tcp_flags;
4245 filter_info->tcp_flags = 0;
4250 static inline struct e1000_5tuple_filter *
4251 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4252 struct e1000_5tuple_filter_info *key)
4254 struct e1000_5tuple_filter *it;
4256 TAILQ_FOREACH(it, filter_list, entries) {
4257 if (memcmp(key, &it->filter_info,
4258 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4265 /* inject a igb 5-tuple filter to HW */
4267 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4268 struct e1000_5tuple_filter *filter)
4270 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4271 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4272 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4276 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4277 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4278 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4279 if (filter->filter_info.dst_ip_mask == 0)
4280 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4281 if (filter->filter_info.src_port_mask == 0)
4282 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4283 if (filter->filter_info.proto_mask == 0)
4284 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4285 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4286 E1000_FTQF_QUEUE_MASK;
4287 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4288 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4289 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4290 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4292 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4293 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4295 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4296 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4297 imir |= E1000_IMIR_PORT_BP;
4299 imir &= ~E1000_IMIR_PORT_BP;
4300 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4302 /* tcp flags bits setting. */
4303 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4304 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4305 imir_ext |= E1000_IMIREXT_CTRL_URG;
4306 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4307 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4308 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4309 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4310 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4311 imir_ext |= E1000_IMIREXT_CTRL_RST;
4312 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4313 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4314 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4315 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4317 imir_ext |= E1000_IMIREXT_CTRL_BP;
4319 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4320 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4324 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4327 * dev: Pointer to struct rte_eth_dev.
4328 * ntuple_filter: ponter to the filter that will be added.
4331 * - On success, zero.
4332 * - On failure, a negative value.
4335 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4336 struct rte_eth_ntuple_filter *ntuple_filter)
4338 struct e1000_filter_info *filter_info =
4339 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4340 struct e1000_5tuple_filter *filter;
4344 filter = rte_zmalloc("e1000_5tuple_filter",
4345 sizeof(struct e1000_5tuple_filter), 0);
4349 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4350 &filter->filter_info);
4356 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4357 &filter->filter_info) != NULL) {
4358 PMD_DRV_LOG(ERR, "filter exists.");
4362 filter->queue = ntuple_filter->queue;
4365 * look for an unused 5tuple filter index,
4366 * and insert the filter to list.
4368 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4369 if (!(filter_info->fivetuple_mask & (1 << i))) {
4370 filter_info->fivetuple_mask |= 1 << i;
4372 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4378 if (i >= E1000_MAX_FTQF_FILTERS) {
4379 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4384 igb_inject_5tuple_filter_82576(dev, filter);
4389 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4390 struct e1000_5tuple_filter *filter)
4392 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4393 struct e1000_filter_info *filter_info =
4394 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4396 filter_info->fivetuple_mask &= ~(1 << filter->index);
4397 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4400 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4401 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4402 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4403 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4404 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4405 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4406 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4411 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4414 * dev: Pointer to struct rte_eth_dev.
4415 * ntuple_filter: ponter to the filter that will be removed.
4418 * - On success, zero.
4419 * - On failure, a negative value.
4422 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4423 struct rte_eth_ntuple_filter *ntuple_filter)
4425 struct e1000_filter_info *filter_info =
4426 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4427 struct e1000_5tuple_filter_info filter_5tuple;
4428 struct e1000_5tuple_filter *filter;
4431 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4432 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4437 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4439 if (filter == NULL) {
4440 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4444 igb_delete_5tuple_filter_82576(dev, filter);
4450 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4453 struct e1000_hw *hw;
4454 struct rte_eth_dev_info dev_info;
4455 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4458 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4460 #ifdef RTE_LIBRTE_82571_SUPPORT
4461 /* XXX: not bigger than max_rx_pktlen */
4462 if (hw->mac.type == e1000_82571)
4465 eth_igb_infos_get(dev, &dev_info);
4467 /* check that mtu is within the allowed range */
4468 if ((mtu < ETHER_MIN_MTU) ||
4469 (frame_size > dev_info.max_rx_pktlen))
4472 /* refuse mtu that requires the support of scattered packets when this
4473 * feature has not been enabled before. */
4474 if (!dev->data->scattered_rx &&
4475 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4478 rctl = E1000_READ_REG(hw, E1000_RCTL);
4480 /* switch to jumbo mode if needed */
4481 if (frame_size > ETHER_MAX_LEN) {
4482 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4483 rctl |= E1000_RCTL_LPE;
4485 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4486 rctl &= ~E1000_RCTL_LPE;
4488 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4490 /* update max frame size */
4491 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4493 E1000_WRITE_REG(hw, E1000_RLPML,
4494 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4500 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4503 * dev: Pointer to struct rte_eth_dev.
4504 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4505 * add: if true, add filter, if false, remove filter
4508 * - On success, zero.
4509 * - On failure, a negative value.
4512 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4513 struct rte_eth_ntuple_filter *ntuple_filter,
4516 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4519 switch (ntuple_filter->flags) {
4520 case RTE_5TUPLE_FLAGS:
4521 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4522 if (hw->mac.type != e1000_82576)
4525 ret = igb_add_5tuple_filter_82576(dev,
4528 ret = igb_remove_5tuple_filter_82576(dev,
4531 case RTE_2TUPLE_FLAGS:
4532 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4533 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4534 hw->mac.type != e1000_i210 &&
4535 hw->mac.type != e1000_i211)
4538 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4540 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4551 * igb_get_ntuple_filter - get a ntuple filter
4554 * dev: Pointer to struct rte_eth_dev.
4555 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4558 * - On success, zero.
4559 * - On failure, a negative value.
4562 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4563 struct rte_eth_ntuple_filter *ntuple_filter)
4565 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4566 struct e1000_filter_info *filter_info =
4567 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4568 struct e1000_5tuple_filter_info filter_5tuple;
4569 struct e1000_2tuple_filter_info filter_2tuple;
4570 struct e1000_5tuple_filter *p_5tuple_filter;
4571 struct e1000_2tuple_filter *p_2tuple_filter;
4574 switch (ntuple_filter->flags) {
4575 case RTE_5TUPLE_FLAGS:
4576 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4577 if (hw->mac.type != e1000_82576)
4579 memset(&filter_5tuple,
4581 sizeof(struct e1000_5tuple_filter_info));
4582 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4586 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4587 &filter_info->fivetuple_list,
4589 if (p_5tuple_filter == NULL) {
4590 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4593 ntuple_filter->queue = p_5tuple_filter->queue;
4595 case RTE_2TUPLE_FLAGS:
4596 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4597 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4599 memset(&filter_2tuple,
4601 sizeof(struct e1000_2tuple_filter_info));
4602 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4605 p_2tuple_filter = igb_2tuple_filter_lookup(
4606 &filter_info->twotuple_list,
4608 if (p_2tuple_filter == NULL) {
4609 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4612 ntuple_filter->queue = p_2tuple_filter->queue;
4623 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4624 * @dev: pointer to rte_eth_dev structure
4625 * @filter_op:operation will be taken.
4626 * @arg: a pointer to specific structure corresponding to the filter_op
4629 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4630 enum rte_filter_op filter_op,
4633 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4636 MAC_TYPE_FILTER_SUP(hw->mac.type);
4638 if (filter_op == RTE_ETH_FILTER_NOP)
4642 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4647 switch (filter_op) {
4648 case RTE_ETH_FILTER_ADD:
4649 ret = igb_add_del_ntuple_filter(dev,
4650 (struct rte_eth_ntuple_filter *)arg,
4653 case RTE_ETH_FILTER_DELETE:
4654 ret = igb_add_del_ntuple_filter(dev,
4655 (struct rte_eth_ntuple_filter *)arg,
4658 case RTE_ETH_FILTER_GET:
4659 ret = igb_get_ntuple_filter(dev,
4660 (struct rte_eth_ntuple_filter *)arg);
4663 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4671 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4676 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4677 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4678 (filter_info->ethertype_mask & (1 << i)))
4685 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4686 uint16_t ethertype, uint32_t etqf)
4690 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4691 if (!(filter_info->ethertype_mask & (1 << i))) {
4692 filter_info->ethertype_mask |= 1 << i;
4693 filter_info->ethertype_filters[i].ethertype = ethertype;
4694 filter_info->ethertype_filters[i].etqf = etqf;
4702 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4705 if (idx >= E1000_MAX_ETQF_FILTERS)
4707 filter_info->ethertype_mask &= ~(1 << idx);
4708 filter_info->ethertype_filters[idx].ethertype = 0;
4709 filter_info->ethertype_filters[idx].etqf = 0;
4715 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4716 struct rte_eth_ethertype_filter *filter,
4719 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4720 struct e1000_filter_info *filter_info =
4721 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4725 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4726 filter->ether_type == ETHER_TYPE_IPv6) {
4727 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4728 " ethertype filter.", filter->ether_type);
4732 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4733 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4736 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4737 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4741 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4742 if (ret >= 0 && add) {
4743 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4744 filter->ether_type);
4747 if (ret < 0 && !add) {
4748 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4749 filter->ether_type);
4754 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4755 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4756 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4757 ret = igb_ethertype_filter_insert(filter_info,
4758 filter->ether_type, etqf);
4760 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4764 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4768 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4769 E1000_WRITE_FLUSH(hw);
4775 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4776 struct rte_eth_ethertype_filter *filter)
4778 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4779 struct e1000_filter_info *filter_info =
4780 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4784 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4786 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4787 filter->ether_type);
4791 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4792 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4793 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4795 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4796 E1000_ETQF_QUEUE_SHIFT;
4804 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4805 * @dev: pointer to rte_eth_dev structure
4806 * @filter_op:operation will be taken.
4807 * @arg: a pointer to specific structure corresponding to the filter_op
4810 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4811 enum rte_filter_op filter_op,
4814 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4817 MAC_TYPE_FILTER_SUP(hw->mac.type);
4819 if (filter_op == RTE_ETH_FILTER_NOP)
4823 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4828 switch (filter_op) {
4829 case RTE_ETH_FILTER_ADD:
4830 ret = igb_add_del_ethertype_filter(dev,
4831 (struct rte_eth_ethertype_filter *)arg,
4834 case RTE_ETH_FILTER_DELETE:
4835 ret = igb_add_del_ethertype_filter(dev,
4836 (struct rte_eth_ethertype_filter *)arg,
4839 case RTE_ETH_FILTER_GET:
4840 ret = igb_get_ethertype_filter(dev,
4841 (struct rte_eth_ethertype_filter *)arg);
4844 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4852 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4853 enum rte_filter_type filter_type,
4854 enum rte_filter_op filter_op,
4859 switch (filter_type) {
4860 case RTE_ETH_FILTER_NTUPLE:
4861 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4863 case RTE_ETH_FILTER_ETHERTYPE:
4864 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4866 case RTE_ETH_FILTER_SYN:
4867 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4869 case RTE_ETH_FILTER_FLEXIBLE:
4870 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4872 case RTE_ETH_FILTER_GENERIC:
4873 if (filter_op != RTE_ETH_FILTER_GET)
4875 *(const void **)arg = &igb_flow_ops;
4878 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4887 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4888 struct ether_addr *mc_addr_set,
4889 uint32_t nb_mc_addr)
4891 struct e1000_hw *hw;
4893 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4894 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4899 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4901 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4902 uint64_t systime_cycles;
4904 switch (hw->mac.type) {
4908 * Need to read System Time Residue Register to be able
4909 * to read the other two registers.
4911 E1000_READ_REG(hw, E1000_SYSTIMR);
4912 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4913 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4914 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4921 * Need to read System Time Residue Register to be able
4922 * to read the other two registers.
4924 E1000_READ_REG(hw, E1000_SYSTIMR);
4925 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4926 /* Only the 8 LSB are valid. */
4927 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4931 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4932 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4937 return systime_cycles;
4941 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4943 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4944 uint64_t rx_tstamp_cycles;
4946 switch (hw->mac.type) {
4949 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4950 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4951 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4957 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4958 /* Only the 8 LSB are valid. */
4959 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4963 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4964 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4969 return rx_tstamp_cycles;
4973 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4975 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4976 uint64_t tx_tstamp_cycles;
4978 switch (hw->mac.type) {
4981 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4982 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4983 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4989 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4990 /* Only the 8 LSB are valid. */
4991 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4995 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4996 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5001 return tx_tstamp_cycles;
5005 igb_start_timecounters(struct rte_eth_dev *dev)
5007 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5008 struct e1000_adapter *adapter =
5009 (struct e1000_adapter *)dev->data->dev_private;
5010 uint32_t incval = 1;
5012 uint64_t mask = E1000_CYCLECOUNTER_MASK;
5014 switch (hw->mac.type) {
5018 /* 32 LSB bits + 8 MSB bits = 40 bits */
5019 mask = (1ULL << 40) - 1;
5024 * Start incrementing the register
5025 * used to timestamp PTP packets.
5027 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5030 incval = E1000_INCVALUE_82576;
5031 shift = IGB_82576_TSYNC_SHIFT;
5032 E1000_WRITE_REG(hw, E1000_TIMINCA,
5033 E1000_INCPERIOD_82576 | incval);
5040 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5041 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5042 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5044 adapter->systime_tc.cc_mask = mask;
5045 adapter->systime_tc.cc_shift = shift;
5046 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5048 adapter->rx_tstamp_tc.cc_mask = mask;
5049 adapter->rx_tstamp_tc.cc_shift = shift;
5050 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5052 adapter->tx_tstamp_tc.cc_mask = mask;
5053 adapter->tx_tstamp_tc.cc_shift = shift;
5054 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5058 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5060 struct e1000_adapter *adapter =
5061 (struct e1000_adapter *)dev->data->dev_private;
5063 adapter->systime_tc.nsec += delta;
5064 adapter->rx_tstamp_tc.nsec += delta;
5065 adapter->tx_tstamp_tc.nsec += delta;
5071 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5074 struct e1000_adapter *adapter =
5075 (struct e1000_adapter *)dev->data->dev_private;
5077 ns = rte_timespec_to_ns(ts);
5079 /* Set the timecounters to a new value. */
5080 adapter->systime_tc.nsec = ns;
5081 adapter->rx_tstamp_tc.nsec = ns;
5082 adapter->tx_tstamp_tc.nsec = ns;
5088 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5090 uint64_t ns, systime_cycles;
5091 struct e1000_adapter *adapter =
5092 (struct e1000_adapter *)dev->data->dev_private;
5094 systime_cycles = igb_read_systime_cyclecounter(dev);
5095 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5096 *ts = rte_ns_to_timespec(ns);
5102 igb_timesync_enable(struct rte_eth_dev *dev)
5104 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5108 /* Stop the timesync system time. */
5109 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5110 /* Reset the timesync system time value. */
5111 switch (hw->mac.type) {
5117 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5120 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5121 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5124 /* Not supported. */
5128 /* Enable system time for it isn't on by default. */
5129 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5130 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5131 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5133 igb_start_timecounters(dev);
5135 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5136 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5138 E1000_ETQF_FILTER_ENABLE |
5141 /* Enable timestamping of received PTP packets. */
5142 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5143 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5144 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5146 /* Enable Timestamping of transmitted PTP packets. */
5147 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5148 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5149 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5155 igb_timesync_disable(struct rte_eth_dev *dev)
5157 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5160 /* Disable timestamping of transmitted PTP packets. */
5161 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5162 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5163 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5165 /* Disable timestamping of received PTP packets. */
5166 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5167 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5168 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5170 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5171 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5173 /* Stop incrementating the System Time registers. */
5174 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5180 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5181 struct timespec *timestamp,
5182 uint32_t flags __rte_unused)
5184 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5185 struct e1000_adapter *adapter =
5186 (struct e1000_adapter *)dev->data->dev_private;
5187 uint32_t tsync_rxctl;
5188 uint64_t rx_tstamp_cycles;
5191 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5192 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5195 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5196 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5197 *timestamp = rte_ns_to_timespec(ns);
5203 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5204 struct timespec *timestamp)
5206 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5207 struct e1000_adapter *adapter =
5208 (struct e1000_adapter *)dev->data->dev_private;
5209 uint32_t tsync_txctl;
5210 uint64_t tx_tstamp_cycles;
5213 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5214 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5217 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5218 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5219 *timestamp = rte_ns_to_timespec(ns);
5225 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5229 const struct reg_info *reg_group;
5231 while ((reg_group = igb_regs[g_ind++]))
5232 count += igb_reg_group_count(reg_group);
5238 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5242 const struct reg_info *reg_group;
5244 while ((reg_group = igbvf_regs[g_ind++]))
5245 count += igb_reg_group_count(reg_group);
5251 eth_igb_get_regs(struct rte_eth_dev *dev,
5252 struct rte_dev_reg_info *regs)
5254 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5255 uint32_t *data = regs->data;
5258 const struct reg_info *reg_group;
5261 regs->length = eth_igb_get_reg_length(dev);
5262 regs->width = sizeof(uint32_t);
5266 /* Support only full register dump */
5267 if ((regs->length == 0) ||
5268 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5269 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5271 while ((reg_group = igb_regs[g_ind++]))
5272 count += igb_read_regs_group(dev, &data[count],
5281 igbvf_get_regs(struct rte_eth_dev *dev,
5282 struct rte_dev_reg_info *regs)
5284 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5285 uint32_t *data = regs->data;
5288 const struct reg_info *reg_group;
5291 regs->length = igbvf_get_reg_length(dev);
5292 regs->width = sizeof(uint32_t);
5296 /* Support only full register dump */
5297 if ((regs->length == 0) ||
5298 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5299 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5301 while ((reg_group = igbvf_regs[g_ind++]))
5302 count += igb_read_regs_group(dev, &data[count],
5311 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5313 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5315 /* Return unit is byte count */
5316 return hw->nvm.word_size * 2;
5320 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5321 struct rte_dev_eeprom_info *in_eeprom)
5323 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5324 struct e1000_nvm_info *nvm = &hw->nvm;
5325 uint16_t *data = in_eeprom->data;
5328 first = in_eeprom->offset >> 1;
5329 length = in_eeprom->length >> 1;
5330 if ((first >= hw->nvm.word_size) ||
5331 ((first + length) >= hw->nvm.word_size))
5334 in_eeprom->magic = hw->vendor_id |
5335 ((uint32_t)hw->device_id << 16);
5337 if ((nvm->ops.read) == NULL)
5340 return nvm->ops.read(hw, first, length, data);
5344 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5345 struct rte_dev_eeprom_info *in_eeprom)
5347 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5348 struct e1000_nvm_info *nvm = &hw->nvm;
5349 uint16_t *data = in_eeprom->data;
5352 first = in_eeprom->offset >> 1;
5353 length = in_eeprom->length >> 1;
5354 if ((first >= hw->nvm.word_size) ||
5355 ((first + length) >= hw->nvm.word_size))
5358 in_eeprom->magic = (uint32_t)hw->vendor_id |
5359 ((uint32_t)hw->device_id << 16);
5361 if ((nvm->ops.write) == NULL)
5363 return nvm->ops.write(hw, first, length, data);
5367 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5369 struct e1000_hw *hw =
5370 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5371 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5372 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5373 uint32_t vec = E1000_MISC_VEC_ID;
5375 if (rte_intr_allow_others(intr_handle))
5376 vec = E1000_RX_VEC_START;
5378 uint32_t mask = 1 << (queue_id + vec);
5380 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5381 E1000_WRITE_FLUSH(hw);
5387 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5389 struct e1000_hw *hw =
5390 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5391 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5392 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5393 uint32_t vec = E1000_MISC_VEC_ID;
5395 if (rte_intr_allow_others(intr_handle))
5396 vec = E1000_RX_VEC_START;
5398 uint32_t mask = 1 << (queue_id + vec);
5401 regval = E1000_READ_REG(hw, E1000_EIMS);
5402 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5403 E1000_WRITE_FLUSH(hw);
5405 rte_intr_enable(intr_handle);
5411 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5412 uint8_t index, uint8_t offset)
5414 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5417 val &= ~((uint32_t)0xFF << offset);
5419 /* write vector and valid bit */
5420 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5422 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5426 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5427 uint8_t queue, uint8_t msix_vector)
5431 if (hw->mac.type == e1000_82575) {
5433 tmp = E1000_EICR_RX_QUEUE0 << queue;
5434 else if (direction == 1)
5435 tmp = E1000_EICR_TX_QUEUE0 << queue;
5436 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5437 } else if (hw->mac.type == e1000_82576) {
5438 if ((direction == 0) || (direction == 1))
5439 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5440 ((queue & 0x8) << 1) +
5442 } else if ((hw->mac.type == e1000_82580) ||
5443 (hw->mac.type == e1000_i350) ||
5444 (hw->mac.type == e1000_i354) ||
5445 (hw->mac.type == e1000_i210) ||
5446 (hw->mac.type == e1000_i211)) {
5447 if ((direction == 0) || (direction == 1))
5448 eth_igb_write_ivar(hw, msix_vector,
5450 ((queue & 0x1) << 4) +
5455 /* Sets up the hardware to generate MSI-X interrupts properly
5457 * board private structure
5460 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5463 uint32_t tmpval, regval, intr_mask;
5464 struct e1000_hw *hw =
5465 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5466 uint32_t vec = E1000_MISC_VEC_ID;
5467 uint32_t base = E1000_MISC_VEC_ID;
5468 uint32_t misc_shift = 0;
5469 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5470 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5472 /* won't configure msix register if no mapping is done
5473 * between intr vector and event fd
5475 if (!rte_intr_dp_is_en(intr_handle))
5478 if (rte_intr_allow_others(intr_handle)) {
5479 vec = base = E1000_RX_VEC_START;
5483 /* set interrupt vector for other causes */
5484 if (hw->mac.type == e1000_82575) {
5485 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5486 /* enable MSI-X PBA support */
5487 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5489 /* Auto-Mask interrupts upon ICR read */
5490 tmpval |= E1000_CTRL_EXT_EIAME;
5491 tmpval |= E1000_CTRL_EXT_IRCA;
5493 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5495 /* enable msix_other interrupt */
5496 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5497 regval = E1000_READ_REG(hw, E1000_EIAC);
5498 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5499 regval = E1000_READ_REG(hw, E1000_EIAM);
5500 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5501 } else if ((hw->mac.type == e1000_82576) ||
5502 (hw->mac.type == e1000_82580) ||
5503 (hw->mac.type == e1000_i350) ||
5504 (hw->mac.type == e1000_i354) ||
5505 (hw->mac.type == e1000_i210) ||
5506 (hw->mac.type == e1000_i211)) {
5507 /* turn on MSI-X capability first */
5508 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5509 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5511 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5513 regval = E1000_READ_REG(hw, E1000_EIAC);
5514 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5516 /* enable msix_other interrupt */
5517 regval = E1000_READ_REG(hw, E1000_EIMS);
5518 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5519 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5520 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5523 /* use EIAM to auto-mask when MSI-X interrupt
5524 * is asserted, this saves a register write for every interrupt
5526 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5528 regval = E1000_READ_REG(hw, E1000_EIAM);
5529 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5531 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5532 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5533 intr_handle->intr_vec[queue_id] = vec;
5534 if (vec < base + intr_handle->nb_efd - 1)
5538 E1000_WRITE_FLUSH(hw);
5541 /* restore n-tuple filter */
5543 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5545 struct e1000_filter_info *filter_info =
5546 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5547 struct e1000_5tuple_filter *p_5tuple;
5548 struct e1000_2tuple_filter *p_2tuple;
5550 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5551 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5554 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5555 igb_inject_2uple_filter(dev, p_2tuple);
5559 /* restore SYN filter */
5561 igb_syn_filter_restore(struct rte_eth_dev *dev)
5563 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5564 struct e1000_filter_info *filter_info =
5565 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5568 synqf = filter_info->syn_info;
5570 if (synqf & E1000_SYN_FILTER_ENABLE) {
5571 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5572 E1000_WRITE_FLUSH(hw);
5576 /* restore ethernet type filter */
5578 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5580 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5581 struct e1000_filter_info *filter_info =
5582 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5585 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5586 if (filter_info->ethertype_mask & (1 << i)) {
5587 E1000_WRITE_REG(hw, E1000_ETQF(i),
5588 filter_info->ethertype_filters[i].etqf);
5589 E1000_WRITE_FLUSH(hw);
5594 /* restore flex byte filter */
5596 igb_flex_filter_restore(struct rte_eth_dev *dev)
5598 struct e1000_filter_info *filter_info =
5599 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5600 struct e1000_flex_filter *flex_filter;
5602 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5603 igb_inject_flex_filter(dev, flex_filter);
5607 /* restore rss filter */
5609 igb_rss_filter_restore(struct rte_eth_dev *dev)
5611 struct e1000_filter_info *filter_info =
5612 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5614 if (filter_info->rss_info.num)
5615 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5618 /* restore all types filter */
5620 igb_filter_restore(struct rte_eth_dev *dev)
5622 igb_ntuple_filter_restore(dev);
5623 igb_ethertype_filter_restore(dev);
5624 igb_syn_filter_restore(dev);
5625 igb_flex_filter_restore(dev);
5626 igb_rss_filter_restore(dev);
5631 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5632 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5633 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5634 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5635 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5636 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");