1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
11 #include <rte_string_fns.h>
12 #include <rte_common.h>
13 #include <rte_interrupts.h>
14 #include <rte_byteorder.h>
16 #include <rte_debug.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memory.h>
24 #include <rte_malloc.h>
27 #include "e1000_logs.h"
28 #include "base/e1000_api.h"
29 #include "e1000_ethdev.h"
33 * Default values for port configuration
35 #define IGB_DEFAULT_RX_FREE_THRESH 32
37 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
38 #define IGB_DEFAULT_RX_HTHRESH 8
39 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
41 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
42 #define IGB_DEFAULT_TX_HTHRESH 1
43 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
45 /* Bit shift and mask */
46 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
47 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
48 #define IGB_8_BIT_WIDTH CHAR_BIT
49 #define IGB_8_BIT_MASK UINT8_MAX
51 /* Additional timesync values. */
52 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
53 #define E1000_ETQF_FILTER_1588 3
54 #define IGB_82576_TSYNC_SHIFT 16
55 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
56 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
59 #define E1000_VTIVAR_MISC 0x01740
60 #define E1000_VTIVAR_MISC_MASK 0xFF
61 #define E1000_VTIVAR_VALID 0x80
62 #define E1000_VTIVAR_MISC_MAILBOX 0
63 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
65 /* External VLAN Enable bit mask */
66 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
68 /* External VLAN Ether Type bit mask and shift */
69 #define E1000_VET_VET_EXT 0xFFFF0000
70 #define E1000_VET_VET_EXT_SHIFT 16
72 /* MSI-X other interrupt vector */
73 #define IGB_MSIX_OTHER_INTR_VEC 0
75 static int eth_igb_configure(struct rte_eth_dev *dev);
76 static int eth_igb_start(struct rte_eth_dev *dev);
77 static void eth_igb_stop(struct rte_eth_dev *dev);
78 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
79 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
80 static void eth_igb_close(struct rte_eth_dev *dev);
81 static int eth_igb_reset(struct rte_eth_dev *dev);
82 static int eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
83 static int eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
84 static int eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
85 static int eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
86 static int eth_igb_link_update(struct rte_eth_dev *dev,
87 int wait_to_complete);
88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
89 struct rte_eth_stats *rte_stats);
90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
91 struct rte_eth_xstat *xstats, unsigned n);
92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
94 uint64_t *values, unsigned int n);
95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
96 struct rte_eth_xstat_name *xstats_names,
98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
99 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
104 char *fw_version, size_t fw_size);
105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
106 struct rte_eth_dev_info *dev_info);
107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
111 struct rte_eth_fc_conf *fc_conf);
112 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
113 struct rte_eth_fc_conf *fc_conf);
114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
118 struct rte_intr_handle *handle);
119 static void eth_igb_interrupt_handler(void *param);
120 static int igb_hardware_init(struct e1000_hw *hw);
121 static void igb_hw_control_acquire(struct e1000_hw *hw);
122 static void igb_hw_control_release(struct e1000_hw *hw);
123 static void igb_init_manageability(struct e1000_hw *hw);
124 static void igb_release_manageability(struct e1000_hw *hw);
126 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
129 uint16_t vlan_id, int on);
130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
131 enum rte_vlan_type vlan_type,
133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
142 static int eth_igb_led_on(struct rte_eth_dev *dev);
143 static int eth_igb_led_off(struct rte_eth_dev *dev);
145 static void igb_intr_disable(struct rte_eth_dev *dev);
146 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
148 struct rte_ether_addr *mac_addr,
149 uint32_t index, uint32_t pool);
150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
152 struct rte_ether_addr *addr);
154 static void igbvf_intr_disable(struct e1000_hw *hw);
155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
156 static int igbvf_dev_start(struct rte_eth_dev *dev);
157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
158 static void igbvf_dev_close(struct rte_eth_dev *dev);
159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
163 static int eth_igbvf_link_update(struct e1000_hw *hw);
164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
165 struct rte_eth_stats *rte_stats);
166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
167 struct rte_eth_xstat *xstats, unsigned n);
168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
169 struct rte_eth_xstat_name *xstats_names,
171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
173 uint16_t vlan_id, int on);
174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
177 struct rte_ether_addr *addr);
178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
179 static int igbvf_get_regs(struct rte_eth_dev *dev,
180 struct rte_dev_reg_info *regs);
182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
183 struct rte_eth_rss_reta_entry64 *reta_conf,
185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
186 struct rte_eth_rss_reta_entry64 *reta_conf,
189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
190 struct rte_eth_syn_filter *filter);
191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
192 enum rte_filter_op filter_op,
194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
195 struct rte_eth_ntuple_filter *ntuple_filter);
196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
197 struct rte_eth_ntuple_filter *ntuple_filter);
198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
199 struct rte_eth_flex_filter *filter);
200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
201 enum rte_filter_op filter_op,
203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
204 struct rte_eth_ntuple_filter *ntuple_filter);
205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
206 struct rte_eth_ntuple_filter *ntuple_filter);
207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
208 struct rte_eth_ntuple_filter *filter);
209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
210 enum rte_filter_op filter_op,
212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
213 enum rte_filter_op filter_op,
215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
216 struct rte_eth_ethertype_filter *filter);
217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
218 enum rte_filter_type filter_type,
219 enum rte_filter_op filter_op,
221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
223 struct rte_dev_reg_info *regs);
224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
226 struct rte_dev_eeprom_info *eeprom);
227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
228 struct rte_dev_eeprom_info *eeprom);
229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
230 struct rte_eth_dev_module_info *modinfo);
231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
232 struct rte_dev_eeprom_info *info);
233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
234 struct rte_ether_addr *mc_addr_set,
235 uint32_t nb_mc_addr);
236 static int igb_timesync_enable(struct rte_eth_dev *dev);
237 static int igb_timesync_disable(struct rte_eth_dev *dev);
238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
239 struct timespec *timestamp,
241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
242 struct timespec *timestamp);
243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
245 struct timespec *timestamp);
246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
247 const struct timespec *timestamp);
248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
253 uint8_t queue, uint8_t msix_vector);
254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
255 uint8_t index, uint8_t offset);
256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
257 static void eth_igbvf_interrupt_handler(void *param);
258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
259 static int igb_filter_restore(struct rte_eth_dev *dev);
262 * Define VF Stats MACRO for Non "cleared on read" register
264 #define UPDATE_VF_STAT(reg, last, cur) \
266 u32 latest = E1000_READ_REG(hw, reg); \
267 cur += (latest - last) & UINT_MAX; \
271 #define IGB_FC_PAUSE_TIME 0x0680
272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
275 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
280 * The set of PCI devices this driver supports
282 static const struct rte_pci_id pci_id_igb_map[] = {
283 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
284 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
285 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
286 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
287 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
288 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
289 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
290 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
292 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
293 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
294 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
296 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
297 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
298 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
299 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
300 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
301 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
303 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
304 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
305 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
306 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
307 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
308 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
324 { .vendor_id = 0, /* sentinel */ },
328 * The set of PCI devices this driver supports (for 82576&I350 VF)
330 static const struct rte_pci_id pci_id_igbvf_map[] = {
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
335 { .vendor_id = 0, /* sentinel */ },
338 static const struct rte_eth_desc_lim rx_desc_lim = {
339 .nb_max = E1000_MAX_RING_DESC,
340 .nb_min = E1000_MIN_RING_DESC,
341 .nb_align = IGB_RXD_ALIGN,
344 static const struct rte_eth_desc_lim tx_desc_lim = {
345 .nb_max = E1000_MAX_RING_DESC,
346 .nb_min = E1000_MIN_RING_DESC,
347 .nb_align = IGB_RXD_ALIGN,
348 .nb_seg_max = IGB_TX_MAX_SEG,
349 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
352 static const struct eth_dev_ops eth_igb_ops = {
353 .dev_configure = eth_igb_configure,
354 .dev_start = eth_igb_start,
355 .dev_stop = eth_igb_stop,
356 .dev_set_link_up = eth_igb_dev_set_link_up,
357 .dev_set_link_down = eth_igb_dev_set_link_down,
358 .dev_close = eth_igb_close,
359 .dev_reset = eth_igb_reset,
360 .promiscuous_enable = eth_igb_promiscuous_enable,
361 .promiscuous_disable = eth_igb_promiscuous_disable,
362 .allmulticast_enable = eth_igb_allmulticast_enable,
363 .allmulticast_disable = eth_igb_allmulticast_disable,
364 .link_update = eth_igb_link_update,
365 .stats_get = eth_igb_stats_get,
366 .xstats_get = eth_igb_xstats_get,
367 .xstats_get_by_id = eth_igb_xstats_get_by_id,
368 .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
369 .xstats_get_names = eth_igb_xstats_get_names,
370 .stats_reset = eth_igb_stats_reset,
371 .xstats_reset = eth_igb_xstats_reset,
372 .fw_version_get = eth_igb_fw_version_get,
373 .dev_infos_get = eth_igb_infos_get,
374 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
375 .mtu_set = eth_igb_mtu_set,
376 .vlan_filter_set = eth_igb_vlan_filter_set,
377 .vlan_tpid_set = eth_igb_vlan_tpid_set,
378 .vlan_offload_set = eth_igb_vlan_offload_set,
379 .rx_queue_setup = eth_igb_rx_queue_setup,
380 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
381 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
382 .rx_queue_release = eth_igb_rx_queue_release,
383 .rx_queue_count = eth_igb_rx_queue_count,
384 .rx_descriptor_done = eth_igb_rx_descriptor_done,
385 .rx_descriptor_status = eth_igb_rx_descriptor_status,
386 .tx_descriptor_status = eth_igb_tx_descriptor_status,
387 .tx_queue_setup = eth_igb_tx_queue_setup,
388 .tx_queue_release = eth_igb_tx_queue_release,
389 .tx_done_cleanup = eth_igb_tx_done_cleanup,
390 .dev_led_on = eth_igb_led_on,
391 .dev_led_off = eth_igb_led_off,
392 .flow_ctrl_get = eth_igb_flow_ctrl_get,
393 .flow_ctrl_set = eth_igb_flow_ctrl_set,
394 .mac_addr_add = eth_igb_rar_set,
395 .mac_addr_remove = eth_igb_rar_clear,
396 .mac_addr_set = eth_igb_default_mac_addr_set,
397 .reta_update = eth_igb_rss_reta_update,
398 .reta_query = eth_igb_rss_reta_query,
399 .rss_hash_update = eth_igb_rss_hash_update,
400 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
401 .filter_ctrl = eth_igb_filter_ctrl,
402 .set_mc_addr_list = eth_igb_set_mc_addr_list,
403 .rxq_info_get = igb_rxq_info_get,
404 .txq_info_get = igb_txq_info_get,
405 .timesync_enable = igb_timesync_enable,
406 .timesync_disable = igb_timesync_disable,
407 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
408 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
409 .get_reg = eth_igb_get_regs,
410 .get_eeprom_length = eth_igb_get_eeprom_length,
411 .get_eeprom = eth_igb_get_eeprom,
412 .set_eeprom = eth_igb_set_eeprom,
413 .get_module_info = eth_igb_get_module_info,
414 .get_module_eeprom = eth_igb_get_module_eeprom,
415 .timesync_adjust_time = igb_timesync_adjust_time,
416 .timesync_read_time = igb_timesync_read_time,
417 .timesync_write_time = igb_timesync_write_time,
421 * dev_ops for virtual function, bare necessities for basic vf
422 * operation have been implemented
424 static const struct eth_dev_ops igbvf_eth_dev_ops = {
425 .dev_configure = igbvf_dev_configure,
426 .dev_start = igbvf_dev_start,
427 .dev_stop = igbvf_dev_stop,
428 .dev_close = igbvf_dev_close,
429 .promiscuous_enable = igbvf_promiscuous_enable,
430 .promiscuous_disable = igbvf_promiscuous_disable,
431 .allmulticast_enable = igbvf_allmulticast_enable,
432 .allmulticast_disable = igbvf_allmulticast_disable,
433 .link_update = eth_igb_link_update,
434 .stats_get = eth_igbvf_stats_get,
435 .xstats_get = eth_igbvf_xstats_get,
436 .xstats_get_names = eth_igbvf_xstats_get_names,
437 .stats_reset = eth_igbvf_stats_reset,
438 .xstats_reset = eth_igbvf_stats_reset,
439 .vlan_filter_set = igbvf_vlan_filter_set,
440 .dev_infos_get = eth_igbvf_infos_get,
441 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
442 .rx_queue_setup = eth_igb_rx_queue_setup,
443 .rx_queue_release = eth_igb_rx_queue_release,
444 .rx_descriptor_done = eth_igb_rx_descriptor_done,
445 .rx_descriptor_status = eth_igb_rx_descriptor_status,
446 .tx_descriptor_status = eth_igb_tx_descriptor_status,
447 .tx_queue_setup = eth_igb_tx_queue_setup,
448 .tx_queue_release = eth_igb_tx_queue_release,
449 .set_mc_addr_list = eth_igb_set_mc_addr_list,
450 .rxq_info_get = igb_rxq_info_get,
451 .txq_info_get = igb_txq_info_get,
452 .mac_addr_set = igbvf_default_mac_addr_set,
453 .get_reg = igbvf_get_regs,
456 /* store statistics names and its offset in stats structure */
457 struct rte_igb_xstats_name_off {
458 char name[RTE_ETH_XSTATS_NAME_SIZE];
462 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
463 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
464 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
465 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
466 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
467 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
468 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
469 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
471 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
472 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
473 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
474 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
475 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
476 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
477 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
478 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
479 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
480 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
481 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
483 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
484 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
485 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
486 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
487 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
489 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
491 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
492 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
493 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
494 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
495 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
496 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
497 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
498 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
499 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
500 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
501 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
502 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
503 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
504 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
505 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
506 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
507 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
508 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
510 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
512 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
513 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
514 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
515 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
516 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
517 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
518 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
520 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
523 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
524 sizeof(rte_igb_stats_strings[0]))
526 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
527 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
528 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
529 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
530 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
531 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
534 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
535 sizeof(rte_igbvf_stats_strings[0]))
539 igb_intr_enable(struct rte_eth_dev *dev)
541 struct e1000_interrupt *intr =
542 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
543 struct e1000_hw *hw =
544 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
545 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
546 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
548 if (rte_intr_allow_others(intr_handle) &&
549 dev->data->dev_conf.intr_conf.lsc != 0) {
550 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
553 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
554 E1000_WRITE_FLUSH(hw);
558 igb_intr_disable(struct rte_eth_dev *dev)
560 struct e1000_hw *hw =
561 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
562 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
563 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
565 if (rte_intr_allow_others(intr_handle) &&
566 dev->data->dev_conf.intr_conf.lsc != 0) {
567 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
570 E1000_WRITE_REG(hw, E1000_IMC, ~0);
571 E1000_WRITE_FLUSH(hw);
575 igbvf_intr_enable(struct rte_eth_dev *dev)
577 struct e1000_hw *hw =
578 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
580 /* only for mailbox */
581 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
582 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
583 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
584 E1000_WRITE_FLUSH(hw);
587 /* only for mailbox now. If RX/TX needed, should extend this function. */
589 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
594 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
595 tmp |= E1000_VTIVAR_VALID;
596 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
600 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
602 struct e1000_hw *hw =
603 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
605 /* Configure VF other cause ivar */
606 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
609 static inline int32_t
610 igb_pf_reset_hw(struct e1000_hw *hw)
615 status = e1000_reset_hw(hw);
617 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
618 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
619 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
620 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
621 E1000_WRITE_FLUSH(hw);
627 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
629 struct e1000_hw *hw =
630 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
633 hw->vendor_id = pci_dev->id.vendor_id;
634 hw->device_id = pci_dev->id.device_id;
635 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
636 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
638 e1000_set_mac_type(hw);
640 /* need to check if it is a vf device below */
644 igb_reset_swfw_lock(struct e1000_hw *hw)
649 * Do mac ops initialization manually here, since we will need
650 * some function pointers set by this call.
652 ret_val = e1000_init_mac_params(hw);
657 * SMBI lock should not fail in this early stage. If this is the case,
658 * it is due to an improper exit of the application.
659 * So force the release of the faulty lock.
661 if (e1000_get_hw_semaphore_generic(hw) < 0) {
662 PMD_DRV_LOG(DEBUG, "SMBI lock released");
664 e1000_put_hw_semaphore_generic(hw);
666 if (hw->mac.ops.acquire_swfw_sync != NULL) {
670 * Phy lock should not fail in this early stage. If this is the case,
671 * it is due to an improper exit of the application.
672 * So force the release of the faulty lock.
674 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
675 if (hw->bus.func > E1000_FUNC_1)
677 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
678 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
681 hw->mac.ops.release_swfw_sync(hw, mask);
684 * This one is more tricky since it is common to all ports; but
685 * swfw_sync retries last long enough (1s) to be almost sure that if
686 * lock can not be taken it is due to an improper lock of the
689 mask = E1000_SWFW_EEP_SM;
690 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
691 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
693 hw->mac.ops.release_swfw_sync(hw, mask);
696 return E1000_SUCCESS;
699 /* Remove all ntuple filters of the device */
700 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
702 struct e1000_filter_info *filter_info =
703 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
704 struct e1000_5tuple_filter *p_5tuple;
705 struct e1000_2tuple_filter *p_2tuple;
707 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
708 TAILQ_REMOVE(&filter_info->fivetuple_list,
712 filter_info->fivetuple_mask = 0;
713 while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
714 TAILQ_REMOVE(&filter_info->twotuple_list,
718 filter_info->twotuple_mask = 0;
723 /* Remove all flex filters of the device */
724 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
726 struct e1000_filter_info *filter_info =
727 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
728 struct e1000_flex_filter *p_flex;
730 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
731 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
734 filter_info->flex_mask = 0;
740 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
743 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
744 struct e1000_hw *hw =
745 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
746 struct e1000_vfta * shadow_vfta =
747 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
748 struct e1000_filter_info *filter_info =
749 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
750 struct e1000_adapter *adapter =
751 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
755 eth_dev->dev_ops = ð_igb_ops;
756 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
757 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
758 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
760 /* for secondary processes, we don't initialise any further as primary
761 * has already done this work. Only check we don't need a different
763 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
764 if (eth_dev->data->scattered_rx)
765 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
769 rte_eth_copy_pci_info(eth_dev, pci_dev);
771 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
773 igb_identify_hardware(eth_dev, pci_dev);
774 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
779 e1000_get_bus_info(hw);
781 /* Reset any pending lock */
782 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
787 /* Finish initialization */
788 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
794 hw->phy.autoneg_wait_to_complete = 0;
795 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
798 if (hw->phy.media_type == e1000_media_type_copper) {
799 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
800 hw->phy.disable_polarity_correction = 0;
801 hw->phy.ms_type = e1000_ms_hw_default;
805 * Start from a known state, this is important in reading the nvm
810 /* Make sure we have a good EEPROM before we read from it */
811 if (e1000_validate_nvm_checksum(hw) < 0) {
813 * Some PCI-E parts fail the first check due to
814 * the link being in sleep state, call it again,
815 * if it fails a second time its a real issue.
817 if (e1000_validate_nvm_checksum(hw) < 0) {
818 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
824 /* Read the permanent MAC address out of the EEPROM */
825 if (e1000_read_mac_addr(hw) != 0) {
826 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
831 /* Allocate memory for storing MAC addresses */
832 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
833 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
834 if (eth_dev->data->mac_addrs == NULL) {
835 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
836 "store MAC addresses",
837 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
842 /* Copy the permanent MAC address */
843 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
844 ð_dev->data->mac_addrs[0]);
846 /* Pass the information to the rte_eth_dev_close() that it should also
847 * release the private port resources.
849 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
851 /* initialize the vfta */
852 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
854 /* Now initialize the hardware */
855 if (igb_hardware_init(hw) != 0) {
856 PMD_INIT_LOG(ERR, "Hardware initialization failed");
857 rte_free(eth_dev->data->mac_addrs);
858 eth_dev->data->mac_addrs = NULL;
862 hw->mac.get_link_status = 1;
863 adapter->stopped = 0;
865 /* Indicate SOL/IDER usage */
866 if (e1000_check_reset_block(hw) < 0) {
867 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
871 /* initialize PF if max_vfs not zero */
872 igb_pf_host_init(eth_dev);
874 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
875 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
876 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
877 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
878 E1000_WRITE_FLUSH(hw);
880 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
881 eth_dev->data->port_id, pci_dev->id.vendor_id,
882 pci_dev->id.device_id);
884 rte_intr_callback_register(&pci_dev->intr_handle,
885 eth_igb_interrupt_handler,
888 /* enable uio/vfio intr/eventfd mapping */
889 rte_intr_enable(&pci_dev->intr_handle);
891 /* enable support intr */
892 igb_intr_enable(eth_dev);
894 /* initialize filter info */
895 memset(filter_info, 0,
896 sizeof(struct e1000_filter_info));
898 TAILQ_INIT(&filter_info->flex_list);
899 TAILQ_INIT(&filter_info->twotuple_list);
900 TAILQ_INIT(&filter_info->fivetuple_list);
902 TAILQ_INIT(&igb_filter_ntuple_list);
903 TAILQ_INIT(&igb_filter_ethertype_list);
904 TAILQ_INIT(&igb_filter_syn_list);
905 TAILQ_INIT(&igb_filter_flex_list);
906 TAILQ_INIT(&igb_filter_rss_list);
907 TAILQ_INIT(&igb_flow_list);
912 igb_hw_control_release(hw);
918 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
920 PMD_INIT_FUNC_TRACE();
922 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
925 eth_igb_close(eth_dev);
931 * Virtual Function device init
934 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
936 struct rte_pci_device *pci_dev;
937 struct rte_intr_handle *intr_handle;
938 struct e1000_adapter *adapter =
939 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
940 struct e1000_hw *hw =
941 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
943 struct rte_ether_addr *perm_addr =
944 (struct rte_ether_addr *)hw->mac.perm_addr;
946 PMD_INIT_FUNC_TRACE();
948 eth_dev->dev_ops = &igbvf_eth_dev_ops;
949 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
950 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
951 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
953 /* for secondary processes, we don't initialise any further as primary
954 * has already done this work. Only check we don't need a different
956 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
957 if (eth_dev->data->scattered_rx)
958 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
962 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
963 rte_eth_copy_pci_info(eth_dev, pci_dev);
965 hw->device_id = pci_dev->id.device_id;
966 hw->vendor_id = pci_dev->id.vendor_id;
967 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
968 adapter->stopped = 0;
970 /* Initialize the shared code (base driver) */
971 diag = e1000_setup_init_funcs(hw, TRUE);
973 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
978 /* init_mailbox_params */
979 hw->mbx.ops.init_params(hw);
981 /* Disable the interrupts for VF */
982 igbvf_intr_disable(hw);
984 diag = hw->mac.ops.reset_hw(hw);
986 /* Allocate memory for storing MAC addresses */
987 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
988 hw->mac.rar_entry_count, 0);
989 if (eth_dev->data->mac_addrs == NULL) {
991 "Failed to allocate %d bytes needed to store MAC "
993 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
997 /* Pass the information to the rte_eth_dev_close() that it should also
998 * release the private port resources.
1000 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1002 /* Generate a random MAC address, if none was assigned by PF. */
1003 if (rte_is_zero_ether_addr(perm_addr)) {
1004 rte_eth_random_addr(perm_addr->addr_bytes);
1005 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1006 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1007 "%02x:%02x:%02x:%02x:%02x:%02x",
1008 perm_addr->addr_bytes[0],
1009 perm_addr->addr_bytes[1],
1010 perm_addr->addr_bytes[2],
1011 perm_addr->addr_bytes[3],
1012 perm_addr->addr_bytes[4],
1013 perm_addr->addr_bytes[5]);
1016 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1018 rte_free(eth_dev->data->mac_addrs);
1019 eth_dev->data->mac_addrs = NULL;
1022 /* Copy the permanent MAC address */
1023 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1024 ð_dev->data->mac_addrs[0]);
1026 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1028 eth_dev->data->port_id, pci_dev->id.vendor_id,
1029 pci_dev->id.device_id, "igb_mac_82576_vf");
1031 intr_handle = &pci_dev->intr_handle;
1032 rte_intr_callback_register(intr_handle,
1033 eth_igbvf_interrupt_handler, eth_dev);
1039 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1041 PMD_INIT_FUNC_TRACE();
1043 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1046 igbvf_dev_close(eth_dev);
1051 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1052 struct rte_pci_device *pci_dev)
1054 return rte_eth_dev_pci_generic_probe(pci_dev,
1055 sizeof(struct e1000_adapter), eth_igb_dev_init);
1058 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1060 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1063 static struct rte_pci_driver rte_igb_pmd = {
1064 .id_table = pci_id_igb_map,
1065 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1066 .probe = eth_igb_pci_probe,
1067 .remove = eth_igb_pci_remove,
1071 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1072 struct rte_pci_device *pci_dev)
1074 return rte_eth_dev_pci_generic_probe(pci_dev,
1075 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1078 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1080 return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1084 * virtual function driver struct
1086 static struct rte_pci_driver rte_igbvf_pmd = {
1087 .id_table = pci_id_igbvf_map,
1088 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1089 .probe = eth_igbvf_pci_probe,
1090 .remove = eth_igbvf_pci_remove,
1094 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1096 struct e1000_hw *hw =
1097 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1098 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1099 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1100 rctl |= E1000_RCTL_VFE;
1101 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1105 igb_check_mq_mode(struct rte_eth_dev *dev)
1107 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1108 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1109 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1110 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1112 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1113 tx_mq_mode == ETH_MQ_TX_DCB ||
1114 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1115 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1118 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1119 /* Check multi-queue mode.
1120 * To no break software we accept ETH_MQ_RX_NONE as this might
1121 * be used to turn off VLAN filter.
1124 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1125 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1126 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1127 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1129 /* Only support one queue on VFs.
1130 * RSS together with SRIOV is not supported.
1132 PMD_INIT_LOG(ERR, "SRIOV is active,"
1133 " wrong mq_mode rx %d.",
1137 /* TX mode is not used here, so mode might be ignored.*/
1138 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1139 /* SRIOV only works in VMDq enable mode */
1140 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1141 " TX mode %d is not supported. "
1142 " Driver will behave as %d mode.",
1143 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1146 /* check valid queue number */
1147 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1148 PMD_INIT_LOG(ERR, "SRIOV is active,"
1149 " only support one queue on VFs.");
1153 /* To no break software that set invalid mode, only display
1154 * warning if invalid mode is used.
1156 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1157 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1158 rx_mq_mode != ETH_MQ_RX_RSS) {
1159 /* RSS together with VMDq not supported*/
1160 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1165 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1166 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1167 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1168 " Due to txmode is meaningless in this"
1169 " driver, just ignore.",
1177 eth_igb_configure(struct rte_eth_dev *dev)
1179 struct e1000_interrupt *intr =
1180 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1183 PMD_INIT_FUNC_TRACE();
1185 /* multipe queue mode checking */
1186 ret = igb_check_mq_mode(dev);
1188 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1193 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1194 PMD_INIT_FUNC_TRACE();
1200 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1203 struct e1000_hw *hw =
1204 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205 uint32_t tctl, rctl;
1207 tctl = E1000_READ_REG(hw, E1000_TCTL);
1208 rctl = E1000_READ_REG(hw, E1000_RCTL);
1212 tctl |= E1000_TCTL_EN;
1213 rctl |= E1000_RCTL_EN;
1216 tctl &= ~E1000_TCTL_EN;
1217 rctl &= ~E1000_RCTL_EN;
1219 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1220 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1221 E1000_WRITE_FLUSH(hw);
1225 eth_igb_start(struct rte_eth_dev *dev)
1227 struct e1000_hw *hw =
1228 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1229 struct e1000_adapter *adapter =
1230 E1000_DEV_PRIVATE(dev->data->dev_private);
1231 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1232 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1234 uint32_t intr_vector = 0;
1240 PMD_INIT_FUNC_TRACE();
1242 /* disable uio/vfio intr/eventfd mapping */
1243 rte_intr_disable(intr_handle);
1245 /* Power up the phy. Needed to make the link go Up */
1246 eth_igb_dev_set_link_up(dev);
1249 * Packet Buffer Allocation (PBA)
1250 * Writing PBA sets the receive portion of the buffer
1251 * the remainder is used for the transmit buffer.
1253 if (hw->mac.type == e1000_82575) {
1256 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1257 E1000_WRITE_REG(hw, E1000_PBA, pba);
1260 /* Put the address into the Receive Address Array */
1261 e1000_rar_set(hw, hw->mac.addr, 0);
1263 /* Initialize the hardware */
1264 if (igb_hardware_init(hw)) {
1265 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1268 adapter->stopped = 0;
1270 E1000_WRITE_REG(hw, E1000_VET,
1271 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1273 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1274 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1275 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1276 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1277 E1000_WRITE_FLUSH(hw);
1279 /* configure PF module if SRIOV enabled */
1280 igb_pf_host_configure(dev);
1282 /* check and configure queue intr-vector mapping */
1283 if ((rte_intr_cap_multiple(intr_handle) ||
1284 !RTE_ETH_DEV_SRIOV(dev).active) &&
1285 dev->data->dev_conf.intr_conf.rxq != 0) {
1286 intr_vector = dev->data->nb_rx_queues;
1287 if (rte_intr_efd_enable(intr_handle, intr_vector))
1291 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1292 intr_handle->intr_vec =
1293 rte_zmalloc("intr_vec",
1294 dev->data->nb_rx_queues * sizeof(int), 0);
1295 if (intr_handle->intr_vec == NULL) {
1296 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1297 " intr_vec", dev->data->nb_rx_queues);
1302 /* confiugre msix for rx interrupt */
1303 eth_igb_configure_msix_intr(dev);
1305 /* Configure for OS presence */
1306 igb_init_manageability(hw);
1308 eth_igb_tx_init(dev);
1310 /* This can fail when allocating mbufs for descriptor rings */
1311 ret = eth_igb_rx_init(dev);
1313 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1314 igb_dev_clear_queues(dev);
1318 e1000_clear_hw_cntrs_base_generic(hw);
1321 * VLAN Offload Settings
1323 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1324 ETH_VLAN_EXTEND_MASK;
1325 ret = eth_igb_vlan_offload_set(dev, mask);
1327 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1328 igb_dev_clear_queues(dev);
1332 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1333 /* Enable VLAN filter since VMDq always use VLAN filter */
1334 igb_vmdq_vlan_hw_filter_enable(dev);
1337 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1338 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1339 (hw->mac.type == e1000_i211)) {
1340 /* Configure EITR with the maximum possible value (0xFFFF) */
1341 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1344 /* Setup link speed and duplex */
1345 speeds = &dev->data->dev_conf.link_speeds;
1346 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1347 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1348 hw->mac.autoneg = 1;
1351 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1354 hw->phy.autoneg_advertised = 0;
1356 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1357 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1358 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1360 goto error_invalid_config;
1362 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1363 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1366 if (*speeds & ETH_LINK_SPEED_10M) {
1367 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1370 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1371 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1374 if (*speeds & ETH_LINK_SPEED_100M) {
1375 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1378 if (*speeds & ETH_LINK_SPEED_1G) {
1379 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1382 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1383 goto error_invalid_config;
1385 /* Set/reset the mac.autoneg based on the link speed,
1389 hw->mac.autoneg = 0;
1390 hw->mac.forced_speed_duplex =
1391 hw->phy.autoneg_advertised;
1393 hw->mac.autoneg = 1;
1397 e1000_setup_link(hw);
1399 if (rte_intr_allow_others(intr_handle)) {
1400 /* check if lsc interrupt is enabled */
1401 if (dev->data->dev_conf.intr_conf.lsc != 0)
1402 eth_igb_lsc_interrupt_setup(dev, TRUE);
1404 eth_igb_lsc_interrupt_setup(dev, FALSE);
1406 rte_intr_callback_unregister(intr_handle,
1407 eth_igb_interrupt_handler,
1409 if (dev->data->dev_conf.intr_conf.lsc != 0)
1410 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1411 " no intr multiplex");
1414 /* check if rxq interrupt is enabled */
1415 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1416 rte_intr_dp_is_en(intr_handle))
1417 eth_igb_rxq_interrupt_setup(dev);
1419 /* enable uio/vfio intr/eventfd mapping */
1420 rte_intr_enable(intr_handle);
1422 /* resume enabled intr since hw reset */
1423 igb_intr_enable(dev);
1425 /* restore all types filter */
1426 igb_filter_restore(dev);
1428 eth_igb_rxtx_control(dev, true);
1429 eth_igb_link_update(dev, 0);
1431 PMD_INIT_LOG(DEBUG, "<<");
1435 error_invalid_config:
1436 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1437 dev->data->dev_conf.link_speeds, dev->data->port_id);
1438 igb_dev_clear_queues(dev);
1442 /*********************************************************************
1444 * This routine disables all traffic on the adapter by issuing a
1445 * global reset on the MAC.
1447 **********************************************************************/
1449 eth_igb_stop(struct rte_eth_dev *dev)
1451 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1452 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1453 struct rte_eth_link link;
1454 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1455 struct e1000_adapter *adapter =
1456 E1000_DEV_PRIVATE(dev->data->dev_private);
1458 if (adapter->stopped)
1461 eth_igb_rxtx_control(dev, false);
1463 igb_intr_disable(dev);
1465 /* disable intr eventfd mapping */
1466 rte_intr_disable(intr_handle);
1468 igb_pf_reset_hw(hw);
1469 E1000_WRITE_REG(hw, E1000_WUC, 0);
1471 /* Set bit for Go Link disconnect if PHY reset is not blocked */
1472 if (hw->mac.type >= e1000_82580 &&
1473 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1476 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1477 phpm_reg |= E1000_82580_PM_GO_LINKD;
1478 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1481 /* Power down the phy. Needed to make the link go Down */
1482 eth_igb_dev_set_link_down(dev);
1484 igb_dev_clear_queues(dev);
1486 /* clear the recorded link status */
1487 memset(&link, 0, sizeof(link));
1488 rte_eth_linkstatus_set(dev, &link);
1490 if (!rte_intr_allow_others(intr_handle))
1491 /* resume to the default handler */
1492 rte_intr_callback_register(intr_handle,
1493 eth_igb_interrupt_handler,
1496 /* Clean datapath event and queue/vec mapping */
1497 rte_intr_efd_disable(intr_handle);
1498 if (intr_handle->intr_vec != NULL) {
1499 rte_free(intr_handle->intr_vec);
1500 intr_handle->intr_vec = NULL;
1503 adapter->stopped = true;
1507 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1509 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1511 if (hw->phy.media_type == e1000_media_type_copper)
1512 e1000_power_up_phy(hw);
1514 e1000_power_up_fiber_serdes_link(hw);
1520 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1522 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524 if (hw->phy.media_type == e1000_media_type_copper)
1525 e1000_power_down_phy(hw);
1527 e1000_shutdown_fiber_serdes_link(hw);
1533 eth_igb_close(struct rte_eth_dev *dev)
1535 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1536 struct rte_eth_link link;
1537 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1538 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1539 struct e1000_filter_info *filter_info =
1540 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1544 e1000_phy_hw_reset(hw);
1545 igb_release_manageability(hw);
1546 igb_hw_control_release(hw);
1548 /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1549 if (hw->mac.type >= e1000_82580 &&
1550 (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1553 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1554 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1555 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1558 igb_dev_free_queues(dev);
1560 if (intr_handle->intr_vec) {
1561 rte_free(intr_handle->intr_vec);
1562 intr_handle->intr_vec = NULL;
1565 memset(&link, 0, sizeof(link));
1566 rte_eth_linkstatus_set(dev, &link);
1568 dev->dev_ops = NULL;
1569 dev->rx_pkt_burst = NULL;
1570 dev->tx_pkt_burst = NULL;
1572 /* Reset any pending lock */
1573 igb_reset_swfw_lock(hw);
1575 /* uninitialize PF if max_vfs not zero */
1576 igb_pf_host_uninit(dev);
1578 rte_intr_callback_unregister(intr_handle,
1579 eth_igb_interrupt_handler, dev);
1581 /* clear the SYN filter info */
1582 filter_info->syn_info = 0;
1584 /* clear the ethertype filters info */
1585 filter_info->ethertype_mask = 0;
1586 memset(filter_info->ethertype_filters, 0,
1587 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1589 /* clear the rss filter info */
1590 memset(&filter_info->rss_info, 0,
1591 sizeof(struct igb_rte_flow_rss_conf));
1593 /* remove all ntuple filters of the device */
1594 igb_ntuple_filter_uninit(dev);
1596 /* remove all flex filters of the device */
1597 igb_flex_filter_uninit(dev);
1599 /* clear all the filters list */
1600 igb_filterlist_flush(dev);
1607 eth_igb_reset(struct rte_eth_dev *dev)
1611 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1612 * its VF to make them align with it. The detailed notification
1613 * mechanism is PMD specific and is currently not implemented.
1614 * To avoid unexpected behavior in VF, currently reset of PF with
1615 * SR-IOV activation is not supported. It might be supported later.
1617 if (dev->data->sriov.active)
1620 ret = eth_igb_dev_uninit(dev);
1624 ret = eth_igb_dev_init(dev);
1631 igb_get_rx_buffer_size(struct e1000_hw *hw)
1633 uint32_t rx_buf_size;
1634 if (hw->mac.type == e1000_82576) {
1635 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1636 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1637 /* PBS needs to be translated according to a lookup table */
1638 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1639 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1640 rx_buf_size = (rx_buf_size << 10);
1641 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1642 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1644 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1650 /*********************************************************************
1652 * Initialize the hardware
1654 **********************************************************************/
1656 igb_hardware_init(struct e1000_hw *hw)
1658 uint32_t rx_buf_size;
1661 /* Let the firmware know the OS is in control */
1662 igb_hw_control_acquire(hw);
1665 * These parameters control the automatic generation (Tx) and
1666 * response (Rx) to Ethernet PAUSE frames.
1667 * - High water mark should allow for at least two standard size (1518)
1668 * frames to be received after sending an XOFF.
1669 * - Low water mark works best when it is very near the high water mark.
1670 * This allows the receiver to restart by sending XON when it has
1671 * drained a bit. Here we use an arbitrary value of 1500 which will
1672 * restart after one full frame is pulled from the buffer. There
1673 * could be several smaller frames in the buffer and if so they will
1674 * not trigger the XON until their total number reduces the buffer
1676 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1678 rx_buf_size = igb_get_rx_buffer_size(hw);
1680 hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1681 hw->fc.low_water = hw->fc.high_water - 1500;
1682 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1683 hw->fc.send_xon = 1;
1685 /* Set Flow control, use the tunable location if sane */
1686 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1687 hw->fc.requested_mode = igb_fc_setting;
1689 hw->fc.requested_mode = e1000_fc_none;
1691 /* Issue a global reset */
1692 igb_pf_reset_hw(hw);
1693 E1000_WRITE_REG(hw, E1000_WUC, 0);
1695 diag = e1000_init_hw(hw);
1699 E1000_WRITE_REG(hw, E1000_VET,
1700 RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1701 e1000_get_phy_info(hw);
1702 e1000_check_for_link(hw);
1707 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1709 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1713 uint64_t old_gprc = stats->gprc;
1714 uint64_t old_gptc = stats->gptc;
1715 uint64_t old_tpr = stats->tpr;
1716 uint64_t old_tpt = stats->tpt;
1717 uint64_t old_rpthc = stats->rpthc;
1718 uint64_t old_hgptc = stats->hgptc;
1720 if(hw->phy.media_type == e1000_media_type_copper ||
1721 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1723 E1000_READ_REG(hw,E1000_SYMERRS);
1724 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1727 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1728 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1729 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1730 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1732 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1733 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1734 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1735 stats->dc += E1000_READ_REG(hw, E1000_DC);
1736 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1737 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1738 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1740 ** For watchdog management we need to know if we have been
1741 ** paused during the last interval, so capture that here.
1743 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1744 stats->xoffrxc += pause_frames;
1745 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1746 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1747 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1748 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1749 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1750 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1751 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1752 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1753 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1754 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1755 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1756 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1758 /* For the 64-bit byte counters the low dword must be read first. */
1759 /* Both registers clear on the read of the high dword */
1761 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1762 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1763 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1764 stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1765 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1766 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1767 stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1769 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1770 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1771 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1772 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1773 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1775 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1776 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1778 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1779 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1780 stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1781 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1782 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1783 stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1785 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1786 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1787 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1788 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1789 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1790 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1791 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1792 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1794 /* Interrupt Counts */
1796 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1797 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1798 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1799 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1800 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1801 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1802 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1803 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1804 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1806 /* Host to Card Statistics */
1808 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1809 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1810 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1811 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1812 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1813 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1814 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1815 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1816 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1817 stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1818 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1819 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1820 stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1821 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1822 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1823 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1825 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1826 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1827 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1828 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1829 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1830 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1834 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1836 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837 struct e1000_hw_stats *stats =
1838 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1840 igb_read_stats_registers(hw, stats);
1842 if (rte_stats == NULL)
1846 rte_stats->imissed = stats->mpc;
1847 rte_stats->ierrors = stats->crcerrs +
1848 stats->rlec + stats->ruc + stats->roc +
1849 stats->rxerrc + stats->algnerrc + stats->cexterr;
1852 rte_stats->oerrors = stats->ecol + stats->latecol;
1854 rte_stats->ipackets = stats->gprc;
1855 rte_stats->opackets = stats->gptc;
1856 rte_stats->ibytes = stats->gorc;
1857 rte_stats->obytes = stats->gotc;
1862 eth_igb_stats_reset(struct rte_eth_dev *dev)
1864 struct e1000_hw_stats *hw_stats =
1865 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1867 /* HW registers are cleared on read */
1868 eth_igb_stats_get(dev, NULL);
1870 /* Reset software totals */
1871 memset(hw_stats, 0, sizeof(*hw_stats));
1877 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1879 struct e1000_hw_stats *stats =
1880 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1882 /* HW registers are cleared on read */
1883 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1885 /* Reset software totals */
1886 memset(stats, 0, sizeof(*stats));
1891 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1892 struct rte_eth_xstat_name *xstats_names,
1893 __rte_unused unsigned int size)
1897 if (xstats_names == NULL)
1898 return IGB_NB_XSTATS;
1900 /* Note: limit checked in rte_eth_xstats_names() */
1902 for (i = 0; i < IGB_NB_XSTATS; i++) {
1903 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1904 sizeof(xstats_names[i].name));
1907 return IGB_NB_XSTATS;
1910 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1911 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1917 if (xstats_names == NULL)
1918 return IGB_NB_XSTATS;
1920 for (i = 0; i < IGB_NB_XSTATS; i++)
1921 strlcpy(xstats_names[i].name,
1922 rte_igb_stats_strings[i].name,
1923 sizeof(xstats_names[i].name));
1925 return IGB_NB_XSTATS;
1928 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1930 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1933 for (i = 0; i < limit; i++) {
1934 if (ids[i] >= IGB_NB_XSTATS) {
1935 PMD_INIT_LOG(ERR, "id value isn't valid");
1938 strcpy(xstats_names[i].name,
1939 xstats_names_copy[ids[i]].name);
1946 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1949 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1950 struct e1000_hw_stats *hw_stats =
1951 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1954 if (n < IGB_NB_XSTATS)
1955 return IGB_NB_XSTATS;
1957 igb_read_stats_registers(hw, hw_stats);
1959 /* If this is a reset xstats is NULL, and we have cleared the
1960 * registers by reading them.
1965 /* Extended stats */
1966 for (i = 0; i < IGB_NB_XSTATS; i++) {
1968 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1969 rte_igb_stats_strings[i].offset);
1972 return IGB_NB_XSTATS;
1976 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1977 uint64_t *values, unsigned int n)
1982 struct e1000_hw *hw =
1983 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1984 struct e1000_hw_stats *hw_stats =
1985 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1987 if (n < IGB_NB_XSTATS)
1988 return IGB_NB_XSTATS;
1990 igb_read_stats_registers(hw, hw_stats);
1992 /* If this is a reset xstats is NULL, and we have cleared the
1993 * registers by reading them.
1998 /* Extended stats */
1999 for (i = 0; i < IGB_NB_XSTATS; i++)
2000 values[i] = *(uint64_t *)(((char *)hw_stats) +
2001 rte_igb_stats_strings[i].offset);
2003 return IGB_NB_XSTATS;
2006 uint64_t values_copy[IGB_NB_XSTATS];
2008 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2011 for (i = 0; i < n; i++) {
2012 if (ids[i] >= IGB_NB_XSTATS) {
2013 PMD_INIT_LOG(ERR, "id value isn't valid");
2016 values[i] = values_copy[ids[i]];
2023 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2025 /* Good Rx packets, include VF loopback */
2026 UPDATE_VF_STAT(E1000_VFGPRC,
2027 hw_stats->last_gprc, hw_stats->gprc);
2029 /* Good Rx octets, include VF loopback */
2030 UPDATE_VF_STAT(E1000_VFGORC,
2031 hw_stats->last_gorc, hw_stats->gorc);
2033 /* Good Tx packets, include VF loopback */
2034 UPDATE_VF_STAT(E1000_VFGPTC,
2035 hw_stats->last_gptc, hw_stats->gptc);
2037 /* Good Tx octets, include VF loopback */
2038 UPDATE_VF_STAT(E1000_VFGOTC,
2039 hw_stats->last_gotc, hw_stats->gotc);
2041 /* Rx Multicst packets */
2042 UPDATE_VF_STAT(E1000_VFMPRC,
2043 hw_stats->last_mprc, hw_stats->mprc);
2045 /* Good Rx loopback packets */
2046 UPDATE_VF_STAT(E1000_VFGPRLBC,
2047 hw_stats->last_gprlbc, hw_stats->gprlbc);
2049 /* Good Rx loopback octets */
2050 UPDATE_VF_STAT(E1000_VFGORLBC,
2051 hw_stats->last_gorlbc, hw_stats->gorlbc);
2053 /* Good Tx loopback packets */
2054 UPDATE_VF_STAT(E1000_VFGPTLBC,
2055 hw_stats->last_gptlbc, hw_stats->gptlbc);
2057 /* Good Tx loopback octets */
2058 UPDATE_VF_STAT(E1000_VFGOTLBC,
2059 hw_stats->last_gotlbc, hw_stats->gotlbc);
2062 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2063 struct rte_eth_xstat_name *xstats_names,
2064 __rte_unused unsigned limit)
2068 if (xstats_names != NULL)
2069 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2070 strlcpy(xstats_names[i].name,
2071 rte_igbvf_stats_strings[i].name,
2072 sizeof(xstats_names[i].name));
2074 return IGBVF_NB_XSTATS;
2078 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2081 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2083 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2086 if (n < IGBVF_NB_XSTATS)
2087 return IGBVF_NB_XSTATS;
2089 igbvf_read_stats_registers(hw, hw_stats);
2094 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2096 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2097 rte_igbvf_stats_strings[i].offset);
2100 return IGBVF_NB_XSTATS;
2104 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2106 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2108 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2110 igbvf_read_stats_registers(hw, hw_stats);
2112 if (rte_stats == NULL)
2115 rte_stats->ipackets = hw_stats->gprc;
2116 rte_stats->ibytes = hw_stats->gorc;
2117 rte_stats->opackets = hw_stats->gptc;
2118 rte_stats->obytes = hw_stats->gotc;
2123 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2125 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2126 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2128 /* Sync HW register to the last stats */
2129 eth_igbvf_stats_get(dev, NULL);
2131 /* reset HW current stats*/
2132 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2133 offsetof(struct e1000_vf_stats, gprc));
2139 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2142 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2143 struct e1000_fw_version fw;
2146 e1000_get_fw_version(hw, &fw);
2148 switch (hw->mac.type) {
2151 if (!(e1000_get_flash_presence_i210(hw))) {
2152 ret = snprintf(fw_version, fw_size,
2154 fw.invm_major, fw.invm_minor,
2160 /* if option rom is valid, display its version too */
2162 ret = snprintf(fw_version, fw_size,
2163 "%d.%d, 0x%08x, %d.%d.%d",
2164 fw.eep_major, fw.eep_minor, fw.etrack_id,
2165 fw.or_major, fw.or_build, fw.or_patch);
2168 if (fw.etrack_id != 0X0000) {
2169 ret = snprintf(fw_version, fw_size,
2171 fw.eep_major, fw.eep_minor,
2174 ret = snprintf(fw_version, fw_size,
2176 fw.eep_major, fw.eep_minor,
2183 ret += 1; /* add the size of '\0' */
2184 if (fw_size < (u32)ret)
2191 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2193 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2196 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2197 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2198 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2199 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2200 dev_info->rx_queue_offload_capa;
2201 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2202 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2203 dev_info->tx_queue_offload_capa;
2205 switch (hw->mac.type) {
2207 dev_info->max_rx_queues = 4;
2208 dev_info->max_tx_queues = 4;
2209 dev_info->max_vmdq_pools = 0;
2213 dev_info->max_rx_queues = 16;
2214 dev_info->max_tx_queues = 16;
2215 dev_info->max_vmdq_pools = ETH_8_POOLS;
2216 dev_info->vmdq_queue_num = 16;
2220 dev_info->max_rx_queues = 8;
2221 dev_info->max_tx_queues = 8;
2222 dev_info->max_vmdq_pools = ETH_8_POOLS;
2223 dev_info->vmdq_queue_num = 8;
2227 dev_info->max_rx_queues = 8;
2228 dev_info->max_tx_queues = 8;
2229 dev_info->max_vmdq_pools = ETH_8_POOLS;
2230 dev_info->vmdq_queue_num = 8;
2234 dev_info->max_rx_queues = 8;
2235 dev_info->max_tx_queues = 8;
2239 dev_info->max_rx_queues = 4;
2240 dev_info->max_tx_queues = 4;
2241 dev_info->max_vmdq_pools = 0;
2245 dev_info->max_rx_queues = 2;
2246 dev_info->max_tx_queues = 2;
2247 dev_info->max_vmdq_pools = 0;
2251 /* Should not happen */
2254 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2255 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2256 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2258 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2260 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2261 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2262 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2264 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2269 dev_info->default_txconf = (struct rte_eth_txconf) {
2271 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2272 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2273 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2278 dev_info->rx_desc_lim = rx_desc_lim;
2279 dev_info->tx_desc_lim = tx_desc_lim;
2281 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2282 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2285 dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2286 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2291 static const uint32_t *
2292 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2294 static const uint32_t ptypes[] = {
2295 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2298 RTE_PTYPE_L3_IPV4_EXT,
2300 RTE_PTYPE_L3_IPV6_EXT,
2304 RTE_PTYPE_TUNNEL_IP,
2305 RTE_PTYPE_INNER_L3_IPV6,
2306 RTE_PTYPE_INNER_L3_IPV6_EXT,
2307 RTE_PTYPE_INNER_L4_TCP,
2308 RTE_PTYPE_INNER_L4_UDP,
2312 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2313 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2319 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2321 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2323 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2324 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2325 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2326 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2327 DEV_TX_OFFLOAD_IPV4_CKSUM |
2328 DEV_TX_OFFLOAD_UDP_CKSUM |
2329 DEV_TX_OFFLOAD_TCP_CKSUM |
2330 DEV_TX_OFFLOAD_SCTP_CKSUM |
2331 DEV_TX_OFFLOAD_TCP_TSO;
2332 switch (hw->mac.type) {
2334 dev_info->max_rx_queues = 2;
2335 dev_info->max_tx_queues = 2;
2337 case e1000_vfadapt_i350:
2338 dev_info->max_rx_queues = 1;
2339 dev_info->max_tx_queues = 1;
2342 /* Should not happen */
2346 dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2347 dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2348 dev_info->rx_queue_offload_capa;
2349 dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2350 dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2351 dev_info->tx_queue_offload_capa;
2353 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2355 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2356 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2357 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2359 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2364 dev_info->default_txconf = (struct rte_eth_txconf) {
2366 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2367 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2368 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2373 dev_info->rx_desc_lim = rx_desc_lim;
2374 dev_info->tx_desc_lim = tx_desc_lim;
2379 /* return 0 means link status changed, -1 means not changed */
2381 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2383 struct e1000_hw *hw =
2384 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2385 struct rte_eth_link link;
2386 int link_check, count;
2389 hw->mac.get_link_status = 1;
2391 /* possible wait-to-complete in up to 9 seconds */
2392 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2393 /* Read the real link status */
2394 switch (hw->phy.media_type) {
2395 case e1000_media_type_copper:
2396 /* Do the work to read phy */
2397 e1000_check_for_link(hw);
2398 link_check = !hw->mac.get_link_status;
2401 case e1000_media_type_fiber:
2402 e1000_check_for_link(hw);
2403 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2407 case e1000_media_type_internal_serdes:
2408 e1000_check_for_link(hw);
2409 link_check = hw->mac.serdes_has_link;
2412 /* VF device is type_unknown */
2413 case e1000_media_type_unknown:
2414 eth_igbvf_link_update(hw);
2415 link_check = !hw->mac.get_link_status;
2421 if (link_check || wait_to_complete == 0)
2423 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2425 memset(&link, 0, sizeof(link));
2427 /* Now we check if a transition has happened */
2429 uint16_t duplex, speed;
2430 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2431 link.link_duplex = (duplex == FULL_DUPLEX) ?
2432 ETH_LINK_FULL_DUPLEX :
2433 ETH_LINK_HALF_DUPLEX;
2434 link.link_speed = speed;
2435 link.link_status = ETH_LINK_UP;
2436 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2437 ETH_LINK_SPEED_FIXED);
2438 } else if (!link_check) {
2439 link.link_speed = 0;
2440 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2441 link.link_status = ETH_LINK_DOWN;
2442 link.link_autoneg = ETH_LINK_FIXED;
2445 return rte_eth_linkstatus_set(dev, &link);
2449 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2450 * For ASF and Pass Through versions of f/w this means
2451 * that the driver is loaded.
2454 igb_hw_control_acquire(struct e1000_hw *hw)
2458 /* Let firmware know the driver has taken over */
2459 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2460 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2464 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2465 * For ASF and Pass Through versions of f/w this means that the
2466 * driver is no longer loaded.
2469 igb_hw_control_release(struct e1000_hw *hw)
2473 /* Let firmware taken over control of h/w */
2474 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2475 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2476 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2480 * Bit of a misnomer, what this really means is
2481 * to enable OS management of the system... aka
2482 * to disable special hardware management features.
2485 igb_init_manageability(struct e1000_hw *hw)
2487 if (e1000_enable_mng_pass_thru(hw)) {
2488 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2489 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2491 /* disable hardware interception of ARP */
2492 manc &= ~(E1000_MANC_ARP_EN);
2494 /* enable receiving management packets to the host */
2495 manc |= E1000_MANC_EN_MNG2HOST;
2496 manc2h |= 1 << 5; /* Mng Port 623 */
2497 manc2h |= 1 << 6; /* Mng Port 664 */
2498 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2499 E1000_WRITE_REG(hw, E1000_MANC, manc);
2504 igb_release_manageability(struct e1000_hw *hw)
2506 if (e1000_enable_mng_pass_thru(hw)) {
2507 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2509 manc |= E1000_MANC_ARP_EN;
2510 manc &= ~E1000_MANC_EN_MNG2HOST;
2512 E1000_WRITE_REG(hw, E1000_MANC, manc);
2517 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2519 struct e1000_hw *hw =
2520 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523 rctl = E1000_READ_REG(hw, E1000_RCTL);
2524 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2525 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2531 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2533 struct e1000_hw *hw =
2534 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537 rctl = E1000_READ_REG(hw, E1000_RCTL);
2538 rctl &= (~E1000_RCTL_UPE);
2539 if (dev->data->all_multicast == 1)
2540 rctl |= E1000_RCTL_MPE;
2542 rctl &= (~E1000_RCTL_MPE);
2543 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2549 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2551 struct e1000_hw *hw =
2552 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555 rctl = E1000_READ_REG(hw, E1000_RCTL);
2556 rctl |= E1000_RCTL_MPE;
2557 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2563 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2565 struct e1000_hw *hw =
2566 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569 if (dev->data->promiscuous == 1)
2570 return 0; /* must remain in all_multicast mode */
2571 rctl = E1000_READ_REG(hw, E1000_RCTL);
2572 rctl &= (~E1000_RCTL_MPE);
2573 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2579 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2581 struct e1000_hw *hw =
2582 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2583 struct e1000_vfta * shadow_vfta =
2584 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2589 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2590 E1000_VFTA_ENTRY_MASK);
2591 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2592 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2597 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2599 /* update local VFTA copy */
2600 shadow_vfta->vfta[vid_idx] = vfta;
2606 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2607 enum rte_vlan_type vlan_type,
2610 struct e1000_hw *hw =
2611 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2614 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2615 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2617 /* only outer TPID of double VLAN can be configured*/
2618 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2619 reg = E1000_READ_REG(hw, E1000_VET);
2620 reg = (reg & (~E1000_VET_VET_EXT)) |
2621 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2622 E1000_WRITE_REG(hw, E1000_VET, reg);
2627 /* all other TPID values are read-only*/
2628 PMD_DRV_LOG(ERR, "Not supported");
2634 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2636 struct e1000_hw *hw =
2637 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640 /* Filter Table Disable */
2641 reg = E1000_READ_REG(hw, E1000_RCTL);
2642 reg &= ~E1000_RCTL_CFIEN;
2643 reg &= ~E1000_RCTL_VFE;
2644 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2648 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2650 struct e1000_hw *hw =
2651 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2652 struct e1000_vfta * shadow_vfta =
2653 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2657 /* Filter Table Enable, CFI not used for packet acceptance */
2658 reg = E1000_READ_REG(hw, E1000_RCTL);
2659 reg &= ~E1000_RCTL_CFIEN;
2660 reg |= E1000_RCTL_VFE;
2661 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2663 /* restore VFTA table */
2664 for (i = 0; i < IGB_VFTA_SIZE; i++)
2665 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2669 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2671 struct e1000_hw *hw =
2672 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2675 /* VLAN Mode Disable */
2676 reg = E1000_READ_REG(hw, E1000_CTRL);
2677 reg &= ~E1000_CTRL_VME;
2678 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2682 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2684 struct e1000_hw *hw =
2685 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2688 /* VLAN Mode Enable */
2689 reg = E1000_READ_REG(hw, E1000_CTRL);
2690 reg |= E1000_CTRL_VME;
2691 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2695 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2697 struct e1000_hw *hw =
2698 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2701 /* CTRL_EXT: Extended VLAN */
2702 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2703 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2704 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2706 /* Update maximum packet length */
2707 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2708 E1000_WRITE_REG(hw, E1000_RLPML,
2709 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2714 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2716 struct e1000_hw *hw =
2717 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2720 /* CTRL_EXT: Extended VLAN */
2721 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2722 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2723 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2725 /* Update maximum packet length */
2726 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2727 E1000_WRITE_REG(hw, E1000_RLPML,
2728 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2733 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2735 struct rte_eth_rxmode *rxmode;
2737 rxmode = &dev->data->dev_conf.rxmode;
2738 if(mask & ETH_VLAN_STRIP_MASK){
2739 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2740 igb_vlan_hw_strip_enable(dev);
2742 igb_vlan_hw_strip_disable(dev);
2745 if(mask & ETH_VLAN_FILTER_MASK){
2746 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2747 igb_vlan_hw_filter_enable(dev);
2749 igb_vlan_hw_filter_disable(dev);
2752 if(mask & ETH_VLAN_EXTEND_MASK){
2753 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2754 igb_vlan_hw_extend_enable(dev);
2756 igb_vlan_hw_extend_disable(dev);
2764 * It enables the interrupt mask and then enable the interrupt.
2767 * Pointer to struct rte_eth_dev.
2772 * - On success, zero.
2773 * - On failure, a negative value.
2776 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2778 struct e1000_interrupt *intr =
2779 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2782 intr->mask |= E1000_ICR_LSC;
2784 intr->mask &= ~E1000_ICR_LSC;
2789 /* It clears the interrupt causes and enables the interrupt.
2790 * It will be called once only during nic initialized.
2793 * Pointer to struct rte_eth_dev.
2796 * - On success, zero.
2797 * - On failure, a negative value.
2799 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2801 uint32_t mask, regval;
2803 struct e1000_hw *hw =
2804 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2805 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2806 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2807 int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2808 struct rte_eth_dev_info dev_info;
2810 memset(&dev_info, 0, sizeof(dev_info));
2811 ret = eth_igb_infos_get(dev, &dev_info);
2815 mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2816 regval = E1000_READ_REG(hw, E1000_EIMS);
2817 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2823 * It reads ICR and gets interrupt causes, check it and set a bit flag
2824 * to update link status.
2827 * Pointer to struct rte_eth_dev.
2830 * - On success, zero.
2831 * - On failure, a negative value.
2834 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2837 struct e1000_hw *hw =
2838 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839 struct e1000_interrupt *intr =
2840 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2842 igb_intr_disable(dev);
2844 /* read-on-clear nic registers here */
2845 icr = E1000_READ_REG(hw, E1000_ICR);
2848 if (icr & E1000_ICR_LSC) {
2849 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2852 if (icr & E1000_ICR_VMMB)
2853 intr->flags |= E1000_FLAG_MAILBOX;
2859 * It executes link_update after knowing an interrupt is prsent.
2862 * Pointer to struct rte_eth_dev.
2865 * - On success, zero.
2866 * - On failure, a negative value.
2869 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2870 struct rte_intr_handle *intr_handle)
2872 struct e1000_hw *hw =
2873 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2874 struct e1000_interrupt *intr =
2875 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2876 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2877 struct rte_eth_link link;
2880 if (intr->flags & E1000_FLAG_MAILBOX) {
2881 igb_pf_mbx_process(dev);
2882 intr->flags &= ~E1000_FLAG_MAILBOX;
2885 igb_intr_enable(dev);
2886 rte_intr_ack(intr_handle);
2888 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2889 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2891 /* set get_link_status to check register later */
2892 hw->mac.get_link_status = 1;
2893 ret = eth_igb_link_update(dev, 0);
2895 /* check if link has changed */
2899 rte_eth_linkstatus_get(dev, &link);
2900 if (link.link_status) {
2902 " Port %d: Link Up - speed %u Mbps - %s",
2904 (unsigned)link.link_speed,
2905 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2906 "full-duplex" : "half-duplex");
2908 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2909 dev->data->port_id);
2912 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2913 pci_dev->addr.domain,
2915 pci_dev->addr.devid,
2916 pci_dev->addr.function);
2917 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2925 * Interrupt handler which shall be registered at first.
2928 * Pointer to interrupt handle.
2930 * The address of parameter (struct rte_eth_dev *) regsitered before.
2936 eth_igb_interrupt_handler(void *param)
2938 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2940 eth_igb_interrupt_get_status(dev);
2941 eth_igb_interrupt_action(dev, dev->intr_handle);
2945 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2948 struct e1000_hw *hw =
2949 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2950 struct e1000_interrupt *intr =
2951 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2953 igbvf_intr_disable(hw);
2955 /* read-on-clear nic registers here */
2956 eicr = E1000_READ_REG(hw, E1000_EICR);
2959 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2960 intr->flags |= E1000_FLAG_MAILBOX;
2965 void igbvf_mbx_process(struct rte_eth_dev *dev)
2967 struct e1000_hw *hw =
2968 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2969 struct e1000_mbx_info *mbx = &hw->mbx;
2972 /* peek the message first */
2973 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2975 /* PF reset VF event */
2976 if (in_msg == E1000_PF_CONTROL_MSG) {
2977 /* dummy mbx read to ack pf */
2978 if (mbx->ops.read(hw, &in_msg, 1, 0))
2980 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2986 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2988 struct e1000_interrupt *intr =
2989 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2991 if (intr->flags & E1000_FLAG_MAILBOX) {
2992 igbvf_mbx_process(dev);
2993 intr->flags &= ~E1000_FLAG_MAILBOX;
2996 igbvf_intr_enable(dev);
2997 rte_intr_ack(intr_handle);
3003 eth_igbvf_interrupt_handler(void *param)
3005 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3007 eth_igbvf_interrupt_get_status(dev);
3008 eth_igbvf_interrupt_action(dev, dev->intr_handle);
3012 eth_igb_led_on(struct rte_eth_dev *dev)
3014 struct e1000_hw *hw;
3016 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3017 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3021 eth_igb_led_off(struct rte_eth_dev *dev)
3023 struct e1000_hw *hw;
3025 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3026 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3030 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3032 struct e1000_hw *hw;
3037 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3038 fc_conf->pause_time = hw->fc.pause_time;
3039 fc_conf->high_water = hw->fc.high_water;
3040 fc_conf->low_water = hw->fc.low_water;
3041 fc_conf->send_xon = hw->fc.send_xon;
3042 fc_conf->autoneg = hw->mac.autoneg;
3045 * Return rx_pause and tx_pause status according to actual setting of
3046 * the TFCE and RFCE bits in the CTRL register.
3048 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3049 if (ctrl & E1000_CTRL_TFCE)
3054 if (ctrl & E1000_CTRL_RFCE)
3059 if (rx_pause && tx_pause)
3060 fc_conf->mode = RTE_FC_FULL;
3062 fc_conf->mode = RTE_FC_RX_PAUSE;
3064 fc_conf->mode = RTE_FC_TX_PAUSE;
3066 fc_conf->mode = RTE_FC_NONE;
3072 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3074 struct e1000_hw *hw;
3076 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3082 uint32_t rx_buf_size;
3083 uint32_t max_high_water;
3086 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3087 if (fc_conf->autoneg != hw->mac.autoneg)
3089 rx_buf_size = igb_get_rx_buffer_size(hw);
3090 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3092 /* At least reserve one Ethernet frame for watermark */
3093 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3094 if ((fc_conf->high_water > max_high_water) ||
3095 (fc_conf->high_water < fc_conf->low_water)) {
3096 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3097 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
3101 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3102 hw->fc.pause_time = fc_conf->pause_time;
3103 hw->fc.high_water = fc_conf->high_water;
3104 hw->fc.low_water = fc_conf->low_water;
3105 hw->fc.send_xon = fc_conf->send_xon;
3107 err = e1000_setup_link_generic(hw);
3108 if (err == E1000_SUCCESS) {
3110 /* check if we want to forward MAC frames - driver doesn't have native
3111 * capability to do that, so we'll write the registers ourselves */
3113 rctl = E1000_READ_REG(hw, E1000_RCTL);
3115 /* set or clear MFLCN.PMCF bit depending on configuration */
3116 if (fc_conf->mac_ctrl_frame_fwd != 0)
3117 rctl |= E1000_RCTL_PMCF;
3119 rctl &= ~E1000_RCTL_PMCF;
3121 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3122 E1000_WRITE_FLUSH(hw);
3127 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3131 #define E1000_RAH_POOLSEL_SHIFT (18)
3133 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3134 uint32_t index, uint32_t pool)
3136 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3139 e1000_rar_set(hw, mac_addr->addr_bytes, index);
3140 rah = E1000_READ_REG(hw, E1000_RAH(index));
3141 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3142 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3147 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3149 uint8_t addr[RTE_ETHER_ADDR_LEN];
3150 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3152 memset(addr, 0, sizeof(addr));
3154 e1000_rar_set(hw, addr, index);
3158 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3159 struct rte_ether_addr *addr)
3161 eth_igb_rar_clear(dev, 0);
3162 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3167 * Virtual Function operations
3170 igbvf_intr_disable(struct e1000_hw *hw)
3172 PMD_INIT_FUNC_TRACE();
3174 /* Clear interrupt mask to stop from interrupts being generated */
3175 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3177 E1000_WRITE_FLUSH(hw);
3181 igbvf_stop_adapter(struct rte_eth_dev *dev)
3185 struct rte_eth_dev_info dev_info;
3186 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3189 memset(&dev_info, 0, sizeof(dev_info));
3190 ret = eth_igbvf_infos_get(dev, &dev_info);
3194 /* Clear interrupt mask to stop from interrupts being generated */
3195 igbvf_intr_disable(hw);
3197 /* Clear any pending interrupts, flush previous writes */
3198 E1000_READ_REG(hw, E1000_EICR);
3200 /* Disable the transmit unit. Each queue must be disabled. */
3201 for (i = 0; i < dev_info.max_tx_queues; i++)
3202 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3204 /* Disable the receive unit by stopping each queue */
3205 for (i = 0; i < dev_info.max_rx_queues; i++) {
3206 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3207 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3208 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3209 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3213 /* flush all queues disables */
3214 E1000_WRITE_FLUSH(hw);
3218 static int eth_igbvf_link_update(struct e1000_hw *hw)
3220 struct e1000_mbx_info *mbx = &hw->mbx;
3221 struct e1000_mac_info *mac = &hw->mac;
3222 int ret_val = E1000_SUCCESS;
3224 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3227 * We only want to run this if there has been a rst asserted.
3228 * in this case that could mean a link change, device reset,
3229 * or a virtual function reset
3232 /* If we were hit with a reset or timeout drop the link */
3233 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3234 mac->get_link_status = TRUE;
3236 if (!mac->get_link_status)
3239 /* if link status is down no point in checking to see if pf is up */
3240 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3243 /* if we passed all the tests above then the link is up and we no
3244 * longer need to check for link */
3245 mac->get_link_status = FALSE;
3253 igbvf_dev_configure(struct rte_eth_dev *dev)
3255 struct rte_eth_conf* conf = &dev->data->dev_conf;
3257 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3258 dev->data->port_id);
3261 * VF has no ability to enable/disable HW CRC
3262 * Keep the persistent behavior the same as Host PF
3264 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3265 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3266 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3267 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3270 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3271 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3272 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3280 igbvf_dev_start(struct rte_eth_dev *dev)
3282 struct e1000_hw *hw =
3283 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3284 struct e1000_adapter *adapter =
3285 E1000_DEV_PRIVATE(dev->data->dev_private);
3286 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3287 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3289 uint32_t intr_vector = 0;
3291 PMD_INIT_FUNC_TRACE();
3293 hw->mac.ops.reset_hw(hw);
3294 adapter->stopped = 0;
3297 igbvf_set_vfta_all(dev,1);
3299 eth_igbvf_tx_init(dev);
3301 /* This can fail when allocating mbufs for descriptor rings */
3302 ret = eth_igbvf_rx_init(dev);
3304 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3305 igb_dev_clear_queues(dev);
3309 /* check and configure queue intr-vector mapping */
3310 if (rte_intr_cap_multiple(intr_handle) &&
3311 dev->data->dev_conf.intr_conf.rxq) {
3312 intr_vector = dev->data->nb_rx_queues;
3313 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3318 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3319 intr_handle->intr_vec =
3320 rte_zmalloc("intr_vec",
3321 dev->data->nb_rx_queues * sizeof(int), 0);
3322 if (!intr_handle->intr_vec) {
3323 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3324 " intr_vec", dev->data->nb_rx_queues);
3329 eth_igbvf_configure_msix_intr(dev);
3331 /* enable uio/vfio intr/eventfd mapping */
3332 rte_intr_enable(intr_handle);
3334 /* resume enabled intr since hw reset */
3335 igbvf_intr_enable(dev);
3341 igbvf_dev_stop(struct rte_eth_dev *dev)
3343 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3344 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3345 struct e1000_adapter *adapter =
3346 E1000_DEV_PRIVATE(dev->data->dev_private);
3348 if (adapter->stopped)
3351 PMD_INIT_FUNC_TRACE();
3353 igbvf_stop_adapter(dev);
3356 * Clear what we set, but we still keep shadow_vfta to
3357 * restore after device starts
3359 igbvf_set_vfta_all(dev,0);
3361 igb_dev_clear_queues(dev);
3363 /* disable intr eventfd mapping */
3364 rte_intr_disable(intr_handle);
3366 /* Clean datapath event and queue/vec mapping */
3367 rte_intr_efd_disable(intr_handle);
3368 if (intr_handle->intr_vec) {
3369 rte_free(intr_handle->intr_vec);
3370 intr_handle->intr_vec = NULL;
3373 adapter->stopped = true;
3377 igbvf_dev_close(struct rte_eth_dev *dev)
3379 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3380 struct rte_ether_addr addr;
3381 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3383 PMD_INIT_FUNC_TRACE();
3387 igbvf_dev_stop(dev);
3389 igb_dev_free_queues(dev);
3392 * reprogram the RAR with a zero mac address,
3393 * to ensure that the VF traffic goes to the PF
3394 * after stop, close and detach of the VF.
3397 memset(&addr, 0, sizeof(addr));
3398 igbvf_default_mac_addr_set(dev, &addr);
3400 dev->dev_ops = NULL;
3401 dev->rx_pkt_burst = NULL;
3402 dev->tx_pkt_burst = NULL;
3404 rte_intr_callback_unregister(&pci_dev->intr_handle,
3405 eth_igbvf_interrupt_handler,
3410 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3412 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3414 /* Set both unicast and multicast promisc */
3415 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3421 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3423 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425 /* If in allmulticast mode leave multicast promisc */
3426 if (dev->data->all_multicast == 1)
3427 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3429 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3435 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3437 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3439 /* In promiscuous mode multicast promisc already set */
3440 if (dev->data->promiscuous == 0)
3441 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3447 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3449 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3451 /* In promiscuous mode leave multicast promisc enabled */
3452 if (dev->data->promiscuous == 0)
3453 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3458 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3460 struct e1000_mbx_info *mbx = &hw->mbx;
3464 /* After set vlan, vlan strip will also be enabled in igb driver*/
3465 msgbuf[0] = E1000_VF_SET_VLAN;
3467 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3469 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3471 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3475 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3479 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3480 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3487 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3489 struct e1000_hw *hw =
3490 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3491 struct e1000_vfta * shadow_vfta =
3492 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3493 int i = 0, j = 0, vfta = 0, mask = 1;
3495 for (i = 0; i < IGB_VFTA_SIZE; i++){
3496 vfta = shadow_vfta->vfta[i];
3499 for (j = 0; j < 32; j++){
3502 (uint16_t)((i<<5)+j), on);
3511 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3513 struct e1000_hw *hw =
3514 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3515 struct e1000_vfta * shadow_vfta =
3516 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3517 uint32_t vid_idx = 0;
3518 uint32_t vid_bit = 0;
3521 PMD_INIT_FUNC_TRACE();
3523 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3524 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3526 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3529 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3530 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3532 /*Save what we set and retore it after device reset*/
3534 shadow_vfta->vfta[vid_idx] |= vid_bit;
3536 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3542 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3544 struct e1000_hw *hw =
3545 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3547 /* index is not used by rar_set() */
3548 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3554 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3555 struct rte_eth_rss_reta_entry64 *reta_conf,
3560 uint16_t idx, shift;
3561 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3563 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3564 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3565 "(%d) doesn't match the number hardware can supported "
3566 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3570 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3571 idx = i / RTE_RETA_GROUP_SIZE;
3572 shift = i % RTE_RETA_GROUP_SIZE;
3573 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3577 if (mask == IGB_4_BIT_MASK)
3580 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3581 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3582 if (mask & (0x1 << j))
3583 reta |= reta_conf[idx].reta[shift + j] <<
3586 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3588 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3595 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3596 struct rte_eth_rss_reta_entry64 *reta_conf,
3601 uint16_t idx, shift;
3602 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3604 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3605 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3606 "(%d) doesn't match the number hardware can supported "
3607 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3611 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3612 idx = i / RTE_RETA_GROUP_SIZE;
3613 shift = i % RTE_RETA_GROUP_SIZE;
3614 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3618 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3619 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3620 if (mask & (0x1 << j))
3621 reta_conf[idx].reta[shift + j] =
3622 ((reta >> (CHAR_BIT * j)) &
3631 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3632 struct rte_eth_syn_filter *filter,
3635 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3636 struct e1000_filter_info *filter_info =
3637 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3638 uint32_t synqf, rfctl;
3640 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3643 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3646 if (synqf & E1000_SYN_FILTER_ENABLE)
3649 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3650 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3652 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3653 if (filter->hig_pri)
3654 rfctl |= E1000_RFCTL_SYNQFP;
3656 rfctl &= ~E1000_RFCTL_SYNQFP;
3658 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3660 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3665 filter_info->syn_info = synqf;
3666 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3667 E1000_WRITE_FLUSH(hw);
3672 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3673 struct rte_eth_syn_filter *filter)
3675 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3676 uint32_t synqf, rfctl;
3678 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3679 if (synqf & E1000_SYN_FILTER_ENABLE) {
3680 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3681 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3682 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3683 E1000_SYN_FILTER_QUEUE_SHIFT);
3691 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3692 enum rte_filter_op filter_op,
3695 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3698 MAC_TYPE_FILTER_SUP(hw->mac.type);
3700 if (filter_op == RTE_ETH_FILTER_NOP)
3704 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3709 switch (filter_op) {
3710 case RTE_ETH_FILTER_ADD:
3711 ret = eth_igb_syn_filter_set(dev,
3712 (struct rte_eth_syn_filter *)arg,
3715 case RTE_ETH_FILTER_DELETE:
3716 ret = eth_igb_syn_filter_set(dev,
3717 (struct rte_eth_syn_filter *)arg,
3720 case RTE_ETH_FILTER_GET:
3721 ret = eth_igb_syn_filter_get(dev,
3722 (struct rte_eth_syn_filter *)arg);
3725 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3733 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3735 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3736 struct e1000_2tuple_filter_info *filter_info)
3738 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3740 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3741 return -EINVAL; /* filter index is out of range. */
3742 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3743 return -EINVAL; /* flags is invalid. */
3745 switch (filter->dst_port_mask) {
3747 filter_info->dst_port_mask = 0;
3748 filter_info->dst_port = filter->dst_port;
3751 filter_info->dst_port_mask = 1;
3754 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3758 switch (filter->proto_mask) {
3760 filter_info->proto_mask = 0;
3761 filter_info->proto = filter->proto;
3764 filter_info->proto_mask = 1;
3767 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3771 filter_info->priority = (uint8_t)filter->priority;
3772 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3773 filter_info->tcp_flags = filter->tcp_flags;
3775 filter_info->tcp_flags = 0;
3780 static inline struct e1000_2tuple_filter *
3781 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3782 struct e1000_2tuple_filter_info *key)
3784 struct e1000_2tuple_filter *it;
3786 TAILQ_FOREACH(it, filter_list, entries) {
3787 if (memcmp(key, &it->filter_info,
3788 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3795 /* inject a igb 2tuple filter to HW */
3797 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3798 struct e1000_2tuple_filter *filter)
3800 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3801 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3802 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3806 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3807 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3808 imir |= E1000_IMIR_PORT_BP;
3810 imir &= ~E1000_IMIR_PORT_BP;
3812 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3814 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3815 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3816 ttqf |= (uint32_t)(filter->filter_info.proto &
3817 E1000_TTQF_PROTOCOL_MASK);
3818 if (filter->filter_info.proto_mask == 0)
3819 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3821 /* tcp flags bits setting. */
3822 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3823 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3824 imir_ext |= E1000_IMIREXT_CTRL_URG;
3825 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3826 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3827 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3828 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3829 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3830 imir_ext |= E1000_IMIREXT_CTRL_RST;
3831 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3832 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3833 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3834 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3836 imir_ext |= E1000_IMIREXT_CTRL_BP;
3838 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3839 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3840 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3844 * igb_add_2tuple_filter - add a 2tuple filter
3847 * dev: Pointer to struct rte_eth_dev.
3848 * ntuple_filter: ponter to the filter that will be added.
3851 * - On success, zero.
3852 * - On failure, a negative value.
3855 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3856 struct rte_eth_ntuple_filter *ntuple_filter)
3858 struct e1000_filter_info *filter_info =
3859 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3860 struct e1000_2tuple_filter *filter;
3863 filter = rte_zmalloc("e1000_2tuple_filter",
3864 sizeof(struct e1000_2tuple_filter), 0);
3868 ret = ntuple_filter_to_2tuple(ntuple_filter,
3869 &filter->filter_info);
3874 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3875 &filter->filter_info) != NULL) {
3876 PMD_DRV_LOG(ERR, "filter exists.");
3880 filter->queue = ntuple_filter->queue;
3883 * look for an unused 2tuple filter index,
3884 * and insert the filter to list.
3886 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3887 if (!(filter_info->twotuple_mask & (1 << i))) {
3888 filter_info->twotuple_mask |= 1 << i;
3890 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3896 if (i >= E1000_MAX_TTQF_FILTERS) {
3897 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3902 igb_inject_2uple_filter(dev, filter);
3907 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3908 struct e1000_2tuple_filter *filter)
3910 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3911 struct e1000_filter_info *filter_info =
3912 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3914 filter_info->twotuple_mask &= ~(1 << filter->index);
3915 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3918 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3919 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3920 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3925 * igb_remove_2tuple_filter - remove a 2tuple filter
3928 * dev: Pointer to struct rte_eth_dev.
3929 * ntuple_filter: ponter to the filter that will be removed.
3932 * - On success, zero.
3933 * - On failure, a negative value.
3936 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3937 struct rte_eth_ntuple_filter *ntuple_filter)
3939 struct e1000_filter_info *filter_info =
3940 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3941 struct e1000_2tuple_filter_info filter_2tuple;
3942 struct e1000_2tuple_filter *filter;
3945 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3946 ret = ntuple_filter_to_2tuple(ntuple_filter,
3951 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3953 if (filter == NULL) {
3954 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3958 igb_delete_2tuple_filter(dev, filter);
3963 /* inject a igb flex filter to HW */
3965 igb_inject_flex_filter(struct rte_eth_dev *dev,
3966 struct e1000_flex_filter *filter)
3968 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3969 uint32_t wufc, queueing;
3973 wufc = E1000_READ_REG(hw, E1000_WUFC);
3974 if (filter->index < E1000_MAX_FHFT)
3975 reg_off = E1000_FHFT(filter->index);
3977 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3979 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3980 (E1000_WUFC_FLX0 << filter->index));
3981 queueing = filter->filter_info.len |
3982 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3983 (filter->filter_info.priority <<
3984 E1000_FHFT_QUEUEING_PRIO_SHIFT);
3985 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3988 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3989 E1000_WRITE_REG(hw, reg_off,
3990 filter->filter_info.dwords[j]);
3991 reg_off += sizeof(uint32_t);
3992 E1000_WRITE_REG(hw, reg_off,
3993 filter->filter_info.dwords[++j]);
3994 reg_off += sizeof(uint32_t);
3995 E1000_WRITE_REG(hw, reg_off,
3996 (uint32_t)filter->filter_info.mask[i]);
3997 reg_off += sizeof(uint32_t) * 2;
4002 static inline struct e1000_flex_filter *
4003 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
4004 struct e1000_flex_filter_info *key)
4006 struct e1000_flex_filter *it;
4008 TAILQ_FOREACH(it, filter_list, entries) {
4009 if (memcmp(key, &it->filter_info,
4010 sizeof(struct e1000_flex_filter_info)) == 0)
4017 /* remove a flex byte filter
4019 * dev: Pointer to struct rte_eth_dev.
4020 * filter: the pointer of the filter will be removed.
4023 igb_remove_flex_filter(struct rte_eth_dev *dev,
4024 struct e1000_flex_filter *filter)
4026 struct e1000_filter_info *filter_info =
4027 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4028 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4032 wufc = E1000_READ_REG(hw, E1000_WUFC);
4033 if (filter->index < E1000_MAX_FHFT)
4034 reg_off = E1000_FHFT(filter->index);
4036 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4038 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4039 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4041 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4042 (~(E1000_WUFC_FLX0 << filter->index)));
4044 filter_info->flex_mask &= ~(1 << filter->index);
4045 TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4050 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4051 struct rte_eth_flex_filter *filter,
4054 struct e1000_filter_info *filter_info =
4055 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4056 struct e1000_flex_filter *flex_filter, *it;
4060 flex_filter = rte_zmalloc("e1000_flex_filter",
4061 sizeof(struct e1000_flex_filter), 0);
4062 if (flex_filter == NULL)
4065 flex_filter->filter_info.len = filter->len;
4066 flex_filter->filter_info.priority = filter->priority;
4067 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4068 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4070 /* reverse bits in flex filter's mask*/
4071 for (shift = 0; shift < CHAR_BIT; shift++) {
4072 if (filter->mask[i] & (0x01 << shift))
4073 mask |= (0x80 >> shift);
4075 flex_filter->filter_info.mask[i] = mask;
4078 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4079 &flex_filter->filter_info);
4080 if (it == NULL && !add) {
4081 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4082 rte_free(flex_filter);
4085 if (it != NULL && add) {
4086 PMD_DRV_LOG(ERR, "filter exists.");
4087 rte_free(flex_filter);
4092 flex_filter->queue = filter->queue;
4094 * look for an unused flex filter index
4095 * and insert the filter into the list.
4097 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4098 if (!(filter_info->flex_mask & (1 << i))) {
4099 filter_info->flex_mask |= 1 << i;
4100 flex_filter->index = i;
4101 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4107 if (i >= E1000_MAX_FLEX_FILTERS) {
4108 PMD_DRV_LOG(ERR, "flex filters are full.");
4109 rte_free(flex_filter);
4113 igb_inject_flex_filter(dev, flex_filter);
4116 igb_remove_flex_filter(dev, it);
4117 rte_free(flex_filter);
4124 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4125 struct rte_eth_flex_filter *filter)
4127 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4128 struct e1000_filter_info *filter_info =
4129 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4130 struct e1000_flex_filter flex_filter, *it;
4131 uint32_t wufc, queueing, wufc_en = 0;
4133 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4134 flex_filter.filter_info.len = filter->len;
4135 flex_filter.filter_info.priority = filter->priority;
4136 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4137 memcpy(flex_filter.filter_info.mask, filter->mask,
4138 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4140 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4141 &flex_filter.filter_info);
4143 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4147 wufc = E1000_READ_REG(hw, E1000_WUFC);
4148 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4150 if ((wufc & wufc_en) == wufc_en) {
4151 uint32_t reg_off = 0;
4152 if (it->index < E1000_MAX_FHFT)
4153 reg_off = E1000_FHFT(it->index);
4155 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4157 queueing = E1000_READ_REG(hw,
4158 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4159 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4160 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4161 E1000_FHFT_QUEUEING_PRIO_SHIFT;
4162 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4163 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4170 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4171 enum rte_filter_op filter_op,
4174 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4175 struct rte_eth_flex_filter *filter;
4178 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4180 if (filter_op == RTE_ETH_FILTER_NOP)
4184 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4189 filter = (struct rte_eth_flex_filter *)arg;
4190 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4191 || filter->len % sizeof(uint64_t) != 0) {
4192 PMD_DRV_LOG(ERR, "filter's length is out of range");
4195 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4196 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4200 switch (filter_op) {
4201 case RTE_ETH_FILTER_ADD:
4202 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4204 case RTE_ETH_FILTER_DELETE:
4205 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4207 case RTE_ETH_FILTER_GET:
4208 ret = eth_igb_get_flex_filter(dev, filter);
4211 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4219 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4221 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4222 struct e1000_5tuple_filter_info *filter_info)
4224 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4226 if (filter->priority > E1000_2TUPLE_MAX_PRI)
4227 return -EINVAL; /* filter index is out of range. */
4228 if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4229 return -EINVAL; /* flags is invalid. */
4231 switch (filter->dst_ip_mask) {
4233 filter_info->dst_ip_mask = 0;
4234 filter_info->dst_ip = filter->dst_ip;
4237 filter_info->dst_ip_mask = 1;
4240 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4244 switch (filter->src_ip_mask) {
4246 filter_info->src_ip_mask = 0;
4247 filter_info->src_ip = filter->src_ip;
4250 filter_info->src_ip_mask = 1;
4253 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4257 switch (filter->dst_port_mask) {
4259 filter_info->dst_port_mask = 0;
4260 filter_info->dst_port = filter->dst_port;
4263 filter_info->dst_port_mask = 1;
4266 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4270 switch (filter->src_port_mask) {
4272 filter_info->src_port_mask = 0;
4273 filter_info->src_port = filter->src_port;
4276 filter_info->src_port_mask = 1;
4279 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4283 switch (filter->proto_mask) {
4285 filter_info->proto_mask = 0;
4286 filter_info->proto = filter->proto;
4289 filter_info->proto_mask = 1;
4292 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4296 filter_info->priority = (uint8_t)filter->priority;
4297 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4298 filter_info->tcp_flags = filter->tcp_flags;
4300 filter_info->tcp_flags = 0;
4305 static inline struct e1000_5tuple_filter *
4306 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4307 struct e1000_5tuple_filter_info *key)
4309 struct e1000_5tuple_filter *it;
4311 TAILQ_FOREACH(it, filter_list, entries) {
4312 if (memcmp(key, &it->filter_info,
4313 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4320 /* inject a igb 5-tuple filter to HW */
4322 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4323 struct e1000_5tuple_filter *filter)
4325 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4326 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4327 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4331 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4332 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4333 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4334 if (filter->filter_info.dst_ip_mask == 0)
4335 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4336 if (filter->filter_info.src_port_mask == 0)
4337 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4338 if (filter->filter_info.proto_mask == 0)
4339 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4340 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4341 E1000_FTQF_QUEUE_MASK;
4342 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4343 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4344 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4345 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4347 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4348 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4350 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4351 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4352 imir |= E1000_IMIR_PORT_BP;
4354 imir &= ~E1000_IMIR_PORT_BP;
4355 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4357 /* tcp flags bits setting. */
4358 if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4359 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4360 imir_ext |= E1000_IMIREXT_CTRL_URG;
4361 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4362 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4363 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4364 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4365 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4366 imir_ext |= E1000_IMIREXT_CTRL_RST;
4367 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4368 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4369 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4370 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4372 imir_ext |= E1000_IMIREXT_CTRL_BP;
4374 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4375 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4379 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4382 * dev: Pointer to struct rte_eth_dev.
4383 * ntuple_filter: ponter to the filter that will be added.
4386 * - On success, zero.
4387 * - On failure, a negative value.
4390 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4391 struct rte_eth_ntuple_filter *ntuple_filter)
4393 struct e1000_filter_info *filter_info =
4394 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4395 struct e1000_5tuple_filter *filter;
4399 filter = rte_zmalloc("e1000_5tuple_filter",
4400 sizeof(struct e1000_5tuple_filter), 0);
4404 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4405 &filter->filter_info);
4411 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4412 &filter->filter_info) != NULL) {
4413 PMD_DRV_LOG(ERR, "filter exists.");
4417 filter->queue = ntuple_filter->queue;
4420 * look for an unused 5tuple filter index,
4421 * and insert the filter to list.
4423 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4424 if (!(filter_info->fivetuple_mask & (1 << i))) {
4425 filter_info->fivetuple_mask |= 1 << i;
4427 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4433 if (i >= E1000_MAX_FTQF_FILTERS) {
4434 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4439 igb_inject_5tuple_filter_82576(dev, filter);
4444 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4445 struct e1000_5tuple_filter *filter)
4447 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4448 struct e1000_filter_info *filter_info =
4449 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4451 filter_info->fivetuple_mask &= ~(1 << filter->index);
4452 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4455 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4456 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4457 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4458 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4459 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4460 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4461 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4466 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4469 * dev: Pointer to struct rte_eth_dev.
4470 * ntuple_filter: ponter to the filter that will be removed.
4473 * - On success, zero.
4474 * - On failure, a negative value.
4477 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4478 struct rte_eth_ntuple_filter *ntuple_filter)
4480 struct e1000_filter_info *filter_info =
4481 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4482 struct e1000_5tuple_filter_info filter_5tuple;
4483 struct e1000_5tuple_filter *filter;
4486 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4487 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4492 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4494 if (filter == NULL) {
4495 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4499 igb_delete_5tuple_filter_82576(dev, filter);
4505 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4508 struct e1000_hw *hw;
4509 struct rte_eth_dev_info dev_info;
4510 uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4513 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4515 #ifdef RTE_LIBRTE_82571_SUPPORT
4516 /* XXX: not bigger than max_rx_pktlen */
4517 if (hw->mac.type == e1000_82571)
4520 ret = eth_igb_infos_get(dev, &dev_info);
4524 /* check that mtu is within the allowed range */
4525 if (mtu < RTE_ETHER_MIN_MTU ||
4526 frame_size > dev_info.max_rx_pktlen)
4529 /* refuse mtu that requires the support of scattered packets when this
4530 * feature has not been enabled before. */
4531 if (!dev->data->scattered_rx &&
4532 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4535 rctl = E1000_READ_REG(hw, E1000_RCTL);
4537 /* switch to jumbo mode if needed */
4538 if (frame_size > RTE_ETHER_MAX_LEN) {
4539 dev->data->dev_conf.rxmode.offloads |=
4540 DEV_RX_OFFLOAD_JUMBO_FRAME;
4541 rctl |= E1000_RCTL_LPE;
4543 dev->data->dev_conf.rxmode.offloads &=
4544 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4545 rctl &= ~E1000_RCTL_LPE;
4547 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4549 /* update max frame size */
4550 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4552 E1000_WRITE_REG(hw, E1000_RLPML,
4553 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4559 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4562 * dev: Pointer to struct rte_eth_dev.
4563 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4564 * add: if true, add filter, if false, remove filter
4567 * - On success, zero.
4568 * - On failure, a negative value.
4571 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4572 struct rte_eth_ntuple_filter *ntuple_filter,
4575 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4578 switch (ntuple_filter->flags) {
4579 case RTE_5TUPLE_FLAGS:
4580 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4581 if (hw->mac.type != e1000_82576)
4584 ret = igb_add_5tuple_filter_82576(dev,
4587 ret = igb_remove_5tuple_filter_82576(dev,
4590 case RTE_2TUPLE_FLAGS:
4591 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4592 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4593 hw->mac.type != e1000_i210 &&
4594 hw->mac.type != e1000_i211)
4597 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4599 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4610 * igb_get_ntuple_filter - get a ntuple filter
4613 * dev: Pointer to struct rte_eth_dev.
4614 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4617 * - On success, zero.
4618 * - On failure, a negative value.
4621 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4622 struct rte_eth_ntuple_filter *ntuple_filter)
4624 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4625 struct e1000_filter_info *filter_info =
4626 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4627 struct e1000_5tuple_filter_info filter_5tuple;
4628 struct e1000_2tuple_filter_info filter_2tuple;
4629 struct e1000_5tuple_filter *p_5tuple_filter;
4630 struct e1000_2tuple_filter *p_2tuple_filter;
4633 switch (ntuple_filter->flags) {
4634 case RTE_5TUPLE_FLAGS:
4635 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4636 if (hw->mac.type != e1000_82576)
4638 memset(&filter_5tuple,
4640 sizeof(struct e1000_5tuple_filter_info));
4641 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4645 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4646 &filter_info->fivetuple_list,
4648 if (p_5tuple_filter == NULL) {
4649 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4652 ntuple_filter->queue = p_5tuple_filter->queue;
4654 case RTE_2TUPLE_FLAGS:
4655 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4656 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4658 memset(&filter_2tuple,
4660 sizeof(struct e1000_2tuple_filter_info));
4661 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4664 p_2tuple_filter = igb_2tuple_filter_lookup(
4665 &filter_info->twotuple_list,
4667 if (p_2tuple_filter == NULL) {
4668 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4671 ntuple_filter->queue = p_2tuple_filter->queue;
4682 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4683 * @dev: pointer to rte_eth_dev structure
4684 * @filter_op:operation will be taken.
4685 * @arg: a pointer to specific structure corresponding to the filter_op
4688 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4689 enum rte_filter_op filter_op,
4692 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695 MAC_TYPE_FILTER_SUP(hw->mac.type);
4697 if (filter_op == RTE_ETH_FILTER_NOP)
4701 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4706 switch (filter_op) {
4707 case RTE_ETH_FILTER_ADD:
4708 ret = igb_add_del_ntuple_filter(dev,
4709 (struct rte_eth_ntuple_filter *)arg,
4712 case RTE_ETH_FILTER_DELETE:
4713 ret = igb_add_del_ntuple_filter(dev,
4714 (struct rte_eth_ntuple_filter *)arg,
4717 case RTE_ETH_FILTER_GET:
4718 ret = igb_get_ntuple_filter(dev,
4719 (struct rte_eth_ntuple_filter *)arg);
4722 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4730 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4735 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4736 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4737 (filter_info->ethertype_mask & (1 << i)))
4744 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4745 uint16_t ethertype, uint32_t etqf)
4749 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4750 if (!(filter_info->ethertype_mask & (1 << i))) {
4751 filter_info->ethertype_mask |= 1 << i;
4752 filter_info->ethertype_filters[i].ethertype = ethertype;
4753 filter_info->ethertype_filters[i].etqf = etqf;
4761 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4764 if (idx >= E1000_MAX_ETQF_FILTERS)
4766 filter_info->ethertype_mask &= ~(1 << idx);
4767 filter_info->ethertype_filters[idx].ethertype = 0;
4768 filter_info->ethertype_filters[idx].etqf = 0;
4774 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4775 struct rte_eth_ethertype_filter *filter,
4778 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4779 struct e1000_filter_info *filter_info =
4780 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4784 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4785 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4786 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4787 " ethertype filter.", filter->ether_type);
4791 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4792 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4795 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4796 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4800 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4801 if (ret >= 0 && add) {
4802 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4803 filter->ether_type);
4806 if (ret < 0 && !add) {
4807 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4808 filter->ether_type);
4813 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4814 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4815 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4816 ret = igb_ethertype_filter_insert(filter_info,
4817 filter->ether_type, etqf);
4819 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4823 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4827 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4828 E1000_WRITE_FLUSH(hw);
4834 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4835 struct rte_eth_ethertype_filter *filter)
4837 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4838 struct e1000_filter_info *filter_info =
4839 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4843 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4845 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4846 filter->ether_type);
4850 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4851 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4852 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4854 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4855 E1000_ETQF_QUEUE_SHIFT;
4863 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4864 * @dev: pointer to rte_eth_dev structure
4865 * @filter_op:operation will be taken.
4866 * @arg: a pointer to specific structure corresponding to the filter_op
4869 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4870 enum rte_filter_op filter_op,
4873 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4876 MAC_TYPE_FILTER_SUP(hw->mac.type);
4878 if (filter_op == RTE_ETH_FILTER_NOP)
4882 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4887 switch (filter_op) {
4888 case RTE_ETH_FILTER_ADD:
4889 ret = igb_add_del_ethertype_filter(dev,
4890 (struct rte_eth_ethertype_filter *)arg,
4893 case RTE_ETH_FILTER_DELETE:
4894 ret = igb_add_del_ethertype_filter(dev,
4895 (struct rte_eth_ethertype_filter *)arg,
4898 case RTE_ETH_FILTER_GET:
4899 ret = igb_get_ethertype_filter(dev,
4900 (struct rte_eth_ethertype_filter *)arg);
4903 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4911 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4912 enum rte_filter_type filter_type,
4913 enum rte_filter_op filter_op,
4918 switch (filter_type) {
4919 case RTE_ETH_FILTER_NTUPLE:
4920 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4922 case RTE_ETH_FILTER_ETHERTYPE:
4923 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4925 case RTE_ETH_FILTER_SYN:
4926 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4928 case RTE_ETH_FILTER_FLEXIBLE:
4929 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4931 case RTE_ETH_FILTER_GENERIC:
4932 if (filter_op != RTE_ETH_FILTER_GET)
4934 *(const void **)arg = &igb_flow_ops;
4937 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4946 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4947 struct rte_ether_addr *mc_addr_set,
4948 uint32_t nb_mc_addr)
4950 struct e1000_hw *hw;
4952 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4953 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4958 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4960 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4961 uint64_t systime_cycles;
4963 switch (hw->mac.type) {
4967 * Need to read System Time Residue Register to be able
4968 * to read the other two registers.
4970 E1000_READ_REG(hw, E1000_SYSTIMR);
4971 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4972 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4973 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4980 * Need to read System Time Residue Register to be able
4981 * to read the other two registers.
4983 E1000_READ_REG(hw, E1000_SYSTIMR);
4984 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4985 /* Only the 8 LSB are valid. */
4986 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4990 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4991 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4996 return systime_cycles;
5000 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5002 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5003 uint64_t rx_tstamp_cycles;
5005 switch (hw->mac.type) {
5008 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5009 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5010 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5016 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5017 /* Only the 8 LSB are valid. */
5018 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
5022 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5023 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5028 return rx_tstamp_cycles;
5032 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5034 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5035 uint64_t tx_tstamp_cycles;
5037 switch (hw->mac.type) {
5040 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5041 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5042 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5048 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5049 /* Only the 8 LSB are valid. */
5050 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5054 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5055 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5060 return tx_tstamp_cycles;
5064 igb_start_timecounters(struct rte_eth_dev *dev)
5066 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5067 struct e1000_adapter *adapter = dev->data->dev_private;
5068 uint32_t incval = 1;
5070 uint64_t mask = E1000_CYCLECOUNTER_MASK;
5072 switch (hw->mac.type) {
5076 /* 32 LSB bits + 8 MSB bits = 40 bits */
5077 mask = (1ULL << 40) - 1;
5082 * Start incrementing the register
5083 * used to timestamp PTP packets.
5085 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5088 incval = E1000_INCVALUE_82576;
5089 shift = IGB_82576_TSYNC_SHIFT;
5090 E1000_WRITE_REG(hw, E1000_TIMINCA,
5091 E1000_INCPERIOD_82576 | incval);
5098 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5099 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5100 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5102 adapter->systime_tc.cc_mask = mask;
5103 adapter->systime_tc.cc_shift = shift;
5104 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5106 adapter->rx_tstamp_tc.cc_mask = mask;
5107 adapter->rx_tstamp_tc.cc_shift = shift;
5108 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5110 adapter->tx_tstamp_tc.cc_mask = mask;
5111 adapter->tx_tstamp_tc.cc_shift = shift;
5112 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5116 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5118 struct e1000_adapter *adapter = dev->data->dev_private;
5120 adapter->systime_tc.nsec += delta;
5121 adapter->rx_tstamp_tc.nsec += delta;
5122 adapter->tx_tstamp_tc.nsec += delta;
5128 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5131 struct e1000_adapter *adapter = dev->data->dev_private;
5133 ns = rte_timespec_to_ns(ts);
5135 /* Set the timecounters to a new value. */
5136 adapter->systime_tc.nsec = ns;
5137 adapter->rx_tstamp_tc.nsec = ns;
5138 adapter->tx_tstamp_tc.nsec = ns;
5144 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5146 uint64_t ns, systime_cycles;
5147 struct e1000_adapter *adapter = dev->data->dev_private;
5149 systime_cycles = igb_read_systime_cyclecounter(dev);
5150 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5151 *ts = rte_ns_to_timespec(ns);
5157 igb_timesync_enable(struct rte_eth_dev *dev)
5159 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5163 /* Stop the timesync system time. */
5164 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5165 /* Reset the timesync system time value. */
5166 switch (hw->mac.type) {
5172 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5175 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5176 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5179 /* Not supported. */
5183 /* Enable system time for it isn't on by default. */
5184 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5185 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5186 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5188 igb_start_timecounters(dev);
5190 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5191 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5192 (RTE_ETHER_TYPE_1588 |
5193 E1000_ETQF_FILTER_ENABLE |
5196 /* Enable timestamping of received PTP packets. */
5197 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5198 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5199 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5201 /* Enable Timestamping of transmitted PTP packets. */
5202 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5203 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5204 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5210 igb_timesync_disable(struct rte_eth_dev *dev)
5212 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5215 /* Disable timestamping of transmitted PTP packets. */
5216 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5217 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5218 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5220 /* Disable timestamping of received PTP packets. */
5221 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5222 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5223 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5225 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5226 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5228 /* Stop incrementating the System Time registers. */
5229 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5235 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5236 struct timespec *timestamp,
5237 uint32_t flags __rte_unused)
5239 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5240 struct e1000_adapter *adapter = dev->data->dev_private;
5241 uint32_t tsync_rxctl;
5242 uint64_t rx_tstamp_cycles;
5245 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5246 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5249 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5250 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5251 *timestamp = rte_ns_to_timespec(ns);
5257 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5258 struct timespec *timestamp)
5260 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5261 struct e1000_adapter *adapter = dev->data->dev_private;
5262 uint32_t tsync_txctl;
5263 uint64_t tx_tstamp_cycles;
5266 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5267 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5270 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5271 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5272 *timestamp = rte_ns_to_timespec(ns);
5278 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5282 const struct reg_info *reg_group;
5284 while ((reg_group = igb_regs[g_ind++]))
5285 count += igb_reg_group_count(reg_group);
5291 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5295 const struct reg_info *reg_group;
5297 while ((reg_group = igbvf_regs[g_ind++]))
5298 count += igb_reg_group_count(reg_group);
5304 eth_igb_get_regs(struct rte_eth_dev *dev,
5305 struct rte_dev_reg_info *regs)
5307 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5308 uint32_t *data = regs->data;
5311 const struct reg_info *reg_group;
5314 regs->length = eth_igb_get_reg_length(dev);
5315 regs->width = sizeof(uint32_t);
5319 /* Support only full register dump */
5320 if ((regs->length == 0) ||
5321 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5322 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5324 while ((reg_group = igb_regs[g_ind++]))
5325 count += igb_read_regs_group(dev, &data[count],
5334 igbvf_get_regs(struct rte_eth_dev *dev,
5335 struct rte_dev_reg_info *regs)
5337 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5338 uint32_t *data = regs->data;
5341 const struct reg_info *reg_group;
5344 regs->length = igbvf_get_reg_length(dev);
5345 regs->width = sizeof(uint32_t);
5349 /* Support only full register dump */
5350 if ((regs->length == 0) ||
5351 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5352 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5354 while ((reg_group = igbvf_regs[g_ind++]))
5355 count += igb_read_regs_group(dev, &data[count],
5364 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5366 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5368 /* Return unit is byte count */
5369 return hw->nvm.word_size * 2;
5373 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5374 struct rte_dev_eeprom_info *in_eeprom)
5376 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5377 struct e1000_nvm_info *nvm = &hw->nvm;
5378 uint16_t *data = in_eeprom->data;
5381 first = in_eeprom->offset >> 1;
5382 length = in_eeprom->length >> 1;
5383 if ((first >= hw->nvm.word_size) ||
5384 ((first + length) >= hw->nvm.word_size))
5387 in_eeprom->magic = hw->vendor_id |
5388 ((uint32_t)hw->device_id << 16);
5390 if ((nvm->ops.read) == NULL)
5393 return nvm->ops.read(hw, first, length, data);
5397 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5398 struct rte_dev_eeprom_info *in_eeprom)
5400 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5401 struct e1000_nvm_info *nvm = &hw->nvm;
5402 uint16_t *data = in_eeprom->data;
5405 first = in_eeprom->offset >> 1;
5406 length = in_eeprom->length >> 1;
5407 if ((first >= hw->nvm.word_size) ||
5408 ((first + length) >= hw->nvm.word_size))
5411 in_eeprom->magic = (uint32_t)hw->vendor_id |
5412 ((uint32_t)hw->device_id << 16);
5414 if ((nvm->ops.write) == NULL)
5416 return nvm->ops.write(hw, first, length, data);
5420 eth_igb_get_module_info(struct rte_eth_dev *dev,
5421 struct rte_eth_dev_module_info *modinfo)
5423 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5425 uint32_t status = 0;
5426 uint16_t sff8472_rev, addr_mode;
5427 bool page_swap = false;
5429 if (hw->phy.media_type == e1000_media_type_copper ||
5430 hw->phy.media_type == e1000_media_type_unknown)
5433 /* Check whether we support SFF-8472 or not */
5434 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5438 /* addressing mode is not supported */
5439 status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5443 /* addressing mode is not supported */
5444 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5446 "Address change required to access page 0xA2, "
5447 "but not supported. Please report the module "
5448 "type to the driver maintainers.\n");
5452 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5453 /* We have an SFP, but it does not support SFF-8472 */
5454 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5455 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5457 /* We have an SFP which supports a revision of SFF-8472 */
5458 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5459 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5466 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5467 struct rte_dev_eeprom_info *info)
5469 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5471 uint32_t status = 0;
5472 uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5473 u16 first_word, last_word;
5476 if (info->length == 0)
5479 first_word = info->offset >> 1;
5480 last_word = (info->offset + info->length - 1) >> 1;
5482 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5483 for (i = 0; i < last_word - first_word + 1; i++) {
5484 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5487 /* Error occurred while reading module */
5491 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5494 memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5500 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5502 struct e1000_hw *hw =
5503 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5504 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5505 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5506 uint32_t vec = E1000_MISC_VEC_ID;
5508 if (rte_intr_allow_others(intr_handle))
5509 vec = E1000_RX_VEC_START;
5511 uint32_t mask = 1 << (queue_id + vec);
5513 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5514 E1000_WRITE_FLUSH(hw);
5520 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5522 struct e1000_hw *hw =
5523 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5524 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5525 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5526 uint32_t vec = E1000_MISC_VEC_ID;
5528 if (rte_intr_allow_others(intr_handle))
5529 vec = E1000_RX_VEC_START;
5531 uint32_t mask = 1 << (queue_id + vec);
5534 regval = E1000_READ_REG(hw, E1000_EIMS);
5535 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5536 E1000_WRITE_FLUSH(hw);
5538 rte_intr_ack(intr_handle);
5544 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5545 uint8_t index, uint8_t offset)
5547 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5550 val &= ~((uint32_t)0xFF << offset);
5552 /* write vector and valid bit */
5553 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5555 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5559 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5560 uint8_t queue, uint8_t msix_vector)
5564 if (hw->mac.type == e1000_82575) {
5566 tmp = E1000_EICR_RX_QUEUE0 << queue;
5567 else if (direction == 1)
5568 tmp = E1000_EICR_TX_QUEUE0 << queue;
5569 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5570 } else if (hw->mac.type == e1000_82576) {
5571 if ((direction == 0) || (direction == 1))
5572 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5573 ((queue & 0x8) << 1) +
5575 } else if ((hw->mac.type == e1000_82580) ||
5576 (hw->mac.type == e1000_i350) ||
5577 (hw->mac.type == e1000_i354) ||
5578 (hw->mac.type == e1000_i210) ||
5579 (hw->mac.type == e1000_i211)) {
5580 if ((direction == 0) || (direction == 1))
5581 eth_igb_write_ivar(hw, msix_vector,
5583 ((queue & 0x1) << 4) +
5588 /* Sets up the hardware to generate MSI-X interrupts properly
5590 * board private structure
5593 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5596 uint32_t tmpval, regval, intr_mask;
5597 struct e1000_hw *hw =
5598 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5599 uint32_t vec = E1000_MISC_VEC_ID;
5600 uint32_t base = E1000_MISC_VEC_ID;
5601 uint32_t misc_shift = 0;
5602 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5603 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5605 /* won't configure msix register if no mapping is done
5606 * between intr vector and event fd
5608 if (!rte_intr_dp_is_en(intr_handle))
5611 if (rte_intr_allow_others(intr_handle)) {
5612 vec = base = E1000_RX_VEC_START;
5616 /* set interrupt vector for other causes */
5617 if (hw->mac.type == e1000_82575) {
5618 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5619 /* enable MSI-X PBA support */
5620 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5622 /* Auto-Mask interrupts upon ICR read */
5623 tmpval |= E1000_CTRL_EXT_EIAME;
5624 tmpval |= E1000_CTRL_EXT_IRCA;
5626 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5628 /* enable msix_other interrupt */
5629 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5630 regval = E1000_READ_REG(hw, E1000_EIAC);
5631 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5632 regval = E1000_READ_REG(hw, E1000_EIAM);
5633 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5634 } else if ((hw->mac.type == e1000_82576) ||
5635 (hw->mac.type == e1000_82580) ||
5636 (hw->mac.type == e1000_i350) ||
5637 (hw->mac.type == e1000_i354) ||
5638 (hw->mac.type == e1000_i210) ||
5639 (hw->mac.type == e1000_i211)) {
5640 /* turn on MSI-X capability first */
5641 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5642 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5644 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5647 if (dev->data->dev_conf.intr_conf.lsc != 0)
5648 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5650 regval = E1000_READ_REG(hw, E1000_EIAC);
5651 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5653 /* enable msix_other interrupt */
5654 regval = E1000_READ_REG(hw, E1000_EIMS);
5655 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5656 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5657 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5660 /* use EIAM to auto-mask when MSI-X interrupt
5661 * is asserted, this saves a register write for every interrupt
5663 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5666 if (dev->data->dev_conf.intr_conf.lsc != 0)
5667 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5669 regval = E1000_READ_REG(hw, E1000_EIAM);
5670 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5672 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5673 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5674 intr_handle->intr_vec[queue_id] = vec;
5675 if (vec < base + intr_handle->nb_efd - 1)
5679 E1000_WRITE_FLUSH(hw);
5682 /* restore n-tuple filter */
5684 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5686 struct e1000_filter_info *filter_info =
5687 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5688 struct e1000_5tuple_filter *p_5tuple;
5689 struct e1000_2tuple_filter *p_2tuple;
5691 TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5692 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5695 TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5696 igb_inject_2uple_filter(dev, p_2tuple);
5700 /* restore SYN filter */
5702 igb_syn_filter_restore(struct rte_eth_dev *dev)
5704 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5705 struct e1000_filter_info *filter_info =
5706 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5709 synqf = filter_info->syn_info;
5711 if (synqf & E1000_SYN_FILTER_ENABLE) {
5712 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5713 E1000_WRITE_FLUSH(hw);
5717 /* restore ethernet type filter */
5719 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5721 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5722 struct e1000_filter_info *filter_info =
5723 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5726 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5727 if (filter_info->ethertype_mask & (1 << i)) {
5728 E1000_WRITE_REG(hw, E1000_ETQF(i),
5729 filter_info->ethertype_filters[i].etqf);
5730 E1000_WRITE_FLUSH(hw);
5735 /* restore flex byte filter */
5737 igb_flex_filter_restore(struct rte_eth_dev *dev)
5739 struct e1000_filter_info *filter_info =
5740 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5741 struct e1000_flex_filter *flex_filter;
5743 TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5744 igb_inject_flex_filter(dev, flex_filter);
5748 /* restore rss filter */
5750 igb_rss_filter_restore(struct rte_eth_dev *dev)
5752 struct e1000_filter_info *filter_info =
5753 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5755 if (filter_info->rss_info.conf.queue_num)
5756 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5759 /* restore all types filter */
5761 igb_filter_restore(struct rte_eth_dev *dev)
5763 igb_ntuple_filter_restore(dev);
5764 igb_ethertype_filter_restore(dev);
5765 igb_syn_filter_restore(dev);
5766 igb_flex_filter_restore(dev);
5767 igb_rss_filter_restore(dev);
5772 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5773 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5774 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5775 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5776 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5777 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5779 /* see e1000_logs.c */
5780 RTE_INIT(e1000_init_log)
5782 e1000_igb_init_log();