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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
61 * Default values for port configuration
63 #define IGB_DEFAULT_RX_FREE_THRESH 32
65 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
66 #define IGB_DEFAULT_RX_HTHRESH 8
67 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
69 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
70 #define IGB_DEFAULT_TX_HTHRESH 1
71 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
73 #define IGB_HKEY_MAX_INDEX 10
75 /* Bit shift and mask */
76 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
77 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
78 #define IGB_8_BIT_WIDTH CHAR_BIT
79 #define IGB_8_BIT_MASK UINT8_MAX
81 /* Additional timesync values. */
82 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
83 #define E1000_ETQF_FILTER_1588 3
84 #define IGB_82576_TSYNC_SHIFT 16
85 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
86 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
89 #define E1000_VTIVAR_MISC 0x01740
90 #define E1000_VTIVAR_MISC_MASK 0xFF
91 #define E1000_VTIVAR_VALID 0x80
92 #define E1000_VTIVAR_MISC_MAILBOX 0
93 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
95 /* External VLAN Enable bit mask */
96 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
98 /* External VLAN Ether Type bit mask and shift */
99 #define E1000_VET_VET_EXT 0xFFFF0000
100 #define E1000_VET_VET_EXT_SHIFT 16
102 static int eth_igb_configure(struct rte_eth_dev *dev);
103 static int eth_igb_start(struct rte_eth_dev *dev);
104 static void eth_igb_stop(struct rte_eth_dev *dev);
105 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
106 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
107 static void eth_igb_close(struct rte_eth_dev *dev);
108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
112 static int eth_igb_link_update(struct rte_eth_dev *dev,
113 int wait_to_complete);
114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
115 struct rte_eth_stats *rte_stats);
116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
117 struct rte_eth_xstat *xstats, unsigned n);
118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
119 struct rte_eth_xstat_name *xstats_names,
121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
123 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
124 char *fw_version, size_t fw_size);
125 static void eth_igb_infos_get(struct rte_eth_dev *dev,
126 struct rte_eth_dev_info *dev_info);
127 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
128 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
129 struct rte_eth_dev_info *dev_info);
130 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
131 struct rte_eth_fc_conf *fc_conf);
132 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
133 struct rte_eth_fc_conf *fc_conf);
134 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
135 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
136 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
137 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
138 struct rte_intr_handle *handle);
139 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
141 static int igb_hardware_init(struct e1000_hw *hw);
142 static void igb_hw_control_acquire(struct e1000_hw *hw);
143 static void igb_hw_control_release(struct e1000_hw *hw);
144 static void igb_init_manageability(struct e1000_hw *hw);
145 static void igb_release_manageability(struct e1000_hw *hw);
147 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
149 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
150 uint16_t vlan_id, int on);
151 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
152 enum rte_vlan_type vlan_type,
154 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
156 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
157 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
158 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
159 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
160 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
161 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
163 static int eth_igb_led_on(struct rte_eth_dev *dev);
164 static int eth_igb_led_off(struct rte_eth_dev *dev);
166 static void igb_intr_disable(struct e1000_hw *hw);
167 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
168 static void eth_igb_rar_set(struct rte_eth_dev *dev,
169 struct ether_addr *mac_addr,
170 uint32_t index, uint32_t pool);
171 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
172 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
173 struct ether_addr *addr);
175 static void igbvf_intr_disable(struct e1000_hw *hw);
176 static int igbvf_dev_configure(struct rte_eth_dev *dev);
177 static int igbvf_dev_start(struct rte_eth_dev *dev);
178 static void igbvf_dev_stop(struct rte_eth_dev *dev);
179 static void igbvf_dev_close(struct rte_eth_dev *dev);
180 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
181 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
182 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
183 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
184 static int eth_igbvf_link_update(struct e1000_hw *hw);
185 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
186 struct rte_eth_stats *rte_stats);
187 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
188 struct rte_eth_xstat *xstats, unsigned n);
189 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
190 struct rte_eth_xstat_name *xstats_names,
192 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
193 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
194 uint16_t vlan_id, int on);
195 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
196 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
197 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
198 struct ether_addr *addr);
199 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
200 static int igbvf_get_regs(struct rte_eth_dev *dev,
201 struct rte_dev_reg_info *regs);
203 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
204 struct rte_eth_rss_reta_entry64 *reta_conf,
206 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
207 struct rte_eth_rss_reta_entry64 *reta_conf,
210 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
211 struct rte_eth_syn_filter *filter,
213 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
214 struct rte_eth_syn_filter *filter);
215 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
216 enum rte_filter_op filter_op,
218 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
219 struct rte_eth_ntuple_filter *ntuple_filter);
220 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
221 struct rte_eth_ntuple_filter *ntuple_filter);
222 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
223 struct rte_eth_flex_filter *filter,
225 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
226 struct rte_eth_flex_filter *filter);
227 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
228 enum rte_filter_op filter_op,
230 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
231 struct rte_eth_ntuple_filter *ntuple_filter);
232 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
233 struct rte_eth_ntuple_filter *ntuple_filter);
234 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
235 struct rte_eth_ntuple_filter *filter,
237 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
238 struct rte_eth_ntuple_filter *filter);
239 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
240 enum rte_filter_op filter_op,
242 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
243 struct rte_eth_ethertype_filter *filter,
245 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
246 enum rte_filter_op filter_op,
248 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
249 struct rte_eth_ethertype_filter *filter);
250 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
251 enum rte_filter_type filter_type,
252 enum rte_filter_op filter_op,
254 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
255 static int eth_igb_get_regs(struct rte_eth_dev *dev,
256 struct rte_dev_reg_info *regs);
257 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
258 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
259 struct rte_dev_eeprom_info *eeprom);
260 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
261 struct rte_dev_eeprom_info *eeprom);
262 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
263 struct ether_addr *mc_addr_set,
264 uint32_t nb_mc_addr);
265 static int igb_timesync_enable(struct rte_eth_dev *dev);
266 static int igb_timesync_disable(struct rte_eth_dev *dev);
267 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
268 struct timespec *timestamp,
270 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
271 struct timespec *timestamp);
272 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
273 static int igb_timesync_read_time(struct rte_eth_dev *dev,
274 struct timespec *timestamp);
275 static int igb_timesync_write_time(struct rte_eth_dev *dev,
276 const struct timespec *timestamp);
277 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
279 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
281 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
282 uint8_t queue, uint8_t msix_vector);
283 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
284 uint8_t index, uint8_t offset);
285 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
286 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
288 static void igbvf_mbx_process(struct rte_eth_dev *dev);
291 * Define VF Stats MACRO for Non "cleared on read" register
293 #define UPDATE_VF_STAT(reg, last, cur) \
295 u32 latest = E1000_READ_REG(hw, reg); \
296 cur += (latest - last) & UINT_MAX; \
300 #define IGB_FC_PAUSE_TIME 0x0680
301 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
302 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
304 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
306 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
309 * The set of PCI devices this driver supports
311 static const struct rte_pci_id pci_id_igb_map[] = {
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
317 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
321 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
325 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
326 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
328 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
329 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
330 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
335 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
336 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
337 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
338 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
339 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
340 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
341 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
342 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
343 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
344 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
345 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
346 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
347 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
348 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
349 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
350 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
351 { .vendor_id = 0, /* sentinel */ },
355 * The set of PCI devices this driver supports (for 82576&I350 VF)
357 static const struct rte_pci_id pci_id_igbvf_map[] = {
358 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
359 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
360 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
361 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
362 { .vendor_id = 0, /* sentinel */ },
365 static const struct rte_eth_desc_lim rx_desc_lim = {
366 .nb_max = E1000_MAX_RING_DESC,
367 .nb_min = E1000_MIN_RING_DESC,
368 .nb_align = IGB_RXD_ALIGN,
371 static const struct rte_eth_desc_lim tx_desc_lim = {
372 .nb_max = E1000_MAX_RING_DESC,
373 .nb_min = E1000_MIN_RING_DESC,
374 .nb_align = IGB_RXD_ALIGN,
375 .nb_seg_max = IGB_TX_MAX_SEG,
376 .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
379 static const struct eth_dev_ops eth_igb_ops = {
380 .dev_configure = eth_igb_configure,
381 .dev_start = eth_igb_start,
382 .dev_stop = eth_igb_stop,
383 .dev_set_link_up = eth_igb_dev_set_link_up,
384 .dev_set_link_down = eth_igb_dev_set_link_down,
385 .dev_close = eth_igb_close,
386 .promiscuous_enable = eth_igb_promiscuous_enable,
387 .promiscuous_disable = eth_igb_promiscuous_disable,
388 .allmulticast_enable = eth_igb_allmulticast_enable,
389 .allmulticast_disable = eth_igb_allmulticast_disable,
390 .link_update = eth_igb_link_update,
391 .stats_get = eth_igb_stats_get,
392 .xstats_get = eth_igb_xstats_get,
393 .xstats_get_names = eth_igb_xstats_get_names,
394 .stats_reset = eth_igb_stats_reset,
395 .xstats_reset = eth_igb_xstats_reset,
396 .fw_version_get = eth_igb_fw_version_get,
397 .dev_infos_get = eth_igb_infos_get,
398 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
399 .mtu_set = eth_igb_mtu_set,
400 .vlan_filter_set = eth_igb_vlan_filter_set,
401 .vlan_tpid_set = eth_igb_vlan_tpid_set,
402 .vlan_offload_set = eth_igb_vlan_offload_set,
403 .rx_queue_setup = eth_igb_rx_queue_setup,
404 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
405 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
406 .rx_queue_release = eth_igb_rx_queue_release,
407 .rx_queue_count = eth_igb_rx_queue_count,
408 .rx_descriptor_done = eth_igb_rx_descriptor_done,
409 .tx_queue_setup = eth_igb_tx_queue_setup,
410 .tx_queue_release = eth_igb_tx_queue_release,
411 .dev_led_on = eth_igb_led_on,
412 .dev_led_off = eth_igb_led_off,
413 .flow_ctrl_get = eth_igb_flow_ctrl_get,
414 .flow_ctrl_set = eth_igb_flow_ctrl_set,
415 .mac_addr_add = eth_igb_rar_set,
416 .mac_addr_remove = eth_igb_rar_clear,
417 .mac_addr_set = eth_igb_default_mac_addr_set,
418 .reta_update = eth_igb_rss_reta_update,
419 .reta_query = eth_igb_rss_reta_query,
420 .rss_hash_update = eth_igb_rss_hash_update,
421 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
422 .filter_ctrl = eth_igb_filter_ctrl,
423 .set_mc_addr_list = eth_igb_set_mc_addr_list,
424 .rxq_info_get = igb_rxq_info_get,
425 .txq_info_get = igb_txq_info_get,
426 .timesync_enable = igb_timesync_enable,
427 .timesync_disable = igb_timesync_disable,
428 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
429 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
430 .get_reg = eth_igb_get_regs,
431 .get_eeprom_length = eth_igb_get_eeprom_length,
432 .get_eeprom = eth_igb_get_eeprom,
433 .set_eeprom = eth_igb_set_eeprom,
434 .timesync_adjust_time = igb_timesync_adjust_time,
435 .timesync_read_time = igb_timesync_read_time,
436 .timesync_write_time = igb_timesync_write_time,
440 * dev_ops for virtual function, bare necessities for basic vf
441 * operation have been implemented
443 static const struct eth_dev_ops igbvf_eth_dev_ops = {
444 .dev_configure = igbvf_dev_configure,
445 .dev_start = igbvf_dev_start,
446 .dev_stop = igbvf_dev_stop,
447 .dev_close = igbvf_dev_close,
448 .promiscuous_enable = igbvf_promiscuous_enable,
449 .promiscuous_disable = igbvf_promiscuous_disable,
450 .allmulticast_enable = igbvf_allmulticast_enable,
451 .allmulticast_disable = igbvf_allmulticast_disable,
452 .link_update = eth_igb_link_update,
453 .stats_get = eth_igbvf_stats_get,
454 .xstats_get = eth_igbvf_xstats_get,
455 .xstats_get_names = eth_igbvf_xstats_get_names,
456 .stats_reset = eth_igbvf_stats_reset,
457 .xstats_reset = eth_igbvf_stats_reset,
458 .vlan_filter_set = igbvf_vlan_filter_set,
459 .dev_infos_get = eth_igbvf_infos_get,
460 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
461 .rx_queue_setup = eth_igb_rx_queue_setup,
462 .rx_queue_release = eth_igb_rx_queue_release,
463 .tx_queue_setup = eth_igb_tx_queue_setup,
464 .tx_queue_release = eth_igb_tx_queue_release,
465 .set_mc_addr_list = eth_igb_set_mc_addr_list,
466 .rxq_info_get = igb_rxq_info_get,
467 .txq_info_get = igb_txq_info_get,
468 .mac_addr_set = igbvf_default_mac_addr_set,
469 .get_reg = igbvf_get_regs,
472 /* store statistics names and its offset in stats structure */
473 struct rte_igb_xstats_name_off {
474 char name[RTE_ETH_XSTATS_NAME_SIZE];
478 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
479 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
480 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
481 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
482 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
483 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
484 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
485 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
487 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
488 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
489 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
490 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
491 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
492 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
493 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
494 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
495 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
496 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
497 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
499 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
500 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
501 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
502 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
503 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
505 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
507 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
508 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
509 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
510 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
511 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
512 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
513 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
514 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
515 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
516 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
517 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
518 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
519 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
520 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
521 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
522 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
523 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
524 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
526 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
528 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
529 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
530 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
531 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
532 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
533 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
534 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
536 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
539 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
540 sizeof(rte_igb_stats_strings[0]))
542 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
543 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
544 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
545 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
546 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
547 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
550 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
551 sizeof(rte_igbvf_stats_strings[0]))
554 * Atomically reads the link status information from global
555 * structure rte_eth_dev.
558 * - Pointer to the structure rte_eth_dev to read from.
559 * - Pointer to the buffer to be saved with the link status.
562 * - On success, zero.
563 * - On failure, negative value.
566 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
567 struct rte_eth_link *link)
569 struct rte_eth_link *dst = link;
570 struct rte_eth_link *src = &(dev->data->dev_link);
572 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
573 *(uint64_t *)src) == 0)
580 * Atomically writes the link status information into global
581 * structure rte_eth_dev.
584 * - Pointer to the structure rte_eth_dev to read from.
585 * - Pointer to the buffer to be saved with the link status.
588 * - On success, zero.
589 * - On failure, negative value.
592 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
593 struct rte_eth_link *link)
595 struct rte_eth_link *dst = &(dev->data->dev_link);
596 struct rte_eth_link *src = link;
598 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
599 *(uint64_t *)src) == 0)
606 igb_intr_enable(struct rte_eth_dev *dev)
608 struct e1000_interrupt *intr =
609 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
610 struct e1000_hw *hw =
611 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
613 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
614 E1000_WRITE_FLUSH(hw);
618 igb_intr_disable(struct e1000_hw *hw)
620 E1000_WRITE_REG(hw, E1000_IMC, ~0);
621 E1000_WRITE_FLUSH(hw);
625 igbvf_intr_enable(struct rte_eth_dev *dev)
627 struct e1000_hw *hw =
628 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
630 /* only for mailbox */
631 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
632 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
633 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
634 E1000_WRITE_FLUSH(hw);
637 /* only for mailbox now. If RX/TX needed, should extend this function. */
639 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
644 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
645 tmp |= E1000_VTIVAR_VALID;
646 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
650 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
652 struct e1000_hw *hw =
653 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
655 /* Configure VF other cause ivar */
656 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
659 static inline int32_t
660 igb_pf_reset_hw(struct e1000_hw *hw)
665 status = e1000_reset_hw(hw);
667 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
668 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
669 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
670 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
671 E1000_WRITE_FLUSH(hw);
677 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
679 struct e1000_hw *hw =
680 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
683 hw->vendor_id = pci_dev->id.vendor_id;
684 hw->device_id = pci_dev->id.device_id;
685 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
686 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
688 e1000_set_mac_type(hw);
690 /* need to check if it is a vf device below */
694 igb_reset_swfw_lock(struct e1000_hw *hw)
699 * Do mac ops initialization manually here, since we will need
700 * some function pointers set by this call.
702 ret_val = e1000_init_mac_params(hw);
707 * SMBI lock should not fail in this early stage. If this is the case,
708 * it is due to an improper exit of the application.
709 * So force the release of the faulty lock.
711 if (e1000_get_hw_semaphore_generic(hw) < 0) {
712 PMD_DRV_LOG(DEBUG, "SMBI lock released");
714 e1000_put_hw_semaphore_generic(hw);
716 if (hw->mac.ops.acquire_swfw_sync != NULL) {
720 * Phy lock should not fail in this early stage. If this is the case,
721 * it is due to an improper exit of the application.
722 * So force the release of the faulty lock.
724 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
725 if (hw->bus.func > E1000_FUNC_1)
727 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
728 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
731 hw->mac.ops.release_swfw_sync(hw, mask);
734 * This one is more tricky since it is common to all ports; but
735 * swfw_sync retries last long enough (1s) to be almost sure that if
736 * lock can not be taken it is due to an improper lock of the
739 mask = E1000_SWFW_EEP_SM;
740 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
741 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
743 hw->mac.ops.release_swfw_sync(hw, mask);
746 return E1000_SUCCESS;
750 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
753 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
754 struct e1000_hw *hw =
755 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
756 struct e1000_vfta * shadow_vfta =
757 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
758 struct e1000_filter_info *filter_info =
759 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
760 struct e1000_adapter *adapter =
761 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
765 eth_dev->dev_ops = ð_igb_ops;
766 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
767 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
768 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
770 /* for secondary processes, we don't initialise any further as primary
771 * has already done this work. Only check we don't need a different
773 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
774 if (eth_dev->data->scattered_rx)
775 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
779 rte_eth_copy_pci_info(eth_dev, pci_dev);
780 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
782 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
784 igb_identify_hardware(eth_dev, pci_dev);
785 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
790 e1000_get_bus_info(hw);
792 /* Reset any pending lock */
793 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
798 /* Finish initialization */
799 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
805 hw->phy.autoneg_wait_to_complete = 0;
806 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
809 if (hw->phy.media_type == e1000_media_type_copper) {
810 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
811 hw->phy.disable_polarity_correction = 0;
812 hw->phy.ms_type = e1000_ms_hw_default;
816 * Start from a known state, this is important in reading the nvm
821 /* Make sure we have a good EEPROM before we read from it */
822 if (e1000_validate_nvm_checksum(hw) < 0) {
824 * Some PCI-E parts fail the first check due to
825 * the link being in sleep state, call it again,
826 * if it fails a second time its a real issue.
828 if (e1000_validate_nvm_checksum(hw) < 0) {
829 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
835 /* Read the permanent MAC address out of the EEPROM */
836 if (e1000_read_mac_addr(hw) != 0) {
837 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
842 /* Allocate memory for storing MAC addresses */
843 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
844 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
845 if (eth_dev->data->mac_addrs == NULL) {
846 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
847 "store MAC addresses",
848 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
853 /* Copy the permanent MAC address */
854 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
856 /* initialize the vfta */
857 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
859 /* Now initialize the hardware */
860 if (igb_hardware_init(hw) != 0) {
861 PMD_INIT_LOG(ERR, "Hardware initialization failed");
862 rte_free(eth_dev->data->mac_addrs);
863 eth_dev->data->mac_addrs = NULL;
867 hw->mac.get_link_status = 1;
868 adapter->stopped = 0;
870 /* Indicate SOL/IDER usage */
871 if (e1000_check_reset_block(hw) < 0) {
872 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
876 /* initialize PF if max_vfs not zero */
877 igb_pf_host_init(eth_dev);
879 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
880 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
881 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
882 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
883 E1000_WRITE_FLUSH(hw);
885 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
886 eth_dev->data->port_id, pci_dev->id.vendor_id,
887 pci_dev->id.device_id);
889 rte_intr_callback_register(&pci_dev->intr_handle,
890 eth_igb_interrupt_handler,
893 /* enable uio/vfio intr/eventfd mapping */
894 rte_intr_enable(&pci_dev->intr_handle);
896 /* enable support intr */
897 igb_intr_enable(eth_dev);
899 TAILQ_INIT(&filter_info->flex_list);
900 filter_info->flex_mask = 0;
901 TAILQ_INIT(&filter_info->twotuple_list);
902 filter_info->twotuple_mask = 0;
903 TAILQ_INIT(&filter_info->fivetuple_list);
904 filter_info->fivetuple_mask = 0;
909 igb_hw_control_release(hw);
915 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
917 struct rte_pci_device *pci_dev;
918 struct rte_intr_handle *intr_handle;
920 struct e1000_adapter *adapter =
921 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
923 PMD_INIT_FUNC_TRACE();
925 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
928 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
929 pci_dev = E1000_DEV_TO_PCI(eth_dev);
930 intr_handle = &pci_dev->intr_handle;
932 if (adapter->stopped == 0)
933 eth_igb_close(eth_dev);
935 eth_dev->dev_ops = NULL;
936 eth_dev->rx_pkt_burst = NULL;
937 eth_dev->tx_pkt_burst = NULL;
939 /* Reset any pending lock */
940 igb_reset_swfw_lock(hw);
942 rte_free(eth_dev->data->mac_addrs);
943 eth_dev->data->mac_addrs = NULL;
945 /* uninitialize PF if max_vfs not zero */
946 igb_pf_host_uninit(eth_dev);
948 /* disable uio intr before callback unregister */
949 rte_intr_disable(intr_handle);
950 rte_intr_callback_unregister(intr_handle,
951 eth_igb_interrupt_handler, eth_dev);
957 * Virtual Function device init
960 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
962 struct rte_pci_device *pci_dev;
963 struct rte_intr_handle *intr_handle;
964 struct e1000_adapter *adapter =
965 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
966 struct e1000_hw *hw =
967 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
969 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
971 PMD_INIT_FUNC_TRACE();
973 eth_dev->dev_ops = &igbvf_eth_dev_ops;
974 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
975 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
976 eth_dev->tx_pkt_prepare = ð_igb_prep_pkts;
978 /* for secondary processes, we don't initialise any further as primary
979 * has already done this work. Only check we don't need a different
981 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
982 if (eth_dev->data->scattered_rx)
983 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
987 pci_dev = E1000_DEV_TO_PCI(eth_dev);
988 rte_eth_copy_pci_info(eth_dev, pci_dev);
989 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
991 hw->device_id = pci_dev->id.device_id;
992 hw->vendor_id = pci_dev->id.vendor_id;
993 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
994 adapter->stopped = 0;
996 /* Initialize the shared code (base driver) */
997 diag = e1000_setup_init_funcs(hw, TRUE);
999 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1004 /* init_mailbox_params */
1005 hw->mbx.ops.init_params(hw);
1007 /* Disable the interrupts for VF */
1008 igbvf_intr_disable(hw);
1010 diag = hw->mac.ops.reset_hw(hw);
1012 /* Allocate memory for storing MAC addresses */
1013 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1014 hw->mac.rar_entry_count, 0);
1015 if (eth_dev->data->mac_addrs == NULL) {
1017 "Failed to allocate %d bytes needed to store MAC "
1019 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1023 /* Generate a random MAC address, if none was assigned by PF. */
1024 if (is_zero_ether_addr(perm_addr)) {
1025 eth_random_addr(perm_addr->addr_bytes);
1026 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1028 rte_free(eth_dev->data->mac_addrs);
1029 eth_dev->data->mac_addrs = NULL;
1032 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1033 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1034 "%02x:%02x:%02x:%02x:%02x:%02x",
1035 perm_addr->addr_bytes[0],
1036 perm_addr->addr_bytes[1],
1037 perm_addr->addr_bytes[2],
1038 perm_addr->addr_bytes[3],
1039 perm_addr->addr_bytes[4],
1040 perm_addr->addr_bytes[5]);
1043 /* Copy the permanent MAC address */
1044 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1045 ð_dev->data->mac_addrs[0]);
1047 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1049 eth_dev->data->port_id, pci_dev->id.vendor_id,
1050 pci_dev->id.device_id, "igb_mac_82576_vf");
1052 intr_handle = &pci_dev->intr_handle;
1053 rte_intr_callback_register(intr_handle,
1054 eth_igbvf_interrupt_handler, eth_dev);
1060 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1062 struct e1000_adapter *adapter =
1063 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1064 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
1066 PMD_INIT_FUNC_TRACE();
1068 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1071 if (adapter->stopped == 0)
1072 igbvf_dev_close(eth_dev);
1074 eth_dev->dev_ops = NULL;
1075 eth_dev->rx_pkt_burst = NULL;
1076 eth_dev->tx_pkt_burst = NULL;
1078 rte_free(eth_dev->data->mac_addrs);
1079 eth_dev->data->mac_addrs = NULL;
1081 /* disable uio intr before callback unregister */
1082 rte_intr_disable(&pci_dev->intr_handle);
1083 rte_intr_callback_unregister(&pci_dev->intr_handle,
1084 eth_igbvf_interrupt_handler,
1090 static struct eth_driver rte_igb_pmd = {
1092 .id_table = pci_id_igb_map,
1093 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1094 .probe = rte_eth_dev_pci_probe,
1095 .remove = rte_eth_dev_pci_remove,
1097 .eth_dev_init = eth_igb_dev_init,
1098 .eth_dev_uninit = eth_igb_dev_uninit,
1099 .dev_private_size = sizeof(struct e1000_adapter),
1103 * virtual function driver struct
1105 static struct eth_driver rte_igbvf_pmd = {
1107 .id_table = pci_id_igbvf_map,
1108 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1109 .probe = rte_eth_dev_pci_probe,
1110 .remove = rte_eth_dev_pci_remove,
1112 .eth_dev_init = eth_igbvf_dev_init,
1113 .eth_dev_uninit = eth_igbvf_dev_uninit,
1114 .dev_private_size = sizeof(struct e1000_adapter),
1118 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1120 struct e1000_hw *hw =
1121 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1122 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1123 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1124 rctl |= E1000_RCTL_VFE;
1125 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1129 igb_check_mq_mode(struct rte_eth_dev *dev)
1131 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1132 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1133 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1134 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1136 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1137 tx_mq_mode == ETH_MQ_TX_DCB ||
1138 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1139 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1142 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1143 /* Check multi-queue mode.
1144 * To no break software we accept ETH_MQ_RX_NONE as this might
1145 * be used to turn off VLAN filter.
1148 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1149 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1150 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1151 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1153 /* Only support one queue on VFs.
1154 * RSS together with SRIOV is not supported.
1156 PMD_INIT_LOG(ERR, "SRIOV is active,"
1157 " wrong mq_mode rx %d.",
1161 /* TX mode is not used here, so mode might be ignored.*/
1162 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1163 /* SRIOV only works in VMDq enable mode */
1164 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1165 " TX mode %d is not supported. "
1166 " Driver will behave as %d mode.",
1167 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1170 /* check valid queue number */
1171 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1172 PMD_INIT_LOG(ERR, "SRIOV is active,"
1173 " only support one queue on VFs.");
1177 /* To no break software that set invalid mode, only display
1178 * warning if invalid mode is used.
1180 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1181 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1182 rx_mq_mode != ETH_MQ_RX_RSS) {
1183 /* RSS together with VMDq not supported*/
1184 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1189 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1190 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1191 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1192 " Due to txmode is meaningless in this"
1193 " driver, just ignore.",
1201 eth_igb_configure(struct rte_eth_dev *dev)
1203 struct e1000_interrupt *intr =
1204 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1207 PMD_INIT_FUNC_TRACE();
1209 /* multipe queue mode checking */
1210 ret = igb_check_mq_mode(dev);
1212 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1217 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1218 PMD_INIT_FUNC_TRACE();
1224 eth_igb_start(struct rte_eth_dev *dev)
1226 struct e1000_hw *hw =
1227 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1228 struct e1000_adapter *adapter =
1229 E1000_DEV_PRIVATE(dev->data->dev_private);
1230 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1231 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1233 uint32_t intr_vector = 0;
1239 PMD_INIT_FUNC_TRACE();
1241 /* disable uio/vfio intr/eventfd mapping */
1242 rte_intr_disable(intr_handle);
1244 /* Power up the phy. Needed to make the link go Up */
1245 eth_igb_dev_set_link_up(dev);
1248 * Packet Buffer Allocation (PBA)
1249 * Writing PBA sets the receive portion of the buffer
1250 * the remainder is used for the transmit buffer.
1252 if (hw->mac.type == e1000_82575) {
1255 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1256 E1000_WRITE_REG(hw, E1000_PBA, pba);
1259 /* Put the address into the Receive Address Array */
1260 e1000_rar_set(hw, hw->mac.addr, 0);
1262 /* Initialize the hardware */
1263 if (igb_hardware_init(hw)) {
1264 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1267 adapter->stopped = 0;
1269 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1271 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1272 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1273 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1274 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1275 E1000_WRITE_FLUSH(hw);
1277 /* configure PF module if SRIOV enabled */
1278 igb_pf_host_configure(dev);
1280 /* check and configure queue intr-vector mapping */
1281 if ((rte_intr_cap_multiple(intr_handle) ||
1282 !RTE_ETH_DEV_SRIOV(dev).active) &&
1283 dev->data->dev_conf.intr_conf.rxq != 0) {
1284 intr_vector = dev->data->nb_rx_queues;
1285 if (rte_intr_efd_enable(intr_handle, intr_vector))
1289 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1290 intr_handle->intr_vec =
1291 rte_zmalloc("intr_vec",
1292 dev->data->nb_rx_queues * sizeof(int), 0);
1293 if (intr_handle->intr_vec == NULL) {
1294 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1295 " intr_vec\n", dev->data->nb_rx_queues);
1300 /* confiugre msix for rx interrupt */
1301 eth_igb_configure_msix_intr(dev);
1303 /* Configure for OS presence */
1304 igb_init_manageability(hw);
1306 eth_igb_tx_init(dev);
1308 /* This can fail when allocating mbufs for descriptor rings */
1309 ret = eth_igb_rx_init(dev);
1311 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1312 igb_dev_clear_queues(dev);
1316 e1000_clear_hw_cntrs_base_generic(hw);
1319 * VLAN Offload Settings
1321 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1322 ETH_VLAN_EXTEND_MASK;
1323 eth_igb_vlan_offload_set(dev, mask);
1325 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1326 /* Enable VLAN filter since VMDq always use VLAN filter */
1327 igb_vmdq_vlan_hw_filter_enable(dev);
1330 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1331 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1332 (hw->mac.type == e1000_i211)) {
1333 /* Configure EITR with the maximum possible value (0xFFFF) */
1334 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1337 /* Setup link speed and duplex */
1338 speeds = &dev->data->dev_conf.link_speeds;
1339 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1340 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1341 hw->mac.autoneg = 1;
1344 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1347 hw->phy.autoneg_advertised = 0;
1349 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1350 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1351 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1353 goto error_invalid_config;
1355 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1356 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1359 if (*speeds & ETH_LINK_SPEED_10M) {
1360 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1363 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1364 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1367 if (*speeds & ETH_LINK_SPEED_100M) {
1368 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1371 if (*speeds & ETH_LINK_SPEED_1G) {
1372 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1375 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1376 goto error_invalid_config;
1378 /* Set/reset the mac.autoneg based on the link speed,
1382 hw->mac.autoneg = 0;
1383 hw->mac.forced_speed_duplex =
1384 hw->phy.autoneg_advertised;
1386 hw->mac.autoneg = 1;
1390 e1000_setup_link(hw);
1392 if (rte_intr_allow_others(intr_handle)) {
1393 /* check if lsc interrupt is enabled */
1394 if (dev->data->dev_conf.intr_conf.lsc != 0)
1395 eth_igb_lsc_interrupt_setup(dev);
1397 rte_intr_callback_unregister(intr_handle,
1398 eth_igb_interrupt_handler,
1400 if (dev->data->dev_conf.intr_conf.lsc != 0)
1401 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1402 " no intr multiplex\n");
1405 /* check if rxq interrupt is enabled */
1406 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1407 rte_intr_dp_is_en(intr_handle))
1408 eth_igb_rxq_interrupt_setup(dev);
1410 /* enable uio/vfio intr/eventfd mapping */
1411 rte_intr_enable(intr_handle);
1413 /* resume enabled intr since hw reset */
1414 igb_intr_enable(dev);
1416 PMD_INIT_LOG(DEBUG, "<<");
1420 error_invalid_config:
1421 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1422 dev->data->dev_conf.link_speeds, dev->data->port_id);
1423 igb_dev_clear_queues(dev);
1427 /*********************************************************************
1429 * This routine disables all traffic on the adapter by issuing a
1430 * global reset on the MAC.
1432 **********************************************************************/
1434 eth_igb_stop(struct rte_eth_dev *dev)
1436 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1437 struct e1000_filter_info *filter_info =
1438 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1439 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1440 struct rte_eth_link link;
1441 struct e1000_flex_filter *p_flex;
1442 struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1443 struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1444 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1446 igb_intr_disable(hw);
1448 /* disable intr eventfd mapping */
1449 rte_intr_disable(intr_handle);
1451 igb_pf_reset_hw(hw);
1452 E1000_WRITE_REG(hw, E1000_WUC, 0);
1454 /* Set bit for Go Link disconnect */
1455 if (hw->mac.type >= e1000_82580) {
1458 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1459 phpm_reg |= E1000_82580_PM_GO_LINKD;
1460 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1463 /* Power down the phy. Needed to make the link go Down */
1464 eth_igb_dev_set_link_down(dev);
1466 igb_dev_clear_queues(dev);
1468 /* clear the recorded link status */
1469 memset(&link, 0, sizeof(link));
1470 rte_igb_dev_atomic_write_link_status(dev, &link);
1472 /* Remove all flex filters of the device */
1473 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1474 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1477 filter_info->flex_mask = 0;
1479 /* Remove all ntuple filters of the device */
1480 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1481 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1482 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1483 TAILQ_REMOVE(&filter_info->fivetuple_list,
1487 filter_info->fivetuple_mask = 0;
1488 for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1489 p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1490 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1491 TAILQ_REMOVE(&filter_info->twotuple_list,
1495 filter_info->twotuple_mask = 0;
1497 if (!rte_intr_allow_others(intr_handle))
1498 /* resume to the default handler */
1499 rte_intr_callback_register(intr_handle,
1500 eth_igb_interrupt_handler,
1503 /* Clean datapath event and queue/vec mapping */
1504 rte_intr_efd_disable(intr_handle);
1505 if (intr_handle->intr_vec != NULL) {
1506 rte_free(intr_handle->intr_vec);
1507 intr_handle->intr_vec = NULL;
1512 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1514 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1516 if (hw->phy.media_type == e1000_media_type_copper)
1517 e1000_power_up_phy(hw);
1519 e1000_power_up_fiber_serdes_link(hw);
1525 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1527 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1529 if (hw->phy.media_type == e1000_media_type_copper)
1530 e1000_power_down_phy(hw);
1532 e1000_shutdown_fiber_serdes_link(hw);
1538 eth_igb_close(struct rte_eth_dev *dev)
1540 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1541 struct e1000_adapter *adapter =
1542 E1000_DEV_PRIVATE(dev->data->dev_private);
1543 struct rte_eth_link link;
1544 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1545 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1548 adapter->stopped = 1;
1550 e1000_phy_hw_reset(hw);
1551 igb_release_manageability(hw);
1552 igb_hw_control_release(hw);
1554 /* Clear bit for Go Link disconnect */
1555 if (hw->mac.type >= e1000_82580) {
1558 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1559 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1560 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1563 igb_dev_free_queues(dev);
1565 if (intr_handle->intr_vec) {
1566 rte_free(intr_handle->intr_vec);
1567 intr_handle->intr_vec = NULL;
1570 memset(&link, 0, sizeof(link));
1571 rte_igb_dev_atomic_write_link_status(dev, &link);
1575 igb_get_rx_buffer_size(struct e1000_hw *hw)
1577 uint32_t rx_buf_size;
1578 if (hw->mac.type == e1000_82576) {
1579 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1580 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1581 /* PBS needs to be translated according to a lookup table */
1582 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1583 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1584 rx_buf_size = (rx_buf_size << 10);
1585 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1586 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1588 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1594 /*********************************************************************
1596 * Initialize the hardware
1598 **********************************************************************/
1600 igb_hardware_init(struct e1000_hw *hw)
1602 uint32_t rx_buf_size;
1605 /* Let the firmware know the OS is in control */
1606 igb_hw_control_acquire(hw);
1609 * These parameters control the automatic generation (Tx) and
1610 * response (Rx) to Ethernet PAUSE frames.
1611 * - High water mark should allow for at least two standard size (1518)
1612 * frames to be received after sending an XOFF.
1613 * - Low water mark works best when it is very near the high water mark.
1614 * This allows the receiver to restart by sending XON when it has
1615 * drained a bit. Here we use an arbitrary value of 1500 which will
1616 * restart after one full frame is pulled from the buffer. There
1617 * could be several smaller frames in the buffer and if so they will
1618 * not trigger the XON until their total number reduces the buffer
1620 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1622 rx_buf_size = igb_get_rx_buffer_size(hw);
1624 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1625 hw->fc.low_water = hw->fc.high_water - 1500;
1626 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1627 hw->fc.send_xon = 1;
1629 /* Set Flow control, use the tunable location if sane */
1630 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1631 hw->fc.requested_mode = igb_fc_setting;
1633 hw->fc.requested_mode = e1000_fc_none;
1635 /* Issue a global reset */
1636 igb_pf_reset_hw(hw);
1637 E1000_WRITE_REG(hw, E1000_WUC, 0);
1639 diag = e1000_init_hw(hw);
1643 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1644 e1000_get_phy_info(hw);
1645 e1000_check_for_link(hw);
1650 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1652 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1656 uint64_t old_gprc = stats->gprc;
1657 uint64_t old_gptc = stats->gptc;
1658 uint64_t old_tpr = stats->tpr;
1659 uint64_t old_tpt = stats->tpt;
1660 uint64_t old_rpthc = stats->rpthc;
1661 uint64_t old_hgptc = stats->hgptc;
1663 if(hw->phy.media_type == e1000_media_type_copper ||
1664 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1666 E1000_READ_REG(hw,E1000_SYMERRS);
1667 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1670 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1671 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1672 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1673 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1675 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1676 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1677 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1678 stats->dc += E1000_READ_REG(hw, E1000_DC);
1679 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1680 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1681 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1683 ** For watchdog management we need to know if we have been
1684 ** paused during the last interval, so capture that here.
1686 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1687 stats->xoffrxc += pause_frames;
1688 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1689 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1690 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1691 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1692 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1693 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1694 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1695 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1696 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1697 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1698 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1699 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1701 /* For the 64-bit byte counters the low dword must be read first. */
1702 /* Both registers clear on the read of the high dword */
1704 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1705 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1706 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1707 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1708 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1709 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1710 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1712 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1713 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1714 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1715 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1716 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1718 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1719 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1721 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1722 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1723 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1724 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1725 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1726 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1728 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1729 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1730 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1731 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1732 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1733 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1734 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1735 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1737 /* Interrupt Counts */
1739 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1740 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1741 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1742 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1743 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1744 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1745 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1746 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1747 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1749 /* Host to Card Statistics */
1751 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1752 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1753 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1754 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1755 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1756 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1757 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1758 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1759 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1760 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1761 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1762 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1763 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1764 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1765 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1766 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1768 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1769 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1770 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1771 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1772 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1773 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1777 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1779 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1780 struct e1000_hw_stats *stats =
1781 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1783 igb_read_stats_registers(hw, stats);
1785 if (rte_stats == NULL)
1789 rte_stats->imissed = stats->mpc;
1790 rte_stats->ierrors = stats->crcerrs +
1791 stats->rlec + stats->ruc + stats->roc +
1792 stats->rxerrc + stats->algnerrc + stats->cexterr;
1795 rte_stats->oerrors = stats->ecol + stats->latecol;
1797 rte_stats->ipackets = stats->gprc;
1798 rte_stats->opackets = stats->gptc;
1799 rte_stats->ibytes = stats->gorc;
1800 rte_stats->obytes = stats->gotc;
1804 eth_igb_stats_reset(struct rte_eth_dev *dev)
1806 struct e1000_hw_stats *hw_stats =
1807 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1809 /* HW registers are cleared on read */
1810 eth_igb_stats_get(dev, NULL);
1812 /* Reset software totals */
1813 memset(hw_stats, 0, sizeof(*hw_stats));
1817 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1819 struct e1000_hw_stats *stats =
1820 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1822 /* HW registers are cleared on read */
1823 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1825 /* Reset software totals */
1826 memset(stats, 0, sizeof(*stats));
1829 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1830 struct rte_eth_xstat_name *xstats_names,
1831 __rte_unused unsigned limit)
1835 if (xstats_names == NULL)
1836 return IGB_NB_XSTATS;
1838 /* Note: limit checked in rte_eth_xstats_names() */
1840 for (i = 0; i < IGB_NB_XSTATS; i++) {
1841 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1842 "%s", rte_igb_stats_strings[i].name);
1845 return IGB_NB_XSTATS;
1849 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1852 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853 struct e1000_hw_stats *hw_stats =
1854 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1857 if (n < IGB_NB_XSTATS)
1858 return IGB_NB_XSTATS;
1860 igb_read_stats_registers(hw, hw_stats);
1862 /* If this is a reset xstats is NULL, and we have cleared the
1863 * registers by reading them.
1868 /* Extended stats */
1869 for (i = 0; i < IGB_NB_XSTATS; i++) {
1871 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1872 rte_igb_stats_strings[i].offset);
1875 return IGB_NB_XSTATS;
1879 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1881 /* Good Rx packets, include VF loopback */
1882 UPDATE_VF_STAT(E1000_VFGPRC,
1883 hw_stats->last_gprc, hw_stats->gprc);
1885 /* Good Rx octets, include VF loopback */
1886 UPDATE_VF_STAT(E1000_VFGORC,
1887 hw_stats->last_gorc, hw_stats->gorc);
1889 /* Good Tx packets, include VF loopback */
1890 UPDATE_VF_STAT(E1000_VFGPTC,
1891 hw_stats->last_gptc, hw_stats->gptc);
1893 /* Good Tx octets, include VF loopback */
1894 UPDATE_VF_STAT(E1000_VFGOTC,
1895 hw_stats->last_gotc, hw_stats->gotc);
1897 /* Rx Multicst packets */
1898 UPDATE_VF_STAT(E1000_VFMPRC,
1899 hw_stats->last_mprc, hw_stats->mprc);
1901 /* Good Rx loopback packets */
1902 UPDATE_VF_STAT(E1000_VFGPRLBC,
1903 hw_stats->last_gprlbc, hw_stats->gprlbc);
1905 /* Good Rx loopback octets */
1906 UPDATE_VF_STAT(E1000_VFGORLBC,
1907 hw_stats->last_gorlbc, hw_stats->gorlbc);
1909 /* Good Tx loopback packets */
1910 UPDATE_VF_STAT(E1000_VFGPTLBC,
1911 hw_stats->last_gptlbc, hw_stats->gptlbc);
1913 /* Good Tx loopback octets */
1914 UPDATE_VF_STAT(E1000_VFGOTLBC,
1915 hw_stats->last_gotlbc, hw_stats->gotlbc);
1918 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1919 struct rte_eth_xstat_name *xstats_names,
1920 __rte_unused unsigned limit)
1924 if (xstats_names != NULL)
1925 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1926 snprintf(xstats_names[i].name,
1927 sizeof(xstats_names[i].name), "%s",
1928 rte_igbvf_stats_strings[i].name);
1930 return IGBVF_NB_XSTATS;
1934 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1937 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1939 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1942 if (n < IGBVF_NB_XSTATS)
1943 return IGBVF_NB_XSTATS;
1945 igbvf_read_stats_registers(hw, hw_stats);
1950 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1952 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1953 rte_igbvf_stats_strings[i].offset);
1956 return IGBVF_NB_XSTATS;
1960 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1962 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1963 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1964 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1966 igbvf_read_stats_registers(hw, hw_stats);
1968 if (rte_stats == NULL)
1971 rte_stats->ipackets = hw_stats->gprc;
1972 rte_stats->ibytes = hw_stats->gorc;
1973 rte_stats->opackets = hw_stats->gptc;
1974 rte_stats->obytes = hw_stats->gotc;
1978 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1980 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1981 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1983 /* Sync HW register to the last stats */
1984 eth_igbvf_stats_get(dev, NULL);
1986 /* reset HW current stats*/
1987 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1988 offsetof(struct e1000_vf_stats, gprc));
1992 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
1995 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996 struct e1000_fw_version fw;
1999 e1000_get_fw_version(hw, &fw);
2001 switch (hw->mac.type) {
2004 if (!(e1000_get_flash_presence_i210(hw))) {
2005 ret = snprintf(fw_version, fw_size,
2007 fw.invm_major, fw.invm_minor,
2013 /* if option rom is valid, display its version too */
2015 ret = snprintf(fw_version, fw_size,
2016 "%d.%d, 0x%08x, %d.%d.%d",
2017 fw.eep_major, fw.eep_minor, fw.etrack_id,
2018 fw.or_major, fw.or_build, fw.or_patch);
2021 if (fw.etrack_id != 0X0000) {
2022 ret = snprintf(fw_version, fw_size,
2024 fw.eep_major, fw.eep_minor,
2027 ret = snprintf(fw_version, fw_size,
2029 fw.eep_major, fw.eep_minor,
2036 ret += 1; /* add the size of '\0' */
2037 if (fw_size < (u32)ret)
2044 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2046 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2048 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2049 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2050 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2051 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2052 dev_info->rx_offload_capa =
2053 DEV_RX_OFFLOAD_VLAN_STRIP |
2054 DEV_RX_OFFLOAD_IPV4_CKSUM |
2055 DEV_RX_OFFLOAD_UDP_CKSUM |
2056 DEV_RX_OFFLOAD_TCP_CKSUM;
2057 dev_info->tx_offload_capa =
2058 DEV_TX_OFFLOAD_VLAN_INSERT |
2059 DEV_TX_OFFLOAD_IPV4_CKSUM |
2060 DEV_TX_OFFLOAD_UDP_CKSUM |
2061 DEV_TX_OFFLOAD_TCP_CKSUM |
2062 DEV_TX_OFFLOAD_SCTP_CKSUM |
2063 DEV_TX_OFFLOAD_TCP_TSO;
2065 switch (hw->mac.type) {
2067 dev_info->max_rx_queues = 4;
2068 dev_info->max_tx_queues = 4;
2069 dev_info->max_vmdq_pools = 0;
2073 dev_info->max_rx_queues = 16;
2074 dev_info->max_tx_queues = 16;
2075 dev_info->max_vmdq_pools = ETH_8_POOLS;
2076 dev_info->vmdq_queue_num = 16;
2080 dev_info->max_rx_queues = 8;
2081 dev_info->max_tx_queues = 8;
2082 dev_info->max_vmdq_pools = ETH_8_POOLS;
2083 dev_info->vmdq_queue_num = 8;
2087 dev_info->max_rx_queues = 8;
2088 dev_info->max_tx_queues = 8;
2089 dev_info->max_vmdq_pools = ETH_8_POOLS;
2090 dev_info->vmdq_queue_num = 8;
2094 dev_info->max_rx_queues = 8;
2095 dev_info->max_tx_queues = 8;
2099 dev_info->max_rx_queues = 4;
2100 dev_info->max_tx_queues = 4;
2101 dev_info->max_vmdq_pools = 0;
2105 dev_info->max_rx_queues = 2;
2106 dev_info->max_tx_queues = 2;
2107 dev_info->max_vmdq_pools = 0;
2111 /* Should not happen */
2114 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2115 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2116 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2118 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2120 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2121 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2122 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2124 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2128 dev_info->default_txconf = (struct rte_eth_txconf) {
2130 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2131 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2132 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2137 dev_info->rx_desc_lim = rx_desc_lim;
2138 dev_info->tx_desc_lim = tx_desc_lim;
2140 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2141 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2145 static const uint32_t *
2146 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2148 static const uint32_t ptypes[] = {
2149 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2152 RTE_PTYPE_L3_IPV4_EXT,
2154 RTE_PTYPE_L3_IPV6_EXT,
2158 RTE_PTYPE_TUNNEL_IP,
2159 RTE_PTYPE_INNER_L3_IPV6,
2160 RTE_PTYPE_INNER_L3_IPV6_EXT,
2161 RTE_PTYPE_INNER_L4_TCP,
2162 RTE_PTYPE_INNER_L4_UDP,
2166 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2167 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2173 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2175 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2178 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2179 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2180 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2181 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2182 DEV_RX_OFFLOAD_IPV4_CKSUM |
2183 DEV_RX_OFFLOAD_UDP_CKSUM |
2184 DEV_RX_OFFLOAD_TCP_CKSUM;
2185 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2186 DEV_TX_OFFLOAD_IPV4_CKSUM |
2187 DEV_TX_OFFLOAD_UDP_CKSUM |
2188 DEV_TX_OFFLOAD_TCP_CKSUM |
2189 DEV_TX_OFFLOAD_SCTP_CKSUM |
2190 DEV_TX_OFFLOAD_TCP_TSO;
2191 switch (hw->mac.type) {
2193 dev_info->max_rx_queues = 2;
2194 dev_info->max_tx_queues = 2;
2196 case e1000_vfadapt_i350:
2197 dev_info->max_rx_queues = 1;
2198 dev_info->max_tx_queues = 1;
2201 /* Should not happen */
2205 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2207 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2208 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2209 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2211 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2215 dev_info->default_txconf = (struct rte_eth_txconf) {
2217 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2218 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2219 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2224 dev_info->rx_desc_lim = rx_desc_lim;
2225 dev_info->tx_desc_lim = tx_desc_lim;
2228 /* return 0 means link status changed, -1 means not changed */
2230 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2232 struct e1000_hw *hw =
2233 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2234 struct rte_eth_link link, old;
2235 int link_check, count;
2238 hw->mac.get_link_status = 1;
2240 /* possible wait-to-complete in up to 9 seconds */
2241 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2242 /* Read the real link status */
2243 switch (hw->phy.media_type) {
2244 case e1000_media_type_copper:
2245 /* Do the work to read phy */
2246 e1000_check_for_link(hw);
2247 link_check = !hw->mac.get_link_status;
2250 case e1000_media_type_fiber:
2251 e1000_check_for_link(hw);
2252 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2256 case e1000_media_type_internal_serdes:
2257 e1000_check_for_link(hw);
2258 link_check = hw->mac.serdes_has_link;
2261 /* VF device is type_unknown */
2262 case e1000_media_type_unknown:
2263 eth_igbvf_link_update(hw);
2264 link_check = !hw->mac.get_link_status;
2270 if (link_check || wait_to_complete == 0)
2272 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2274 memset(&link, 0, sizeof(link));
2275 rte_igb_dev_atomic_read_link_status(dev, &link);
2278 /* Now we check if a transition has happened */
2280 uint16_t duplex, speed;
2281 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2282 link.link_duplex = (duplex == FULL_DUPLEX) ?
2283 ETH_LINK_FULL_DUPLEX :
2284 ETH_LINK_HALF_DUPLEX;
2285 link.link_speed = speed;
2286 link.link_status = ETH_LINK_UP;
2287 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2288 ETH_LINK_SPEED_FIXED);
2289 } else if (!link_check) {
2290 link.link_speed = 0;
2291 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2292 link.link_status = ETH_LINK_DOWN;
2293 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2295 rte_igb_dev_atomic_write_link_status(dev, &link);
2298 if (old.link_status == link.link_status)
2306 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2307 * For ASF and Pass Through versions of f/w this means
2308 * that the driver is loaded.
2311 igb_hw_control_acquire(struct e1000_hw *hw)
2315 /* Let firmware know the driver has taken over */
2316 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2317 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2321 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2322 * For ASF and Pass Through versions of f/w this means that the
2323 * driver is no longer loaded.
2326 igb_hw_control_release(struct e1000_hw *hw)
2330 /* Let firmware taken over control of h/w */
2331 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2332 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2333 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2337 * Bit of a misnomer, what this really means is
2338 * to enable OS management of the system... aka
2339 * to disable special hardware management features.
2342 igb_init_manageability(struct e1000_hw *hw)
2344 if (e1000_enable_mng_pass_thru(hw)) {
2345 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2346 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2348 /* disable hardware interception of ARP */
2349 manc &= ~(E1000_MANC_ARP_EN);
2351 /* enable receiving management packets to the host */
2352 manc |= E1000_MANC_EN_MNG2HOST;
2353 manc2h |= 1 << 5; /* Mng Port 623 */
2354 manc2h |= 1 << 6; /* Mng Port 664 */
2355 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2356 E1000_WRITE_REG(hw, E1000_MANC, manc);
2361 igb_release_manageability(struct e1000_hw *hw)
2363 if (e1000_enable_mng_pass_thru(hw)) {
2364 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2366 manc |= E1000_MANC_ARP_EN;
2367 manc &= ~E1000_MANC_EN_MNG2HOST;
2369 E1000_WRITE_REG(hw, E1000_MANC, manc);
2374 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2376 struct e1000_hw *hw =
2377 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2380 rctl = E1000_READ_REG(hw, E1000_RCTL);
2381 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2382 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2386 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2388 struct e1000_hw *hw =
2389 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392 rctl = E1000_READ_REG(hw, E1000_RCTL);
2393 rctl &= (~E1000_RCTL_UPE);
2394 if (dev->data->all_multicast == 1)
2395 rctl |= E1000_RCTL_MPE;
2397 rctl &= (~E1000_RCTL_MPE);
2398 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2402 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2404 struct e1000_hw *hw =
2405 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2408 rctl = E1000_READ_REG(hw, E1000_RCTL);
2409 rctl |= E1000_RCTL_MPE;
2410 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2414 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2416 struct e1000_hw *hw =
2417 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2420 if (dev->data->promiscuous == 1)
2421 return; /* must remain in all_multicast mode */
2422 rctl = E1000_READ_REG(hw, E1000_RCTL);
2423 rctl &= (~E1000_RCTL_MPE);
2424 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2428 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2430 struct e1000_hw *hw =
2431 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2432 struct e1000_vfta * shadow_vfta =
2433 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2438 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2439 E1000_VFTA_ENTRY_MASK);
2440 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2441 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2446 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2448 /* update local VFTA copy */
2449 shadow_vfta->vfta[vid_idx] = vfta;
2455 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2456 enum rte_vlan_type vlan_type,
2459 struct e1000_hw *hw =
2460 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2463 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2464 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2466 /* only outer TPID of double VLAN can be configured*/
2467 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2468 reg = E1000_READ_REG(hw, E1000_VET);
2469 reg = (reg & (~E1000_VET_VET_EXT)) |
2470 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2471 E1000_WRITE_REG(hw, E1000_VET, reg);
2476 /* all other TPID values are read-only*/
2477 PMD_DRV_LOG(ERR, "Not supported");
2483 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2485 struct e1000_hw *hw =
2486 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2489 /* Filter Table Disable */
2490 reg = E1000_READ_REG(hw, E1000_RCTL);
2491 reg &= ~E1000_RCTL_CFIEN;
2492 reg &= ~E1000_RCTL_VFE;
2493 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2497 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2499 struct e1000_hw *hw =
2500 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2501 struct e1000_vfta * shadow_vfta =
2502 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2506 /* Filter Table Enable, CFI not used for packet acceptance */
2507 reg = E1000_READ_REG(hw, E1000_RCTL);
2508 reg &= ~E1000_RCTL_CFIEN;
2509 reg |= E1000_RCTL_VFE;
2510 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2512 /* restore VFTA table */
2513 for (i = 0; i < IGB_VFTA_SIZE; i++)
2514 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2518 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2520 struct e1000_hw *hw =
2521 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2524 /* VLAN Mode Disable */
2525 reg = E1000_READ_REG(hw, E1000_CTRL);
2526 reg &= ~E1000_CTRL_VME;
2527 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2531 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2533 struct e1000_hw *hw =
2534 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537 /* VLAN Mode Enable */
2538 reg = E1000_READ_REG(hw, E1000_CTRL);
2539 reg |= E1000_CTRL_VME;
2540 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2544 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2546 struct e1000_hw *hw =
2547 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2550 /* CTRL_EXT: Extended VLAN */
2551 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2552 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2553 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2555 /* Update maximum packet length */
2556 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2557 E1000_WRITE_REG(hw, E1000_RLPML,
2558 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2563 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2565 struct e1000_hw *hw =
2566 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569 /* CTRL_EXT: Extended VLAN */
2570 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2571 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2572 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2574 /* Update maximum packet length */
2575 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2576 E1000_WRITE_REG(hw, E1000_RLPML,
2577 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2582 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2584 if(mask & ETH_VLAN_STRIP_MASK){
2585 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2586 igb_vlan_hw_strip_enable(dev);
2588 igb_vlan_hw_strip_disable(dev);
2591 if(mask & ETH_VLAN_FILTER_MASK){
2592 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2593 igb_vlan_hw_filter_enable(dev);
2595 igb_vlan_hw_filter_disable(dev);
2598 if(mask & ETH_VLAN_EXTEND_MASK){
2599 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2600 igb_vlan_hw_extend_enable(dev);
2602 igb_vlan_hw_extend_disable(dev);
2608 * It enables the interrupt mask and then enable the interrupt.
2611 * Pointer to struct rte_eth_dev.
2614 * - On success, zero.
2615 * - On failure, a negative value.
2618 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2620 struct e1000_interrupt *intr =
2621 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2623 intr->mask |= E1000_ICR_LSC;
2628 /* It clears the interrupt causes and enables the interrupt.
2629 * It will be called once only during nic initialized.
2632 * Pointer to struct rte_eth_dev.
2635 * - On success, zero.
2636 * - On failure, a negative value.
2638 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2640 uint32_t mask, regval;
2641 struct e1000_hw *hw =
2642 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2643 struct rte_eth_dev_info dev_info;
2645 memset(&dev_info, 0, sizeof(dev_info));
2646 eth_igb_infos_get(dev, &dev_info);
2648 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2649 regval = E1000_READ_REG(hw, E1000_EIMS);
2650 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2656 * It reads ICR and gets interrupt causes, check it and set a bit flag
2657 * to update link status.
2660 * Pointer to struct rte_eth_dev.
2663 * - On success, zero.
2664 * - On failure, a negative value.
2667 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2670 struct e1000_hw *hw =
2671 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2672 struct e1000_interrupt *intr =
2673 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2675 igb_intr_disable(hw);
2677 /* read-on-clear nic registers here */
2678 icr = E1000_READ_REG(hw, E1000_ICR);
2681 if (icr & E1000_ICR_LSC) {
2682 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2685 if (icr & E1000_ICR_VMMB)
2686 intr->flags |= E1000_FLAG_MAILBOX;
2692 * It executes link_update after knowing an interrupt is prsent.
2695 * Pointer to struct rte_eth_dev.
2698 * - On success, zero.
2699 * - On failure, a negative value.
2702 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2703 struct rte_intr_handle *intr_handle)
2705 struct e1000_hw *hw =
2706 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707 struct e1000_interrupt *intr =
2708 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2709 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
2710 uint32_t tctl, rctl;
2711 struct rte_eth_link link;
2714 if (intr->flags & E1000_FLAG_MAILBOX) {
2715 igb_pf_mbx_process(dev);
2716 intr->flags &= ~E1000_FLAG_MAILBOX;
2719 igb_intr_enable(dev);
2720 rte_intr_enable(intr_handle);
2722 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2723 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2725 /* set get_link_status to check register later */
2726 hw->mac.get_link_status = 1;
2727 ret = eth_igb_link_update(dev, 0);
2729 /* check if link has changed */
2733 memset(&link, 0, sizeof(link));
2734 rte_igb_dev_atomic_read_link_status(dev, &link);
2735 if (link.link_status) {
2737 " Port %d: Link Up - speed %u Mbps - %s",
2739 (unsigned)link.link_speed,
2740 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2741 "full-duplex" : "half-duplex");
2743 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2744 dev->data->port_id);
2747 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2748 pci_dev->addr.domain,
2750 pci_dev->addr.devid,
2751 pci_dev->addr.function);
2752 tctl = E1000_READ_REG(hw, E1000_TCTL);
2753 rctl = E1000_READ_REG(hw, E1000_RCTL);
2754 if (link.link_status) {
2756 tctl |= E1000_TCTL_EN;
2757 rctl |= E1000_RCTL_EN;
2760 tctl &= ~E1000_TCTL_EN;
2761 rctl &= ~E1000_RCTL_EN;
2763 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2764 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2765 E1000_WRITE_FLUSH(hw);
2766 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2773 * Interrupt handler which shall be registered at first.
2776 * Pointer to interrupt handle.
2778 * The address of parameter (struct rte_eth_dev *) regsitered before.
2784 eth_igb_interrupt_handler(struct rte_intr_handle *handle, void *param)
2786 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2788 eth_igb_interrupt_get_status(dev);
2789 eth_igb_interrupt_action(dev, handle);
2793 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2796 struct e1000_hw *hw =
2797 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2798 struct e1000_interrupt *intr =
2799 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2801 igbvf_intr_disable(hw);
2803 /* read-on-clear nic registers here */
2804 eicr = E1000_READ_REG(hw, E1000_EICR);
2807 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2808 intr->flags |= E1000_FLAG_MAILBOX;
2813 void igbvf_mbx_process(struct rte_eth_dev *dev)
2815 struct e1000_hw *hw =
2816 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2817 struct e1000_mbx_info *mbx = &hw->mbx;
2820 if (mbx->ops.read(hw, &in_msg, 1, 0))
2823 /* PF reset VF event */
2824 if (in_msg == E1000_PF_CONTROL_MSG)
2825 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2829 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2831 struct e1000_interrupt *intr =
2832 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2834 if (intr->flags & E1000_FLAG_MAILBOX) {
2835 igbvf_mbx_process(dev);
2836 intr->flags &= ~E1000_FLAG_MAILBOX;
2839 igbvf_intr_enable(dev);
2840 rte_intr_enable(intr_handle);
2846 eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
2849 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2851 eth_igbvf_interrupt_get_status(dev);
2852 eth_igbvf_interrupt_action(dev, handle);
2856 eth_igb_led_on(struct rte_eth_dev *dev)
2858 struct e1000_hw *hw;
2860 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2865 eth_igb_led_off(struct rte_eth_dev *dev)
2867 struct e1000_hw *hw;
2869 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2870 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2874 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2876 struct e1000_hw *hw;
2881 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2882 fc_conf->pause_time = hw->fc.pause_time;
2883 fc_conf->high_water = hw->fc.high_water;
2884 fc_conf->low_water = hw->fc.low_water;
2885 fc_conf->send_xon = hw->fc.send_xon;
2886 fc_conf->autoneg = hw->mac.autoneg;
2889 * Return rx_pause and tx_pause status according to actual setting of
2890 * the TFCE and RFCE bits in the CTRL register.
2892 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2893 if (ctrl & E1000_CTRL_TFCE)
2898 if (ctrl & E1000_CTRL_RFCE)
2903 if (rx_pause && tx_pause)
2904 fc_conf->mode = RTE_FC_FULL;
2906 fc_conf->mode = RTE_FC_RX_PAUSE;
2908 fc_conf->mode = RTE_FC_TX_PAUSE;
2910 fc_conf->mode = RTE_FC_NONE;
2916 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2918 struct e1000_hw *hw;
2920 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2926 uint32_t rx_buf_size;
2927 uint32_t max_high_water;
2930 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2931 if (fc_conf->autoneg != hw->mac.autoneg)
2933 rx_buf_size = igb_get_rx_buffer_size(hw);
2934 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2936 /* At least reserve one Ethernet frame for watermark */
2937 max_high_water = rx_buf_size - ETHER_MAX_LEN;
2938 if ((fc_conf->high_water > max_high_water) ||
2939 (fc_conf->high_water < fc_conf->low_water)) {
2940 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2941 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
2945 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2946 hw->fc.pause_time = fc_conf->pause_time;
2947 hw->fc.high_water = fc_conf->high_water;
2948 hw->fc.low_water = fc_conf->low_water;
2949 hw->fc.send_xon = fc_conf->send_xon;
2951 err = e1000_setup_link_generic(hw);
2952 if (err == E1000_SUCCESS) {
2954 /* check if we want to forward MAC frames - driver doesn't have native
2955 * capability to do that, so we'll write the registers ourselves */
2957 rctl = E1000_READ_REG(hw, E1000_RCTL);
2959 /* set or clear MFLCN.PMCF bit depending on configuration */
2960 if (fc_conf->mac_ctrl_frame_fwd != 0)
2961 rctl |= E1000_RCTL_PMCF;
2963 rctl &= ~E1000_RCTL_PMCF;
2965 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2966 E1000_WRITE_FLUSH(hw);
2971 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2975 #define E1000_RAH_POOLSEL_SHIFT (18)
2977 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2978 uint32_t index, __rte_unused uint32_t pool)
2980 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2983 e1000_rar_set(hw, mac_addr->addr_bytes, index);
2984 rah = E1000_READ_REG(hw, E1000_RAH(index));
2985 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2986 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2990 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2992 uint8_t addr[ETHER_ADDR_LEN];
2993 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2995 memset(addr, 0, sizeof(addr));
2997 e1000_rar_set(hw, addr, index);
3001 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3002 struct ether_addr *addr)
3004 eth_igb_rar_clear(dev, 0);
3006 eth_igb_rar_set(dev, (void *)addr, 0, 0);
3009 * Virtual Function operations
3012 igbvf_intr_disable(struct e1000_hw *hw)
3014 PMD_INIT_FUNC_TRACE();
3016 /* Clear interrupt mask to stop from interrupts being generated */
3017 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3019 E1000_WRITE_FLUSH(hw);
3023 igbvf_stop_adapter(struct rte_eth_dev *dev)
3027 struct rte_eth_dev_info dev_info;
3028 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030 memset(&dev_info, 0, sizeof(dev_info));
3031 eth_igbvf_infos_get(dev, &dev_info);
3033 /* Clear interrupt mask to stop from interrupts being generated */
3034 igbvf_intr_disable(hw);
3036 /* Clear any pending interrupts, flush previous writes */
3037 E1000_READ_REG(hw, E1000_EICR);
3039 /* Disable the transmit unit. Each queue must be disabled. */
3040 for (i = 0; i < dev_info.max_tx_queues; i++)
3041 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3043 /* Disable the receive unit by stopping each queue */
3044 for (i = 0; i < dev_info.max_rx_queues; i++) {
3045 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3046 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3047 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3048 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3052 /* flush all queues disables */
3053 E1000_WRITE_FLUSH(hw);
3057 static int eth_igbvf_link_update(struct e1000_hw *hw)
3059 struct e1000_mbx_info *mbx = &hw->mbx;
3060 struct e1000_mac_info *mac = &hw->mac;
3061 int ret_val = E1000_SUCCESS;
3063 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3066 * We only want to run this if there has been a rst asserted.
3067 * in this case that could mean a link change, device reset,
3068 * or a virtual function reset
3071 /* If we were hit with a reset or timeout drop the link */
3072 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3073 mac->get_link_status = TRUE;
3075 if (!mac->get_link_status)
3078 /* if link status is down no point in checking to see if pf is up */
3079 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3082 /* if we passed all the tests above then the link is up and we no
3083 * longer need to check for link */
3084 mac->get_link_status = FALSE;
3092 igbvf_dev_configure(struct rte_eth_dev *dev)
3094 struct rte_eth_conf* conf = &dev->data->dev_conf;
3096 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3097 dev->data->port_id);
3100 * VF has no ability to enable/disable HW CRC
3101 * Keep the persistent behavior the same as Host PF
3103 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3104 if (!conf->rxmode.hw_strip_crc) {
3105 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3106 conf->rxmode.hw_strip_crc = 1;
3109 if (conf->rxmode.hw_strip_crc) {
3110 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3111 conf->rxmode.hw_strip_crc = 0;
3119 igbvf_dev_start(struct rte_eth_dev *dev)
3121 struct e1000_hw *hw =
3122 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3123 struct e1000_adapter *adapter =
3124 E1000_DEV_PRIVATE(dev->data->dev_private);
3125 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3126 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3128 uint32_t intr_vector = 0;
3130 PMD_INIT_FUNC_TRACE();
3132 hw->mac.ops.reset_hw(hw);
3133 adapter->stopped = 0;
3136 igbvf_set_vfta_all(dev,1);
3138 eth_igbvf_tx_init(dev);
3140 /* This can fail when allocating mbufs for descriptor rings */
3141 ret = eth_igbvf_rx_init(dev);
3143 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3144 igb_dev_clear_queues(dev);
3148 /* check and configure queue intr-vector mapping */
3149 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3150 intr_vector = dev->data->nb_rx_queues;
3151 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3156 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3157 intr_handle->intr_vec =
3158 rte_zmalloc("intr_vec",
3159 dev->data->nb_rx_queues * sizeof(int), 0);
3160 if (!intr_handle->intr_vec) {
3161 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3162 " intr_vec\n", dev->data->nb_rx_queues);
3167 eth_igbvf_configure_msix_intr(dev);
3169 /* enable uio/vfio intr/eventfd mapping */
3170 rte_intr_enable(intr_handle);
3172 /* resume enabled intr since hw reset */
3173 igbvf_intr_enable(dev);
3179 igbvf_dev_stop(struct rte_eth_dev *dev)
3181 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3182 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3184 PMD_INIT_FUNC_TRACE();
3186 igbvf_stop_adapter(dev);
3189 * Clear what we set, but we still keep shadow_vfta to
3190 * restore after device starts
3192 igbvf_set_vfta_all(dev,0);
3194 igb_dev_clear_queues(dev);
3196 /* disable intr eventfd mapping */
3197 rte_intr_disable(intr_handle);
3199 /* Clean datapath event and queue/vec mapping */
3200 rte_intr_efd_disable(intr_handle);
3201 if (intr_handle->intr_vec) {
3202 rte_free(intr_handle->intr_vec);
3203 intr_handle->intr_vec = NULL;
3208 igbvf_dev_close(struct rte_eth_dev *dev)
3210 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3211 struct e1000_adapter *adapter =
3212 E1000_DEV_PRIVATE(dev->data->dev_private);
3213 struct ether_addr addr;
3215 PMD_INIT_FUNC_TRACE();
3219 igbvf_dev_stop(dev);
3220 adapter->stopped = 1;
3221 igb_dev_free_queues(dev);
3224 * reprogram the RAR with a zero mac address,
3225 * to ensure that the VF traffic goes to the PF
3226 * after stop, close and detach of the VF.
3229 memset(&addr, 0, sizeof(addr));
3230 igbvf_default_mac_addr_set(dev, &addr);
3234 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3236 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3238 /* Set both unicast and multicast promisc */
3239 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3243 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3245 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3247 /* If in allmulticast mode leave multicast promisc */
3248 if (dev->data->all_multicast == 1)
3249 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3251 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3255 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3257 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3259 /* In promiscuous mode multicast promisc already set */
3260 if (dev->data->promiscuous == 0)
3261 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3265 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3267 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269 /* In promiscuous mode leave multicast promisc enabled */
3270 if (dev->data->promiscuous == 0)
3271 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3274 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3276 struct e1000_mbx_info *mbx = &hw->mbx;
3280 /* After set vlan, vlan strip will also be enabled in igb driver*/
3281 msgbuf[0] = E1000_VF_SET_VLAN;
3283 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3285 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3287 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3291 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3295 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3296 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3303 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3305 struct e1000_hw *hw =
3306 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307 struct e1000_vfta * shadow_vfta =
3308 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3309 int i = 0, j = 0, vfta = 0, mask = 1;
3311 for (i = 0; i < IGB_VFTA_SIZE; i++){
3312 vfta = shadow_vfta->vfta[i];
3315 for (j = 0; j < 32; j++){
3318 (uint16_t)((i<<5)+j), on);
3327 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3329 struct e1000_hw *hw =
3330 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3331 struct e1000_vfta * shadow_vfta =
3332 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3333 uint32_t vid_idx = 0;
3334 uint32_t vid_bit = 0;
3337 PMD_INIT_FUNC_TRACE();
3339 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3340 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3342 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3345 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3346 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3348 /*Save what we set and retore it after device reset*/
3350 shadow_vfta->vfta[vid_idx] |= vid_bit;
3352 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3358 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3360 struct e1000_hw *hw =
3361 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3363 /* index is not used by rar_set() */
3364 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3369 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3370 struct rte_eth_rss_reta_entry64 *reta_conf,
3375 uint16_t idx, shift;
3376 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3379 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3380 "(%d) doesn't match the number hardware can supported "
3381 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3385 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3386 idx = i / RTE_RETA_GROUP_SIZE;
3387 shift = i % RTE_RETA_GROUP_SIZE;
3388 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3392 if (mask == IGB_4_BIT_MASK)
3395 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3396 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3397 if (mask & (0x1 << j))
3398 reta |= reta_conf[idx].reta[shift + j] <<
3401 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3403 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3410 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3411 struct rte_eth_rss_reta_entry64 *reta_conf,
3416 uint16_t idx, shift;
3417 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3419 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3420 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3421 "(%d) doesn't match the number hardware can supported "
3422 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3426 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3427 idx = i / RTE_RETA_GROUP_SIZE;
3428 shift = i % RTE_RETA_GROUP_SIZE;
3429 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3433 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3434 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3435 if (mask & (0x1 << j))
3436 reta_conf[idx].reta[shift + j] =
3437 ((reta >> (CHAR_BIT * j)) &
3445 #define MAC_TYPE_FILTER_SUP(type) do {\
3446 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3447 (type) != e1000_82576)\
3452 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3453 struct rte_eth_syn_filter *filter,
3456 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3457 uint32_t synqf, rfctl;
3459 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3462 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3465 if (synqf & E1000_SYN_FILTER_ENABLE)
3468 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3469 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3471 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3472 if (filter->hig_pri)
3473 rfctl |= E1000_RFCTL_SYNQFP;
3475 rfctl &= ~E1000_RFCTL_SYNQFP;
3477 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3479 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3484 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3485 E1000_WRITE_FLUSH(hw);
3490 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3491 struct rte_eth_syn_filter *filter)
3493 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3494 uint32_t synqf, rfctl;
3496 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3497 if (synqf & E1000_SYN_FILTER_ENABLE) {
3498 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3499 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3500 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3501 E1000_SYN_FILTER_QUEUE_SHIFT);
3509 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3510 enum rte_filter_op filter_op,
3513 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3516 MAC_TYPE_FILTER_SUP(hw->mac.type);
3518 if (filter_op == RTE_ETH_FILTER_NOP)
3522 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3527 switch (filter_op) {
3528 case RTE_ETH_FILTER_ADD:
3529 ret = eth_igb_syn_filter_set(dev,
3530 (struct rte_eth_syn_filter *)arg,
3533 case RTE_ETH_FILTER_DELETE:
3534 ret = eth_igb_syn_filter_set(dev,
3535 (struct rte_eth_syn_filter *)arg,
3538 case RTE_ETH_FILTER_GET:
3539 ret = eth_igb_syn_filter_get(dev,
3540 (struct rte_eth_syn_filter *)arg);
3543 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3551 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
3552 if ((type) != e1000_82580 && (type) != e1000_i350)\
3556 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3558 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3559 struct e1000_2tuple_filter_info *filter_info)
3561 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3563 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3564 return -EINVAL; /* filter index is out of range. */
3565 if (filter->tcp_flags > TCP_FLAG_ALL)
3566 return -EINVAL; /* flags is invalid. */
3568 switch (filter->dst_port_mask) {
3570 filter_info->dst_port_mask = 0;
3571 filter_info->dst_port = filter->dst_port;
3574 filter_info->dst_port_mask = 1;
3577 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3581 switch (filter->proto_mask) {
3583 filter_info->proto_mask = 0;
3584 filter_info->proto = filter->proto;
3587 filter_info->proto_mask = 1;
3590 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3594 filter_info->priority = (uint8_t)filter->priority;
3595 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3596 filter_info->tcp_flags = filter->tcp_flags;
3598 filter_info->tcp_flags = 0;
3603 static inline struct e1000_2tuple_filter *
3604 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3605 struct e1000_2tuple_filter_info *key)
3607 struct e1000_2tuple_filter *it;
3609 TAILQ_FOREACH(it, filter_list, entries) {
3610 if (memcmp(key, &it->filter_info,
3611 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3619 * igb_add_2tuple_filter - add a 2tuple filter
3622 * dev: Pointer to struct rte_eth_dev.
3623 * ntuple_filter: ponter to the filter that will be added.
3626 * - On success, zero.
3627 * - On failure, a negative value.
3630 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3631 struct rte_eth_ntuple_filter *ntuple_filter)
3633 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3634 struct e1000_filter_info *filter_info =
3635 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3636 struct e1000_2tuple_filter *filter;
3637 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3638 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3641 filter = rte_zmalloc("e1000_2tuple_filter",
3642 sizeof(struct e1000_2tuple_filter), 0);
3646 ret = ntuple_filter_to_2tuple(ntuple_filter,
3647 &filter->filter_info);
3652 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3653 &filter->filter_info) != NULL) {
3654 PMD_DRV_LOG(ERR, "filter exists.");
3658 filter->queue = ntuple_filter->queue;
3661 * look for an unused 2tuple filter index,
3662 * and insert the filter to list.
3664 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3665 if (!(filter_info->twotuple_mask & (1 << i))) {
3666 filter_info->twotuple_mask |= 1 << i;
3668 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3674 if (i >= E1000_MAX_TTQF_FILTERS) {
3675 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3680 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3681 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3682 imir |= E1000_IMIR_PORT_BP;
3684 imir &= ~E1000_IMIR_PORT_BP;
3686 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3688 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3689 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3690 ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3691 if (filter->filter_info.proto_mask == 0)
3692 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3694 /* tcp flags bits setting. */
3695 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3696 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3697 imir_ext |= E1000_IMIREXT_CTRL_URG;
3698 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3699 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3700 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3701 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3702 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3703 imir_ext |= E1000_IMIREXT_CTRL_RST;
3704 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3705 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3706 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3707 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3709 imir_ext |= E1000_IMIREXT_CTRL_BP;
3710 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3711 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3712 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3717 * igb_remove_2tuple_filter - remove a 2tuple filter
3720 * dev: Pointer to struct rte_eth_dev.
3721 * ntuple_filter: ponter to the filter that will be removed.
3724 * - On success, zero.
3725 * - On failure, a negative value.
3728 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3729 struct rte_eth_ntuple_filter *ntuple_filter)
3731 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3732 struct e1000_filter_info *filter_info =
3733 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3734 struct e1000_2tuple_filter_info filter_2tuple;
3735 struct e1000_2tuple_filter *filter;
3738 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3739 ret = ntuple_filter_to_2tuple(ntuple_filter,
3744 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3746 if (filter == NULL) {
3747 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3751 filter_info->twotuple_mask &= ~(1 << filter->index);
3752 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3755 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3756 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3757 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3761 static inline struct e1000_flex_filter *
3762 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3763 struct e1000_flex_filter_info *key)
3765 struct e1000_flex_filter *it;
3767 TAILQ_FOREACH(it, filter_list, entries) {
3768 if (memcmp(key, &it->filter_info,
3769 sizeof(struct e1000_flex_filter_info)) == 0)
3777 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3778 struct rte_eth_flex_filter *filter,
3781 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3782 struct e1000_filter_info *filter_info =
3783 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3784 struct e1000_flex_filter *flex_filter, *it;
3785 uint32_t wufc, queueing, mask;
3787 uint8_t shift, i, j = 0;
3789 flex_filter = rte_zmalloc("e1000_flex_filter",
3790 sizeof(struct e1000_flex_filter), 0);
3791 if (flex_filter == NULL)
3794 flex_filter->filter_info.len = filter->len;
3795 flex_filter->filter_info.priority = filter->priority;
3796 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3797 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3799 /* reverse bits in flex filter's mask*/
3800 for (shift = 0; shift < CHAR_BIT; shift++) {
3801 if (filter->mask[i] & (0x01 << shift))
3802 mask |= (0x80 >> shift);
3804 flex_filter->filter_info.mask[i] = mask;
3807 wufc = E1000_READ_REG(hw, E1000_WUFC);
3808 if (flex_filter->index < E1000_MAX_FHFT)
3809 reg_off = E1000_FHFT(flex_filter->index);
3811 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3814 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3815 &flex_filter->filter_info) != NULL) {
3816 PMD_DRV_LOG(ERR, "filter exists.");
3817 rte_free(flex_filter);
3820 flex_filter->queue = filter->queue;
3822 * look for an unused flex filter index
3823 * and insert the filter into the list.
3825 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3826 if (!(filter_info->flex_mask & (1 << i))) {
3827 filter_info->flex_mask |= 1 << i;
3828 flex_filter->index = i;
3829 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3835 if (i >= E1000_MAX_FLEX_FILTERS) {
3836 PMD_DRV_LOG(ERR, "flex filters are full.");
3837 rte_free(flex_filter);
3841 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3842 (E1000_WUFC_FLX0 << flex_filter->index));
3843 queueing = filter->len |
3844 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3845 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3846 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3848 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3849 E1000_WRITE_REG(hw, reg_off,
3850 flex_filter->filter_info.dwords[j]);
3851 reg_off += sizeof(uint32_t);
3852 E1000_WRITE_REG(hw, reg_off,
3853 flex_filter->filter_info.dwords[++j]);
3854 reg_off += sizeof(uint32_t);
3855 E1000_WRITE_REG(hw, reg_off,
3856 (uint32_t)flex_filter->filter_info.mask[i]);
3857 reg_off += sizeof(uint32_t) * 2;
3861 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3862 &flex_filter->filter_info);
3864 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3865 rte_free(flex_filter);
3869 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3870 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3871 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3872 (~(E1000_WUFC_FLX0 << it->index)));
3874 filter_info->flex_mask &= ~(1 << it->index);
3875 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3877 rte_free(flex_filter);
3884 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3885 struct rte_eth_flex_filter *filter)
3887 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3888 struct e1000_filter_info *filter_info =
3889 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3890 struct e1000_flex_filter flex_filter, *it;
3891 uint32_t wufc, queueing, wufc_en = 0;
3893 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3894 flex_filter.filter_info.len = filter->len;
3895 flex_filter.filter_info.priority = filter->priority;
3896 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3897 memcpy(flex_filter.filter_info.mask, filter->mask,
3898 RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3900 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3901 &flex_filter.filter_info);
3903 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3907 wufc = E1000_READ_REG(hw, E1000_WUFC);
3908 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3910 if ((wufc & wufc_en) == wufc_en) {
3911 uint32_t reg_off = 0;
3912 if (it->index < E1000_MAX_FHFT)
3913 reg_off = E1000_FHFT(it->index);
3915 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3917 queueing = E1000_READ_REG(hw,
3918 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3919 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3920 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3921 E1000_FHFT_QUEUEING_PRIO_SHIFT;
3922 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3923 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3930 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3931 enum rte_filter_op filter_op,
3934 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3935 struct rte_eth_flex_filter *filter;
3938 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3940 if (filter_op == RTE_ETH_FILTER_NOP)
3944 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3949 filter = (struct rte_eth_flex_filter *)arg;
3950 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3951 || filter->len % sizeof(uint64_t) != 0) {
3952 PMD_DRV_LOG(ERR, "filter's length is out of range");
3955 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3956 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3960 switch (filter_op) {
3961 case RTE_ETH_FILTER_ADD:
3962 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3964 case RTE_ETH_FILTER_DELETE:
3965 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3967 case RTE_ETH_FILTER_GET:
3968 ret = eth_igb_get_flex_filter(dev, filter);
3971 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3979 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3981 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3982 struct e1000_5tuple_filter_info *filter_info)
3984 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3986 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3987 return -EINVAL; /* filter index is out of range. */
3988 if (filter->tcp_flags > TCP_FLAG_ALL)
3989 return -EINVAL; /* flags is invalid. */
3991 switch (filter->dst_ip_mask) {
3993 filter_info->dst_ip_mask = 0;
3994 filter_info->dst_ip = filter->dst_ip;
3997 filter_info->dst_ip_mask = 1;
4000 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4004 switch (filter->src_ip_mask) {
4006 filter_info->src_ip_mask = 0;
4007 filter_info->src_ip = filter->src_ip;
4010 filter_info->src_ip_mask = 1;
4013 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4017 switch (filter->dst_port_mask) {
4019 filter_info->dst_port_mask = 0;
4020 filter_info->dst_port = filter->dst_port;
4023 filter_info->dst_port_mask = 1;
4026 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4030 switch (filter->src_port_mask) {
4032 filter_info->src_port_mask = 0;
4033 filter_info->src_port = filter->src_port;
4036 filter_info->src_port_mask = 1;
4039 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4043 switch (filter->proto_mask) {
4045 filter_info->proto_mask = 0;
4046 filter_info->proto = filter->proto;
4049 filter_info->proto_mask = 1;
4052 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4056 filter_info->priority = (uint8_t)filter->priority;
4057 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4058 filter_info->tcp_flags = filter->tcp_flags;
4060 filter_info->tcp_flags = 0;
4065 static inline struct e1000_5tuple_filter *
4066 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4067 struct e1000_5tuple_filter_info *key)
4069 struct e1000_5tuple_filter *it;
4071 TAILQ_FOREACH(it, filter_list, entries) {
4072 if (memcmp(key, &it->filter_info,
4073 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4081 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4084 * dev: Pointer to struct rte_eth_dev.
4085 * ntuple_filter: ponter to the filter that will be added.
4088 * - On success, zero.
4089 * - On failure, a negative value.
4092 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4093 struct rte_eth_ntuple_filter *ntuple_filter)
4095 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4096 struct e1000_filter_info *filter_info =
4097 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4098 struct e1000_5tuple_filter *filter;
4099 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4100 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4104 filter = rte_zmalloc("e1000_5tuple_filter",
4105 sizeof(struct e1000_5tuple_filter), 0);
4109 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4110 &filter->filter_info);
4116 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4117 &filter->filter_info) != NULL) {
4118 PMD_DRV_LOG(ERR, "filter exists.");
4122 filter->queue = ntuple_filter->queue;
4125 * look for an unused 5tuple filter index,
4126 * and insert the filter to list.
4128 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4129 if (!(filter_info->fivetuple_mask & (1 << i))) {
4130 filter_info->fivetuple_mask |= 1 << i;
4132 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4138 if (i >= E1000_MAX_FTQF_FILTERS) {
4139 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4144 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4145 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4146 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4147 if (filter->filter_info.dst_ip_mask == 0)
4148 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4149 if (filter->filter_info.src_port_mask == 0)
4150 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4151 if (filter->filter_info.proto_mask == 0)
4152 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4153 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4154 E1000_FTQF_QUEUE_MASK;
4155 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4156 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4157 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4158 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4160 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4161 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4163 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4164 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4165 imir |= E1000_IMIR_PORT_BP;
4167 imir &= ~E1000_IMIR_PORT_BP;
4168 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4170 /* tcp flags bits setting. */
4171 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4172 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4173 imir_ext |= E1000_IMIREXT_CTRL_URG;
4174 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4175 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4176 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4177 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4178 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4179 imir_ext |= E1000_IMIREXT_CTRL_RST;
4180 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4181 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4182 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4183 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4185 imir_ext |= E1000_IMIREXT_CTRL_BP;
4186 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4187 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4192 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4195 * dev: Pointer to struct rte_eth_dev.
4196 * ntuple_filter: ponter to the filter that will be removed.
4199 * - On success, zero.
4200 * - On failure, a negative value.
4203 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4204 struct rte_eth_ntuple_filter *ntuple_filter)
4206 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4207 struct e1000_filter_info *filter_info =
4208 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4209 struct e1000_5tuple_filter_info filter_5tuple;
4210 struct e1000_5tuple_filter *filter;
4213 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4214 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4219 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4221 if (filter == NULL) {
4222 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4226 filter_info->fivetuple_mask &= ~(1 << filter->index);
4227 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4230 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4231 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4232 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4233 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4234 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4235 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4236 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4241 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4244 struct e1000_hw *hw;
4245 struct rte_eth_dev_info dev_info;
4246 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4249 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4251 #ifdef RTE_LIBRTE_82571_SUPPORT
4252 /* XXX: not bigger than max_rx_pktlen */
4253 if (hw->mac.type == e1000_82571)
4256 eth_igb_infos_get(dev, &dev_info);
4258 /* check that mtu is within the allowed range */
4259 if ((mtu < ETHER_MIN_MTU) ||
4260 (frame_size > dev_info.max_rx_pktlen))
4263 /* refuse mtu that requires the support of scattered packets when this
4264 * feature has not been enabled before. */
4265 if (!dev->data->scattered_rx &&
4266 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4269 rctl = E1000_READ_REG(hw, E1000_RCTL);
4271 /* switch to jumbo mode if needed */
4272 if (frame_size > ETHER_MAX_LEN) {
4273 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4274 rctl |= E1000_RCTL_LPE;
4276 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4277 rctl &= ~E1000_RCTL_LPE;
4279 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4281 /* update max frame size */
4282 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4284 E1000_WRITE_REG(hw, E1000_RLPML,
4285 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4291 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4294 * dev: Pointer to struct rte_eth_dev.
4295 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4296 * add: if true, add filter, if false, remove filter
4299 * - On success, zero.
4300 * - On failure, a negative value.
4303 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4304 struct rte_eth_ntuple_filter *ntuple_filter,
4307 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4310 switch (ntuple_filter->flags) {
4311 case RTE_5TUPLE_FLAGS:
4312 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4313 if (hw->mac.type != e1000_82576)
4316 ret = igb_add_5tuple_filter_82576(dev,
4319 ret = igb_remove_5tuple_filter_82576(dev,
4322 case RTE_2TUPLE_FLAGS:
4323 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4324 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4327 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4329 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4340 * igb_get_ntuple_filter - get a ntuple filter
4343 * dev: Pointer to struct rte_eth_dev.
4344 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4347 * - On success, zero.
4348 * - On failure, a negative value.
4351 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4352 struct rte_eth_ntuple_filter *ntuple_filter)
4354 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4355 struct e1000_filter_info *filter_info =
4356 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4357 struct e1000_5tuple_filter_info filter_5tuple;
4358 struct e1000_2tuple_filter_info filter_2tuple;
4359 struct e1000_5tuple_filter *p_5tuple_filter;
4360 struct e1000_2tuple_filter *p_2tuple_filter;
4363 switch (ntuple_filter->flags) {
4364 case RTE_5TUPLE_FLAGS:
4365 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4366 if (hw->mac.type != e1000_82576)
4368 memset(&filter_5tuple,
4370 sizeof(struct e1000_5tuple_filter_info));
4371 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4375 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4376 &filter_info->fivetuple_list,
4378 if (p_5tuple_filter == NULL) {
4379 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4382 ntuple_filter->queue = p_5tuple_filter->queue;
4384 case RTE_2TUPLE_FLAGS:
4385 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4386 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4388 memset(&filter_2tuple,
4390 sizeof(struct e1000_2tuple_filter_info));
4391 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4394 p_2tuple_filter = igb_2tuple_filter_lookup(
4395 &filter_info->twotuple_list,
4397 if (p_2tuple_filter == NULL) {
4398 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4401 ntuple_filter->queue = p_2tuple_filter->queue;
4412 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4413 * @dev: pointer to rte_eth_dev structure
4414 * @filter_op:operation will be taken.
4415 * @arg: a pointer to specific structure corresponding to the filter_op
4418 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4419 enum rte_filter_op filter_op,
4422 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4425 MAC_TYPE_FILTER_SUP(hw->mac.type);
4427 if (filter_op == RTE_ETH_FILTER_NOP)
4431 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4436 switch (filter_op) {
4437 case RTE_ETH_FILTER_ADD:
4438 ret = igb_add_del_ntuple_filter(dev,
4439 (struct rte_eth_ntuple_filter *)arg,
4442 case RTE_ETH_FILTER_DELETE:
4443 ret = igb_add_del_ntuple_filter(dev,
4444 (struct rte_eth_ntuple_filter *)arg,
4447 case RTE_ETH_FILTER_GET:
4448 ret = igb_get_ntuple_filter(dev,
4449 (struct rte_eth_ntuple_filter *)arg);
4452 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4460 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4465 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4466 if (filter_info->ethertype_filters[i] == ethertype &&
4467 (filter_info->ethertype_mask & (1 << i)))
4474 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4479 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4480 if (!(filter_info->ethertype_mask & (1 << i))) {
4481 filter_info->ethertype_mask |= 1 << i;
4482 filter_info->ethertype_filters[i] = ethertype;
4490 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4493 if (idx >= E1000_MAX_ETQF_FILTERS)
4495 filter_info->ethertype_mask &= ~(1 << idx);
4496 filter_info->ethertype_filters[idx] = 0;
4502 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4503 struct rte_eth_ethertype_filter *filter,
4506 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4507 struct e1000_filter_info *filter_info =
4508 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4512 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4513 filter->ether_type == ETHER_TYPE_IPv6) {
4514 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4515 " ethertype filter.", filter->ether_type);
4519 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4520 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4523 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4524 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4528 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4529 if (ret >= 0 && add) {
4530 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4531 filter->ether_type);
4534 if (ret < 0 && !add) {
4535 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4536 filter->ether_type);
4541 ret = igb_ethertype_filter_insert(filter_info,
4542 filter->ether_type);
4544 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4548 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4549 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4550 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4552 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4556 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4557 E1000_WRITE_FLUSH(hw);
4563 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4564 struct rte_eth_ethertype_filter *filter)
4566 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4567 struct e1000_filter_info *filter_info =
4568 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4572 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4574 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4575 filter->ether_type);
4579 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4580 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4581 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4583 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4584 E1000_ETQF_QUEUE_SHIFT;
4592 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4593 * @dev: pointer to rte_eth_dev structure
4594 * @filter_op:operation will be taken.
4595 * @arg: a pointer to specific structure corresponding to the filter_op
4598 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4599 enum rte_filter_op filter_op,
4602 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4605 MAC_TYPE_FILTER_SUP(hw->mac.type);
4607 if (filter_op == RTE_ETH_FILTER_NOP)
4611 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4616 switch (filter_op) {
4617 case RTE_ETH_FILTER_ADD:
4618 ret = igb_add_del_ethertype_filter(dev,
4619 (struct rte_eth_ethertype_filter *)arg,
4622 case RTE_ETH_FILTER_DELETE:
4623 ret = igb_add_del_ethertype_filter(dev,
4624 (struct rte_eth_ethertype_filter *)arg,
4627 case RTE_ETH_FILTER_GET:
4628 ret = igb_get_ethertype_filter(dev,
4629 (struct rte_eth_ethertype_filter *)arg);
4632 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4640 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4641 enum rte_filter_type filter_type,
4642 enum rte_filter_op filter_op,
4647 switch (filter_type) {
4648 case RTE_ETH_FILTER_NTUPLE:
4649 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4651 case RTE_ETH_FILTER_ETHERTYPE:
4652 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4654 case RTE_ETH_FILTER_SYN:
4655 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4657 case RTE_ETH_FILTER_FLEXIBLE:
4658 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4661 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4670 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4671 struct ether_addr *mc_addr_set,
4672 uint32_t nb_mc_addr)
4674 struct e1000_hw *hw;
4676 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4682 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4684 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4685 uint64_t systime_cycles;
4687 switch (hw->mac.type) {
4691 * Need to read System Time Residue Register to be able
4692 * to read the other two registers.
4694 E1000_READ_REG(hw, E1000_SYSTIMR);
4695 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4696 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4697 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4704 * Need to read System Time Residue Register to be able
4705 * to read the other two registers.
4707 E1000_READ_REG(hw, E1000_SYSTIMR);
4708 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4709 /* Only the 8 LSB are valid. */
4710 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4714 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4715 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4720 return systime_cycles;
4724 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4726 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4727 uint64_t rx_tstamp_cycles;
4729 switch (hw->mac.type) {
4732 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4733 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4734 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4740 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4741 /* Only the 8 LSB are valid. */
4742 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4746 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4747 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4752 return rx_tstamp_cycles;
4756 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4758 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4759 uint64_t tx_tstamp_cycles;
4761 switch (hw->mac.type) {
4764 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4765 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4766 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4772 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4773 /* Only the 8 LSB are valid. */
4774 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4778 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4779 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4784 return tx_tstamp_cycles;
4788 igb_start_timecounters(struct rte_eth_dev *dev)
4790 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4791 struct e1000_adapter *adapter =
4792 (struct e1000_adapter *)dev->data->dev_private;
4793 uint32_t incval = 1;
4795 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4797 switch (hw->mac.type) {
4801 /* 32 LSB bits + 8 MSB bits = 40 bits */
4802 mask = (1ULL << 40) - 1;
4807 * Start incrementing the register
4808 * used to timestamp PTP packets.
4810 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4813 incval = E1000_INCVALUE_82576;
4814 shift = IGB_82576_TSYNC_SHIFT;
4815 E1000_WRITE_REG(hw, E1000_TIMINCA,
4816 E1000_INCPERIOD_82576 | incval);
4823 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4824 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4825 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4827 adapter->systime_tc.cc_mask = mask;
4828 adapter->systime_tc.cc_shift = shift;
4829 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4831 adapter->rx_tstamp_tc.cc_mask = mask;
4832 adapter->rx_tstamp_tc.cc_shift = shift;
4833 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4835 adapter->tx_tstamp_tc.cc_mask = mask;
4836 adapter->tx_tstamp_tc.cc_shift = shift;
4837 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4841 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4843 struct e1000_adapter *adapter =
4844 (struct e1000_adapter *)dev->data->dev_private;
4846 adapter->systime_tc.nsec += delta;
4847 adapter->rx_tstamp_tc.nsec += delta;
4848 adapter->tx_tstamp_tc.nsec += delta;
4854 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4857 struct e1000_adapter *adapter =
4858 (struct e1000_adapter *)dev->data->dev_private;
4860 ns = rte_timespec_to_ns(ts);
4862 /* Set the timecounters to a new value. */
4863 adapter->systime_tc.nsec = ns;
4864 adapter->rx_tstamp_tc.nsec = ns;
4865 adapter->tx_tstamp_tc.nsec = ns;
4871 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4873 uint64_t ns, systime_cycles;
4874 struct e1000_adapter *adapter =
4875 (struct e1000_adapter *)dev->data->dev_private;
4877 systime_cycles = igb_read_systime_cyclecounter(dev);
4878 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4879 *ts = rte_ns_to_timespec(ns);
4885 igb_timesync_enable(struct rte_eth_dev *dev)
4887 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4891 /* Stop the timesync system time. */
4892 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4893 /* Reset the timesync system time value. */
4894 switch (hw->mac.type) {
4900 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4903 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4904 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4907 /* Not supported. */
4911 /* Enable system time for it isn't on by default. */
4912 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4913 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4914 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4916 igb_start_timecounters(dev);
4918 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4919 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4921 E1000_ETQF_FILTER_ENABLE |
4924 /* Enable timestamping of received PTP packets. */
4925 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4926 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4927 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4929 /* Enable Timestamping of transmitted PTP packets. */
4930 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4931 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4932 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4938 igb_timesync_disable(struct rte_eth_dev *dev)
4940 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4943 /* Disable timestamping of transmitted PTP packets. */
4944 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4945 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4946 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4948 /* Disable timestamping of received PTP packets. */
4949 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4950 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4951 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4953 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4954 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4956 /* Stop incrementating the System Time registers. */
4957 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4963 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4964 struct timespec *timestamp,
4965 uint32_t flags __rte_unused)
4967 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4968 struct e1000_adapter *adapter =
4969 (struct e1000_adapter *)dev->data->dev_private;
4970 uint32_t tsync_rxctl;
4971 uint64_t rx_tstamp_cycles;
4974 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4975 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4978 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4979 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4980 *timestamp = rte_ns_to_timespec(ns);
4986 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4987 struct timespec *timestamp)
4989 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4990 struct e1000_adapter *adapter =
4991 (struct e1000_adapter *)dev->data->dev_private;
4992 uint32_t tsync_txctl;
4993 uint64_t tx_tstamp_cycles;
4996 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4997 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5000 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5001 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5002 *timestamp = rte_ns_to_timespec(ns);
5008 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5012 const struct reg_info *reg_group;
5014 while ((reg_group = igb_regs[g_ind++]))
5015 count += igb_reg_group_count(reg_group);
5021 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5025 const struct reg_info *reg_group;
5027 while ((reg_group = igbvf_regs[g_ind++]))
5028 count += igb_reg_group_count(reg_group);
5034 eth_igb_get_regs(struct rte_eth_dev *dev,
5035 struct rte_dev_reg_info *regs)
5037 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5038 uint32_t *data = regs->data;
5041 const struct reg_info *reg_group;
5044 regs->length = eth_igb_get_reg_length(dev);
5045 regs->width = sizeof(uint32_t);
5049 /* Support only full register dump */
5050 if ((regs->length == 0) ||
5051 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5052 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5054 while ((reg_group = igb_regs[g_ind++]))
5055 count += igb_read_regs_group(dev, &data[count],
5064 igbvf_get_regs(struct rte_eth_dev *dev,
5065 struct rte_dev_reg_info *regs)
5067 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5068 uint32_t *data = regs->data;
5071 const struct reg_info *reg_group;
5074 regs->length = igbvf_get_reg_length(dev);
5075 regs->width = sizeof(uint32_t);
5079 /* Support only full register dump */
5080 if ((regs->length == 0) ||
5081 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5082 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5084 while ((reg_group = igbvf_regs[g_ind++]))
5085 count += igb_read_regs_group(dev, &data[count],
5094 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5096 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5098 /* Return unit is byte count */
5099 return hw->nvm.word_size * 2;
5103 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5104 struct rte_dev_eeprom_info *in_eeprom)
5106 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5107 struct e1000_nvm_info *nvm = &hw->nvm;
5108 uint16_t *data = in_eeprom->data;
5111 first = in_eeprom->offset >> 1;
5112 length = in_eeprom->length >> 1;
5113 if ((first >= hw->nvm.word_size) ||
5114 ((first + length) >= hw->nvm.word_size))
5117 in_eeprom->magic = hw->vendor_id |
5118 ((uint32_t)hw->device_id << 16);
5120 if ((nvm->ops.read) == NULL)
5123 return nvm->ops.read(hw, first, length, data);
5127 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5128 struct rte_dev_eeprom_info *in_eeprom)
5130 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131 struct e1000_nvm_info *nvm = &hw->nvm;
5132 uint16_t *data = in_eeprom->data;
5135 first = in_eeprom->offset >> 1;
5136 length = in_eeprom->length >> 1;
5137 if ((first >= hw->nvm.word_size) ||
5138 ((first + length) >= hw->nvm.word_size))
5141 in_eeprom->magic = (uint32_t)hw->vendor_id |
5142 ((uint32_t)hw->device_id << 16);
5144 if ((nvm->ops.write) == NULL)
5146 return nvm->ops.write(hw, first, length, data);
5150 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5152 struct e1000_hw *hw =
5153 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5154 uint32_t mask = 1 << queue_id;
5156 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5157 E1000_WRITE_FLUSH(hw);
5163 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5165 struct e1000_hw *hw =
5166 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5167 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5168 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5169 uint32_t mask = 1 << queue_id;
5172 regval = E1000_READ_REG(hw, E1000_EIMS);
5173 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5174 E1000_WRITE_FLUSH(hw);
5176 rte_intr_enable(intr_handle);
5182 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5183 uint8_t index, uint8_t offset)
5185 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5188 val &= ~((uint32_t)0xFF << offset);
5190 /* write vector and valid bit */
5191 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5193 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5197 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5198 uint8_t queue, uint8_t msix_vector)
5202 if (hw->mac.type == e1000_82575) {
5204 tmp = E1000_EICR_RX_QUEUE0 << queue;
5205 else if (direction == 1)
5206 tmp = E1000_EICR_TX_QUEUE0 << queue;
5207 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5208 } else if (hw->mac.type == e1000_82576) {
5209 if ((direction == 0) || (direction == 1))
5210 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5211 ((queue & 0x8) << 1) +
5213 } else if ((hw->mac.type == e1000_82580) ||
5214 (hw->mac.type == e1000_i350) ||
5215 (hw->mac.type == e1000_i354) ||
5216 (hw->mac.type == e1000_i210) ||
5217 (hw->mac.type == e1000_i211)) {
5218 if ((direction == 0) || (direction == 1))
5219 eth_igb_write_ivar(hw, msix_vector,
5221 ((queue & 0x1) << 4) +
5226 /* Sets up the hardware to generate MSI-X interrupts properly
5228 * board private structure
5231 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5234 uint32_t tmpval, regval, intr_mask;
5235 struct e1000_hw *hw =
5236 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5237 uint32_t vec = E1000_MISC_VEC_ID;
5238 uint32_t base = E1000_MISC_VEC_ID;
5239 uint32_t misc_shift = 0;
5240 struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5241 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5243 /* won't configure msix register if no mapping is done
5244 * between intr vector and event fd
5246 if (!rte_intr_dp_is_en(intr_handle))
5249 if (rte_intr_allow_others(intr_handle)) {
5250 vec = base = E1000_RX_VEC_START;
5254 /* set interrupt vector for other causes */
5255 if (hw->mac.type == e1000_82575) {
5256 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5257 /* enable MSI-X PBA support */
5258 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5260 /* Auto-Mask interrupts upon ICR read */
5261 tmpval |= E1000_CTRL_EXT_EIAME;
5262 tmpval |= E1000_CTRL_EXT_IRCA;
5264 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5266 /* enable msix_other interrupt */
5267 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5268 regval = E1000_READ_REG(hw, E1000_EIAC);
5269 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5270 regval = E1000_READ_REG(hw, E1000_EIAM);
5271 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5272 } else if ((hw->mac.type == e1000_82576) ||
5273 (hw->mac.type == e1000_82580) ||
5274 (hw->mac.type == e1000_i350) ||
5275 (hw->mac.type == e1000_i354) ||
5276 (hw->mac.type == e1000_i210) ||
5277 (hw->mac.type == e1000_i211)) {
5278 /* turn on MSI-X capability first */
5279 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5280 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5282 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5284 regval = E1000_READ_REG(hw, E1000_EIAC);
5285 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5287 /* enable msix_other interrupt */
5288 regval = E1000_READ_REG(hw, E1000_EIMS);
5289 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5290 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5291 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5294 /* use EIAM to auto-mask when MSI-X interrupt
5295 * is asserted, this saves a register write for every interrupt
5297 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5299 regval = E1000_READ_REG(hw, E1000_EIAM);
5300 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5302 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5303 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5304 intr_handle->intr_vec[queue_id] = vec;
5305 if (vec < base + intr_handle->nb_efd - 1)
5309 E1000_WRITE_FLUSH(hw);
5312 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd.pci_drv);
5313 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5314 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio");
5315 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd.pci_drv);
5316 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5317 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio");