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34 #ifndef _ENA_ETH_IO_H_
35 #define _ENA_ETH_IO_H_
37 enum ena_eth_io_l3_proto_index {
38 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0,
40 ENA_ETH_IO_L3_PROTO_IPV4 = 8,
42 ENA_ETH_IO_L3_PROTO_IPV6 = 11,
44 ENA_ETH_IO_L3_PROTO_FCOE = 21,
46 ENA_ETH_IO_L3_PROTO_ROCE = 22,
49 enum ena_eth_io_l4_proto_index {
50 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0,
52 ENA_ETH_IO_L4_PROTO_TCP = 12,
54 ENA_ETH_IO_L4_PROTO_UDP = 13,
56 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
59 struct ena_eth_io_tx_desc {
60 /* 15:0 : length - Buffer length in bytes, must
61 * include any packet trailers that the ENA supposed
62 * to update like End-to-End CRC, Authentication GMAC
63 * etc. This length must not include the
64 * 'Push_Buffer' length. This length must not include
65 * the 4-byte added in the end for 802.3 Ethernet FCS
66 * 21:16 : req_id_hi - Request ID[15:10]
67 * 22 : reserved22 - MBZ
68 * 23 : meta_desc - MBZ
70 * 25 : reserved1 - MBZ
71 * 26 : first - Indicates first descriptor in
73 * 27 : last - Indicates last descriptor in
75 * 28 : comp_req - Indicates whether completion
76 * should be posted, after packet is transmitted.
77 * Valid only for first descriptor
78 * 30:29 : reserved29 - MBZ
79 * 31 : reserved31 - MBZ
83 /* 3:0 : l3_proto_idx - L3 protocol. This field
84 * required when l3_csum_en,l3_csum or tso_en are set.
85 * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and
86 * DF flags of the IPv4 header is 0. Otherwise must
89 * 7 : tso_en - Enable TSO, For TCP only.
90 * 12:8 : l4_proto_idx - L4 protocol. This field need
91 * to be set when l4_csum_en or tso_en are set.
92 * 13 : l3_csum_en - enable IPv4 header checksum.
93 * 14 : l4_csum_en - enable TCP/UDP checksum.
94 * 15 : ethernet_fcs_dis - when set, the controller
95 * will not append the 802.3 Ethernet Frame Check
96 * Sequence to the packet
98 * 17 : l4_csum_partial - L4 partial checksum. when
99 * set to 0, the ENA calculates the L4 checksum,
100 * where the Destination Address required for the
101 * TCP/UDP pseudo-header is taken from the actual
102 * packet L3 header. when set to 1, the ENA doesn't
103 * calculate the sum of the pseudo-header, instead,
104 * the checksum field of the L4 is used instead. When
105 * TSO enabled, the checksum of the pseudo-header
106 * must not include the tcp length field. L4 partial
107 * checksum should be used for IPv6 packet that
108 * contains Routing Headers.
109 * 20:18 : reserved18 - MBZ
110 * 21 : reserved21 - MBZ
111 * 31:22 : req_id_lo - Request ID[9:0]
115 uint32_t buff_addr_lo;
117 /* address high and header size
118 * 15:0 : addr_hi - Buffer Pointer[47:32]
119 * 23:16 : reserved16_w2
120 * 31:24 : header_length - Header length. For Low
121 * Latency Queues, this fields indicates the number
122 * of bytes written to the headers' memory. For
123 * normal queues, if packet is TCP or UDP, and longer
124 * than max_header_size, then this field should be
125 * set to the sum of L4 header offset and L4 header
126 * size(without options), otherwise, this field
127 * should be set to 0. For both modes, this field
128 * must not exceed the max_header_size.
129 * max_header_size value is reported by the Max
130 * Queues Feature descriptor
132 uint32_t buff_addr_hi_hdr_sz;
135 struct ena_eth_io_tx_meta_desc {
136 /* 9:0 : req_id_lo - Request ID[9:0]
137 * 11:10 : reserved10 - MBZ
138 * 12 : reserved12 - MBZ
139 * 13 : reserved13 - MBZ
140 * 14 : ext_valid - if set, offset fields in Word2
141 * are valid Also MSS High in Word 0 and bits [31:24]
145 * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1:
146 * Extended Metadata Descriptor
147 * 21 : meta_store - Store extended metadata in queue
149 * 22 : reserved22 - MBZ
150 * 23 : meta_desc - MBO
152 * 25 : reserved25 - MBZ
153 * 26 : first - Indicates first descriptor in
155 * 27 : last - Indicates last descriptor in
157 * 28 : comp_req - Indicates whether completion
158 * should be posted, after packet is transmitted.
159 * Valid only for first descriptor
160 * 30:29 : reserved29 - MBZ
161 * 31 : reserved31 - MBZ
166 * 31:6 : reserved6 - MBZ
172 * 21:16 : l4_hdr_len_in_words - counts the L4 header
173 * length in words. there is an explicit assumption
174 * that L4 header appears right after L3 header and
175 * L4 offset is based on l3_hdr_off+l3_hdr_len
183 struct ena_eth_io_tx_cdesc {
184 /* Request ID[15:0] */
197 uint16_t sq_head_idx;
200 struct ena_eth_io_rx_desc {
201 /* In bytes. 0 means 64KB */
208 * 1 : reserved1 - MBZ
209 * 2 : first - Indicates first descriptor in
211 * 3 : last - Indicates last descriptor in transaction
213 * 5 : reserved5 - MBO
214 * 7:6 : reserved6 - MBZ
223 uint32_t buff_addr_lo;
225 uint16_t buff_addr_hi;
228 uint16_t reserved16_w3;
231 /* 4-word format Note: all ethernet parsing information are valid only when
234 struct ena_eth_io_rx_cdesc_base {
235 /* 4:0 : l3_proto_idx
237 * 7 : reserved7 - MBZ
238 * 12:8 : l4_proto_idx
239 * 13 : l3_csum_err - when set, either the L3
240 * checksum error detected, or, the controller didn't
241 * validate the checksum. This bit is valid only when
242 * l3_proto_idx indicates IPv4 packet
243 * 14 : l4_csum_err - when set, either the L4
244 * checksum error detected, or, the controller didn't
245 * validate the checksum. This bit is valid only when
246 * l4_proto_idx indicates TCP/UDP packet, and,
247 * ipv4_frag is not set
248 * 15 : ipv4_frag - Indicates IPv4 fragmented packet
251 * 25 : l3_csum2 - second checksum engine result
252 * 26 : first - Indicates first descriptor in
254 * 27 : last - Indicates last descriptor in
257 * 30 : buffer - 0: Metadata descriptor. 1: Buffer
258 * Descriptor was used
267 /* 32-bit hash result */
276 struct ena_eth_io_rx_cdesc_ext {
277 struct ena_eth_io_rx_cdesc_base base;
279 uint32_t buff_addr_lo;
281 uint16_t buff_addr_hi;
285 uint32_t reserved_w6;
287 uint32_t reserved_w7;
290 struct ena_eth_io_intr_reg {
291 /* 14:0 : rx_intr_delay
292 * 29:15 : tx_intr_delay
296 uint32_t intr_control;
299 struct ena_eth_io_numa_node_cfg_reg {
308 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
309 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
310 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
311 #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
312 #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
313 #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
314 #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
315 #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
316 #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
317 #define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
318 #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
319 #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
320 #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
321 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
322 #define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
323 #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
324 #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
325 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
326 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
327 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
328 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
329 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
330 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
331 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
332 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
333 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
334 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
335 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
336 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
337 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
338 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
339 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
340 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
343 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
344 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
345 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
346 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16
347 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
348 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
349 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
350 #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
351 #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
352 #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
353 #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
354 #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
355 #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
356 #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
357 #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
358 #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
359 #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
360 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
361 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
362 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
363 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
364 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
365 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
366 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
367 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
368 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
369 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
372 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
375 #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
376 #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
377 #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
378 #define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
379 #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
380 #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
381 #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
384 #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
385 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
386 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
387 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
388 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
389 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
390 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
391 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
392 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
393 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
394 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
395 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
396 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
397 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
398 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
399 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
400 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
401 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
402 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
403 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
404 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
407 #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
408 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
409 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
410 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
411 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
413 /* numa_node_cfg_reg */
414 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
415 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
416 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
418 #if !defined(ENA_DEFS_LINUX_MAINLINE)
419 static inline uint32_t get_ena_eth_io_tx_desc_length(const struct ena_eth_io_tx_desc *p)
421 return p->len_ctrl & ENA_ETH_IO_TX_DESC_LENGTH_MASK;
424 static inline void set_ena_eth_io_tx_desc_length(struct ena_eth_io_tx_desc *p, uint32_t val)
426 p->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK;
429 static inline uint32_t get_ena_eth_io_tx_desc_req_id_hi(const struct ena_eth_io_tx_desc *p)
431 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT;
434 static inline void set_ena_eth_io_tx_desc_req_id_hi(struct ena_eth_io_tx_desc *p, uint32_t val)
436 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK;
439 static inline uint32_t get_ena_eth_io_tx_desc_meta_desc(const struct ena_eth_io_tx_desc *p)
441 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_DESC_META_DESC_SHIFT;
444 static inline void set_ena_eth_io_tx_desc_meta_desc(struct ena_eth_io_tx_desc *p, uint32_t val)
446 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_DESC_META_DESC_MASK;
449 static inline uint32_t get_ena_eth_io_tx_desc_phase(const struct ena_eth_io_tx_desc *p)
451 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_DESC_PHASE_SHIFT;
454 static inline void set_ena_eth_io_tx_desc_phase(struct ena_eth_io_tx_desc *p, uint32_t val)
456 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_DESC_PHASE_MASK;
459 static inline uint32_t get_ena_eth_io_tx_desc_first(const struct ena_eth_io_tx_desc *p)
461 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_DESC_FIRST_SHIFT;
464 static inline void set_ena_eth_io_tx_desc_first(struct ena_eth_io_tx_desc *p, uint32_t val)
466 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_DESC_FIRST_MASK;
469 static inline uint32_t get_ena_eth_io_tx_desc_last(const struct ena_eth_io_tx_desc *p)
471 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_LAST_MASK) >> ENA_ETH_IO_TX_DESC_LAST_SHIFT;
474 static inline void set_ena_eth_io_tx_desc_last(struct ena_eth_io_tx_desc *p, uint32_t val)
476 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_DESC_LAST_MASK;
479 static inline uint32_t get_ena_eth_io_tx_desc_comp_req(const struct ena_eth_io_tx_desc *p)
481 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT;
484 static inline void set_ena_eth_io_tx_desc_comp_req(struct ena_eth_io_tx_desc *p, uint32_t val)
486 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK;
489 static inline uint32_t get_ena_eth_io_tx_desc_l3_proto_idx(const struct ena_eth_io_tx_desc *p)
491 return p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;
494 static inline void set_ena_eth_io_tx_desc_l3_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val)
496 p->meta_ctrl |= val & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;
499 static inline uint32_t get_ena_eth_io_tx_desc_DF(const struct ena_eth_io_tx_desc *p)
501 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_DF_MASK) >> ENA_ETH_IO_TX_DESC_DF_SHIFT;
504 static inline void set_ena_eth_io_tx_desc_DF(struct ena_eth_io_tx_desc *p, uint32_t val)
506 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_DF_SHIFT) & ENA_ETH_IO_TX_DESC_DF_MASK;
509 static inline uint32_t get_ena_eth_io_tx_desc_tso_en(const struct ena_eth_io_tx_desc *p)
511 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TSO_EN_MASK) >> ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT;
514 static inline void set_ena_eth_io_tx_desc_tso_en(struct ena_eth_io_tx_desc *p, uint32_t val)
516 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) & ENA_ETH_IO_TX_DESC_TSO_EN_MASK;
519 static inline uint32_t get_ena_eth_io_tx_desc_l4_proto_idx(const struct ena_eth_io_tx_desc *p)
521 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT;
524 static inline void set_ena_eth_io_tx_desc_l4_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val)
526 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK;
529 static inline uint32_t get_ena_eth_io_tx_desc_l3_csum_en(const struct ena_eth_io_tx_desc *p)
531 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT;
534 static inline void set_ena_eth_io_tx_desc_l3_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val)
536 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK;
539 static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_en(const struct ena_eth_io_tx_desc *p)
541 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT;
544 static inline void set_ena_eth_io_tx_desc_l4_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val)
546 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK;
549 static inline uint32_t get_ena_eth_io_tx_desc_ethernet_fcs_dis(const struct ena_eth_io_tx_desc *p)
551 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK) >> ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT;
554 static inline void set_ena_eth_io_tx_desc_ethernet_fcs_dis(struct ena_eth_io_tx_desc *p, uint32_t val)
556 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT) & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK;
559 static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_partial(const struct ena_eth_io_tx_desc *p)
561 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT;
564 static inline void set_ena_eth_io_tx_desc_l4_csum_partial(struct ena_eth_io_tx_desc *p, uint32_t val)
566 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK;
569 static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(const struct ena_eth_io_tx_desc *p)
571 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT;
574 static inline void set_ena_eth_io_tx_desc_req_id_lo(struct ena_eth_io_tx_desc *p, uint32_t val)
576 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;
579 static inline uint32_t get_ena_eth_io_tx_desc_addr_hi(const struct ena_eth_io_tx_desc *p)
581 return p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;
584 static inline void set_ena_eth_io_tx_desc_addr_hi(struct ena_eth_io_tx_desc *p, uint32_t val)
586 p->buff_addr_hi_hdr_sz |= val & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;
589 static inline uint32_t get_ena_eth_io_tx_desc_header_length(const struct ena_eth_io_tx_desc *p)
591 return (p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK) >> ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT;
594 static inline void set_ena_eth_io_tx_desc_header_length(struct ena_eth_io_tx_desc *p, uint32_t val)
596 p->buff_addr_hi_hdr_sz |= (val << ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK;
599 static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_lo(const struct ena_eth_io_tx_meta_desc *p)
601 return p->len_ctrl & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK;
604 static inline void set_ena_eth_io_tx_meta_desc_req_id_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
606 p->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK;
609 static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(const struct ena_eth_io_tx_meta_desc *p)
611 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK) >> ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT;
614 static inline void set_ena_eth_io_tx_meta_desc_ext_valid(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
616 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT) & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;
619 static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_hi(const struct ena_eth_io_tx_meta_desc *p)
621 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT;
624 static inline void set_ena_eth_io_tx_meta_desc_mss_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
626 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK;
629 static inline uint32_t get_ena_eth_io_tx_meta_desc_eth_meta_type(const struct ena_eth_io_tx_meta_desc *p)
631 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK) >> ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT;
634 static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
636 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT) & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;
639 static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_store(const struct ena_eth_io_tx_meta_desc *p)
641 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK) >> ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT;
644 static inline void set_ena_eth_io_tx_meta_desc_meta_store(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
646 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK;
649 static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_desc(const struct ena_eth_io_tx_meta_desc *p)
651 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT;
654 static inline void set_ena_eth_io_tx_meta_desc_meta_desc(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
656 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK;
659 static inline uint32_t get_ena_eth_io_tx_meta_desc_phase(const struct ena_eth_io_tx_meta_desc *p)
661 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT;
664 static inline void set_ena_eth_io_tx_meta_desc_phase(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
666 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_META_DESC_PHASE_MASK;
669 static inline uint32_t get_ena_eth_io_tx_meta_desc_first(const struct ena_eth_io_tx_meta_desc *p)
671 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT;
674 static inline void set_ena_eth_io_tx_meta_desc_first(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
676 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_META_DESC_FIRST_MASK;
679 static inline uint32_t get_ena_eth_io_tx_meta_desc_last(const struct ena_eth_io_tx_meta_desc *p)
681 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_LAST_MASK) >> ENA_ETH_IO_TX_META_DESC_LAST_SHIFT;
684 static inline void set_ena_eth_io_tx_meta_desc_last(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
686 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_META_DESC_LAST_MASK;
689 static inline uint32_t get_ena_eth_io_tx_meta_desc_comp_req(const struct ena_eth_io_tx_meta_desc *p)
691 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT;
694 static inline void set_ena_eth_io_tx_meta_desc_comp_req(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
696 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK;
699 static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_hi(const struct ena_eth_io_tx_meta_desc *p)
701 return p->word1 & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK;
704 static inline void set_ena_eth_io_tx_meta_desc_req_id_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
706 p->word1 |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK;
709 static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_len(const struct ena_eth_io_tx_meta_desc *p)
711 return p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;
714 static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_len(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
716 p->word2 |= val & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;
719 static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_off(const struct ena_eth_io_tx_meta_desc *p)
721 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK) >> ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT;
724 static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_off(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
726 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK;
729 static inline uint32_t get_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(const struct ena_eth_io_tx_meta_desc *p)
731 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK) >> ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT;
734 static inline void set_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
736 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK;
739 static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_lo(const struct ena_eth_io_tx_meta_desc *p)
741 return (p->word2 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT;
744 static inline void set_ena_eth_io_tx_meta_desc_mss_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
746 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;
749 static inline uint8_t get_ena_eth_io_tx_cdesc_phase(const struct ena_eth_io_tx_cdesc *p)
751 return p->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
754 static inline void set_ena_eth_io_tx_cdesc_phase(struct ena_eth_io_tx_cdesc *p, uint8_t val)
756 p->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
759 static inline uint8_t get_ena_eth_io_rx_desc_phase(const struct ena_eth_io_rx_desc *p)
761 return p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK;
764 static inline void set_ena_eth_io_rx_desc_phase(struct ena_eth_io_rx_desc *p, uint8_t val)
766 p->ctrl |= val & ENA_ETH_IO_RX_DESC_PHASE_MASK;
769 static inline uint8_t get_ena_eth_io_rx_desc_first(const struct ena_eth_io_rx_desc *p)
771 return (p->ctrl & ENA_ETH_IO_RX_DESC_FIRST_MASK) >> ENA_ETH_IO_RX_DESC_FIRST_SHIFT;
774 static inline void set_ena_eth_io_rx_desc_first(struct ena_eth_io_rx_desc *p, uint8_t val)
776 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_FIRST_SHIFT) & ENA_ETH_IO_RX_DESC_FIRST_MASK;
779 static inline uint8_t get_ena_eth_io_rx_desc_last(const struct ena_eth_io_rx_desc *p)
781 return (p->ctrl & ENA_ETH_IO_RX_DESC_LAST_MASK) >> ENA_ETH_IO_RX_DESC_LAST_SHIFT;
784 static inline void set_ena_eth_io_rx_desc_last(struct ena_eth_io_rx_desc *p, uint8_t val)
786 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_LAST_SHIFT) & ENA_ETH_IO_RX_DESC_LAST_MASK;
789 static inline uint8_t get_ena_eth_io_rx_desc_comp_req(const struct ena_eth_io_rx_desc *p)
791 return (p->ctrl & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT;
794 static inline void set_ena_eth_io_rx_desc_comp_req(struct ena_eth_io_rx_desc *p, uint8_t val)
796 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;
799 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_proto_idx(const struct ena_eth_io_rx_cdesc_base *p)
801 return p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
804 static inline void set_ena_eth_io_rx_cdesc_base_l3_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
806 p->status |= val & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
809 static inline uint32_t get_ena_eth_io_rx_cdesc_base_src_vlan_cnt(const struct ena_eth_io_rx_cdesc_base *p)
811 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT;
814 static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
816 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK;
819 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(const struct ena_eth_io_rx_cdesc_base *p)
821 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;
824 static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
826 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK;
829 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum_err(const struct ena_eth_io_rx_cdesc_base *p)
831 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT;
834 static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
836 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK;
839 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_err(const struct ena_eth_io_rx_cdesc_base *p)
841 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT;
844 static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
846 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK;
849 static inline uint32_t get_ena_eth_io_rx_cdesc_base_ipv4_frag(const struct ena_eth_io_rx_cdesc_base *p)
851 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;
854 static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
856 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK;
859 static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p)
861 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;
864 static inline void set_ena_eth_io_rx_cdesc_base_phase(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
866 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK;
869 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum2(const struct ena_eth_io_rx_cdesc_base *p)
871 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT;
874 static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
876 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK;
879 static inline uint32_t get_ena_eth_io_rx_cdesc_base_first(const struct ena_eth_io_rx_cdesc_base *p)
881 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT;
884 static inline void set_ena_eth_io_rx_cdesc_base_first(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
886 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK;
889 static inline uint32_t get_ena_eth_io_rx_cdesc_base_last(const struct ena_eth_io_rx_cdesc_base *p)
891 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT;
894 static inline void set_ena_eth_io_rx_cdesc_base_last(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
896 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK;
899 static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(const struct ena_eth_io_rx_cdesc_base *p)
901 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT;
904 static inline void set_ena_eth_io_rx_cdesc_base_buffer(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
906 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK;
909 static inline uint32_t get_ena_eth_io_intr_reg_rx_intr_delay(const struct ena_eth_io_intr_reg *p)
911 return p->intr_control & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
914 static inline void set_ena_eth_io_intr_reg_rx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val)
916 p->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
919 static inline uint32_t get_ena_eth_io_intr_reg_tx_intr_delay(const struct ena_eth_io_intr_reg *p)
921 return (p->intr_control & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK) >> ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT;
924 static inline void set_ena_eth_io_intr_reg_tx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val)
926 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
929 static inline uint32_t get_ena_eth_io_intr_reg_intr_unmask(const struct ena_eth_io_intr_reg *p)
931 return (p->intr_control & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK) >> ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT;
934 static inline void set_ena_eth_io_intr_reg_intr_unmask(struct ena_eth_io_intr_reg *p, uint32_t val)
936 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT) & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
939 static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(const struct ena_eth_io_numa_node_cfg_reg *p)
941 return p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;
944 static inline void set_ena_eth_io_numa_node_cfg_reg_numa(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)
946 p->numa_cfg |= val & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;
949 static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_enabled(const struct ena_eth_io_numa_node_cfg_reg *p)
951 return (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK) >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT;
954 static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)
956 p->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT) & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
959 #endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */
960 #endif /*_ENA_ETH_IO_H_ */