4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ether.h>
35 #include <rte_ethdev_driver.h>
36 #include <rte_ethdev_pci.h>
38 #include <rte_atomic.h>
40 #include <rte_errno.h>
41 #include <rte_version.h>
42 #include <rte_eal_memconfig.h>
45 #include "ena_ethdev.h"
47 #include "ena_platform.h"
49 #include "ena_eth_com.h"
51 #include <ena_common_defs.h>
52 #include <ena_regs_defs.h>
53 #include <ena_admin_defs.h>
54 #include <ena_eth_io_defs.h>
56 #define DRV_MODULE_VER_MAJOR 1
57 #define DRV_MODULE_VER_MINOR 1
58 #define DRV_MODULE_VER_SUBMINOR 0
60 #define ENA_IO_TXQ_IDX(q) (2 * (q))
61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
62 /*reverse version of ENA_IO_RXQ_IDX*/
63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
65 /* While processing submitted and completed descriptors (rx and tx path
66 * respectively) in a loop it is desired to:
67 * - perform batch submissions while populating sumbissmion queue
68 * - avoid blocking transmission of other packets during cleanup phase
69 * Hence the utilization ratio of 1/8 of a queue size.
71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
76 #define GET_L4_HDR_LEN(mbuf) \
77 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \
78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
82 #define ENA_HASH_KEY_SIZE 40
83 #define ENA_ETH_SS_STATS 0xFF
84 #define ETH_GSTRING_LEN 32
86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
88 enum ethtool_stringset {
94 char name[ETH_GSTRING_LEN];
98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
100 .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
103 #define ENA_STAT_ENTRY(stat, stat_type) { \
105 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
108 #define ENA_STAT_RX_ENTRY(stat) \
109 ENA_STAT_ENTRY(stat, rx)
111 #define ENA_STAT_TX_ENTRY(stat) \
112 ENA_STAT_ENTRY(stat, tx)
114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
115 ENA_STAT_ENTRY(stat, dev)
118 * Each rte_memzone should have unique name.
119 * To satisfy it, count number of allocation and add it to name.
121 uint32_t ena_alloc_cnt;
123 static const struct ena_stats ena_stats_global_strings[] = {
124 ENA_STAT_GLOBAL_ENTRY(tx_timeout),
125 ENA_STAT_GLOBAL_ENTRY(io_suspend),
126 ENA_STAT_GLOBAL_ENTRY(io_resume),
127 ENA_STAT_GLOBAL_ENTRY(wd_expired),
128 ENA_STAT_GLOBAL_ENTRY(interface_up),
129 ENA_STAT_GLOBAL_ENTRY(interface_down),
130 ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
133 static const struct ena_stats ena_stats_tx_strings[] = {
134 ENA_STAT_TX_ENTRY(cnt),
135 ENA_STAT_TX_ENTRY(bytes),
136 ENA_STAT_TX_ENTRY(queue_stop),
137 ENA_STAT_TX_ENTRY(queue_wakeup),
138 ENA_STAT_TX_ENTRY(dma_mapping_err),
139 ENA_STAT_TX_ENTRY(linearize),
140 ENA_STAT_TX_ENTRY(linearize_failed),
141 ENA_STAT_TX_ENTRY(tx_poll),
142 ENA_STAT_TX_ENTRY(doorbells),
143 ENA_STAT_TX_ENTRY(prepare_ctx_err),
144 ENA_STAT_TX_ENTRY(missing_tx_comp),
145 ENA_STAT_TX_ENTRY(bad_req_id),
148 static const struct ena_stats ena_stats_rx_strings[] = {
149 ENA_STAT_RX_ENTRY(cnt),
150 ENA_STAT_RX_ENTRY(bytes),
151 ENA_STAT_RX_ENTRY(refil_partial),
152 ENA_STAT_RX_ENTRY(bad_csum),
153 ENA_STAT_RX_ENTRY(page_alloc_fail),
154 ENA_STAT_RX_ENTRY(skb_alloc_fail),
155 ENA_STAT_RX_ENTRY(dma_mapping_err),
156 ENA_STAT_RX_ENTRY(bad_desc_num),
157 ENA_STAT_RX_ENTRY(small_copy_len_pkt),
160 static const struct ena_stats ena_stats_ena_com_strings[] = {
161 ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
162 ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
163 ENA_STAT_ENA_COM_ENTRY(completed_cmd),
164 ENA_STAT_ENA_COM_ENTRY(out_of_space),
165 ENA_STAT_ENA_COM_ENTRY(no_completion),
168 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
169 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
170 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
171 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
173 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
174 DEV_TX_OFFLOAD_UDP_CKSUM |\
175 DEV_TX_OFFLOAD_IPV4_CKSUM |\
176 DEV_TX_OFFLOAD_TCP_TSO)
177 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
181 /** Vendor ID used by Amazon devices */
182 #define PCI_VENDOR_ID_AMAZON 0x1D0F
183 /** Amazon devices */
184 #define PCI_DEVICE_ID_ENA_VF 0xEC20
185 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
187 #define ENA_TX_OFFLOAD_MASK (\
192 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
193 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
195 int ena_logtype_init;
196 int ena_logtype_driver;
198 static const struct rte_pci_id pci_id_ena_map[] = {
199 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
200 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
204 static struct ena_aenq_handlers aenq_handlers;
206 static int ena_device_init(struct ena_com_dev *ena_dev,
207 struct ena_com_dev_get_features_ctx *get_feat_ctx,
209 static int ena_dev_configure(struct rte_eth_dev *dev);
210 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
212 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
214 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
215 uint16_t nb_desc, unsigned int socket_id,
216 const struct rte_eth_txconf *tx_conf);
217 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
218 uint16_t nb_desc, unsigned int socket_id,
219 const struct rte_eth_rxconf *rx_conf,
220 struct rte_mempool *mp);
221 static uint16_t eth_ena_recv_pkts(void *rx_queue,
222 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
223 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
224 static void ena_init_rings(struct ena_adapter *adapter);
225 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
226 static int ena_start(struct rte_eth_dev *dev);
227 static void ena_stop(struct rte_eth_dev *dev);
228 static void ena_close(struct rte_eth_dev *dev);
229 static int ena_dev_reset(struct rte_eth_dev *dev);
230 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
231 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
232 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
233 static void ena_rx_queue_release(void *queue);
234 static void ena_tx_queue_release(void *queue);
235 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
236 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
237 static int ena_link_update(struct rte_eth_dev *dev,
238 int wait_to_complete);
239 static int ena_queue_restart(struct ena_ring *ring);
240 static int ena_queue_restart_all(struct rte_eth_dev *dev,
241 enum ena_ring_type ring_type);
242 static void ena_stats_restart(struct rte_eth_dev *dev);
243 static void ena_infos_get(struct rte_eth_dev *dev,
244 struct rte_eth_dev_info *dev_info);
245 static int ena_rss_reta_update(struct rte_eth_dev *dev,
246 struct rte_eth_rss_reta_entry64 *reta_conf,
248 static int ena_rss_reta_query(struct rte_eth_dev *dev,
249 struct rte_eth_rss_reta_entry64 *reta_conf,
251 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
252 static void ena_interrupt_handler_rte(void *cb_arg);
253 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
255 static const struct eth_dev_ops ena_dev_ops = {
256 .dev_configure = ena_dev_configure,
257 .dev_infos_get = ena_infos_get,
258 .rx_queue_setup = ena_rx_queue_setup,
259 .tx_queue_setup = ena_tx_queue_setup,
260 .dev_start = ena_start,
261 .dev_stop = ena_stop,
262 .link_update = ena_link_update,
263 .stats_get = ena_stats_get,
264 .mtu_set = ena_mtu_set,
265 .rx_queue_release = ena_rx_queue_release,
266 .tx_queue_release = ena_tx_queue_release,
267 .dev_close = ena_close,
268 .dev_reset = ena_dev_reset,
269 .reta_update = ena_rss_reta_update,
270 .reta_query = ena_rss_reta_query,
273 #define NUMA_NO_NODE SOCKET_ID_ANY
275 static inline int ena_cpu_to_node(int cpu)
277 struct rte_config *config = rte_eal_get_configuration();
278 struct rte_fbarray *arr = &config->mem_config->memzones;
279 const struct rte_memzone *mz;
281 if (unlikely(cpu >= RTE_MAX_MEMZONE))
284 mz = rte_fbarray_get(arr, cpu);
286 return mz->socket_id;
289 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
290 struct ena_com_rx_ctx *ena_rx_ctx)
292 uint64_t ol_flags = 0;
293 uint32_t packet_type = 0;
295 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
296 packet_type |= RTE_PTYPE_L4_TCP;
297 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
298 packet_type |= RTE_PTYPE_L4_UDP;
300 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
301 packet_type |= RTE_PTYPE_L3_IPV4;
302 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
303 packet_type |= RTE_PTYPE_L3_IPV6;
305 if (unlikely(ena_rx_ctx->l4_csum_err))
306 ol_flags |= PKT_RX_L4_CKSUM_BAD;
307 if (unlikely(ena_rx_ctx->l3_csum_err))
308 ol_flags |= PKT_RX_IP_CKSUM_BAD;
310 mbuf->ol_flags = ol_flags;
311 mbuf->packet_type = packet_type;
314 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
315 struct ena_com_tx_ctx *ena_tx_ctx,
316 uint64_t queue_offloads)
318 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
320 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
321 (queue_offloads & QUEUE_OFFLOADS)) {
322 /* check if TSO is required */
323 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
324 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
325 ena_tx_ctx->tso_enable = true;
327 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
330 /* check if L3 checksum is needed */
331 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
332 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
333 ena_tx_ctx->l3_csum_enable = true;
335 if (mbuf->ol_flags & PKT_TX_IPV6) {
336 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
338 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
340 /* set don't fragment (DF) flag */
341 if (mbuf->packet_type &
342 (RTE_PTYPE_L4_NONFRAG
343 | RTE_PTYPE_INNER_L4_NONFRAG))
344 ena_tx_ctx->df = true;
347 /* check if L4 checksum is needed */
348 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
349 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
350 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
351 ena_tx_ctx->l4_csum_enable = true;
352 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
353 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
354 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
355 ena_tx_ctx->l4_csum_enable = true;
357 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
358 ena_tx_ctx->l4_csum_enable = false;
361 ena_meta->mss = mbuf->tso_segsz;
362 ena_meta->l3_hdr_len = mbuf->l3_len;
363 ena_meta->l3_hdr_offset = mbuf->l2_len;
365 ena_tx_ctx->meta_valid = true;
367 ena_tx_ctx->meta_valid = false;
371 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
373 if (likely(req_id < rx_ring->ring_size))
376 RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
378 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
379 rx_ring->adapter->trigger_reset = true;
384 static void ena_config_host_info(struct ena_com_dev *ena_dev)
386 struct ena_admin_host_info *host_info;
389 /* Allocate only the host info */
390 rc = ena_com_allocate_host_info(ena_dev);
392 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
396 host_info = ena_dev->host_attr.host_info;
398 host_info->os_type = ENA_ADMIN_OS_DPDK;
399 host_info->kernel_ver = RTE_VERSION;
400 snprintf((char *)host_info->kernel_ver_str,
401 sizeof(host_info->kernel_ver_str),
402 "%s", rte_version());
403 host_info->os_dist = RTE_VERSION;
404 snprintf((char *)host_info->os_dist_str,
405 sizeof(host_info->os_dist_str),
406 "%s", rte_version());
407 host_info->driver_version =
408 (DRV_MODULE_VER_MAJOR) |
409 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
410 (DRV_MODULE_VER_SUBMINOR <<
411 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
413 rc = ena_com_set_host_attributes(ena_dev);
415 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
416 if (rc != -ENA_COM_UNSUPPORTED)
423 ena_com_delete_host_info(ena_dev);
427 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
429 if (sset != ETH_SS_STATS)
432 /* Workaround for clang:
433 * touch internal structures to prevent
436 ENA_TOUCH(ena_stats_global_strings);
437 ENA_TOUCH(ena_stats_tx_strings);
438 ENA_TOUCH(ena_stats_rx_strings);
439 ENA_TOUCH(ena_stats_ena_com_strings);
441 return dev->data->nb_tx_queues *
442 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
443 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
446 static void ena_config_debug_area(struct ena_adapter *adapter)
451 ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
453 RTE_LOG(ERR, PMD, "SS count is negative\n");
457 /* allocate 32 bytes for each string and 64bit for the value */
458 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
460 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
462 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
466 rc = ena_com_set_host_attributes(&adapter->ena_dev);
468 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
469 if (rc != -ENA_COM_UNSUPPORTED)
475 ena_com_delete_debug_area(&adapter->ena_dev);
478 static void ena_close(struct rte_eth_dev *dev)
480 struct ena_adapter *adapter =
481 (struct ena_adapter *)(dev->data->dev_private);
484 adapter->state = ENA_ADAPTER_STATE_CLOSED;
486 ena_rx_queue_release_all(dev);
487 ena_tx_queue_release_all(dev);
491 ena_dev_reset(struct rte_eth_dev *dev)
493 struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
494 struct rte_eth_dev *eth_dev;
495 struct rte_pci_device *pci_dev;
496 struct rte_intr_handle *intr_handle;
497 struct ena_com_dev *ena_dev;
498 struct ena_com_dev_get_features_ctx get_feat_ctx;
499 struct ena_adapter *adapter;
504 adapter = (struct ena_adapter *)(dev->data->dev_private);
505 ena_dev = &adapter->ena_dev;
506 eth_dev = adapter->rte_dev;
507 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
508 intr_handle = &pci_dev->intr_handle;
509 nb_queues = eth_dev->data->nb_rx_queues;
511 ena_com_set_admin_running_state(ena_dev, false);
513 ena_com_dev_reset(ena_dev, adapter->reset_reason);
515 for (i = 0; i < nb_queues; i++)
516 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
518 ena_rx_queue_release_all(eth_dev);
519 ena_tx_queue_release_all(eth_dev);
521 rte_intr_disable(intr_handle);
523 ena_com_abort_admin_commands(ena_dev);
524 ena_com_wait_for_abort_completion(ena_dev);
525 ena_com_admin_destroy(ena_dev);
526 ena_com_mmio_reg_read_request_destroy(ena_dev);
528 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
530 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
533 adapter->wd_state = wd_state;
535 rte_intr_enable(intr_handle);
536 ena_com_set_admin_polling_mode(ena_dev, false);
537 ena_com_admin_aenq_enable(ena_dev);
539 for (i = 0; i < nb_queues; ++i)
540 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
543 for (i = 0; i < nb_queues; ++i)
544 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
546 adapter->trigger_reset = false;
551 static int ena_rss_reta_update(struct rte_eth_dev *dev,
552 struct rte_eth_rss_reta_entry64 *reta_conf,
555 struct ena_adapter *adapter =
556 (struct ena_adapter *)(dev->data->dev_private);
557 struct ena_com_dev *ena_dev = &adapter->ena_dev;
563 if ((reta_size == 0) || (reta_conf == NULL))
566 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
567 RTE_LOG(WARNING, PMD,
568 "indirection table %d is bigger than supported (%d)\n",
569 reta_size, ENA_RX_RSS_TABLE_SIZE);
574 for (i = 0 ; i < reta_size ; i++) {
575 /* each reta_conf is for 64 entries.
576 * to support 128 we use 2 conf of 64
578 conf_idx = i / RTE_RETA_GROUP_SIZE;
579 idx = i % RTE_RETA_GROUP_SIZE;
580 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
582 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
583 ret = ena_com_indirect_table_fill_entry(ena_dev,
586 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
588 "Cannot fill indirect table\n");
595 ret = ena_com_indirect_table_set(ena_dev);
596 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
597 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
602 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n",
603 __func__, reta_size, adapter->rte_dev->data->port_id);
608 /* Query redirection table. */
609 static int ena_rss_reta_query(struct rte_eth_dev *dev,
610 struct rte_eth_rss_reta_entry64 *reta_conf,
613 struct ena_adapter *adapter =
614 (struct ena_adapter *)(dev->data->dev_private);
615 struct ena_com_dev *ena_dev = &adapter->ena_dev;
618 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
622 if (reta_size == 0 || reta_conf == NULL ||
623 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
626 ret = ena_com_indirect_table_get(ena_dev, indirect_table);
627 if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
628 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
633 for (i = 0 ; i < reta_size ; i++) {
634 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
635 reta_idx = i % RTE_RETA_GROUP_SIZE;
636 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
637 reta_conf[reta_conf_idx].reta[reta_idx] =
638 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
644 static int ena_rss_init_default(struct ena_adapter *adapter)
646 struct ena_com_dev *ena_dev = &adapter->ena_dev;
647 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
651 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
653 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
657 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
658 val = i % nb_rx_queues;
659 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
660 ENA_IO_RXQ_IDX(val));
661 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
662 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
667 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
668 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
669 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
670 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
674 rc = ena_com_set_default_hash_ctrl(ena_dev);
675 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
676 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
680 rc = ena_com_indirect_table_set(ena_dev);
681 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
682 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
685 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
686 adapter->rte_dev->data->port_id);
691 ena_com_rss_destroy(ena_dev);
697 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
699 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
700 int nb_queues = dev->data->nb_rx_queues;
703 for (i = 0; i < nb_queues; i++)
704 ena_rx_queue_release(queues[i]);
707 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
709 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
710 int nb_queues = dev->data->nb_tx_queues;
713 for (i = 0; i < nb_queues; i++)
714 ena_tx_queue_release(queues[i]);
717 static void ena_rx_queue_release(void *queue)
719 struct ena_ring *ring = (struct ena_ring *)queue;
720 struct ena_adapter *adapter = ring->adapter;
723 ena_assert_msg(ring->configured,
724 "API violation - releasing not configured queue");
725 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
728 /* Destroy HW queue */
729 ena_qid = ENA_IO_RXQ_IDX(ring->id);
730 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
733 ena_rx_queue_release_bufs(ring);
735 /* Free ring resources */
736 if (ring->rx_buffer_info)
737 rte_free(ring->rx_buffer_info);
738 ring->rx_buffer_info = NULL;
740 if (ring->empty_rx_reqs)
741 rte_free(ring->empty_rx_reqs);
742 ring->empty_rx_reqs = NULL;
744 ring->configured = 0;
746 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
747 ring->port_id, ring->id);
750 static void ena_tx_queue_release(void *queue)
752 struct ena_ring *ring = (struct ena_ring *)queue;
753 struct ena_adapter *adapter = ring->adapter;
756 ena_assert_msg(ring->configured,
757 "API violation. Releasing not configured queue");
758 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
761 /* Destroy HW queue */
762 ena_qid = ENA_IO_TXQ_IDX(ring->id);
763 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
766 ena_tx_queue_release_bufs(ring);
768 /* Free ring resources */
769 if (ring->tx_buffer_info)
770 rte_free(ring->tx_buffer_info);
772 if (ring->empty_tx_reqs)
773 rte_free(ring->empty_tx_reqs);
775 ring->empty_tx_reqs = NULL;
776 ring->tx_buffer_info = NULL;
778 ring->configured = 0;
780 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
781 ring->port_id, ring->id);
784 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
786 unsigned int ring_mask = ring->ring_size - 1;
788 while (ring->next_to_clean != ring->next_to_use) {
790 ring->rx_buffer_info[ring->next_to_clean & ring_mask];
793 rte_mbuf_raw_free(m);
795 ring->next_to_clean++;
799 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
803 for (i = 0; i < ring->ring_size; ++i) {
804 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
807 rte_pktmbuf_free(tx_buf->mbuf);
809 ring->next_to_clean++;
813 static int ena_link_update(struct rte_eth_dev *dev,
814 __rte_unused int wait_to_complete)
816 struct rte_eth_link *link = &dev->data->dev_link;
817 struct ena_adapter *adapter;
819 adapter = (struct ena_adapter *)(dev->data->dev_private);
821 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
822 link->link_speed = ETH_SPEED_NUM_10G;
823 link->link_duplex = ETH_LINK_FULL_DUPLEX;
828 static int ena_queue_restart_all(struct rte_eth_dev *dev,
829 enum ena_ring_type ring_type)
831 struct ena_adapter *adapter =
832 (struct ena_adapter *)(dev->data->dev_private);
833 struct ena_ring *queues = NULL;
838 if (ring_type == ENA_RING_TYPE_RX) {
839 queues = adapter->rx_ring;
840 nb_queues = dev->data->nb_rx_queues;
842 queues = adapter->tx_ring;
843 nb_queues = dev->data->nb_tx_queues;
845 for (i = 0; i < nb_queues; i++) {
846 if (queues[i].configured) {
847 if (ring_type == ENA_RING_TYPE_RX) {
849 dev->data->rx_queues[i] == &queues[i],
850 "Inconsistent state of rx queues\n");
853 dev->data->tx_queues[i] == &queues[i],
854 "Inconsistent state of tx queues\n");
857 rc = ena_queue_restart(&queues[i]);
861 "failed to restart queue %d type(%d)",
871 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
873 uint32_t max_frame_len = adapter->max_mtu;
875 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
876 DEV_RX_OFFLOAD_JUMBO_FRAME)
878 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
880 return max_frame_len;
883 static int ena_check_valid_conf(struct ena_adapter *adapter)
885 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
887 if (max_frame_len > adapter->max_mtu) {
888 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
896 ena_calc_queue_size(struct ena_com_dev *ena_dev,
897 struct ena_com_dev_get_features_ctx *get_feat_ctx)
899 uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
901 queue_size = RTE_MIN(queue_size,
902 get_feat_ctx->max_queues.max_cq_depth);
903 queue_size = RTE_MIN(queue_size,
904 get_feat_ctx->max_queues.max_sq_depth);
906 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
907 queue_size = RTE_MIN(queue_size,
908 get_feat_ctx->max_queues.max_llq_depth);
910 /* Round down to power of 2 */
911 if (!rte_is_power_of_2(queue_size))
912 queue_size = rte_align32pow2(queue_size >> 1);
914 if (queue_size == 0) {
915 PMD_INIT_LOG(ERR, "Invalid queue size");
922 static void ena_stats_restart(struct rte_eth_dev *dev)
924 struct ena_adapter *adapter =
925 (struct ena_adapter *)(dev->data->dev_private);
927 rte_atomic64_init(&adapter->drv_stats->ierrors);
928 rte_atomic64_init(&adapter->drv_stats->oerrors);
929 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
932 static int ena_stats_get(struct rte_eth_dev *dev,
933 struct rte_eth_stats *stats)
935 struct ena_admin_basic_stats ena_stats;
936 struct ena_adapter *adapter =
937 (struct ena_adapter *)(dev->data->dev_private);
938 struct ena_com_dev *ena_dev = &adapter->ena_dev;
941 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
944 memset(&ena_stats, 0, sizeof(ena_stats));
945 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
947 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
951 /* Set of basic statistics from ENA */
952 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
953 ena_stats.rx_pkts_low);
954 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
955 ena_stats.tx_pkts_low);
956 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
957 ena_stats.rx_bytes_low);
958 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
959 ena_stats.tx_bytes_low);
960 stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
961 ena_stats.rx_drops_low);
963 /* Driver related stats */
964 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
965 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
966 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
970 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
972 struct ena_adapter *adapter;
973 struct ena_com_dev *ena_dev;
976 ena_assert_msg(dev->data != NULL, "Uninitialized device");
977 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
978 adapter = (struct ena_adapter *)(dev->data->dev_private);
980 ena_dev = &adapter->ena_dev;
981 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
983 if (mtu > ena_get_mtu_conf(adapter)) {
985 "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
986 mtu, ena_get_mtu_conf(adapter));
991 rc = ena_com_set_dev_mtu(ena_dev, mtu);
993 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
995 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1001 static int ena_start(struct rte_eth_dev *dev)
1003 struct ena_adapter *adapter =
1004 (struct ena_adapter *)(dev->data->dev_private);
1008 rc = ena_check_valid_conf(adapter);
1012 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
1016 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
1020 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1021 ETH_MQ_RX_RSS_FLAG) {
1022 rc = ena_rss_init_default(adapter);
1027 ena_stats_restart(dev);
1029 adapter->timestamp_wd = rte_get_timer_cycles();
1030 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1032 ticks = rte_get_timer_hz();
1033 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1034 ena_timer_wd_callback, adapter);
1036 adapter->state = ENA_ADAPTER_STATE_RUNNING;
1041 static void ena_stop(struct rte_eth_dev *dev)
1043 struct ena_adapter *adapter =
1044 (struct ena_adapter *)(dev->data->dev_private);
1046 rte_timer_stop_sync(&adapter->timer_wd);
1048 adapter->state = ENA_ADAPTER_STATE_STOPPED;
1051 static int ena_queue_restart(struct ena_ring *ring)
1055 ena_assert_msg(ring->configured == 1,
1056 "Trying to restart unconfigured queue\n");
1058 ring->next_to_clean = 0;
1059 ring->next_to_use = 0;
1061 if (ring->type == ENA_RING_TYPE_TX)
1064 bufs_num = ring->ring_size - 1;
1065 rc = ena_populate_rx_queue(ring, bufs_num);
1066 if (rc != bufs_num) {
1067 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1074 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1077 __rte_unused unsigned int socket_id,
1078 const struct rte_eth_txconf *tx_conf)
1080 struct ena_com_create_io_ctx ctx =
1081 /* policy set to _HOST just to satisfy icc compiler */
1082 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1083 ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
1084 struct ena_ring *txq = NULL;
1085 struct ena_adapter *adapter =
1086 (struct ena_adapter *)(dev->data->dev_private);
1090 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1092 txq = &adapter->tx_ring[queue_idx];
1094 if (txq->configured) {
1096 "API violation. Queue %d is already configured\n",
1101 if (!rte_is_power_of_2(nb_desc)) {
1103 "Unsupported size of RX queue: %d is not a power of 2.",
1108 if (nb_desc > adapter->tx_ring_size) {
1110 "Unsupported size of TX queue (max size: %d)\n",
1111 adapter->tx_ring_size);
1115 ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1117 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1119 ctx.msix_vector = -1; /* admin interrupts not used */
1120 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1121 ctx.queue_size = adapter->tx_ring_size;
1122 ctx.numa_node = ena_cpu_to_node(queue_idx);
1124 rc = ena_com_create_io_queue(ena_dev, &ctx);
1127 "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1128 queue_idx, ena_qid, rc);
1130 txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1131 txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1133 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1134 &txq->ena_com_io_sq,
1135 &txq->ena_com_io_cq);
1138 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1140 ena_com_destroy_io_queue(ena_dev, ena_qid);
1144 txq->port_id = dev->data->port_id;
1145 txq->next_to_clean = 0;
1146 txq->next_to_use = 0;
1147 txq->ring_size = nb_desc;
1149 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1150 sizeof(struct ena_tx_buffer) *
1152 RTE_CACHE_LINE_SIZE);
1153 if (!txq->tx_buffer_info) {
1154 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1158 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1159 sizeof(u16) * txq->ring_size,
1160 RTE_CACHE_LINE_SIZE);
1161 if (!txq->empty_tx_reqs) {
1162 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1163 rte_free(txq->tx_buffer_info);
1166 for (i = 0; i < txq->ring_size; i++)
1167 txq->empty_tx_reqs[i] = i;
1169 if (tx_conf != NULL) {
1171 tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1174 /* Store pointer to this queue in upper layer */
1175 txq->configured = 1;
1176 dev->data->tx_queues[queue_idx] = txq;
1181 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1184 __rte_unused unsigned int socket_id,
1185 __rte_unused const struct rte_eth_rxconf *rx_conf,
1186 struct rte_mempool *mp)
1188 struct ena_com_create_io_ctx ctx =
1189 /* policy set to _HOST just to satisfy icc compiler */
1190 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1191 ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1192 struct ena_adapter *adapter =
1193 (struct ena_adapter *)(dev->data->dev_private);
1194 struct ena_ring *rxq = NULL;
1195 uint16_t ena_qid = 0;
1197 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1199 rxq = &adapter->rx_ring[queue_idx];
1200 if (rxq->configured) {
1202 "API violation. Queue %d is already configured\n",
1207 if (!rte_is_power_of_2(nb_desc)) {
1209 "Unsupported size of TX queue: %d is not a power of 2.",
1214 if (nb_desc > adapter->rx_ring_size) {
1216 "Unsupported size of RX queue (max size: %d)\n",
1217 adapter->rx_ring_size);
1221 ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1224 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1225 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1226 ctx.msix_vector = -1; /* admin interrupts not used */
1227 ctx.queue_size = adapter->rx_ring_size;
1228 ctx.numa_node = ena_cpu_to_node(queue_idx);
1230 rc = ena_com_create_io_queue(ena_dev, &ctx);
1232 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1235 rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1236 rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1238 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1239 &rxq->ena_com_io_sq,
1240 &rxq->ena_com_io_cq);
1243 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1245 ena_com_destroy_io_queue(ena_dev, ena_qid);
1248 rxq->port_id = dev->data->port_id;
1249 rxq->next_to_clean = 0;
1250 rxq->next_to_use = 0;
1251 rxq->ring_size = nb_desc;
1254 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1255 sizeof(struct rte_mbuf *) * nb_desc,
1256 RTE_CACHE_LINE_SIZE);
1257 if (!rxq->rx_buffer_info) {
1258 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1262 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1263 sizeof(uint16_t) * nb_desc,
1264 RTE_CACHE_LINE_SIZE);
1265 if (!rxq->empty_rx_reqs) {
1266 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1267 rte_free(rxq->rx_buffer_info);
1268 rxq->rx_buffer_info = NULL;
1272 for (i = 0; i < nb_desc; i++)
1273 rxq->empty_tx_reqs[i] = i;
1275 /* Store pointer to this queue in upper layer */
1276 rxq->configured = 1;
1277 dev->data->rx_queues[queue_idx] = rxq;
1282 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1286 uint16_t ring_size = rxq->ring_size;
1287 uint16_t ring_mask = ring_size - 1;
1288 uint16_t next_to_use = rxq->next_to_use;
1289 uint16_t in_use, req_id;
1290 struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1292 if (unlikely(!count))
1295 in_use = rxq->next_to_use - rxq->next_to_clean;
1296 ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1298 count = RTE_MIN(count,
1299 (uint16_t)(ring_size - (next_to_use & ring_mask)));
1301 /* get resources for incoming packets */
1302 rc = rte_mempool_get_bulk(rxq->mb_pool,
1303 (void **)(&mbufs[next_to_use & ring_mask]),
1305 if (unlikely(rc < 0)) {
1306 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1307 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1311 for (i = 0; i < count; i++) {
1312 uint16_t next_to_use_masked = next_to_use & ring_mask;
1313 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1314 struct ena_com_buf ebuf;
1316 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1318 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1319 /* prepare physical address for DMA transaction */
1320 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1321 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1322 /* pass resource to device */
1323 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1326 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1328 RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1334 /* When we submitted free recources to device... */
1336 /* ...let HW know that it can fill buffers with data */
1338 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1340 rxq->next_to_use = next_to_use;
1346 static int ena_device_init(struct ena_com_dev *ena_dev,
1347 struct ena_com_dev_get_features_ctx *get_feat_ctx,
1350 uint32_t aenq_groups;
1352 bool readless_supported;
1354 /* Initialize mmio registers */
1355 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1357 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1361 /* The PCIe configuration space revision id indicate if mmio reg
1364 readless_supported =
1365 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1366 & ENA_MMIO_DISABLE_REG_READ);
1367 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1370 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1372 RTE_LOG(ERR, PMD, "cannot reset device\n");
1373 goto err_mmio_read_less;
1376 /* check FW version */
1377 rc = ena_com_validate_version(ena_dev);
1379 RTE_LOG(ERR, PMD, "device version is too low\n");
1380 goto err_mmio_read_less;
1383 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1385 /* ENA device administration layer init */
1386 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
1389 "cannot initialize ena admin queue with device\n");
1390 goto err_mmio_read_less;
1393 /* To enable the msix interrupts the driver needs to know the number
1394 * of queues. So the driver uses polling mode to retrieve this
1397 ena_com_set_admin_polling_mode(ena_dev, true);
1399 ena_config_host_info(ena_dev);
1401 /* Get Device Attributes and features */
1402 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1405 "cannot get attribute for ena device rc= %d\n", rc);
1406 goto err_admin_init;
1409 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1410 BIT(ENA_ADMIN_NOTIFICATION) |
1411 BIT(ENA_ADMIN_KEEP_ALIVE);
1413 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1414 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1416 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1417 goto err_admin_init;
1420 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1425 ena_com_admin_destroy(ena_dev);
1428 ena_com_mmio_reg_read_request_destroy(ena_dev);
1433 static void ena_interrupt_handler_rte(void *cb_arg)
1435 struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1436 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1438 ena_com_admin_q_comp_intr_handler(ena_dev);
1439 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1440 ena_com_aenq_intr_handler(ena_dev, adapter);
1443 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1445 if (!adapter->wd_state)
1448 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1451 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1452 adapter->keep_alive_timeout)) {
1453 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1454 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1455 adapter->trigger_reset = true;
1459 /* Check if admin queue is enabled */
1460 static void check_for_admin_com_state(struct ena_adapter *adapter)
1462 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1463 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1464 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1465 adapter->trigger_reset = true;
1469 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1472 struct ena_adapter *adapter = (struct ena_adapter *)arg;
1473 struct rte_eth_dev *dev = adapter->rte_dev;
1475 check_for_missing_keep_alive(adapter);
1476 check_for_admin_com_state(adapter);
1478 if (unlikely(adapter->trigger_reset)) {
1479 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1480 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1485 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1487 struct rte_pci_device *pci_dev;
1488 struct rte_intr_handle *intr_handle;
1489 struct ena_adapter *adapter =
1490 (struct ena_adapter *)(eth_dev->data->dev_private);
1491 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1492 struct ena_com_dev_get_features_ctx get_feat_ctx;
1495 static int adapters_found;
1498 memset(adapter, 0, sizeof(struct ena_adapter));
1499 ena_dev = &adapter->ena_dev;
1501 eth_dev->dev_ops = &ena_dev_ops;
1502 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1503 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1504 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1505 adapter->rte_eth_dev_data = eth_dev->data;
1506 adapter->rte_dev = eth_dev;
1508 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1511 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1512 adapter->pdev = pci_dev;
1514 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1515 pci_dev->addr.domain,
1517 pci_dev->addr.devid,
1518 pci_dev->addr.function);
1520 intr_handle = &pci_dev->intr_handle;
1522 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1523 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1525 if (!adapter->regs) {
1526 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1531 ena_dev->reg_bar = adapter->regs;
1532 ena_dev->dmadev = adapter->pdev;
1534 adapter->id_number = adapters_found;
1536 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1537 adapter->id_number);
1539 /* device specific initialization routine */
1540 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1542 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1545 adapter->wd_state = wd_state;
1547 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1548 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1550 queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1551 if ((queue_size <= 0) || (adapter->num_queues <= 0))
1554 adapter->tx_ring_size = queue_size;
1555 adapter->rx_ring_size = queue_size;
1557 /* prepare ring structures */
1558 ena_init_rings(adapter);
1560 ena_config_debug_area(adapter);
1562 /* Set max MTU for this device */
1563 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1565 /* set device support for TSO */
1566 adapter->tso4_supported = get_feat_ctx.offload.tx &
1567 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1569 /* Copy MAC address and point DPDK to it */
1570 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1571 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1572 (struct ether_addr *)adapter->mac_addr);
1574 adapter->drv_stats = rte_zmalloc("adapter stats",
1575 sizeof(*adapter->drv_stats),
1576 RTE_CACHE_LINE_SIZE);
1577 if (!adapter->drv_stats) {
1578 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1582 rte_intr_callback_register(intr_handle,
1583 ena_interrupt_handler_rte,
1585 rte_intr_enable(intr_handle);
1586 ena_com_set_admin_polling_mode(ena_dev, false);
1587 ena_com_admin_aenq_enable(ena_dev);
1589 if (adapters_found == 0)
1590 rte_timer_subsystem_init();
1591 rte_timer_init(&adapter->timer_wd);
1594 adapter->state = ENA_ADAPTER_STATE_INIT;
1599 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1601 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1602 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1603 struct ena_adapter *adapter =
1604 (struct ena_adapter *)(eth_dev->data->dev_private);
1606 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1609 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1612 eth_dev->dev_ops = NULL;
1613 eth_dev->rx_pkt_burst = NULL;
1614 eth_dev->tx_pkt_burst = NULL;
1615 eth_dev->tx_pkt_prepare = NULL;
1617 rte_free(adapter->drv_stats);
1618 adapter->drv_stats = NULL;
1620 rte_intr_disable(intr_handle);
1621 rte_intr_callback_unregister(intr_handle,
1622 ena_interrupt_handler_rte,
1625 adapter->state = ENA_ADAPTER_STATE_FREE;
1630 static int ena_dev_configure(struct rte_eth_dev *dev)
1632 struct ena_adapter *adapter =
1633 (struct ena_adapter *)(dev->data->dev_private);
1635 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1637 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1638 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1642 static void ena_init_rings(struct ena_adapter *adapter)
1646 for (i = 0; i < adapter->num_queues; i++) {
1647 struct ena_ring *ring = &adapter->tx_ring[i];
1649 ring->configured = 0;
1650 ring->type = ENA_RING_TYPE_TX;
1651 ring->adapter = adapter;
1653 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1654 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1657 for (i = 0; i < adapter->num_queues; i++) {
1658 struct ena_ring *ring = &adapter->rx_ring[i];
1660 ring->configured = 0;
1661 ring->type = ENA_RING_TYPE_RX;
1662 ring->adapter = adapter;
1667 static void ena_infos_get(struct rte_eth_dev *dev,
1668 struct rte_eth_dev_info *dev_info)
1670 struct ena_adapter *adapter;
1671 struct ena_com_dev *ena_dev;
1672 struct ena_com_dev_get_features_ctx feat;
1673 uint64_t rx_feat = 0, tx_feat = 0;
1676 ena_assert_msg(dev->data != NULL, "Uninitialized device");
1677 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1678 adapter = (struct ena_adapter *)(dev->data->dev_private);
1680 ena_dev = &adapter->ena_dev;
1681 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1683 dev_info->speed_capa =
1685 ETH_LINK_SPEED_2_5G |
1687 ETH_LINK_SPEED_10G |
1688 ETH_LINK_SPEED_25G |
1689 ETH_LINK_SPEED_40G |
1690 ETH_LINK_SPEED_50G |
1691 ETH_LINK_SPEED_100G;
1693 /* Get supported features from HW */
1694 rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1697 "Cannot get attribute for ena device rc= %d\n", rc);
1701 /* Set Tx & Rx features available for device */
1702 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1703 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1705 if (feat.offload.tx &
1706 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1707 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1708 DEV_TX_OFFLOAD_UDP_CKSUM |
1709 DEV_TX_OFFLOAD_TCP_CKSUM;
1711 if (feat.offload.rx_supported &
1712 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1713 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1714 DEV_RX_OFFLOAD_UDP_CKSUM |
1715 DEV_RX_OFFLOAD_TCP_CKSUM;
1717 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1719 /* Inform framework about available features */
1720 dev_info->rx_offload_capa = rx_feat;
1721 dev_info->rx_queue_offload_capa = rx_feat;
1722 dev_info->tx_offload_capa = tx_feat;
1723 dev_info->tx_queue_offload_capa = tx_feat;
1725 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1726 dev_info->max_rx_pktlen = adapter->max_mtu;
1727 dev_info->max_mac_addrs = 1;
1729 dev_info->max_rx_queues = adapter->num_queues;
1730 dev_info->max_tx_queues = adapter->num_queues;
1731 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1733 adapter->tx_supported_offloads = tx_feat;
1734 adapter->rx_supported_offloads = rx_feat;
1737 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1740 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1741 unsigned int ring_size = rx_ring->ring_size;
1742 unsigned int ring_mask = ring_size - 1;
1743 uint16_t next_to_clean = rx_ring->next_to_clean;
1744 uint16_t desc_in_use = 0;
1746 unsigned int recv_idx = 0;
1747 struct rte_mbuf *mbuf = NULL;
1748 struct rte_mbuf *mbuf_head = NULL;
1749 struct rte_mbuf *mbuf_prev = NULL;
1750 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1751 unsigned int completed;
1753 struct ena_com_rx_ctx ena_rx_ctx;
1756 /* Check adapter state */
1757 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1759 "Trying to receive pkts while device is NOT running\n");
1763 desc_in_use = rx_ring->next_to_use - next_to_clean;
1764 if (unlikely(nb_pkts > desc_in_use))
1765 nb_pkts = desc_in_use;
1767 for (completed = 0; completed < nb_pkts; completed++) {
1770 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1771 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1772 ena_rx_ctx.descs = 0;
1773 /* receive packet context */
1774 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1775 rx_ring->ena_com_io_sq,
1778 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1782 if (unlikely(ena_rx_ctx.descs == 0))
1785 while (segments < ena_rx_ctx.descs) {
1786 req_id = ena_rx_ctx.ena_bufs[segments].req_id;
1787 rc = validate_rx_req_id(rx_ring, req_id);
1791 mbuf = rx_buff_info[req_id];
1792 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1793 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1796 if (segments == 0) {
1797 mbuf->nb_segs = ena_rx_ctx.descs;
1798 mbuf->port = rx_ring->port_id;
1802 /* for multi-segment pkts create mbuf chain */
1803 mbuf_prev->next = mbuf;
1805 mbuf_head->pkt_len += mbuf->data_len;
1808 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
1814 /* fill mbuf attributes if any */
1815 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1816 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1818 /* pass to DPDK application head mbuf */
1819 rx_pkts[recv_idx] = mbuf_head;
1823 rx_ring->next_to_clean = next_to_clean;
1825 desc_in_use = desc_in_use - completed + 1;
1826 /* Burst refill to save doorbells, memory barriers, const interval */
1827 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1828 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1834 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1840 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1841 struct ipv4_hdr *ip_hdr;
1843 uint16_t frag_field;
1845 for (i = 0; i != nb_pkts; i++) {
1847 ol_flags = m->ol_flags;
1849 if (!(ol_flags & PKT_TX_IPV4))
1852 /* If there was not L2 header length specified, assume it is
1853 * length of the ethernet header.
1855 if (unlikely(m->l2_len == 0))
1856 m->l2_len = sizeof(struct ether_hdr);
1858 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1860 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1862 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1863 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1865 /* If IPv4 header has DF flag enabled and TSO support is
1866 * disabled, partial chcecksum should not be calculated.
1868 if (!tx_ring->adapter->tso4_supported)
1872 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1873 (ol_flags & PKT_TX_L4_MASK) ==
1874 PKT_TX_SCTP_CKSUM) {
1875 rte_errno = -ENOTSUP;
1879 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1880 ret = rte_validate_tx_offload(m);
1887 /* In case we are supposed to TSO and have DF not set (DF=0)
1888 * hardware must be provided with partial checksum, otherwise
1889 * it will take care of necessary calculations.
1892 ret = rte_net_intel_cksum_flags_prepare(m,
1893 ol_flags & ~PKT_TX_TCP_SEG);
1903 static void ena_update_hints(struct ena_adapter *adapter,
1904 struct ena_admin_ena_hw_hints *hints)
1906 if (hints->admin_completion_tx_timeout)
1907 adapter->ena_dev.admin_queue.completion_timeout =
1908 hints->admin_completion_tx_timeout * 1000;
1910 if (hints->mmio_read_timeout)
1911 /* convert to usec */
1912 adapter->ena_dev.mmio_read.reg_read_to =
1913 hints->mmio_read_timeout * 1000;
1915 if (hints->driver_watchdog_timeout) {
1916 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1917 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
1919 // Convert msecs to ticks
1920 adapter->keep_alive_timeout =
1921 (hints->driver_watchdog_timeout *
1922 rte_get_timer_hz()) / 1000;
1926 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1929 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1930 uint16_t next_to_use = tx_ring->next_to_use;
1931 uint16_t next_to_clean = tx_ring->next_to_clean;
1932 struct rte_mbuf *mbuf;
1933 unsigned int ring_size = tx_ring->ring_size;
1934 unsigned int ring_mask = ring_size - 1;
1935 struct ena_com_tx_ctx ena_tx_ctx;
1936 struct ena_tx_buffer *tx_info;
1937 struct ena_com_buf *ebuf;
1938 uint16_t rc, req_id, total_tx_descs = 0;
1939 uint16_t sent_idx = 0, empty_tx_reqs;
1942 /* Check adapter state */
1943 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1945 "Trying to xmit pkts while device is NOT running\n");
1949 empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1950 if (nb_pkts > empty_tx_reqs)
1951 nb_pkts = empty_tx_reqs;
1953 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1954 mbuf = tx_pkts[sent_idx];
1956 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1957 tx_info = &tx_ring->tx_buffer_info[req_id];
1958 tx_info->mbuf = mbuf;
1959 tx_info->num_of_bufs = 0;
1960 ebuf = tx_info->bufs;
1962 /* Prepare TX context */
1963 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1964 memset(&ena_tx_ctx.ena_meta, 0x0,
1965 sizeof(struct ena_com_tx_meta));
1966 ena_tx_ctx.ena_bufs = ebuf;
1967 ena_tx_ctx.req_id = req_id;
1968 if (tx_ring->tx_mem_queue_type ==
1969 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1970 /* prepare the push buffer with
1971 * virtual address of the data
1973 ena_tx_ctx.header_len =
1974 RTE_MIN(mbuf->data_len,
1975 tx_ring->tx_max_header_size);
1976 ena_tx_ctx.push_header =
1977 (void *)((char *)mbuf->buf_addr +
1979 } /* there's no else as we take advantage of memset zeroing */
1981 /* Set TX offloads flags, if applicable */
1982 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
1984 if (unlikely(mbuf->ol_flags &
1985 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1986 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1988 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1990 /* Process first segment taking into
1991 * consideration pushed header
1993 if (mbuf->data_len > ena_tx_ctx.header_len) {
1994 ebuf->paddr = mbuf->buf_iova +
1996 ena_tx_ctx.header_len;
1997 ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1999 tx_info->num_of_bufs++;
2002 while ((mbuf = mbuf->next) != NULL) {
2003 ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
2004 ebuf->len = mbuf->data_len;
2006 tx_info->num_of_bufs++;
2009 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2011 /* Write data to device */
2012 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2013 &ena_tx_ctx, &nb_hw_desc);
2017 tx_info->tx_descs = nb_hw_desc;
2022 /* If there are ready packets to be xmitted... */
2024 /* ...let HW do its best :-) */
2026 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2028 tx_ring->next_to_use = next_to_use;
2031 /* Clear complete packets */
2032 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2033 /* Get Tx info & store how many descs were processed */
2034 tx_info = &tx_ring->tx_buffer_info[req_id];
2035 total_tx_descs += tx_info->tx_descs;
2037 /* Free whole mbuf chain */
2038 mbuf = tx_info->mbuf;
2039 rte_pktmbuf_free(mbuf);
2040 tx_info->mbuf = NULL;
2042 /* Put back descriptor to the ring for reuse */
2043 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2046 /* If too many descs to clean, leave it for another run */
2047 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2051 if (total_tx_descs > 0) {
2052 /* acknowledge completion of sent packets */
2053 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2054 tx_ring->next_to_clean = next_to_clean;
2060 /*********************************************************************
2062 *********************************************************************/
2063 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2064 struct rte_pci_device *pci_dev)
2066 return rte_eth_dev_pci_generic_probe(pci_dev,
2067 sizeof(struct ena_adapter), eth_ena_dev_init);
2070 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2072 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2075 static struct rte_pci_driver rte_ena_pmd = {
2076 .id_table = pci_id_ena_map,
2077 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2078 .probe = eth_ena_pci_probe,
2079 .remove = eth_ena_pci_remove,
2082 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2083 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2084 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2086 RTE_INIT(ena_init_log);
2090 ena_logtype_init = rte_log_register("pmd.net.ena.init");
2091 if (ena_logtype_init >= 0)
2092 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2093 ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2094 if (ena_logtype_driver >= 0)
2095 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2098 /******************************************************************************
2099 ******************************** AENQ Handlers *******************************
2100 *****************************************************************************/
2101 static void ena_update_on_link_change(void *adapter_data,
2102 struct ena_admin_aenq_entry *aenq_e)
2104 struct rte_eth_dev *eth_dev;
2105 struct ena_adapter *adapter;
2106 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2109 adapter = (struct ena_adapter *)adapter_data;
2110 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2111 eth_dev = adapter->rte_dev;
2113 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2114 adapter->link_status = status;
2116 ena_link_update(eth_dev, 0);
2117 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2120 static void ena_notification(void *data,
2121 struct ena_admin_aenq_entry *aenq_e)
2123 struct ena_adapter *adapter = (struct ena_adapter *)data;
2124 struct ena_admin_ena_hw_hints *hints;
2126 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2127 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2128 aenq_e->aenq_common_desc.group,
2129 ENA_ADMIN_NOTIFICATION);
2131 switch (aenq_e->aenq_common_desc.syndrom) {
2132 case ENA_ADMIN_UPDATE_HINTS:
2133 hints = (struct ena_admin_ena_hw_hints *)
2134 (&aenq_e->inline_data_w4);
2135 ena_update_hints(adapter, hints);
2138 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2139 aenq_e->aenq_common_desc.syndrom);
2143 static void ena_keep_alive(void *adapter_data,
2144 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2146 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2148 adapter->timestamp_wd = rte_get_timer_cycles();
2152 * This handler will called for unknown event group or unimplemented handlers
2154 static void unimplemented_aenq_handler(__rte_unused void *data,
2155 __rte_unused struct ena_admin_aenq_entry *aenq_e)
2157 // Unimplemented handler
2160 static struct ena_aenq_handlers aenq_handlers = {
2162 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2163 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2164 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2166 .unimplemented_handler = unimplemented_aenq_handler