1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
6 #include <rte_string_fns.h>
8 #include <rte_version.h>
10 #include <rte_kvargs.h>
12 #include "ena_ethdev.h"
14 #include "ena_platform.h"
16 #include "ena_eth_com.h"
18 #include <ena_common_defs.h>
19 #include <ena_regs_defs.h>
20 #include <ena_admin_defs.h>
21 #include <ena_eth_io_defs.h>
23 #define DRV_MODULE_VER_MAJOR 2
24 #define DRV_MODULE_VER_MINOR 4
25 #define DRV_MODULE_VER_SUBMINOR 0
27 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
29 #define GET_L4_HDR_LEN(mbuf) \
30 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \
31 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
33 #define ETH_GSTRING_LEN 32
35 #define ARRAY_SIZE(x) RTE_DIM(x)
37 #define ENA_MIN_RING_DESC 128
39 #define ENA_PTYPE_HAS_HASH (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP)
41 enum ethtool_stringset {
47 char name[ETH_GSTRING_LEN];
51 #define ENA_STAT_ENTRY(stat, stat_type) { \
53 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
56 #define ENA_STAT_RX_ENTRY(stat) \
57 ENA_STAT_ENTRY(stat, rx)
59 #define ENA_STAT_TX_ENTRY(stat) \
60 ENA_STAT_ENTRY(stat, tx)
62 #define ENA_STAT_ENI_ENTRY(stat) \
63 ENA_STAT_ENTRY(stat, eni)
65 #define ENA_STAT_GLOBAL_ENTRY(stat) \
66 ENA_STAT_ENTRY(stat, dev)
68 /* Device arguments */
69 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
72 * Each rte_memzone should have unique name.
73 * To satisfy it, count number of allocation and add it to name.
75 rte_atomic64_t ena_alloc_cnt;
77 static const struct ena_stats ena_stats_global_strings[] = {
78 ENA_STAT_GLOBAL_ENTRY(wd_expired),
79 ENA_STAT_GLOBAL_ENTRY(dev_start),
80 ENA_STAT_GLOBAL_ENTRY(dev_stop),
81 ENA_STAT_GLOBAL_ENTRY(tx_drops),
84 static const struct ena_stats ena_stats_eni_strings[] = {
85 ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
86 ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
87 ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
88 ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
89 ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
92 static const struct ena_stats ena_stats_tx_strings[] = {
93 ENA_STAT_TX_ENTRY(cnt),
94 ENA_STAT_TX_ENTRY(bytes),
95 ENA_STAT_TX_ENTRY(prepare_ctx_err),
96 ENA_STAT_TX_ENTRY(linearize),
97 ENA_STAT_TX_ENTRY(linearize_failed),
98 ENA_STAT_TX_ENTRY(tx_poll),
99 ENA_STAT_TX_ENTRY(doorbells),
100 ENA_STAT_TX_ENTRY(bad_req_id),
101 ENA_STAT_TX_ENTRY(available_desc),
104 static const struct ena_stats ena_stats_rx_strings[] = {
105 ENA_STAT_RX_ENTRY(cnt),
106 ENA_STAT_RX_ENTRY(bytes),
107 ENA_STAT_RX_ENTRY(refill_partial),
108 ENA_STAT_RX_ENTRY(bad_csum),
109 ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
110 ENA_STAT_RX_ENTRY(bad_desc_num),
111 ENA_STAT_RX_ENTRY(bad_req_id),
114 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
115 #define ENA_STATS_ARRAY_ENI ARRAY_SIZE(ena_stats_eni_strings)
116 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
117 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
119 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
120 DEV_TX_OFFLOAD_UDP_CKSUM |\
121 DEV_TX_OFFLOAD_IPV4_CKSUM |\
122 DEV_TX_OFFLOAD_TCP_TSO)
123 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
127 /** Vendor ID used by Amazon devices */
128 #define PCI_VENDOR_ID_AMAZON 0x1D0F
129 /** Amazon devices */
130 #define PCI_DEVICE_ID_ENA_VF 0xEC20
131 #define PCI_DEVICE_ID_ENA_VF_RSERV0 0xEC21
133 #define ENA_TX_OFFLOAD_MASK (\
140 #define ENA_TX_OFFLOAD_NOTSUP_MASK \
141 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
143 /** HW specific offloads capabilities. */
144 /* IPv4 checksum offload. */
145 #define ENA_L3_IPV4_CSUM 0x0001
146 /* TCP/UDP checksum offload for IPv4 packets. */
147 #define ENA_L4_IPV4_CSUM 0x0002
148 /* TCP/UDP checksum offload for IPv4 packets with pseudo header checksum. */
149 #define ENA_L4_IPV4_CSUM_PARTIAL 0x0004
150 /* TCP/UDP checksum offload for IPv6 packets. */
151 #define ENA_L4_IPV6_CSUM 0x0008
152 /* TCP/UDP checksum offload for IPv6 packets with pseudo header checksum. */
153 #define ENA_L4_IPV6_CSUM_PARTIAL 0x0010
154 /* TSO support for IPv4 packets. */
155 #define ENA_IPV4_TSO 0x0020
157 /* Device supports setting RSS hash. */
158 #define ENA_RX_RSS_HASH 0x0040
160 static const struct rte_pci_id pci_id_ena_map[] = {
161 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
162 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
166 static struct ena_aenq_handlers aenq_handlers;
168 static int ena_device_init(struct ena_com_dev *ena_dev,
169 struct rte_pci_device *pdev,
170 struct ena_com_dev_get_features_ctx *get_feat_ctx,
172 static int ena_dev_configure(struct rte_eth_dev *dev);
173 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
174 struct ena_tx_buffer *tx_info,
175 struct rte_mbuf *mbuf,
177 uint16_t *header_len);
178 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
179 static void ena_tx_cleanup(struct ena_ring *tx_ring);
180 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
182 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
184 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
185 uint16_t nb_desc, unsigned int socket_id,
186 const struct rte_eth_txconf *tx_conf);
187 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
188 uint16_t nb_desc, unsigned int socket_id,
189 const struct rte_eth_rxconf *rx_conf,
190 struct rte_mempool *mp);
191 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
192 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
193 struct ena_com_rx_buf_info *ena_bufs,
195 uint16_t *next_to_clean,
197 static uint16_t eth_ena_recv_pkts(void *rx_queue,
198 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
199 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
200 struct rte_mbuf *mbuf, uint16_t id);
201 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
202 static void ena_init_rings(struct ena_adapter *adapter,
203 bool disable_meta_caching);
204 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
205 static int ena_start(struct rte_eth_dev *dev);
206 static int ena_stop(struct rte_eth_dev *dev);
207 static int ena_close(struct rte_eth_dev *dev);
208 static int ena_dev_reset(struct rte_eth_dev *dev);
209 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
210 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
211 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
212 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
213 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
214 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
215 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
216 static int ena_link_update(struct rte_eth_dev *dev,
217 int wait_to_complete);
218 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring);
219 static void ena_queue_stop(struct ena_ring *ring);
220 static void ena_queue_stop_all(struct rte_eth_dev *dev,
221 enum ena_ring_type ring_type);
222 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring);
223 static int ena_queue_start_all(struct rte_eth_dev *dev,
224 enum ena_ring_type ring_type);
225 static void ena_stats_restart(struct rte_eth_dev *dev);
226 static int ena_infos_get(struct rte_eth_dev *dev,
227 struct rte_eth_dev_info *dev_info);
228 static void ena_interrupt_handler_rte(void *cb_arg);
229 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
230 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
231 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
232 static int ena_xstats_get_names(struct rte_eth_dev *dev,
233 struct rte_eth_xstat_name *xstats_names,
235 static int ena_xstats_get(struct rte_eth_dev *dev,
236 struct rte_eth_xstat *stats,
238 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
242 static int ena_process_bool_devarg(const char *key,
245 static int ena_parse_devargs(struct ena_adapter *adapter,
246 struct rte_devargs *devargs);
247 static int ena_copy_eni_stats(struct ena_adapter *adapter);
248 static int ena_setup_rx_intr(struct rte_eth_dev *dev);
249 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
251 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
254 static const struct eth_dev_ops ena_dev_ops = {
255 .dev_configure = ena_dev_configure,
256 .dev_infos_get = ena_infos_get,
257 .rx_queue_setup = ena_rx_queue_setup,
258 .tx_queue_setup = ena_tx_queue_setup,
259 .dev_start = ena_start,
260 .dev_stop = ena_stop,
261 .link_update = ena_link_update,
262 .stats_get = ena_stats_get,
263 .xstats_get_names = ena_xstats_get_names,
264 .xstats_get = ena_xstats_get,
265 .xstats_get_by_id = ena_xstats_get_by_id,
266 .mtu_set = ena_mtu_set,
267 .rx_queue_release = ena_rx_queue_release,
268 .tx_queue_release = ena_tx_queue_release,
269 .dev_close = ena_close,
270 .dev_reset = ena_dev_reset,
271 .reta_update = ena_rss_reta_update,
272 .reta_query = ena_rss_reta_query,
273 .rx_queue_intr_enable = ena_rx_queue_intr_enable,
274 .rx_queue_intr_disable = ena_rx_queue_intr_disable,
275 .rss_hash_update = ena_rss_hash_update,
276 .rss_hash_conf_get = ena_rss_hash_conf_get,
279 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
280 struct ena_com_rx_ctx *ena_rx_ctx,
283 uint64_t ol_flags = 0;
284 uint32_t packet_type = 0;
286 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
287 packet_type |= RTE_PTYPE_L4_TCP;
288 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
289 packet_type |= RTE_PTYPE_L4_UDP;
291 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
292 packet_type |= RTE_PTYPE_L3_IPV4;
293 if (unlikely(ena_rx_ctx->l3_csum_err))
294 ol_flags |= PKT_RX_IP_CKSUM_BAD;
296 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
297 } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
298 packet_type |= RTE_PTYPE_L3_IPV6;
301 if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag)
302 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
304 if (unlikely(ena_rx_ctx->l4_csum_err))
305 ol_flags |= PKT_RX_L4_CKSUM_BAD;
307 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
310 likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) {
311 ol_flags |= PKT_RX_RSS_HASH;
312 mbuf->hash.rss = ena_rx_ctx->hash;
315 mbuf->ol_flags = ol_flags;
316 mbuf->packet_type = packet_type;
319 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
320 struct ena_com_tx_ctx *ena_tx_ctx,
321 uint64_t queue_offloads,
322 bool disable_meta_caching)
324 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
326 if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
327 (queue_offloads & QUEUE_OFFLOADS)) {
328 /* check if TSO is required */
329 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
330 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
331 ena_tx_ctx->tso_enable = true;
333 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
336 /* check if L3 checksum is needed */
337 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
338 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
339 ena_tx_ctx->l3_csum_enable = true;
341 if (mbuf->ol_flags & PKT_TX_IPV6) {
342 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
344 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
346 /* set don't fragment (DF) flag */
347 if (mbuf->packet_type &
348 (RTE_PTYPE_L4_NONFRAG
349 | RTE_PTYPE_INNER_L4_NONFRAG))
350 ena_tx_ctx->df = true;
353 /* check if L4 checksum is needed */
354 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
355 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
356 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
357 ena_tx_ctx->l4_csum_enable = true;
358 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
360 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
361 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
362 ena_tx_ctx->l4_csum_enable = true;
364 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
365 ena_tx_ctx->l4_csum_enable = false;
368 ena_meta->mss = mbuf->tso_segsz;
369 ena_meta->l3_hdr_len = mbuf->l3_len;
370 ena_meta->l3_hdr_offset = mbuf->l2_len;
372 ena_tx_ctx->meta_valid = true;
373 } else if (disable_meta_caching) {
374 memset(ena_meta, 0, sizeof(*ena_meta));
375 ena_tx_ctx->meta_valid = true;
377 ena_tx_ctx->meta_valid = false;
381 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
383 struct ena_tx_buffer *tx_info = NULL;
385 if (likely(req_id < tx_ring->ring_size)) {
386 tx_info = &tx_ring->tx_buffer_info[req_id];
387 if (likely(tx_info->mbuf))
392 PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf\n");
394 PMD_TX_LOG(ERR, "Invalid req_id: %hu\n", req_id);
396 /* Trigger device reset */
397 ++tx_ring->tx_stats.bad_req_id;
398 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
399 tx_ring->adapter->trigger_reset = true;
403 static void ena_config_host_info(struct ena_com_dev *ena_dev)
405 struct ena_admin_host_info *host_info;
408 /* Allocate only the host info */
409 rc = ena_com_allocate_host_info(ena_dev);
411 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
415 host_info = ena_dev->host_attr.host_info;
417 host_info->os_type = ENA_ADMIN_OS_DPDK;
418 host_info->kernel_ver = RTE_VERSION;
419 strlcpy((char *)host_info->kernel_ver_str, rte_version(),
420 sizeof(host_info->kernel_ver_str));
421 host_info->os_dist = RTE_VERSION;
422 strlcpy((char *)host_info->os_dist_str, rte_version(),
423 sizeof(host_info->os_dist_str));
424 host_info->driver_version =
425 (DRV_MODULE_VER_MAJOR) |
426 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
427 (DRV_MODULE_VER_SUBMINOR <<
428 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
429 host_info->num_cpus = rte_lcore_count();
431 host_info->driver_supported_features =
432 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK |
433 ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
435 rc = ena_com_set_host_attributes(ena_dev);
437 if (rc == -ENA_COM_UNSUPPORTED)
438 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
440 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
448 ena_com_delete_host_info(ena_dev);
451 /* This function calculates the number of xstats based on the current config */
452 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data)
454 return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
455 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
456 (data->nb_rx_queues * ENA_STATS_ARRAY_RX);
459 static void ena_config_debug_area(struct ena_adapter *adapter)
464 ss_count = ena_xstats_calc_num(adapter->edev_data);
466 /* allocate 32 bytes for each string and 64bit for the value */
467 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
469 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
471 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
475 rc = ena_com_set_host_attributes(&adapter->ena_dev);
477 if (rc == -ENA_COM_UNSUPPORTED)
478 PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
480 PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
487 ena_com_delete_debug_area(&adapter->ena_dev);
490 static int ena_close(struct rte_eth_dev *dev)
492 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
493 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
494 struct ena_adapter *adapter = dev->data->dev_private;
497 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
500 if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
502 adapter->state = ENA_ADAPTER_STATE_CLOSED;
504 ena_rx_queue_release_all(dev);
505 ena_tx_queue_release_all(dev);
507 rte_free(adapter->drv_stats);
508 adapter->drv_stats = NULL;
510 rte_intr_disable(intr_handle);
511 rte_intr_callback_unregister(intr_handle,
512 ena_interrupt_handler_rte,
516 * MAC is not allocated dynamically. Setting NULL should prevent from
517 * release of the resource in the rte_eth_dev_release_port().
519 dev->data->mac_addrs = NULL;
525 ena_dev_reset(struct rte_eth_dev *dev)
529 /* Cannot release memory in secondary process */
530 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
531 PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n");
535 ena_destroy_device(dev);
536 rc = eth_ena_dev_init(dev);
538 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
543 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
545 int nb_queues = dev->data->nb_rx_queues;
548 for (i = 0; i < nb_queues; i++)
549 ena_rx_queue_release(dev, i);
552 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
554 int nb_queues = dev->data->nb_tx_queues;
557 for (i = 0; i < nb_queues; i++)
558 ena_tx_queue_release(dev, i);
561 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
563 struct ena_ring *ring = dev->data->rx_queues[qid];
565 /* Free ring resources */
566 if (ring->rx_buffer_info)
567 rte_free(ring->rx_buffer_info);
568 ring->rx_buffer_info = NULL;
570 if (ring->rx_refill_buffer)
571 rte_free(ring->rx_refill_buffer);
572 ring->rx_refill_buffer = NULL;
574 if (ring->empty_rx_reqs)
575 rte_free(ring->empty_rx_reqs);
576 ring->empty_rx_reqs = NULL;
578 ring->configured = 0;
580 PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n",
581 ring->port_id, ring->id);
584 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
586 struct ena_ring *ring = dev->data->tx_queues[qid];
588 /* Free ring resources */
589 if (ring->push_buf_intermediate_buf)
590 rte_free(ring->push_buf_intermediate_buf);
592 if (ring->tx_buffer_info)
593 rte_free(ring->tx_buffer_info);
595 if (ring->empty_tx_reqs)
596 rte_free(ring->empty_tx_reqs);
598 ring->empty_tx_reqs = NULL;
599 ring->tx_buffer_info = NULL;
600 ring->push_buf_intermediate_buf = NULL;
602 ring->configured = 0;
604 PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n",
605 ring->port_id, ring->id);
608 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
612 for (i = 0; i < ring->ring_size; ++i) {
613 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
615 rte_mbuf_raw_free(rx_info->mbuf);
616 rx_info->mbuf = NULL;
621 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
625 for (i = 0; i < ring->ring_size; ++i) {
626 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
629 rte_pktmbuf_free(tx_buf->mbuf);
635 static int ena_link_update(struct rte_eth_dev *dev,
636 __rte_unused int wait_to_complete)
638 struct rte_eth_link *link = &dev->data->dev_link;
639 struct ena_adapter *adapter = dev->data->dev_private;
641 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
642 link->link_speed = ETH_SPEED_NUM_NONE;
643 link->link_duplex = ETH_LINK_FULL_DUPLEX;
648 static int ena_queue_start_all(struct rte_eth_dev *dev,
649 enum ena_ring_type ring_type)
651 struct ena_adapter *adapter = dev->data->dev_private;
652 struct ena_ring *queues = NULL;
657 if (ring_type == ENA_RING_TYPE_RX) {
658 queues = adapter->rx_ring;
659 nb_queues = dev->data->nb_rx_queues;
661 queues = adapter->tx_ring;
662 nb_queues = dev->data->nb_tx_queues;
664 for (i = 0; i < nb_queues; i++) {
665 if (queues[i].configured) {
666 if (ring_type == ENA_RING_TYPE_RX) {
668 dev->data->rx_queues[i] == &queues[i],
669 "Inconsistent state of Rx queues\n");
672 dev->data->tx_queues[i] == &queues[i],
673 "Inconsistent state of Tx queues\n");
676 rc = ena_queue_start(dev, &queues[i]);
680 "Failed to start queue[%d] of type(%d)\n",
691 if (queues[i].configured)
692 ena_queue_stop(&queues[i]);
697 static int ena_check_valid_conf(struct ena_adapter *adapter)
699 uint32_t mtu = adapter->edev_data->mtu;
701 if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
703 "Unsupported MTU of %d. Max MTU: %d, min MTU: %d\n",
704 mtu, adapter->max_mtu, ENA_MIN_MTU);
705 return ENA_COM_UNSUPPORTED;
712 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
713 bool use_large_llq_hdr)
715 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
716 struct ena_com_dev *ena_dev = ctx->ena_dev;
717 uint32_t max_tx_queue_size;
718 uint32_t max_rx_queue_size;
720 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
721 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
722 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
723 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
724 max_queue_ext->max_rx_sq_depth);
725 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
727 if (ena_dev->tx_mem_queue_type ==
728 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
729 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
732 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
733 max_queue_ext->max_tx_sq_depth);
736 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
737 max_queue_ext->max_per_packet_rx_descs);
738 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
739 max_queue_ext->max_per_packet_tx_descs);
741 struct ena_admin_queue_feature_desc *max_queues =
742 &ctx->get_feat_ctx->max_queues;
743 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
744 max_queues->max_sq_depth);
745 max_tx_queue_size = max_queues->max_cq_depth;
747 if (ena_dev->tx_mem_queue_type ==
748 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
749 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
752 max_tx_queue_size = RTE_MIN(max_tx_queue_size,
753 max_queues->max_sq_depth);
756 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
757 max_queues->max_packet_rx_descs);
758 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
759 max_queues->max_packet_tx_descs);
762 /* Round down to the nearest power of 2 */
763 max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
764 max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
766 if (use_large_llq_hdr) {
767 if ((llq->entry_size_ctrl_supported &
768 ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
769 (ena_dev->tx_mem_queue_type ==
770 ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
771 max_tx_queue_size /= 2;
773 "Forcing large headers and decreasing maximum Tx queue size to %d\n",
777 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
781 if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
782 PMD_INIT_LOG(ERR, "Invalid queue size\n");
786 ctx->max_tx_queue_size = max_tx_queue_size;
787 ctx->max_rx_queue_size = max_rx_queue_size;
792 static void ena_stats_restart(struct rte_eth_dev *dev)
794 struct ena_adapter *adapter = dev->data->dev_private;
796 rte_atomic64_init(&adapter->drv_stats->ierrors);
797 rte_atomic64_init(&adapter->drv_stats->oerrors);
798 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
799 adapter->drv_stats->rx_drops = 0;
802 static int ena_stats_get(struct rte_eth_dev *dev,
803 struct rte_eth_stats *stats)
805 struct ena_admin_basic_stats ena_stats;
806 struct ena_adapter *adapter = dev->data->dev_private;
807 struct ena_com_dev *ena_dev = &adapter->ena_dev;
812 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
815 memset(&ena_stats, 0, sizeof(ena_stats));
817 rte_spinlock_lock(&adapter->admin_lock);
818 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
819 rte_spinlock_unlock(&adapter->admin_lock);
821 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
825 /* Set of basic statistics from ENA */
826 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
827 ena_stats.rx_pkts_low);
828 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
829 ena_stats.tx_pkts_low);
830 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
831 ena_stats.rx_bytes_low);
832 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
833 ena_stats.tx_bytes_low);
835 /* Driver related stats */
836 stats->imissed = adapter->drv_stats->rx_drops;
837 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
838 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
839 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
841 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
842 RTE_ETHDEV_QUEUE_STAT_CNTRS);
843 for (i = 0; i < max_rings_stats; ++i) {
844 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
846 stats->q_ibytes[i] = rx_stats->bytes;
847 stats->q_ipackets[i] = rx_stats->cnt;
848 stats->q_errors[i] = rx_stats->bad_desc_num +
849 rx_stats->bad_req_id;
852 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
853 RTE_ETHDEV_QUEUE_STAT_CNTRS);
854 for (i = 0; i < max_rings_stats; ++i) {
855 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
857 stats->q_obytes[i] = tx_stats->bytes;
858 stats->q_opackets[i] = tx_stats->cnt;
864 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
866 struct ena_adapter *adapter;
867 struct ena_com_dev *ena_dev;
870 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
871 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
872 adapter = dev->data->dev_private;
874 ena_dev = &adapter->ena_dev;
875 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
877 if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
879 "Invalid MTU setting. New MTU: %d, max MTU: %d, min MTU: %d\n",
880 mtu, adapter->max_mtu, ENA_MIN_MTU);
884 rc = ena_com_set_dev_mtu(ena_dev, mtu);
886 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
888 PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu);
893 static int ena_start(struct rte_eth_dev *dev)
895 struct ena_adapter *adapter = dev->data->dev_private;
899 /* Cannot allocate memory in secondary process */
900 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
901 PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n");
905 rc = ena_check_valid_conf(adapter);
909 rc = ena_setup_rx_intr(dev);
913 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
917 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
921 if (adapter->edev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
922 rc = ena_rss_configure(adapter);
927 ena_stats_restart(dev);
929 adapter->timestamp_wd = rte_get_timer_cycles();
930 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
932 ticks = rte_get_timer_hz();
933 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
934 ena_timer_wd_callback, dev);
936 ++adapter->dev_stats.dev_start;
937 adapter->state = ENA_ADAPTER_STATE_RUNNING;
942 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
944 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
948 static int ena_stop(struct rte_eth_dev *dev)
950 struct ena_adapter *adapter = dev->data->dev_private;
951 struct ena_com_dev *ena_dev = &adapter->ena_dev;
952 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
953 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
956 /* Cannot free memory in secondary process */
957 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
958 PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n");
962 rte_timer_stop_sync(&adapter->timer_wd);
963 ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
964 ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
966 if (adapter->trigger_reset) {
967 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
969 PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc);
972 rte_intr_disable(intr_handle);
974 rte_intr_efd_disable(intr_handle);
975 if (intr_handle->intr_vec != NULL) {
976 rte_free(intr_handle->intr_vec);
977 intr_handle->intr_vec = NULL;
980 rte_intr_enable(intr_handle);
982 ++adapter->dev_stats.dev_stop;
983 adapter->state = ENA_ADAPTER_STATE_STOPPED;
984 dev->data->dev_started = 0;
989 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring)
991 struct ena_adapter *adapter = ring->adapter;
992 struct ena_com_dev *ena_dev = &adapter->ena_dev;
993 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
994 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
995 struct ena_com_create_io_ctx ctx =
996 /* policy set to _HOST just to satisfy icc compiler */
997 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1003 ctx.msix_vector = -1;
1004 if (ring->type == ENA_RING_TYPE_TX) {
1005 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1006 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1007 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1008 for (i = 0; i < ring->ring_size; i++)
1009 ring->empty_tx_reqs[i] = i;
1011 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1012 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1013 if (rte_intr_dp_is_en(intr_handle))
1014 ctx.msix_vector = intr_handle->intr_vec[ring->id];
1015 for (i = 0; i < ring->ring_size; i++)
1016 ring->empty_rx_reqs[i] = i;
1018 ctx.queue_size = ring->ring_size;
1020 ctx.numa_node = ring->numa_socket_id;
1022 rc = ena_com_create_io_queue(ena_dev, &ctx);
1025 "Failed to create IO queue[%d] (qid:%d), rc: %d\n",
1026 ring->id, ena_qid, rc);
1030 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1031 &ring->ena_com_io_sq,
1032 &ring->ena_com_io_cq);
1035 "Failed to get IO queue[%d] handlers, rc: %d\n",
1037 ena_com_destroy_io_queue(ena_dev, ena_qid);
1041 if (ring->type == ENA_RING_TYPE_TX)
1042 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1044 /* Start with Rx interrupts being masked. */
1045 if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle))
1046 ena_rx_queue_intr_disable(dev, ring->id);
1051 static void ena_queue_stop(struct ena_ring *ring)
1053 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1055 if (ring->type == ENA_RING_TYPE_RX) {
1056 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1057 ena_rx_queue_release_bufs(ring);
1059 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1060 ena_tx_queue_release_bufs(ring);
1064 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1065 enum ena_ring_type ring_type)
1067 struct ena_adapter *adapter = dev->data->dev_private;
1068 struct ena_ring *queues = NULL;
1069 uint16_t nb_queues, i;
1071 if (ring_type == ENA_RING_TYPE_RX) {
1072 queues = adapter->rx_ring;
1073 nb_queues = dev->data->nb_rx_queues;
1075 queues = adapter->tx_ring;
1076 nb_queues = dev->data->nb_tx_queues;
1079 for (i = 0; i < nb_queues; ++i)
1080 if (queues[i].configured)
1081 ena_queue_stop(&queues[i]);
1084 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring)
1088 ena_assert_msg(ring->configured == 1,
1089 "Trying to start unconfigured queue\n");
1091 rc = ena_create_io_queue(dev, ring);
1093 PMD_INIT_LOG(ERR, "Failed to create IO queue\n");
1097 ring->next_to_clean = 0;
1098 ring->next_to_use = 0;
1100 if (ring->type == ENA_RING_TYPE_TX) {
1101 ring->tx_stats.available_desc =
1102 ena_com_free_q_entries(ring->ena_com_io_sq);
1106 bufs_num = ring->ring_size - 1;
1107 rc = ena_populate_rx_queue(ring, bufs_num);
1108 if (rc != bufs_num) {
1109 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1110 ENA_IO_RXQ_IDX(ring->id));
1111 PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n");
1112 return ENA_COM_FAULT;
1114 /* Flush per-core RX buffers pools cache as they can be used on other
1117 rte_mempool_cache_flush(NULL, ring->mb_pool);
1122 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1125 unsigned int socket_id,
1126 const struct rte_eth_txconf *tx_conf)
1128 struct ena_ring *txq = NULL;
1129 struct ena_adapter *adapter = dev->data->dev_private;
1131 uint16_t dyn_thresh;
1133 txq = &adapter->tx_ring[queue_idx];
1135 if (txq->configured) {
1137 "API violation. Queue[%d] is already configured\n",
1139 return ENA_COM_FAULT;
1142 if (!rte_is_power_of_2(nb_desc)) {
1144 "Unsupported size of Tx queue: %d is not a power of 2.\n",
1149 if (nb_desc > adapter->max_tx_ring_size) {
1151 "Unsupported size of Tx queue (max size: %d)\n",
1152 adapter->max_tx_ring_size);
1156 txq->port_id = dev->data->port_id;
1157 txq->next_to_clean = 0;
1158 txq->next_to_use = 0;
1159 txq->ring_size = nb_desc;
1160 txq->size_mask = nb_desc - 1;
1161 txq->numa_socket_id = socket_id;
1162 txq->pkts_without_db = false;
1164 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1165 sizeof(struct ena_tx_buffer) *
1167 RTE_CACHE_LINE_SIZE);
1168 if (!txq->tx_buffer_info) {
1170 "Failed to allocate memory for Tx buffer info\n");
1174 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1175 sizeof(u16) * txq->ring_size,
1176 RTE_CACHE_LINE_SIZE);
1177 if (!txq->empty_tx_reqs) {
1179 "Failed to allocate memory for empty Tx requests\n");
1180 rte_free(txq->tx_buffer_info);
1184 txq->push_buf_intermediate_buf =
1185 rte_zmalloc("txq->push_buf_intermediate_buf",
1186 txq->tx_max_header_size,
1187 RTE_CACHE_LINE_SIZE);
1188 if (!txq->push_buf_intermediate_buf) {
1189 PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n");
1190 rte_free(txq->tx_buffer_info);
1191 rte_free(txq->empty_tx_reqs);
1195 for (i = 0; i < txq->ring_size; i++)
1196 txq->empty_tx_reqs[i] = i;
1198 txq->offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1200 /* Check if caller provided the Tx cleanup threshold value. */
1201 if (tx_conf->tx_free_thresh != 0) {
1202 txq->tx_free_thresh = tx_conf->tx_free_thresh;
1204 dyn_thresh = txq->ring_size -
1205 txq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1206 txq->tx_free_thresh = RTE_MAX(dyn_thresh,
1207 txq->ring_size - ENA_REFILL_THRESH_PACKET);
1210 /* Store pointer to this queue in upper layer */
1211 txq->configured = 1;
1212 dev->data->tx_queues[queue_idx] = txq;
1217 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1220 unsigned int socket_id,
1221 const struct rte_eth_rxconf *rx_conf,
1222 struct rte_mempool *mp)
1224 struct ena_adapter *adapter = dev->data->dev_private;
1225 struct ena_ring *rxq = NULL;
1228 uint16_t dyn_thresh;
1230 rxq = &adapter->rx_ring[queue_idx];
1231 if (rxq->configured) {
1233 "API violation. Queue[%d] is already configured\n",
1235 return ENA_COM_FAULT;
1238 if (!rte_is_power_of_2(nb_desc)) {
1240 "Unsupported size of Rx queue: %d is not a power of 2.\n",
1245 if (nb_desc > adapter->max_rx_ring_size) {
1247 "Unsupported size of Rx queue (max size: %d)\n",
1248 adapter->max_rx_ring_size);
1252 /* ENA isn't supporting buffers smaller than 1400 bytes */
1253 buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1254 if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1256 "Unsupported size of Rx buffer: %zu (min size: %d)\n",
1257 buffer_size, ENA_RX_BUF_MIN_SIZE);
1261 rxq->port_id = dev->data->port_id;
1262 rxq->next_to_clean = 0;
1263 rxq->next_to_use = 0;
1264 rxq->ring_size = nb_desc;
1265 rxq->size_mask = nb_desc - 1;
1266 rxq->numa_socket_id = socket_id;
1269 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1270 sizeof(struct ena_rx_buffer) * nb_desc,
1271 RTE_CACHE_LINE_SIZE);
1272 if (!rxq->rx_buffer_info) {
1274 "Failed to allocate memory for Rx buffer info\n");
1278 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1279 sizeof(struct rte_mbuf *) * nb_desc,
1280 RTE_CACHE_LINE_SIZE);
1282 if (!rxq->rx_refill_buffer) {
1284 "Failed to allocate memory for Rx refill buffer\n");
1285 rte_free(rxq->rx_buffer_info);
1286 rxq->rx_buffer_info = NULL;
1290 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1291 sizeof(uint16_t) * nb_desc,
1292 RTE_CACHE_LINE_SIZE);
1293 if (!rxq->empty_rx_reqs) {
1295 "Failed to allocate memory for empty Rx requests\n");
1296 rte_free(rxq->rx_buffer_info);
1297 rxq->rx_buffer_info = NULL;
1298 rte_free(rxq->rx_refill_buffer);
1299 rxq->rx_refill_buffer = NULL;
1303 for (i = 0; i < nb_desc; i++)
1304 rxq->empty_rx_reqs[i] = i;
1306 rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1308 if (rx_conf->rx_free_thresh != 0) {
1309 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1311 dyn_thresh = rxq->ring_size / ENA_REFILL_THRESH_DIVIDER;
1312 rxq->rx_free_thresh = RTE_MIN(dyn_thresh,
1313 (uint16_t)(ENA_REFILL_THRESH_PACKET));
1316 /* Store pointer to this queue in upper layer */
1317 rxq->configured = 1;
1318 dev->data->rx_queues[queue_idx] = rxq;
1323 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1324 struct rte_mbuf *mbuf, uint16_t id)
1326 struct ena_com_buf ebuf;
1329 /* prepare physical address for DMA transaction */
1330 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1331 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1333 /* pass resource to device */
1334 rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1335 if (unlikely(rc != 0))
1336 PMD_RX_LOG(WARNING, "Failed adding Rx desc\n");
1341 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1345 uint16_t next_to_use = rxq->next_to_use;
1347 #ifdef RTE_ETHDEV_DEBUG_RX
1350 struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1352 if (unlikely(!count))
1355 #ifdef RTE_ETHDEV_DEBUG_RX
1356 in_use = rxq->ring_size - 1 -
1357 ena_com_free_q_entries(rxq->ena_com_io_sq);
1358 if (unlikely((in_use + count) >= rxq->ring_size))
1359 PMD_RX_LOG(ERR, "Bad Rx ring state\n");
1362 /* get resources for incoming packets */
1363 rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1364 if (unlikely(rc < 0)) {
1365 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1366 ++rxq->rx_stats.mbuf_alloc_fail;
1367 PMD_RX_LOG(DEBUG, "There are not enough free buffers\n");
1371 for (i = 0; i < count; i++) {
1372 struct rte_mbuf *mbuf = mbufs[i];
1373 struct ena_rx_buffer *rx_info;
1375 if (likely((i + 4) < count))
1376 rte_prefetch0(mbufs[i + 4]);
1378 req_id = rxq->empty_rx_reqs[next_to_use];
1379 rx_info = &rxq->rx_buffer_info[req_id];
1381 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1382 if (unlikely(rc != 0))
1385 rx_info->mbuf = mbuf;
1386 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1389 if (unlikely(i < count)) {
1391 "Refilled Rx queue[%d] with only %d/%d buffers\n",
1393 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1394 ++rxq->rx_stats.refill_partial;
1397 /* When we submitted free recources to device... */
1398 if (likely(i > 0)) {
1399 /* ...let HW know that it can fill buffers with data. */
1400 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1402 rxq->next_to_use = next_to_use;
1408 static int ena_device_init(struct ena_com_dev *ena_dev,
1409 struct rte_pci_device *pdev,
1410 struct ena_com_dev_get_features_ctx *get_feat_ctx,
1413 uint32_t aenq_groups;
1415 bool readless_supported;
1417 /* Initialize mmio registers */
1418 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1420 PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n");
1424 /* The PCIe configuration space revision id indicate if mmio reg
1427 readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ);
1428 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1431 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1433 PMD_DRV_LOG(ERR, "Cannot reset device\n");
1434 goto err_mmio_read_less;
1437 /* check FW version */
1438 rc = ena_com_validate_version(ena_dev);
1440 PMD_DRV_LOG(ERR, "Device version is too low\n");
1441 goto err_mmio_read_less;
1444 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1446 /* ENA device administration layer init */
1447 rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1450 "Cannot initialize ENA admin queue\n");
1451 goto err_mmio_read_less;
1454 /* To enable the msix interrupts the driver needs to know the number
1455 * of queues. So the driver uses polling mode to retrieve this
1458 ena_com_set_admin_polling_mode(ena_dev, true);
1460 ena_config_host_info(ena_dev);
1462 /* Get Device Attributes and features */
1463 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1466 "Cannot get attribute for ENA device, rc: %d\n", rc);
1467 goto err_admin_init;
1470 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1471 BIT(ENA_ADMIN_NOTIFICATION) |
1472 BIT(ENA_ADMIN_KEEP_ALIVE) |
1473 BIT(ENA_ADMIN_FATAL_ERROR) |
1474 BIT(ENA_ADMIN_WARNING);
1476 aenq_groups &= get_feat_ctx->aenq.supported_groups;
1477 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1479 PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc: %d\n", rc);
1480 goto err_admin_init;
1483 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1488 ena_com_admin_destroy(ena_dev);
1491 ena_com_mmio_reg_read_request_destroy(ena_dev);
1496 static void ena_interrupt_handler_rte(void *cb_arg)
1498 struct rte_eth_dev *dev = cb_arg;
1499 struct ena_adapter *adapter = dev->data->dev_private;
1500 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1502 ena_com_admin_q_comp_intr_handler(ena_dev);
1503 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1504 ena_com_aenq_intr_handler(ena_dev, dev);
1507 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1509 if (!adapter->wd_state)
1512 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1515 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1516 adapter->keep_alive_timeout)) {
1517 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1518 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1519 adapter->trigger_reset = true;
1520 ++adapter->dev_stats.wd_expired;
1524 /* Check if admin queue is enabled */
1525 static void check_for_admin_com_state(struct ena_adapter *adapter)
1527 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1528 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n");
1529 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1530 adapter->trigger_reset = true;
1534 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1537 struct rte_eth_dev *dev = arg;
1538 struct ena_adapter *adapter = dev->data->dev_private;
1540 check_for_missing_keep_alive(adapter);
1541 check_for_admin_com_state(adapter);
1543 if (unlikely(adapter->trigger_reset)) {
1544 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1545 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1551 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1552 struct ena_admin_feature_llq_desc *llq,
1553 bool use_large_llq_hdr)
1555 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1556 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1557 llq_config->llq_num_decs_before_header =
1558 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1560 if (use_large_llq_hdr &&
1561 (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1562 llq_config->llq_ring_entry_size =
1563 ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1564 llq_config->llq_ring_entry_size_value = 256;
1566 llq_config->llq_ring_entry_size =
1567 ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1568 llq_config->llq_ring_entry_size_value = 128;
1573 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1574 struct ena_com_dev *ena_dev,
1575 struct ena_admin_feature_llq_desc *llq,
1576 struct ena_llq_configurations *llq_default_configurations)
1579 u32 llq_feature_mask;
1581 llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1582 if (!(ena_dev->supported_features & llq_feature_mask)) {
1584 "LLQ is not supported. Fallback to host mode policy.\n");
1585 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1589 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1591 PMD_INIT_LOG(WARNING,
1592 "Failed to config dev mode. Fallback to host mode policy.\n");
1593 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1597 /* Nothing to config, exit */
1598 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1601 if (!adapter->dev_mem_base) {
1603 "Unable to access LLQ BAR resource. Fallback to host mode policy.\n");
1604 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1608 ena_dev->mem_bar = adapter->dev_mem_base;
1613 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1614 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1616 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1618 /* Regular queues capabilities */
1619 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1620 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1621 &get_feat_ctx->max_queue_ext.max_queue_ext;
1622 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1623 max_queue_ext->max_rx_cq_num);
1624 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1625 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1627 struct ena_admin_queue_feature_desc *max_queues =
1628 &get_feat_ctx->max_queues;
1629 io_tx_sq_num = max_queues->max_sq_num;
1630 io_tx_cq_num = max_queues->max_cq_num;
1631 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1634 /* In case of LLQ use the llq number in the get feature cmd */
1635 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1636 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1638 max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1639 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1640 max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1642 if (unlikely(max_num_io_queues == 0)) {
1643 PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n");
1647 return max_num_io_queues;
1651 ena_set_offloads(struct ena_offloads *offloads,
1652 struct ena_admin_feature_offload_desc *offload_desc)
1654 if (offload_desc->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1655 offloads->tx_offloads |= ENA_IPV4_TSO;
1657 /* Tx IPv4 checksum offloads */
1658 if (offload_desc->tx &
1659 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)
1660 offloads->tx_offloads |= ENA_L3_IPV4_CSUM;
1661 if (offload_desc->tx &
1662 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK)
1663 offloads->tx_offloads |= ENA_L4_IPV4_CSUM;
1664 if (offload_desc->tx &
1665 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1666 offloads->tx_offloads |= ENA_L4_IPV4_CSUM_PARTIAL;
1668 /* Tx IPv6 checksum offloads */
1669 if (offload_desc->tx &
1670 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK)
1671 offloads->tx_offloads |= ENA_L4_IPV6_CSUM;
1672 if (offload_desc->tx &
1673 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
1674 offloads->tx_offloads |= ENA_L4_IPV6_CSUM_PARTIAL;
1676 /* Rx IPv4 checksum offloads */
1677 if (offload_desc->rx_supported &
1678 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)
1679 offloads->rx_offloads |= ENA_L3_IPV4_CSUM;
1680 if (offload_desc->rx_supported &
1681 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1682 offloads->rx_offloads |= ENA_L4_IPV4_CSUM;
1684 /* Rx IPv6 checksum offloads */
1685 if (offload_desc->rx_supported &
1686 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
1687 offloads->rx_offloads |= ENA_L4_IPV6_CSUM;
1689 if (offload_desc->rx_supported &
1690 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK)
1691 offloads->rx_offloads |= ENA_RX_RSS_HASH;
1694 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1696 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1697 struct rte_pci_device *pci_dev;
1698 struct rte_intr_handle *intr_handle;
1699 struct ena_adapter *adapter = eth_dev->data->dev_private;
1700 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1701 struct ena_com_dev_get_features_ctx get_feat_ctx;
1702 struct ena_llq_configurations llq_config;
1703 const char *queue_type_str;
1704 uint32_t max_num_io_queues;
1706 static int adapters_found;
1707 bool disable_meta_caching;
1708 bool wd_state = false;
1710 eth_dev->dev_ops = &ena_dev_ops;
1711 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1712 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1713 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts;
1715 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1718 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1720 memset(adapter, 0, sizeof(struct ena_adapter));
1721 ena_dev = &adapter->ena_dev;
1723 adapter->edev_data = eth_dev->data;
1725 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1727 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
1728 pci_dev->addr.domain,
1730 pci_dev->addr.devid,
1731 pci_dev->addr.function);
1733 intr_handle = &pci_dev->intr_handle;
1735 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1736 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1738 if (!adapter->regs) {
1739 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
1744 ena_dev->reg_bar = adapter->regs;
1745 /* This is a dummy pointer for ena_com functions. */
1746 ena_dev->dmadev = adapter;
1748 adapter->id_number = adapters_found;
1750 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1751 adapter->id_number);
1753 rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1755 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1759 /* device specific initialization routine */
1760 rc = ena_device_init(ena_dev, pci_dev, &get_feat_ctx, &wd_state);
1762 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
1765 adapter->wd_state = wd_state;
1767 set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1768 adapter->use_large_llq_hdr);
1769 rc = ena_set_queues_placement_policy(adapter, ena_dev,
1770 &get_feat_ctx.llq, &llq_config);
1772 PMD_INIT_LOG(CRIT, "Failed to set placement policy\n");
1776 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1777 queue_type_str = "Regular";
1779 queue_type_str = "Low latency";
1780 PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1782 calc_queue_ctx.ena_dev = ena_dev;
1783 calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1785 max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1786 rc = ena_calc_io_queue_size(&calc_queue_ctx,
1787 adapter->use_large_llq_hdr);
1788 if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1790 goto err_device_destroy;
1793 adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1794 adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1795 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1796 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1797 adapter->max_num_io_queues = max_num_io_queues;
1799 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1800 disable_meta_caching =
1801 !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1802 BIT(ENA_ADMIN_DISABLE_META_CACHING));
1804 disable_meta_caching = false;
1807 /* prepare ring structures */
1808 ena_init_rings(adapter, disable_meta_caching);
1810 ena_config_debug_area(adapter);
1812 /* Set max MTU for this device */
1813 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1815 ena_set_offloads(&adapter->offloads, &get_feat_ctx.offload);
1817 /* Copy MAC address and point DPDK to it */
1818 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1819 rte_ether_addr_copy((struct rte_ether_addr *)
1820 get_feat_ctx.dev_attr.mac_addr,
1821 (struct rte_ether_addr *)adapter->mac_addr);
1823 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
1824 if (unlikely(rc != 0)) {
1825 PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n");
1826 goto err_delete_debug_area;
1829 adapter->drv_stats = rte_zmalloc("adapter stats",
1830 sizeof(*adapter->drv_stats),
1831 RTE_CACHE_LINE_SIZE);
1832 if (!adapter->drv_stats) {
1834 "Failed to allocate memory for adapter statistics\n");
1836 goto err_rss_destroy;
1839 rte_spinlock_init(&adapter->admin_lock);
1841 rte_intr_callback_register(intr_handle,
1842 ena_interrupt_handler_rte,
1844 rte_intr_enable(intr_handle);
1845 ena_com_set_admin_polling_mode(ena_dev, false);
1846 ena_com_admin_aenq_enable(ena_dev);
1848 if (adapters_found == 0)
1849 rte_timer_subsystem_init();
1850 rte_timer_init(&adapter->timer_wd);
1853 adapter->state = ENA_ADAPTER_STATE_INIT;
1858 ena_com_rss_destroy(ena_dev);
1859 err_delete_debug_area:
1860 ena_com_delete_debug_area(ena_dev);
1863 ena_com_delete_host_info(ena_dev);
1864 ena_com_admin_destroy(ena_dev);
1870 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1872 struct ena_adapter *adapter = eth_dev->data->dev_private;
1873 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1875 if (adapter->state == ENA_ADAPTER_STATE_FREE)
1878 ena_com_set_admin_running_state(ena_dev, false);
1880 if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1883 ena_com_rss_destroy(ena_dev);
1885 ena_com_delete_debug_area(ena_dev);
1886 ena_com_delete_host_info(ena_dev);
1888 ena_com_abort_admin_commands(ena_dev);
1889 ena_com_wait_for_abort_completion(ena_dev);
1890 ena_com_admin_destroy(ena_dev);
1891 ena_com_mmio_reg_read_request_destroy(ena_dev);
1893 adapter->state = ENA_ADAPTER_STATE_FREE;
1896 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1898 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1901 ena_destroy_device(eth_dev);
1906 static int ena_dev_configure(struct rte_eth_dev *dev)
1908 struct ena_adapter *adapter = dev->data->dev_private;
1910 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1912 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1913 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1914 dev->data->dev_conf.txmode.offloads |= DEV_TX_OFFLOAD_MULTI_SEGS;
1916 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1917 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1921 static void ena_init_rings(struct ena_adapter *adapter,
1922 bool disable_meta_caching)
1926 for (i = 0; i < adapter->max_num_io_queues; i++) {
1927 struct ena_ring *ring = &adapter->tx_ring[i];
1929 ring->configured = 0;
1930 ring->type = ENA_RING_TYPE_TX;
1931 ring->adapter = adapter;
1933 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1934 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1935 ring->sgl_size = adapter->max_tx_sgl_size;
1936 ring->disable_meta_caching = disable_meta_caching;
1939 for (i = 0; i < adapter->max_num_io_queues; i++) {
1940 struct ena_ring *ring = &adapter->rx_ring[i];
1942 ring->configured = 0;
1943 ring->type = ENA_RING_TYPE_RX;
1944 ring->adapter = adapter;
1946 ring->sgl_size = adapter->max_rx_sgl_size;
1950 static int ena_infos_get(struct rte_eth_dev *dev,
1951 struct rte_eth_dev_info *dev_info)
1953 struct ena_adapter *adapter;
1954 struct ena_com_dev *ena_dev;
1955 uint64_t rx_feat = 0, tx_feat = 0;
1957 ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1958 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1959 adapter = dev->data->dev_private;
1961 ena_dev = &adapter->ena_dev;
1962 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1964 dev_info->speed_capa =
1966 ETH_LINK_SPEED_2_5G |
1968 ETH_LINK_SPEED_10G |
1969 ETH_LINK_SPEED_25G |
1970 ETH_LINK_SPEED_40G |
1971 ETH_LINK_SPEED_50G |
1972 ETH_LINK_SPEED_100G;
1974 /* Set Tx & Rx features available for device */
1975 if (adapter->offloads.tx_offloads & ENA_IPV4_TSO)
1976 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1978 if (adapter->offloads.tx_offloads & ENA_L3_IPV4_CSUM)
1979 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM;
1980 if (adapter->offloads.tx_offloads &
1981 (ENA_L4_IPV4_CSUM_PARTIAL | ENA_L4_IPV4_CSUM |
1982 ENA_L4_IPV6_CSUM | ENA_L4_IPV6_CSUM_PARTIAL))
1983 tx_feat |= DEV_TX_OFFLOAD_UDP_CKSUM | DEV_TX_OFFLOAD_TCP_CKSUM;
1985 if (adapter->offloads.rx_offloads & ENA_L3_IPV4_CSUM)
1986 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM;
1987 if (adapter->offloads.rx_offloads &
1988 (ENA_L4_IPV4_CSUM | ENA_L4_IPV6_CSUM))
1989 rx_feat |= DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM;
1991 tx_feat |= DEV_TX_OFFLOAD_MULTI_SEGS;
1993 /* Inform framework about available features */
1994 dev_info->rx_offload_capa = rx_feat;
1995 if (adapter->offloads.rx_offloads & ENA_RX_RSS_HASH)
1996 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_RSS_HASH;
1997 dev_info->rx_queue_offload_capa = rx_feat;
1998 dev_info->tx_offload_capa = tx_feat;
1999 dev_info->tx_queue_offload_capa = tx_feat;
2001 dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF;
2002 dev_info->hash_key_size = ENA_HASH_KEY_SIZE;
2004 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2005 dev_info->max_rx_pktlen = adapter->max_mtu + RTE_ETHER_HDR_LEN +
2007 dev_info->min_mtu = ENA_MIN_MTU;
2008 dev_info->max_mtu = adapter->max_mtu;
2009 dev_info->max_mac_addrs = 1;
2011 dev_info->max_rx_queues = adapter->max_num_io_queues;
2012 dev_info->max_tx_queues = adapter->max_num_io_queues;
2013 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2015 adapter->tx_supported_offloads = tx_feat;
2016 adapter->rx_supported_offloads = rx_feat;
2018 dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2019 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2020 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2021 adapter->max_rx_sgl_size);
2022 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2023 adapter->max_rx_sgl_size);
2025 dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2026 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2027 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2028 adapter->max_tx_sgl_size);
2029 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2030 adapter->max_tx_sgl_size);
2032 dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2033 dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
2038 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2040 mbuf->data_len = len;
2041 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2046 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2047 struct ena_com_rx_buf_info *ena_bufs,
2049 uint16_t *next_to_clean,
2052 struct rte_mbuf *mbuf;
2053 struct rte_mbuf *mbuf_head;
2054 struct ena_rx_buffer *rx_info;
2056 uint16_t ntc, len, req_id, buf = 0;
2058 if (unlikely(descs == 0))
2061 ntc = *next_to_clean;
2063 len = ena_bufs[buf].len;
2064 req_id = ena_bufs[buf].req_id;
2066 rx_info = &rx_ring->rx_buffer_info[req_id];
2068 mbuf = rx_info->mbuf;
2069 RTE_ASSERT(mbuf != NULL);
2071 ena_init_rx_mbuf(mbuf, len);
2073 /* Fill the mbuf head with the data specific for 1st segment. */
2075 mbuf_head->nb_segs = descs;
2076 mbuf_head->port = rx_ring->port_id;
2077 mbuf_head->pkt_len = len;
2078 mbuf_head->data_off += offset;
2080 rx_info->mbuf = NULL;
2081 rx_ring->empty_rx_reqs[ntc] = req_id;
2082 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2086 len = ena_bufs[buf].len;
2087 req_id = ena_bufs[buf].req_id;
2089 rx_info = &rx_ring->rx_buffer_info[req_id];
2090 RTE_ASSERT(rx_info->mbuf != NULL);
2092 if (unlikely(len == 0)) {
2094 * Some devices can pass descriptor with the length 0.
2095 * To avoid confusion, the PMD is simply putting the
2096 * descriptor back, as it was never used. We'll avoid
2097 * mbuf allocation that way.
2099 rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2100 rx_info->mbuf, req_id);
2101 if (unlikely(rc != 0)) {
2102 /* Free the mbuf in case of an error. */
2103 rte_mbuf_raw_free(rx_info->mbuf);
2106 * If there was no error, just exit the loop as
2107 * 0 length descriptor is always the last one.
2112 /* Create an mbuf chain. */
2113 mbuf->next = rx_info->mbuf;
2116 ena_init_rx_mbuf(mbuf, len);
2117 mbuf_head->pkt_len += len;
2121 * Mark the descriptor as depleted and perform necessary
2123 * This code will execute in two cases:
2124 * 1. Descriptor len was greater than 0 - normal situation.
2125 * 2. Descriptor len was 0 and we failed to add the descriptor
2126 * to the device. In that situation, we should try to add
2127 * the mbuf again in the populate routine and mark the
2128 * descriptor as used up by the device.
2130 rx_info->mbuf = NULL;
2131 rx_ring->empty_rx_reqs[ntc] = req_id;
2132 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2135 *next_to_clean = ntc;
2140 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2143 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2144 unsigned int free_queue_entries;
2145 uint16_t next_to_clean = rx_ring->next_to_clean;
2146 uint16_t descs_in_use;
2147 struct rte_mbuf *mbuf;
2149 struct ena_com_rx_ctx ena_rx_ctx;
2153 #ifdef RTE_ETHDEV_DEBUG_RX
2154 /* Check adapter state */
2155 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2157 "Trying to receive pkts while device is NOT running\n");
2162 fill_hash = rx_ring->offloads & DEV_RX_OFFLOAD_RSS_HASH;
2164 descs_in_use = rx_ring->ring_size -
2165 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2166 nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2168 for (completed = 0; completed < nb_pkts; completed++) {
2169 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2170 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2171 ena_rx_ctx.descs = 0;
2172 ena_rx_ctx.pkt_offset = 0;
2173 /* receive packet context */
2174 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2175 rx_ring->ena_com_io_sq,
2179 "Failed to get the packet from the device, rc: %d\n",
2181 if (rc == ENA_COM_NO_SPACE) {
2182 ++rx_ring->rx_stats.bad_desc_num;
2183 rx_ring->adapter->reset_reason =
2184 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2186 ++rx_ring->rx_stats.bad_req_id;
2187 rx_ring->adapter->reset_reason =
2188 ENA_REGS_RESET_INV_RX_REQ_ID;
2190 rx_ring->adapter->trigger_reset = true;
2194 mbuf = ena_rx_mbuf(rx_ring,
2195 ena_rx_ctx.ena_bufs,
2198 ena_rx_ctx.pkt_offset);
2199 if (unlikely(mbuf == NULL)) {
2200 for (i = 0; i < ena_rx_ctx.descs; ++i) {
2201 rx_ring->empty_rx_reqs[next_to_clean] =
2202 rx_ring->ena_bufs[i].req_id;
2203 next_to_clean = ENA_IDX_NEXT_MASKED(
2204 next_to_clean, rx_ring->size_mask);
2209 /* fill mbuf attributes if any */
2210 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx, fill_hash);
2212 if (unlikely(mbuf->ol_flags &
2213 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2214 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2215 ++rx_ring->rx_stats.bad_csum;
2218 rx_pkts[completed] = mbuf;
2219 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2222 rx_ring->rx_stats.cnt += completed;
2223 rx_ring->next_to_clean = next_to_clean;
2225 free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2227 /* Burst refill to save doorbells, memory barriers, const interval */
2228 if (free_queue_entries >= rx_ring->rx_free_thresh) {
2229 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2230 ena_populate_rx_queue(rx_ring, free_queue_entries);
2237 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2243 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2244 struct ena_adapter *adapter = tx_ring->adapter;
2245 struct rte_ipv4_hdr *ip_hdr;
2247 uint64_t l4_csum_flag;
2248 uint64_t dev_offload_capa;
2249 uint16_t frag_field;
2250 bool need_pseudo_csum;
2252 dev_offload_capa = adapter->offloads.tx_offloads;
2253 for (i = 0; i != nb_pkts; i++) {
2255 ol_flags = m->ol_flags;
2257 /* Check if any offload flag was set */
2261 l4_csum_flag = ol_flags & PKT_TX_L4_MASK;
2262 /* SCTP checksum offload is not supported by the ENA. */
2263 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) ||
2264 l4_csum_flag == PKT_TX_SCTP_CKSUM) {
2266 "mbuf[%" PRIu32 "] has unsupported offloads flags set: 0x%" PRIu64 "\n",
2268 rte_errno = ENOTSUP;
2272 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2273 /* Check if requested offload is also enabled for the queue */
2274 if ((ol_flags & PKT_TX_IP_CKSUM &&
2275 !(tx_ring->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) ||
2276 (l4_csum_flag == PKT_TX_TCP_CKSUM &&
2277 !(tx_ring->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) ||
2278 (l4_csum_flag == PKT_TX_UDP_CKSUM &&
2279 !(tx_ring->offloads & DEV_TX_OFFLOAD_UDP_CKSUM))) {
2281 "mbuf[%" PRIu32 "]: requested offloads: %" PRIu16 " are not enabled for the queue[%u]\n",
2282 i, m->nb_segs, tx_ring->id);
2287 /* The caller is obligated to set l2 and l3 len if any cksum
2288 * offload is enabled.
2290 if (unlikely(ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK) &&
2291 (m->l2_len == 0 || m->l3_len == 0))) {
2293 "mbuf[%" PRIu32 "]: l2_len or l3_len values are 0 while the offload was requested\n",
2298 ret = rte_validate_tx_offload(m);
2305 /* Verify HW support for requested offloads and determine if
2306 * pseudo header checksum is needed.
2308 need_pseudo_csum = false;
2309 if (ol_flags & PKT_TX_IPV4) {
2310 if (ol_flags & PKT_TX_IP_CKSUM &&
2311 !(dev_offload_capa & ENA_L3_IPV4_CSUM)) {
2312 rte_errno = ENOTSUP;
2316 if (ol_flags & PKT_TX_TCP_SEG &&
2317 !(dev_offload_capa & ENA_IPV4_TSO)) {
2318 rte_errno = ENOTSUP;
2322 /* Check HW capabilities and if pseudo csum is needed
2325 if (l4_csum_flag != PKT_TX_L4_NO_CKSUM &&
2326 !(dev_offload_capa & ENA_L4_IPV4_CSUM)) {
2327 if (dev_offload_capa &
2328 ENA_L4_IPV4_CSUM_PARTIAL) {
2329 need_pseudo_csum = true;
2331 rte_errno = ENOTSUP;
2336 /* Parse the DF flag */
2337 ip_hdr = rte_pktmbuf_mtod_offset(m,
2338 struct rte_ipv4_hdr *, m->l2_len);
2339 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2340 if (frag_field & RTE_IPV4_HDR_DF_FLAG) {
2341 m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2342 } else if (ol_flags & PKT_TX_TCP_SEG) {
2343 /* In case we are supposed to TSO and have DF
2344 * not set (DF=0) hardware must be provided with
2347 need_pseudo_csum = true;
2349 } else if (ol_flags & PKT_TX_IPV6) {
2350 /* There is no support for IPv6 TSO as for now. */
2351 if (ol_flags & PKT_TX_TCP_SEG) {
2352 rte_errno = ENOTSUP;
2356 /* Check HW capabilities and if pseudo csum is needed */
2357 if (l4_csum_flag != PKT_TX_L4_NO_CKSUM &&
2358 !(dev_offload_capa & ENA_L4_IPV6_CSUM)) {
2359 if (dev_offload_capa &
2360 ENA_L4_IPV6_CSUM_PARTIAL) {
2361 need_pseudo_csum = true;
2363 rte_errno = ENOTSUP;
2369 if (need_pseudo_csum) {
2370 ret = rte_net_intel_cksum_flags_prepare(m, ol_flags);
2381 static void ena_update_hints(struct ena_adapter *adapter,
2382 struct ena_admin_ena_hw_hints *hints)
2384 if (hints->admin_completion_tx_timeout)
2385 adapter->ena_dev.admin_queue.completion_timeout =
2386 hints->admin_completion_tx_timeout * 1000;
2388 if (hints->mmio_read_timeout)
2389 /* convert to usec */
2390 adapter->ena_dev.mmio_read.reg_read_to =
2391 hints->mmio_read_timeout * 1000;
2393 if (hints->driver_watchdog_timeout) {
2394 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2395 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2397 // Convert msecs to ticks
2398 adapter->keep_alive_timeout =
2399 (hints->driver_watchdog_timeout *
2400 rte_get_timer_hz()) / 1000;
2404 static int ena_check_space_and_linearize_mbuf(struct ena_ring *tx_ring,
2405 struct rte_mbuf *mbuf)
2407 struct ena_com_dev *ena_dev;
2408 int num_segments, header_len, rc;
2410 ena_dev = &tx_ring->adapter->ena_dev;
2411 num_segments = mbuf->nb_segs;
2412 header_len = mbuf->data_len;
2414 if (likely(num_segments < tx_ring->sgl_size))
2417 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2418 (num_segments == tx_ring->sgl_size) &&
2419 (header_len < tx_ring->tx_max_header_size))
2422 /* Checking for space for 2 additional metadata descriptors due to
2423 * possible header split and metadata descriptor. Linearization will
2424 * be needed so we reduce the segments number from num_segments to 1
2426 if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 3)) {
2427 PMD_TX_LOG(DEBUG, "Not enough space in the Tx queue\n");
2428 return ENA_COM_NO_MEM;
2430 ++tx_ring->tx_stats.linearize;
2431 rc = rte_pktmbuf_linearize(mbuf);
2433 PMD_TX_LOG(WARNING, "Mbuf linearize failed\n");
2434 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2435 ++tx_ring->tx_stats.linearize_failed;
2442 /* Checking for space for 2 additional metadata descriptors due to
2443 * possible header split and metadata descriptor
2445 if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2446 num_segments + 2)) {
2447 PMD_TX_LOG(DEBUG, "Not enough space in the Tx queue\n");
2448 return ENA_COM_NO_MEM;
2454 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2455 struct ena_tx_buffer *tx_info,
2456 struct rte_mbuf *mbuf,
2458 uint16_t *header_len)
2460 struct ena_com_buf *ena_buf;
2461 uint16_t delta, seg_len, push_len;
2464 seg_len = mbuf->data_len;
2466 tx_info->mbuf = mbuf;
2467 ena_buf = tx_info->bufs;
2469 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2471 * Tx header might be (and will be in most cases) smaller than
2472 * tx_max_header_size. But it's not an issue to send more data
2473 * to the device, than actually needed if the mbuf size is
2474 * greater than tx_max_header_size.
2476 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2477 *header_len = push_len;
2479 if (likely(push_len <= seg_len)) {
2480 /* If the push header is in the single segment, then
2481 * just point it to the 1st mbuf data.
2483 *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2485 /* If the push header lays in the several segments, copy
2486 * it to the intermediate buffer.
2488 rte_pktmbuf_read(mbuf, 0, push_len,
2489 tx_ring->push_buf_intermediate_buf);
2490 *push_header = tx_ring->push_buf_intermediate_buf;
2491 delta = push_len - seg_len;
2494 *push_header = NULL;
2499 /* Process first segment taking into consideration pushed header */
2500 if (seg_len > push_len) {
2501 ena_buf->paddr = mbuf->buf_iova +
2504 ena_buf->len = seg_len - push_len;
2506 tx_info->num_of_bufs++;
2509 while ((mbuf = mbuf->next) != NULL) {
2510 seg_len = mbuf->data_len;
2512 /* Skip mbufs if whole data is pushed as a header */
2513 if (unlikely(delta > seg_len)) {
2518 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2519 ena_buf->len = seg_len - delta;
2521 tx_info->num_of_bufs++;
2527 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2529 struct ena_tx_buffer *tx_info;
2530 struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2531 uint16_t next_to_use;
2532 uint16_t header_len;
2538 rc = ena_check_space_and_linearize_mbuf(tx_ring, mbuf);
2542 next_to_use = tx_ring->next_to_use;
2544 req_id = tx_ring->empty_tx_reqs[next_to_use];
2545 tx_info = &tx_ring->tx_buffer_info[req_id];
2546 tx_info->num_of_bufs = 0;
2548 ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2550 ena_tx_ctx.ena_bufs = tx_info->bufs;
2551 ena_tx_ctx.push_header = push_header;
2552 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2553 ena_tx_ctx.req_id = req_id;
2554 ena_tx_ctx.header_len = header_len;
2556 /* Set Tx offloads flags, if applicable */
2557 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2558 tx_ring->disable_meta_caching);
2560 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2563 "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2565 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2566 tx_ring->tx_stats.doorbells++;
2567 tx_ring->pkts_without_db = false;
2570 /* prepare the packet's descriptors to dma engine */
2571 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2574 PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc);
2575 ++tx_ring->tx_stats.prepare_ctx_err;
2576 tx_ring->adapter->reset_reason =
2577 ENA_REGS_RESET_DRIVER_INVALID_STATE;
2578 tx_ring->adapter->trigger_reset = true;
2582 tx_info->tx_descs = nb_hw_desc;
2584 tx_ring->tx_stats.cnt++;
2585 tx_ring->tx_stats.bytes += mbuf->pkt_len;
2587 tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2588 tx_ring->size_mask);
2593 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2595 unsigned int total_tx_descs = 0;
2596 uint16_t cleanup_budget;
2597 uint16_t next_to_clean = tx_ring->next_to_clean;
2599 /* Attempt to release all Tx descriptors (ring_size - 1 -> size_mask) */
2600 cleanup_budget = tx_ring->size_mask;
2602 while (likely(total_tx_descs < cleanup_budget)) {
2603 struct rte_mbuf *mbuf;
2604 struct ena_tx_buffer *tx_info;
2607 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2610 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2613 /* Get Tx info & store how many descs were processed */
2614 tx_info = &tx_ring->tx_buffer_info[req_id];
2616 mbuf = tx_info->mbuf;
2617 rte_pktmbuf_free(mbuf);
2619 tx_info->mbuf = NULL;
2620 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2622 total_tx_descs += tx_info->tx_descs;
2624 /* Put back descriptor to the ring for reuse */
2625 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2626 tx_ring->size_mask);
2629 if (likely(total_tx_descs > 0)) {
2630 /* acknowledge completion of sent packets */
2631 tx_ring->next_to_clean = next_to_clean;
2632 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2633 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2637 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2640 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2642 uint16_t sent_idx = 0;
2644 #ifdef RTE_ETHDEV_DEBUG_TX
2645 /* Check adapter state */
2646 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2648 "Trying to xmit pkts while device is NOT running\n");
2653 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2654 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2656 tx_ring->pkts_without_db = true;
2657 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2658 tx_ring->size_mask)]);
2661 available_desc = ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2662 tx_ring->tx_stats.available_desc = available_desc;
2664 /* If there are ready packets to be xmitted... */
2665 if (likely(tx_ring->pkts_without_db)) {
2666 /* ...let HW do its best :-) */
2667 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2668 tx_ring->tx_stats.doorbells++;
2669 tx_ring->pkts_without_db = false;
2672 if (available_desc < tx_ring->tx_free_thresh)
2673 ena_tx_cleanup(tx_ring);
2675 tx_ring->tx_stats.available_desc =
2676 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2677 tx_ring->tx_stats.tx_poll++;
2682 int ena_copy_eni_stats(struct ena_adapter *adapter)
2684 struct ena_admin_eni_stats admin_eni_stats;
2687 rte_spinlock_lock(&adapter->admin_lock);
2688 rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2689 rte_spinlock_unlock(&adapter->admin_lock);
2691 if (rc == ENA_COM_UNSUPPORTED) {
2693 "Retrieving ENI metrics is not supported\n");
2695 PMD_DRV_LOG(WARNING,
2696 "Failed to get ENI metrics, rc: %d\n", rc);
2701 rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2702 sizeof(struct ena_stats_eni));
2708 * DPDK callback to retrieve names of extended device statistics
2711 * Pointer to Ethernet device structure.
2712 * @param[out] xstats_names
2713 * Buffer to insert names into.
2718 * Number of xstats names.
2720 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2721 struct rte_eth_xstat_name *xstats_names,
2724 unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2725 unsigned int stat, i, count = 0;
2727 if (n < xstats_count || !xstats_names)
2728 return xstats_count;
2730 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2731 strcpy(xstats_names[count].name,
2732 ena_stats_global_strings[stat].name);
2734 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2735 strcpy(xstats_names[count].name,
2736 ena_stats_eni_strings[stat].name);
2738 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2739 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2740 snprintf(xstats_names[count].name,
2741 sizeof(xstats_names[count].name),
2743 ena_stats_rx_strings[stat].name);
2745 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2746 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2747 snprintf(xstats_names[count].name,
2748 sizeof(xstats_names[count].name),
2750 ena_stats_tx_strings[stat].name);
2752 return xstats_count;
2756 * DPDK callback to get extended device statistics.
2759 * Pointer to Ethernet device structure.
2761 * Stats table output buffer.
2763 * The size of the stats table.
2766 * Number of xstats on success, negative on failure.
2768 static int ena_xstats_get(struct rte_eth_dev *dev,
2769 struct rte_eth_xstat *xstats,
2772 struct ena_adapter *adapter = dev->data->dev_private;
2773 unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2774 unsigned int stat, i, count = 0;
2778 if (n < xstats_count)
2779 return xstats_count;
2784 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2785 stat_offset = ena_stats_global_strings[stat].stat_offset;
2786 stats_begin = &adapter->dev_stats;
2788 xstats[count].id = count;
2789 xstats[count].value = *((uint64_t *)
2790 ((char *)stats_begin + stat_offset));
2793 /* Even if the function below fails, we should copy previous (or initial
2794 * values) to keep structure of rte_eth_xstat consistent.
2796 ena_copy_eni_stats(adapter);
2797 for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2798 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2799 stats_begin = &adapter->eni_stats;
2801 xstats[count].id = count;
2802 xstats[count].value = *((uint64_t *)
2803 ((char *)stats_begin + stat_offset));
2806 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2807 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2808 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2809 stats_begin = &adapter->rx_ring[i].rx_stats;
2811 xstats[count].id = count;
2812 xstats[count].value = *((uint64_t *)
2813 ((char *)stats_begin + stat_offset));
2817 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2818 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2819 stat_offset = ena_stats_tx_strings[stat].stat_offset;
2820 stats_begin = &adapter->tx_ring[i].rx_stats;
2822 xstats[count].id = count;
2823 xstats[count].value = *((uint64_t *)
2824 ((char *)stats_begin + stat_offset));
2831 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2832 const uint64_t *ids,
2836 struct ena_adapter *adapter = dev->data->dev_private;
2838 uint64_t rx_entries, tx_entries;
2842 bool was_eni_copied = false;
2844 for (i = 0; i < n; ++i) {
2846 /* Check if id belongs to global statistics */
2847 if (id < ENA_STATS_ARRAY_GLOBAL) {
2848 values[i] = *((uint64_t *)&adapter->dev_stats + id);
2853 /* Check if id belongs to ENI statistics */
2854 id -= ENA_STATS_ARRAY_GLOBAL;
2855 if (id < ENA_STATS_ARRAY_ENI) {
2856 /* Avoid reading ENI stats multiple times in a single
2857 * function call, as it requires communication with the
2860 if (!was_eni_copied) {
2861 was_eni_copied = true;
2862 ena_copy_eni_stats(adapter);
2864 values[i] = *((uint64_t *)&adapter->eni_stats + id);
2869 /* Check if id belongs to rx queue statistics */
2870 id -= ENA_STATS_ARRAY_ENI;
2871 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2872 if (id < rx_entries) {
2873 qid = id % dev->data->nb_rx_queues;
2874 id /= dev->data->nb_rx_queues;
2875 values[i] = *((uint64_t *)
2876 &adapter->rx_ring[qid].rx_stats + id);
2880 /* Check if id belongs to rx queue statistics */
2882 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2883 if (id < tx_entries) {
2884 qid = id % dev->data->nb_tx_queues;
2885 id /= dev->data->nb_tx_queues;
2886 values[i] = *((uint64_t *)
2887 &adapter->tx_ring[qid].tx_stats + id);
2896 static int ena_process_bool_devarg(const char *key,
2900 struct ena_adapter *adapter = opaque;
2903 /* Parse the value. */
2904 if (strcmp(value, "1") == 0) {
2906 } else if (strcmp(value, "0") == 0) {
2910 "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2915 /* Now, assign it to the proper adapter field. */
2916 if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
2917 adapter->use_large_llq_hdr = bool_value;
2922 static int ena_parse_devargs(struct ena_adapter *adapter,
2923 struct rte_devargs *devargs)
2925 static const char * const allowed_args[] = {
2926 ENA_DEVARG_LARGE_LLQ_HDR,
2929 struct rte_kvargs *kvlist;
2932 if (devargs == NULL)
2935 kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2936 if (kvlist == NULL) {
2937 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2942 rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2943 ena_process_bool_devarg, adapter);
2945 rte_kvargs_free(kvlist);
2950 static int ena_setup_rx_intr(struct rte_eth_dev *dev)
2952 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2953 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2955 uint16_t vectors_nb, i;
2956 bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq;
2958 if (!rx_intr_requested)
2961 if (!rte_intr_cap_multiple(intr_handle)) {
2963 "Rx interrupt requested, but it isn't supported by the PCI driver\n");
2967 /* Disable interrupt mapping before the configuration starts. */
2968 rte_intr_disable(intr_handle);
2970 /* Verify if there are enough vectors available. */
2971 vectors_nb = dev->data->nb_rx_queues;
2972 if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) {
2974 "Too many Rx interrupts requested, maximum number: %d\n",
2975 RTE_MAX_RXTX_INTR_VEC_ID);
2980 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2981 dev->data->nb_rx_queues * sizeof(*intr_handle->intr_vec), 0);
2982 if (intr_handle->intr_vec == NULL) {
2984 "Failed to allocate interrupt vector for %d queues\n",
2985 dev->data->nb_rx_queues);
2990 rc = rte_intr_efd_enable(intr_handle, vectors_nb);
2994 if (!rte_intr_allow_others(intr_handle)) {
2996 "Not enough interrupts available to use both ENA Admin and Rx interrupts\n");
2997 goto disable_intr_efd;
3000 for (i = 0; i < vectors_nb; ++i)
3001 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + i;
3003 rte_intr_enable(intr_handle);
3007 rte_intr_efd_disable(intr_handle);
3009 rte_free(intr_handle->intr_vec);
3010 intr_handle->intr_vec = NULL;
3012 rte_intr_enable(intr_handle);
3016 static void ena_rx_queue_intr_set(struct rte_eth_dev *dev,
3020 struct ena_adapter *adapter = dev->data->dev_private;
3021 struct ena_ring *rxq = &adapter->rx_ring[queue_id];
3022 struct ena_eth_io_intr_reg intr_reg;
3024 ena_com_update_intr_reg(&intr_reg, 0, 0, unmask);
3025 ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg);
3028 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
3031 ena_rx_queue_intr_set(dev, queue_id, true);
3036 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
3039 ena_rx_queue_intr_set(dev, queue_id, false);
3044 /*********************************************************************
3046 *********************************************************************/
3047 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3048 struct rte_pci_device *pci_dev)
3050 return rte_eth_dev_pci_generic_probe(pci_dev,
3051 sizeof(struct ena_adapter), eth_ena_dev_init);
3054 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
3056 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
3059 static struct rte_pci_driver rte_ena_pmd = {
3060 .id_table = pci_id_ena_map,
3061 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3062 RTE_PCI_DRV_WC_ACTIVATE,
3063 .probe = eth_ena_pci_probe,
3064 .remove = eth_ena_pci_remove,
3067 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
3068 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
3069 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
3070 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
3071 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
3072 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
3073 #ifdef RTE_ETHDEV_DEBUG_RX
3074 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG);
3076 #ifdef RTE_ETHDEV_DEBUG_TX
3077 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG);
3079 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING);
3081 /******************************************************************************
3082 ******************************** AENQ Handlers *******************************
3083 *****************************************************************************/
3084 static void ena_update_on_link_change(void *adapter_data,
3085 struct ena_admin_aenq_entry *aenq_e)
3087 struct rte_eth_dev *eth_dev = adapter_data;
3088 struct ena_adapter *adapter = eth_dev->data->dev_private;
3089 struct ena_admin_aenq_link_change_desc *aenq_link_desc;
3092 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
3094 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
3095 adapter->link_status = status;
3097 ena_link_update(eth_dev, 0);
3098 rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3101 static void ena_notification(void *adapter_data,
3102 struct ena_admin_aenq_entry *aenq_e)
3104 struct rte_eth_dev *eth_dev = adapter_data;
3105 struct ena_adapter *adapter = eth_dev->data->dev_private;
3106 struct ena_admin_ena_hw_hints *hints;
3108 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
3109 PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n",
3110 aenq_e->aenq_common_desc.group,
3111 ENA_ADMIN_NOTIFICATION);
3113 switch (aenq_e->aenq_common_desc.syndrome) {
3114 case ENA_ADMIN_UPDATE_HINTS:
3115 hints = (struct ena_admin_ena_hw_hints *)
3116 (&aenq_e->inline_data_w4);
3117 ena_update_hints(adapter, hints);
3120 PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n",
3121 aenq_e->aenq_common_desc.syndrome);
3125 static void ena_keep_alive(void *adapter_data,
3126 __rte_unused struct ena_admin_aenq_entry *aenq_e)
3128 struct rte_eth_dev *eth_dev = adapter_data;
3129 struct ena_adapter *adapter = eth_dev->data->dev_private;
3130 struct ena_admin_aenq_keep_alive_desc *desc;
3134 adapter->timestamp_wd = rte_get_timer_cycles();
3136 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
3137 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
3138 tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
3140 adapter->drv_stats->rx_drops = rx_drops;
3141 adapter->dev_stats.tx_drops = tx_drops;
3145 * This handler will called for unknown event group or unimplemented handlers
3147 static void unimplemented_aenq_handler(__rte_unused void *data,
3148 __rte_unused struct ena_admin_aenq_entry *aenq_e)
3151 "Unknown event was received or event with unimplemented handler\n");
3154 static struct ena_aenq_handlers aenq_handlers = {
3156 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3157 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3158 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3160 .unimplemented_handler = unimplemented_aenq_handler