1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Huawei Technologies Co., Ltd
6 #include <rte_bus_pci.h>
7 #include <rte_ethdev_pci.h>
9 #include <rte_malloc.h>
10 #include <rte_memcpy.h>
11 #include <rte_mempool.h>
12 #include <rte_errno.h>
14 #include "base/hinic_compat.h"
15 #include "base/hinic_pmd_hwdev.h"
16 #include "base/hinic_pmd_hwif.h"
17 #include "base/hinic_pmd_wq.h"
18 #include "base/hinic_pmd_cfg.h"
19 #include "base/hinic_pmd_mgmt.h"
20 #include "base/hinic_pmd_cmdq.h"
21 #include "base/hinic_pmd_niccfg.h"
22 #include "base/hinic_pmd_nicio.h"
23 #include "hinic_pmd_ethdev.h"
24 #include "hinic_pmd_tx.h"
25 #include "hinic_pmd_rx.h"
27 /* Vendor ID used by Huawei devices */
28 #define HINIC_HUAWEI_VENDOR_ID 0x19E5
31 #define HINIC_DEV_ID_PRD 0x1822
32 #define HINIC_DEV_ID_MEZZ_25GE 0x0210
33 #define HINIC_DEV_ID_MEZZ_40GE 0x020D
34 #define HINIC_DEV_ID_MEZZ_100GE 0x0205
36 #define HINIC_SERVICE_MODE_NIC 2
38 #define HINIC_INTR_CB_UNREG_MAX_RETRIES 10
40 #define DEFAULT_BASE_COS 4
43 #define HINIC_MIN_RX_BUF_SIZE 1024
44 #define HINIC_MAX_MAC_ADDRS 1
46 /** Driver-specific log messages type. */
49 struct hinic_xstats_name_off {
50 char name[RTE_ETH_XSTATS_NAME_SIZE];
54 #define HINIC_FUNC_STAT(_stat_item) { \
55 .name = #_stat_item, \
56 .offset = offsetof(struct hinic_vport_stats, _stat_item) \
59 #define HINIC_PORT_STAT(_stat_item) { \
60 .name = #_stat_item, \
61 .offset = offsetof(struct hinic_phy_port_stats, _stat_item) \
64 static const struct hinic_xstats_name_off hinic_vport_stats_strings[] = {
65 HINIC_FUNC_STAT(tx_unicast_pkts_vport),
66 HINIC_FUNC_STAT(tx_unicast_bytes_vport),
67 HINIC_FUNC_STAT(tx_multicast_pkts_vport),
68 HINIC_FUNC_STAT(tx_multicast_bytes_vport),
69 HINIC_FUNC_STAT(tx_broadcast_pkts_vport),
70 HINIC_FUNC_STAT(tx_broadcast_bytes_vport),
72 HINIC_FUNC_STAT(rx_unicast_pkts_vport),
73 HINIC_FUNC_STAT(rx_unicast_bytes_vport),
74 HINIC_FUNC_STAT(rx_multicast_pkts_vport),
75 HINIC_FUNC_STAT(rx_multicast_bytes_vport),
76 HINIC_FUNC_STAT(rx_broadcast_pkts_vport),
77 HINIC_FUNC_STAT(rx_broadcast_bytes_vport),
79 HINIC_FUNC_STAT(tx_discard_vport),
80 HINIC_FUNC_STAT(rx_discard_vport),
81 HINIC_FUNC_STAT(tx_err_vport),
82 HINIC_FUNC_STAT(rx_err_vport),
85 #define HINIC_VPORT_XSTATS_NUM (sizeof(hinic_vport_stats_strings) / \
86 sizeof(hinic_vport_stats_strings[0]))
88 static const struct hinic_xstats_name_off hinic_phyport_stats_strings[] = {
89 HINIC_PORT_STAT(mac_rx_total_pkt_num),
90 HINIC_PORT_STAT(mac_rx_total_oct_num),
91 HINIC_PORT_STAT(mac_rx_bad_pkt_num),
92 HINIC_PORT_STAT(mac_rx_bad_oct_num),
93 HINIC_PORT_STAT(mac_rx_good_pkt_num),
94 HINIC_PORT_STAT(mac_rx_good_oct_num),
95 HINIC_PORT_STAT(mac_rx_uni_pkt_num),
96 HINIC_PORT_STAT(mac_rx_multi_pkt_num),
97 HINIC_PORT_STAT(mac_rx_broad_pkt_num),
98 HINIC_PORT_STAT(mac_tx_total_pkt_num),
99 HINIC_PORT_STAT(mac_tx_total_oct_num),
100 HINIC_PORT_STAT(mac_tx_bad_pkt_num),
101 HINIC_PORT_STAT(mac_tx_bad_oct_num),
102 HINIC_PORT_STAT(mac_tx_good_pkt_num),
103 HINIC_PORT_STAT(mac_tx_good_oct_num),
104 HINIC_PORT_STAT(mac_tx_uni_pkt_num),
105 HINIC_PORT_STAT(mac_tx_multi_pkt_num),
106 HINIC_PORT_STAT(mac_tx_broad_pkt_num),
107 HINIC_PORT_STAT(mac_rx_fragment_pkt_num),
108 HINIC_PORT_STAT(mac_rx_undersize_pkt_num),
109 HINIC_PORT_STAT(mac_rx_undermin_pkt_num),
110 HINIC_PORT_STAT(mac_rx_64_oct_pkt_num),
111 HINIC_PORT_STAT(mac_rx_65_127_oct_pkt_num),
112 HINIC_PORT_STAT(mac_rx_128_255_oct_pkt_num),
113 HINIC_PORT_STAT(mac_rx_256_511_oct_pkt_num),
114 HINIC_PORT_STAT(mac_rx_512_1023_oct_pkt_num),
115 HINIC_PORT_STAT(mac_rx_1024_1518_oct_pkt_num),
116 HINIC_PORT_STAT(mac_rx_1519_2047_oct_pkt_num),
117 HINIC_PORT_STAT(mac_rx_2048_4095_oct_pkt_num),
118 HINIC_PORT_STAT(mac_rx_4096_8191_oct_pkt_num),
119 HINIC_PORT_STAT(mac_rx_8192_9216_oct_pkt_num),
120 HINIC_PORT_STAT(mac_rx_9217_12287_oct_pkt_num),
121 HINIC_PORT_STAT(mac_rx_12288_16383_oct_pkt_num),
122 HINIC_PORT_STAT(mac_rx_1519_max_bad_pkt_num),
123 HINIC_PORT_STAT(mac_rx_1519_max_good_pkt_num),
124 HINIC_PORT_STAT(mac_rx_oversize_pkt_num),
125 HINIC_PORT_STAT(mac_rx_jabber_pkt_num),
126 HINIC_PORT_STAT(mac_rx_mac_pause_num),
127 HINIC_PORT_STAT(mac_rx_pfc_pkt_num),
128 HINIC_PORT_STAT(mac_rx_pfc_pri0_pkt_num),
129 HINIC_PORT_STAT(mac_rx_pfc_pri1_pkt_num),
130 HINIC_PORT_STAT(mac_rx_pfc_pri2_pkt_num),
131 HINIC_PORT_STAT(mac_rx_pfc_pri3_pkt_num),
132 HINIC_PORT_STAT(mac_rx_pfc_pri4_pkt_num),
133 HINIC_PORT_STAT(mac_rx_pfc_pri5_pkt_num),
134 HINIC_PORT_STAT(mac_rx_pfc_pri6_pkt_num),
135 HINIC_PORT_STAT(mac_rx_pfc_pri7_pkt_num),
136 HINIC_PORT_STAT(mac_rx_mac_control_pkt_num),
137 HINIC_PORT_STAT(mac_rx_sym_err_pkt_num),
138 HINIC_PORT_STAT(mac_rx_fcs_err_pkt_num),
139 HINIC_PORT_STAT(mac_rx_send_app_good_pkt_num),
140 HINIC_PORT_STAT(mac_rx_send_app_bad_pkt_num),
141 HINIC_PORT_STAT(mac_tx_fragment_pkt_num),
142 HINIC_PORT_STAT(mac_tx_undersize_pkt_num),
143 HINIC_PORT_STAT(mac_tx_undermin_pkt_num),
144 HINIC_PORT_STAT(mac_tx_64_oct_pkt_num),
145 HINIC_PORT_STAT(mac_tx_65_127_oct_pkt_num),
146 HINIC_PORT_STAT(mac_tx_128_255_oct_pkt_num),
147 HINIC_PORT_STAT(mac_tx_256_511_oct_pkt_num),
148 HINIC_PORT_STAT(mac_tx_512_1023_oct_pkt_num),
149 HINIC_PORT_STAT(mac_tx_1024_1518_oct_pkt_num),
150 HINIC_PORT_STAT(mac_tx_1519_2047_oct_pkt_num),
151 HINIC_PORT_STAT(mac_tx_2048_4095_oct_pkt_num),
152 HINIC_PORT_STAT(mac_tx_4096_8191_oct_pkt_num),
153 HINIC_PORT_STAT(mac_tx_8192_9216_oct_pkt_num),
154 HINIC_PORT_STAT(mac_tx_9217_12287_oct_pkt_num),
155 HINIC_PORT_STAT(mac_tx_12288_16383_oct_pkt_num),
156 HINIC_PORT_STAT(mac_tx_1519_max_bad_pkt_num),
157 HINIC_PORT_STAT(mac_tx_1519_max_good_pkt_num),
158 HINIC_PORT_STAT(mac_tx_oversize_pkt_num),
159 HINIC_PORT_STAT(mac_trans_jabber_pkt_num),
160 HINIC_PORT_STAT(mac_tx_mac_pause_num),
161 HINIC_PORT_STAT(mac_tx_pfc_pkt_num),
162 HINIC_PORT_STAT(mac_tx_pfc_pri0_pkt_num),
163 HINIC_PORT_STAT(mac_tx_pfc_pri1_pkt_num),
164 HINIC_PORT_STAT(mac_tx_pfc_pri2_pkt_num),
165 HINIC_PORT_STAT(mac_tx_pfc_pri3_pkt_num),
166 HINIC_PORT_STAT(mac_tx_pfc_pri4_pkt_num),
167 HINIC_PORT_STAT(mac_tx_pfc_pri5_pkt_num),
168 HINIC_PORT_STAT(mac_tx_pfc_pri6_pkt_num),
169 HINIC_PORT_STAT(mac_tx_pfc_pri7_pkt_num),
170 HINIC_PORT_STAT(mac_tx_mac_control_pkt_num),
171 HINIC_PORT_STAT(mac_tx_err_all_pkt_num),
172 HINIC_PORT_STAT(mac_tx_from_app_good_pkt_num),
173 HINIC_PORT_STAT(mac_tx_from_app_bad_pkt_num),
176 #define HINIC_PHYPORT_XSTATS_NUM (sizeof(hinic_phyport_stats_strings) / \
177 sizeof(hinic_phyport_stats_strings[0]))
179 static const struct hinic_xstats_name_off hinic_rxq_stats_strings[] = {
180 {"rx_nombuf", offsetof(struct hinic_rxq_stats, rx_nombuf)},
181 {"burst_pkt", offsetof(struct hinic_rxq_stats, burst_pkts)},
184 #define HINIC_RXQ_XSTATS_NUM (sizeof(hinic_rxq_stats_strings) / \
185 sizeof(hinic_rxq_stats_strings[0]))
187 static const struct hinic_xstats_name_off hinic_txq_stats_strings[] = {
188 {"tx_busy", offsetof(struct hinic_txq_stats, tx_busy)},
189 {"offload_errors", offsetof(struct hinic_txq_stats, off_errs)},
190 {"copy_pkts", offsetof(struct hinic_txq_stats, cpy_pkts)},
191 {"rl_drop", offsetof(struct hinic_txq_stats, rl_drop)},
192 {"burst_pkts", offsetof(struct hinic_txq_stats, burst_pkts)},
195 #define HINIC_TXQ_XSTATS_NUM (sizeof(hinic_txq_stats_strings) / \
196 sizeof(hinic_txq_stats_strings[0]))
198 static int hinic_xstats_calc_num(struct hinic_nic_dev *nic_dev)
200 return (HINIC_VPORT_XSTATS_NUM +
201 HINIC_PHYPORT_XSTATS_NUM +
202 HINIC_RXQ_XSTATS_NUM * nic_dev->num_rq +
203 HINIC_TXQ_XSTATS_NUM * nic_dev->num_sq);
206 static const struct rte_eth_desc_lim hinic_rx_desc_lim = {
207 .nb_max = HINIC_MAX_QUEUE_DEPTH,
208 .nb_min = HINIC_MIN_QUEUE_DEPTH,
209 .nb_align = HINIC_RXD_ALIGN,
212 static const struct rte_eth_desc_lim hinic_tx_desc_lim = {
213 .nb_max = HINIC_MAX_QUEUE_DEPTH,
214 .nb_min = HINIC_MIN_QUEUE_DEPTH,
215 .nb_align = HINIC_TXD_ALIGN,
220 * Interrupt handler triggered by NIC for handling
223 * @param: The address of parameter (struct rte_eth_dev *) regsitered before.
225 static void hinic_dev_interrupt_handler(void *param)
227 struct rte_eth_dev *dev = param;
228 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
230 if (!hinic_test_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status)) {
231 PMD_DRV_LOG(WARNING, "Device's interrupt is disabled, ignore interrupt event, dev_name: %s, port_id: %d",
232 nic_dev->proc_dev_name, dev->data->port_id);
236 /* aeq0 msg handler */
237 hinic_dev_handle_aeq_event(nic_dev->hwdev, param);
241 * Ethernet device configuration.
243 * Prepare the driver for a given number of TX and RX queues, mtu size
247 * Pointer to Ethernet device structure.
250 * 0 on success, negative error value otherwise.
252 static int hinic_dev_configure(struct rte_eth_dev *dev)
254 struct hinic_nic_dev *nic_dev;
255 struct hinic_nic_io *nic_io;
258 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
259 nic_io = nic_dev->hwdev->nic_io;
261 nic_dev->num_sq = dev->data->nb_tx_queues;
262 nic_dev->num_rq = dev->data->nb_rx_queues;
264 nic_io->num_sqs = dev->data->nb_tx_queues;
265 nic_io->num_rqs = dev->data->nb_rx_queues;
267 /* queue pair is max_num(sq, rq) */
268 nic_dev->num_qps = (nic_dev->num_sq > nic_dev->num_rq) ?
269 nic_dev->num_sq : nic_dev->num_rq;
270 nic_io->num_qps = nic_dev->num_qps;
272 if (nic_dev->num_qps > nic_io->max_qps) {
274 "Queue number out of range, get queue_num:%d, max_queue_num:%d",
275 nic_dev->num_qps, nic_io->max_qps);
279 /* mtu size is 256~9600 */
280 if (dev->data->dev_conf.rxmode.max_rx_pkt_len < HINIC_MIN_FRAME_SIZE ||
281 dev->data->dev_conf.rxmode.max_rx_pkt_len >
282 HINIC_MAX_JUMBO_FRAME_SIZE) {
284 "Max rx pkt len out of range, get max_rx_pkt_len:%d, "
285 "expect between %d and %d",
286 dev->data->dev_conf.rxmode.max_rx_pkt_len,
287 HINIC_MIN_FRAME_SIZE, HINIC_MAX_JUMBO_FRAME_SIZE);
292 HINIC_PKTLEN_TO_MTU(dev->data->dev_conf.rxmode.max_rx_pkt_len);
295 err = hinic_config_mq_mode(dev, TRUE);
297 PMD_DRV_LOG(ERR, "Config multi-queue failed");
305 * DPDK callback to create the receive queue.
308 * Pointer to Ethernet device structure.
312 * Number of descriptors for receive queue.
314 * NUMA socket on which memory must be allocated.
316 * Thresholds parameters (unused_).
318 * Memory pool for buffer allocations.
321 * 0 on success, negative error value otherwise.
323 static int hinic_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
324 uint16_t nb_desc, unsigned int socket_id,
325 __rte_unused const struct rte_eth_rxconf *rx_conf,
326 struct rte_mempool *mp)
329 struct hinic_nic_dev *nic_dev;
330 struct hinic_hwdev *hwdev;
331 struct hinic_rxq *rxq;
332 u16 rq_depth, rx_free_thresh;
335 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
336 hwdev = nic_dev->hwdev;
338 /* queue depth must be power of 2, otherwise will be aligned up */
339 rq_depth = (nb_desc & (nb_desc - 1)) ?
340 ((u16)(1U << (ilog2(nb_desc) + 1))) : nb_desc;
343 * Validate number of receive descriptors.
344 * It must not exceed hardware maximum and minimum.
346 if (rq_depth > HINIC_MAX_QUEUE_DEPTH ||
347 rq_depth < HINIC_MIN_QUEUE_DEPTH) {
348 PMD_DRV_LOG(ERR, "RX queue depth is out of range from %d to %d, (nb_desc=%d, q_depth=%d, port=%d queue=%d)",
349 HINIC_MIN_QUEUE_DEPTH, HINIC_MAX_QUEUE_DEPTH,
350 (int)nb_desc, (int)rq_depth,
351 (int)dev->data->port_id, (int)queue_idx);
356 * The RX descriptor ring will be cleaned after rxq->rx_free_thresh
357 * descriptors are used or if the number of descriptors required
358 * to transmit a packet is greater than the number of free RX
360 * The following constraints must be satisfied:
361 * rx_free_thresh must be greater than 0.
362 * rx_free_thresh must be less than the size of the ring minus 1.
363 * When set to zero use default values.
365 rx_free_thresh = (u16)((rx_conf->rx_free_thresh) ?
366 rx_conf->rx_free_thresh : HINIC_DEFAULT_RX_FREE_THRESH);
367 if (rx_free_thresh >= (rq_depth - 1)) {
368 PMD_DRV_LOG(ERR, "rx_free_thresh must be less than the number of RX descriptors minus 1. (rx_free_thresh=%u port=%d queue=%d)",
369 (unsigned int)rx_free_thresh,
370 (int)dev->data->port_id,
375 rxq = rte_zmalloc_socket("hinic_rx_queue", sizeof(struct hinic_rxq),
376 RTE_CACHE_LINE_SIZE, socket_id);
378 PMD_DRV_LOG(ERR, "Allocate rxq[%d] failed, dev_name: %s",
379 queue_idx, dev->data->name);
382 nic_dev->rxqs[queue_idx] = rxq;
384 /* alloc rx sq hw wqepage*/
385 rc = hinic_create_rq(hwdev, queue_idx, rq_depth);
387 PMD_DRV_LOG(ERR, "Create rxq[%d] failed, dev_name: %s, rq_depth: %d",
388 queue_idx, dev->data->name, rq_depth);
392 /* mbuf pool must be assigned before setup rx resources */
396 hinic_convert_rx_buf_size(rte_pktmbuf_data_room_size(rxq->mb_pool) -
397 RTE_PKTMBUF_HEADROOM, &buf_size);
399 PMD_DRV_LOG(ERR, "Adjust buf size failed, dev_name: %s",
401 goto adjust_bufsize_fail;
404 /* rx queue info, rearm control */
405 rxq->wq = &hwdev->nic_io->rq_wq[queue_idx];
406 rxq->pi_virt_addr = hwdev->nic_io->qps[queue_idx].rq.pi_virt_addr;
407 rxq->nic_dev = nic_dev;
408 rxq->q_id = queue_idx;
409 rxq->q_depth = rq_depth;
410 rxq->buf_len = (u16)buf_size;
411 rxq->rx_free_thresh = rx_free_thresh;
413 /* the last point cant do mbuf rearm in bulk */
414 rxq->rxinfo_align_end = rxq->q_depth - rxq->rx_free_thresh;
416 /* device port identifier */
417 rxq->port_id = dev->data->port_id;
419 /* alloc rx_cqe and prepare rq_wqe */
420 rc = hinic_setup_rx_resources(rxq);
422 PMD_DRV_LOG(ERR, "Setup rxq[%d] rx_resources failed, dev_name:%s",
423 queue_idx, dev->data->name);
424 goto setup_rx_res_err;
427 /* record nic_dev rxq in rte_eth rx_queues */
428 dev->data->rx_queues[queue_idx] = rxq;
434 hinic_destroy_rq(hwdev, queue_idx);
442 static void hinic_reset_rx_queue(struct rte_eth_dev *dev)
444 struct hinic_rxq *rxq;
445 struct hinic_nic_dev *nic_dev;
448 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
450 for (q_id = 0; q_id < nic_dev->num_rq; q_id++) {
451 rxq = dev->data->rx_queues[q_id];
453 rxq->wq->cons_idx = 0;
454 rxq->wq->prod_idx = 0;
455 rxq->wq->delta = rxq->q_depth;
456 rxq->wq->mask = rxq->q_depth - 1;
458 /* alloc mbuf to rq */
459 hinic_rx_alloc_pkts(rxq);
464 * DPDK callback to configure the transmit queue.
467 * Pointer to Ethernet device structure.
469 * Transmit queue index.
471 * Number of descriptors for transmit queue.
473 * NUMA socket on which memory must be allocated.
475 * Tx queue configuration parameters.
478 * 0 on success, negative error value otherwise.
480 static int hinic_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
481 uint16_t nb_desc, unsigned int socket_id,
482 __rte_unused const struct rte_eth_txconf *tx_conf)
485 struct hinic_nic_dev *nic_dev;
486 struct hinic_hwdev *hwdev;
487 struct hinic_txq *txq;
488 u16 sq_depth, tx_free_thresh;
490 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
491 hwdev = nic_dev->hwdev;
493 /* queue depth must be power of 2, otherwise will be aligned up */
494 sq_depth = (nb_desc & (nb_desc - 1)) ?
495 ((u16)(1U << (ilog2(nb_desc) + 1))) : nb_desc;
498 * Validate number of transmit descriptors.
499 * It must not exceed hardware maximum and minimum.
501 if (sq_depth > HINIC_MAX_QUEUE_DEPTH ||
502 sq_depth < HINIC_MIN_QUEUE_DEPTH) {
503 PMD_DRV_LOG(ERR, "TX queue depth is out of range from %d to %d, (nb_desc=%d, q_depth=%d, port=%d queue=%d)",
504 HINIC_MIN_QUEUE_DEPTH, HINIC_MAX_QUEUE_DEPTH,
505 (int)nb_desc, (int)sq_depth,
506 (int)dev->data->port_id, (int)queue_idx);
511 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
512 * descriptors are used or if the number of descriptors required
513 * to transmit a packet is greater than the number of free TX
515 * The following constraints must be satisfied:
516 * tx_free_thresh must be greater than 0.
517 * tx_free_thresh must be less than the size of the ring minus 1.
518 * When set to zero use default values.
520 tx_free_thresh = (u16)((tx_conf->tx_free_thresh) ?
521 tx_conf->tx_free_thresh : HINIC_DEFAULT_TX_FREE_THRESH);
522 if (tx_free_thresh >= (sq_depth - 1)) {
523 PMD_DRV_LOG(ERR, "tx_free_thresh must be less than the number of TX descriptors minus 1. (tx_free_thresh=%u port=%d queue=%d)",
524 (unsigned int)tx_free_thresh, (int)dev->data->port_id,
529 txq = rte_zmalloc_socket("hinic_tx_queue", sizeof(struct hinic_txq),
530 RTE_CACHE_LINE_SIZE, socket_id);
532 PMD_DRV_LOG(ERR, "Allocate txq[%d] failed, dev_name: %s",
533 queue_idx, dev->data->name);
536 nic_dev->txqs[queue_idx] = txq;
538 /* alloc tx sq hw wqepage */
539 rc = hinic_create_sq(hwdev, queue_idx, sq_depth);
541 PMD_DRV_LOG(ERR, "Create txq[%d] failed, dev_name: %s, sq_depth: %d",
542 queue_idx, dev->data->name, sq_depth);
546 txq->q_id = queue_idx;
547 txq->q_depth = sq_depth;
548 txq->port_id = dev->data->port_id;
549 txq->tx_free_thresh = tx_free_thresh;
550 txq->nic_dev = nic_dev;
551 txq->wq = &hwdev->nic_io->sq_wq[queue_idx];
552 txq->sq = &hwdev->nic_io->qps[queue_idx].sq;
553 txq->cons_idx_addr = hwdev->nic_io->qps[queue_idx].sq.cons_idx_addr;
554 txq->sq_head_addr = HINIC_GET_WQ_HEAD(txq);
555 txq->sq_bot_sge_addr = HINIC_GET_WQ_TAIL(txq) -
556 sizeof(struct hinic_sq_bufdesc);
557 txq->cos = nic_dev->default_cos;
559 /* alloc software txinfo */
560 rc = hinic_setup_tx_resources(txq);
562 PMD_DRV_LOG(ERR, "Setup txq[%d] tx_resources failed, dev_name: %s",
563 queue_idx, dev->data->name);
564 goto setup_tx_res_fail;
567 /* record nic_dev txq in rte_eth tx_queues */
568 dev->data->tx_queues[queue_idx] = txq;
573 hinic_destroy_sq(hwdev, queue_idx);
581 static void hinic_reset_tx_queue(struct rte_eth_dev *dev)
583 struct hinic_nic_dev *nic_dev;
584 struct hinic_txq *txq;
585 struct hinic_nic_io *nic_io;
586 struct hinic_hwdev *hwdev;
587 volatile u32 *ci_addr;
590 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
591 hwdev = nic_dev->hwdev;
592 nic_io = hwdev->nic_io;
594 for (q_id = 0; q_id < nic_dev->num_sq; q_id++) {
595 txq = dev->data->tx_queues[q_id];
597 txq->wq->cons_idx = 0;
598 txq->wq->prod_idx = 0;
599 txq->wq->delta = txq->q_depth;
600 txq->wq->mask = txq->q_depth - 1;
602 /*clear hardware ci*/
603 ci_addr = (volatile u32 *)HINIC_CI_VADDR(nic_io->ci_vaddr_base,
610 * Get link speed from NIC.
613 * Pointer to Ethernet device structure.
615 * Pointer to link speed structure.
617 static void hinic_get_speed_capa(struct rte_eth_dev *dev, uint32_t *speed_capa)
619 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
620 u32 supported_link, advertised_link;
623 #define HINIC_LINK_MODE_SUPPORT_1G (1U << HINIC_GE_BASE_KX)
625 #define HINIC_LINK_MODE_SUPPORT_10G (1U << HINIC_10GE_BASE_KR)
627 #define HINIC_LINK_MODE_SUPPORT_25G ((1U << HINIC_25GE_BASE_KR_S) | \
628 (1U << HINIC_25GE_BASE_CR_S) | \
629 (1U << HINIC_25GE_BASE_KR) | \
630 (1U << HINIC_25GE_BASE_CR))
632 #define HINIC_LINK_MODE_SUPPORT_40G ((1U << HINIC_40GE_BASE_KR4) | \
633 (1U << HINIC_40GE_BASE_CR4))
635 #define HINIC_LINK_MODE_SUPPORT_100G ((1U << HINIC_100GE_BASE_KR4) | \
636 (1U << HINIC_100GE_BASE_CR4))
638 err = hinic_get_link_mode(nic_dev->hwdev,
639 &supported_link, &advertised_link);
640 if (err || supported_link == HINIC_SUPPORTED_UNKNOWN ||
641 advertised_link == HINIC_SUPPORTED_UNKNOWN) {
642 PMD_DRV_LOG(WARNING, "Get speed capability info failed, device: %s, port_id: %u",
643 nic_dev->proc_dev_name, dev->data->port_id);
646 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_1G))
647 *speed_capa |= ETH_LINK_SPEED_1G;
648 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_10G))
649 *speed_capa |= ETH_LINK_SPEED_10G;
650 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_25G))
651 *speed_capa |= ETH_LINK_SPEED_25G;
652 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_40G))
653 *speed_capa |= ETH_LINK_SPEED_40G;
654 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_100G))
655 *speed_capa |= ETH_LINK_SPEED_100G;
660 * DPDK callback to get information about the device.
663 * Pointer to Ethernet device structure.
665 * Pointer to Info structure output buffer.
668 hinic_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
670 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
672 info->max_rx_queues = nic_dev->nic_cap.max_rqs;
673 info->max_tx_queues = nic_dev->nic_cap.max_sqs;
674 info->min_rx_bufsize = HINIC_MIN_RX_BUF_SIZE;
675 info->max_rx_pktlen = HINIC_MAX_JUMBO_FRAME_SIZE;
676 info->max_mac_addrs = HINIC_MAX_MAC_ADDRS;
678 hinic_get_speed_capa(dev, &info->speed_capa);
679 info->rx_queue_offload_capa = 0;
680 info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
681 DEV_RX_OFFLOAD_IPV4_CKSUM |
682 DEV_RX_OFFLOAD_UDP_CKSUM |
683 DEV_RX_OFFLOAD_TCP_CKSUM;
685 info->tx_queue_offload_capa = 0;
686 info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
687 DEV_TX_OFFLOAD_IPV4_CKSUM |
688 DEV_TX_OFFLOAD_UDP_CKSUM |
689 DEV_TX_OFFLOAD_TCP_CKSUM |
690 DEV_TX_OFFLOAD_SCTP_CKSUM |
691 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
692 DEV_TX_OFFLOAD_TCP_TSO |
693 DEV_TX_OFFLOAD_MULTI_SEGS;
695 info->hash_key_size = HINIC_RSS_KEY_SIZE;
696 info->reta_size = HINIC_RSS_INDIR_SIZE;
697 info->flow_type_rss_offloads = HINIC_RSS_OFFLOAD_ALL;
698 info->rx_desc_lim = hinic_rx_desc_lim;
699 info->tx_desc_lim = hinic_tx_desc_lim;
702 static int hinic_config_rx_mode(struct hinic_nic_dev *nic_dev, u32 rx_mode_ctrl)
706 err = hinic_set_rx_mode(nic_dev->hwdev, rx_mode_ctrl);
708 PMD_DRV_LOG(ERR, "Failed to set rx mode");
711 nic_dev->rx_mode_status = rx_mode_ctrl;
717 static int hinic_rxtx_configure(struct rte_eth_dev *dev)
720 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
722 /* rx configure, if rss enable, need to init default configuration */
723 err = hinic_rx_configure(dev);
725 PMD_DRV_LOG(ERR, "Configure rss failed");
730 err = hinic_config_rx_mode(nic_dev, HINIC_DEFAULT_RX_MODE);
732 PMD_DRV_LOG(ERR, "Configure rx_mode:0x%x failed",
733 HINIC_DEFAULT_RX_MODE);
734 goto set_rx_mode_fail;
740 hinic_rx_remove_configure(dev);
745 static void hinic_remove_rxtx_configure(struct rte_eth_dev *dev)
747 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
749 (void)hinic_config_rx_mode(nic_dev, 0);
750 hinic_rx_remove_configure(dev);
753 static int hinic_priv_get_dev_link_status(struct hinic_nic_dev *nic_dev,
754 struct rte_eth_link *link)
757 u8 port_link_status = 0;
758 struct nic_port_info port_link_info;
759 struct hinic_hwdev *nic_hwdev = nic_dev->hwdev;
760 uint32_t port_speed[LINK_SPEED_MAX] = {ETH_SPEED_NUM_10M,
761 ETH_SPEED_NUM_100M, ETH_SPEED_NUM_1G,
762 ETH_SPEED_NUM_10G, ETH_SPEED_NUM_25G,
763 ETH_SPEED_NUM_40G, ETH_SPEED_NUM_100G};
765 rc = hinic_get_link_status(nic_hwdev, &port_link_status);
769 if (!port_link_status) {
770 link->link_status = ETH_LINK_DOWN;
771 link->link_speed = 0;
772 link->link_duplex = ETH_LINK_HALF_DUPLEX;
773 link->link_autoneg = ETH_LINK_FIXED;
777 memset(&port_link_info, 0, sizeof(port_link_info));
778 rc = hinic_get_port_info(nic_hwdev, &port_link_info);
782 link->link_speed = port_speed[port_link_info.speed % LINK_SPEED_MAX];
783 link->link_duplex = port_link_info.duplex;
784 link->link_autoneg = port_link_info.autoneg_state;
785 link->link_status = port_link_status;
791 * DPDK callback to retrieve physical link information.
794 * Pointer to Ethernet device structure.
795 * @param wait_to_complete
796 * Wait for request completion.
799 * 0 link status changed, -1 link status not changed
801 static int hinic_link_update(struct rte_eth_dev *dev, int wait_to_complete)
803 #define CHECK_INTERVAL 10 /* 10ms */
804 #define MAX_REPEAT_TIME 100 /* 1s (100 * 10ms) in total */
806 struct rte_eth_link link;
807 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
808 unsigned int rep_cnt = MAX_REPEAT_TIME;
810 memset(&link, 0, sizeof(link));
812 /* Get link status information from hardware */
813 rc = hinic_priv_get_dev_link_status(nic_dev, &link);
814 if (rc != HINIC_OK) {
815 link.link_speed = ETH_SPEED_NUM_NONE;
816 link.link_duplex = ETH_LINK_FULL_DUPLEX;
817 PMD_DRV_LOG(ERR, "Get link status failed");
821 if (!wait_to_complete || link.link_status)
824 rte_delay_ms(CHECK_INTERVAL);
828 rc = rte_eth_linkstatus_set(dev, &link);
833 * DPDK callback to start the device.
836 * Pointer to Ethernet device structure.
839 * 0 on success, negative errno value on failure.
841 static int hinic_dev_start(struct rte_eth_dev *dev)
845 struct hinic_nic_dev *nic_dev;
847 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
848 name = dev->data->name;
850 /* reset rx and tx queue */
851 hinic_reset_rx_queue(dev);
852 hinic_reset_tx_queue(dev);
854 /* get func rx buf size */
855 hinic_get_func_rx_buf_size(nic_dev);
857 /* init txq and rxq context */
858 rc = hinic_init_qp_ctxts(nic_dev->hwdev);
860 PMD_DRV_LOG(ERR, "Initialize qp context failed, dev_name:%s",
866 rc = hinic_config_mq_mode(dev, TRUE);
868 PMD_DRV_LOG(ERR, "Configure mq mode failed, dev_name: %s",
870 goto cfg_mq_mode_fail;
873 /* set default mtu */
874 rc = hinic_set_port_mtu(nic_dev->hwdev, nic_dev->mtu_size);
876 PMD_DRV_LOG(ERR, "Set mtu_size[%d] failed, dev_name: %s",
877 nic_dev->mtu_size, name);
881 /* configure rss rx_mode and other rx or tx default feature */
882 rc = hinic_rxtx_configure(dev);
884 PMD_DRV_LOG(ERR, "Configure tx and rx failed, dev_name: %s",
889 /* open virtual port and ready to start packet receiving */
890 rc = hinic_set_vport_enable(nic_dev->hwdev, true);
892 PMD_DRV_LOG(ERR, "Enable vport failed, dev_name:%s", name);
896 /* open physical port and start packet receiving */
897 rc = hinic_set_port_enable(nic_dev->hwdev, true);
899 PMD_DRV_LOG(ERR, "Enable physical port failed, dev_name:%s",
904 /* update eth_dev link status */
905 if (dev->data->dev_conf.intr_conf.lsc != 0)
906 (void)hinic_link_update(dev, 0);
908 hinic_set_bit(HINIC_DEV_START, &nic_dev->dev_status);
913 (void)hinic_set_vport_enable(nic_dev->hwdev, false);
916 /* Flush tx && rx chip resources in case of set vport fake fail */
917 (void)hinic_flush_qp_res(nic_dev->hwdev);
920 hinic_remove_rxtx_configure(dev);
925 hinic_free_qp_ctxts(nic_dev->hwdev);
928 hinic_free_all_rx_mbuf(dev);
929 hinic_free_all_tx_mbuf(dev);
935 * DPDK callback to release the receive queue.
938 * Generic receive queue pointer.
940 static void hinic_rx_queue_release(void *queue)
942 struct hinic_rxq *rxq = queue;
943 struct hinic_nic_dev *nic_dev;
946 PMD_DRV_LOG(WARNING, "Rxq is null when release");
949 nic_dev = rxq->nic_dev;
951 /* free rxq_pkt mbuf */
952 hinic_free_all_rx_skbs(rxq);
954 /* free rxq_cqe, rxq_info */
955 hinic_free_rx_resources(rxq);
957 /* free root rq wq */
958 hinic_destroy_rq(nic_dev->hwdev, rxq->q_id);
960 nic_dev->rxqs[rxq->q_id] = NULL;
967 * DPDK callback to release the transmit queue.
970 * Generic transmit queue pointer.
972 static void hinic_tx_queue_release(void *queue)
974 struct hinic_txq *txq = queue;
975 struct hinic_nic_dev *nic_dev;
978 PMD_DRV_LOG(WARNING, "Txq is null when release");
981 nic_dev = txq->nic_dev;
983 /* free txq_pkt mbuf */
984 hinic_free_all_tx_skbs(txq);
987 hinic_free_tx_resources(txq);
989 /* free root sq wq */
990 hinic_destroy_sq(nic_dev->hwdev, txq->q_id);
991 nic_dev->txqs[txq->q_id] = NULL;
997 static void hinic_free_all_rq(struct hinic_nic_dev *nic_dev)
1001 for (q_id = 0; q_id < nic_dev->num_rq; q_id++)
1002 hinic_destroy_rq(nic_dev->hwdev, q_id);
1005 static void hinic_free_all_sq(struct hinic_nic_dev *nic_dev)
1009 for (q_id = 0; q_id < nic_dev->num_sq; q_id++)
1010 hinic_destroy_sq(nic_dev->hwdev, q_id);
1014 * DPDK callback to stop the device.
1017 * Pointer to Ethernet device structure.
1019 static void hinic_dev_stop(struct rte_eth_dev *dev)
1024 struct hinic_nic_dev *nic_dev;
1025 struct rte_eth_link link;
1027 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1028 name = dev->data->name;
1029 port_id = dev->data->port_id;
1031 if (!hinic_test_and_clear_bit(HINIC_DEV_START, &nic_dev->dev_status)) {
1032 PMD_DRV_LOG(INFO, "Device %s already stopped", name);
1036 /* just stop phy port and vport */
1037 rc = hinic_set_port_enable(nic_dev->hwdev, false);
1039 PMD_DRV_LOG(WARNING, "Disable phy port failed, error: %d, dev_name:%s, port_id:%d",
1042 rc = hinic_set_vport_enable(nic_dev->hwdev, false);
1044 PMD_DRV_LOG(WARNING, "Disable vport failed, error: %d, dev_name:%s, port_id:%d",
1047 /* Clear recorded link status */
1048 memset(&link, 0, sizeof(link));
1049 (void)rte_eth_linkstatus_set(dev, &link);
1051 /* flush pending io request */
1052 rc = hinic_rx_tx_flush(nic_dev->hwdev);
1054 PMD_DRV_LOG(WARNING, "Flush pending io failed, error: %d, dev_name: %s, port_id: %d",
1057 /* clean rss table and rx_mode */
1058 hinic_remove_rxtx_configure(dev);
1060 /* clean root context */
1061 hinic_free_qp_ctxts(nic_dev->hwdev);
1064 hinic_free_all_rx_mbuf(dev);
1065 hinic_free_all_tx_mbuf(dev);
1068 static void hinic_disable_interrupt(struct rte_eth_dev *dev)
1070 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1071 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1072 int ret, retries = 0;
1074 hinic_clear_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status);
1076 /* disable msix interrupt in hardware */
1077 hinic_set_msix_state(nic_dev->hwdev, 0, HINIC_MSIX_DISABLE);
1079 /* disable rte interrupt */
1080 ret = rte_intr_disable(&pci_dev->intr_handle);
1082 PMD_DRV_LOG(ERR, "Disable intr failed: %d", ret);
1086 rte_intr_callback_unregister(&pci_dev->intr_handle,
1087 hinic_dev_interrupt_handler, dev);
1090 } else if (ret == -EAGAIN) {
1094 PMD_DRV_LOG(ERR, "intr callback unregister failed: %d",
1098 } while (retries < HINIC_INTR_CB_UNREG_MAX_RETRIES);
1100 if (retries == HINIC_INTR_CB_UNREG_MAX_RETRIES)
1101 PMD_DRV_LOG(ERR, "Unregister intr callback failed after %d retries",
1105 static int hinic_set_dev_promiscuous(struct hinic_nic_dev *nic_dev, bool enable)
1107 u32 rx_mode_ctrl = nic_dev->rx_mode_status;
1110 rx_mode_ctrl |= HINIC_RX_MODE_PROMISC;
1112 rx_mode_ctrl &= (~HINIC_RX_MODE_PROMISC);
1114 return hinic_config_rx_mode(nic_dev, rx_mode_ctrl);
1118 * DPDK callback to get device statistics.
1121 * Pointer to Ethernet device structure.
1123 * Stats structure output buffer.
1126 * 0 on success and stats is filled,
1127 * negative error value otherwise.
1130 hinic_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1133 u64 rx_discards_pmd = 0;
1134 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1135 struct hinic_vport_stats vport_stats;
1136 struct hinic_rxq *rxq = NULL;
1137 struct hinic_rxq_stats rxq_stats;
1138 struct hinic_txq *txq = NULL;
1139 struct hinic_txq_stats txq_stats;
1141 err = hinic_get_vport_stats(nic_dev->hwdev, &vport_stats);
1143 PMD_DRV_LOG(ERR, "Get vport stats from fw failed, nic_dev: %s",
1144 nic_dev->proc_dev_name);
1148 /* rx queue stats */
1149 q_num = (nic_dev->num_rq < RTE_ETHDEV_QUEUE_STAT_CNTRS) ?
1150 nic_dev->num_rq : RTE_ETHDEV_QUEUE_STAT_CNTRS;
1151 for (i = 0; i < q_num; i++) {
1152 rxq = nic_dev->rxqs[i];
1153 hinic_rxq_get_stats(rxq, &rxq_stats);
1154 stats->q_ipackets[i] = rxq_stats.packets;
1155 stats->q_ibytes[i] = rxq_stats.bytes;
1156 stats->q_errors[i] = rxq_stats.rx_discards;
1158 stats->ierrors += rxq_stats.errors;
1159 rx_discards_pmd += rxq_stats.rx_discards;
1160 dev->data->rx_mbuf_alloc_failed += rxq_stats.rx_nombuf;
1163 /* tx queue stats */
1164 q_num = (nic_dev->num_sq < RTE_ETHDEV_QUEUE_STAT_CNTRS) ?
1165 nic_dev->num_sq : RTE_ETHDEV_QUEUE_STAT_CNTRS;
1166 for (i = 0; i < q_num; i++) {
1167 txq = nic_dev->txqs[i];
1168 hinic_txq_get_stats(txq, &txq_stats);
1169 stats->q_opackets[i] = txq_stats.packets;
1170 stats->q_obytes[i] = txq_stats.bytes;
1171 stats->oerrors += (txq_stats.tx_busy + txq_stats.off_errs);
1175 stats->oerrors += vport_stats.tx_discard_vport;
1177 stats->imissed = vport_stats.rx_discard_vport + rx_discards_pmd;
1179 stats->ipackets = (vport_stats.rx_unicast_pkts_vport +
1180 vport_stats.rx_multicast_pkts_vport +
1181 vport_stats.rx_broadcast_pkts_vport -
1184 stats->opackets = (vport_stats.tx_unicast_pkts_vport +
1185 vport_stats.tx_multicast_pkts_vport +
1186 vport_stats.tx_broadcast_pkts_vport);
1188 stats->ibytes = (vport_stats.rx_unicast_bytes_vport +
1189 vport_stats.rx_multicast_bytes_vport +
1190 vport_stats.rx_broadcast_bytes_vport);
1192 stats->obytes = (vport_stats.tx_unicast_bytes_vport +
1193 vport_stats.tx_multicast_bytes_vport +
1194 vport_stats.tx_broadcast_bytes_vport);
1199 * DPDK callback to clear device statistics.
1202 * Pointer to Ethernet device structure.
1204 static void hinic_dev_stats_reset(struct rte_eth_dev *dev)
1207 struct hinic_rxq *rxq = NULL;
1208 struct hinic_txq *txq = NULL;
1209 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1211 hinic_clear_vport_stats(nic_dev->hwdev);
1213 for (qid = 0; qid < nic_dev->num_rq; qid++) {
1214 rxq = nic_dev->rxqs[qid];
1215 hinic_rxq_stats_reset(rxq);
1218 for (qid = 0; qid < nic_dev->num_sq; qid++) {
1219 txq = nic_dev->txqs[qid];
1220 hinic_txq_stats_reset(txq);
1225 * DPDK callback to clear device extended statistics.
1228 * Pointer to Ethernet device structure.
1230 static void hinic_dev_xstats_reset(struct rte_eth_dev *dev)
1232 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1234 hinic_dev_stats_reset(dev);
1236 if (hinic_func_type(nic_dev->hwdev) != TYPE_VF)
1237 hinic_clear_phy_port_stats(nic_dev->hwdev);
1240 static void hinic_gen_random_mac_addr(struct rte_ether_addr *mac_addr)
1242 uint64_t random_value;
1244 /* Set Organizationally Unique Identifier (OUI) prefix */
1245 mac_addr->addr_bytes[0] = 0x00;
1246 mac_addr->addr_bytes[1] = 0x09;
1247 mac_addr->addr_bytes[2] = 0xC0;
1248 /* Force indication of locally assigned MAC address. */
1249 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1250 /* Generate the last 3 bytes of the MAC address with a random number. */
1251 random_value = rte_rand();
1252 memcpy(&mac_addr->addr_bytes[3], &random_value, 3);
1256 * Init mac_vlan table in NIC.
1259 * Pointer to Ethernet device structure.
1262 * 0 on success and stats is filled,
1263 * negative error value otherwise.
1265 static int hinic_init_mac_addr(struct rte_eth_dev *eth_dev)
1267 struct hinic_nic_dev *nic_dev =
1268 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);
1269 uint8_t addr_bytes[RTE_ETHER_ADDR_LEN];
1273 rc = hinic_get_default_mac(nic_dev->hwdev, addr_bytes);
1277 memmove(eth_dev->data->mac_addrs->addr_bytes,
1278 addr_bytes, RTE_ETHER_ADDR_LEN);
1280 if (rte_is_zero_ether_addr(eth_dev->data->mac_addrs))
1281 hinic_gen_random_mac_addr(eth_dev->data->mac_addrs);
1283 func_id = hinic_global_func_id(nic_dev->hwdev);
1284 rc = hinic_set_mac(nic_dev->hwdev, eth_dev->data->mac_addrs->addr_bytes,
1286 if (rc && rc != HINIC_PF_SET_VF_ALREADY)
1293 * Deinit mac_vlan table in NIC.
1296 * Pointer to Ethernet device structure.
1299 * 0 on success and stats is filled,
1300 * negative error value otherwise.
1302 static void hinic_deinit_mac_addr(struct rte_eth_dev *eth_dev)
1304 struct hinic_nic_dev *nic_dev =
1305 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);
1309 if (rte_is_zero_ether_addr(eth_dev->data->mac_addrs))
1312 func_id = hinic_global_func_id(nic_dev->hwdev);
1313 rc = hinic_del_mac(nic_dev->hwdev,
1314 eth_dev->data->mac_addrs->addr_bytes,
1316 if (rc && rc != HINIC_PF_SET_VF_ALREADY)
1317 PMD_DRV_LOG(ERR, "Delete mac table failed, dev_name: %s",
1318 eth_dev->data->name);
1322 * DPDK callback to enable promiscuous mode.
1325 * Pointer to Ethernet device structure.
1327 static void hinic_dev_promiscuous_enable(struct rte_eth_dev *dev)
1330 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1332 PMD_DRV_LOG(INFO, "Enable promiscuous, nic_dev: %s, port_id: %d, promisc: %d",
1333 nic_dev->proc_dev_name, dev->data->port_id,
1334 dev->data->promiscuous);
1336 rc = hinic_set_dev_promiscuous(nic_dev, true);
1338 PMD_DRV_LOG(ERR, "Enable promiscuous failed");
1342 * DPDK callback to disable promiscuous mode.
1345 * Pointer to Ethernet device structure.
1347 static void hinic_dev_promiscuous_disable(struct rte_eth_dev *dev)
1350 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1352 PMD_DRV_LOG(INFO, "Disable promiscuous, nic_dev: %s, port_id: %d, promisc: %d",
1353 nic_dev->proc_dev_name, dev->data->port_id,
1354 dev->data->promiscuous);
1356 rc = hinic_set_dev_promiscuous(nic_dev, false);
1358 PMD_DRV_LOG(ERR, "Disable promiscuous failed");
1362 * DPDK callback to update the RSS hash key and RSS hash type.
1365 * Pointer to Ethernet device structure.
1367 * RSS configuration data.
1370 * 0 on success, negative error value otherwise.
1372 static int hinic_rss_hash_update(struct rte_eth_dev *dev,
1373 struct rte_eth_rss_conf *rss_conf)
1375 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1376 u8 tmpl_idx = nic_dev->rss_tmpl_idx;
1377 u8 hashkey[HINIC_RSS_KEY_SIZE] = {0};
1378 u8 prio_tc[HINIC_DCB_UP_MAX] = {0};
1379 u64 rss_hf = rss_conf->rss_hf;
1380 struct nic_rss_type rss_type = {0};
1383 if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) {
1384 PMD_DRV_LOG(WARNING, "RSS is not enabled");
1388 if (rss_conf->rss_key_len > HINIC_RSS_KEY_SIZE) {
1389 PMD_DRV_LOG(ERR, "Invalid rss key, rss_key_len:%d",
1390 rss_conf->rss_key_len);
1394 if (rss_conf->rss_key) {
1395 memcpy(hashkey, rss_conf->rss_key, rss_conf->rss_key_len);
1396 err = hinic_rss_set_template_tbl(nic_dev->hwdev, tmpl_idx,
1399 PMD_DRV_LOG(ERR, "Set rss template table failed");
1404 rss_type.ipv4 = (rss_hf & (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4)) ? 1 : 0;
1405 rss_type.tcp_ipv4 = (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) ? 1 : 0;
1406 rss_type.ipv6 = (rss_hf & (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6)) ? 1 : 0;
1407 rss_type.ipv6_ext = (rss_hf & ETH_RSS_IPV6_EX) ? 1 : 0;
1408 rss_type.tcp_ipv6 = (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) ? 1 : 0;
1409 rss_type.tcp_ipv6_ext = (rss_hf & ETH_RSS_IPV6_TCP_EX) ? 1 : 0;
1410 rss_type.udp_ipv4 = (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) ? 1 : 0;
1411 rss_type.udp_ipv6 = (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) ? 1 : 0;
1413 err = hinic_set_rss_type(nic_dev->hwdev, tmpl_idx, rss_type);
1415 PMD_DRV_LOG(ERR, "Set rss type table failed");
1422 memset(prio_tc, 0, sizeof(prio_tc));
1423 (void)hinic_rss_cfg(nic_dev->hwdev, 0, tmpl_idx, 0, prio_tc);
1428 * DPDK callback to get the RSS hash configuration.
1431 * Pointer to Ethernet device structure.
1433 * RSS configuration data.
1436 * 0 on success, negative error value otherwise.
1438 static int hinic_rss_conf_get(struct rte_eth_dev *dev,
1439 struct rte_eth_rss_conf *rss_conf)
1441 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1442 u8 tmpl_idx = nic_dev->rss_tmpl_idx;
1443 u8 hashkey[HINIC_RSS_KEY_SIZE] = {0};
1444 struct nic_rss_type rss_type = {0};
1447 if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) {
1448 PMD_DRV_LOG(WARNING, "RSS is not enabled");
1452 err = hinic_rss_get_template_tbl(nic_dev->hwdev, tmpl_idx, hashkey);
1456 if (rss_conf->rss_key &&
1457 rss_conf->rss_key_len >= HINIC_RSS_KEY_SIZE) {
1458 memcpy(rss_conf->rss_key, hashkey, sizeof(hashkey));
1459 rss_conf->rss_key_len = sizeof(hashkey);
1462 err = hinic_get_rss_type(nic_dev->hwdev, tmpl_idx, &rss_type);
1466 rss_conf->rss_hf = 0;
1467 rss_conf->rss_hf |= rss_type.ipv4 ?
1468 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4) : 0;
1469 rss_conf->rss_hf |= rss_type.tcp_ipv4 ? ETH_RSS_NONFRAG_IPV4_TCP : 0;
1470 rss_conf->rss_hf |= rss_type.ipv6 ?
1471 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6) : 0;
1472 rss_conf->rss_hf |= rss_type.ipv6_ext ? ETH_RSS_IPV6_EX : 0;
1473 rss_conf->rss_hf |= rss_type.tcp_ipv6 ? ETH_RSS_NONFRAG_IPV6_TCP : 0;
1474 rss_conf->rss_hf |= rss_type.tcp_ipv6_ext ? ETH_RSS_IPV6_TCP_EX : 0;
1475 rss_conf->rss_hf |= rss_type.udp_ipv4 ? ETH_RSS_NONFRAG_IPV4_UDP : 0;
1476 rss_conf->rss_hf |= rss_type.udp_ipv6 ? ETH_RSS_NONFRAG_IPV6_UDP : 0;
1482 * DPDK callback to update the RETA indirection table.
1485 * Pointer to Ethernet device structure.
1487 * Pointer to RETA configuration structure array.
1489 * Size of the RETA table.
1492 * 0 on success, negative error value otherwise.
1494 static int hinic_rss_indirtbl_update(struct rte_eth_dev *dev,
1495 struct rte_eth_rss_reta_entry64 *reta_conf,
1498 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1499 u8 tmpl_idx = nic_dev->rss_tmpl_idx;
1500 u8 prio_tc[HINIC_DCB_UP_MAX] = {0};
1501 u32 indirtbl[NIC_RSS_INDIR_SIZE] = {0};
1506 if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG))
1509 if (reta_size != NIC_RSS_INDIR_SIZE) {
1510 PMD_DRV_LOG(ERR, "Invalid reta size, reta_size:%d", reta_size);
1514 err = hinic_rss_get_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl);
1518 /* update rss indir_tbl */
1519 for (i = 0; i < reta_size; i++) {
1520 idx = i / RTE_RETA_GROUP_SIZE;
1521 shift = i % RTE_RETA_GROUP_SIZE;
1522 if (reta_conf[idx].mask & (1ULL << shift))
1523 indirtbl[i] = reta_conf[idx].reta[shift];
1526 for (i = 0 ; i < reta_size; i++) {
1527 if (indirtbl[i] >= nic_dev->num_rq) {
1528 PMD_DRV_LOG(ERR, "Invalid reta entry, index:%d, num_rq:%d",
1529 i, nic_dev->num_rq);
1534 err = hinic_rss_set_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl);
1538 nic_dev->rss_indir_flag = true;
1543 memset(prio_tc, 0, sizeof(prio_tc));
1544 (void)hinic_rss_cfg(nic_dev->hwdev, 0, tmpl_idx, 0, prio_tc);
1551 * DPDK callback to get the RETA indirection table.
1554 * Pointer to Ethernet device structure.
1556 * Pointer to RETA configuration structure array.
1558 * Size of the RETA table.
1561 * 0 on success, negative error value otherwise.
1563 static int hinic_rss_indirtbl_query(struct rte_eth_dev *dev,
1564 struct rte_eth_rss_reta_entry64 *reta_conf,
1567 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1568 u8 tmpl_idx = nic_dev->rss_tmpl_idx;
1570 u32 indirtbl[NIC_RSS_INDIR_SIZE] = {0};
1574 if (reta_size != NIC_RSS_INDIR_SIZE) {
1575 PMD_DRV_LOG(ERR, "Invalid reta size, reta_size:%d", reta_size);
1579 err = hinic_rss_get_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl);
1581 PMD_DRV_LOG(ERR, "Get rss indirect table failed, error:%d",
1586 for (i = 0; i < reta_size; i++) {
1587 idx = i / RTE_RETA_GROUP_SIZE;
1588 shift = i % RTE_RETA_GROUP_SIZE;
1589 if (reta_conf[idx].mask & (1ULL << shift))
1590 reta_conf[idx].reta[shift] = (uint16_t)indirtbl[i];
1597 * DPDK callback to get extended device statistics.
1600 * Pointer to Ethernet device.
1602 * Pointer to rte extended stats table.
1604 * The size of the stats table.
1607 * Number of extended stats on success and stats is filled,
1608 * negative error value otherwise.
1610 static int hinic_dev_xstats_get(struct rte_eth_dev *dev,
1611 struct rte_eth_xstat *xstats,
1617 struct hinic_nic_dev *nic_dev;
1618 struct hinic_phy_port_stats port_stats;
1619 struct hinic_vport_stats vport_stats;
1620 struct hinic_rxq *rxq = NULL;
1621 struct hinic_rxq_stats rxq_stats;
1622 struct hinic_txq *txq = NULL;
1623 struct hinic_txq_stats txq_stats;
1625 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1626 count = hinic_xstats_calc_num(nic_dev);
1632 /* Get stats from hinic_rxq_stats */
1633 for (qid = 0; qid < nic_dev->num_rq; qid++) {
1634 rxq = nic_dev->rxqs[qid];
1635 hinic_rxq_get_stats(rxq, &rxq_stats);
1637 for (i = 0; i < HINIC_RXQ_XSTATS_NUM; i++) {
1638 xstats[count].value =
1639 *(uint64_t *)(((char *)&rxq_stats) +
1640 hinic_rxq_stats_strings[i].offset);
1641 xstats[count].id = count;
1646 /* Get stats from hinic_txq_stats */
1647 for (qid = 0; qid < nic_dev->num_sq; qid++) {
1648 txq = nic_dev->txqs[qid];
1649 hinic_txq_get_stats(txq, &txq_stats);
1651 for (i = 0; i < HINIC_TXQ_XSTATS_NUM; i++) {
1652 xstats[count].value =
1653 *(uint64_t *)(((char *)&txq_stats) +
1654 hinic_txq_stats_strings[i].offset);
1655 xstats[count].id = count;
1660 /* Get stats from hinic_vport_stats */
1661 err = hinic_get_vport_stats(nic_dev->hwdev, &vport_stats);
1665 for (i = 0; i < HINIC_VPORT_XSTATS_NUM; i++) {
1666 xstats[count].value =
1667 *(uint64_t *)(((char *)&vport_stats) +
1668 hinic_vport_stats_strings[i].offset);
1669 xstats[count].id = count;
1673 /* Get stats from hinic_phy_port_stats */
1674 err = hinic_get_phy_port_stats(nic_dev->hwdev, &port_stats);
1678 for (i = 0; i < HINIC_PHYPORT_XSTATS_NUM; i++) {
1679 xstats[count].value = *(uint64_t *)(((char *)&port_stats) +
1680 hinic_phyport_stats_strings[i].offset);
1681 xstats[count].id = count;
1689 * DPDK callback to retrieve names of extended device statistics
1692 * Pointer to Ethernet device structure.
1693 * @param xstats_names
1694 * Buffer to insert names into.
1697 * Number of xstats names.
1699 static int hinic_dev_xstats_get_names(struct rte_eth_dev *dev,
1700 struct rte_eth_xstat_name *xstats_names,
1701 __rte_unused unsigned int limit)
1703 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1707 if (xstats_names == NULL)
1708 return hinic_xstats_calc_num(nic_dev);
1710 /* get pmd rxq stats */
1711 for (q_num = 0; q_num < nic_dev->num_rq; q_num++) {
1712 for (i = 0; i < HINIC_RXQ_XSTATS_NUM; i++) {
1713 snprintf(xstats_names[count].name,
1714 sizeof(xstats_names[count].name),
1716 q_num, hinic_rxq_stats_strings[i].name);
1721 /* get pmd txq stats */
1722 for (q_num = 0; q_num < nic_dev->num_sq; q_num++) {
1723 for (i = 0; i < HINIC_TXQ_XSTATS_NUM; i++) {
1724 snprintf(xstats_names[count].name,
1725 sizeof(xstats_names[count].name),
1727 q_num, hinic_txq_stats_strings[i].name);
1732 /* get vport stats */
1733 for (i = 0; i < HINIC_VPORT_XSTATS_NUM; i++) {
1734 snprintf(xstats_names[count].name,
1735 sizeof(xstats_names[count].name),
1737 hinic_vport_stats_strings[i].name);
1741 /* get phy port stats */
1742 for (i = 0; i < HINIC_PHYPORT_XSTATS_NUM; i++) {
1743 snprintf(xstats_names[count].name,
1744 sizeof(xstats_names[count].name),
1746 hinic_phyport_stats_strings[i].name);
1753 static int hinic_set_default_pause_feature(struct hinic_nic_dev *nic_dev)
1755 struct nic_pause_config pause_config = {0};
1757 pause_config.auto_neg = 0;
1758 pause_config.rx_pause = HINIC_DEFAUT_PAUSE_CONFIG;
1759 pause_config.tx_pause = HINIC_DEFAUT_PAUSE_CONFIG;
1761 return hinic_set_pause_config(nic_dev->hwdev, pause_config);
1764 static int hinic_set_default_dcb_feature(struct hinic_nic_dev *nic_dev)
1766 u8 up_tc[HINIC_DCB_UP_MAX] = {0};
1767 u8 up_pgid[HINIC_DCB_UP_MAX] = {0};
1768 u8 up_bw[HINIC_DCB_UP_MAX] = {0};
1769 u8 pg_bw[HINIC_DCB_UP_MAX] = {0};
1770 u8 up_strict[HINIC_DCB_UP_MAX] = {0};
1774 for (i = 0; i < HINIC_DCB_UP_MAX; i++)
1777 return hinic_dcb_set_ets(nic_dev->hwdev, up_tc, pg_bw,
1778 up_pgid, up_bw, up_strict);
1781 static void hinic_init_default_cos(struct hinic_nic_dev *nic_dev)
1783 nic_dev->default_cos =
1784 (hinic_global_func_id(nic_dev->hwdev) +
1785 DEFAULT_BASE_COS) % NR_MAX_COS;
1788 static int hinic_set_default_hw_feature(struct hinic_nic_dev *nic_dev)
1792 hinic_init_default_cos(nic_dev);
1794 /* Restore DCB configure to default status */
1795 err = hinic_set_default_dcb_feature(nic_dev);
1800 err = hinic_set_rx_lro(nic_dev->hwdev, 0, 0, (u8)0);
1804 /* Set pause enable, and up will disable pfc. */
1805 err = hinic_set_default_pause_feature(nic_dev);
1809 err = hinic_reset_port_link_cfg(nic_dev->hwdev);
1813 err = hinic_set_link_status_follow(nic_dev->hwdev,
1814 HINIC_LINK_FOLLOW_PORT);
1815 if (err == HINIC_MGMT_CMD_UNSUPPORTED)
1816 PMD_DRV_LOG(WARNING, "Don't support to set link status follow phy port status");
1820 return hinic_set_anti_attack(nic_dev->hwdev, true);
1823 static int32_t hinic_card_workmode_check(struct hinic_nic_dev *nic_dev)
1825 struct hinic_board_info info = { 0 };
1828 rc = hinic_get_board_info(nic_dev->hwdev, &info);
1832 return (info.service_mode == HINIC_SERVICE_MODE_NIC ? HINIC_OK :
1836 static int hinic_copy_mempool_init(struct hinic_nic_dev *nic_dev)
1838 nic_dev->cpy_mpool = rte_mempool_lookup(nic_dev->proc_dev_name);
1839 if (nic_dev->cpy_mpool == NULL) {
1840 nic_dev->cpy_mpool =
1841 rte_pktmbuf_pool_create(nic_dev->proc_dev_name,
1842 HINIC_COPY_MEMPOOL_DEPTH,
1843 RTE_CACHE_LINE_SIZE, 0,
1844 HINIC_COPY_MBUF_SIZE,
1846 if (!nic_dev->cpy_mpool) {
1847 PMD_DRV_LOG(ERR, "Create copy mempool failed, errno: %d, dev_name: %s",
1848 rte_errno, nic_dev->proc_dev_name);
1856 static void hinic_copy_mempool_uninit(struct hinic_nic_dev *nic_dev)
1858 if (nic_dev->cpy_mpool != NULL)
1859 rte_mempool_free(nic_dev->cpy_mpool);
1862 static int hinic_init_sw_rxtxqs(struct hinic_nic_dev *nic_dev)
1867 /* allocate software txq array */
1868 txq_size = nic_dev->nic_cap.max_sqs * sizeof(*nic_dev->txqs);
1869 nic_dev->txqs = kzalloc_aligned(txq_size, GFP_KERNEL);
1870 if (!nic_dev->txqs) {
1871 PMD_DRV_LOG(ERR, "Allocate txqs failed");
1875 /* allocate software rxq array */
1876 rxq_size = nic_dev->nic_cap.max_rqs * sizeof(*nic_dev->rxqs);
1877 nic_dev->rxqs = kzalloc_aligned(rxq_size, GFP_KERNEL);
1878 if (!nic_dev->rxqs) {
1880 kfree(nic_dev->txqs);
1881 nic_dev->txqs = NULL;
1883 PMD_DRV_LOG(ERR, "Allocate rxqs failed");
1890 static void hinic_deinit_sw_rxtxqs(struct hinic_nic_dev *nic_dev)
1892 kfree(nic_dev->txqs);
1893 nic_dev->txqs = NULL;
1895 kfree(nic_dev->rxqs);
1896 nic_dev->rxqs = NULL;
1899 static int hinic_nic_dev_create(struct rte_eth_dev *eth_dev)
1901 struct hinic_nic_dev *nic_dev =
1902 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);
1905 nic_dev->hwdev = rte_zmalloc("hinic_hwdev", sizeof(*nic_dev->hwdev),
1906 RTE_CACHE_LINE_SIZE);
1907 if (!nic_dev->hwdev) {
1908 PMD_DRV_LOG(ERR, "Allocate hinic hwdev memory failed, dev_name: %s",
1909 eth_dev->data->name);
1912 nic_dev->hwdev->pcidev_hdl = RTE_ETH_DEV_TO_PCI(eth_dev);
1915 rc = hinic_osdep_init(nic_dev->hwdev);
1917 PMD_DRV_LOG(ERR, "Initialize os_dep failed, dev_name: %s",
1918 eth_dev->data->name);
1919 goto init_osdep_fail;
1923 rc = hinic_hwif_res_init(nic_dev->hwdev);
1925 PMD_DRV_LOG(ERR, "Initialize hwif failed, dev_name: %s",
1926 eth_dev->data->name);
1927 goto init_hwif_fail;
1931 rc = init_cfg_mgmt(nic_dev->hwdev);
1933 PMD_DRV_LOG(ERR, "Initialize cfg_mgmt failed, dev_name: %s",
1934 eth_dev->data->name);
1935 goto init_cfgmgnt_fail;
1939 rc = hinic_comm_aeqs_init(nic_dev->hwdev);
1941 PMD_DRV_LOG(ERR, "Initialize aeqs failed, dev_name: %s",
1942 eth_dev->data->name);
1943 goto init_aeqs_fail;
1946 /* init_pf_to_mgnt */
1947 rc = hinic_comm_pf_to_mgmt_init(nic_dev->hwdev);
1949 PMD_DRV_LOG(ERR, "Initialize pf_to_mgmt failed, dev_name: %s",
1950 eth_dev->data->name);
1951 goto init_pf_to_mgmt_fail;
1954 rc = hinic_card_workmode_check(nic_dev);
1956 PMD_DRV_LOG(ERR, "Check card workmode failed, dev_name: %s",
1957 eth_dev->data->name);
1958 goto workmode_check_fail;
1961 /* do l2nic reset to make chip clear */
1962 rc = hinic_l2nic_reset(nic_dev->hwdev);
1964 PMD_DRV_LOG(ERR, "Do l2nic reset failed, dev_name: %s",
1965 eth_dev->data->name);
1966 goto l2nic_reset_fail;
1969 /* init dma and aeq msix attribute table */
1970 (void)hinic_init_attr_table(nic_dev->hwdev);
1973 rc = hinic_comm_cmdqs_init(nic_dev->hwdev);
1975 PMD_DRV_LOG(ERR, "Initialize cmdq failed, dev_name: %s",
1976 eth_dev->data->name);
1977 goto init_cmdq_fail;
1980 /* set hardware state active */
1981 rc = hinic_activate_hwdev_state(nic_dev->hwdev);
1983 PMD_DRV_LOG(ERR, "Initialize resources state failed, dev_name: %s",
1984 eth_dev->data->name);
1985 goto init_resources_state_fail;
1988 /* init_capability */
1989 rc = hinic_init_capability(nic_dev->hwdev);
1991 PMD_DRV_LOG(ERR, "Initialize capability failed, dev_name: %s",
1992 eth_dev->data->name);
1996 /* get nic capability */
1997 if (!hinic_support_nic(nic_dev->hwdev, &nic_dev->nic_cap))
1998 goto nic_check_fail;
2000 /* init root cla and function table */
2001 rc = hinic_init_nicio(nic_dev->hwdev);
2003 PMD_DRV_LOG(ERR, "Initialize nic_io failed, dev_name: %s",
2004 eth_dev->data->name);
2005 goto init_nicio_fail;
2008 /* init_software_txrxq */
2009 rc = hinic_init_sw_rxtxqs(nic_dev);
2011 PMD_DRV_LOG(ERR, "Initialize sw_rxtxqs failed, dev_name: %s",
2012 eth_dev->data->name);
2013 goto init_sw_rxtxqs_fail;
2016 rc = hinic_copy_mempool_init(nic_dev);
2018 PMD_DRV_LOG(ERR, "Create copy mempool failed, dev_name: %s",
2019 eth_dev->data->name);
2020 goto init_mpool_fail;
2023 /* set hardware feature to default status */
2024 rc = hinic_set_default_hw_feature(nic_dev);
2026 PMD_DRV_LOG(ERR, "Initialize hardware default features failed, dev_name: %s",
2027 eth_dev->data->name);
2028 goto set_default_hw_feature_fail;
2033 set_default_hw_feature_fail:
2034 hinic_copy_mempool_uninit(nic_dev);
2037 hinic_deinit_sw_rxtxqs(nic_dev);
2039 init_sw_rxtxqs_fail:
2040 hinic_deinit_nicio(nic_dev->hwdev);
2045 hinic_deactivate_hwdev_state(nic_dev->hwdev);
2047 init_resources_state_fail:
2048 hinic_comm_cmdqs_free(nic_dev->hwdev);
2052 workmode_check_fail:
2053 hinic_comm_pf_to_mgmt_free(nic_dev->hwdev);
2055 init_pf_to_mgmt_fail:
2056 hinic_comm_aeqs_free(nic_dev->hwdev);
2059 free_cfg_mgmt(nic_dev->hwdev);
2062 hinic_hwif_res_free(nic_dev->hwdev);
2065 hinic_osdep_deinit(nic_dev->hwdev);
2068 rte_free(nic_dev->hwdev);
2069 nic_dev->hwdev = NULL;
2074 static void hinic_nic_dev_destroy(struct rte_eth_dev *eth_dev)
2076 struct hinic_nic_dev *nic_dev =
2077 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);
2079 (void)hinic_set_link_status_follow(nic_dev->hwdev,
2080 HINIC_LINK_FOLLOW_DEFAULT);
2081 hinic_copy_mempool_uninit(nic_dev);
2082 hinic_deinit_sw_rxtxqs(nic_dev);
2083 hinic_deinit_nicio(nic_dev->hwdev);
2084 hinic_deactivate_hwdev_state(nic_dev->hwdev);
2085 hinic_comm_cmdqs_free(nic_dev->hwdev);
2086 hinic_comm_pf_to_mgmt_free(nic_dev->hwdev);
2087 hinic_comm_aeqs_free(nic_dev->hwdev);
2088 free_cfg_mgmt(nic_dev->hwdev);
2089 hinic_hwif_res_free(nic_dev->hwdev);
2090 hinic_osdep_deinit(nic_dev->hwdev);
2091 rte_free(nic_dev->hwdev);
2092 nic_dev->hwdev = NULL;
2095 static int hinic_func_init(struct rte_eth_dev *eth_dev)
2097 struct rte_pci_device *pci_dev;
2098 struct rte_ether_addr *eth_addr;
2099 struct hinic_nic_dev *nic_dev;
2102 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2104 /* EAL is SECONDARY and eth_dev is already created */
2105 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2106 rc = rte_intr_callback_register(&pci_dev->intr_handle,
2107 hinic_dev_interrupt_handler,
2110 PMD_DRV_LOG(ERR, "Initialize %s failed in secondary process",
2111 eth_dev->data->name);
2116 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);
2117 memset(nic_dev, 0, sizeof(*nic_dev));
2119 snprintf(nic_dev->proc_dev_name,
2120 sizeof(nic_dev->proc_dev_name),
2121 "hinic-%.4x:%.2x:%.2x.%x",
2122 pci_dev->addr.domain, pci_dev->addr.bus,
2123 pci_dev->addr.devid, pci_dev->addr.function);
2125 /* alloc mac_addrs */
2126 eth_addr = rte_zmalloc("hinic_mac", sizeof(*eth_addr), 0);
2128 PMD_DRV_LOG(ERR, "Allocate ethernet addresses' memory failed, dev_name: %s",
2129 eth_dev->data->name);
2133 eth_dev->data->mac_addrs = eth_addr;
2136 * Pass the information to the rte_eth_dev_close() that it should also
2137 * release the private port resources.
2139 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2141 /* create hardware nic_device */
2142 rc = hinic_nic_dev_create(eth_dev);
2144 PMD_DRV_LOG(ERR, "Create nic device failed, dev_name: %s",
2145 eth_dev->data->name);
2146 goto create_nic_dev_fail;
2149 rc = hinic_init_mac_addr(eth_dev);
2151 PMD_DRV_LOG(ERR, "Initialize mac table failed, dev_name: %s",
2152 eth_dev->data->name);
2156 /* register callback func to eal lib */
2157 rc = rte_intr_callback_register(&pci_dev->intr_handle,
2158 hinic_dev_interrupt_handler,
2161 PMD_DRV_LOG(ERR, "Register rte interrupt callback failed, dev_name: %s",
2162 eth_dev->data->name);
2163 goto reg_intr_cb_fail;
2166 /* enable uio/vfio intr/eventfd mapping */
2167 rc = rte_intr_enable(&pci_dev->intr_handle);
2169 PMD_DRV_LOG(ERR, "Enable rte interrupt failed, dev_name: %s",
2170 eth_dev->data->name);
2171 goto enable_intr_fail;
2173 hinic_set_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status);
2175 hinic_set_bit(HINIC_DEV_INIT, &nic_dev->dev_status);
2176 PMD_DRV_LOG(INFO, "Initialize %s in primary successfully",
2177 eth_dev->data->name);
2182 (void)rte_intr_callback_unregister(&pci_dev->intr_handle,
2183 hinic_dev_interrupt_handler,
2187 hinic_deinit_mac_addr(eth_dev);
2190 hinic_nic_dev_destroy(eth_dev);
2192 create_nic_dev_fail:
2194 eth_dev->data->mac_addrs = NULL;
2197 PMD_DRV_LOG(ERR, "Initialize %s in primary failed",
2198 eth_dev->data->name);
2203 * DPDK callback to close the device.
2206 * Pointer to Ethernet device structure.
2208 static void hinic_dev_close(struct rte_eth_dev *dev)
2210 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
2212 if (hinic_test_and_set_bit(HINIC_DEV_CLOSE, &nic_dev->dev_status)) {
2213 PMD_DRV_LOG(WARNING, "Device %s already closed",
2218 /* stop device first */
2219 hinic_dev_stop(dev);
2221 /* rx_cqe, rx_info */
2222 hinic_free_all_rx_resources(dev);
2225 hinic_free_all_tx_resources(dev);
2227 /* free wq, pi_dma_addr */
2228 hinic_free_all_rq(nic_dev);
2230 /* free wq, db_addr */
2231 hinic_free_all_sq(nic_dev);
2233 /* deinit mac vlan tbl */
2234 hinic_deinit_mac_addr(dev);
2236 /* disable hardware and uio interrupt */
2237 hinic_disable_interrupt(dev);
2239 /* deinit nic hardware device */
2240 hinic_nic_dev_destroy(dev);
2243 static const struct eth_dev_ops hinic_pmd_ops = {
2244 .dev_configure = hinic_dev_configure,
2245 .dev_infos_get = hinic_dev_infos_get,
2246 .rx_queue_setup = hinic_rx_queue_setup,
2247 .tx_queue_setup = hinic_tx_queue_setup,
2248 .dev_start = hinic_dev_start,
2249 .link_update = hinic_link_update,
2250 .rx_queue_release = hinic_rx_queue_release,
2251 .tx_queue_release = hinic_tx_queue_release,
2252 .dev_stop = hinic_dev_stop,
2253 .dev_close = hinic_dev_close,
2254 .promiscuous_enable = hinic_dev_promiscuous_enable,
2255 .promiscuous_disable = hinic_dev_promiscuous_disable,
2256 .rss_hash_update = hinic_rss_hash_update,
2257 .rss_hash_conf_get = hinic_rss_conf_get,
2258 .reta_update = hinic_rss_indirtbl_update,
2259 .reta_query = hinic_rss_indirtbl_query,
2260 .stats_get = hinic_dev_stats_get,
2261 .stats_reset = hinic_dev_stats_reset,
2262 .xstats_get = hinic_dev_xstats_get,
2263 .xstats_reset = hinic_dev_xstats_reset,
2264 .xstats_get_names = hinic_dev_xstats_get_names,
2267 static int hinic_dev_init(struct rte_eth_dev *eth_dev)
2269 struct rte_pci_device *pci_dev;
2271 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2273 PMD_DRV_LOG(INFO, "Initializing pf hinic-%.4x:%.2x:%.2x.%x in %s process",
2274 pci_dev->addr.domain, pci_dev->addr.bus,
2275 pci_dev->addr.devid, pci_dev->addr.function,
2276 (rte_eal_process_type() == RTE_PROC_PRIMARY) ?
2277 "primary" : "secondary");
2279 /* rte_eth_dev ops, rx_burst and tx_burst */
2280 eth_dev->dev_ops = &hinic_pmd_ops;
2281 eth_dev->rx_pkt_burst = hinic_recv_pkts;
2282 eth_dev->tx_pkt_burst = hinic_xmit_pkts;
2284 return hinic_func_init(eth_dev);
2287 static int hinic_dev_uninit(struct rte_eth_dev *dev)
2289 struct hinic_nic_dev *nic_dev;
2291 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
2292 hinic_clear_bit(HINIC_DEV_INIT, &nic_dev->dev_status);
2294 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2297 hinic_dev_close(dev);
2299 dev->dev_ops = NULL;
2300 dev->rx_pkt_burst = NULL;
2301 dev->tx_pkt_burst = NULL;
2303 rte_free(dev->data->mac_addrs);
2304 dev->data->mac_addrs = NULL;
2309 static struct rte_pci_id pci_id_hinic_map[] = {
2310 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_PRD) },
2311 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_25GE) },
2312 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_40GE) },
2313 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_100GE) },
2317 static int hinic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2318 struct rte_pci_device *pci_dev)
2320 return rte_eth_dev_pci_generic_probe(pci_dev,
2321 sizeof(struct hinic_nic_dev), hinic_dev_init);
2324 static int hinic_pci_remove(struct rte_pci_device *pci_dev)
2326 return rte_eth_dev_pci_generic_remove(pci_dev, hinic_dev_uninit);
2329 static struct rte_pci_driver rte_hinic_pmd = {
2330 .id_table = pci_id_hinic_map,
2331 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2332 .probe = hinic_pci_probe,
2333 .remove = hinic_pci_remove,
2336 RTE_PMD_REGISTER_PCI(net_hinic, rte_hinic_pmd);
2337 RTE_PMD_REGISTER_PCI_TABLE(net_hinic, pci_id_hinic_map);
2339 RTE_INIT(hinic_init_log)
2341 hinic_logtype = rte_log_register("pmd.net.hinic");
2342 if (hinic_logtype >= 0)
2343 rte_log_set_level(hinic_logtype, RTE_LOG_INFO);