1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_A:
62 case I40E_DEV_ID_KX_B:
63 case I40E_DEV_ID_KX_C:
64 case I40E_DEV_ID_QSFP_A:
65 case I40E_DEV_ID_QSFP_B:
66 case I40E_DEV_ID_QSFP_C:
67 case I40E_DEV_ID_10G_BASE_T:
68 case I40E_DEV_ID_10G_BASE_T4:
69 case I40E_DEV_ID_20G_KR2:
70 case I40E_DEV_ID_20G_KR2_A:
71 hw->mac.type = I40E_MAC_XL710;
74 case I40E_DEV_ID_VF_HV:
75 hw->mac.type = I40E_MAC_VF;
78 hw->mac.type = I40E_MAC_GENERIC;
82 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
85 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
86 hw->mac.type, status);
90 #ifndef I40E_NDIS_SUPPORT
92 * i40e_aq_str - convert AQ err code to a string
93 * @hw: pointer to the HW structure
94 * @aq_err: the AQ error code to convert
96 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
101 case I40E_AQ_RC_EPERM:
102 return "I40E_AQ_RC_EPERM";
103 case I40E_AQ_RC_ENOENT:
104 return "I40E_AQ_RC_ENOENT";
105 case I40E_AQ_RC_ESRCH:
106 return "I40E_AQ_RC_ESRCH";
107 case I40E_AQ_RC_EINTR:
108 return "I40E_AQ_RC_EINTR";
110 return "I40E_AQ_RC_EIO";
111 case I40E_AQ_RC_ENXIO:
112 return "I40E_AQ_RC_ENXIO";
113 case I40E_AQ_RC_E2BIG:
114 return "I40E_AQ_RC_E2BIG";
115 case I40E_AQ_RC_EAGAIN:
116 return "I40E_AQ_RC_EAGAIN";
117 case I40E_AQ_RC_ENOMEM:
118 return "I40E_AQ_RC_ENOMEM";
119 case I40E_AQ_RC_EACCES:
120 return "I40E_AQ_RC_EACCES";
121 case I40E_AQ_RC_EFAULT:
122 return "I40E_AQ_RC_EFAULT";
123 case I40E_AQ_RC_EBUSY:
124 return "I40E_AQ_RC_EBUSY";
125 case I40E_AQ_RC_EEXIST:
126 return "I40E_AQ_RC_EEXIST";
127 case I40E_AQ_RC_EINVAL:
128 return "I40E_AQ_RC_EINVAL";
129 case I40E_AQ_RC_ENOTTY:
130 return "I40E_AQ_RC_ENOTTY";
131 case I40E_AQ_RC_ENOSPC:
132 return "I40E_AQ_RC_ENOSPC";
133 case I40E_AQ_RC_ENOSYS:
134 return "I40E_AQ_RC_ENOSYS";
135 case I40E_AQ_RC_ERANGE:
136 return "I40E_AQ_RC_ERANGE";
137 case I40E_AQ_RC_EFLUSHED:
138 return "I40E_AQ_RC_EFLUSHED";
139 case I40E_AQ_RC_BAD_ADDR:
140 return "I40E_AQ_RC_BAD_ADDR";
141 case I40E_AQ_RC_EMODE:
142 return "I40E_AQ_RC_EMODE";
143 case I40E_AQ_RC_EFBIG:
144 return "I40E_AQ_RC_EFBIG";
147 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
152 * i40e_stat_str - convert status err code to a string
153 * @hw: pointer to the HW structure
154 * @stat_err: the status error code to convert
156 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
162 return "I40E_ERR_NVM";
163 case I40E_ERR_NVM_CHECKSUM:
164 return "I40E_ERR_NVM_CHECKSUM";
166 return "I40E_ERR_PHY";
167 case I40E_ERR_CONFIG:
168 return "I40E_ERR_CONFIG";
170 return "I40E_ERR_PARAM";
171 case I40E_ERR_MAC_TYPE:
172 return "I40E_ERR_MAC_TYPE";
173 case I40E_ERR_UNKNOWN_PHY:
174 return "I40E_ERR_UNKNOWN_PHY";
175 case I40E_ERR_LINK_SETUP:
176 return "I40E_ERR_LINK_SETUP";
177 case I40E_ERR_ADAPTER_STOPPED:
178 return "I40E_ERR_ADAPTER_STOPPED";
179 case I40E_ERR_INVALID_MAC_ADDR:
180 return "I40E_ERR_INVALID_MAC_ADDR";
181 case I40E_ERR_DEVICE_NOT_SUPPORTED:
182 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
183 case I40E_ERR_MASTER_REQUESTS_PENDING:
184 return "I40E_ERR_MASTER_REQUESTS_PENDING";
185 case I40E_ERR_INVALID_LINK_SETTINGS:
186 return "I40E_ERR_INVALID_LINK_SETTINGS";
187 case I40E_ERR_AUTONEG_NOT_COMPLETE:
188 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
189 case I40E_ERR_RESET_FAILED:
190 return "I40E_ERR_RESET_FAILED";
191 case I40E_ERR_SWFW_SYNC:
192 return "I40E_ERR_SWFW_SYNC";
193 case I40E_ERR_NO_AVAILABLE_VSI:
194 return "I40E_ERR_NO_AVAILABLE_VSI";
195 case I40E_ERR_NO_MEMORY:
196 return "I40E_ERR_NO_MEMORY";
197 case I40E_ERR_BAD_PTR:
198 return "I40E_ERR_BAD_PTR";
199 case I40E_ERR_RING_FULL:
200 return "I40E_ERR_RING_FULL";
201 case I40E_ERR_INVALID_PD_ID:
202 return "I40E_ERR_INVALID_PD_ID";
203 case I40E_ERR_INVALID_QP_ID:
204 return "I40E_ERR_INVALID_QP_ID";
205 case I40E_ERR_INVALID_CQ_ID:
206 return "I40E_ERR_INVALID_CQ_ID";
207 case I40E_ERR_INVALID_CEQ_ID:
208 return "I40E_ERR_INVALID_CEQ_ID";
209 case I40E_ERR_INVALID_AEQ_ID:
210 return "I40E_ERR_INVALID_AEQ_ID";
211 case I40E_ERR_INVALID_SIZE:
212 return "I40E_ERR_INVALID_SIZE";
213 case I40E_ERR_INVALID_ARP_INDEX:
214 return "I40E_ERR_INVALID_ARP_INDEX";
215 case I40E_ERR_INVALID_FPM_FUNC_ID:
216 return "I40E_ERR_INVALID_FPM_FUNC_ID";
217 case I40E_ERR_QP_INVALID_MSG_SIZE:
218 return "I40E_ERR_QP_INVALID_MSG_SIZE";
219 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
220 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
221 case I40E_ERR_INVALID_FRAG_COUNT:
222 return "I40E_ERR_INVALID_FRAG_COUNT";
223 case I40E_ERR_QUEUE_EMPTY:
224 return "I40E_ERR_QUEUE_EMPTY";
225 case I40E_ERR_INVALID_ALIGNMENT:
226 return "I40E_ERR_INVALID_ALIGNMENT";
227 case I40E_ERR_FLUSHED_QUEUE:
228 return "I40E_ERR_FLUSHED_QUEUE";
229 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
230 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
231 case I40E_ERR_INVALID_IMM_DATA_SIZE:
232 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
233 case I40E_ERR_TIMEOUT:
234 return "I40E_ERR_TIMEOUT";
235 case I40E_ERR_OPCODE_MISMATCH:
236 return "I40E_ERR_OPCODE_MISMATCH";
237 case I40E_ERR_CQP_COMPL_ERROR:
238 return "I40E_ERR_CQP_COMPL_ERROR";
239 case I40E_ERR_INVALID_VF_ID:
240 return "I40E_ERR_INVALID_VF_ID";
241 case I40E_ERR_INVALID_HMCFN_ID:
242 return "I40E_ERR_INVALID_HMCFN_ID";
243 case I40E_ERR_BACKING_PAGE_ERROR:
244 return "I40E_ERR_BACKING_PAGE_ERROR";
245 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
246 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
247 case I40E_ERR_INVALID_PBLE_INDEX:
248 return "I40E_ERR_INVALID_PBLE_INDEX";
249 case I40E_ERR_INVALID_SD_INDEX:
250 return "I40E_ERR_INVALID_SD_INDEX";
251 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
252 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
253 case I40E_ERR_INVALID_SD_TYPE:
254 return "I40E_ERR_INVALID_SD_TYPE";
255 case I40E_ERR_MEMCPY_FAILED:
256 return "I40E_ERR_MEMCPY_FAILED";
257 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
258 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
259 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
260 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
261 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
262 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
263 case I40E_ERR_SRQ_ENABLED:
264 return "I40E_ERR_SRQ_ENABLED";
265 case I40E_ERR_ADMIN_QUEUE_ERROR:
266 return "I40E_ERR_ADMIN_QUEUE_ERROR";
267 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
268 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
269 case I40E_ERR_BUF_TOO_SHORT:
270 return "I40E_ERR_BUF_TOO_SHORT";
271 case I40E_ERR_ADMIN_QUEUE_FULL:
272 return "I40E_ERR_ADMIN_QUEUE_FULL";
273 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
274 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
275 case I40E_ERR_BAD_IWARP_CQE:
276 return "I40E_ERR_BAD_IWARP_CQE";
277 case I40E_ERR_NVM_BLANK_MODE:
278 return "I40E_ERR_NVM_BLANK_MODE";
279 case I40E_ERR_NOT_IMPLEMENTED:
280 return "I40E_ERR_NOT_IMPLEMENTED";
281 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
282 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
283 case I40E_ERR_DIAG_TEST_FAILED:
284 return "I40E_ERR_DIAG_TEST_FAILED";
285 case I40E_ERR_NOT_READY:
286 return "I40E_ERR_NOT_READY";
287 case I40E_NOT_SUPPORTED:
288 return "I40E_NOT_SUPPORTED";
289 case I40E_ERR_FIRMWARE_API_VERSION:
290 return "I40E_ERR_FIRMWARE_API_VERSION";
293 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
297 #endif /* I40E_NDIS_SUPPORT */
300 * @hw: debug mask related to admin queue
302 * @desc: pointer to admin queue descriptor
303 * @buffer: pointer to command buffer
304 * @buf_len: max length of buffer
306 * Dumps debug log about adminq command with descriptor contents.
308 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
309 void *buffer, u16 buf_len)
311 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
312 u16 len = LE16_TO_CPU(aq_desc->datalen);
313 u8 *buf = (u8 *)buffer;
316 if ((!(mask & hw->debug_mask)) || (desc == NULL))
320 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
321 LE16_TO_CPU(aq_desc->opcode),
322 LE16_TO_CPU(aq_desc->flags),
323 LE16_TO_CPU(aq_desc->datalen),
324 LE16_TO_CPU(aq_desc->retval));
325 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
326 LE32_TO_CPU(aq_desc->cookie_high),
327 LE32_TO_CPU(aq_desc->cookie_low));
328 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
329 LE32_TO_CPU(aq_desc->params.internal.param0),
330 LE32_TO_CPU(aq_desc->params.internal.param1));
331 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
332 LE32_TO_CPU(aq_desc->params.external.addr_high),
333 LE32_TO_CPU(aq_desc->params.external.addr_low));
335 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
336 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
339 /* write the full 16-byte chunks */
340 for (i = 0; i < (len - 16); i += 16)
342 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
343 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
344 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
345 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
346 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
347 /* the most we could have left is 16 bytes, pad with zeros */
352 memset(d_buf, 0, sizeof(d_buf));
353 for (j = 0; i < len; j++, i++)
356 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
357 i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
358 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
359 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
360 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
366 * i40e_check_asq_alive
367 * @hw: pointer to the hw struct
369 * Returns true if Queue is enabled else false.
371 bool i40e_check_asq_alive(struct i40e_hw *hw)
374 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
380 * i40e_aq_queue_shutdown
381 * @hw: pointer to the hw struct
382 * @unloading: is the driver unloading itself
384 * Tell the Firmware that we're shutting down the AdminQ and whether
385 * or not the driver is unloading as well.
387 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
390 struct i40e_aq_desc desc;
391 struct i40e_aqc_queue_shutdown *cmd =
392 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
393 enum i40e_status_code status;
395 i40e_fill_default_direct_cmd_desc(&desc,
396 i40e_aqc_opc_queue_shutdown);
399 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
400 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
405 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
406 * hardware to a bit-field that can be used by SW to more easily determine the
409 * Macros are used to shorten the table lines and make this table human
412 * We store the PTYPE in the top byte of the bit field - this is just so that
413 * we can check that the table doesn't have a row missing, as the index into
414 * the table should be the PTYPE.
418 * IF NOT i40e_ptype_lookup[ptype].known
421 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
422 * Use the rest of the fields to look at the tunnels, inner protocols, etc
424 * Use the enum i40e_rx_l2_ptype to decode the packet type
428 /* macro to make the table lines short */
429 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
432 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
433 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
434 I40E_RX_PTYPE_##OUTER_FRAG, \
435 I40E_RX_PTYPE_TUNNEL_##T, \
436 I40E_RX_PTYPE_TUNNEL_END_##TE, \
437 I40E_RX_PTYPE_##TEF, \
438 I40E_RX_PTYPE_INNER_PROT_##I, \
439 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
441 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
442 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
444 /* shorter macros makes the table fit but are terse */
445 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
446 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
447 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
449 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
450 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
451 /* L2 Packet types */
452 I40E_PTT_UNUSED_ENTRY(0),
453 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
454 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
455 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
456 I40E_PTT_UNUSED_ENTRY(4),
457 I40E_PTT_UNUSED_ENTRY(5),
458 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
459 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
460 I40E_PTT_UNUSED_ENTRY(8),
461 I40E_PTT_UNUSED_ENTRY(9),
462 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
463 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
464 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
465 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
466 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
467 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
468 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
469 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
470 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
471 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
472 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
473 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
475 /* Non Tunneled IPv4 */
476 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
477 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
478 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
479 I40E_PTT_UNUSED_ENTRY(25),
480 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
481 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
482 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
485 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
486 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
487 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
488 I40E_PTT_UNUSED_ENTRY(32),
489 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
490 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
491 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
494 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
495 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
496 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
497 I40E_PTT_UNUSED_ENTRY(39),
498 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
499 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
500 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
502 /* IPv4 --> GRE/NAT */
503 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
505 /* IPv4 --> GRE/NAT --> IPv4 */
506 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
507 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
508 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
509 I40E_PTT_UNUSED_ENTRY(47),
510 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
511 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
512 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
514 /* IPv4 --> GRE/NAT --> IPv6 */
515 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
516 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
517 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
518 I40E_PTT_UNUSED_ENTRY(54),
519 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
520 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
521 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
523 /* IPv4 --> GRE/NAT --> MAC */
524 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
526 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
527 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
528 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
529 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
530 I40E_PTT_UNUSED_ENTRY(62),
531 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
532 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
533 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
535 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
536 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
537 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
538 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
539 I40E_PTT_UNUSED_ENTRY(69),
540 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
541 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
542 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
544 /* IPv4 --> GRE/NAT --> MAC/VLAN */
545 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
547 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
548 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
549 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
550 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
551 I40E_PTT_UNUSED_ENTRY(77),
552 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
553 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
554 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
556 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
557 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
558 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
559 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
560 I40E_PTT_UNUSED_ENTRY(84),
561 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
562 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
563 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
565 /* Non Tunneled IPv6 */
566 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
567 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
568 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
569 I40E_PTT_UNUSED_ENTRY(91),
570 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
571 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
572 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
575 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
576 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
577 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
578 I40E_PTT_UNUSED_ENTRY(98),
579 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
580 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
581 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
584 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
585 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
586 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
587 I40E_PTT_UNUSED_ENTRY(105),
588 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
589 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
590 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
592 /* IPv6 --> GRE/NAT */
593 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
595 /* IPv6 --> GRE/NAT -> IPv4 */
596 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
597 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
598 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
599 I40E_PTT_UNUSED_ENTRY(113),
600 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
601 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
602 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
604 /* IPv6 --> GRE/NAT -> IPv6 */
605 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
606 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
607 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
608 I40E_PTT_UNUSED_ENTRY(120),
609 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
610 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
611 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
613 /* IPv6 --> GRE/NAT -> MAC */
614 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
616 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
617 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
618 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
619 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
620 I40E_PTT_UNUSED_ENTRY(128),
621 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
622 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
623 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
625 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
626 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
627 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
628 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
629 I40E_PTT_UNUSED_ENTRY(135),
630 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
631 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
632 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
634 /* IPv6 --> GRE/NAT -> MAC/VLAN */
635 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
637 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
638 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
639 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
640 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
641 I40E_PTT_UNUSED_ENTRY(143),
642 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
643 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
644 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
646 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
647 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
648 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
649 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
650 I40E_PTT_UNUSED_ENTRY(150),
651 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
652 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
653 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
656 I40E_PTT_UNUSED_ENTRY(154),
657 I40E_PTT_UNUSED_ENTRY(155),
658 I40E_PTT_UNUSED_ENTRY(156),
659 I40E_PTT_UNUSED_ENTRY(157),
660 I40E_PTT_UNUSED_ENTRY(158),
661 I40E_PTT_UNUSED_ENTRY(159),
663 I40E_PTT_UNUSED_ENTRY(160),
664 I40E_PTT_UNUSED_ENTRY(161),
665 I40E_PTT_UNUSED_ENTRY(162),
666 I40E_PTT_UNUSED_ENTRY(163),
667 I40E_PTT_UNUSED_ENTRY(164),
668 I40E_PTT_UNUSED_ENTRY(165),
669 I40E_PTT_UNUSED_ENTRY(166),
670 I40E_PTT_UNUSED_ENTRY(167),
671 I40E_PTT_UNUSED_ENTRY(168),
672 I40E_PTT_UNUSED_ENTRY(169),
674 I40E_PTT_UNUSED_ENTRY(170),
675 I40E_PTT_UNUSED_ENTRY(171),
676 I40E_PTT_UNUSED_ENTRY(172),
677 I40E_PTT_UNUSED_ENTRY(173),
678 I40E_PTT_UNUSED_ENTRY(174),
679 I40E_PTT_UNUSED_ENTRY(175),
680 I40E_PTT_UNUSED_ENTRY(176),
681 I40E_PTT_UNUSED_ENTRY(177),
682 I40E_PTT_UNUSED_ENTRY(178),
683 I40E_PTT_UNUSED_ENTRY(179),
685 I40E_PTT_UNUSED_ENTRY(180),
686 I40E_PTT_UNUSED_ENTRY(181),
687 I40E_PTT_UNUSED_ENTRY(182),
688 I40E_PTT_UNUSED_ENTRY(183),
689 I40E_PTT_UNUSED_ENTRY(184),
690 I40E_PTT_UNUSED_ENTRY(185),
691 I40E_PTT_UNUSED_ENTRY(186),
692 I40E_PTT_UNUSED_ENTRY(187),
693 I40E_PTT_UNUSED_ENTRY(188),
694 I40E_PTT_UNUSED_ENTRY(189),
696 I40E_PTT_UNUSED_ENTRY(190),
697 I40E_PTT_UNUSED_ENTRY(191),
698 I40E_PTT_UNUSED_ENTRY(192),
699 I40E_PTT_UNUSED_ENTRY(193),
700 I40E_PTT_UNUSED_ENTRY(194),
701 I40E_PTT_UNUSED_ENTRY(195),
702 I40E_PTT_UNUSED_ENTRY(196),
703 I40E_PTT_UNUSED_ENTRY(197),
704 I40E_PTT_UNUSED_ENTRY(198),
705 I40E_PTT_UNUSED_ENTRY(199),
707 I40E_PTT_UNUSED_ENTRY(200),
708 I40E_PTT_UNUSED_ENTRY(201),
709 I40E_PTT_UNUSED_ENTRY(202),
710 I40E_PTT_UNUSED_ENTRY(203),
711 I40E_PTT_UNUSED_ENTRY(204),
712 I40E_PTT_UNUSED_ENTRY(205),
713 I40E_PTT_UNUSED_ENTRY(206),
714 I40E_PTT_UNUSED_ENTRY(207),
715 I40E_PTT_UNUSED_ENTRY(208),
716 I40E_PTT_UNUSED_ENTRY(209),
718 I40E_PTT_UNUSED_ENTRY(210),
719 I40E_PTT_UNUSED_ENTRY(211),
720 I40E_PTT_UNUSED_ENTRY(212),
721 I40E_PTT_UNUSED_ENTRY(213),
722 I40E_PTT_UNUSED_ENTRY(214),
723 I40E_PTT_UNUSED_ENTRY(215),
724 I40E_PTT_UNUSED_ENTRY(216),
725 I40E_PTT_UNUSED_ENTRY(217),
726 I40E_PTT_UNUSED_ENTRY(218),
727 I40E_PTT_UNUSED_ENTRY(219),
729 I40E_PTT_UNUSED_ENTRY(220),
730 I40E_PTT_UNUSED_ENTRY(221),
731 I40E_PTT_UNUSED_ENTRY(222),
732 I40E_PTT_UNUSED_ENTRY(223),
733 I40E_PTT_UNUSED_ENTRY(224),
734 I40E_PTT_UNUSED_ENTRY(225),
735 I40E_PTT_UNUSED_ENTRY(226),
736 I40E_PTT_UNUSED_ENTRY(227),
737 I40E_PTT_UNUSED_ENTRY(228),
738 I40E_PTT_UNUSED_ENTRY(229),
740 I40E_PTT_UNUSED_ENTRY(230),
741 I40E_PTT_UNUSED_ENTRY(231),
742 I40E_PTT_UNUSED_ENTRY(232),
743 I40E_PTT_UNUSED_ENTRY(233),
744 I40E_PTT_UNUSED_ENTRY(234),
745 I40E_PTT_UNUSED_ENTRY(235),
746 I40E_PTT_UNUSED_ENTRY(236),
747 I40E_PTT_UNUSED_ENTRY(237),
748 I40E_PTT_UNUSED_ENTRY(238),
749 I40E_PTT_UNUSED_ENTRY(239),
751 I40E_PTT_UNUSED_ENTRY(240),
752 I40E_PTT_UNUSED_ENTRY(241),
753 I40E_PTT_UNUSED_ENTRY(242),
754 I40E_PTT_UNUSED_ENTRY(243),
755 I40E_PTT_UNUSED_ENTRY(244),
756 I40E_PTT_UNUSED_ENTRY(245),
757 I40E_PTT_UNUSED_ENTRY(246),
758 I40E_PTT_UNUSED_ENTRY(247),
759 I40E_PTT_UNUSED_ENTRY(248),
760 I40E_PTT_UNUSED_ENTRY(249),
762 I40E_PTT_UNUSED_ENTRY(250),
763 I40E_PTT_UNUSED_ENTRY(251),
764 I40E_PTT_UNUSED_ENTRY(252),
765 I40E_PTT_UNUSED_ENTRY(253),
766 I40E_PTT_UNUSED_ENTRY(254),
767 I40E_PTT_UNUSED_ENTRY(255)
772 * i40e_validate_mac_addr - Validate unicast MAC address
773 * @mac_addr: pointer to MAC address
775 * Tests a MAC address to ensure it is a valid Individual Address
777 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
779 enum i40e_status_code status = I40E_SUCCESS;
781 DEBUGFUNC("i40e_validate_mac_addr");
783 /* Broadcast addresses ARE multicast addresses
784 * Make sure it is not a multicast address
785 * Reject the zero address
787 if (I40E_IS_MULTICAST(mac_addr) ||
788 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
789 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
790 status = I40E_ERR_INVALID_MAC_ADDR;
797 * i40e_init_shared_code - Initialize the shared code
798 * @hw: pointer to hardware structure
800 * This assigns the MAC type and PHY code and inits the NVM.
801 * Does not touch the hardware. This function must be called prior to any
802 * other function in the shared code. The i40e_hw structure should be
803 * memset to 0 prior to calling this function. The following fields in
804 * hw structure should be filled in prior to calling this function:
805 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
806 * subsystem_vendor_id, and revision_id
808 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
810 enum i40e_status_code status = I40E_SUCCESS;
811 u32 port, ari, func_rid;
813 DEBUGFUNC("i40e_init_shared_code");
815 i40e_set_mac_type(hw);
817 switch (hw->mac.type) {
821 return I40E_ERR_DEVICE_NOT_SUPPORTED;
824 hw->phy.get_link_info = true;
826 /* Determine port number and PF number*/
827 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
828 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
830 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
831 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
832 func_rid = rd32(hw, I40E_PF_FUNC_RID);
834 hw->pf_id = (u8)(func_rid & 0xff);
836 hw->pf_id = (u8)(func_rid & 0x7);
838 status = i40e_init_nvm(hw);
843 * i40e_aq_mac_address_read - Retrieve the MAC addresses
844 * @hw: pointer to the hw struct
845 * @flags: a return indicator of what addresses were added to the addr store
846 * @addrs: the requestor's mac addr store
847 * @cmd_details: pointer to command details structure or NULL
849 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
851 struct i40e_aqc_mac_address_read_data *addrs,
852 struct i40e_asq_cmd_details *cmd_details)
854 struct i40e_aq_desc desc;
855 struct i40e_aqc_mac_address_read *cmd_data =
856 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
857 enum i40e_status_code status;
859 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
860 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
862 status = i40e_asq_send_command(hw, &desc, addrs,
863 sizeof(*addrs), cmd_details);
864 *flags = LE16_TO_CPU(cmd_data->command_flags);
870 * i40e_aq_mac_address_write - Change the MAC addresses
871 * @hw: pointer to the hw struct
872 * @flags: indicates which MAC to be written
873 * @mac_addr: address to write
874 * @cmd_details: pointer to command details structure or NULL
876 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
877 u16 flags, u8 *mac_addr,
878 struct i40e_asq_cmd_details *cmd_details)
880 struct i40e_aq_desc desc;
881 struct i40e_aqc_mac_address_write *cmd_data =
882 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
883 enum i40e_status_code status;
885 i40e_fill_default_direct_cmd_desc(&desc,
886 i40e_aqc_opc_mac_address_write);
887 cmd_data->command_flags = CPU_TO_LE16(flags);
888 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
889 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
890 ((u32)mac_addr[3] << 16) |
891 ((u32)mac_addr[4] << 8) |
894 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
900 * i40e_get_mac_addr - get MAC address
901 * @hw: pointer to the HW structure
902 * @mac_addr: pointer to MAC address
904 * Reads the adapter's MAC address from register
906 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
908 struct i40e_aqc_mac_address_read_data addrs;
909 enum i40e_status_code status;
912 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
914 if (flags & I40E_AQC_LAN_ADDR_VALID)
915 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
921 * i40e_get_port_mac_addr - get Port MAC address
922 * @hw: pointer to the HW structure
923 * @mac_addr: pointer to Port MAC address
925 * Reads the adapter's Port MAC address
927 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
929 struct i40e_aqc_mac_address_read_data addrs;
930 enum i40e_status_code status;
933 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
937 if (flags & I40E_AQC_PORT_ADDR_VALID)
938 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
940 status = I40E_ERR_INVALID_MAC_ADDR;
946 * i40e_pre_tx_queue_cfg - pre tx queue configure
947 * @hw: pointer to the HW structure
948 * @queue: target pf queue index
949 * @enable: state change request
951 * Handles hw requirement to indicate intention to enable
952 * or disable target queue.
954 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
956 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
960 if (abs_queue_idx >= 128) {
961 reg_block = abs_queue_idx / 128;
962 abs_queue_idx %= 128;
965 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
966 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
967 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
970 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
972 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
974 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
978 * i40e_read_pba_string - Reads part number string from EEPROM
979 * @hw: pointer to hardware structure
980 * @pba_num: stores the part number string from the EEPROM
981 * @pba_num_size: part number string buffer length
983 * Reads the part number string from the EEPROM.
985 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
988 enum i40e_status_code status = I40E_SUCCESS;
994 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
995 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
996 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1000 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1001 if (status != I40E_SUCCESS) {
1002 DEBUGOUT("Failed to read PBA Block pointer.\n");
1006 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1007 if (status != I40E_SUCCESS) {
1008 DEBUGOUT("Failed to read PBA Block size.\n");
1012 /* Subtract one to get PBA word count (PBA Size word is included in
1016 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1017 DEBUGOUT("Buffer to small for PBA data.\n");
1018 return I40E_ERR_PARAM;
1021 for (i = 0; i < pba_size; i++) {
1022 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1023 if (status != I40E_SUCCESS) {
1024 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1028 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1029 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1031 pba_num[(pba_size * 2)] = '\0';
1037 * i40e_get_media_type - Gets media type
1038 * @hw: pointer to the hardware structure
1040 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1042 enum i40e_media_type media;
1044 switch (hw->phy.link_info.phy_type) {
1045 case I40E_PHY_TYPE_10GBASE_SR:
1046 case I40E_PHY_TYPE_10GBASE_LR:
1047 case I40E_PHY_TYPE_1000BASE_SX:
1048 case I40E_PHY_TYPE_1000BASE_LX:
1049 case I40E_PHY_TYPE_40GBASE_SR4:
1050 case I40E_PHY_TYPE_40GBASE_LR4:
1051 media = I40E_MEDIA_TYPE_FIBER;
1053 case I40E_PHY_TYPE_100BASE_TX:
1054 case I40E_PHY_TYPE_1000BASE_T:
1055 case I40E_PHY_TYPE_10GBASE_T:
1056 media = I40E_MEDIA_TYPE_BASET;
1058 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1059 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1060 case I40E_PHY_TYPE_10GBASE_CR1:
1061 case I40E_PHY_TYPE_40GBASE_CR4:
1062 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1063 case I40E_PHY_TYPE_40GBASE_AOC:
1064 case I40E_PHY_TYPE_10GBASE_AOC:
1065 media = I40E_MEDIA_TYPE_DA;
1067 case I40E_PHY_TYPE_1000BASE_KX:
1068 case I40E_PHY_TYPE_10GBASE_KX4:
1069 case I40E_PHY_TYPE_10GBASE_KR:
1070 case I40E_PHY_TYPE_40GBASE_KR4:
1071 case I40E_PHY_TYPE_20GBASE_KR2:
1072 media = I40E_MEDIA_TYPE_BACKPLANE;
1074 case I40E_PHY_TYPE_SGMII:
1075 case I40E_PHY_TYPE_XAUI:
1076 case I40E_PHY_TYPE_XFI:
1077 case I40E_PHY_TYPE_XLAUI:
1078 case I40E_PHY_TYPE_XLPPI:
1080 media = I40E_MEDIA_TYPE_UNKNOWN;
1087 #define I40E_PF_RESET_WAIT_COUNT 110
1089 * i40e_pf_reset - Reset the PF
1090 * @hw: pointer to the hardware structure
1092 * Assuming someone else has triggered a global reset,
1093 * assure the global reset is complete and then reset the PF
1095 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1102 /* Poll for Global Reset steady state in case of recent GRST.
1103 * The grst delay value is in 100ms units, and we'll wait a
1104 * couple counts longer to be sure we don't just miss the end.
1106 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1107 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1108 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1109 for (cnt = 0; cnt < grst_del + 2; cnt++) {
1110 reg = rd32(hw, I40E_GLGEN_RSTAT);
1111 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1113 i40e_msec_delay(100);
1115 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1116 DEBUGOUT("Global reset polling failed to complete.\n");
1117 return I40E_ERR_RESET_FAILED;
1120 /* Now Wait for the FW to be ready */
1121 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1122 reg = rd32(hw, I40E_GLNVM_ULD);
1123 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1124 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1125 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1126 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1127 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1130 i40e_msec_delay(10);
1132 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1133 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1134 DEBUGOUT("wait for FW Reset complete timedout\n");
1135 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1136 return I40E_ERR_RESET_FAILED;
1139 /* If there was a Global Reset in progress when we got here,
1140 * we don't need to do the PF Reset
1143 reg = rd32(hw, I40E_PFGEN_CTRL);
1144 wr32(hw, I40E_PFGEN_CTRL,
1145 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1146 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1147 reg = rd32(hw, I40E_PFGEN_CTRL);
1148 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1152 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1153 DEBUGOUT("PF reset polling failed to complete.\n");
1154 return I40E_ERR_RESET_FAILED;
1158 i40e_clear_pxe_mode(hw);
1161 return I40E_SUCCESS;
1165 * i40e_clear_hw - clear out any left over hw state
1166 * @hw: pointer to the hw struct
1168 * Clear queues and interrupts, typically called at init time,
1169 * but after the capabilities have been found so we know how many
1170 * queues and msix vectors have been allocated.
1172 void i40e_clear_hw(struct i40e_hw *hw)
1174 u32 num_queues, base_queue;
1182 /* get number of interrupts, queues, and vfs */
1183 val = rd32(hw, I40E_GLPCI_CNF2);
1184 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1185 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1186 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1187 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1189 val = rd32(hw, I40E_PFLAN_QALLOC);
1190 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1191 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1192 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1193 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1194 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1195 num_queues = (j - base_queue) + 1;
1199 val = rd32(hw, I40E_PF_VT_PFALLOC);
1200 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1201 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1202 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1203 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1204 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1205 num_vfs = (j - i) + 1;
1209 /* stop all the interrupts */
1210 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1211 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1212 for (i = 0; i < num_pf_int - 2; i++)
1213 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1215 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1216 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1217 wr32(hw, I40E_PFINT_LNKLST0, val);
1218 for (i = 0; i < num_pf_int - 2; i++)
1219 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1220 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1221 for (i = 0; i < num_vfs; i++)
1222 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1223 for (i = 0; i < num_vf_int - 2; i++)
1224 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1226 /* warn the HW of the coming Tx disables */
1227 for (i = 0; i < num_queues; i++) {
1228 u32 abs_queue_idx = base_queue + i;
1231 if (abs_queue_idx >= 128) {
1232 reg_block = abs_queue_idx / 128;
1233 abs_queue_idx %= 128;
1236 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1237 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1238 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1239 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1241 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1243 i40e_usec_delay(400);
1245 /* stop all the queues */
1246 for (i = 0; i < num_queues; i++) {
1247 wr32(hw, I40E_QINT_TQCTL(i), 0);
1248 wr32(hw, I40E_QTX_ENA(i), 0);
1249 wr32(hw, I40E_QINT_RQCTL(i), 0);
1250 wr32(hw, I40E_QRX_ENA(i), 0);
1253 /* short wait for all queue disables to settle */
1254 i40e_usec_delay(50);
1258 * i40e_clear_pxe_mode - clear pxe operations mode
1259 * @hw: pointer to the hw struct
1261 * Make sure all PXE mode settings are cleared, including things
1262 * like descriptor fetch/write-back mode.
1264 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1266 if (i40e_check_asq_alive(hw))
1267 i40e_aq_clear_pxe_mode(hw, NULL);
1271 * i40e_led_is_mine - helper to find matching led
1272 * @hw: pointer to the hw struct
1273 * @idx: index into GPIO registers
1275 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1277 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1282 if (!hw->func_caps.led[idx])
1285 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1286 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1287 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1289 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1290 * if it is not our port then ignore
1292 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1299 #define I40E_COMBINED_ACTIVITY 0xA
1300 #define I40E_FILTER_ACTIVITY 0xE
1301 #define I40E_LINK_ACTIVITY 0xC
1302 #define I40E_MAC_ACTIVITY 0xD
1303 #define I40E_LED0 22
1306 * i40e_led_get - return current on/off mode
1307 * @hw: pointer to the hw struct
1309 * The value returned is the 'mode' field as defined in the
1310 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1311 * values are variations of possible behaviors relating to
1312 * blink, link, and wire.
1314 u32 i40e_led_get(struct i40e_hw *hw)
1316 u32 current_mode = 0;
1320 /* as per the documentation GPIO 22-29 are the LED
1321 * GPIO pins named LED0..LED7
1323 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1324 u32 gpio_val = i40e_led_is_mine(hw, i);
1329 /* ignore gpio LED src mode entries related to the activity LEDs */
1330 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1331 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1332 switch (current_mode) {
1333 case I40E_COMBINED_ACTIVITY:
1334 case I40E_FILTER_ACTIVITY:
1335 case I40E_MAC_ACTIVITY:
1341 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1342 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1350 * i40e_led_set - set new on/off mode
1351 * @hw: pointer to the hw struct
1352 * @mode: 0=off, 0xf=on (else see manual for mode details)
1353 * @blink: true if the LED should blink when on, false if steady
1355 * if this function is used to turn on the blink it should
1356 * be used to disable the blink when restoring the original state.
1358 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1360 u32 current_mode = 0;
1363 if (mode & 0xfffffff0)
1364 DEBUGOUT1("invalid mode passed in %X\n", mode);
1366 /* as per the documentation GPIO 22-29 are the LED
1367 * GPIO pins named LED0..LED7
1369 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1370 u32 gpio_val = i40e_led_is_mine(hw, i);
1375 /* ignore gpio LED src mode entries related to the activity LEDs */
1376 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1377 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1378 switch (current_mode) {
1379 case I40E_COMBINED_ACTIVITY:
1380 case I40E_FILTER_ACTIVITY:
1381 case I40E_MAC_ACTIVITY:
1387 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1388 /* this & is a bit of paranoia, but serves as a range check */
1389 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1390 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1392 if (mode == I40E_LINK_ACTIVITY)
1396 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1398 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1400 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1405 /* Admin command wrappers */
1408 * i40e_aq_get_phy_capabilities
1409 * @hw: pointer to the hw struct
1410 * @abilities: structure for PHY capabilities to be filled
1411 * @qualified_modules: report Qualified Modules
1412 * @report_init: report init capabilities (active are default)
1413 * @cmd_details: pointer to command details structure or NULL
1415 * Returns the various PHY abilities supported on the Port.
1417 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1418 bool qualified_modules, bool report_init,
1419 struct i40e_aq_get_phy_abilities_resp *abilities,
1420 struct i40e_asq_cmd_details *cmd_details)
1422 struct i40e_aq_desc desc;
1423 enum i40e_status_code status;
1424 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1427 return I40E_ERR_PARAM;
1429 i40e_fill_default_direct_cmd_desc(&desc,
1430 i40e_aqc_opc_get_phy_abilities);
1432 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1433 if (abilities_size > I40E_AQ_LARGE_BUF)
1434 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1436 if (qualified_modules)
1437 desc.params.external.param0 |=
1438 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1441 desc.params.external.param0 |=
1442 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1444 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1447 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1448 status = I40E_ERR_UNKNOWN_PHY;
1454 * i40e_aq_set_phy_config
1455 * @hw: pointer to the hw struct
1456 * @config: structure with PHY configuration to be set
1457 * @cmd_details: pointer to command details structure or NULL
1459 * Set the various PHY configuration parameters
1460 * supported on the Port.One or more of the Set PHY config parameters may be
1461 * ignored in an MFP mode as the PF may not have the privilege to set some
1462 * of the PHY Config parameters. This status will be indicated by the
1465 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1466 struct i40e_aq_set_phy_config *config,
1467 struct i40e_asq_cmd_details *cmd_details)
1469 struct i40e_aq_desc desc;
1470 struct i40e_aq_set_phy_config *cmd =
1471 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1472 enum i40e_status_code status;
1475 return I40E_ERR_PARAM;
1477 i40e_fill_default_direct_cmd_desc(&desc,
1478 i40e_aqc_opc_set_phy_config);
1482 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1489 * @hw: pointer to the hw struct
1491 * Set the requested flow control mode using set_phy_config.
1493 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1494 bool atomic_restart)
1496 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1497 struct i40e_aq_get_phy_abilities_resp abilities;
1498 struct i40e_aq_set_phy_config config;
1499 enum i40e_status_code status;
1500 u8 pause_mask = 0x0;
1506 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1507 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1509 case I40E_FC_RX_PAUSE:
1510 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1512 case I40E_FC_TX_PAUSE:
1513 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1519 /* Get the current phy config */
1520 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1523 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1527 memset(&config, 0, sizeof(config));
1528 /* clear the old pause settings */
1529 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1530 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1531 /* set the new abilities */
1532 config.abilities |= pause_mask;
1533 /* If the abilities have changed, then set the new config */
1534 if (config.abilities != abilities.abilities) {
1535 /* Auto restart link so settings take effect */
1537 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1538 /* Copy over all the old settings */
1539 config.phy_type = abilities.phy_type;
1540 config.link_speed = abilities.link_speed;
1541 config.eee_capability = abilities.eee_capability;
1542 config.eeer = abilities.eeer_val;
1543 config.low_power_ctrl = abilities.d3_lpan;
1544 status = i40e_aq_set_phy_config(hw, &config, NULL);
1547 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1549 /* Update the link info */
1550 status = i40e_update_link_info(hw);
1552 /* Wait a little bit (on 40G cards it sometimes takes a really
1553 * long time for link to come back from the atomic reset)
1556 i40e_msec_delay(1000);
1557 status = i40e_update_link_info(hw);
1560 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1566 * i40e_aq_set_mac_config
1567 * @hw: pointer to the hw struct
1568 * @max_frame_size: Maximum Frame Size to be supported by the port
1569 * @crc_en: Tell HW to append a CRC to outgoing frames
1570 * @pacing: Pacing configurations
1571 * @cmd_details: pointer to command details structure or NULL
1573 * Configure MAC settings for frame size, jumbo frame support and the
1574 * addition of a CRC by the hardware.
1576 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1578 bool crc_en, u16 pacing,
1579 struct i40e_asq_cmd_details *cmd_details)
1581 struct i40e_aq_desc desc;
1582 struct i40e_aq_set_mac_config *cmd =
1583 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1584 enum i40e_status_code status;
1586 if (max_frame_size == 0)
1587 return I40E_ERR_PARAM;
1589 i40e_fill_default_direct_cmd_desc(&desc,
1590 i40e_aqc_opc_set_mac_config);
1592 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1593 cmd->params = ((u8)pacing & 0x0F) << 3;
1595 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1597 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1603 * i40e_aq_clear_pxe_mode
1604 * @hw: pointer to the hw struct
1605 * @cmd_details: pointer to command details structure or NULL
1607 * Tell the firmware that the driver is taking over from PXE
1609 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1610 struct i40e_asq_cmd_details *cmd_details)
1612 enum i40e_status_code status;
1613 struct i40e_aq_desc desc;
1614 struct i40e_aqc_clear_pxe *cmd =
1615 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1617 i40e_fill_default_direct_cmd_desc(&desc,
1618 i40e_aqc_opc_clear_pxe_mode);
1622 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1624 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1630 * i40e_aq_set_link_restart_an
1631 * @hw: pointer to the hw struct
1632 * @enable_link: if true: enable link, if false: disable link
1633 * @cmd_details: pointer to command details structure or NULL
1635 * Sets up the link and restarts the Auto-Negotiation over the link.
1637 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1638 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1640 struct i40e_aq_desc desc;
1641 struct i40e_aqc_set_link_restart_an *cmd =
1642 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1643 enum i40e_status_code status;
1645 i40e_fill_default_direct_cmd_desc(&desc,
1646 i40e_aqc_opc_set_link_restart_an);
1648 cmd->command = I40E_AQ_PHY_RESTART_AN;
1650 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1652 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1654 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1660 * i40e_aq_get_link_info
1661 * @hw: pointer to the hw struct
1662 * @enable_lse: enable/disable LinkStatusEvent reporting
1663 * @link: pointer to link status structure - optional
1664 * @cmd_details: pointer to command details structure or NULL
1666 * Returns the link status of the adapter.
1668 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1669 bool enable_lse, struct i40e_link_status *link,
1670 struct i40e_asq_cmd_details *cmd_details)
1672 struct i40e_aq_desc desc;
1673 struct i40e_aqc_get_link_status *resp =
1674 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1675 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1676 enum i40e_status_code status;
1677 bool tx_pause, rx_pause;
1680 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1683 command_flags = I40E_AQ_LSE_ENABLE;
1685 command_flags = I40E_AQ_LSE_DISABLE;
1686 resp->command_flags = CPU_TO_LE16(command_flags);
1688 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1690 if (status != I40E_SUCCESS)
1691 goto aq_get_link_info_exit;
1693 /* save off old link status information */
1694 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1695 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1697 /* update link status */
1698 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1699 hw->phy.media_type = i40e_get_media_type(hw);
1700 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1701 hw_link_info->link_info = resp->link_info;
1702 hw_link_info->an_info = resp->an_info;
1703 hw_link_info->ext_info = resp->ext_info;
1704 hw_link_info->loopback = resp->loopback;
1705 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1706 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1708 /* update fc info */
1709 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1710 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1711 if (tx_pause & rx_pause)
1712 hw->fc.current_mode = I40E_FC_FULL;
1714 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1716 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1718 hw->fc.current_mode = I40E_FC_NONE;
1720 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1721 hw_link_info->crc_enable = true;
1723 hw_link_info->crc_enable = false;
1725 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1726 hw_link_info->lse_enable = true;
1728 hw_link_info->lse_enable = false;
1730 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1731 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1732 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1734 /* save link status information */
1736 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1737 I40E_NONDMA_TO_NONDMA);
1739 /* flag cleared so helper functions don't call AQ again */
1740 hw->phy.get_link_info = false;
1742 aq_get_link_info_exit:
1747 * i40e_aq_set_phy_int_mask
1748 * @hw: pointer to the hw struct
1749 * @mask: interrupt mask to be set
1750 * @cmd_details: pointer to command details structure or NULL
1752 * Set link interrupt mask.
1754 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1756 struct i40e_asq_cmd_details *cmd_details)
1758 struct i40e_aq_desc desc;
1759 struct i40e_aqc_set_phy_int_mask *cmd =
1760 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1761 enum i40e_status_code status;
1763 i40e_fill_default_direct_cmd_desc(&desc,
1764 i40e_aqc_opc_set_phy_int_mask);
1766 cmd->event_mask = CPU_TO_LE16(mask);
1768 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1774 * i40e_aq_get_local_advt_reg
1775 * @hw: pointer to the hw struct
1776 * @advt_reg: local AN advertisement register value
1777 * @cmd_details: pointer to command details structure or NULL
1779 * Get the Local AN advertisement register value.
1781 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1783 struct i40e_asq_cmd_details *cmd_details)
1785 struct i40e_aq_desc desc;
1786 struct i40e_aqc_an_advt_reg *resp =
1787 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1788 enum i40e_status_code status;
1790 i40e_fill_default_direct_cmd_desc(&desc,
1791 i40e_aqc_opc_get_local_advt_reg);
1793 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1795 if (status != I40E_SUCCESS)
1796 goto aq_get_local_advt_reg_exit;
1798 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1799 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1801 aq_get_local_advt_reg_exit:
1806 * i40e_aq_set_local_advt_reg
1807 * @hw: pointer to the hw struct
1808 * @advt_reg: local AN advertisement register value
1809 * @cmd_details: pointer to command details structure or NULL
1811 * Get the Local AN advertisement register value.
1813 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1815 struct i40e_asq_cmd_details *cmd_details)
1817 struct i40e_aq_desc desc;
1818 struct i40e_aqc_an_advt_reg *cmd =
1819 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1820 enum i40e_status_code status;
1822 i40e_fill_default_direct_cmd_desc(&desc,
1823 i40e_aqc_opc_get_local_advt_reg);
1825 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
1826 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
1828 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1834 * i40e_aq_get_partner_advt
1835 * @hw: pointer to the hw struct
1836 * @advt_reg: AN partner advertisement register value
1837 * @cmd_details: pointer to command details structure or NULL
1839 * Get the link partner AN advertisement register value.
1841 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
1843 struct i40e_asq_cmd_details *cmd_details)
1845 struct i40e_aq_desc desc;
1846 struct i40e_aqc_an_advt_reg *resp =
1847 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1848 enum i40e_status_code status;
1850 i40e_fill_default_direct_cmd_desc(&desc,
1851 i40e_aqc_opc_get_partner_advt);
1853 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1855 if (status != I40E_SUCCESS)
1856 goto aq_get_partner_advt_exit;
1858 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1859 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1861 aq_get_partner_advt_exit:
1866 * i40e_aq_set_lb_modes
1867 * @hw: pointer to the hw struct
1868 * @lb_modes: loopback mode to be set
1869 * @cmd_details: pointer to command details structure or NULL
1871 * Sets loopback modes.
1873 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
1875 struct i40e_asq_cmd_details *cmd_details)
1877 struct i40e_aq_desc desc;
1878 struct i40e_aqc_set_lb_mode *cmd =
1879 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1880 enum i40e_status_code status;
1882 i40e_fill_default_direct_cmd_desc(&desc,
1883 i40e_aqc_opc_set_lb_modes);
1885 cmd->lb_mode = CPU_TO_LE16(lb_modes);
1887 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1893 * i40e_aq_set_phy_debug
1894 * @hw: pointer to the hw struct
1895 * @cmd_flags: debug command flags
1896 * @cmd_details: pointer to command details structure or NULL
1898 * Reset the external PHY.
1900 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1901 struct i40e_asq_cmd_details *cmd_details)
1903 struct i40e_aq_desc desc;
1904 struct i40e_aqc_set_phy_debug *cmd =
1905 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1906 enum i40e_status_code status;
1908 i40e_fill_default_direct_cmd_desc(&desc,
1909 i40e_aqc_opc_set_phy_debug);
1911 cmd->command_flags = cmd_flags;
1913 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1920 * @hw: pointer to the hw struct
1921 * @vsi_ctx: pointer to a vsi context struct
1922 * @cmd_details: pointer to command details structure or NULL
1924 * Add a VSI context to the hardware.
1926 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
1927 struct i40e_vsi_context *vsi_ctx,
1928 struct i40e_asq_cmd_details *cmd_details)
1930 struct i40e_aq_desc desc;
1931 struct i40e_aqc_add_get_update_vsi *cmd =
1932 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1933 struct i40e_aqc_add_get_update_vsi_completion *resp =
1934 (struct i40e_aqc_add_get_update_vsi_completion *)
1936 enum i40e_status_code status;
1938 i40e_fill_default_direct_cmd_desc(&desc,
1939 i40e_aqc_opc_add_vsi);
1941 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
1942 cmd->connection_type = vsi_ctx->connection_type;
1943 cmd->vf_id = vsi_ctx->vf_num;
1944 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
1946 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1948 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1949 sizeof(vsi_ctx->info), cmd_details);
1951 if (status != I40E_SUCCESS)
1952 goto aq_add_vsi_exit;
1954 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
1955 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
1956 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
1957 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
1964 * i40e_aq_set_default_vsi
1965 * @hw: pointer to the hw struct
1967 * @cmd_details: pointer to command details structure or NULL
1969 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
1971 struct i40e_asq_cmd_details *cmd_details)
1973 struct i40e_aq_desc desc;
1974 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1975 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1977 enum i40e_status_code status;
1979 i40e_fill_default_direct_cmd_desc(&desc,
1980 i40e_aqc_opc_set_vsi_promiscuous_modes);
1982 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1983 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
1984 cmd->seid = CPU_TO_LE16(seid);
1986 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1992 * i40e_aq_set_vsi_unicast_promiscuous
1993 * @hw: pointer to the hw struct
1995 * @set: set unicast promiscuous enable/disable
1996 * @cmd_details: pointer to command details structure or NULL
1998 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2000 struct i40e_asq_cmd_details *cmd_details)
2002 struct i40e_aq_desc desc;
2003 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2004 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2005 enum i40e_status_code status;
2008 i40e_fill_default_direct_cmd_desc(&desc,
2009 i40e_aqc_opc_set_vsi_promiscuous_modes);
2012 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2014 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2016 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2018 cmd->seid = CPU_TO_LE16(seid);
2019 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2025 * i40e_aq_set_vsi_multicast_promiscuous
2026 * @hw: pointer to the hw struct
2028 * @set: set multicast promiscuous enable/disable
2029 * @cmd_details: pointer to command details structure or NULL
2031 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2032 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2034 struct i40e_aq_desc desc;
2035 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2036 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2037 enum i40e_status_code status;
2040 i40e_fill_default_direct_cmd_desc(&desc,
2041 i40e_aqc_opc_set_vsi_promiscuous_modes);
2044 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2046 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2048 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2050 cmd->seid = CPU_TO_LE16(seid);
2051 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2057 * i40e_aq_set_vsi_mc_promisc_on_vlan
2058 * @hw: pointer to the hw struct
2060 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2061 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2062 * @cmd_details: pointer to command details structure or NULL
2064 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2065 u16 seid, bool enable, u16 vid,
2066 struct i40e_asq_cmd_details *cmd_details)
2068 struct i40e_aq_desc desc;
2069 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2070 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2071 enum i40e_status_code status;
2074 i40e_fill_default_direct_cmd_desc(&desc,
2075 i40e_aqc_opc_set_vsi_promiscuous_modes);
2078 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2080 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2081 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2082 cmd->seid = CPU_TO_LE16(seid);
2083 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2085 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2091 * i40e_aq_set_vsi_uc_promisc_on_vlan
2092 * @hw: pointer to the hw struct
2094 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2095 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2096 * @cmd_details: pointer to command details structure or NULL
2098 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2099 u16 seid, bool enable, u16 vid,
2100 struct i40e_asq_cmd_details *cmd_details)
2102 struct i40e_aq_desc desc;
2103 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2104 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2105 enum i40e_status_code status;
2108 i40e_fill_default_direct_cmd_desc(&desc,
2109 i40e_aqc_opc_set_vsi_promiscuous_modes);
2112 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2114 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2115 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2116 cmd->seid = CPU_TO_LE16(seid);
2117 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2119 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2125 * i40e_aq_set_vsi_broadcast
2126 * @hw: pointer to the hw struct
2128 * @set_filter: true to set filter, false to clear filter
2129 * @cmd_details: pointer to command details structure or NULL
2131 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2133 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2134 u16 seid, bool set_filter,
2135 struct i40e_asq_cmd_details *cmd_details)
2137 struct i40e_aq_desc desc;
2138 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2139 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2140 enum i40e_status_code status;
2142 i40e_fill_default_direct_cmd_desc(&desc,
2143 i40e_aqc_opc_set_vsi_promiscuous_modes);
2146 cmd->promiscuous_flags
2147 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2149 cmd->promiscuous_flags
2150 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2152 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2153 cmd->seid = CPU_TO_LE16(seid);
2154 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2160 * i40e_get_vsi_params - get VSI configuration info
2161 * @hw: pointer to the hw struct
2162 * @vsi_ctx: pointer to a vsi context struct
2163 * @cmd_details: pointer to command details structure or NULL
2165 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2166 struct i40e_vsi_context *vsi_ctx,
2167 struct i40e_asq_cmd_details *cmd_details)
2169 struct i40e_aq_desc desc;
2170 struct i40e_aqc_add_get_update_vsi *cmd =
2171 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2172 struct i40e_aqc_add_get_update_vsi_completion *resp =
2173 (struct i40e_aqc_add_get_update_vsi_completion *)
2175 enum i40e_status_code status;
2177 UNREFERENCED_1PARAMETER(cmd_details);
2178 i40e_fill_default_direct_cmd_desc(&desc,
2179 i40e_aqc_opc_get_vsi_parameters);
2181 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2183 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2185 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2186 sizeof(vsi_ctx->info), NULL);
2188 if (status != I40E_SUCCESS)
2189 goto aq_get_vsi_params_exit;
2191 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2192 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2193 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2194 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2196 aq_get_vsi_params_exit:
2201 * i40e_aq_update_vsi_params
2202 * @hw: pointer to the hw struct
2203 * @vsi_ctx: pointer to a vsi context struct
2204 * @cmd_details: pointer to command details structure or NULL
2206 * Update a VSI context.
2208 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2209 struct i40e_vsi_context *vsi_ctx,
2210 struct i40e_asq_cmd_details *cmd_details)
2212 struct i40e_aq_desc desc;
2213 struct i40e_aqc_add_get_update_vsi *cmd =
2214 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2215 enum i40e_status_code status;
2217 i40e_fill_default_direct_cmd_desc(&desc,
2218 i40e_aqc_opc_update_vsi_parameters);
2219 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2221 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2223 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2224 sizeof(vsi_ctx->info), cmd_details);
2230 * i40e_aq_get_switch_config
2231 * @hw: pointer to the hardware structure
2232 * @buf: pointer to the result buffer
2233 * @buf_size: length of input buffer
2234 * @start_seid: seid to start for the report, 0 == beginning
2235 * @cmd_details: pointer to command details structure or NULL
2237 * Fill the buf with switch configuration returned from AdminQ command
2239 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2240 struct i40e_aqc_get_switch_config_resp *buf,
2241 u16 buf_size, u16 *start_seid,
2242 struct i40e_asq_cmd_details *cmd_details)
2244 struct i40e_aq_desc desc;
2245 struct i40e_aqc_switch_seid *scfg =
2246 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2247 enum i40e_status_code status;
2249 i40e_fill_default_direct_cmd_desc(&desc,
2250 i40e_aqc_opc_get_switch_config);
2251 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2252 if (buf_size > I40E_AQ_LARGE_BUF)
2253 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2254 scfg->seid = CPU_TO_LE16(*start_seid);
2256 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2257 *start_seid = LE16_TO_CPU(scfg->seid);
2263 * i40e_aq_get_firmware_version
2264 * @hw: pointer to the hw struct
2265 * @fw_major_version: firmware major version
2266 * @fw_minor_version: firmware minor version
2267 * @fw_build: firmware build number
2268 * @api_major_version: major queue version
2269 * @api_minor_version: minor queue version
2270 * @cmd_details: pointer to command details structure or NULL
2272 * Get the firmware version from the admin queue commands
2274 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2275 u16 *fw_major_version, u16 *fw_minor_version,
2277 u16 *api_major_version, u16 *api_minor_version,
2278 struct i40e_asq_cmd_details *cmd_details)
2280 struct i40e_aq_desc desc;
2281 struct i40e_aqc_get_version *resp =
2282 (struct i40e_aqc_get_version *)&desc.params.raw;
2283 enum i40e_status_code status;
2285 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2287 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2289 if (status == I40E_SUCCESS) {
2290 if (fw_major_version != NULL)
2291 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2292 if (fw_minor_version != NULL)
2293 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2294 if (fw_build != NULL)
2295 *fw_build = LE32_TO_CPU(resp->fw_build);
2296 if (api_major_version != NULL)
2297 *api_major_version = LE16_TO_CPU(resp->api_major);
2298 if (api_minor_version != NULL)
2299 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2301 /* A workaround to fix the API version in SW */
2302 if (api_major_version && api_minor_version &&
2303 fw_major_version && fw_minor_version &&
2304 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2305 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2306 (*fw_major_version > 4)))
2307 *api_minor_version = 2;
2314 * i40e_aq_send_driver_version
2315 * @hw: pointer to the hw struct
2316 * @dv: driver's major, minor version
2317 * @cmd_details: pointer to command details structure or NULL
2319 * Send the driver version to the firmware
2321 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2322 struct i40e_driver_version *dv,
2323 struct i40e_asq_cmd_details *cmd_details)
2325 struct i40e_aq_desc desc;
2326 struct i40e_aqc_driver_version *cmd =
2327 (struct i40e_aqc_driver_version *)&desc.params.raw;
2328 enum i40e_status_code status;
2332 return I40E_ERR_PARAM;
2334 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2336 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2337 cmd->driver_major_ver = dv->major_version;
2338 cmd->driver_minor_ver = dv->minor_version;
2339 cmd->driver_build_ver = dv->build_version;
2340 cmd->driver_subbuild_ver = dv->subbuild_version;
2343 while (len < sizeof(dv->driver_string) &&
2344 (dv->driver_string[len] < 0x80) &&
2345 dv->driver_string[len])
2347 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2354 * i40e_get_link_status - get status of the HW network link
2355 * @hw: pointer to the hw struct
2356 * @link_up: pointer to bool (true/false = linkup/linkdown)
2358 * Variable link_up true if link is up, false if link is down.
2359 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2361 * Side effect: LinkStatusEvent reporting becomes enabled
2363 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2365 enum i40e_status_code status = I40E_SUCCESS;
2367 if (hw->phy.get_link_info) {
2368 status = i40e_update_link_info(hw);
2370 if (status != I40E_SUCCESS)
2371 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2375 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2381 * i40e_updatelink_status - update status of the HW network link
2382 * @hw: pointer to the hw struct
2384 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2386 struct i40e_aq_get_phy_abilities_resp abilities;
2387 enum i40e_status_code status = I40E_SUCCESS;
2389 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2393 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
2398 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2399 sizeof(hw->phy.link_info.module_type));
2405 * i40e_get_link_speed
2406 * @hw: pointer to the hw struct
2408 * Returns the link speed of the adapter.
2410 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2412 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2413 enum i40e_status_code status = I40E_SUCCESS;
2415 if (hw->phy.get_link_info) {
2416 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2418 if (status != I40E_SUCCESS)
2419 goto i40e_link_speed_exit;
2422 speed = hw->phy.link_info.link_speed;
2424 i40e_link_speed_exit:
2429 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2430 * @hw: pointer to the hw struct
2431 * @uplink_seid: the MAC or other gizmo SEID
2432 * @downlink_seid: the VSI SEID
2433 * @enabled_tc: bitmap of TCs to be enabled
2434 * @default_port: true for default port VSI, false for control port
2435 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2436 * @veb_seid: pointer to where to put the resulting VEB SEID
2437 * @cmd_details: pointer to command details structure or NULL
2439 * This asks the FW to add a VEB between the uplink and downlink
2440 * elements. If the uplink SEID is 0, this will be a floating VEB.
2442 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2443 u16 downlink_seid, u8 enabled_tc,
2444 bool default_port, bool enable_l2_filtering,
2446 struct i40e_asq_cmd_details *cmd_details)
2448 struct i40e_aq_desc desc;
2449 struct i40e_aqc_add_veb *cmd =
2450 (struct i40e_aqc_add_veb *)&desc.params.raw;
2451 struct i40e_aqc_add_veb_completion *resp =
2452 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2453 enum i40e_status_code status;
2456 /* SEIDs need to either both be set or both be 0 for floating VEB */
2457 if (!!uplink_seid != !!downlink_seid)
2458 return I40E_ERR_PARAM;
2460 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2462 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2463 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2464 cmd->enable_tcs = enabled_tc;
2466 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2468 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2470 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2472 if (enable_l2_filtering)
2473 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2475 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2477 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2479 if (!status && veb_seid)
2480 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2486 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2487 * @hw: pointer to the hw struct
2488 * @veb_seid: the SEID of the VEB to query
2489 * @switch_id: the uplink switch id
2490 * @floating: set to true if the VEB is floating
2491 * @statistic_index: index of the stats counter block for this VEB
2492 * @vebs_used: number of VEB's used by function
2493 * @vebs_free: total VEB's not reserved by any function
2494 * @cmd_details: pointer to command details structure or NULL
2496 * This retrieves the parameters for a particular VEB, specified by
2497 * uplink_seid, and returns them to the caller.
2499 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2500 u16 veb_seid, u16 *switch_id,
2501 bool *floating, u16 *statistic_index,
2502 u16 *vebs_used, u16 *vebs_free,
2503 struct i40e_asq_cmd_details *cmd_details)
2505 struct i40e_aq_desc desc;
2506 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2507 (struct i40e_aqc_get_veb_parameters_completion *)
2509 enum i40e_status_code status;
2512 return I40E_ERR_PARAM;
2514 i40e_fill_default_direct_cmd_desc(&desc,
2515 i40e_aqc_opc_get_veb_parameters);
2516 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2518 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2523 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2524 if (statistic_index)
2525 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2527 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2529 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2531 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2532 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2543 * i40e_aq_add_macvlan
2544 * @hw: pointer to the hw struct
2545 * @seid: VSI for the mac address
2546 * @mv_list: list of macvlans to be added
2547 * @count: length of the list
2548 * @cmd_details: pointer to command details structure or NULL
2550 * Add MAC/VLAN addresses to the HW filtering
2552 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2553 struct i40e_aqc_add_macvlan_element_data *mv_list,
2554 u16 count, struct i40e_asq_cmd_details *cmd_details)
2556 struct i40e_aq_desc desc;
2557 struct i40e_aqc_macvlan *cmd =
2558 (struct i40e_aqc_macvlan *)&desc.params.raw;
2559 enum i40e_status_code status;
2562 if (count == 0 || !mv_list || !hw)
2563 return I40E_ERR_PARAM;
2565 buf_size = count * sizeof(*mv_list);
2567 /* prep the rest of the request */
2568 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2569 cmd->num_addresses = CPU_TO_LE16(count);
2570 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2574 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2575 if (buf_size > I40E_AQ_LARGE_BUF)
2576 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2578 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2585 * i40e_aq_remove_macvlan
2586 * @hw: pointer to the hw struct
2587 * @seid: VSI for the mac address
2588 * @mv_list: list of macvlans to be removed
2589 * @count: length of the list
2590 * @cmd_details: pointer to command details structure or NULL
2592 * Remove MAC/VLAN addresses from the HW filtering
2594 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2595 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2596 u16 count, struct i40e_asq_cmd_details *cmd_details)
2598 struct i40e_aq_desc desc;
2599 struct i40e_aqc_macvlan *cmd =
2600 (struct i40e_aqc_macvlan *)&desc.params.raw;
2601 enum i40e_status_code status;
2604 if (count == 0 || !mv_list || !hw)
2605 return I40E_ERR_PARAM;
2607 buf_size = count * sizeof(*mv_list);
2609 /* prep the rest of the request */
2610 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2611 cmd->num_addresses = CPU_TO_LE16(count);
2612 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2616 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2617 if (buf_size > I40E_AQ_LARGE_BUF)
2618 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2620 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2627 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2628 * @hw: pointer to the hw struct
2629 * @seid: VSI for the vlan filters
2630 * @v_list: list of vlan filters to be added
2631 * @count: length of the list
2632 * @cmd_details: pointer to command details structure or NULL
2634 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2635 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2636 u8 count, struct i40e_asq_cmd_details *cmd_details)
2638 struct i40e_aq_desc desc;
2639 struct i40e_aqc_macvlan *cmd =
2640 (struct i40e_aqc_macvlan *)&desc.params.raw;
2641 enum i40e_status_code status;
2644 if (count == 0 || !v_list || !hw)
2645 return I40E_ERR_PARAM;
2647 buf_size = count * sizeof(*v_list);
2649 /* prep the rest of the request */
2650 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2651 cmd->num_addresses = CPU_TO_LE16(count);
2652 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2656 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2657 if (buf_size > I40E_AQ_LARGE_BUF)
2658 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2660 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2667 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2668 * @hw: pointer to the hw struct
2669 * @seid: VSI for the vlan filters
2670 * @v_list: list of macvlans to be removed
2671 * @count: length of the list
2672 * @cmd_details: pointer to command details structure or NULL
2674 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2675 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2676 u8 count, struct i40e_asq_cmd_details *cmd_details)
2678 struct i40e_aq_desc desc;
2679 struct i40e_aqc_macvlan *cmd =
2680 (struct i40e_aqc_macvlan *)&desc.params.raw;
2681 enum i40e_status_code status;
2684 if (count == 0 || !v_list || !hw)
2685 return I40E_ERR_PARAM;
2687 buf_size = count * sizeof(*v_list);
2689 /* prep the rest of the request */
2690 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2691 cmd->num_addresses = CPU_TO_LE16(count);
2692 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2696 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2697 if (buf_size > I40E_AQ_LARGE_BUF)
2698 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2700 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2707 * i40e_aq_send_msg_to_vf
2708 * @hw: pointer to the hardware structure
2709 * @vfid: vf id to send msg
2710 * @v_opcode: opcodes for VF-PF communication
2711 * @v_retval: return error code
2712 * @msg: pointer to the msg buffer
2713 * @msglen: msg length
2714 * @cmd_details: pointer to command details
2718 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2719 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2720 struct i40e_asq_cmd_details *cmd_details)
2722 struct i40e_aq_desc desc;
2723 struct i40e_aqc_pf_vf_message *cmd =
2724 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2725 enum i40e_status_code status;
2727 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2728 cmd->id = CPU_TO_LE32(vfid);
2729 desc.cookie_high = CPU_TO_LE32(v_opcode);
2730 desc.cookie_low = CPU_TO_LE32(v_retval);
2731 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2733 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2735 if (msglen > I40E_AQ_LARGE_BUF)
2736 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2737 desc.datalen = CPU_TO_LE16(msglen);
2739 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2745 * i40e_aq_debug_read_register
2746 * @hw: pointer to the hw struct
2747 * @reg_addr: register address
2748 * @reg_val: register value
2749 * @cmd_details: pointer to command details structure or NULL
2751 * Read the register using the admin queue commands
2753 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2754 u32 reg_addr, u64 *reg_val,
2755 struct i40e_asq_cmd_details *cmd_details)
2757 struct i40e_aq_desc desc;
2758 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2759 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2760 enum i40e_status_code status;
2762 if (reg_val == NULL)
2763 return I40E_ERR_PARAM;
2765 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2767 cmd_resp->address = CPU_TO_LE32(reg_addr);
2769 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2771 if (status == I40E_SUCCESS) {
2772 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2773 (u64)LE32_TO_CPU(cmd_resp->value_low);
2780 * i40e_aq_debug_write_register
2781 * @hw: pointer to the hw struct
2782 * @reg_addr: register address
2783 * @reg_val: register value
2784 * @cmd_details: pointer to command details structure or NULL
2786 * Write to a register using the admin queue commands
2788 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
2789 u32 reg_addr, u64 reg_val,
2790 struct i40e_asq_cmd_details *cmd_details)
2792 struct i40e_aq_desc desc;
2793 struct i40e_aqc_debug_reg_read_write *cmd =
2794 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2795 enum i40e_status_code status;
2797 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2799 cmd->address = CPU_TO_LE32(reg_addr);
2800 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
2801 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
2803 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2809 * i40e_aq_get_hmc_resource_profile
2810 * @hw: pointer to the hw struct
2811 * @profile: type of profile the HMC is to be set as
2812 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2813 * @cmd_details: pointer to command details structure or NULL
2815 * query the HMC profile of the device.
2817 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
2818 enum i40e_aq_hmc_profile *profile,
2819 u8 *pe_vf_enabled_count,
2820 struct i40e_asq_cmd_details *cmd_details)
2822 struct i40e_aq_desc desc;
2823 struct i40e_aq_get_set_hmc_resource_profile *resp =
2824 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2825 enum i40e_status_code status;
2827 i40e_fill_default_direct_cmd_desc(&desc,
2828 i40e_aqc_opc_query_hmc_resource_profile);
2829 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2831 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
2832 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
2833 *pe_vf_enabled_count = resp->pe_vf_enabled &
2834 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
2840 * i40e_aq_set_hmc_resource_profile
2841 * @hw: pointer to the hw struct
2842 * @profile: type of profile the HMC is to be set as
2843 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2844 * @cmd_details: pointer to command details structure or NULL
2846 * set the HMC profile of the device.
2848 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2849 enum i40e_aq_hmc_profile profile,
2850 u8 pe_vf_enabled_count,
2851 struct i40e_asq_cmd_details *cmd_details)
2853 struct i40e_aq_desc desc;
2854 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2855 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2856 enum i40e_status_code status;
2858 i40e_fill_default_direct_cmd_desc(&desc,
2859 i40e_aqc_opc_set_hmc_resource_profile);
2861 cmd->pm_profile = (u8)profile;
2862 cmd->pe_vf_enabled = pe_vf_enabled_count;
2864 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2870 * i40e_aq_request_resource
2871 * @hw: pointer to the hw struct
2872 * @resource: resource id
2873 * @access: access type
2874 * @sdp_number: resource number
2875 * @timeout: the maximum time in ms that the driver may hold the resource
2876 * @cmd_details: pointer to command details structure or NULL
2878 * requests common resource using the admin queue commands
2880 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
2881 enum i40e_aq_resources_ids resource,
2882 enum i40e_aq_resource_access_type access,
2883 u8 sdp_number, u64 *timeout,
2884 struct i40e_asq_cmd_details *cmd_details)
2886 struct i40e_aq_desc desc;
2887 struct i40e_aqc_request_resource *cmd_resp =
2888 (struct i40e_aqc_request_resource *)&desc.params.raw;
2889 enum i40e_status_code status;
2891 DEBUGFUNC("i40e_aq_request_resource");
2893 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2895 cmd_resp->resource_id = CPU_TO_LE16(resource);
2896 cmd_resp->access_type = CPU_TO_LE16(access);
2897 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
2899 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2900 /* The completion specifies the maximum time in ms that the driver
2901 * may hold the resource in the Timeout field.
2902 * If the resource is held by someone else, the command completes with
2903 * busy return value and the timeout field indicates the maximum time
2904 * the current owner of the resource has to free it.
2906 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2907 *timeout = LE32_TO_CPU(cmd_resp->timeout);
2913 * i40e_aq_release_resource
2914 * @hw: pointer to the hw struct
2915 * @resource: resource id
2916 * @sdp_number: resource number
2917 * @cmd_details: pointer to command details structure or NULL
2919 * release common resource using the admin queue commands
2921 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
2922 enum i40e_aq_resources_ids resource,
2924 struct i40e_asq_cmd_details *cmd_details)
2926 struct i40e_aq_desc desc;
2927 struct i40e_aqc_request_resource *cmd =
2928 (struct i40e_aqc_request_resource *)&desc.params.raw;
2929 enum i40e_status_code status;
2931 DEBUGFUNC("i40e_aq_release_resource");
2933 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2935 cmd->resource_id = CPU_TO_LE16(resource);
2936 cmd->resource_number = CPU_TO_LE32(sdp_number);
2938 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2945 * @hw: pointer to the hw struct
2946 * @module_pointer: module pointer location in words from the NVM beginning
2947 * @offset: byte offset from the module beginning
2948 * @length: length of the section to be read (in bytes from the offset)
2949 * @data: command buffer (size [bytes] = length)
2950 * @last_command: tells if this is the last command in a series
2951 * @cmd_details: pointer to command details structure or NULL
2953 * Read the NVM using the admin queue commands
2955 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2956 u32 offset, u16 length, void *data,
2958 struct i40e_asq_cmd_details *cmd_details)
2960 struct i40e_aq_desc desc;
2961 struct i40e_aqc_nvm_update *cmd =
2962 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2963 enum i40e_status_code status;
2965 DEBUGFUNC("i40e_aq_read_nvm");
2967 /* In offset the highest byte must be zeroed. */
2968 if (offset & 0xFF000000) {
2969 status = I40E_ERR_PARAM;
2970 goto i40e_aq_read_nvm_exit;
2973 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2975 /* If this is the last command in a series, set the proper flag. */
2977 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2978 cmd->module_pointer = module_pointer;
2979 cmd->offset = CPU_TO_LE32(offset);
2980 cmd->length = CPU_TO_LE16(length);
2982 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2983 if (length > I40E_AQ_LARGE_BUF)
2984 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2986 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2988 i40e_aq_read_nvm_exit:
2993 * i40e_aq_read_nvm_config - read an nvm config block
2994 * @hw: pointer to the hw struct
2995 * @cmd_flags: NVM access admin command bits
2996 * @field_id: field or feature id
2997 * @data: buffer for result
2998 * @buf_size: buffer size
2999 * @element_count: pointer to count of elements read by FW
3000 * @cmd_details: pointer to command details structure or NULL
3002 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3003 u8 cmd_flags, u32 field_id, void *data,
3004 u16 buf_size, u16 *element_count,
3005 struct i40e_asq_cmd_details *cmd_details)
3007 struct i40e_aq_desc desc;
3008 struct i40e_aqc_nvm_config_read *cmd =
3009 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3010 enum i40e_status_code status;
3012 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3013 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3014 if (buf_size > I40E_AQ_LARGE_BUF)
3015 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3017 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3018 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3019 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3020 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3022 cmd->element_id_msw = 0;
3024 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3026 if (!status && element_count)
3027 *element_count = LE16_TO_CPU(cmd->element_count);
3033 * i40e_aq_write_nvm_config - write an nvm config block
3034 * @hw: pointer to the hw struct
3035 * @cmd_flags: NVM access admin command bits
3036 * @data: buffer for result
3037 * @buf_size: buffer size
3038 * @element_count: count of elements to be written
3039 * @cmd_details: pointer to command details structure or NULL
3041 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3042 u8 cmd_flags, void *data, u16 buf_size,
3044 struct i40e_asq_cmd_details *cmd_details)
3046 struct i40e_aq_desc desc;
3047 struct i40e_aqc_nvm_config_write *cmd =
3048 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3049 enum i40e_status_code status;
3051 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3052 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3053 if (buf_size > I40E_AQ_LARGE_BUF)
3054 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3056 cmd->element_count = CPU_TO_LE16(element_count);
3057 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3058 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3064 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3065 * @hw: pointer to the hw struct
3066 * @cmd_details: pointer to command details structure or NULL
3068 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3069 void *buff, u16 buff_size,
3070 struct i40e_asq_cmd_details *cmd_details)
3072 struct i40e_aq_desc desc;
3073 enum i40e_status_code status;
3075 UNREFERENCED_2PARAMETER(buff, buff_size);
3077 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3078 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3079 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3080 status = I40E_ERR_NOT_IMPLEMENTED;
3087 * @hw: pointer to the hw struct
3088 * @module_pointer: module pointer location in words from the NVM beginning
3089 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3090 * @length: length of the section to be erased (expressed in 4 KB)
3091 * @last_command: tells if this is the last command in a series
3092 * @cmd_details: pointer to command details structure or NULL
3094 * Erase the NVM sector using the admin queue commands
3096 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3097 u32 offset, u16 length, bool last_command,
3098 struct i40e_asq_cmd_details *cmd_details)
3100 struct i40e_aq_desc desc;
3101 struct i40e_aqc_nvm_update *cmd =
3102 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3103 enum i40e_status_code status;
3105 DEBUGFUNC("i40e_aq_erase_nvm");
3107 /* In offset the highest byte must be zeroed. */
3108 if (offset & 0xFF000000) {
3109 status = I40E_ERR_PARAM;
3110 goto i40e_aq_erase_nvm_exit;
3113 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3115 /* If this is the last command in a series, set the proper flag. */
3117 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3118 cmd->module_pointer = module_pointer;
3119 cmd->offset = CPU_TO_LE32(offset);
3120 cmd->length = CPU_TO_LE16(length);
3122 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3124 i40e_aq_erase_nvm_exit:
3128 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
3129 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
3130 #define I40E_DEV_FUNC_CAP_NPAR 0x03
3131 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
3132 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
3133 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
3134 #define I40E_DEV_FUNC_CAP_VF 0x13
3135 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
3136 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
3137 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
3138 #define I40E_DEV_FUNC_CAP_VSI 0x17
3139 #define I40E_DEV_FUNC_CAP_DCB 0x18
3140 #define I40E_DEV_FUNC_CAP_FCOE 0x21
3141 #define I40E_DEV_FUNC_CAP_ISCSI 0x22
3142 #define I40E_DEV_FUNC_CAP_RSS 0x40
3143 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
3144 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
3145 #define I40E_DEV_FUNC_CAP_MSIX 0x43
3146 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
3147 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
3148 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
3149 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
3150 #define I40E_DEV_FUNC_CAP_CEM 0xF2
3151 #define I40E_DEV_FUNC_CAP_IWARP 0x51
3152 #define I40E_DEV_FUNC_CAP_LED 0x61
3153 #define I40E_DEV_FUNC_CAP_SDP 0x62
3154 #define I40E_DEV_FUNC_CAP_MDIO 0x63
3157 * i40e_parse_discover_capabilities
3158 * @hw: pointer to the hw struct
3159 * @buff: pointer to a buffer containing device/function capability records
3160 * @cap_count: number of capability records in the list
3161 * @list_type_opc: type of capabilities list to parse
3163 * Parse the device/function capabilities list.
3165 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3167 enum i40e_admin_queue_opc list_type_opc)
3169 struct i40e_aqc_list_capabilities_element_resp *cap;
3170 u32 valid_functions, num_functions;
3171 u32 number, logical_id, phys_id;
3172 struct i40e_hw_capabilities *p;
3176 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3178 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3179 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3180 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3181 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3185 for (i = 0; i < cap_count; i++, cap++) {
3186 id = LE16_TO_CPU(cap->id);
3187 number = LE32_TO_CPU(cap->number);
3188 logical_id = LE32_TO_CPU(cap->logical_id);
3189 phys_id = LE32_TO_CPU(cap->phys_id);
3192 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
3193 p->switch_mode = number;
3195 case I40E_DEV_FUNC_CAP_MGMT_MODE:
3196 p->management_mode = number;
3198 case I40E_DEV_FUNC_CAP_NPAR:
3199 p->npar_enable = number;
3201 case I40E_DEV_FUNC_CAP_OS2BMC:
3204 case I40E_DEV_FUNC_CAP_VALID_FUNC:
3205 p->valid_functions = number;
3207 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
3209 p->sr_iov_1_1 = true;
3211 case I40E_DEV_FUNC_CAP_VF:
3212 p->num_vfs = number;
3213 p->vf_base_id = logical_id;
3215 case I40E_DEV_FUNC_CAP_VMDQ:
3219 case I40E_DEV_FUNC_CAP_802_1_QBG:
3221 p->evb_802_1_qbg = true;
3223 case I40E_DEV_FUNC_CAP_802_1_QBH:
3225 p->evb_802_1_qbh = true;
3227 case I40E_DEV_FUNC_CAP_VSI:
3228 p->num_vsis = number;
3230 case I40E_DEV_FUNC_CAP_DCB:
3233 p->enabled_tcmap = logical_id;
3237 case I40E_DEV_FUNC_CAP_FCOE:
3241 case I40E_DEV_FUNC_CAP_ISCSI:
3245 case I40E_DEV_FUNC_CAP_RSS:
3247 p->rss_table_size = number;
3248 p->rss_table_entry_width = logical_id;
3250 case I40E_DEV_FUNC_CAP_RX_QUEUES:
3251 p->num_rx_qp = number;
3252 p->base_queue = phys_id;
3254 case I40E_DEV_FUNC_CAP_TX_QUEUES:
3255 p->num_tx_qp = number;
3256 p->base_queue = phys_id;
3258 case I40E_DEV_FUNC_CAP_MSIX:
3259 p->num_msix_vectors = number;
3261 case I40E_DEV_FUNC_CAP_MSIX_VF:
3262 p->num_msix_vectors_vf = number;
3264 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
3266 p->mfp_mode_1 = true;
3268 case I40E_DEV_FUNC_CAP_CEM:
3272 case I40E_DEV_FUNC_CAP_IWARP:
3276 case I40E_DEV_FUNC_CAP_LED:
3277 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3278 p->led[phys_id] = true;
3280 case I40E_DEV_FUNC_CAP_SDP:
3281 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3282 p->sdp[phys_id] = true;
3284 case I40E_DEV_FUNC_CAP_MDIO:
3286 p->mdio_port_num = phys_id;
3287 p->mdio_port_mode = logical_id;
3290 case I40E_DEV_FUNC_CAP_IEEE_1588:
3292 p->ieee_1588 = true;
3294 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
3296 p->fd_filters_guaranteed = number;
3297 p->fd_filters_best_effort = logical_id;
3304 #ifdef I40E_FCOE_ENA
3305 /* Software override ensuring FCoE is disabled if npar or mfp
3306 * mode because it is not supported in these modes.
3308 if (p->npar_enable || p->mfp_mode_1)
3311 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3315 /* count the enabled ports (aka the "not disabled" ports) */
3317 for (i = 0; i < 4; i++) {
3318 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3321 /* use AQ read to get the physical register offset instead
3322 * of the port relative offset
3324 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3325 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3329 valid_functions = p->valid_functions;
3331 while (valid_functions) {
3332 if (valid_functions & 1)
3334 valid_functions >>= 1;
3337 /* partition id is 1-based, and functions are evenly spread
3338 * across the ports as partitions
3340 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3341 hw->num_partitions = num_functions / hw->num_ports;
3343 /* additional HW specific goodies that might
3344 * someday be HW version specific
3346 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3350 * i40e_aq_discover_capabilities
3351 * @hw: pointer to the hw struct
3352 * @buff: a virtual buffer to hold the capabilities
3353 * @buff_size: Size of the virtual buffer
3354 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3355 * @list_type_opc: capabilities type to discover - pass in the command opcode
3356 * @cmd_details: pointer to command details structure or NULL
3358 * Get the device capabilities descriptions from the firmware
3360 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3361 void *buff, u16 buff_size, u16 *data_size,
3362 enum i40e_admin_queue_opc list_type_opc,
3363 struct i40e_asq_cmd_details *cmd_details)
3365 struct i40e_aqc_list_capabilites *cmd;
3366 struct i40e_aq_desc desc;
3367 enum i40e_status_code status = I40E_SUCCESS;
3369 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3371 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3372 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3373 status = I40E_ERR_PARAM;
3377 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3379 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3380 if (buff_size > I40E_AQ_LARGE_BUF)
3381 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3383 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3384 *data_size = LE16_TO_CPU(desc.datalen);
3389 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3397 * i40e_aq_update_nvm
3398 * @hw: pointer to the hw struct
3399 * @module_pointer: module pointer location in words from the NVM beginning
3400 * @offset: byte offset from the module beginning
3401 * @length: length of the section to be written (in bytes from the offset)
3402 * @data: command buffer (size [bytes] = length)
3403 * @last_command: tells if this is the last command in a series
3404 * @cmd_details: pointer to command details structure or NULL
3406 * Update the NVM using the admin queue commands
3408 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3409 u32 offset, u16 length, void *data,
3411 struct i40e_asq_cmd_details *cmd_details)
3413 struct i40e_aq_desc desc;
3414 struct i40e_aqc_nvm_update *cmd =
3415 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3416 enum i40e_status_code status;
3418 DEBUGFUNC("i40e_aq_update_nvm");
3420 /* In offset the highest byte must be zeroed. */
3421 if (offset & 0xFF000000) {
3422 status = I40E_ERR_PARAM;
3423 goto i40e_aq_update_nvm_exit;
3426 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3428 /* If this is the last command in a series, set the proper flag. */
3430 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3431 cmd->module_pointer = module_pointer;
3432 cmd->offset = CPU_TO_LE32(offset);
3433 cmd->length = CPU_TO_LE16(length);
3435 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3436 if (length > I40E_AQ_LARGE_BUF)
3437 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3439 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3441 i40e_aq_update_nvm_exit:
3446 * i40e_aq_get_lldp_mib
3447 * @hw: pointer to the hw struct
3448 * @bridge_type: type of bridge requested
3449 * @mib_type: Local, Remote or both Local and Remote MIBs
3450 * @buff: pointer to a user supplied buffer to store the MIB block
3451 * @buff_size: size of the buffer (in bytes)
3452 * @local_len : length of the returned Local LLDP MIB
3453 * @remote_len: length of the returned Remote LLDP MIB
3454 * @cmd_details: pointer to command details structure or NULL
3456 * Requests the complete LLDP MIB (entire packet).
3458 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3459 u8 mib_type, void *buff, u16 buff_size,
3460 u16 *local_len, u16 *remote_len,
3461 struct i40e_asq_cmd_details *cmd_details)
3463 struct i40e_aq_desc desc;
3464 struct i40e_aqc_lldp_get_mib *cmd =
3465 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3466 struct i40e_aqc_lldp_get_mib *resp =
3467 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3468 enum i40e_status_code status;
3470 if (buff_size == 0 || !buff)
3471 return I40E_ERR_PARAM;
3473 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3474 /* Indirect Command */
3475 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3477 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3478 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3479 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3481 desc.datalen = CPU_TO_LE16(buff_size);
3483 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3484 if (buff_size > I40E_AQ_LARGE_BUF)
3485 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3487 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3489 if (local_len != NULL)
3490 *local_len = LE16_TO_CPU(resp->local_len);
3491 if (remote_len != NULL)
3492 *remote_len = LE16_TO_CPU(resp->remote_len);
3499 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3500 * @hw: pointer to the hw struct
3501 * @mib_type: Local, Remote or both Local and Remote MIBs
3502 * @buff: pointer to a user supplied buffer to store the MIB block
3503 * @buff_size: size of the buffer (in bytes)
3504 * @cmd_details: pointer to command details structure or NULL
3508 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3509 u8 mib_type, void *buff, u16 buff_size,
3510 struct i40e_asq_cmd_details *cmd_details)
3512 struct i40e_aq_desc desc;
3513 struct i40e_aqc_lldp_set_local_mib *cmd =
3514 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3515 enum i40e_status_code status;
3517 if (buff_size == 0 || !buff)
3518 return I40E_ERR_PARAM;
3520 i40e_fill_default_direct_cmd_desc(&desc,
3521 i40e_aqc_opc_lldp_set_local_mib);
3522 /* Indirect Command */
3523 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3524 if (buff_size > I40E_AQ_LARGE_BUF)
3525 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3526 desc.datalen = CPU_TO_LE16(buff_size);
3528 cmd->type = mib_type;
3529 cmd->length = CPU_TO_LE16(buff_size);
3530 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3531 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3533 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3538 * i40e_aq_cfg_lldp_mib_change_event
3539 * @hw: pointer to the hw struct
3540 * @enable_update: Enable or Disable event posting
3541 * @cmd_details: pointer to command details structure or NULL
3543 * Enable or Disable posting of an event on ARQ when LLDP MIB
3544 * associated with the interface changes
3546 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3548 struct i40e_asq_cmd_details *cmd_details)
3550 struct i40e_aq_desc desc;
3551 struct i40e_aqc_lldp_update_mib *cmd =
3552 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3553 enum i40e_status_code status;
3555 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3558 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3560 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3566 * i40e_aq_add_lldp_tlv
3567 * @hw: pointer to the hw struct
3568 * @bridge_type: type of bridge
3569 * @buff: buffer with TLV to add
3570 * @buff_size: length of the buffer
3571 * @tlv_len: length of the TLV to be added
3572 * @mib_len: length of the LLDP MIB returned in response
3573 * @cmd_details: pointer to command details structure or NULL
3575 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3576 * it is responsibility of the caller to make sure that the TLV is not
3577 * already present in the LLDPDU.
3578 * In return firmware will write the complete LLDP MIB with the newly
3579 * added TLV in the response buffer.
3581 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3582 void *buff, u16 buff_size, u16 tlv_len,
3584 struct i40e_asq_cmd_details *cmd_details)
3586 struct i40e_aq_desc desc;
3587 struct i40e_aqc_lldp_add_tlv *cmd =
3588 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3589 enum i40e_status_code status;
3591 if (buff_size == 0 || !buff || tlv_len == 0)
3592 return I40E_ERR_PARAM;
3594 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3596 /* Indirect Command */
3597 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3598 if (buff_size > I40E_AQ_LARGE_BUF)
3599 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3600 desc.datalen = CPU_TO_LE16(buff_size);
3602 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3603 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3604 cmd->len = CPU_TO_LE16(tlv_len);
3606 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3608 if (mib_len != NULL)
3609 *mib_len = LE16_TO_CPU(desc.datalen);
3616 * i40e_aq_update_lldp_tlv
3617 * @hw: pointer to the hw struct
3618 * @bridge_type: type of bridge
3619 * @buff: buffer with TLV to update
3620 * @buff_size: size of the buffer holding original and updated TLVs
3621 * @old_len: Length of the Original TLV
3622 * @new_len: Length of the Updated TLV
3623 * @offset: offset of the updated TLV in the buff
3624 * @mib_len: length of the returned LLDP MIB
3625 * @cmd_details: pointer to command details structure or NULL
3627 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3628 * Firmware will place the complete LLDP MIB in response buffer with the
3631 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3632 u8 bridge_type, void *buff, u16 buff_size,
3633 u16 old_len, u16 new_len, u16 offset,
3635 struct i40e_asq_cmd_details *cmd_details)
3637 struct i40e_aq_desc desc;
3638 struct i40e_aqc_lldp_update_tlv *cmd =
3639 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3640 enum i40e_status_code status;
3642 if (buff_size == 0 || !buff || offset == 0 ||
3643 old_len == 0 || new_len == 0)
3644 return I40E_ERR_PARAM;
3646 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3648 /* Indirect Command */
3649 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3650 if (buff_size > I40E_AQ_LARGE_BUF)
3651 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3652 desc.datalen = CPU_TO_LE16(buff_size);
3654 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3655 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3656 cmd->old_len = CPU_TO_LE16(old_len);
3657 cmd->new_offset = CPU_TO_LE16(offset);
3658 cmd->new_len = CPU_TO_LE16(new_len);
3660 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3662 if (mib_len != NULL)
3663 *mib_len = LE16_TO_CPU(desc.datalen);
3670 * i40e_aq_delete_lldp_tlv
3671 * @hw: pointer to the hw struct
3672 * @bridge_type: type of bridge
3673 * @buff: pointer to a user supplied buffer that has the TLV
3674 * @buff_size: length of the buffer
3675 * @tlv_len: length of the TLV to be deleted
3676 * @mib_len: length of the returned LLDP MIB
3677 * @cmd_details: pointer to command details structure or NULL
3679 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
3680 * The firmware places the entire LLDP MIB in the response buffer.
3682 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
3683 u8 bridge_type, void *buff, u16 buff_size,
3684 u16 tlv_len, u16 *mib_len,
3685 struct i40e_asq_cmd_details *cmd_details)
3687 struct i40e_aq_desc desc;
3688 struct i40e_aqc_lldp_add_tlv *cmd =
3689 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3690 enum i40e_status_code status;
3692 if (buff_size == 0 || !buff)
3693 return I40E_ERR_PARAM;
3695 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
3697 /* Indirect Command */
3698 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3699 if (buff_size > I40E_AQ_LARGE_BUF)
3700 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3701 desc.datalen = CPU_TO_LE16(buff_size);
3702 cmd->len = CPU_TO_LE16(tlv_len);
3703 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3704 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3706 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3708 if (mib_len != NULL)
3709 *mib_len = LE16_TO_CPU(desc.datalen);
3717 * @hw: pointer to the hw struct
3718 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3719 * @cmd_details: pointer to command details structure or NULL
3721 * Stop or Shutdown the embedded LLDP Agent
3723 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3724 struct i40e_asq_cmd_details *cmd_details)
3726 struct i40e_aq_desc desc;
3727 struct i40e_aqc_lldp_stop *cmd =
3728 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3729 enum i40e_status_code status;
3731 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3734 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3736 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3742 * i40e_aq_start_lldp
3743 * @hw: pointer to the hw struct
3744 * @cmd_details: pointer to command details structure or NULL
3746 * Start the embedded LLDP Agent on all ports.
3748 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
3749 struct i40e_asq_cmd_details *cmd_details)
3751 struct i40e_aq_desc desc;
3752 struct i40e_aqc_lldp_start *cmd =
3753 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3754 enum i40e_status_code status;
3756 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3758 cmd->command = I40E_AQ_LLDP_AGENT_START;
3760 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3766 * i40e_aq_get_cee_dcb_config
3767 * @hw: pointer to the hw struct
3768 * @buff: response buffer that stores CEE operational configuration
3769 * @buff_size: size of the buffer passed
3770 * @cmd_details: pointer to command details structure or NULL
3772 * Get CEE DCBX mode operational configuration from firmware
3774 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3775 void *buff, u16 buff_size,
3776 struct i40e_asq_cmd_details *cmd_details)
3778 struct i40e_aq_desc desc;
3779 enum i40e_status_code status;
3781 if (buff_size == 0 || !buff)
3782 return I40E_ERR_PARAM;
3784 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3786 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3787 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3794 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
3795 * @hw: pointer to the hw struct
3796 * @start_agent: True if DCBx Agent needs to be Started
3797 * False if DCBx Agent needs to be Stopped
3798 * @cmd_details: pointer to command details structure or NULL
3800 * Start/Stop the embedded dcbx Agent
3802 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
3804 struct i40e_asq_cmd_details *cmd_details)
3806 struct i40e_aq_desc desc;
3807 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
3808 (struct i40e_aqc_lldp_stop_start_specific_agent *)
3810 enum i40e_status_code status;
3812 i40e_fill_default_direct_cmd_desc(&desc,
3813 i40e_aqc_opc_lldp_stop_start_spec_agent);
3816 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
3818 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3824 * i40e_aq_add_udp_tunnel
3825 * @hw: pointer to the hw struct
3826 * @udp_port: the UDP port to add
3827 * @header_len: length of the tunneling header length in DWords
3828 * @protocol_index: protocol index type
3829 * @filter_index: pointer to filter index
3830 * @cmd_details: pointer to command details structure or NULL
3832 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3833 u16 udp_port, u8 protocol_index,
3835 struct i40e_asq_cmd_details *cmd_details)
3837 struct i40e_aq_desc desc;
3838 struct i40e_aqc_add_udp_tunnel *cmd =
3839 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3840 struct i40e_aqc_del_udp_tunnel_completion *resp =
3841 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3842 enum i40e_status_code status;
3844 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3846 cmd->udp_port = CPU_TO_LE16(udp_port);
3847 cmd->protocol_type = protocol_index;
3849 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3851 if (!status && filter_index)
3852 *filter_index = resp->index;
3858 * i40e_aq_del_udp_tunnel
3859 * @hw: pointer to the hw struct
3860 * @index: filter index
3861 * @cmd_details: pointer to command details structure or NULL
3863 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3864 struct i40e_asq_cmd_details *cmd_details)
3866 struct i40e_aq_desc desc;
3867 struct i40e_aqc_remove_udp_tunnel *cmd =
3868 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3869 enum i40e_status_code status;
3871 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3875 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3881 * i40e_aq_get_switch_resource_alloc (0x0204)
3882 * @hw: pointer to the hw struct
3883 * @num_entries: pointer to u8 to store the number of resource entries returned
3884 * @buf: pointer to a user supplied buffer. This buffer must be large enough
3885 * to store the resource information for all resource types. Each
3886 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
3887 * @count: size, in bytes, of the buffer provided
3888 * @cmd_details: pointer to command details structure or NULL
3890 * Query the resources allocated to a function.
3892 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
3894 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
3896 struct i40e_asq_cmd_details *cmd_details)
3898 struct i40e_aq_desc desc;
3899 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
3900 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
3901 enum i40e_status_code status;
3902 u16 length = count * sizeof(*buf);
3904 i40e_fill_default_direct_cmd_desc(&desc,
3905 i40e_aqc_opc_get_switch_resource_alloc);
3907 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3908 if (length > I40E_AQ_LARGE_BUF)
3909 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3911 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
3913 if (!status && num_entries)
3914 *num_entries = cmd_resp->num_entries;
3920 * i40e_aq_delete_element - Delete switch element
3921 * @hw: pointer to the hw struct
3922 * @seid: the SEID to delete from the switch
3923 * @cmd_details: pointer to command details structure or NULL
3925 * This deletes a switch element from the switch.
3927 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3928 struct i40e_asq_cmd_details *cmd_details)
3930 struct i40e_aq_desc desc;
3931 struct i40e_aqc_switch_seid *cmd =
3932 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3933 enum i40e_status_code status;
3936 return I40E_ERR_PARAM;
3938 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3940 cmd->seid = CPU_TO_LE16(seid);
3942 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3948 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
3949 * @hw: pointer to the hw struct
3950 * @flags: component flags
3951 * @mac_seid: uplink seid (MAC SEID)
3952 * @vsi_seid: connected vsi seid
3953 * @ret_seid: seid of create pv component
3955 * This instantiates an i40e port virtualizer with specified flags.
3956 * Depending on specified flags the port virtualizer can act as a
3957 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
3959 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
3960 u16 mac_seid, u16 vsi_seid,
3963 struct i40e_aq_desc desc;
3964 struct i40e_aqc_add_update_pv *cmd =
3965 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
3966 struct i40e_aqc_add_update_pv_completion *resp =
3967 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
3968 enum i40e_status_code status;
3971 return I40E_ERR_PARAM;
3973 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
3974 cmd->command_flags = CPU_TO_LE16(flags);
3975 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
3976 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
3978 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
3979 if (!status && ret_seid)
3980 *ret_seid = LE16_TO_CPU(resp->pv_seid);
3986 * i40e_aq_add_tag - Add an S/E-tag
3987 * @hw: pointer to the hw struct
3988 * @direct_to_queue: should s-tag direct flow to a specific queue
3989 * @vsi_seid: VSI SEID to use this tag
3990 * @tag: value of the tag
3991 * @queue_num: queue number, only valid is direct_to_queue is true
3992 * @tags_used: return value, number of tags in use by this PF
3993 * @tags_free: return value, number of unallocated tags
3994 * @cmd_details: pointer to command details structure or NULL
3996 * This associates an S- or E-tag to a VSI in the switch complex. It returns
3997 * the number of tags allocated by the PF, and the number of unallocated
4000 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4001 u16 vsi_seid, u16 tag, u16 queue_num,
4002 u16 *tags_used, u16 *tags_free,
4003 struct i40e_asq_cmd_details *cmd_details)
4005 struct i40e_aq_desc desc;
4006 struct i40e_aqc_add_tag *cmd =
4007 (struct i40e_aqc_add_tag *)&desc.params.raw;
4008 struct i40e_aqc_add_remove_tag_completion *resp =
4009 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4010 enum i40e_status_code status;
4013 return I40E_ERR_PARAM;
4015 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4017 cmd->seid = CPU_TO_LE16(vsi_seid);
4018 cmd->tag = CPU_TO_LE16(tag);
4019 if (direct_to_queue) {
4020 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4021 cmd->queue_number = CPU_TO_LE16(queue_num);
4024 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4027 if (tags_used != NULL)
4028 *tags_used = LE16_TO_CPU(resp->tags_used);
4029 if (tags_free != NULL)
4030 *tags_free = LE16_TO_CPU(resp->tags_free);
4037 * i40e_aq_remove_tag - Remove an S- or E-tag
4038 * @hw: pointer to the hw struct
4039 * @vsi_seid: VSI SEID this tag is associated with
4040 * @tag: value of the S-tag to delete
4041 * @tags_used: return value, number of tags in use by this PF
4042 * @tags_free: return value, number of unallocated tags
4043 * @cmd_details: pointer to command details structure or NULL
4045 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4046 * the number of tags allocated by the PF, and the number of unallocated
4049 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4050 u16 tag, u16 *tags_used, u16 *tags_free,
4051 struct i40e_asq_cmd_details *cmd_details)
4053 struct i40e_aq_desc desc;
4054 struct i40e_aqc_remove_tag *cmd =
4055 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4056 struct i40e_aqc_add_remove_tag_completion *resp =
4057 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4058 enum i40e_status_code status;
4061 return I40E_ERR_PARAM;
4063 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4065 cmd->seid = CPU_TO_LE16(vsi_seid);
4066 cmd->tag = CPU_TO_LE16(tag);
4068 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4071 if (tags_used != NULL)
4072 *tags_used = LE16_TO_CPU(resp->tags_used);
4073 if (tags_free != NULL)
4074 *tags_free = LE16_TO_CPU(resp->tags_free);
4081 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4082 * @hw: pointer to the hw struct
4083 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4084 * @etag: value of E-tag to add
4085 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4086 * @buf: address of indirect buffer
4087 * @tags_used: return value, number of E-tags in use by this port
4088 * @tags_free: return value, number of unallocated M-tags
4089 * @cmd_details: pointer to command details structure or NULL
4091 * This associates a multicast E-tag to a port virtualizer. It will return
4092 * the number of tags allocated by the PF, and the number of unallocated
4095 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4096 * num_tags_in_buf long.
4098 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4099 u16 etag, u8 num_tags_in_buf, void *buf,
4100 u16 *tags_used, u16 *tags_free,
4101 struct i40e_asq_cmd_details *cmd_details)
4103 struct i40e_aq_desc desc;
4104 struct i40e_aqc_add_remove_mcast_etag *cmd =
4105 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4106 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4107 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4108 enum i40e_status_code status;
4109 u16 length = sizeof(u16) * num_tags_in_buf;
4111 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4112 return I40E_ERR_PARAM;
4114 i40e_fill_default_direct_cmd_desc(&desc,
4115 i40e_aqc_opc_add_multicast_etag);
4117 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4118 cmd->etag = CPU_TO_LE16(etag);
4119 cmd->num_unicast_etags = num_tags_in_buf;
4121 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4122 if (length > I40E_AQ_LARGE_BUF)
4123 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4125 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4128 if (tags_used != NULL)
4129 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4130 if (tags_free != NULL)
4131 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4138 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4139 * @hw: pointer to the hw struct
4140 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4141 * @etag: value of the E-tag to remove
4142 * @tags_used: return value, number of tags in use by this port
4143 * @tags_free: return value, number of unallocated tags
4144 * @cmd_details: pointer to command details structure or NULL
4146 * This deletes an E-tag from the port virtualizer. It will return
4147 * the number of tags allocated by the port, and the number of unallocated
4150 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4151 u16 etag, u16 *tags_used, u16 *tags_free,
4152 struct i40e_asq_cmd_details *cmd_details)
4154 struct i40e_aq_desc desc;
4155 struct i40e_aqc_add_remove_mcast_etag *cmd =
4156 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4157 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4158 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4159 enum i40e_status_code status;
4163 return I40E_ERR_PARAM;
4165 i40e_fill_default_direct_cmd_desc(&desc,
4166 i40e_aqc_opc_remove_multicast_etag);
4168 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4169 cmd->etag = CPU_TO_LE16(etag);
4171 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4174 if (tags_used != NULL)
4175 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4176 if (tags_free != NULL)
4177 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4184 * i40e_aq_update_tag - Update an S/E-tag
4185 * @hw: pointer to the hw struct
4186 * @vsi_seid: VSI SEID using this S-tag
4187 * @old_tag: old tag value
4188 * @new_tag: new tag value
4189 * @tags_used: return value, number of tags in use by this PF
4190 * @tags_free: return value, number of unallocated tags
4191 * @cmd_details: pointer to command details structure or NULL
4193 * This updates the value of the tag currently attached to this VSI
4194 * in the switch complex. It will return the number of tags allocated
4195 * by the PF, and the number of unallocated tags available.
4197 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4198 u16 old_tag, u16 new_tag, u16 *tags_used,
4200 struct i40e_asq_cmd_details *cmd_details)
4202 struct i40e_aq_desc desc;
4203 struct i40e_aqc_update_tag *cmd =
4204 (struct i40e_aqc_update_tag *)&desc.params.raw;
4205 struct i40e_aqc_update_tag_completion *resp =
4206 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4207 enum i40e_status_code status;
4210 return I40E_ERR_PARAM;
4212 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4214 cmd->seid = CPU_TO_LE16(vsi_seid);
4215 cmd->old_tag = CPU_TO_LE16(old_tag);
4216 cmd->new_tag = CPU_TO_LE16(new_tag);
4218 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4221 if (tags_used != NULL)
4222 *tags_used = LE16_TO_CPU(resp->tags_used);
4223 if (tags_free != NULL)
4224 *tags_free = LE16_TO_CPU(resp->tags_free);
4231 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4232 * @hw: pointer to the hw struct
4233 * @tcmap: TC map for request/release any ignore PFC condition
4234 * @request: request or release ignore PFC condition
4235 * @tcmap_ret: return TCs for which PFC is currently ignored
4236 * @cmd_details: pointer to command details structure or NULL
4238 * This sends out request/release to ignore PFC condition for a TC.
4239 * It will return the TCs for which PFC is currently ignored.
4241 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4242 bool request, u8 *tcmap_ret,
4243 struct i40e_asq_cmd_details *cmd_details)
4245 struct i40e_aq_desc desc;
4246 struct i40e_aqc_pfc_ignore *cmd_resp =
4247 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4248 enum i40e_status_code status;
4250 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4253 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4255 cmd_resp->tc_bitmap = tcmap;
4257 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4260 if (tcmap_ret != NULL)
4261 *tcmap_ret = cmd_resp->tc_bitmap;
4268 * i40e_aq_dcb_updated - DCB Updated Command
4269 * @hw: pointer to the hw struct
4270 * @cmd_details: pointer to command details structure or NULL
4272 * When LLDP is handled in PF this command is used by the PF
4273 * to notify EMP that a DCB setting is modified.
4274 * When LLDP is handled in EMP this command is used by the PF
4275 * to notify EMP whenever one of the following parameters get
4277 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4278 * - PCIRTT in PRTDCB_GENC.PCIRTT
4279 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4280 * EMP will return when the shared RPB settings have been
4281 * recomputed and modified. The retval field in the descriptor
4282 * will be set to 0 when RPB is modified.
4284 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4285 struct i40e_asq_cmd_details *cmd_details)
4287 struct i40e_aq_desc desc;
4288 enum i40e_status_code status;
4290 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4292 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4298 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4299 * @hw: pointer to the hw struct
4300 * @seid: defines the SEID of the switch for which the stats are requested
4301 * @vlan_id: the VLAN ID for which the statistics are requested
4302 * @stat_index: index of the statistics counters block assigned to this VLAN
4303 * @cmd_details: pointer to command details structure or NULL
4305 * XL710 supports 128 smonVlanStats counters.This command is used to
4306 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4309 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4310 u16 vlan_id, u16 *stat_index,
4311 struct i40e_asq_cmd_details *cmd_details)
4313 struct i40e_aq_desc desc;
4314 struct i40e_aqc_add_remove_statistics *cmd_resp =
4315 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4316 enum i40e_status_code status;
4318 if ((seid == 0) || (stat_index == NULL))
4319 return I40E_ERR_PARAM;
4321 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4323 cmd_resp->seid = CPU_TO_LE16(seid);
4324 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4326 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4328 if (!status && stat_index)
4329 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4335 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4336 * @hw: pointer to the hw struct
4337 * @seid: defines the SEID of the switch for which the stats are requested
4338 * @vlan_id: the VLAN ID for which the statistics are requested
4339 * @stat_index: index of the statistics counters block assigned to this VLAN
4340 * @cmd_details: pointer to command details structure or NULL
4342 * XL710 supports 128 smonVlanStats counters.This command is used to
4343 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4346 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4347 u16 vlan_id, u16 stat_index,
4348 struct i40e_asq_cmd_details *cmd_details)
4350 struct i40e_aq_desc desc;
4351 struct i40e_aqc_add_remove_statistics *cmd =
4352 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4353 enum i40e_status_code status;
4356 return I40E_ERR_PARAM;
4358 i40e_fill_default_direct_cmd_desc(&desc,
4359 i40e_aqc_opc_remove_statistics);
4361 cmd->seid = CPU_TO_LE16(seid);
4362 cmd->vlan = CPU_TO_LE16(vlan_id);
4363 cmd->stat_index = CPU_TO_LE16(stat_index);
4365 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4371 * i40e_aq_set_port_parameters - set physical port parameters.
4372 * @hw: pointer to the hw struct
4373 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4374 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4375 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4376 * @double_vlan: if set double VLAN is enabled
4377 * @cmd_details: pointer to command details structure or NULL
4379 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4380 u16 bad_frame_vsi, bool save_bad_pac,
4381 bool pad_short_pac, bool double_vlan,
4382 struct i40e_asq_cmd_details *cmd_details)
4384 struct i40e_aqc_set_port_parameters *cmd;
4385 enum i40e_status_code status;
4386 struct i40e_aq_desc desc;
4387 u16 command_flags = 0;
4389 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4391 i40e_fill_default_direct_cmd_desc(&desc,
4392 i40e_aqc_opc_set_port_parameters);
4394 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4396 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4398 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4400 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4401 cmd->command_flags = CPU_TO_LE16(command_flags);
4403 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4409 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4410 * @hw: pointer to the hw struct
4411 * @seid: seid for the physical port/switching component/vsi
4412 * @buff: Indirect buffer to hold data parameters and response
4413 * @buff_size: Indirect buffer size
4414 * @opcode: Tx scheduler AQ command opcode
4415 * @cmd_details: pointer to command details structure or NULL
4417 * Generic command handler for Tx scheduler AQ commands
4419 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4420 void *buff, u16 buff_size,
4421 enum i40e_admin_queue_opc opcode,
4422 struct i40e_asq_cmd_details *cmd_details)
4424 struct i40e_aq_desc desc;
4425 struct i40e_aqc_tx_sched_ind *cmd =
4426 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4427 enum i40e_status_code status;
4428 bool cmd_param_flag = false;
4431 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4432 case i40e_aqc_opc_configure_vsi_tc_bw:
4433 case i40e_aqc_opc_enable_switching_comp_ets:
4434 case i40e_aqc_opc_modify_switching_comp_ets:
4435 case i40e_aqc_opc_disable_switching_comp_ets:
4436 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4437 case i40e_aqc_opc_configure_switching_comp_bw_config:
4438 cmd_param_flag = true;
4440 case i40e_aqc_opc_query_vsi_bw_config:
4441 case i40e_aqc_opc_query_vsi_ets_sla_config:
4442 case i40e_aqc_opc_query_switching_comp_ets_config:
4443 case i40e_aqc_opc_query_port_ets_config:
4444 case i40e_aqc_opc_query_switching_comp_bw_config:
4445 cmd_param_flag = false;
4448 return I40E_ERR_PARAM;
4451 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4453 /* Indirect command */
4454 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4456 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4457 if (buff_size > I40E_AQ_LARGE_BUF)
4458 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4460 desc.datalen = CPU_TO_LE16(buff_size);
4462 cmd->vsi_seid = CPU_TO_LE16(seid);
4464 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4470 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4471 * @hw: pointer to the hw struct
4473 * @credit: BW limit credits (0 = disabled)
4474 * @max_credit: Max BW limit credits
4475 * @cmd_details: pointer to command details structure or NULL
4477 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4478 u16 seid, u16 credit, u8 max_credit,
4479 struct i40e_asq_cmd_details *cmd_details)
4481 struct i40e_aq_desc desc;
4482 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4483 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4484 enum i40e_status_code status;
4486 i40e_fill_default_direct_cmd_desc(&desc,
4487 i40e_aqc_opc_configure_vsi_bw_limit);
4489 cmd->vsi_seid = CPU_TO_LE16(seid);
4490 cmd->credit = CPU_TO_LE16(credit);
4491 cmd->max_credit = max_credit;
4493 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4499 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4500 * @hw: pointer to the hw struct
4501 * @seid: switching component seid
4502 * @credit: BW limit credits (0 = disabled)
4503 * @max_bw: Max BW limit credits
4504 * @cmd_details: pointer to command details structure or NULL
4506 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4507 u16 seid, u16 credit, u8 max_bw,
4508 struct i40e_asq_cmd_details *cmd_details)
4510 struct i40e_aq_desc desc;
4511 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4512 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4513 enum i40e_status_code status;
4515 i40e_fill_default_direct_cmd_desc(&desc,
4516 i40e_aqc_opc_configure_switching_comp_bw_limit);
4518 cmd->seid = CPU_TO_LE16(seid);
4519 cmd->credit = CPU_TO_LE16(credit);
4520 cmd->max_bw = max_bw;
4522 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4528 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4529 * @hw: pointer to the hw struct
4531 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4532 * @cmd_details: pointer to command details structure or NULL
4534 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4536 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4537 struct i40e_asq_cmd_details *cmd_details)
4539 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4540 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4545 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4546 * @hw: pointer to the hw struct
4548 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4549 * @cmd_details: pointer to command details structure or NULL
4551 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4553 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4554 struct i40e_asq_cmd_details *cmd_details)
4556 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4557 i40e_aqc_opc_configure_vsi_tc_bw,
4562 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4563 * @hw: pointer to the hw struct
4564 * @seid: seid of the switching component connected to Physical Port
4565 * @ets_data: Buffer holding ETS parameters
4566 * @cmd_details: pointer to command details structure or NULL
4568 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4570 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4571 enum i40e_admin_queue_opc opcode,
4572 struct i40e_asq_cmd_details *cmd_details)
4574 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4575 sizeof(*ets_data), opcode, cmd_details);
4579 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4580 * @hw: pointer to the hw struct
4581 * @seid: seid of the switching component
4582 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4583 * @cmd_details: pointer to command details structure or NULL
4585 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4587 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4588 struct i40e_asq_cmd_details *cmd_details)
4590 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4591 i40e_aqc_opc_configure_switching_comp_bw_config,
4596 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4597 * @hw: pointer to the hw struct
4598 * @seid: seid of the switching component
4599 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4600 * @cmd_details: pointer to command details structure or NULL
4602 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4603 struct i40e_hw *hw, u16 seid,
4604 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4605 struct i40e_asq_cmd_details *cmd_details)
4607 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4608 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4613 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4614 * @hw: pointer to the hw struct
4615 * @seid: seid of the VSI
4616 * @bw_data: Buffer to hold VSI BW configuration
4617 * @cmd_details: pointer to command details structure or NULL
4619 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4621 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4622 struct i40e_asq_cmd_details *cmd_details)
4624 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4625 i40e_aqc_opc_query_vsi_bw_config,
4630 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4631 * @hw: pointer to the hw struct
4632 * @seid: seid of the VSI
4633 * @bw_data: Buffer to hold VSI BW configuration per TC
4634 * @cmd_details: pointer to command details structure or NULL
4636 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4638 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4639 struct i40e_asq_cmd_details *cmd_details)
4641 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4642 i40e_aqc_opc_query_vsi_ets_sla_config,
4647 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4648 * @hw: pointer to the hw struct
4649 * @seid: seid of the switching component
4650 * @bw_data: Buffer to hold switching component's per TC BW config
4651 * @cmd_details: pointer to command details structure or NULL
4653 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4655 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4656 struct i40e_asq_cmd_details *cmd_details)
4658 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4659 i40e_aqc_opc_query_switching_comp_ets_config,
4664 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4665 * @hw: pointer to the hw struct
4666 * @seid: seid of the VSI or switching component connected to Physical Port
4667 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4668 * @cmd_details: pointer to command details structure or NULL
4670 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4672 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4673 struct i40e_asq_cmd_details *cmd_details)
4675 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4676 i40e_aqc_opc_query_port_ets_config,
4681 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4682 * @hw: pointer to the hw struct
4683 * @seid: seid of the switching component
4684 * @bw_data: Buffer to hold switching component's BW configuration
4685 * @cmd_details: pointer to command details structure or NULL
4687 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4689 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4690 struct i40e_asq_cmd_details *cmd_details)
4692 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4693 i40e_aqc_opc_query_switching_comp_bw_config,
4698 * i40e_validate_filter_settings
4699 * @hw: pointer to the hardware structure
4700 * @settings: Filter control settings
4702 * Check and validate the filter control settings passed.
4703 * The function checks for the valid filter/context sizes being
4704 * passed for FCoE and PE.
4706 * Returns I40E_SUCCESS if the values passed are valid and within
4707 * range else returns an error.
4709 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
4710 struct i40e_filter_control_settings *settings)
4712 u32 fcoe_cntx_size, fcoe_filt_size;
4713 u32 pe_cntx_size, pe_filt_size;
4718 /* Validate FCoE settings passed */
4719 switch (settings->fcoe_filt_num) {
4720 case I40E_HASH_FILTER_SIZE_1K:
4721 case I40E_HASH_FILTER_SIZE_2K:
4722 case I40E_HASH_FILTER_SIZE_4K:
4723 case I40E_HASH_FILTER_SIZE_8K:
4724 case I40E_HASH_FILTER_SIZE_16K:
4725 case I40E_HASH_FILTER_SIZE_32K:
4726 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4727 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4730 return I40E_ERR_PARAM;
4733 switch (settings->fcoe_cntx_num) {
4734 case I40E_DMA_CNTX_SIZE_512:
4735 case I40E_DMA_CNTX_SIZE_1K:
4736 case I40E_DMA_CNTX_SIZE_2K:
4737 case I40E_DMA_CNTX_SIZE_4K:
4738 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4739 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4742 return I40E_ERR_PARAM;
4745 /* Validate PE settings passed */
4746 switch (settings->pe_filt_num) {
4747 case I40E_HASH_FILTER_SIZE_1K:
4748 case I40E_HASH_FILTER_SIZE_2K:
4749 case I40E_HASH_FILTER_SIZE_4K:
4750 case I40E_HASH_FILTER_SIZE_8K:
4751 case I40E_HASH_FILTER_SIZE_16K:
4752 case I40E_HASH_FILTER_SIZE_32K:
4753 case I40E_HASH_FILTER_SIZE_64K:
4754 case I40E_HASH_FILTER_SIZE_128K:
4755 case I40E_HASH_FILTER_SIZE_256K:
4756 case I40E_HASH_FILTER_SIZE_512K:
4757 case I40E_HASH_FILTER_SIZE_1M:
4758 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4759 pe_filt_size <<= (u32)settings->pe_filt_num;
4762 return I40E_ERR_PARAM;
4765 switch (settings->pe_cntx_num) {
4766 case I40E_DMA_CNTX_SIZE_512:
4767 case I40E_DMA_CNTX_SIZE_1K:
4768 case I40E_DMA_CNTX_SIZE_2K:
4769 case I40E_DMA_CNTX_SIZE_4K:
4770 case I40E_DMA_CNTX_SIZE_8K:
4771 case I40E_DMA_CNTX_SIZE_16K:
4772 case I40E_DMA_CNTX_SIZE_32K:
4773 case I40E_DMA_CNTX_SIZE_64K:
4774 case I40E_DMA_CNTX_SIZE_128K:
4775 case I40E_DMA_CNTX_SIZE_256K:
4776 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4777 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4780 return I40E_ERR_PARAM;
4783 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4784 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4785 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4786 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4787 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4788 return I40E_ERR_INVALID_SIZE;
4790 return I40E_SUCCESS;
4794 * i40e_set_filter_control
4795 * @hw: pointer to the hardware structure
4796 * @settings: Filter control settings
4798 * Set the Queue Filters for PE/FCoE and enable filters required
4799 * for a single PF. It is expected that these settings are programmed
4800 * at the driver initialization time.
4802 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
4803 struct i40e_filter_control_settings *settings)
4805 enum i40e_status_code ret = I40E_SUCCESS;
4806 u32 hash_lut_size = 0;
4810 return I40E_ERR_PARAM;
4812 /* Validate the input settings */
4813 ret = i40e_validate_filter_settings(hw, settings);
4817 /* Read the PF Queue Filter control register */
4818 val = rd32(hw, I40E_PFQF_CTL_0);
4820 /* Program required PE hash buckets for the PF */
4821 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4822 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4823 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4824 /* Program required PE contexts for the PF */
4825 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4826 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4827 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4829 /* Program required FCoE hash buckets for the PF */
4830 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4831 val |= ((u32)settings->fcoe_filt_num <<
4832 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4833 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4834 /* Program required FCoE DDP contexts for the PF */
4835 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4836 val |= ((u32)settings->fcoe_cntx_num <<
4837 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4838 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4840 /* Program Hash LUT size for the PF */
4841 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4842 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4844 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4845 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4847 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4848 if (settings->enable_fdir)
4849 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4850 if (settings->enable_ethtype)
4851 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4852 if (settings->enable_macvlan)
4853 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4855 wr32(hw, I40E_PFQF_CTL_0, val);
4857 return I40E_SUCCESS;
4861 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4862 * @hw: pointer to the hw struct
4863 * @mac_addr: MAC address to use in the filter
4864 * @ethtype: Ethertype to use in the filter
4865 * @flags: Flags that needs to be applied to the filter
4866 * @vsi_seid: seid of the control VSI
4867 * @queue: VSI queue number to send the packet to
4868 * @is_add: Add control packet filter if True else remove
4869 * @stats: Structure to hold information on control filter counts
4870 * @cmd_details: pointer to command details structure or NULL
4872 * This command will Add or Remove control packet filter for a control VSI.
4873 * In return it will update the total number of perfect filter count in
4876 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4877 u8 *mac_addr, u16 ethtype, u16 flags,
4878 u16 vsi_seid, u16 queue, bool is_add,
4879 struct i40e_control_filter_stats *stats,
4880 struct i40e_asq_cmd_details *cmd_details)
4882 struct i40e_aq_desc desc;
4883 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4884 (struct i40e_aqc_add_remove_control_packet_filter *)
4886 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4887 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4889 enum i40e_status_code status;
4892 return I40E_ERR_PARAM;
4895 i40e_fill_default_direct_cmd_desc(&desc,
4896 i40e_aqc_opc_add_control_packet_filter);
4897 cmd->queue = CPU_TO_LE16(queue);
4899 i40e_fill_default_direct_cmd_desc(&desc,
4900 i40e_aqc_opc_remove_control_packet_filter);
4904 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
4905 I40E_NONDMA_TO_NONDMA);
4907 cmd->etype = CPU_TO_LE16(ethtype);
4908 cmd->flags = CPU_TO_LE16(flags);
4909 cmd->seid = CPU_TO_LE16(vsi_seid);
4911 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4913 if (!status && stats) {
4914 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
4915 stats->etype_used = LE16_TO_CPU(resp->etype_used);
4916 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
4917 stats->etype_free = LE16_TO_CPU(resp->etype_free);
4924 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4925 * @hw: pointer to the hw struct
4926 * @seid: VSI seid to add ethertype filter from
4928 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4929 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4932 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4933 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4934 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4935 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4936 enum i40e_status_code status;
4938 status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
4939 seid, 0, true, NULL,
4942 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4946 * i40e_aq_add_cloud_filters
4947 * @hw: pointer to the hardware structure
4948 * @seid: VSI seid to add cloud filters from
4949 * @filters: Buffer which contains the filters to be added
4950 * @filter_count: number of filters contained in the buffer
4952 * Set the cloud filters for a given VSI. The contents of the
4953 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4954 * in by the caller of the function.
4957 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
4959 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4962 struct i40e_aq_desc desc;
4963 struct i40e_aqc_add_remove_cloud_filters *cmd =
4964 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
4966 enum i40e_status_code status;
4968 i40e_fill_default_direct_cmd_desc(&desc,
4969 i40e_aqc_opc_add_cloud_filters);
4971 buff_len = filter_count * sizeof(*filters);
4972 desc.datalen = CPU_TO_LE16(buff_len);
4973 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4974 cmd->num_filters = filter_count;
4975 cmd->seid = CPU_TO_LE16(seid);
4977 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
4983 * i40e_aq_remove_cloud_filters
4984 * @hw: pointer to the hardware structure
4985 * @seid: VSI seid to remove cloud filters from
4986 * @filters: Buffer which contains the filters to be removed
4987 * @filter_count: number of filters contained in the buffer
4989 * Remove the cloud filters for a given VSI. The contents of the
4990 * i40e_aqc_add_remove_cloud_filters_element_data are filled
4991 * in by the caller of the function.
4994 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
4996 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
4999 struct i40e_aq_desc desc;
5000 struct i40e_aqc_add_remove_cloud_filters *cmd =
5001 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5002 enum i40e_status_code status;
5005 i40e_fill_default_direct_cmd_desc(&desc,
5006 i40e_aqc_opc_remove_cloud_filters);
5008 buff_len = filter_count * sizeof(*filters);
5009 desc.datalen = CPU_TO_LE16(buff_len);
5010 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5011 cmd->num_filters = filter_count;
5012 cmd->seid = CPU_TO_LE16(seid);
5014 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5020 * i40e_aq_alternate_write
5021 * @hw: pointer to the hardware structure
5022 * @reg_addr0: address of first dword to be read
5023 * @reg_val0: value to be written under 'reg_addr0'
5024 * @reg_addr1: address of second dword to be read
5025 * @reg_val1: value to be written under 'reg_addr1'
5027 * Write one or two dwords to alternate structure. Fields are indicated
5028 * by 'reg_addr0' and 'reg_addr1' register numbers.
5031 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5032 u32 reg_addr0, u32 reg_val0,
5033 u32 reg_addr1, u32 reg_val1)
5035 struct i40e_aq_desc desc;
5036 struct i40e_aqc_alternate_write *cmd_resp =
5037 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5038 enum i40e_status_code status;
5040 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5041 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5042 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5043 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5044 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5046 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5052 * i40e_aq_alternate_write_indirect
5053 * @hw: pointer to the hardware structure
5054 * @addr: address of a first register to be modified
5055 * @dw_count: number of alternate structure fields to write
5056 * @buffer: pointer to the command buffer
5058 * Write 'dw_count' dwords from 'buffer' to alternate structure
5059 * starting at 'addr'.
5062 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5063 u32 addr, u32 dw_count, void *buffer)
5065 struct i40e_aq_desc desc;
5066 struct i40e_aqc_alternate_ind_write *cmd_resp =
5067 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5068 enum i40e_status_code status;
5071 return I40E_ERR_PARAM;
5073 /* Indirect command */
5074 i40e_fill_default_direct_cmd_desc(&desc,
5075 i40e_aqc_opc_alternate_write_indirect);
5077 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5078 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5079 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5080 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5082 cmd_resp->address = CPU_TO_LE32(addr);
5083 cmd_resp->length = CPU_TO_LE32(dw_count);
5084 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));
5085 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
5087 status = i40e_asq_send_command(hw, &desc, buffer,
5088 I40E_LO_DWORD(4*dw_count), NULL);
5094 * i40e_aq_alternate_read
5095 * @hw: pointer to the hardware structure
5096 * @reg_addr0: address of first dword to be read
5097 * @reg_val0: pointer for data read from 'reg_addr0'
5098 * @reg_addr1: address of second dword to be read
5099 * @reg_val1: pointer for data read from 'reg_addr1'
5101 * Read one or two dwords from alternate structure. Fields are indicated
5102 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5103 * is not passed then only register at 'reg_addr0' is read.
5106 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5107 u32 reg_addr0, u32 *reg_val0,
5108 u32 reg_addr1, u32 *reg_val1)
5110 struct i40e_aq_desc desc;
5111 struct i40e_aqc_alternate_write *cmd_resp =
5112 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5113 enum i40e_status_code status;
5115 if (reg_val0 == NULL)
5116 return I40E_ERR_PARAM;
5118 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5119 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5120 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5122 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5124 if (status == I40E_SUCCESS) {
5125 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5127 if (reg_val1 != NULL)
5128 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5135 * i40e_aq_alternate_read_indirect
5136 * @hw: pointer to the hardware structure
5137 * @addr: address of the alternate structure field
5138 * @dw_count: number of alternate structure fields to read
5139 * @buffer: pointer to the command buffer
5141 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5142 * place them in 'buffer'. The buffer should be allocated by caller.
5145 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5146 u32 addr, u32 dw_count, void *buffer)
5148 struct i40e_aq_desc desc;
5149 struct i40e_aqc_alternate_ind_write *cmd_resp =
5150 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5151 enum i40e_status_code status;
5154 return I40E_ERR_PARAM;
5156 /* Indirect command */
5157 i40e_fill_default_direct_cmd_desc(&desc,
5158 i40e_aqc_opc_alternate_read_indirect);
5160 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5161 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5162 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5163 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5165 cmd_resp->address = CPU_TO_LE32(addr);
5166 cmd_resp->length = CPU_TO_LE32(dw_count);
5167 cmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));
5168 cmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));
5170 status = i40e_asq_send_command(hw, &desc, buffer,
5171 I40E_LO_DWORD(4*dw_count), NULL);
5177 * i40e_aq_alternate_clear
5178 * @hw: pointer to the HW structure.
5180 * Clear the alternate structures of the port from which the function
5184 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5186 struct i40e_aq_desc desc;
5187 enum i40e_status_code status;
5189 i40e_fill_default_direct_cmd_desc(&desc,
5190 i40e_aqc_opc_alternate_clear_port);
5192 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5198 * i40e_aq_alternate_write_done
5199 * @hw: pointer to the HW structure.
5200 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5201 * @reset_needed: indicates the SW should trigger GLOBAL reset
5203 * Indicates to the FW that alternate structures have been changed.
5206 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5207 u8 bios_mode, bool *reset_needed)
5209 struct i40e_aq_desc desc;
5210 struct i40e_aqc_alternate_write_done *cmd =
5211 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5212 enum i40e_status_code status;
5214 if (reset_needed == NULL)
5215 return I40E_ERR_PARAM;
5217 i40e_fill_default_direct_cmd_desc(&desc,
5218 i40e_aqc_opc_alternate_write_done);
5220 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5222 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5223 if (!status && reset_needed)
5224 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5225 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5231 * i40e_aq_set_oem_mode
5232 * @hw: pointer to the HW structure.
5233 * @oem_mode: the OEM mode to be used
5235 * Sets the device to a specific operating mode. Currently the only supported
5236 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5239 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5242 struct i40e_aq_desc desc;
5243 struct i40e_aqc_alternate_write_done *cmd =
5244 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5245 enum i40e_status_code status;
5247 i40e_fill_default_direct_cmd_desc(&desc,
5248 i40e_aqc_opc_alternate_set_mode);
5250 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5252 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5258 * i40e_aq_resume_port_tx
5259 * @hw: pointer to the hardware structure
5260 * @cmd_details: pointer to command details structure or NULL
5262 * Resume port's Tx traffic
5264 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5265 struct i40e_asq_cmd_details *cmd_details)
5267 struct i40e_aq_desc desc;
5268 enum i40e_status_code status;
5270 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5272 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5278 * i40e_set_pci_config_data - store PCI bus info
5279 * @hw: pointer to hardware structure
5280 * @link_status: the link status word from PCI config space
5282 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5284 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5286 hw->bus.type = i40e_bus_type_pci_express;
5288 switch (link_status & I40E_PCI_LINK_WIDTH) {
5289 case I40E_PCI_LINK_WIDTH_1:
5290 hw->bus.width = i40e_bus_width_pcie_x1;
5292 case I40E_PCI_LINK_WIDTH_2:
5293 hw->bus.width = i40e_bus_width_pcie_x2;
5295 case I40E_PCI_LINK_WIDTH_4:
5296 hw->bus.width = i40e_bus_width_pcie_x4;
5298 case I40E_PCI_LINK_WIDTH_8:
5299 hw->bus.width = i40e_bus_width_pcie_x8;
5302 hw->bus.width = i40e_bus_width_unknown;
5306 switch (link_status & I40E_PCI_LINK_SPEED) {
5307 case I40E_PCI_LINK_SPEED_2500:
5308 hw->bus.speed = i40e_bus_speed_2500;
5310 case I40E_PCI_LINK_SPEED_5000:
5311 hw->bus.speed = i40e_bus_speed_5000;
5313 case I40E_PCI_LINK_SPEED_8000:
5314 hw->bus.speed = i40e_bus_speed_8000;
5317 hw->bus.speed = i40e_bus_speed_unknown;
5323 * i40e_aq_debug_dump
5324 * @hw: pointer to the hardware structure
5325 * @cluster_id: specific cluster to dump
5326 * @table_id: table id within cluster
5327 * @start_index: index of line in the block to read
5328 * @buff_size: dump buffer size
5329 * @buff: dump buffer
5330 * @ret_buff_size: actual buffer size returned
5331 * @ret_next_table: next block to read
5332 * @ret_next_index: next index to read
5334 * Dump internal FW/HW data for debug purposes.
5337 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5338 u8 table_id, u32 start_index, u16 buff_size,
5339 void *buff, u16 *ret_buff_size,
5340 u8 *ret_next_table, u32 *ret_next_index,
5341 struct i40e_asq_cmd_details *cmd_details)
5343 struct i40e_aq_desc desc;
5344 struct i40e_aqc_debug_dump_internals *cmd =
5345 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5346 struct i40e_aqc_debug_dump_internals *resp =
5347 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5348 enum i40e_status_code status;
5350 if (buff_size == 0 || !buff)
5351 return I40E_ERR_PARAM;
5353 i40e_fill_default_direct_cmd_desc(&desc,
5354 i40e_aqc_opc_debug_dump_internals);
5355 /* Indirect Command */
5356 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5357 if (buff_size > I40E_AQ_LARGE_BUF)
5358 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5360 cmd->cluster_id = cluster_id;
5361 cmd->table_id = table_id;
5362 cmd->idx = CPU_TO_LE32(start_index);
5364 desc.datalen = CPU_TO_LE16(buff_size);
5366 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5368 if (ret_buff_size != NULL)
5369 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5370 if (ret_next_table != NULL)
5371 *ret_next_table = resp->table_id;
5372 if (ret_next_index != NULL)
5373 *ret_next_index = LE32_TO_CPU(resp->idx);
5380 * i40e_read_bw_from_alt_ram
5381 * @hw: pointer to the hardware structure
5382 * @max_bw: pointer for max_bw read
5383 * @min_bw: pointer for min_bw read
5384 * @min_valid: pointer for bool that is true if min_bw is a valid value
5385 * @max_valid: pointer for bool that is true if max_bw is a valid value
5387 * Read bw from the alternate ram for the given pf
5389 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5390 u32 *max_bw, u32 *min_bw,
5391 bool *min_valid, bool *max_valid)
5393 enum i40e_status_code status;
5394 u32 max_bw_addr, min_bw_addr;
5396 /* Calculate the address of the min/max bw registers */
5397 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5398 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5399 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5400 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5401 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5402 (I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);
5404 /* Read the bandwidths from alt ram */
5405 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5406 min_bw_addr, min_bw);
5408 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5413 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5422 * i40e_aq_configure_partition_bw
5423 * @hw: pointer to the hardware structure
5424 * @bw_data: Buffer holding valid pfs and bw limits
5425 * @cmd_details: pointer to command details
5427 * Configure partitions guaranteed/max bw
5429 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5430 struct i40e_aqc_configure_partition_bw_data *bw_data,
5431 struct i40e_asq_cmd_details *cmd_details)
5433 enum i40e_status_code status;
5434 struct i40e_aq_desc desc;
5435 u16 bwd_size = sizeof(*bw_data);
5437 i40e_fill_default_direct_cmd_desc(&desc,
5438 i40e_aqc_opc_configure_partition_bw);
5440 /* Indirect command */
5441 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5442 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5444 if (bwd_size > I40E_AQ_LARGE_BUF)
5445 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5447 desc.datalen = CPU_TO_LE16(bwd_size);
5449 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5453 #endif /* PF_DRIVER */
5457 * i40e_aq_send_msg_to_pf
5458 * @hw: pointer to the hardware structure
5459 * @v_opcode: opcodes for VF-PF communication
5460 * @v_retval: return error code
5461 * @msg: pointer to the msg buffer
5462 * @msglen: msg length
5463 * @cmd_details: pointer to command details
5465 * Send message to PF driver using admin queue. By default, this message
5466 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5467 * completion before returning.
5469 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5470 enum i40e_virtchnl_ops v_opcode,
5471 enum i40e_status_code v_retval,
5472 u8 *msg, u16 msglen,
5473 struct i40e_asq_cmd_details *cmd_details)
5475 struct i40e_aq_desc desc;
5476 struct i40e_asq_cmd_details details;
5477 enum i40e_status_code status;
5479 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5480 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5481 desc.cookie_high = CPU_TO_LE32(v_opcode);
5482 desc.cookie_low = CPU_TO_LE32(v_retval);
5484 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5485 | I40E_AQ_FLAG_RD));
5486 if (msglen > I40E_AQ_LARGE_BUF)
5487 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5488 desc.datalen = CPU_TO_LE16(msglen);
5491 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5492 details.async = true;
5493 cmd_details = &details;
5495 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5496 msglen, cmd_details);
5501 * i40e_vf_parse_hw_config
5502 * @hw: pointer to the hardware structure
5503 * @msg: pointer to the virtual channel VF resource structure
5505 * Given a VF resource message from the PF, populate the hw struct
5506 * with appropriate information.
5508 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5509 struct i40e_virtchnl_vf_resource *msg)
5511 struct i40e_virtchnl_vsi_resource *vsi_res;
5514 vsi_res = &msg->vsi_res[0];
5516 hw->dev_caps.num_vsis = msg->num_vsis;
5517 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5518 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5519 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5520 hw->dev_caps.dcb = msg->vf_offload_flags &
5521 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5522 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5523 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5524 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5525 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5526 for (i = 0; i < msg->num_vsis; i++) {
5527 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5528 i40e_memcpy(hw->mac.perm_addr,
5529 vsi_res->default_mac_addr,
5530 I40E_ETH_LENGTH_OF_ADDRESS,
5531 I40E_NONDMA_TO_NONDMA);
5532 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5533 I40E_ETH_LENGTH_OF_ADDRESS,
5534 I40E_NONDMA_TO_NONDMA);
5542 * @hw: pointer to the hardware structure
5544 * Send a VF_RESET message to the PF. Does not wait for response from PF
5545 * as none will be forthcoming. Immediately after calling this function,
5546 * the admin queue should be shut down and (optionally) reinitialized.
5548 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5550 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5551 I40E_SUCCESS, NULL, 0, NULL);
5553 #endif /* VF_DRIVER */