1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2018
6 #include "i40e_adminq.h"
7 #include "i40e_prototype.h"
11 * i40e_set_mac_type - Sets MAC type
12 * @hw: pointer to the HW structure
14 * This function sets the mac type of the adapter based on the
15 * vendor ID and device ID stored in the hw structure.
17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
23 enum i40e_status_code status = I40E_SUCCESS;
25 DEBUGFUNC("i40e_set_mac_type\n");
27 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
28 switch (hw->device_id) {
29 case I40E_DEV_ID_SFP_XL710:
30 case I40E_DEV_ID_QEMU:
31 case I40E_DEV_ID_KX_B:
32 case I40E_DEV_ID_KX_C:
33 case I40E_DEV_ID_QSFP_A:
34 case I40E_DEV_ID_QSFP_B:
35 case I40E_DEV_ID_QSFP_C:
36 case I40E_DEV_ID_10G_BASE_T:
37 case I40E_DEV_ID_10G_BASE_T4:
38 case I40E_DEV_ID_10G_BASE_T_BC:
39 case I40E_DEV_ID_10G_B:
40 case I40E_DEV_ID_10G_SFP:
41 case I40E_DEV_ID_20G_KR2:
42 case I40E_DEV_ID_20G_KR2_A:
43 case I40E_DEV_ID_25G_B:
44 case I40E_DEV_ID_25G_SFP28:
45 case I40E_DEV_ID_X710_N3000:
46 case I40E_DEV_ID_XXV710_N3000:
47 hw->mac.type = I40E_MAC_XL710;
49 #ifdef X722_A0_SUPPORT
50 case I40E_DEV_ID_X722_A0:
52 case I40E_DEV_ID_KX_X722:
53 case I40E_DEV_ID_QSFP_X722:
54 case I40E_DEV_ID_SFP_X722:
55 case I40E_DEV_ID_1G_BASE_T_X722:
56 case I40E_DEV_ID_10G_BASE_T_X722:
57 case I40E_DEV_ID_SFP_I_X722:
58 hw->mac.type = I40E_MAC_X722;
60 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
61 case I40E_DEV_ID_X722_VF:
62 #ifdef X722_A0_SUPPORT
63 case I40E_DEV_ID_X722_A0_VF:
65 hw->mac.type = I40E_MAC_X722_VF;
67 #endif /* INTEGRATED_VF || VF_DRIVER */
68 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
70 case I40E_DEV_ID_VF_HV:
71 case I40E_DEV_ID_ADAPTIVE_VF:
72 hw->mac.type = I40E_MAC_VF;
76 hw->mac.type = I40E_MAC_GENERIC;
80 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
83 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
84 hw->mac.type, status);
89 * i40e_aq_str - convert AQ err code to a string
90 * @hw: pointer to the HW structure
91 * @aq_err: the AQ error code to convert
93 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
98 case I40E_AQ_RC_EPERM:
99 return "I40E_AQ_RC_EPERM";
100 case I40E_AQ_RC_ENOENT:
101 return "I40E_AQ_RC_ENOENT";
102 case I40E_AQ_RC_ESRCH:
103 return "I40E_AQ_RC_ESRCH";
104 case I40E_AQ_RC_EINTR:
105 return "I40E_AQ_RC_EINTR";
107 return "I40E_AQ_RC_EIO";
108 case I40E_AQ_RC_ENXIO:
109 return "I40E_AQ_RC_ENXIO";
110 case I40E_AQ_RC_E2BIG:
111 return "I40E_AQ_RC_E2BIG";
112 case I40E_AQ_RC_EAGAIN:
113 return "I40E_AQ_RC_EAGAIN";
114 case I40E_AQ_RC_ENOMEM:
115 return "I40E_AQ_RC_ENOMEM";
116 case I40E_AQ_RC_EACCES:
117 return "I40E_AQ_RC_EACCES";
118 case I40E_AQ_RC_EFAULT:
119 return "I40E_AQ_RC_EFAULT";
120 case I40E_AQ_RC_EBUSY:
121 return "I40E_AQ_RC_EBUSY";
122 case I40E_AQ_RC_EEXIST:
123 return "I40E_AQ_RC_EEXIST";
124 case I40E_AQ_RC_EINVAL:
125 return "I40E_AQ_RC_EINVAL";
126 case I40E_AQ_RC_ENOTTY:
127 return "I40E_AQ_RC_ENOTTY";
128 case I40E_AQ_RC_ENOSPC:
129 return "I40E_AQ_RC_ENOSPC";
130 case I40E_AQ_RC_ENOSYS:
131 return "I40E_AQ_RC_ENOSYS";
132 case I40E_AQ_RC_ERANGE:
133 return "I40E_AQ_RC_ERANGE";
134 case I40E_AQ_RC_EFLUSHED:
135 return "I40E_AQ_RC_EFLUSHED";
136 case I40E_AQ_RC_BAD_ADDR:
137 return "I40E_AQ_RC_BAD_ADDR";
138 case I40E_AQ_RC_EMODE:
139 return "I40E_AQ_RC_EMODE";
140 case I40E_AQ_RC_EFBIG:
141 return "I40E_AQ_RC_EFBIG";
144 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
149 * i40e_stat_str - convert status err code to a string
150 * @hw: pointer to the HW structure
151 * @stat_err: the status error code to convert
153 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
159 return "I40E_ERR_NVM";
160 case I40E_ERR_NVM_CHECKSUM:
161 return "I40E_ERR_NVM_CHECKSUM";
163 return "I40E_ERR_PHY";
164 case I40E_ERR_CONFIG:
165 return "I40E_ERR_CONFIG";
167 return "I40E_ERR_PARAM";
168 case I40E_ERR_MAC_TYPE:
169 return "I40E_ERR_MAC_TYPE";
170 case I40E_ERR_UNKNOWN_PHY:
171 return "I40E_ERR_UNKNOWN_PHY";
172 case I40E_ERR_LINK_SETUP:
173 return "I40E_ERR_LINK_SETUP";
174 case I40E_ERR_ADAPTER_STOPPED:
175 return "I40E_ERR_ADAPTER_STOPPED";
176 case I40E_ERR_INVALID_MAC_ADDR:
177 return "I40E_ERR_INVALID_MAC_ADDR";
178 case I40E_ERR_DEVICE_NOT_SUPPORTED:
179 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
180 case I40E_ERR_MASTER_REQUESTS_PENDING:
181 return "I40E_ERR_MASTER_REQUESTS_PENDING";
182 case I40E_ERR_INVALID_LINK_SETTINGS:
183 return "I40E_ERR_INVALID_LINK_SETTINGS";
184 case I40E_ERR_AUTONEG_NOT_COMPLETE:
185 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
186 case I40E_ERR_RESET_FAILED:
187 return "I40E_ERR_RESET_FAILED";
188 case I40E_ERR_SWFW_SYNC:
189 return "I40E_ERR_SWFW_SYNC";
190 case I40E_ERR_NO_AVAILABLE_VSI:
191 return "I40E_ERR_NO_AVAILABLE_VSI";
192 case I40E_ERR_NO_MEMORY:
193 return "I40E_ERR_NO_MEMORY";
194 case I40E_ERR_BAD_PTR:
195 return "I40E_ERR_BAD_PTR";
196 case I40E_ERR_RING_FULL:
197 return "I40E_ERR_RING_FULL";
198 case I40E_ERR_INVALID_PD_ID:
199 return "I40E_ERR_INVALID_PD_ID";
200 case I40E_ERR_INVALID_QP_ID:
201 return "I40E_ERR_INVALID_QP_ID";
202 case I40E_ERR_INVALID_CQ_ID:
203 return "I40E_ERR_INVALID_CQ_ID";
204 case I40E_ERR_INVALID_CEQ_ID:
205 return "I40E_ERR_INVALID_CEQ_ID";
206 case I40E_ERR_INVALID_AEQ_ID:
207 return "I40E_ERR_INVALID_AEQ_ID";
208 case I40E_ERR_INVALID_SIZE:
209 return "I40E_ERR_INVALID_SIZE";
210 case I40E_ERR_INVALID_ARP_INDEX:
211 return "I40E_ERR_INVALID_ARP_INDEX";
212 case I40E_ERR_INVALID_FPM_FUNC_ID:
213 return "I40E_ERR_INVALID_FPM_FUNC_ID";
214 case I40E_ERR_QP_INVALID_MSG_SIZE:
215 return "I40E_ERR_QP_INVALID_MSG_SIZE";
216 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
217 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
218 case I40E_ERR_INVALID_FRAG_COUNT:
219 return "I40E_ERR_INVALID_FRAG_COUNT";
220 case I40E_ERR_QUEUE_EMPTY:
221 return "I40E_ERR_QUEUE_EMPTY";
222 case I40E_ERR_INVALID_ALIGNMENT:
223 return "I40E_ERR_INVALID_ALIGNMENT";
224 case I40E_ERR_FLUSHED_QUEUE:
225 return "I40E_ERR_FLUSHED_QUEUE";
226 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
227 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
228 case I40E_ERR_INVALID_IMM_DATA_SIZE:
229 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
230 case I40E_ERR_TIMEOUT:
231 return "I40E_ERR_TIMEOUT";
232 case I40E_ERR_OPCODE_MISMATCH:
233 return "I40E_ERR_OPCODE_MISMATCH";
234 case I40E_ERR_CQP_COMPL_ERROR:
235 return "I40E_ERR_CQP_COMPL_ERROR";
236 case I40E_ERR_INVALID_VF_ID:
237 return "I40E_ERR_INVALID_VF_ID";
238 case I40E_ERR_INVALID_HMCFN_ID:
239 return "I40E_ERR_INVALID_HMCFN_ID";
240 case I40E_ERR_BACKING_PAGE_ERROR:
241 return "I40E_ERR_BACKING_PAGE_ERROR";
242 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
243 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
244 case I40E_ERR_INVALID_PBLE_INDEX:
245 return "I40E_ERR_INVALID_PBLE_INDEX";
246 case I40E_ERR_INVALID_SD_INDEX:
247 return "I40E_ERR_INVALID_SD_INDEX";
248 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
249 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
250 case I40E_ERR_INVALID_SD_TYPE:
251 return "I40E_ERR_INVALID_SD_TYPE";
252 case I40E_ERR_MEMCPY_FAILED:
253 return "I40E_ERR_MEMCPY_FAILED";
254 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
255 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
256 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
257 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
258 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
259 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
260 case I40E_ERR_SRQ_ENABLED:
261 return "I40E_ERR_SRQ_ENABLED";
262 case I40E_ERR_ADMIN_QUEUE_ERROR:
263 return "I40E_ERR_ADMIN_QUEUE_ERROR";
264 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
265 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
266 case I40E_ERR_BUF_TOO_SHORT:
267 return "I40E_ERR_BUF_TOO_SHORT";
268 case I40E_ERR_ADMIN_QUEUE_FULL:
269 return "I40E_ERR_ADMIN_QUEUE_FULL";
270 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
271 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
272 case I40E_ERR_BAD_IWARP_CQE:
273 return "I40E_ERR_BAD_IWARP_CQE";
274 case I40E_ERR_NVM_BLANK_MODE:
275 return "I40E_ERR_NVM_BLANK_MODE";
276 case I40E_ERR_NOT_IMPLEMENTED:
277 return "I40E_ERR_NOT_IMPLEMENTED";
278 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
279 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
280 case I40E_ERR_DIAG_TEST_FAILED:
281 return "I40E_ERR_DIAG_TEST_FAILED";
282 case I40E_ERR_NOT_READY:
283 return "I40E_ERR_NOT_READY";
284 case I40E_NOT_SUPPORTED:
285 return "I40E_NOT_SUPPORTED";
286 case I40E_ERR_FIRMWARE_API_VERSION:
287 return "I40E_ERR_FIRMWARE_API_VERSION";
288 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
289 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
292 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
298 * @hw: debug mask related to admin queue
300 * @desc: pointer to admin queue descriptor
301 * @buffer: pointer to command buffer
302 * @buf_len: max length of buffer
304 * Dumps debug log about adminq command with descriptor contents.
306 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
307 void *buffer, u16 buf_len)
309 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
310 u8 *buf = (u8 *)buffer;
314 if ((!(mask & hw->debug_mask)) || (desc == NULL))
317 len = LE16_TO_CPU(aq_desc->datalen);
320 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
321 LE16_TO_CPU(aq_desc->opcode),
322 LE16_TO_CPU(aq_desc->flags),
323 LE16_TO_CPU(aq_desc->datalen),
324 LE16_TO_CPU(aq_desc->retval));
325 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
326 LE32_TO_CPU(aq_desc->cookie_high),
327 LE32_TO_CPU(aq_desc->cookie_low));
328 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
329 LE32_TO_CPU(aq_desc->params.internal.param0),
330 LE32_TO_CPU(aq_desc->params.internal.param1));
331 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
332 LE32_TO_CPU(aq_desc->params.external.addr_high),
333 LE32_TO_CPU(aq_desc->params.external.addr_low));
335 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
336 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
339 /* write the full 16-byte chunks */
340 for (i = 0; i < (len - 16); i += 16)
342 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
343 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
344 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
345 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
346 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
347 /* the most we could have left is 16 bytes, pad with zeros */
353 memset(d_buf, 0, sizeof(d_buf));
354 for (j = 0; i < len; j++, i++)
357 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
358 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
359 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
360 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
361 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
367 * i40e_check_asq_alive
368 * @hw: pointer to the hw struct
370 * Returns true if Queue is enabled else false.
372 bool i40e_check_asq_alive(struct i40e_hw *hw)
378 return !!(rd32(hw, hw->aq.asq.len) &
379 I40E_PF_ATQLEN_ATQENABLE_MASK);
381 return !!(rd32(hw, hw->aq.asq.len) &
382 I40E_PF_ATQLEN_ATQENABLE_MASK);
383 #endif /* INTEGRATED_VF */
384 #endif /* PF_DRIVER */
388 return !!(rd32(hw, hw->aq.asq.len) &
389 I40E_VF_ATQLEN1_ATQENABLE_MASK);
391 return !!(rd32(hw, hw->aq.asq.len) &
392 I40E_VF_ATQLEN1_ATQENABLE_MASK);
393 #endif /* INTEGRATED_VF */
394 #endif /* VF_DRIVER */
399 * i40e_aq_queue_shutdown
400 * @hw: pointer to the hw struct
401 * @unloading: is the driver unloading itself
403 * Tell the Firmware that we're shutting down the AdminQ and whether
404 * or not the driver is unloading as well.
406 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
409 struct i40e_aq_desc desc;
410 struct i40e_aqc_queue_shutdown *cmd =
411 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
412 enum i40e_status_code status;
414 i40e_fill_default_direct_cmd_desc(&desc,
415 i40e_aqc_opc_queue_shutdown);
418 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
419 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
425 * i40e_aq_get_set_rss_lut
426 * @hw: pointer to the hardware structure
427 * @vsi_id: vsi fw index
428 * @pf_lut: for PF table set true, for VSI table set false
429 * @lut: pointer to the lut buffer provided by the caller
430 * @lut_size: size of the lut buffer
431 * @set: set true to set the table, false to get the table
433 * Internal function to get or set RSS look up table
435 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
436 u16 vsi_id, bool pf_lut,
437 u8 *lut, u16 lut_size,
440 enum i40e_status_code status;
441 struct i40e_aq_desc desc;
442 struct i40e_aqc_get_set_rss_lut *cmd_resp =
443 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
446 i40e_fill_default_direct_cmd_desc(&desc,
447 i40e_aqc_opc_set_rss_lut);
449 i40e_fill_default_direct_cmd_desc(&desc,
450 i40e_aqc_opc_get_rss_lut);
452 /* Indirect command */
453 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
454 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
457 CPU_TO_LE16((u16)((vsi_id <<
458 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
459 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
460 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
463 cmd_resp->flags |= CPU_TO_LE16((u16)
464 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
465 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
466 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
468 cmd_resp->flags |= CPU_TO_LE16((u16)
469 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
470 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
471 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
473 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
479 * i40e_aq_get_rss_lut
480 * @hw: pointer to the hardware structure
481 * @vsi_id: vsi fw index
482 * @pf_lut: for PF table set true, for VSI table set false
483 * @lut: pointer to the lut buffer provided by the caller
484 * @lut_size: size of the lut buffer
486 * get the RSS lookup table, PF or VSI type
488 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
489 bool pf_lut, u8 *lut, u16 lut_size)
491 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
496 * i40e_aq_set_rss_lut
497 * @hw: pointer to the hardware structure
498 * @vsi_id: vsi fw index
499 * @pf_lut: for PF table set true, for VSI table set false
500 * @lut: pointer to the lut buffer provided by the caller
501 * @lut_size: size of the lut buffer
503 * set the RSS lookup table, PF or VSI type
505 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
506 bool pf_lut, u8 *lut, u16 lut_size)
508 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
512 * i40e_aq_get_set_rss_key
513 * @hw: pointer to the hw struct
514 * @vsi_id: vsi fw index
515 * @key: pointer to key info struct
516 * @set: set true to set the key, false to get the key
518 * get the RSS key per VSI
520 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
522 struct i40e_aqc_get_set_rss_key_data *key,
525 enum i40e_status_code status;
526 struct i40e_aq_desc desc;
527 struct i40e_aqc_get_set_rss_key *cmd_resp =
528 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
529 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
532 i40e_fill_default_direct_cmd_desc(&desc,
533 i40e_aqc_opc_set_rss_key);
535 i40e_fill_default_direct_cmd_desc(&desc,
536 i40e_aqc_opc_get_rss_key);
538 /* Indirect command */
539 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
540 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
543 CPU_TO_LE16((u16)((vsi_id <<
544 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
545 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
546 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
548 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
554 * i40e_aq_get_rss_key
555 * @hw: pointer to the hw struct
556 * @vsi_id: vsi fw index
557 * @key: pointer to key info struct
560 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
562 struct i40e_aqc_get_set_rss_key_data *key)
564 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
568 * i40e_aq_set_rss_key
569 * @hw: pointer to the hw struct
570 * @vsi_id: vsi fw index
571 * @key: pointer to key info struct
573 * set the RSS key per VSI
575 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
577 struct i40e_aqc_get_set_rss_key_data *key)
579 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
582 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
583 * hardware to a bit-field that can be used by SW to more easily determine the
586 * Macros are used to shorten the table lines and make this table human
589 * We store the PTYPE in the top byte of the bit field - this is just so that
590 * we can check that the table doesn't have a row missing, as the index into
591 * the table should be the PTYPE.
595 * IF NOT i40e_ptype_lookup[ptype].known
598 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
599 * Use the rest of the fields to look at the tunnels, inner protocols, etc
601 * Use the enum i40e_rx_l2_ptype to decode the packet type
605 /* macro to make the table lines short */
606 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
609 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
610 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
611 I40E_RX_PTYPE_##OUTER_FRAG, \
612 I40E_RX_PTYPE_TUNNEL_##T, \
613 I40E_RX_PTYPE_TUNNEL_END_##TE, \
614 I40E_RX_PTYPE_##TEF, \
615 I40E_RX_PTYPE_INNER_PROT_##I, \
616 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
618 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
619 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
621 /* shorter macros makes the table fit but are terse */
622 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
623 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
624 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
626 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
627 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
628 /* L2 Packet types */
629 I40E_PTT_UNUSED_ENTRY(0),
630 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
631 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
632 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
633 I40E_PTT_UNUSED_ENTRY(4),
634 I40E_PTT_UNUSED_ENTRY(5),
635 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
636 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
637 I40E_PTT_UNUSED_ENTRY(8),
638 I40E_PTT_UNUSED_ENTRY(9),
639 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
640 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
641 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
642 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
643 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
644 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
645 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
646 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
647 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
648 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
649 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
650 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
652 /* Non Tunneled IPv4 */
653 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
654 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
655 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
656 I40E_PTT_UNUSED_ENTRY(25),
657 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
658 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
659 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
662 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
663 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
664 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
665 I40E_PTT_UNUSED_ENTRY(32),
666 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
667 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
668 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
671 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
672 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
673 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
674 I40E_PTT_UNUSED_ENTRY(39),
675 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
676 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
677 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
679 /* IPv4 --> GRE/NAT */
680 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
682 /* IPv4 --> GRE/NAT --> IPv4 */
683 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
684 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
685 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
686 I40E_PTT_UNUSED_ENTRY(47),
687 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
688 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
689 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
691 /* IPv4 --> GRE/NAT --> IPv6 */
692 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
693 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
694 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
695 I40E_PTT_UNUSED_ENTRY(54),
696 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
697 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
698 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
700 /* IPv4 --> GRE/NAT --> MAC */
701 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
703 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
704 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
705 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
706 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
707 I40E_PTT_UNUSED_ENTRY(62),
708 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
709 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
710 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
712 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
713 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
714 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
715 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
716 I40E_PTT_UNUSED_ENTRY(69),
717 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
718 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
719 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
721 /* IPv4 --> GRE/NAT --> MAC/VLAN */
722 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
724 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
725 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
726 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
727 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
728 I40E_PTT_UNUSED_ENTRY(77),
729 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
730 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
731 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
733 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
734 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
735 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
736 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
737 I40E_PTT_UNUSED_ENTRY(84),
738 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
739 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
740 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
742 /* Non Tunneled IPv6 */
743 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
744 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
745 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
746 I40E_PTT_UNUSED_ENTRY(91),
747 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
748 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
749 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
752 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
753 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
754 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
755 I40E_PTT_UNUSED_ENTRY(98),
756 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
757 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
758 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
761 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
762 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
763 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
764 I40E_PTT_UNUSED_ENTRY(105),
765 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
766 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
767 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
769 /* IPv6 --> GRE/NAT */
770 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
772 /* IPv6 --> GRE/NAT -> IPv4 */
773 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
774 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
775 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
776 I40E_PTT_UNUSED_ENTRY(113),
777 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
778 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
779 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
781 /* IPv6 --> GRE/NAT -> IPv6 */
782 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
783 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
784 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
785 I40E_PTT_UNUSED_ENTRY(120),
786 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
787 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
788 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
790 /* IPv6 --> GRE/NAT -> MAC */
791 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
793 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
794 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
795 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
796 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
797 I40E_PTT_UNUSED_ENTRY(128),
798 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
799 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
800 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
802 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
803 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
804 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
805 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
806 I40E_PTT_UNUSED_ENTRY(135),
807 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
808 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
809 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
811 /* IPv6 --> GRE/NAT -> MAC/VLAN */
812 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
814 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
815 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
816 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
817 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
818 I40E_PTT_UNUSED_ENTRY(143),
819 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
820 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
821 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
823 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
824 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
825 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
826 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
827 I40E_PTT_UNUSED_ENTRY(150),
828 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
829 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
830 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
833 I40E_PTT_UNUSED_ENTRY(154),
834 I40E_PTT_UNUSED_ENTRY(155),
835 I40E_PTT_UNUSED_ENTRY(156),
836 I40E_PTT_UNUSED_ENTRY(157),
837 I40E_PTT_UNUSED_ENTRY(158),
838 I40E_PTT_UNUSED_ENTRY(159),
840 I40E_PTT_UNUSED_ENTRY(160),
841 I40E_PTT_UNUSED_ENTRY(161),
842 I40E_PTT_UNUSED_ENTRY(162),
843 I40E_PTT_UNUSED_ENTRY(163),
844 I40E_PTT_UNUSED_ENTRY(164),
845 I40E_PTT_UNUSED_ENTRY(165),
846 I40E_PTT_UNUSED_ENTRY(166),
847 I40E_PTT_UNUSED_ENTRY(167),
848 I40E_PTT_UNUSED_ENTRY(168),
849 I40E_PTT_UNUSED_ENTRY(169),
851 I40E_PTT_UNUSED_ENTRY(170),
852 I40E_PTT_UNUSED_ENTRY(171),
853 I40E_PTT_UNUSED_ENTRY(172),
854 I40E_PTT_UNUSED_ENTRY(173),
855 I40E_PTT_UNUSED_ENTRY(174),
856 I40E_PTT_UNUSED_ENTRY(175),
857 I40E_PTT_UNUSED_ENTRY(176),
858 I40E_PTT_UNUSED_ENTRY(177),
859 I40E_PTT_UNUSED_ENTRY(178),
860 I40E_PTT_UNUSED_ENTRY(179),
862 I40E_PTT_UNUSED_ENTRY(180),
863 I40E_PTT_UNUSED_ENTRY(181),
864 I40E_PTT_UNUSED_ENTRY(182),
865 I40E_PTT_UNUSED_ENTRY(183),
866 I40E_PTT_UNUSED_ENTRY(184),
867 I40E_PTT_UNUSED_ENTRY(185),
868 I40E_PTT_UNUSED_ENTRY(186),
869 I40E_PTT_UNUSED_ENTRY(187),
870 I40E_PTT_UNUSED_ENTRY(188),
871 I40E_PTT_UNUSED_ENTRY(189),
873 I40E_PTT_UNUSED_ENTRY(190),
874 I40E_PTT_UNUSED_ENTRY(191),
875 I40E_PTT_UNUSED_ENTRY(192),
876 I40E_PTT_UNUSED_ENTRY(193),
877 I40E_PTT_UNUSED_ENTRY(194),
878 I40E_PTT_UNUSED_ENTRY(195),
879 I40E_PTT_UNUSED_ENTRY(196),
880 I40E_PTT_UNUSED_ENTRY(197),
881 I40E_PTT_UNUSED_ENTRY(198),
882 I40E_PTT_UNUSED_ENTRY(199),
884 I40E_PTT_UNUSED_ENTRY(200),
885 I40E_PTT_UNUSED_ENTRY(201),
886 I40E_PTT_UNUSED_ENTRY(202),
887 I40E_PTT_UNUSED_ENTRY(203),
888 I40E_PTT_UNUSED_ENTRY(204),
889 I40E_PTT_UNUSED_ENTRY(205),
890 I40E_PTT_UNUSED_ENTRY(206),
891 I40E_PTT_UNUSED_ENTRY(207),
892 I40E_PTT_UNUSED_ENTRY(208),
893 I40E_PTT_UNUSED_ENTRY(209),
895 I40E_PTT_UNUSED_ENTRY(210),
896 I40E_PTT_UNUSED_ENTRY(211),
897 I40E_PTT_UNUSED_ENTRY(212),
898 I40E_PTT_UNUSED_ENTRY(213),
899 I40E_PTT_UNUSED_ENTRY(214),
900 I40E_PTT_UNUSED_ENTRY(215),
901 I40E_PTT_UNUSED_ENTRY(216),
902 I40E_PTT_UNUSED_ENTRY(217),
903 I40E_PTT_UNUSED_ENTRY(218),
904 I40E_PTT_UNUSED_ENTRY(219),
906 I40E_PTT_UNUSED_ENTRY(220),
907 I40E_PTT_UNUSED_ENTRY(221),
908 I40E_PTT_UNUSED_ENTRY(222),
909 I40E_PTT_UNUSED_ENTRY(223),
910 I40E_PTT_UNUSED_ENTRY(224),
911 I40E_PTT_UNUSED_ENTRY(225),
912 I40E_PTT_UNUSED_ENTRY(226),
913 I40E_PTT_UNUSED_ENTRY(227),
914 I40E_PTT_UNUSED_ENTRY(228),
915 I40E_PTT_UNUSED_ENTRY(229),
917 I40E_PTT_UNUSED_ENTRY(230),
918 I40E_PTT_UNUSED_ENTRY(231),
919 I40E_PTT_UNUSED_ENTRY(232),
920 I40E_PTT_UNUSED_ENTRY(233),
921 I40E_PTT_UNUSED_ENTRY(234),
922 I40E_PTT_UNUSED_ENTRY(235),
923 I40E_PTT_UNUSED_ENTRY(236),
924 I40E_PTT_UNUSED_ENTRY(237),
925 I40E_PTT_UNUSED_ENTRY(238),
926 I40E_PTT_UNUSED_ENTRY(239),
928 I40E_PTT_UNUSED_ENTRY(240),
929 I40E_PTT_UNUSED_ENTRY(241),
930 I40E_PTT_UNUSED_ENTRY(242),
931 I40E_PTT_UNUSED_ENTRY(243),
932 I40E_PTT_UNUSED_ENTRY(244),
933 I40E_PTT_UNUSED_ENTRY(245),
934 I40E_PTT_UNUSED_ENTRY(246),
935 I40E_PTT_UNUSED_ENTRY(247),
936 I40E_PTT_UNUSED_ENTRY(248),
937 I40E_PTT_UNUSED_ENTRY(249),
939 I40E_PTT_UNUSED_ENTRY(250),
940 I40E_PTT_UNUSED_ENTRY(251),
941 I40E_PTT_UNUSED_ENTRY(252),
942 I40E_PTT_UNUSED_ENTRY(253),
943 I40E_PTT_UNUSED_ENTRY(254),
944 I40E_PTT_UNUSED_ENTRY(255)
949 * i40e_validate_mac_addr - Validate unicast MAC address
950 * @mac_addr: pointer to MAC address
952 * Tests a MAC address to ensure it is a valid Individual Address
954 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
956 enum i40e_status_code status = I40E_SUCCESS;
958 DEBUGFUNC("i40e_validate_mac_addr");
960 /* Broadcast addresses ARE multicast addresses
961 * Make sure it is not a multicast address
962 * Reject the zero address
964 if (I40E_IS_MULTICAST(mac_addr) ||
965 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
966 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
967 status = I40E_ERR_INVALID_MAC_ADDR;
974 * i40e_init_shared_code - Initialize the shared code
975 * @hw: pointer to hardware structure
977 * This assigns the MAC type and PHY code and inits the NVM.
978 * Does not touch the hardware. This function must be called prior to any
979 * other function in the shared code. The i40e_hw structure should be
980 * memset to 0 prior to calling this function. The following fields in
981 * hw structure should be filled in prior to calling this function:
982 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
983 * subsystem_vendor_id, and revision_id
985 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
987 enum i40e_status_code status = I40E_SUCCESS;
988 u32 port, ari, func_rid;
990 DEBUGFUNC("i40e_init_shared_code");
992 i40e_set_mac_type(hw);
994 switch (hw->mac.type) {
999 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1002 hw->phy.get_link_info = true;
1004 /* Determine port number and PF number*/
1005 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1006 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1007 hw->port = (u8)port;
1008 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1009 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1010 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1012 hw->pf_id = (u8)(func_rid & 0xff);
1014 hw->pf_id = (u8)(func_rid & 0x7);
1016 if (hw->mac.type == I40E_MAC_X722)
1017 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1018 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1019 /* NVMUpdate features structure initialization */
1020 hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1021 hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1022 hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1023 i40e_memset(hw->nvmupd_features.features, 0x0,
1024 I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1025 sizeof(*hw->nvmupd_features.features),
1028 /* No features supported at the moment */
1029 hw->nvmupd_features.features[0] = 0;
1031 status = i40e_init_nvm(hw);
1036 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1037 * @hw: pointer to the hw struct
1038 * @flags: a return indicator of what addresses were added to the addr store
1039 * @addrs: the requestor's mac addr store
1040 * @cmd_details: pointer to command details structure or NULL
1042 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1044 struct i40e_aqc_mac_address_read_data *addrs,
1045 struct i40e_asq_cmd_details *cmd_details)
1047 struct i40e_aq_desc desc;
1048 struct i40e_aqc_mac_address_read *cmd_data =
1049 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1050 enum i40e_status_code status;
1052 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1053 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1055 status = i40e_asq_send_command(hw, &desc, addrs,
1056 sizeof(*addrs), cmd_details);
1057 *flags = LE16_TO_CPU(cmd_data->command_flags);
1063 * i40e_aq_mac_address_write - Change the MAC addresses
1064 * @hw: pointer to the hw struct
1065 * @flags: indicates which MAC to be written
1066 * @mac_addr: address to write
1067 * @cmd_details: pointer to command details structure or NULL
1069 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1070 u16 flags, u8 *mac_addr,
1071 struct i40e_asq_cmd_details *cmd_details)
1073 struct i40e_aq_desc desc;
1074 struct i40e_aqc_mac_address_write *cmd_data =
1075 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1076 enum i40e_status_code status;
1078 i40e_fill_default_direct_cmd_desc(&desc,
1079 i40e_aqc_opc_mac_address_write);
1080 cmd_data->command_flags = CPU_TO_LE16(flags);
1081 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1082 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1083 ((u32)mac_addr[3] << 16) |
1084 ((u32)mac_addr[4] << 8) |
1087 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1093 * i40e_get_mac_addr - get MAC address
1094 * @hw: pointer to the HW structure
1095 * @mac_addr: pointer to MAC address
1097 * Reads the adapter's MAC address from register
1099 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1101 struct i40e_aqc_mac_address_read_data addrs;
1102 enum i40e_status_code status;
1105 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1107 if (flags & I40E_AQC_LAN_ADDR_VALID)
1108 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1109 I40E_NONDMA_TO_NONDMA);
1115 * i40e_get_port_mac_addr - get Port MAC address
1116 * @hw: pointer to the HW structure
1117 * @mac_addr: pointer to Port MAC address
1119 * Reads the adapter's Port MAC address
1121 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1123 struct i40e_aqc_mac_address_read_data addrs;
1124 enum i40e_status_code status;
1127 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1131 if (flags & I40E_AQC_PORT_ADDR_VALID)
1132 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1133 I40E_NONDMA_TO_NONDMA);
1135 status = I40E_ERR_INVALID_MAC_ADDR;
1141 * i40e_pre_tx_queue_cfg - pre tx queue configure
1142 * @hw: pointer to the HW structure
1143 * @queue: target pf queue index
1144 * @enable: state change request
1146 * Handles hw requirement to indicate intention to enable
1147 * or disable target queue.
1149 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1151 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1155 if (abs_queue_idx >= 128) {
1156 reg_block = abs_queue_idx / 128;
1157 abs_queue_idx %= 128;
1160 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1161 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1162 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1165 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1167 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1169 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1173 * i40e_get_san_mac_addr - get SAN MAC address
1174 * @hw: pointer to the HW structure
1175 * @mac_addr: pointer to SAN MAC address
1177 * Reads the adapter's SAN MAC address from NVM
1179 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1182 struct i40e_aqc_mac_address_read_data addrs;
1183 enum i40e_status_code status;
1186 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1190 if (flags & I40E_AQC_SAN_ADDR_VALID)
1191 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1192 I40E_NONDMA_TO_NONDMA);
1194 status = I40E_ERR_INVALID_MAC_ADDR;
1200 * i40e_read_pba_string - Reads part number string from EEPROM
1201 * @hw: pointer to hardware structure
1202 * @pba_num: stores the part number string from the EEPROM
1203 * @pba_num_size: part number string buffer length
1205 * Reads the part number string from the EEPROM.
1207 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1210 enum i40e_status_code status = I40E_SUCCESS;
1216 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1217 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1218 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1222 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1223 if (status != I40E_SUCCESS) {
1224 DEBUGOUT("Failed to read PBA Block pointer.\n");
1228 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1229 if (status != I40E_SUCCESS) {
1230 DEBUGOUT("Failed to read PBA Block size.\n");
1234 /* Subtract one to get PBA word count (PBA Size word is included in
1238 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1239 DEBUGOUT("Buffer to small for PBA data.\n");
1240 return I40E_ERR_PARAM;
1243 for (i = 0; i < pba_size; i++) {
1244 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1245 if (status != I40E_SUCCESS) {
1246 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1250 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1251 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1253 pba_num[(pba_size * 2)] = '\0';
1259 * i40e_get_media_type - Gets media type
1260 * @hw: pointer to the hardware structure
1262 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1264 enum i40e_media_type media;
1266 switch (hw->phy.link_info.phy_type) {
1267 case I40E_PHY_TYPE_10GBASE_SR:
1268 case I40E_PHY_TYPE_10GBASE_LR:
1269 case I40E_PHY_TYPE_1000BASE_SX:
1270 case I40E_PHY_TYPE_1000BASE_LX:
1271 case I40E_PHY_TYPE_40GBASE_SR4:
1272 case I40E_PHY_TYPE_40GBASE_LR4:
1273 case I40E_PHY_TYPE_25GBASE_LR:
1274 case I40E_PHY_TYPE_25GBASE_SR:
1275 media = I40E_MEDIA_TYPE_FIBER;
1277 case I40E_PHY_TYPE_100BASE_TX:
1278 case I40E_PHY_TYPE_1000BASE_T:
1279 case I40E_PHY_TYPE_2_5GBASE_T:
1280 case I40E_PHY_TYPE_5GBASE_T:
1281 case I40E_PHY_TYPE_10GBASE_T:
1282 media = I40E_MEDIA_TYPE_BASET;
1284 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1285 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1286 case I40E_PHY_TYPE_10GBASE_CR1:
1287 case I40E_PHY_TYPE_40GBASE_CR4:
1288 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1289 case I40E_PHY_TYPE_40GBASE_AOC:
1290 case I40E_PHY_TYPE_10GBASE_AOC:
1291 case I40E_PHY_TYPE_25GBASE_CR:
1292 case I40E_PHY_TYPE_25GBASE_AOC:
1293 case I40E_PHY_TYPE_25GBASE_ACC:
1294 media = I40E_MEDIA_TYPE_DA;
1296 case I40E_PHY_TYPE_1000BASE_KX:
1297 case I40E_PHY_TYPE_10GBASE_KX4:
1298 case I40E_PHY_TYPE_10GBASE_KR:
1299 case I40E_PHY_TYPE_40GBASE_KR4:
1300 case I40E_PHY_TYPE_20GBASE_KR2:
1301 case I40E_PHY_TYPE_25GBASE_KR:
1302 media = I40E_MEDIA_TYPE_BACKPLANE;
1304 case I40E_PHY_TYPE_SGMII:
1305 case I40E_PHY_TYPE_XAUI:
1306 case I40E_PHY_TYPE_XFI:
1307 case I40E_PHY_TYPE_XLAUI:
1308 case I40E_PHY_TYPE_XLPPI:
1310 media = I40E_MEDIA_TYPE_UNKNOWN;
1318 * i40e_poll_globr - Poll for Global Reset completion
1319 * @hw: pointer to the hardware structure
1320 * @retry_limit: how many times to retry before failure
1322 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1327 for (cnt = 0; cnt < retry_limit; cnt++) {
1328 reg = rd32(hw, I40E_GLGEN_RSTAT);
1329 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1330 return I40E_SUCCESS;
1331 i40e_msec_delay(100);
1334 DEBUGOUT("Global reset failed.\n");
1335 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1337 return I40E_ERR_RESET_FAILED;
1340 #define I40E_PF_RESET_WAIT_COUNT 200
1342 * i40e_pf_reset - Reset the PF
1343 * @hw: pointer to the hardware structure
1345 * Assuming someone else has triggered a global reset,
1346 * assure the global reset is complete and then reset the PF
1348 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1355 /* Poll for Global Reset steady state in case of recent GRST.
1356 * The grst delay value is in 100ms units, and we'll wait a
1357 * couple counts longer to be sure we don't just miss the end.
1359 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1360 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1361 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1363 grst_del = min(grst_del * 20, 160U);
1365 for (cnt = 0; cnt < grst_del; cnt++) {
1366 reg = rd32(hw, I40E_GLGEN_RSTAT);
1367 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1369 i40e_msec_delay(100);
1371 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1372 DEBUGOUT("Global reset polling failed to complete.\n");
1373 return I40E_ERR_RESET_FAILED;
1376 /* Now Wait for the FW to be ready */
1377 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1378 reg = rd32(hw, I40E_GLNVM_ULD);
1379 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1380 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1381 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1382 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1383 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1386 i40e_msec_delay(10);
1388 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1389 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1390 DEBUGOUT("wait for FW Reset complete timedout\n");
1391 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1392 return I40E_ERR_RESET_FAILED;
1395 /* If there was a Global Reset in progress when we got here,
1396 * we don't need to do the PF Reset
1401 reg = rd32(hw, I40E_PFGEN_CTRL);
1402 wr32(hw, I40E_PFGEN_CTRL,
1403 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1404 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1405 reg = rd32(hw, I40E_PFGEN_CTRL);
1406 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1408 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1409 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1413 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1414 if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1415 return I40E_ERR_RESET_FAILED;
1416 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1417 DEBUGOUT("PF reset polling failed to complete.\n");
1418 return I40E_ERR_RESET_FAILED;
1422 i40e_clear_pxe_mode(hw);
1425 return I40E_SUCCESS;
1429 * i40e_clear_hw - clear out any left over hw state
1430 * @hw: pointer to the hw struct
1432 * Clear queues and interrupts, typically called at init time,
1433 * but after the capabilities have been found so we know how many
1434 * queues and msix vectors have been allocated.
1436 void i40e_clear_hw(struct i40e_hw *hw)
1438 u32 num_queues, base_queue;
1446 /* get number of interrupts, queues, and vfs */
1447 val = rd32(hw, I40E_GLPCI_CNF2);
1448 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1449 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1450 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1451 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1453 val = rd32(hw, I40E_PFLAN_QALLOC);
1454 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1455 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1456 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1457 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1458 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1459 num_queues = (j - base_queue) + 1;
1463 val = rd32(hw, I40E_PF_VT_PFALLOC);
1464 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1465 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1466 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1467 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1468 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1469 num_vfs = (j - i) + 1;
1473 /* stop all the interrupts */
1474 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1475 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1476 for (i = 0; i < num_pf_int - 2; i++)
1477 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1479 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1480 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1481 wr32(hw, I40E_PFINT_LNKLST0, val);
1482 for (i = 0; i < num_pf_int - 2; i++)
1483 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1484 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1485 for (i = 0; i < num_vfs; i++)
1486 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1487 for (i = 0; i < num_vf_int - 2; i++)
1488 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1490 /* warn the HW of the coming Tx disables */
1491 for (i = 0; i < num_queues; i++) {
1492 u32 abs_queue_idx = base_queue + i;
1495 if (abs_queue_idx >= 128) {
1496 reg_block = abs_queue_idx / 128;
1497 abs_queue_idx %= 128;
1500 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1501 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1502 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1503 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1505 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1507 i40e_usec_delay(400);
1509 /* stop all the queues */
1510 for (i = 0; i < num_queues; i++) {
1511 wr32(hw, I40E_QINT_TQCTL(i), 0);
1512 wr32(hw, I40E_QTX_ENA(i), 0);
1513 wr32(hw, I40E_QINT_RQCTL(i), 0);
1514 wr32(hw, I40E_QRX_ENA(i), 0);
1517 /* short wait for all queue disables to settle */
1518 i40e_usec_delay(50);
1522 * i40e_clear_pxe_mode - clear pxe operations mode
1523 * @hw: pointer to the hw struct
1525 * Make sure all PXE mode settings are cleared, including things
1526 * like descriptor fetch/write-back mode.
1528 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1530 if (i40e_check_asq_alive(hw))
1531 i40e_aq_clear_pxe_mode(hw, NULL);
1535 * i40e_led_is_mine - helper to find matching led
1536 * @hw: pointer to the hw struct
1537 * @idx: index into GPIO registers
1539 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1541 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1546 if (!hw->func_caps.led[idx])
1549 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1550 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1551 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1553 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1554 * if it is not our port then ignore
1556 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1563 #define I40E_COMBINED_ACTIVITY 0xA
1564 #define I40E_FILTER_ACTIVITY 0xE
1565 #define I40E_LINK_ACTIVITY 0xC
1566 #define I40E_MAC_ACTIVITY 0xD
1567 #define I40E_LED0 22
1570 * i40e_led_get - return current on/off mode
1571 * @hw: pointer to the hw struct
1573 * The value returned is the 'mode' field as defined in the
1574 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1575 * values are variations of possible behaviors relating to
1576 * blink, link, and wire.
1578 u32 i40e_led_get(struct i40e_hw *hw)
1580 u32 current_mode = 0;
1584 /* as per the documentation GPIO 22-29 are the LED
1585 * GPIO pins named LED0..LED7
1587 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1588 u32 gpio_val = i40e_led_is_mine(hw, i);
1593 /* ignore gpio LED src mode entries related to the activity
1596 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1597 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1598 switch (current_mode) {
1599 case I40E_COMBINED_ACTIVITY:
1600 case I40E_FILTER_ACTIVITY:
1601 case I40E_MAC_ACTIVITY:
1602 case I40E_LINK_ACTIVITY:
1608 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1609 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1617 * i40e_led_set - set new on/off mode
1618 * @hw: pointer to the hw struct
1619 * @mode: 0=off, 0xf=on (else see manual for mode details)
1620 * @blink: true if the LED should blink when on, false if steady
1622 * if this function is used to turn on the blink it should
1623 * be used to disable the blink when restoring the original state.
1625 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1627 u32 current_mode = 0;
1630 if (mode & 0xfffffff0)
1631 DEBUGOUT1("invalid mode passed in %X\n", mode);
1633 /* as per the documentation GPIO 22-29 are the LED
1634 * GPIO pins named LED0..LED7
1636 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1637 u32 gpio_val = i40e_led_is_mine(hw, i);
1642 /* ignore gpio LED src mode entries related to the activity
1645 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1646 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1647 switch (current_mode) {
1648 case I40E_COMBINED_ACTIVITY:
1649 case I40E_FILTER_ACTIVITY:
1650 case I40E_MAC_ACTIVITY:
1651 case I40E_LINK_ACTIVITY:
1657 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1658 /* this & is a bit of paranoia, but serves as a range check */
1659 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1660 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1663 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1665 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1667 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1672 /* Admin command wrappers */
1675 * i40e_aq_get_phy_capabilities
1676 * @hw: pointer to the hw struct
1677 * @abilities: structure for PHY capabilities to be filled
1678 * @qualified_modules: report Qualified Modules
1679 * @report_init: report init capabilities (active are default)
1680 * @cmd_details: pointer to command details structure or NULL
1682 * Returns the various PHY abilities supported on the Port.
1684 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1685 bool qualified_modules, bool report_init,
1686 struct i40e_aq_get_phy_abilities_resp *abilities,
1687 struct i40e_asq_cmd_details *cmd_details)
1689 struct i40e_aq_desc desc;
1690 enum i40e_status_code status;
1691 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1692 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1695 return I40E_ERR_PARAM;
1698 i40e_fill_default_direct_cmd_desc(&desc,
1699 i40e_aqc_opc_get_phy_abilities);
1701 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1702 if (abilities_size > I40E_AQ_LARGE_BUF)
1703 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1705 if (qualified_modules)
1706 desc.params.external.param0 |=
1707 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1710 desc.params.external.param0 |=
1711 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1713 status = i40e_asq_send_command(hw, &desc, abilities,
1714 abilities_size, cmd_details);
1716 if (status != I40E_SUCCESS)
1719 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1720 status = I40E_ERR_UNKNOWN_PHY;
1722 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1725 status = I40E_ERR_TIMEOUT;
1727 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1728 (total_delay < max_delay));
1730 if (status != I40E_SUCCESS)
1734 if (hw->mac.type == I40E_MAC_XL710 &&
1735 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1736 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1737 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1739 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1740 hw->phy.phy_types |=
1741 ((u64)abilities->phy_type_ext << 32);
1749 * i40e_aq_set_phy_config
1750 * @hw: pointer to the hw struct
1751 * @config: structure with PHY configuration to be set
1752 * @cmd_details: pointer to command details structure or NULL
1754 * Set the various PHY configuration parameters
1755 * supported on the Port.One or more of the Set PHY config parameters may be
1756 * ignored in an MFP mode as the PF may not have the privilege to set some
1757 * of the PHY Config parameters. This status will be indicated by the
1760 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1761 struct i40e_aq_set_phy_config *config,
1762 struct i40e_asq_cmd_details *cmd_details)
1764 struct i40e_aq_desc desc;
1765 struct i40e_aq_set_phy_config *cmd =
1766 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1767 enum i40e_status_code status;
1770 return I40E_ERR_PARAM;
1772 i40e_fill_default_direct_cmd_desc(&desc,
1773 i40e_aqc_opc_set_phy_config);
1777 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1784 * @hw: pointer to the hw struct
1785 * @aq_failures: buffer to return AdminQ failure information
1786 * @atomic_restart: whether to enable atomic link restart
1788 * Set the requested flow control mode using set_phy_config.
1790 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1791 bool atomic_restart)
1793 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1794 struct i40e_aq_get_phy_abilities_resp abilities;
1795 struct i40e_aq_set_phy_config config;
1796 enum i40e_status_code status;
1797 u8 pause_mask = 0x0;
1803 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1804 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1806 case I40E_FC_RX_PAUSE:
1807 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1809 case I40E_FC_TX_PAUSE:
1810 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1816 /* Get the current phy config */
1817 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1820 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1824 memset(&config, 0, sizeof(config));
1825 /* clear the old pause settings */
1826 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1827 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1828 /* set the new abilities */
1829 config.abilities |= pause_mask;
1830 /* If the abilities have changed, then set the new config */
1831 if (config.abilities != abilities.abilities) {
1832 /* Auto restart link so settings take effect */
1834 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1835 /* Copy over all the old settings */
1836 config.phy_type = abilities.phy_type;
1837 config.phy_type_ext = abilities.phy_type_ext;
1838 config.link_speed = abilities.link_speed;
1839 config.eee_capability = abilities.eee_capability;
1840 config.eeer = abilities.eeer_val;
1841 config.low_power_ctrl = abilities.d3_lpan;
1842 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1843 I40E_AQ_PHY_FEC_CONFIG_MASK;
1844 status = i40e_aq_set_phy_config(hw, &config, NULL);
1847 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1849 /* Update the link info */
1850 status = i40e_update_link_info(hw);
1852 /* Wait a little bit (on 40G cards it sometimes takes a really
1853 * long time for link to come back from the atomic reset)
1856 i40e_msec_delay(1000);
1857 status = i40e_update_link_info(hw);
1860 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1866 * i40e_aq_set_mac_config
1867 * @hw: pointer to the hw struct
1868 * @max_frame_size: Maximum Frame Size to be supported by the port
1869 * @crc_en: Tell HW to append a CRC to outgoing frames
1870 * @pacing: Pacing configurations
1871 * @cmd_details: pointer to command details structure or NULL
1873 * Configure MAC settings for frame size, jumbo frame support and the
1874 * addition of a CRC by the hardware.
1876 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1878 bool crc_en, u16 pacing,
1879 struct i40e_asq_cmd_details *cmd_details)
1881 struct i40e_aq_desc desc;
1882 struct i40e_aq_set_mac_config *cmd =
1883 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1884 enum i40e_status_code status;
1886 if (max_frame_size == 0)
1887 return I40E_ERR_PARAM;
1889 i40e_fill_default_direct_cmd_desc(&desc,
1890 i40e_aqc_opc_set_mac_config);
1892 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1893 cmd->params = ((u8)pacing & 0x0F) << 3;
1895 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1897 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD 0x7FFF
1898 cmd->fc_refresh_threshold =
1899 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1901 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1907 * i40e_aq_clear_pxe_mode
1908 * @hw: pointer to the hw struct
1909 * @cmd_details: pointer to command details structure or NULL
1911 * Tell the firmware that the driver is taking over from PXE
1913 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1914 struct i40e_asq_cmd_details *cmd_details)
1916 enum i40e_status_code status;
1917 struct i40e_aq_desc desc;
1918 struct i40e_aqc_clear_pxe *cmd =
1919 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1921 i40e_fill_default_direct_cmd_desc(&desc,
1922 i40e_aqc_opc_clear_pxe_mode);
1926 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1928 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1934 * i40e_aq_set_link_restart_an
1935 * @hw: pointer to the hw struct
1936 * @enable_link: if true: enable link, if false: disable link
1937 * @cmd_details: pointer to command details structure or NULL
1939 * Sets up the link and restarts the Auto-Negotiation over the link.
1941 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1942 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1944 struct i40e_aq_desc desc;
1945 struct i40e_aqc_set_link_restart_an *cmd =
1946 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1947 enum i40e_status_code status;
1949 i40e_fill_default_direct_cmd_desc(&desc,
1950 i40e_aqc_opc_set_link_restart_an);
1952 cmd->command = I40E_AQ_PHY_RESTART_AN;
1954 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1956 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1958 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1964 * i40e_aq_get_link_info
1965 * @hw: pointer to the hw struct
1966 * @enable_lse: enable/disable LinkStatusEvent reporting
1967 * @link: pointer to link status structure - optional
1968 * @cmd_details: pointer to command details structure or NULL
1970 * Returns the link status of the adapter.
1972 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1973 bool enable_lse, struct i40e_link_status *link,
1974 struct i40e_asq_cmd_details *cmd_details)
1976 struct i40e_aq_desc desc;
1977 struct i40e_aqc_get_link_status *resp =
1978 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1979 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1980 enum i40e_status_code status;
1981 bool tx_pause, rx_pause;
1984 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1987 command_flags = I40E_AQ_LSE_ENABLE;
1989 command_flags = I40E_AQ_LSE_DISABLE;
1990 resp->command_flags = CPU_TO_LE16(command_flags);
1992 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1994 if (status != I40E_SUCCESS)
1995 goto aq_get_link_info_exit;
1997 /* save off old link status information */
1998 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1999 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
2001 /* update link status */
2002 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2003 hw->phy.media_type = i40e_get_media_type(hw);
2004 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2005 hw_link_info->link_info = resp->link_info;
2006 hw_link_info->an_info = resp->an_info;
2007 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2008 I40E_AQ_CONFIG_FEC_RS_ENA);
2009 hw_link_info->ext_info = resp->ext_info;
2010 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2011 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2012 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2014 /* update fc info */
2015 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2016 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2017 if (tx_pause & rx_pause)
2018 hw->fc.current_mode = I40E_FC_FULL;
2020 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2022 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2024 hw->fc.current_mode = I40E_FC_NONE;
2026 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2027 hw_link_info->crc_enable = true;
2029 hw_link_info->crc_enable = false;
2031 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2032 hw_link_info->lse_enable = true;
2034 hw_link_info->lse_enable = false;
2036 if ((hw->mac.type == I40E_MAC_XL710) &&
2037 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2038 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2039 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2041 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2042 hw->aq.api_min_ver >= 7) {
2045 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2046 I40E_NONDMA_TO_NONDMA);
2047 hw->phy.phy_types = LE32_TO_CPU(tmp);
2048 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2051 /* save link status information */
2053 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2054 I40E_NONDMA_TO_NONDMA);
2056 /* flag cleared so helper functions don't call AQ again */
2057 hw->phy.get_link_info = false;
2059 aq_get_link_info_exit:
2064 * i40e_aq_set_phy_int_mask
2065 * @hw: pointer to the hw struct
2066 * @mask: interrupt mask to be set
2067 * @cmd_details: pointer to command details structure or NULL
2069 * Set link interrupt mask.
2071 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2073 struct i40e_asq_cmd_details *cmd_details)
2075 struct i40e_aq_desc desc;
2076 struct i40e_aqc_set_phy_int_mask *cmd =
2077 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2078 enum i40e_status_code status;
2080 i40e_fill_default_direct_cmd_desc(&desc,
2081 i40e_aqc_opc_set_phy_int_mask);
2083 cmd->event_mask = CPU_TO_LE16(mask);
2085 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2091 * i40e_aq_get_local_advt_reg
2092 * @hw: pointer to the hw struct
2093 * @advt_reg: local AN advertisement register value
2094 * @cmd_details: pointer to command details structure or NULL
2096 * Get the Local AN advertisement register value.
2098 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2100 struct i40e_asq_cmd_details *cmd_details)
2102 struct i40e_aq_desc desc;
2103 struct i40e_aqc_an_advt_reg *resp =
2104 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2105 enum i40e_status_code status;
2107 i40e_fill_default_direct_cmd_desc(&desc,
2108 i40e_aqc_opc_get_local_advt_reg);
2110 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2112 if (status != I40E_SUCCESS)
2113 goto aq_get_local_advt_reg_exit;
2115 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2116 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2118 aq_get_local_advt_reg_exit:
2123 * i40e_aq_set_local_advt_reg
2124 * @hw: pointer to the hw struct
2125 * @advt_reg: local AN advertisement register value
2126 * @cmd_details: pointer to command details structure or NULL
2128 * Get the Local AN advertisement register value.
2130 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2132 struct i40e_asq_cmd_details *cmd_details)
2134 struct i40e_aq_desc desc;
2135 struct i40e_aqc_an_advt_reg *cmd =
2136 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2137 enum i40e_status_code status;
2139 i40e_fill_default_direct_cmd_desc(&desc,
2140 i40e_aqc_opc_get_local_advt_reg);
2142 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2143 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2145 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2151 * i40e_aq_get_partner_advt
2152 * @hw: pointer to the hw struct
2153 * @advt_reg: AN partner advertisement register value
2154 * @cmd_details: pointer to command details structure or NULL
2156 * Get the link partner AN advertisement register value.
2158 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2160 struct i40e_asq_cmd_details *cmd_details)
2162 struct i40e_aq_desc desc;
2163 struct i40e_aqc_an_advt_reg *resp =
2164 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2165 enum i40e_status_code status;
2167 i40e_fill_default_direct_cmd_desc(&desc,
2168 i40e_aqc_opc_get_partner_advt);
2170 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2172 if (status != I40E_SUCCESS)
2173 goto aq_get_partner_advt_exit;
2175 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2176 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2178 aq_get_partner_advt_exit:
2183 * i40e_aq_set_lb_modes
2184 * @hw: pointer to the hw struct
2185 * @lb_modes: loopback mode to be set
2186 * @cmd_details: pointer to command details structure or NULL
2188 * Sets loopback modes.
2190 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2192 struct i40e_asq_cmd_details *cmd_details)
2194 struct i40e_aq_desc desc;
2195 struct i40e_aqc_set_lb_mode *cmd =
2196 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2197 enum i40e_status_code status;
2199 i40e_fill_default_direct_cmd_desc(&desc,
2200 i40e_aqc_opc_set_lb_modes);
2202 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2204 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2210 * i40e_aq_set_phy_debug
2211 * @hw: pointer to the hw struct
2212 * @cmd_flags: debug command flags
2213 * @cmd_details: pointer to command details structure or NULL
2215 * Reset the external PHY.
2217 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2218 struct i40e_asq_cmd_details *cmd_details)
2220 struct i40e_aq_desc desc;
2221 struct i40e_aqc_set_phy_debug *cmd =
2222 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2223 enum i40e_status_code status;
2225 i40e_fill_default_direct_cmd_desc(&desc,
2226 i40e_aqc_opc_set_phy_debug);
2228 cmd->command_flags = cmd_flags;
2230 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2237 * @hw: pointer to the hw struct
2238 * @vsi_ctx: pointer to a vsi context struct
2239 * @cmd_details: pointer to command details structure or NULL
2241 * Add a VSI context to the hardware.
2243 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2244 struct i40e_vsi_context *vsi_ctx,
2245 struct i40e_asq_cmd_details *cmd_details)
2247 struct i40e_aq_desc desc;
2248 struct i40e_aqc_add_get_update_vsi *cmd =
2249 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2250 struct i40e_aqc_add_get_update_vsi_completion *resp =
2251 (struct i40e_aqc_add_get_update_vsi_completion *)
2253 enum i40e_status_code status;
2255 i40e_fill_default_direct_cmd_desc(&desc,
2256 i40e_aqc_opc_add_vsi);
2258 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2259 cmd->connection_type = vsi_ctx->connection_type;
2260 cmd->vf_id = vsi_ctx->vf_num;
2261 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2263 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2265 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2266 sizeof(vsi_ctx->info), cmd_details);
2268 if (status != I40E_SUCCESS)
2269 goto aq_add_vsi_exit;
2271 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2272 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2273 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2274 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2281 * i40e_aq_set_default_vsi
2282 * @hw: pointer to the hw struct
2284 * @cmd_details: pointer to command details structure or NULL
2286 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2288 struct i40e_asq_cmd_details *cmd_details)
2290 struct i40e_aq_desc desc;
2291 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2292 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2294 enum i40e_status_code status;
2296 i40e_fill_default_direct_cmd_desc(&desc,
2297 i40e_aqc_opc_set_vsi_promiscuous_modes);
2299 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2300 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2301 cmd->seid = CPU_TO_LE16(seid);
2303 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2309 * i40e_aq_clear_default_vsi
2310 * @hw: pointer to the hw struct
2312 * @cmd_details: pointer to command details structure or NULL
2314 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2316 struct i40e_asq_cmd_details *cmd_details)
2318 struct i40e_aq_desc desc;
2319 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2320 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2322 enum i40e_status_code status;
2324 i40e_fill_default_direct_cmd_desc(&desc,
2325 i40e_aqc_opc_set_vsi_promiscuous_modes);
2327 cmd->promiscuous_flags = CPU_TO_LE16(0);
2328 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2329 cmd->seid = CPU_TO_LE16(seid);
2331 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2337 * i40e_aq_set_vsi_unicast_promiscuous
2338 * @hw: pointer to the hw struct
2340 * @set: set unicast promiscuous enable/disable
2341 * @cmd_details: pointer to command details structure or NULL
2342 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2344 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2346 struct i40e_asq_cmd_details *cmd_details,
2347 bool rx_only_promisc)
2349 struct i40e_aq_desc desc;
2350 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2351 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2352 enum i40e_status_code status;
2355 i40e_fill_default_direct_cmd_desc(&desc,
2356 i40e_aqc_opc_set_vsi_promiscuous_modes);
2359 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2360 if (rx_only_promisc &&
2361 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2362 (hw->aq.api_maj_ver > 1)))
2363 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2366 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2368 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2369 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2370 (hw->aq.api_maj_ver > 1))
2371 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2373 cmd->seid = CPU_TO_LE16(seid);
2374 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2380 * i40e_aq_set_vsi_multicast_promiscuous
2381 * @hw: pointer to the hw struct
2383 * @set: set multicast promiscuous enable/disable
2384 * @cmd_details: pointer to command details structure or NULL
2386 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2387 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2389 struct i40e_aq_desc desc;
2390 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2391 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2392 enum i40e_status_code status;
2395 i40e_fill_default_direct_cmd_desc(&desc,
2396 i40e_aqc_opc_set_vsi_promiscuous_modes);
2399 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2401 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2403 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2405 cmd->seid = CPU_TO_LE16(seid);
2406 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2412 * i40e_aq_set_vsi_full_promiscuous
2413 * @hw: pointer to the hw struct
2415 * @set: set promiscuous enable/disable
2416 * @cmd_details: pointer to command details structure or NULL
2418 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2420 struct i40e_asq_cmd_details *cmd_details)
2422 struct i40e_aq_desc desc;
2423 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2424 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2425 enum i40e_status_code status;
2428 i40e_fill_default_direct_cmd_desc(&desc,
2429 i40e_aqc_opc_set_vsi_promiscuous_modes);
2432 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST |
2433 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2434 I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2436 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2438 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST |
2439 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2440 I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2442 cmd->seid = CPU_TO_LE16(seid);
2443 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2449 * i40e_aq_set_vsi_mc_promisc_on_vlan
2450 * @hw: pointer to the hw struct
2452 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2453 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2454 * @cmd_details: pointer to command details structure or NULL
2456 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2457 u16 seid, bool enable, u16 vid,
2458 struct i40e_asq_cmd_details *cmd_details)
2460 struct i40e_aq_desc desc;
2461 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2462 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2463 enum i40e_status_code status;
2466 i40e_fill_default_direct_cmd_desc(&desc,
2467 i40e_aqc_opc_set_vsi_promiscuous_modes);
2470 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2472 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2473 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2474 cmd->seid = CPU_TO_LE16(seid);
2475 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2477 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2483 * i40e_aq_set_vsi_uc_promisc_on_vlan
2484 * @hw: pointer to the hw struct
2486 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2487 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2488 * @cmd_details: pointer to command details structure or NULL
2490 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2491 u16 seid, bool enable, u16 vid,
2492 struct i40e_asq_cmd_details *cmd_details)
2494 struct i40e_aq_desc desc;
2495 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2496 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2497 enum i40e_status_code status;
2500 i40e_fill_default_direct_cmd_desc(&desc,
2501 i40e_aqc_opc_set_vsi_promiscuous_modes);
2504 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2506 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2507 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2508 cmd->seid = CPU_TO_LE16(seid);
2509 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2511 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2517 * i40e_aq_set_vsi_bc_promisc_on_vlan
2518 * @hw: pointer to the hw struct
2520 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2521 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2522 * @cmd_details: pointer to command details structure or NULL
2524 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2525 u16 seid, bool enable, u16 vid,
2526 struct i40e_asq_cmd_details *cmd_details)
2528 struct i40e_aq_desc desc;
2529 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2530 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2531 enum i40e_status_code status;
2534 i40e_fill_default_direct_cmd_desc(&desc,
2535 i40e_aqc_opc_set_vsi_promiscuous_modes);
2538 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2540 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2541 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2542 cmd->seid = CPU_TO_LE16(seid);
2543 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2545 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2551 * i40e_aq_set_vsi_broadcast
2552 * @hw: pointer to the hw struct
2554 * @set_filter: true to set filter, false to clear filter
2555 * @cmd_details: pointer to command details structure or NULL
2557 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2559 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2560 u16 seid, bool set_filter,
2561 struct i40e_asq_cmd_details *cmd_details)
2563 struct i40e_aq_desc desc;
2564 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2565 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2566 enum i40e_status_code status;
2568 i40e_fill_default_direct_cmd_desc(&desc,
2569 i40e_aqc_opc_set_vsi_promiscuous_modes);
2572 cmd->promiscuous_flags
2573 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2575 cmd->promiscuous_flags
2576 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2578 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2579 cmd->seid = CPU_TO_LE16(seid);
2580 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2586 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2587 * @hw: pointer to the hw struct
2589 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2590 * @cmd_details: pointer to command details structure or NULL
2592 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2593 u16 seid, bool enable,
2594 struct i40e_asq_cmd_details *cmd_details)
2596 struct i40e_aq_desc desc;
2597 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2598 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2599 enum i40e_status_code status;
2602 i40e_fill_default_direct_cmd_desc(&desc,
2603 i40e_aqc_opc_set_vsi_promiscuous_modes);
2605 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2607 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2608 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2609 cmd->seid = CPU_TO_LE16(seid);
2611 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2617 * i40e_get_vsi_params - get VSI configuration info
2618 * @hw: pointer to the hw struct
2619 * @vsi_ctx: pointer to a vsi context struct
2620 * @cmd_details: pointer to command details structure or NULL
2622 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2623 struct i40e_vsi_context *vsi_ctx,
2624 struct i40e_asq_cmd_details *cmd_details)
2626 struct i40e_aq_desc desc;
2627 struct i40e_aqc_add_get_update_vsi *cmd =
2628 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2629 struct i40e_aqc_add_get_update_vsi_completion *resp =
2630 (struct i40e_aqc_add_get_update_vsi_completion *)
2632 enum i40e_status_code status;
2634 UNREFERENCED_1PARAMETER(cmd_details);
2635 i40e_fill_default_direct_cmd_desc(&desc,
2636 i40e_aqc_opc_get_vsi_parameters);
2638 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2640 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2642 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2643 sizeof(vsi_ctx->info), NULL);
2645 if (status != I40E_SUCCESS)
2646 goto aq_get_vsi_params_exit;
2648 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2649 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2650 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2651 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2653 aq_get_vsi_params_exit:
2658 * i40e_aq_update_vsi_params
2659 * @hw: pointer to the hw struct
2660 * @vsi_ctx: pointer to a vsi context struct
2661 * @cmd_details: pointer to command details structure or NULL
2663 * Update a VSI context.
2665 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2666 struct i40e_vsi_context *vsi_ctx,
2667 struct i40e_asq_cmd_details *cmd_details)
2669 struct i40e_aq_desc desc;
2670 struct i40e_aqc_add_get_update_vsi *cmd =
2671 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2672 struct i40e_aqc_add_get_update_vsi_completion *resp =
2673 (struct i40e_aqc_add_get_update_vsi_completion *)
2675 enum i40e_status_code status;
2677 i40e_fill_default_direct_cmd_desc(&desc,
2678 i40e_aqc_opc_update_vsi_parameters);
2679 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2681 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2683 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2684 sizeof(vsi_ctx->info), cmd_details);
2686 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2687 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2693 * i40e_aq_get_switch_config
2694 * @hw: pointer to the hardware structure
2695 * @buf: pointer to the result buffer
2696 * @buf_size: length of input buffer
2697 * @start_seid: seid to start for the report, 0 == beginning
2698 * @cmd_details: pointer to command details structure or NULL
2700 * Fill the buf with switch configuration returned from AdminQ command
2702 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2703 struct i40e_aqc_get_switch_config_resp *buf,
2704 u16 buf_size, u16 *start_seid,
2705 struct i40e_asq_cmd_details *cmd_details)
2707 struct i40e_aq_desc desc;
2708 struct i40e_aqc_switch_seid *scfg =
2709 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2710 enum i40e_status_code status;
2712 i40e_fill_default_direct_cmd_desc(&desc,
2713 i40e_aqc_opc_get_switch_config);
2714 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2715 if (buf_size > I40E_AQ_LARGE_BUF)
2716 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2717 scfg->seid = CPU_TO_LE16(*start_seid);
2719 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2720 *start_seid = LE16_TO_CPU(scfg->seid);
2726 * i40e_aq_set_switch_config
2727 * @hw: pointer to the hardware structure
2728 * @flags: bit flag values to set
2729 * @mode: cloud filter mode
2730 * @valid_flags: which bit flags to set
2731 * @cmd_details: pointer to command details structure or NULL
2733 * Set switch configuration bits
2735 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2736 u16 flags, u16 valid_flags, u8 mode,
2737 struct i40e_asq_cmd_details *cmd_details)
2739 struct i40e_aq_desc desc;
2740 struct i40e_aqc_set_switch_config *scfg =
2741 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2742 enum i40e_status_code status;
2744 i40e_fill_default_direct_cmd_desc(&desc,
2745 i40e_aqc_opc_set_switch_config);
2746 scfg->flags = CPU_TO_LE16(flags);
2747 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2749 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2750 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2751 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2752 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2754 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2760 * i40e_aq_get_firmware_version
2761 * @hw: pointer to the hw struct
2762 * @fw_major_version: firmware major version
2763 * @fw_minor_version: firmware minor version
2764 * @fw_build: firmware build number
2765 * @api_major_version: major queue version
2766 * @api_minor_version: minor queue version
2767 * @cmd_details: pointer to command details structure or NULL
2769 * Get the firmware version from the admin queue commands
2771 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2772 u16 *fw_major_version, u16 *fw_minor_version,
2774 u16 *api_major_version, u16 *api_minor_version,
2775 struct i40e_asq_cmd_details *cmd_details)
2777 struct i40e_aq_desc desc;
2778 struct i40e_aqc_get_version *resp =
2779 (struct i40e_aqc_get_version *)&desc.params.raw;
2780 enum i40e_status_code status;
2782 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2784 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2786 if (status == I40E_SUCCESS) {
2787 if (fw_major_version != NULL)
2788 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2789 if (fw_minor_version != NULL)
2790 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2791 if (fw_build != NULL)
2792 *fw_build = LE32_TO_CPU(resp->fw_build);
2793 if (api_major_version != NULL)
2794 *api_major_version = LE16_TO_CPU(resp->api_major);
2795 if (api_minor_version != NULL)
2796 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2798 /* A workaround to fix the API version in SW */
2799 if (api_major_version && api_minor_version &&
2800 fw_major_version && fw_minor_version &&
2801 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2802 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2803 (*fw_major_version > 4)))
2804 *api_minor_version = 2;
2811 * i40e_aq_send_driver_version
2812 * @hw: pointer to the hw struct
2813 * @dv: driver's major, minor version
2814 * @cmd_details: pointer to command details structure or NULL
2816 * Send the driver version to the firmware
2818 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2819 struct i40e_driver_version *dv,
2820 struct i40e_asq_cmd_details *cmd_details)
2822 struct i40e_aq_desc desc;
2823 struct i40e_aqc_driver_version *cmd =
2824 (struct i40e_aqc_driver_version *)&desc.params.raw;
2825 enum i40e_status_code status;
2829 return I40E_ERR_PARAM;
2831 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2833 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2834 cmd->driver_major_ver = dv->major_version;
2835 cmd->driver_minor_ver = dv->minor_version;
2836 cmd->driver_build_ver = dv->build_version;
2837 cmd->driver_subbuild_ver = dv->subbuild_version;
2840 while (len < sizeof(dv->driver_string) &&
2841 (dv->driver_string[len] < 0x80) &&
2842 dv->driver_string[len])
2844 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2851 * i40e_get_link_status - get status of the HW network link
2852 * @hw: pointer to the hw struct
2853 * @link_up: pointer to bool (true/false = linkup/linkdown)
2855 * Variable link_up true if link is up, false if link is down.
2856 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2858 * Side effect: LinkStatusEvent reporting becomes enabled
2860 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2862 enum i40e_status_code status = I40E_SUCCESS;
2864 if (hw->phy.get_link_info) {
2865 status = i40e_update_link_info(hw);
2867 if (status != I40E_SUCCESS)
2868 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2872 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2878 * i40e_updatelink_status - update status of the HW network link
2879 * @hw: pointer to the hw struct
2881 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2883 struct i40e_aq_get_phy_abilities_resp abilities;
2884 enum i40e_status_code status = I40E_SUCCESS;
2886 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2890 /* extra checking needed to ensure link info to user is timely */
2891 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2892 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2893 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2894 status = i40e_aq_get_phy_capabilities(hw, false, false,
2899 hw->phy.link_info.req_fec_info =
2900 abilities.fec_cfg_curr_mod_ext_info &
2901 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2903 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2904 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2911 * i40e_get_link_speed
2912 * @hw: pointer to the hw struct
2914 * Returns the link speed of the adapter.
2916 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2918 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2919 enum i40e_status_code status = I40E_SUCCESS;
2921 if (hw->phy.get_link_info) {
2922 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2924 if (status != I40E_SUCCESS)
2925 goto i40e_link_speed_exit;
2928 speed = hw->phy.link_info.link_speed;
2930 i40e_link_speed_exit:
2935 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2936 * @hw: pointer to the hw struct
2937 * @uplink_seid: the MAC or other gizmo SEID
2938 * @downlink_seid: the VSI SEID
2939 * @enabled_tc: bitmap of TCs to be enabled
2940 * @default_port: true for default port VSI, false for control port
2941 * @veb_seid: pointer to where to put the resulting VEB SEID
2942 * @enable_stats: true to turn on VEB stats
2943 * @cmd_details: pointer to command details structure or NULL
2945 * This asks the FW to add a VEB between the uplink and downlink
2946 * elements. If the uplink SEID is 0, this will be a floating VEB.
2948 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2949 u16 downlink_seid, u8 enabled_tc,
2950 bool default_port, u16 *veb_seid,
2952 struct i40e_asq_cmd_details *cmd_details)
2954 struct i40e_aq_desc desc;
2955 struct i40e_aqc_add_veb *cmd =
2956 (struct i40e_aqc_add_veb *)&desc.params.raw;
2957 struct i40e_aqc_add_veb_completion *resp =
2958 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2959 enum i40e_status_code status;
2962 /* SEIDs need to either both be set or both be 0 for floating VEB */
2963 if (!!uplink_seid != !!downlink_seid)
2964 return I40E_ERR_PARAM;
2966 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2968 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2969 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2970 cmd->enable_tcs = enabled_tc;
2972 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2974 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2976 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2978 /* reverse logic here: set the bitflag to disable the stats */
2980 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2982 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2984 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2986 if (!status && veb_seid)
2987 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2993 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2994 * @hw: pointer to the hw struct
2995 * @veb_seid: the SEID of the VEB to query
2996 * @switch_id: the uplink switch id
2997 * @floating: set to true if the VEB is floating
2998 * @statistic_index: index of the stats counter block for this VEB
2999 * @vebs_used: number of VEB's used by function
3000 * @vebs_free: total VEB's not reserved by any function
3001 * @cmd_details: pointer to command details structure or NULL
3003 * This retrieves the parameters for a particular VEB, specified by
3004 * uplink_seid, and returns them to the caller.
3006 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
3007 u16 veb_seid, u16 *switch_id,
3008 bool *floating, u16 *statistic_index,
3009 u16 *vebs_used, u16 *vebs_free,
3010 struct i40e_asq_cmd_details *cmd_details)
3012 struct i40e_aq_desc desc;
3013 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3014 (struct i40e_aqc_get_veb_parameters_completion *)
3016 enum i40e_status_code status;
3019 return I40E_ERR_PARAM;
3021 i40e_fill_default_direct_cmd_desc(&desc,
3022 i40e_aqc_opc_get_veb_parameters);
3023 cmd_resp->seid = CPU_TO_LE16(veb_seid);
3025 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3030 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3031 if (statistic_index)
3032 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3034 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3036 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3038 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3040 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3051 * i40e_aq_add_macvlan
3052 * @hw: pointer to the hw struct
3053 * @seid: VSI for the mac address
3054 * @mv_list: list of macvlans to be added
3055 * @count: length of the list
3056 * @cmd_details: pointer to command details structure or NULL
3058 * Add MAC/VLAN addresses to the HW filtering
3060 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3061 struct i40e_aqc_add_macvlan_element_data *mv_list,
3062 u16 count, struct i40e_asq_cmd_details *cmd_details)
3064 struct i40e_aq_desc desc;
3065 struct i40e_aqc_macvlan *cmd =
3066 (struct i40e_aqc_macvlan *)&desc.params.raw;
3067 enum i40e_status_code status;
3071 if (count == 0 || !mv_list || !hw)
3072 return I40E_ERR_PARAM;
3074 buf_size = count * sizeof(*mv_list);
3076 /* prep the rest of the request */
3077 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3078 cmd->num_addresses = CPU_TO_LE16(count);
3079 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3083 for (i = 0; i < count; i++)
3084 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3086 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3088 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3089 if (buf_size > I40E_AQ_LARGE_BUF)
3090 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3092 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3099 * i40e_aq_remove_macvlan
3100 * @hw: pointer to the hw struct
3101 * @seid: VSI for the mac address
3102 * @mv_list: list of macvlans to be removed
3103 * @count: length of the list
3104 * @cmd_details: pointer to command details structure or NULL
3106 * Remove MAC/VLAN addresses from the HW filtering
3108 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3109 struct i40e_aqc_remove_macvlan_element_data *mv_list,
3110 u16 count, struct i40e_asq_cmd_details *cmd_details)
3112 struct i40e_aq_desc desc;
3113 struct i40e_aqc_macvlan *cmd =
3114 (struct i40e_aqc_macvlan *)&desc.params.raw;
3115 enum i40e_status_code status;
3118 if (count == 0 || !mv_list || !hw)
3119 return I40E_ERR_PARAM;
3121 buf_size = count * sizeof(*mv_list);
3123 /* prep the rest of the request */
3124 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3125 cmd->num_addresses = CPU_TO_LE16(count);
3126 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3130 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3131 if (buf_size > I40E_AQ_LARGE_BUF)
3132 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3134 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3141 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3142 * @hw: pointer to the hw struct
3143 * @opcode: AQ opcode for add or delete mirror rule
3144 * @sw_seid: Switch SEID (to which rule refers)
3145 * @rule_type: Rule Type (ingress/egress/VLAN)
3146 * @id: Destination VSI SEID or Rule ID
3147 * @count: length of the list
3148 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3149 * @cmd_details: pointer to command details structure or NULL
3150 * @rule_id: Rule ID returned from FW
3151 * @rules_used: Number of rules used in internal switch
3152 * @rules_free: Number of rules free in internal switch
3154 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3155 * VEBs/VEPA elements only
3157 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3158 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3159 u16 count, __le16 *mr_list,
3160 struct i40e_asq_cmd_details *cmd_details,
3161 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3163 struct i40e_aq_desc desc;
3164 struct i40e_aqc_add_delete_mirror_rule *cmd =
3165 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3166 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3167 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3168 enum i40e_status_code status;
3171 buf_size = count * sizeof(*mr_list);
3173 /* prep the rest of the request */
3174 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3175 cmd->seid = CPU_TO_LE16(sw_seid);
3176 cmd->rule_type = CPU_TO_LE16(rule_type &
3177 I40E_AQC_MIRROR_RULE_TYPE_MASK);
3178 cmd->num_entries = CPU_TO_LE16(count);
3179 /* Dest VSI for add, rule_id for delete */
3180 cmd->destination = CPU_TO_LE16(id);
3182 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3184 if (buf_size > I40E_AQ_LARGE_BUF)
3185 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3188 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3190 if (status == I40E_SUCCESS ||
3191 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3193 *rule_id = LE16_TO_CPU(resp->rule_id);
3195 *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3197 *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3203 * i40e_aq_add_mirrorrule - add a mirror rule
3204 * @hw: pointer to the hw struct
3205 * @sw_seid: Switch SEID (to which rule refers)
3206 * @rule_type: Rule Type (ingress/egress/VLAN)
3207 * @dest_vsi: SEID of VSI to which packets will be mirrored
3208 * @count: length of the list
3209 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3210 * @cmd_details: pointer to command details structure or NULL
3211 * @rule_id: Rule ID returned from FW
3212 * @rules_used: Number of rules used in internal switch
3213 * @rules_free: Number of rules free in internal switch
3215 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3217 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3218 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3219 struct i40e_asq_cmd_details *cmd_details,
3220 u16 *rule_id, u16 *rules_used, u16 *rules_free)
3222 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3223 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3224 if (count == 0 || !mr_list)
3225 return I40E_ERR_PARAM;
3228 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3229 rule_type, dest_vsi, count, mr_list,
3230 cmd_details, rule_id, rules_used, rules_free);
3234 * i40e_aq_delete_mirrorrule - delete a mirror rule
3235 * @hw: pointer to the hw struct
3236 * @sw_seid: Switch SEID (to which rule refers)
3237 * @rule_type: Rule Type (ingress/egress/VLAN)
3238 * @count: length of the list
3239 * @rule_id: Rule ID that is returned in the receive desc as part of
3241 * @mr_list: list of mirrored VLAN IDs to be removed
3242 * @cmd_details: pointer to command details structure or NULL
3243 * @rules_used: Number of rules used in internal switch
3244 * @rules_free: Number of rules free in internal switch
3246 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3248 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3249 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3250 struct i40e_asq_cmd_details *cmd_details,
3251 u16 *rules_used, u16 *rules_free)
3253 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3254 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3255 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3256 * mirroring. For other rule_type, count and rule_type should
3259 if (count == 0 || !mr_list)
3260 return I40E_ERR_PARAM;
3263 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3264 rule_type, rule_id, count, mr_list,
3265 cmd_details, NULL, rules_used, rules_free);
3269 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3270 * @hw: pointer to the hw struct
3271 * @seid: VSI for the vlan filters
3272 * @v_list: list of vlan filters to be added
3273 * @count: length of the list
3274 * @cmd_details: pointer to command details structure or NULL
3276 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3277 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3278 u8 count, struct i40e_asq_cmd_details *cmd_details)
3280 struct i40e_aq_desc desc;
3281 struct i40e_aqc_macvlan *cmd =
3282 (struct i40e_aqc_macvlan *)&desc.params.raw;
3283 enum i40e_status_code status;
3286 if (count == 0 || !v_list || !hw)
3287 return I40E_ERR_PARAM;
3289 buf_size = count * sizeof(*v_list);
3291 /* prep the rest of the request */
3292 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3293 cmd->num_addresses = CPU_TO_LE16(count);
3294 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3298 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3299 if (buf_size > I40E_AQ_LARGE_BUF)
3300 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3302 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3309 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3310 * @hw: pointer to the hw struct
3311 * @seid: VSI for the vlan filters
3312 * @v_list: list of macvlans to be removed
3313 * @count: length of the list
3314 * @cmd_details: pointer to command details structure or NULL
3316 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3317 struct i40e_aqc_add_remove_vlan_element_data *v_list,
3318 u8 count, struct i40e_asq_cmd_details *cmd_details)
3320 struct i40e_aq_desc desc;
3321 struct i40e_aqc_macvlan *cmd =
3322 (struct i40e_aqc_macvlan *)&desc.params.raw;
3323 enum i40e_status_code status;
3326 if (count == 0 || !v_list || !hw)
3327 return I40E_ERR_PARAM;
3329 buf_size = count * sizeof(*v_list);
3331 /* prep the rest of the request */
3332 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3333 cmd->num_addresses = CPU_TO_LE16(count);
3334 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3338 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3339 if (buf_size > I40E_AQ_LARGE_BUF)
3340 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3342 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3349 * i40e_aq_send_msg_to_vf
3350 * @hw: pointer to the hardware structure
3351 * @vfid: vf id to send msg
3352 * @v_opcode: opcodes for VF-PF communication
3353 * @v_retval: return error code
3354 * @msg: pointer to the msg buffer
3355 * @msglen: msg length
3356 * @cmd_details: pointer to command details
3360 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3361 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3362 struct i40e_asq_cmd_details *cmd_details)
3364 struct i40e_aq_desc desc;
3365 struct i40e_aqc_pf_vf_message *cmd =
3366 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3367 enum i40e_status_code status;
3369 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3370 cmd->id = CPU_TO_LE32(vfid);
3371 desc.cookie_high = CPU_TO_LE32(v_opcode);
3372 desc.cookie_low = CPU_TO_LE32(v_retval);
3373 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3375 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3377 if (msglen > I40E_AQ_LARGE_BUF)
3378 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3379 desc.datalen = CPU_TO_LE16(msglen);
3381 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3387 * i40e_aq_debug_read_register
3388 * @hw: pointer to the hw struct
3389 * @reg_addr: register address
3390 * @reg_val: register value
3391 * @cmd_details: pointer to command details structure or NULL
3393 * Read the register using the admin queue commands
3395 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3396 u32 reg_addr, u64 *reg_val,
3397 struct i40e_asq_cmd_details *cmd_details)
3399 struct i40e_aq_desc desc;
3400 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3401 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3402 enum i40e_status_code status;
3404 if (reg_val == NULL)
3405 return I40E_ERR_PARAM;
3407 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3409 cmd_resp->address = CPU_TO_LE32(reg_addr);
3411 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3413 if (status == I40E_SUCCESS) {
3414 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3415 (u64)LE32_TO_CPU(cmd_resp->value_low);
3422 * i40e_aq_debug_write_register
3423 * @hw: pointer to the hw struct
3424 * @reg_addr: register address
3425 * @reg_val: register value
3426 * @cmd_details: pointer to command details structure or NULL
3428 * Write to a register using the admin queue commands
3430 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3431 u32 reg_addr, u64 reg_val,
3432 struct i40e_asq_cmd_details *cmd_details)
3434 struct i40e_aq_desc desc;
3435 struct i40e_aqc_debug_reg_read_write *cmd =
3436 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3437 enum i40e_status_code status;
3439 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3441 cmd->address = CPU_TO_LE32(reg_addr);
3442 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3443 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3445 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3451 * i40e_aq_request_resource
3452 * @hw: pointer to the hw struct
3453 * @resource: resource id
3454 * @access: access type
3455 * @sdp_number: resource number
3456 * @timeout: the maximum time in ms that the driver may hold the resource
3457 * @cmd_details: pointer to command details structure or NULL
3459 * requests common resource using the admin queue commands
3461 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3462 enum i40e_aq_resources_ids resource,
3463 enum i40e_aq_resource_access_type access,
3464 u8 sdp_number, u64 *timeout,
3465 struct i40e_asq_cmd_details *cmd_details)
3467 struct i40e_aq_desc desc;
3468 struct i40e_aqc_request_resource *cmd_resp =
3469 (struct i40e_aqc_request_resource *)&desc.params.raw;
3470 enum i40e_status_code status;
3472 DEBUGFUNC("i40e_aq_request_resource");
3474 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3476 cmd_resp->resource_id = CPU_TO_LE16(resource);
3477 cmd_resp->access_type = CPU_TO_LE16(access);
3478 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3480 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3481 /* The completion specifies the maximum time in ms that the driver
3482 * may hold the resource in the Timeout field.
3483 * If the resource is held by someone else, the command completes with
3484 * busy return value and the timeout field indicates the maximum time
3485 * the current owner of the resource has to free it.
3487 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3488 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3494 * i40e_aq_release_resource
3495 * @hw: pointer to the hw struct
3496 * @resource: resource id
3497 * @sdp_number: resource number
3498 * @cmd_details: pointer to command details structure or NULL
3500 * release common resource using the admin queue commands
3502 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3503 enum i40e_aq_resources_ids resource,
3505 struct i40e_asq_cmd_details *cmd_details)
3507 struct i40e_aq_desc desc;
3508 struct i40e_aqc_request_resource *cmd =
3509 (struct i40e_aqc_request_resource *)&desc.params.raw;
3510 enum i40e_status_code status;
3512 DEBUGFUNC("i40e_aq_release_resource");
3514 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3516 cmd->resource_id = CPU_TO_LE16(resource);
3517 cmd->resource_number = CPU_TO_LE32(sdp_number);
3519 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3526 * @hw: pointer to the hw struct
3527 * @module_pointer: module pointer location in words from the NVM beginning
3528 * @offset: byte offset from the module beginning
3529 * @length: length of the section to be read (in bytes from the offset)
3530 * @data: command buffer (size [bytes] = length)
3531 * @last_command: tells if this is the last command in a series
3532 * @cmd_details: pointer to command details structure or NULL
3534 * Read the NVM using the admin queue commands
3536 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3537 u32 offset, u16 length, void *data,
3539 struct i40e_asq_cmd_details *cmd_details)
3541 struct i40e_aq_desc desc;
3542 struct i40e_aqc_nvm_update *cmd =
3543 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3544 enum i40e_status_code status;
3546 DEBUGFUNC("i40e_aq_read_nvm");
3548 /* In offset the highest byte must be zeroed. */
3549 if (offset & 0xFF000000) {
3550 status = I40E_ERR_PARAM;
3551 goto i40e_aq_read_nvm_exit;
3554 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3556 /* If this is the last command in a series, set the proper flag. */
3558 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3559 cmd->module_pointer = module_pointer;
3560 cmd->offset = CPU_TO_LE32(offset);
3561 cmd->length = CPU_TO_LE16(length);
3563 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3564 if (length > I40E_AQ_LARGE_BUF)
3565 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3567 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3569 i40e_aq_read_nvm_exit:
3574 * i40e_aq_read_nvm_config - read an nvm config block
3575 * @hw: pointer to the hw struct
3576 * @cmd_flags: NVM access admin command bits
3577 * @field_id: field or feature id
3578 * @data: buffer for result
3579 * @buf_size: buffer size
3580 * @element_count: pointer to count of elements read by FW
3581 * @cmd_details: pointer to command details structure or NULL
3583 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3584 u8 cmd_flags, u32 field_id, void *data,
3585 u16 buf_size, u16 *element_count,
3586 struct i40e_asq_cmd_details *cmd_details)
3588 struct i40e_aq_desc desc;
3589 struct i40e_aqc_nvm_config_read *cmd =
3590 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3591 enum i40e_status_code status;
3593 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3594 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3595 if (buf_size > I40E_AQ_LARGE_BUF)
3596 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3598 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3599 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3600 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3601 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3603 cmd->element_id_msw = 0;
3605 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3607 if (!status && element_count)
3608 *element_count = LE16_TO_CPU(cmd->element_count);
3614 * i40e_aq_write_nvm_config - write an nvm config block
3615 * @hw: pointer to the hw struct
3616 * @cmd_flags: NVM access admin command bits
3617 * @data: buffer for result
3618 * @buf_size: buffer size
3619 * @element_count: count of elements to be written
3620 * @cmd_details: pointer to command details structure or NULL
3622 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3623 u8 cmd_flags, void *data, u16 buf_size,
3625 struct i40e_asq_cmd_details *cmd_details)
3627 struct i40e_aq_desc desc;
3628 struct i40e_aqc_nvm_config_write *cmd =
3629 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3630 enum i40e_status_code status;
3632 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3633 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3634 if (buf_size > I40E_AQ_LARGE_BUF)
3635 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3637 cmd->element_count = CPU_TO_LE16(element_count);
3638 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3639 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3645 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3646 * @hw: pointer to the hw struct
3647 * @buff: buffer for result
3648 * @buff_size: buffer size
3649 * @cmd_details: pointer to command details structure or NULL
3651 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3652 void *buff, u16 buff_size,
3653 struct i40e_asq_cmd_details *cmd_details)
3655 struct i40e_aq_desc desc;
3656 enum i40e_status_code status;
3658 UNREFERENCED_2PARAMETER(buff, buff_size);
3660 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3661 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3662 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3663 status = I40E_ERR_NOT_IMPLEMENTED;
3670 * @hw: pointer to the hw struct
3671 * @module_pointer: module pointer location in words from the NVM beginning
3672 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3673 * @length: length of the section to be erased (expressed in 4 KB)
3674 * @last_command: tells if this is the last command in a series
3675 * @cmd_details: pointer to command details structure or NULL
3677 * Erase the NVM sector using the admin queue commands
3679 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3680 u32 offset, u16 length, bool last_command,
3681 struct i40e_asq_cmd_details *cmd_details)
3683 struct i40e_aq_desc desc;
3684 struct i40e_aqc_nvm_update *cmd =
3685 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3686 enum i40e_status_code status;
3688 DEBUGFUNC("i40e_aq_erase_nvm");
3690 /* In offset the highest byte must be zeroed. */
3691 if (offset & 0xFF000000) {
3692 status = I40E_ERR_PARAM;
3693 goto i40e_aq_erase_nvm_exit;
3696 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3698 /* If this is the last command in a series, set the proper flag. */
3700 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3701 cmd->module_pointer = module_pointer;
3702 cmd->offset = CPU_TO_LE32(offset);
3703 cmd->length = CPU_TO_LE16(length);
3705 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3707 i40e_aq_erase_nvm_exit:
3712 * i40e_parse_discover_capabilities
3713 * @hw: pointer to the hw struct
3714 * @buff: pointer to a buffer containing device/function capability records
3715 * @cap_count: number of capability records in the list
3716 * @list_type_opc: type of capabilities list to parse
3718 * Parse the device/function capabilities list.
3720 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3722 enum i40e_admin_queue_opc list_type_opc)
3724 struct i40e_aqc_list_capabilities_element_resp *cap;
3725 u32 valid_functions, num_functions;
3726 u32 number, logical_id, phys_id;
3727 struct i40e_hw_capabilities *p;
3728 enum i40e_status_code status;
3729 u16 id, ocp_cfg_word0;
3733 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3735 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3736 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3737 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3738 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3742 for (i = 0; i < cap_count; i++, cap++) {
3743 id = LE16_TO_CPU(cap->id);
3744 number = LE32_TO_CPU(cap->number);
3745 logical_id = LE32_TO_CPU(cap->logical_id);
3746 phys_id = LE32_TO_CPU(cap->phys_id);
3747 major_rev = cap->major_rev;
3750 case I40E_AQ_CAP_ID_SWITCH_MODE:
3751 p->switch_mode = number;
3752 i40e_debug(hw, I40E_DEBUG_INIT,
3753 "HW Capability: Switch mode = %d\n",
3756 case I40E_AQ_CAP_ID_MNG_MODE:
3757 p->management_mode = number;
3758 if (major_rev > 1) {
3759 p->mng_protocols_over_mctp = logical_id;
3760 i40e_debug(hw, I40E_DEBUG_INIT,
3761 "HW Capability: Protocols over MCTP = %d\n",
3762 p->mng_protocols_over_mctp);
3764 p->mng_protocols_over_mctp = 0;
3766 i40e_debug(hw, I40E_DEBUG_INIT,
3767 "HW Capability: Management Mode = %d\n",
3768 p->management_mode);
3770 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3771 p->npar_enable = number;
3772 i40e_debug(hw, I40E_DEBUG_INIT,
3773 "HW Capability: NPAR enable = %d\n",
3776 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3778 i40e_debug(hw, I40E_DEBUG_INIT,
3779 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3781 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3782 p->valid_functions = number;
3783 i40e_debug(hw, I40E_DEBUG_INIT,
3784 "HW Capability: Valid Functions = %d\n",
3785 p->valid_functions);
3787 case I40E_AQ_CAP_ID_SRIOV:
3789 p->sr_iov_1_1 = true;
3790 i40e_debug(hw, I40E_DEBUG_INIT,
3791 "HW Capability: SR-IOV = %d\n",
3794 case I40E_AQ_CAP_ID_VF:
3795 p->num_vfs = number;
3796 p->vf_base_id = logical_id;
3797 i40e_debug(hw, I40E_DEBUG_INIT,
3798 "HW Capability: VF count = %d\n",
3800 i40e_debug(hw, I40E_DEBUG_INIT,
3801 "HW Capability: VF base_id = %d\n",
3804 case I40E_AQ_CAP_ID_VMDQ:
3807 i40e_debug(hw, I40E_DEBUG_INIT,
3808 "HW Capability: VMDQ = %d\n", p->vmdq);
3810 case I40E_AQ_CAP_ID_8021QBG:
3812 p->evb_802_1_qbg = true;
3813 i40e_debug(hw, I40E_DEBUG_INIT,
3814 "HW Capability: 802.1Qbg = %d\n", number);
3816 case I40E_AQ_CAP_ID_8021QBR:
3818 p->evb_802_1_qbh = true;
3819 i40e_debug(hw, I40E_DEBUG_INIT,
3820 "HW Capability: 802.1Qbh = %d\n", number);
3822 case I40E_AQ_CAP_ID_VSI:
3823 p->num_vsis = number;
3824 i40e_debug(hw, I40E_DEBUG_INIT,
3825 "HW Capability: VSI count = %d\n",
3828 case I40E_AQ_CAP_ID_DCB:
3831 p->enabled_tcmap = logical_id;
3834 i40e_debug(hw, I40E_DEBUG_INIT,
3835 "HW Capability: DCB = %d\n", p->dcb);
3836 i40e_debug(hw, I40E_DEBUG_INIT,
3837 "HW Capability: TC Mapping = %d\n",
3839 i40e_debug(hw, I40E_DEBUG_INIT,
3840 "HW Capability: TC Max = %d\n", p->maxtc);
3842 case I40E_AQ_CAP_ID_FCOE:
3845 i40e_debug(hw, I40E_DEBUG_INIT,
3846 "HW Capability: FCOE = %d\n", p->fcoe);
3848 case I40E_AQ_CAP_ID_ISCSI:
3851 i40e_debug(hw, I40E_DEBUG_INIT,
3852 "HW Capability: iSCSI = %d\n", p->iscsi);
3854 case I40E_AQ_CAP_ID_RSS:
3856 p->rss_table_size = number;
3857 p->rss_table_entry_width = logical_id;
3858 i40e_debug(hw, I40E_DEBUG_INIT,
3859 "HW Capability: RSS = %d\n", p->rss);
3860 i40e_debug(hw, I40E_DEBUG_INIT,
3861 "HW Capability: RSS table size = %d\n",
3863 i40e_debug(hw, I40E_DEBUG_INIT,
3864 "HW Capability: RSS table width = %d\n",
3865 p->rss_table_entry_width);
3867 case I40E_AQ_CAP_ID_RXQ:
3868 p->num_rx_qp = number;
3869 p->base_queue = phys_id;
3870 i40e_debug(hw, I40E_DEBUG_INIT,
3871 "HW Capability: Rx QP = %d\n", number);
3872 i40e_debug(hw, I40E_DEBUG_INIT,
3873 "HW Capability: base_queue = %d\n",
3876 case I40E_AQ_CAP_ID_TXQ:
3877 p->num_tx_qp = number;
3878 p->base_queue = phys_id;
3879 i40e_debug(hw, I40E_DEBUG_INIT,
3880 "HW Capability: Tx QP = %d\n", number);
3881 i40e_debug(hw, I40E_DEBUG_INIT,
3882 "HW Capability: base_queue = %d\n",
3885 case I40E_AQ_CAP_ID_MSIX:
3886 p->num_msix_vectors = number;
3887 i40e_debug(hw, I40E_DEBUG_INIT,
3888 "HW Capability: MSIX vector count = %d\n",
3889 p->num_msix_vectors);
3891 case I40E_AQ_CAP_ID_VF_MSIX:
3892 p->num_msix_vectors_vf = number;
3893 i40e_debug(hw, I40E_DEBUG_INIT,
3894 "HW Capability: MSIX VF vector count = %d\n",
3895 p->num_msix_vectors_vf);
3897 case I40E_AQ_CAP_ID_FLEX10:
3898 if (major_rev == 1) {
3900 p->flex10_enable = true;
3901 p->flex10_capable = true;
3904 /* Capability revision >= 2 */
3906 p->flex10_enable = true;
3908 p->flex10_capable = true;
3910 p->flex10_mode = logical_id;
3911 p->flex10_status = phys_id;
3912 i40e_debug(hw, I40E_DEBUG_INIT,
3913 "HW Capability: Flex10 mode = %d\n",
3915 i40e_debug(hw, I40E_DEBUG_INIT,
3916 "HW Capability: Flex10 status = %d\n",
3919 case I40E_AQ_CAP_ID_CEM:
3922 i40e_debug(hw, I40E_DEBUG_INIT,
3923 "HW Capability: CEM = %d\n", p->mgmt_cem);
3925 case I40E_AQ_CAP_ID_IWARP:
3928 i40e_debug(hw, I40E_DEBUG_INIT,
3929 "HW Capability: iWARP = %d\n", p->iwarp);
3931 case I40E_AQ_CAP_ID_LED:
3932 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3933 p->led[phys_id] = true;
3934 i40e_debug(hw, I40E_DEBUG_INIT,
3935 "HW Capability: LED - PIN %d\n", phys_id);
3937 case I40E_AQ_CAP_ID_SDP:
3938 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3939 p->sdp[phys_id] = true;
3940 i40e_debug(hw, I40E_DEBUG_INIT,
3941 "HW Capability: SDP - PIN %d\n", phys_id);
3943 case I40E_AQ_CAP_ID_MDIO:
3945 p->mdio_port_num = phys_id;
3946 p->mdio_port_mode = logical_id;
3948 i40e_debug(hw, I40E_DEBUG_INIT,
3949 "HW Capability: MDIO port number = %d\n",
3951 i40e_debug(hw, I40E_DEBUG_INIT,
3952 "HW Capability: MDIO port mode = %d\n",
3955 case I40E_AQ_CAP_ID_1588:
3957 p->ieee_1588 = true;
3958 i40e_debug(hw, I40E_DEBUG_INIT,
3959 "HW Capability: IEEE 1588 = %d\n",
3962 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3964 p->fd_filters_guaranteed = number;
3965 p->fd_filters_best_effort = logical_id;
3966 i40e_debug(hw, I40E_DEBUG_INIT,
3967 "HW Capability: Flow Director = 1\n");
3968 i40e_debug(hw, I40E_DEBUG_INIT,
3969 "HW Capability: Guaranteed FD filters = %d\n",
3970 p->fd_filters_guaranteed);
3972 case I40E_AQ_CAP_ID_WSR_PROT:
3973 p->wr_csr_prot = (u64)number;
3974 p->wr_csr_prot |= (u64)logical_id << 32;
3975 i40e_debug(hw, I40E_DEBUG_INIT,
3976 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3977 (p->wr_csr_prot & 0xffff));
3979 case I40E_AQ_CAP_ID_NVM_MGMT:
3980 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3981 p->sec_rev_disabled = true;
3982 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3983 p->update_disabled = true;
3985 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3986 hw->num_wol_proxy_filters = (u16)number;
3987 hw->wol_proxy_vsi_seid = (u16)logical_id;
3988 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3989 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3990 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3992 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3993 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3994 i40e_debug(hw, I40E_DEBUG_INIT,
3995 "HW Capability: WOL proxy filters = %d\n",
3996 hw->num_wol_proxy_filters);
4004 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
4006 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
4009 /* count the enabled ports (aka the "not disabled" ports) */
4011 for (i = 0; i < 4; i++) {
4012 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4015 /* use AQ read to get the physical register offset instead
4016 * of the port relative offset
4018 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4019 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4023 /* OCP cards case: if a mezz is removed the ethernet port is at
4024 * disabled state in PRTGEN_CNF register. Additional NVM read is
4025 * needed in order to check if we are dealing with OCP card.
4026 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4027 * physical ports results in wrong partition id calculation and thus
4028 * not supporting WoL.
4030 if (hw->mac.type == I40E_MAC_X722) {
4031 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4032 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4033 2 * I40E_SR_OCP_CFG_WORD0,
4034 sizeof(ocp_cfg_word0),
4035 &ocp_cfg_word0, true, NULL);
4036 if (status == I40E_SUCCESS &&
4037 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4039 i40e_release_nvm(hw);
4043 valid_functions = p->valid_functions;
4045 while (valid_functions) {
4046 if (valid_functions & 1)
4048 valid_functions >>= 1;
4051 /* partition id is 1-based, and functions are evenly spread
4052 * across the ports as partitions
4054 if (hw->num_ports != 0) {
4055 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4056 hw->num_partitions = num_functions / hw->num_ports;
4059 /* additional HW specific goodies that might
4060 * someday be HW version specific
4062 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4066 * i40e_aq_discover_capabilities
4067 * @hw: pointer to the hw struct
4068 * @buff: a virtual buffer to hold the capabilities
4069 * @buff_size: Size of the virtual buffer
4070 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4071 * @list_type_opc: capabilities type to discover - pass in the command opcode
4072 * @cmd_details: pointer to command details structure or NULL
4074 * Get the device capabilities descriptions from the firmware
4076 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4077 void *buff, u16 buff_size, u16 *data_size,
4078 enum i40e_admin_queue_opc list_type_opc,
4079 struct i40e_asq_cmd_details *cmd_details)
4081 struct i40e_aqc_list_capabilites *cmd;
4082 struct i40e_aq_desc desc;
4083 enum i40e_status_code status = I40E_SUCCESS;
4085 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4087 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4088 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4089 status = I40E_ERR_PARAM;
4093 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4095 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4096 if (buff_size > I40E_AQ_LARGE_BUF)
4097 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4099 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4100 *data_size = LE16_TO_CPU(desc.datalen);
4105 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4113 * i40e_aq_update_nvm
4114 * @hw: pointer to the hw struct
4115 * @module_pointer: module pointer location in words from the NVM beginning
4116 * @offset: byte offset from the module beginning
4117 * @length: length of the section to be written (in bytes from the offset)
4118 * @data: command buffer (size [bytes] = length)
4119 * @last_command: tells if this is the last command in a series
4120 * @preservation_flags: Preservation mode flags
4121 * @cmd_details: pointer to command details structure or NULL
4123 * Update the NVM using the admin queue commands
4125 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4126 u32 offset, u16 length, void *data,
4127 bool last_command, u8 preservation_flags,
4128 struct i40e_asq_cmd_details *cmd_details)
4130 struct i40e_aq_desc desc;
4131 struct i40e_aqc_nvm_update *cmd =
4132 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4133 enum i40e_status_code status;
4135 DEBUGFUNC("i40e_aq_update_nvm");
4137 /* In offset the highest byte must be zeroed. */
4138 if (offset & 0xFF000000) {
4139 status = I40E_ERR_PARAM;
4140 goto i40e_aq_update_nvm_exit;
4143 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4145 /* If this is the last command in a series, set the proper flag. */
4147 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4148 if (hw->mac.type == I40E_MAC_X722) {
4149 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4150 cmd->command_flags |=
4151 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4152 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4153 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4154 cmd->command_flags |=
4155 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4156 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4158 cmd->module_pointer = module_pointer;
4159 cmd->offset = CPU_TO_LE32(offset);
4160 cmd->length = CPU_TO_LE16(length);
4162 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4163 if (length > I40E_AQ_LARGE_BUF)
4164 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4166 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4168 i40e_aq_update_nvm_exit:
4173 * i40e_aq_rearrange_nvm
4174 * @hw: pointer to the hw struct
4175 * @rearrange_nvm: defines direction of rearrangement
4176 * @cmd_details: pointer to command details structure or NULL
4178 * Rearrange NVM structure, available only for transition FW
4180 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4182 struct i40e_asq_cmd_details *cmd_details)
4184 struct i40e_aqc_nvm_update *cmd;
4185 enum i40e_status_code status;
4186 struct i40e_aq_desc desc;
4188 DEBUGFUNC("i40e_aq_rearrange_nvm");
4190 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4192 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4194 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4195 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4197 if (!rearrange_nvm) {
4198 status = I40E_ERR_PARAM;
4199 goto i40e_aq_rearrange_nvm_exit;
4202 cmd->command_flags |= rearrange_nvm;
4203 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4205 i40e_aq_rearrange_nvm_exit:
4210 * i40e_aq_nvm_progress
4211 * @hw: pointer to the hw struct
4212 * @progress: pointer to progress returned from AQ
4213 * @cmd_details: pointer to command details structure or NULL
4215 * Gets progress of flash rearrangement process
4217 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4218 struct i40e_asq_cmd_details *cmd_details)
4220 enum i40e_status_code status;
4221 struct i40e_aq_desc desc;
4223 DEBUGFUNC("i40e_aq_nvm_progress");
4225 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4226 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4227 *progress = desc.params.raw[0];
4232 * i40e_aq_get_lldp_mib
4233 * @hw: pointer to the hw struct
4234 * @bridge_type: type of bridge requested
4235 * @mib_type: Local, Remote or both Local and Remote MIBs
4236 * @buff: pointer to a user supplied buffer to store the MIB block
4237 * @buff_size: size of the buffer (in bytes)
4238 * @local_len : length of the returned Local LLDP MIB
4239 * @remote_len: length of the returned Remote LLDP MIB
4240 * @cmd_details: pointer to command details structure or NULL
4242 * Requests the complete LLDP MIB (entire packet).
4244 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4245 u8 mib_type, void *buff, u16 buff_size,
4246 u16 *local_len, u16 *remote_len,
4247 struct i40e_asq_cmd_details *cmd_details)
4249 struct i40e_aq_desc desc;
4250 struct i40e_aqc_lldp_get_mib *cmd =
4251 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4252 struct i40e_aqc_lldp_get_mib *resp =
4253 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4254 enum i40e_status_code status;
4256 if (buff_size == 0 || !buff)
4257 return I40E_ERR_PARAM;
4259 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4260 /* Indirect Command */
4261 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4263 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4264 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4265 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4267 desc.datalen = CPU_TO_LE16(buff_size);
4269 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4270 if (buff_size > I40E_AQ_LARGE_BUF)
4271 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4273 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4275 if (local_len != NULL)
4276 *local_len = LE16_TO_CPU(resp->local_len);
4277 if (remote_len != NULL)
4278 *remote_len = LE16_TO_CPU(resp->remote_len);
4285 * i40e_aq_set_lldp_mib - Set the LLDP MIB
4286 * @hw: pointer to the hw struct
4287 * @mib_type: Local, Remote or both Local and Remote MIBs
4288 * @buff: pointer to a user supplied buffer to store the MIB block
4289 * @buff_size: size of the buffer (in bytes)
4290 * @cmd_details: pointer to command details structure or NULL
4294 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4295 u8 mib_type, void *buff, u16 buff_size,
4296 struct i40e_asq_cmd_details *cmd_details)
4298 struct i40e_aq_desc desc;
4299 struct i40e_aqc_lldp_set_local_mib *cmd =
4300 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4301 enum i40e_status_code status;
4303 if (buff_size == 0 || !buff)
4304 return I40E_ERR_PARAM;
4306 i40e_fill_default_direct_cmd_desc(&desc,
4307 i40e_aqc_opc_lldp_set_local_mib);
4308 /* Indirect Command */
4309 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4310 if (buff_size > I40E_AQ_LARGE_BUF)
4311 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4312 desc.datalen = CPU_TO_LE16(buff_size);
4314 cmd->type = mib_type;
4315 cmd->length = CPU_TO_LE16(buff_size);
4316 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
4317 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4319 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4324 * i40e_aq_cfg_lldp_mib_change_event
4325 * @hw: pointer to the hw struct
4326 * @enable_update: Enable or Disable event posting
4327 * @cmd_details: pointer to command details structure or NULL
4329 * Enable or Disable posting of an event on ARQ when LLDP MIB
4330 * associated with the interface changes
4332 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4334 struct i40e_asq_cmd_details *cmd_details)
4336 struct i40e_aq_desc desc;
4337 struct i40e_aqc_lldp_update_mib *cmd =
4338 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4339 enum i40e_status_code status;
4341 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4344 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4346 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4352 * i40e_aq_restore_lldp
4353 * @hw: pointer to the hw struct
4354 * @setting: pointer to factory setting variable or NULL
4355 * @restore: True if factory settings should be restored
4356 * @cmd_details: pointer to command details structure or NULL
4358 * Restore LLDP Agent factory settings if @restore set to True. In other case
4359 * only returns factory setting in AQ response.
4361 enum i40e_status_code
4362 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
4363 struct i40e_asq_cmd_details *cmd_details)
4365 struct i40e_aq_desc desc;
4366 struct i40e_aqc_lldp_restore *cmd =
4367 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
4368 enum i40e_status_code status;
4370 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
4371 i40e_debug(hw, I40E_DEBUG_ALL,
4372 "Restore LLDP not supported by current FW version.\n");
4373 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4376 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
4379 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
4381 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4384 *setting = cmd->command & 1;
4391 * @hw: pointer to the hw struct
4392 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4393 * @persist: True if stop of LLDP should be persistent across power cycles
4394 * @cmd_details: pointer to command details structure or NULL
4396 * Stop or Shutdown the embedded LLDP Agent
4398 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4400 struct i40e_asq_cmd_details *cmd_details)
4402 struct i40e_aq_desc desc;
4403 struct i40e_aqc_lldp_stop *cmd =
4404 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4405 enum i40e_status_code status;
4407 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4410 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4413 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4414 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
4416 i40e_debug(hw, I40E_DEBUG_ALL,
4417 "Persistent Stop LLDP not supported by current FW version.\n");
4420 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4426 * i40e_aq_start_lldp
4427 * @hw: pointer to the hw struct
4428 * @persist: True if start of LLDP should be persistent across power cycles
4429 * @cmd_details: pointer to command details structure or NULL
4431 * Start the embedded LLDP Agent on all ports.
4433 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4435 struct i40e_asq_cmd_details *cmd_details)
4437 struct i40e_aq_desc desc;
4438 struct i40e_aqc_lldp_start *cmd =
4439 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4440 enum i40e_status_code status;
4442 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4444 cmd->command = I40E_AQ_LLDP_AGENT_START;
4447 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
4448 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
4450 i40e_debug(hw, I40E_DEBUG_ALL,
4451 "Persistent Start LLDP not supported by current FW version.\n");
4454 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4460 * i40e_aq_set_dcb_parameters
4461 * @hw: pointer to the hw struct
4462 * @cmd_details: pointer to command details structure or NULL
4463 * @dcb_enable: True if DCB configuration needs to be applied
4466 enum i40e_status_code
4467 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4468 struct i40e_asq_cmd_details *cmd_details)
4470 struct i40e_aq_desc desc;
4471 struct i40e_aqc_set_dcb_parameters *cmd =
4472 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4473 enum i40e_status_code status;
4475 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4476 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4478 i40e_fill_default_direct_cmd_desc(&desc,
4479 i40e_aqc_opc_set_dcb_parameters);
4482 cmd->valid_flags = I40E_DCB_VALID;
4483 cmd->command = I40E_AQ_DCB_SET_AGENT;
4485 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4491 * i40e_aq_get_cee_dcb_config
4492 * @hw: pointer to the hw struct
4493 * @buff: response buffer that stores CEE operational configuration
4494 * @buff_size: size of the buffer passed
4495 * @cmd_details: pointer to command details structure or NULL
4497 * Get CEE DCBX mode operational configuration from firmware
4499 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4500 void *buff, u16 buff_size,
4501 struct i40e_asq_cmd_details *cmd_details)
4503 struct i40e_aq_desc desc;
4504 enum i40e_status_code status;
4506 if (buff_size == 0 || !buff)
4507 return I40E_ERR_PARAM;
4509 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4511 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4512 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4519 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4520 * @hw: pointer to the hw struct
4521 * @start_agent: True if DCBx Agent needs to be Started
4522 * False if DCBx Agent needs to be Stopped
4523 * @cmd_details: pointer to command details structure or NULL
4525 * Start/Stop the embedded dcbx Agent
4527 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4529 struct i40e_asq_cmd_details *cmd_details)
4531 struct i40e_aq_desc desc;
4532 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4533 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4535 enum i40e_status_code status;
4537 i40e_fill_default_direct_cmd_desc(&desc,
4538 i40e_aqc_opc_lldp_stop_start_spec_agent);
4541 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4543 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4549 * i40e_aq_add_udp_tunnel
4550 * @hw: pointer to the hw struct
4551 * @udp_port: the UDP port to add in Host byte order
4552 * @protocol_index: protocol index type
4553 * @filter_index: pointer to filter index
4554 * @cmd_details: pointer to command details structure or NULL
4556 * Note: Firmware expects the udp_port value to be in Little Endian format,
4557 * and this function will call CPU_TO_LE16 to convert from Host byte order to
4558 * Little Endian order.
4560 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4561 u16 udp_port, u8 protocol_index,
4563 struct i40e_asq_cmd_details *cmd_details)
4565 struct i40e_aq_desc desc;
4566 struct i40e_aqc_add_udp_tunnel *cmd =
4567 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4568 struct i40e_aqc_del_udp_tunnel_completion *resp =
4569 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4570 enum i40e_status_code status;
4572 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4574 cmd->udp_port = CPU_TO_LE16(udp_port);
4575 cmd->protocol_type = protocol_index;
4577 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4579 if (!status && filter_index)
4580 *filter_index = resp->index;
4586 * i40e_aq_del_udp_tunnel
4587 * @hw: pointer to the hw struct
4588 * @index: filter index
4589 * @cmd_details: pointer to command details structure or NULL
4591 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4592 struct i40e_asq_cmd_details *cmd_details)
4594 struct i40e_aq_desc desc;
4595 struct i40e_aqc_remove_udp_tunnel *cmd =
4596 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4597 enum i40e_status_code status;
4599 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4603 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4609 * i40e_aq_get_switch_resource_alloc (0x0204)
4610 * @hw: pointer to the hw struct
4611 * @num_entries: pointer to u8 to store the number of resource entries returned
4612 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4613 * to store the resource information for all resource types. Each
4614 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4615 * @count: size, in bytes, of the buffer provided
4616 * @cmd_details: pointer to command details structure or NULL
4618 * Query the resources allocated to a function.
4620 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4622 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4624 struct i40e_asq_cmd_details *cmd_details)
4626 struct i40e_aq_desc desc;
4627 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4628 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4629 enum i40e_status_code status;
4630 u16 length = count * sizeof(*buf);
4632 i40e_fill_default_direct_cmd_desc(&desc,
4633 i40e_aqc_opc_get_switch_resource_alloc);
4635 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4636 if (length > I40E_AQ_LARGE_BUF)
4637 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4639 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4641 if (!status && num_entries)
4642 *num_entries = cmd_resp->num_entries;
4648 * i40e_aq_delete_element - Delete switch element
4649 * @hw: pointer to the hw struct
4650 * @seid: the SEID to delete from the switch
4651 * @cmd_details: pointer to command details structure or NULL
4653 * This deletes a switch element from the switch.
4655 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4656 struct i40e_asq_cmd_details *cmd_details)
4658 struct i40e_aq_desc desc;
4659 struct i40e_aqc_switch_seid *cmd =
4660 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4661 enum i40e_status_code status;
4664 return I40E_ERR_PARAM;
4666 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4668 cmd->seid = CPU_TO_LE16(seid);
4670 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4676 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4677 * @hw: pointer to the hw struct
4678 * @flags: component flags
4679 * @mac_seid: uplink seid (MAC SEID)
4680 * @vsi_seid: connected vsi seid
4681 * @ret_seid: seid of create pv component
4683 * This instantiates an i40e port virtualizer with specified flags.
4684 * Depending on specified flags the port virtualizer can act as a
4685 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4687 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4688 u16 mac_seid, u16 vsi_seid,
4691 struct i40e_aq_desc desc;
4692 struct i40e_aqc_add_update_pv *cmd =
4693 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4694 struct i40e_aqc_add_update_pv_completion *resp =
4695 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4696 enum i40e_status_code status;
4699 return I40E_ERR_PARAM;
4701 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4702 cmd->command_flags = CPU_TO_LE16(flags);
4703 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4704 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4706 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4707 if (!status && ret_seid)
4708 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4714 * i40e_aq_add_tag - Add an S/E-tag
4715 * @hw: pointer to the hw struct
4716 * @direct_to_queue: should s-tag direct flow to a specific queue
4717 * @vsi_seid: VSI SEID to use this tag
4718 * @tag: value of the tag
4719 * @queue_num: queue number, only valid is direct_to_queue is true
4720 * @tags_used: return value, number of tags in use by this PF
4721 * @tags_free: return value, number of unallocated tags
4722 * @cmd_details: pointer to command details structure or NULL
4724 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4725 * the number of tags allocated by the PF, and the number of unallocated
4728 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4729 u16 vsi_seid, u16 tag, u16 queue_num,
4730 u16 *tags_used, u16 *tags_free,
4731 struct i40e_asq_cmd_details *cmd_details)
4733 struct i40e_aq_desc desc;
4734 struct i40e_aqc_add_tag *cmd =
4735 (struct i40e_aqc_add_tag *)&desc.params.raw;
4736 struct i40e_aqc_add_remove_tag_completion *resp =
4737 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4738 enum i40e_status_code status;
4741 return I40E_ERR_PARAM;
4743 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4745 cmd->seid = CPU_TO_LE16(vsi_seid);
4746 cmd->tag = CPU_TO_LE16(tag);
4747 if (direct_to_queue) {
4748 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4749 cmd->queue_number = CPU_TO_LE16(queue_num);
4752 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4755 if (tags_used != NULL)
4756 *tags_used = LE16_TO_CPU(resp->tags_used);
4757 if (tags_free != NULL)
4758 *tags_free = LE16_TO_CPU(resp->tags_free);
4765 * i40e_aq_remove_tag - Remove an S- or E-tag
4766 * @hw: pointer to the hw struct
4767 * @vsi_seid: VSI SEID this tag is associated with
4768 * @tag: value of the S-tag to delete
4769 * @tags_used: return value, number of tags in use by this PF
4770 * @tags_free: return value, number of unallocated tags
4771 * @cmd_details: pointer to command details structure or NULL
4773 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4774 * the number of tags allocated by the PF, and the number of unallocated
4777 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4778 u16 tag, u16 *tags_used, u16 *tags_free,
4779 struct i40e_asq_cmd_details *cmd_details)
4781 struct i40e_aq_desc desc;
4782 struct i40e_aqc_remove_tag *cmd =
4783 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4784 struct i40e_aqc_add_remove_tag_completion *resp =
4785 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4786 enum i40e_status_code status;
4789 return I40E_ERR_PARAM;
4791 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4793 cmd->seid = CPU_TO_LE16(vsi_seid);
4794 cmd->tag = CPU_TO_LE16(tag);
4796 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4799 if (tags_used != NULL)
4800 *tags_used = LE16_TO_CPU(resp->tags_used);
4801 if (tags_free != NULL)
4802 *tags_free = LE16_TO_CPU(resp->tags_free);
4809 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4810 * @hw: pointer to the hw struct
4811 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4812 * @etag: value of E-tag to add
4813 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4814 * @buf: address of indirect buffer
4815 * @tags_used: return value, number of E-tags in use by this port
4816 * @tags_free: return value, number of unallocated M-tags
4817 * @cmd_details: pointer to command details structure or NULL
4819 * This associates a multicast E-tag to a port virtualizer. It will return
4820 * the number of tags allocated by the PF, and the number of unallocated
4823 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4824 * num_tags_in_buf long.
4826 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4827 u16 etag, u8 num_tags_in_buf, void *buf,
4828 u16 *tags_used, u16 *tags_free,
4829 struct i40e_asq_cmd_details *cmd_details)
4831 struct i40e_aq_desc desc;
4832 struct i40e_aqc_add_remove_mcast_etag *cmd =
4833 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4834 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4835 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4836 enum i40e_status_code status;
4837 u16 length = sizeof(u16) * num_tags_in_buf;
4839 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4840 return I40E_ERR_PARAM;
4842 i40e_fill_default_direct_cmd_desc(&desc,
4843 i40e_aqc_opc_add_multicast_etag);
4845 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4846 cmd->etag = CPU_TO_LE16(etag);
4847 cmd->num_unicast_etags = num_tags_in_buf;
4849 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4850 if (length > I40E_AQ_LARGE_BUF)
4851 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4853 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4856 if (tags_used != NULL)
4857 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4858 if (tags_free != NULL)
4859 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4866 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4867 * @hw: pointer to the hw struct
4868 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4869 * @etag: value of the E-tag to remove
4870 * @tags_used: return value, number of tags in use by this port
4871 * @tags_free: return value, number of unallocated tags
4872 * @cmd_details: pointer to command details structure or NULL
4874 * This deletes an E-tag from the port virtualizer. It will return
4875 * the number of tags allocated by the port, and the number of unallocated
4878 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4879 u16 etag, u16 *tags_used, u16 *tags_free,
4880 struct i40e_asq_cmd_details *cmd_details)
4882 struct i40e_aq_desc desc;
4883 struct i40e_aqc_add_remove_mcast_etag *cmd =
4884 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4885 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4886 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4887 enum i40e_status_code status;
4891 return I40E_ERR_PARAM;
4893 i40e_fill_default_direct_cmd_desc(&desc,
4894 i40e_aqc_opc_remove_multicast_etag);
4896 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4897 cmd->etag = CPU_TO_LE16(etag);
4899 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4902 if (tags_used != NULL)
4903 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4904 if (tags_free != NULL)
4905 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4912 * i40e_aq_update_tag - Update an S/E-tag
4913 * @hw: pointer to the hw struct
4914 * @vsi_seid: VSI SEID using this S-tag
4915 * @old_tag: old tag value
4916 * @new_tag: new tag value
4917 * @tags_used: return value, number of tags in use by this PF
4918 * @tags_free: return value, number of unallocated tags
4919 * @cmd_details: pointer to command details structure or NULL
4921 * This updates the value of the tag currently attached to this VSI
4922 * in the switch complex. It will return the number of tags allocated
4923 * by the PF, and the number of unallocated tags available.
4925 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4926 u16 old_tag, u16 new_tag, u16 *tags_used,
4928 struct i40e_asq_cmd_details *cmd_details)
4930 struct i40e_aq_desc desc;
4931 struct i40e_aqc_update_tag *cmd =
4932 (struct i40e_aqc_update_tag *)&desc.params.raw;
4933 struct i40e_aqc_update_tag_completion *resp =
4934 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4935 enum i40e_status_code status;
4938 return I40E_ERR_PARAM;
4940 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4942 cmd->seid = CPU_TO_LE16(vsi_seid);
4943 cmd->old_tag = CPU_TO_LE16(old_tag);
4944 cmd->new_tag = CPU_TO_LE16(new_tag);
4946 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4949 if (tags_used != NULL)
4950 *tags_used = LE16_TO_CPU(resp->tags_used);
4951 if (tags_free != NULL)
4952 *tags_free = LE16_TO_CPU(resp->tags_free);
4959 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4960 * @hw: pointer to the hw struct
4961 * @tcmap: TC map for request/release any ignore PFC condition
4962 * @request: request or release ignore PFC condition
4963 * @tcmap_ret: return TCs for which PFC is currently ignored
4964 * @cmd_details: pointer to command details structure or NULL
4966 * This sends out request/release to ignore PFC condition for a TC.
4967 * It will return the TCs for which PFC is currently ignored.
4969 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4970 bool request, u8 *tcmap_ret,
4971 struct i40e_asq_cmd_details *cmd_details)
4973 struct i40e_aq_desc desc;
4974 struct i40e_aqc_pfc_ignore *cmd_resp =
4975 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4976 enum i40e_status_code status;
4978 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4981 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4983 cmd_resp->tc_bitmap = tcmap;
4985 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4988 if (tcmap_ret != NULL)
4989 *tcmap_ret = cmd_resp->tc_bitmap;
4996 * i40e_aq_dcb_updated - DCB Updated Command
4997 * @hw: pointer to the hw struct
4998 * @cmd_details: pointer to command details structure or NULL
5000 * When LLDP is handled in PF this command is used by the PF
5001 * to notify EMP that a DCB setting is modified.
5002 * When LLDP is handled in EMP this command is used by the PF
5003 * to notify EMP whenever one of the following parameters get
5005 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5006 * - PCIRTT in PRTDCB_GENC.PCIRTT
5007 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5008 * EMP will return when the shared RPB settings have been
5009 * recomputed and modified. The retval field in the descriptor
5010 * will be set to 0 when RPB is modified.
5012 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5013 struct i40e_asq_cmd_details *cmd_details)
5015 struct i40e_aq_desc desc;
5016 enum i40e_status_code status;
5018 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5020 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5026 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5027 * @hw: pointer to the hw struct
5028 * @seid: defines the SEID of the switch for which the stats are requested
5029 * @vlan_id: the VLAN ID for which the statistics are requested
5030 * @stat_index: index of the statistics counters block assigned to this VLAN
5031 * @cmd_details: pointer to command details structure or NULL
5033 * XL710 supports 128 smonVlanStats counters.This command is used to
5034 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5037 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5038 u16 vlan_id, u16 *stat_index,
5039 struct i40e_asq_cmd_details *cmd_details)
5041 struct i40e_aq_desc desc;
5042 struct i40e_aqc_add_remove_statistics *cmd_resp =
5043 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5044 enum i40e_status_code status;
5046 if ((seid == 0) || (stat_index == NULL))
5047 return I40E_ERR_PARAM;
5049 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5051 cmd_resp->seid = CPU_TO_LE16(seid);
5052 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5054 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5056 if (!status && stat_index)
5057 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5063 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5064 * @hw: pointer to the hw struct
5065 * @seid: defines the SEID of the switch for which the stats are requested
5066 * @vlan_id: the VLAN ID for which the statistics are requested
5067 * @stat_index: index of the statistics counters block assigned to this VLAN
5068 * @cmd_details: pointer to command details structure or NULL
5070 * XL710 supports 128 smonVlanStats counters.This command is used to
5071 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5074 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5075 u16 vlan_id, u16 stat_index,
5076 struct i40e_asq_cmd_details *cmd_details)
5078 struct i40e_aq_desc desc;
5079 struct i40e_aqc_add_remove_statistics *cmd =
5080 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5081 enum i40e_status_code status;
5084 return I40E_ERR_PARAM;
5086 i40e_fill_default_direct_cmd_desc(&desc,
5087 i40e_aqc_opc_remove_statistics);
5089 cmd->seid = CPU_TO_LE16(seid);
5090 cmd->vlan = CPU_TO_LE16(vlan_id);
5091 cmd->stat_index = CPU_TO_LE16(stat_index);
5093 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5099 * i40e_aq_set_port_parameters - set physical port parameters.
5100 * @hw: pointer to the hw struct
5101 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5102 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5103 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5104 * @double_vlan: if set double VLAN is enabled
5105 * @cmd_details: pointer to command details structure or NULL
5107 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5108 u16 bad_frame_vsi, bool save_bad_pac,
5109 bool pad_short_pac, bool double_vlan,
5110 struct i40e_asq_cmd_details *cmd_details)
5112 struct i40e_aqc_set_port_parameters *cmd;
5113 enum i40e_status_code status;
5114 struct i40e_aq_desc desc;
5115 u16 command_flags = 0;
5117 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5119 i40e_fill_default_direct_cmd_desc(&desc,
5120 i40e_aqc_opc_set_port_parameters);
5122 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5124 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5126 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5128 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5129 cmd->command_flags = CPU_TO_LE16(command_flags);
5131 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5137 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5138 * @hw: pointer to the hw struct
5139 * @seid: seid for the physical port/switching component/vsi
5140 * @buff: Indirect buffer to hold data parameters and response
5141 * @buff_size: Indirect buffer size
5142 * @opcode: Tx scheduler AQ command opcode
5143 * @cmd_details: pointer to command details structure or NULL
5145 * Generic command handler for Tx scheduler AQ commands
5147 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5148 void *buff, u16 buff_size,
5149 enum i40e_admin_queue_opc opcode,
5150 struct i40e_asq_cmd_details *cmd_details)
5152 struct i40e_aq_desc desc;
5153 struct i40e_aqc_tx_sched_ind *cmd =
5154 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5155 enum i40e_status_code status;
5156 bool cmd_param_flag = false;
5159 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5160 case i40e_aqc_opc_configure_vsi_tc_bw:
5161 case i40e_aqc_opc_enable_switching_comp_ets:
5162 case i40e_aqc_opc_modify_switching_comp_ets:
5163 case i40e_aqc_opc_disable_switching_comp_ets:
5164 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5165 case i40e_aqc_opc_configure_switching_comp_bw_config:
5166 cmd_param_flag = true;
5168 case i40e_aqc_opc_query_vsi_bw_config:
5169 case i40e_aqc_opc_query_vsi_ets_sla_config:
5170 case i40e_aqc_opc_query_switching_comp_ets_config:
5171 case i40e_aqc_opc_query_port_ets_config:
5172 case i40e_aqc_opc_query_switching_comp_bw_config:
5173 cmd_param_flag = false;
5176 return I40E_ERR_PARAM;
5179 i40e_fill_default_direct_cmd_desc(&desc, opcode);
5181 /* Indirect command */
5182 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5184 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5185 if (buff_size > I40E_AQ_LARGE_BUF)
5186 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5188 desc.datalen = CPU_TO_LE16(buff_size);
5190 cmd->vsi_seid = CPU_TO_LE16(seid);
5192 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5198 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5199 * @hw: pointer to the hw struct
5201 * @credit: BW limit credits (0 = disabled)
5202 * @max_credit: Max BW limit credits
5203 * @cmd_details: pointer to command details structure or NULL
5205 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5206 u16 seid, u16 credit, u8 max_credit,
5207 struct i40e_asq_cmd_details *cmd_details)
5209 struct i40e_aq_desc desc;
5210 struct i40e_aqc_configure_vsi_bw_limit *cmd =
5211 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5212 enum i40e_status_code status;
5214 i40e_fill_default_direct_cmd_desc(&desc,
5215 i40e_aqc_opc_configure_vsi_bw_limit);
5217 cmd->vsi_seid = CPU_TO_LE16(seid);
5218 cmd->credit = CPU_TO_LE16(credit);
5219 cmd->max_credit = max_credit;
5221 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5227 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5228 * @hw: pointer to the hw struct
5229 * @seid: switching component seid
5230 * @credit: BW limit credits (0 = disabled)
5231 * @max_bw: Max BW limit credits
5232 * @cmd_details: pointer to command details structure or NULL
5234 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5235 u16 seid, u16 credit, u8 max_bw,
5236 struct i40e_asq_cmd_details *cmd_details)
5238 struct i40e_aq_desc desc;
5239 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5240 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5241 enum i40e_status_code status;
5243 i40e_fill_default_direct_cmd_desc(&desc,
5244 i40e_aqc_opc_configure_switching_comp_bw_limit);
5246 cmd->seid = CPU_TO_LE16(seid);
5247 cmd->credit = CPU_TO_LE16(credit);
5248 cmd->max_bw = max_bw;
5250 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5256 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5257 * @hw: pointer to the hw struct
5259 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5260 * @cmd_details: pointer to command details structure or NULL
5262 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5264 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5265 struct i40e_asq_cmd_details *cmd_details)
5267 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5268 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5273 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5274 * @hw: pointer to the hw struct
5276 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5277 * @cmd_details: pointer to command details structure or NULL
5279 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5281 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5282 struct i40e_asq_cmd_details *cmd_details)
5284 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5285 i40e_aqc_opc_configure_vsi_tc_bw,
5290 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5291 * @hw: pointer to the hw struct
5292 * @seid: seid of the switching component connected to Physical Port
5293 * @ets_data: Buffer holding ETS parameters
5294 * @opcode: Tx scheduler AQ command opcode
5295 * @cmd_details: pointer to command details structure or NULL
5297 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5299 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5300 enum i40e_admin_queue_opc opcode,
5301 struct i40e_asq_cmd_details *cmd_details)
5303 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5304 sizeof(*ets_data), opcode, cmd_details);
5308 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5309 * @hw: pointer to the hw struct
5310 * @seid: seid of the switching component
5311 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5312 * @cmd_details: pointer to command details structure or NULL
5314 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5316 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5317 struct i40e_asq_cmd_details *cmd_details)
5319 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5320 i40e_aqc_opc_configure_switching_comp_bw_config,
5325 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5326 * @hw: pointer to the hw struct
5327 * @seid: seid of the switching component
5328 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5329 * @cmd_details: pointer to command details structure or NULL
5331 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5332 struct i40e_hw *hw, u16 seid,
5333 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5334 struct i40e_asq_cmd_details *cmd_details)
5336 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5337 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5342 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5343 * @hw: pointer to the hw struct
5344 * @seid: seid of the VSI
5345 * @bw_data: Buffer to hold VSI BW configuration
5346 * @cmd_details: pointer to command details structure or NULL
5348 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5350 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5351 struct i40e_asq_cmd_details *cmd_details)
5353 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5354 i40e_aqc_opc_query_vsi_bw_config,
5359 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5360 * @hw: pointer to the hw struct
5361 * @seid: seid of the VSI
5362 * @bw_data: Buffer to hold VSI BW configuration per TC
5363 * @cmd_details: pointer to command details structure or NULL
5365 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5367 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5368 struct i40e_asq_cmd_details *cmd_details)
5370 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5371 i40e_aqc_opc_query_vsi_ets_sla_config,
5376 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5377 * @hw: pointer to the hw struct
5378 * @seid: seid of the switching component
5379 * @bw_data: Buffer to hold switching component's per TC BW config
5380 * @cmd_details: pointer to command details structure or NULL
5382 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5384 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5385 struct i40e_asq_cmd_details *cmd_details)
5387 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5388 i40e_aqc_opc_query_switching_comp_ets_config,
5393 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5394 * @hw: pointer to the hw struct
5395 * @seid: seid of the VSI or switching component connected to Physical Port
5396 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5397 * @cmd_details: pointer to command details structure or NULL
5399 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5401 struct i40e_aqc_query_port_ets_config_resp *bw_data,
5402 struct i40e_asq_cmd_details *cmd_details)
5404 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5405 i40e_aqc_opc_query_port_ets_config,
5410 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5411 * @hw: pointer to the hw struct
5412 * @seid: seid of the switching component
5413 * @bw_data: Buffer to hold switching component's BW configuration
5414 * @cmd_details: pointer to command details structure or NULL
5416 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5418 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5419 struct i40e_asq_cmd_details *cmd_details)
5421 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5422 i40e_aqc_opc_query_switching_comp_bw_config,
5427 * i40e_validate_filter_settings
5428 * @hw: pointer to the hardware structure
5429 * @settings: Filter control settings
5431 * Check and validate the filter control settings passed.
5432 * The function checks for the valid filter/context sizes being
5433 * passed for FCoE and PE.
5435 * Returns I40E_SUCCESS if the values passed are valid and within
5436 * range else returns an error.
5438 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5439 struct i40e_filter_control_settings *settings)
5441 u32 fcoe_cntx_size, fcoe_filt_size;
5442 u32 pe_cntx_size, pe_filt_size;
5447 /* Validate FCoE settings passed */
5448 switch (settings->fcoe_filt_num) {
5449 case I40E_HASH_FILTER_SIZE_1K:
5450 case I40E_HASH_FILTER_SIZE_2K:
5451 case I40E_HASH_FILTER_SIZE_4K:
5452 case I40E_HASH_FILTER_SIZE_8K:
5453 case I40E_HASH_FILTER_SIZE_16K:
5454 case I40E_HASH_FILTER_SIZE_32K:
5455 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5456 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5459 return I40E_ERR_PARAM;
5462 switch (settings->fcoe_cntx_num) {
5463 case I40E_DMA_CNTX_SIZE_512:
5464 case I40E_DMA_CNTX_SIZE_1K:
5465 case I40E_DMA_CNTX_SIZE_2K:
5466 case I40E_DMA_CNTX_SIZE_4K:
5467 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5468 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5471 return I40E_ERR_PARAM;
5474 /* Validate PE settings passed */
5475 switch (settings->pe_filt_num) {
5476 case I40E_HASH_FILTER_SIZE_1K:
5477 case I40E_HASH_FILTER_SIZE_2K:
5478 case I40E_HASH_FILTER_SIZE_4K:
5479 case I40E_HASH_FILTER_SIZE_8K:
5480 case I40E_HASH_FILTER_SIZE_16K:
5481 case I40E_HASH_FILTER_SIZE_32K:
5482 case I40E_HASH_FILTER_SIZE_64K:
5483 case I40E_HASH_FILTER_SIZE_128K:
5484 case I40E_HASH_FILTER_SIZE_256K:
5485 case I40E_HASH_FILTER_SIZE_512K:
5486 case I40E_HASH_FILTER_SIZE_1M:
5487 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5488 pe_filt_size <<= (u32)settings->pe_filt_num;
5491 return I40E_ERR_PARAM;
5494 switch (settings->pe_cntx_num) {
5495 case I40E_DMA_CNTX_SIZE_512:
5496 case I40E_DMA_CNTX_SIZE_1K:
5497 case I40E_DMA_CNTX_SIZE_2K:
5498 case I40E_DMA_CNTX_SIZE_4K:
5499 case I40E_DMA_CNTX_SIZE_8K:
5500 case I40E_DMA_CNTX_SIZE_16K:
5501 case I40E_DMA_CNTX_SIZE_32K:
5502 case I40E_DMA_CNTX_SIZE_64K:
5503 case I40E_DMA_CNTX_SIZE_128K:
5504 case I40E_DMA_CNTX_SIZE_256K:
5505 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5506 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5509 return I40E_ERR_PARAM;
5512 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5513 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5514 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5515 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5516 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5517 return I40E_ERR_INVALID_SIZE;
5519 return I40E_SUCCESS;
5523 * i40e_set_filter_control
5524 * @hw: pointer to the hardware structure
5525 * @settings: Filter control settings
5527 * Set the Queue Filters for PE/FCoE and enable filters required
5528 * for a single PF. It is expected that these settings are programmed
5529 * at the driver initialization time.
5531 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5532 struct i40e_filter_control_settings *settings)
5534 enum i40e_status_code ret = I40E_SUCCESS;
5535 u32 hash_lut_size = 0;
5539 return I40E_ERR_PARAM;
5541 /* Validate the input settings */
5542 ret = i40e_validate_filter_settings(hw, settings);
5546 /* Read the PF Queue Filter control register */
5547 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5549 /* Program required PE hash buckets for the PF */
5550 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5551 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5552 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5553 /* Program required PE contexts for the PF */
5554 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5555 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5556 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5558 /* Program required FCoE hash buckets for the PF */
5559 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5560 val |= ((u32)settings->fcoe_filt_num <<
5561 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5562 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5563 /* Program required FCoE DDP contexts for the PF */
5564 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5565 val |= ((u32)settings->fcoe_cntx_num <<
5566 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5567 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5569 /* Program Hash LUT size for the PF */
5570 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5571 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5573 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5574 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5576 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5577 if (settings->enable_fdir)
5578 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5579 if (settings->enable_ethtype)
5580 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5581 if (settings->enable_macvlan)
5582 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5584 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5586 return I40E_SUCCESS;
5590 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5591 * @hw: pointer to the hw struct
5592 * @mac_addr: MAC address to use in the filter
5593 * @ethtype: Ethertype to use in the filter
5594 * @flags: Flags that needs to be applied to the filter
5595 * @vsi_seid: seid of the control VSI
5596 * @queue: VSI queue number to send the packet to
5597 * @is_add: Add control packet filter if True else remove
5598 * @stats: Structure to hold information on control filter counts
5599 * @cmd_details: pointer to command details structure or NULL
5601 * This command will Add or Remove control packet filter for a control VSI.
5602 * In return it will update the total number of perfect filter count in
5605 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5606 u8 *mac_addr, u16 ethtype, u16 flags,
5607 u16 vsi_seid, u16 queue, bool is_add,
5608 struct i40e_control_filter_stats *stats,
5609 struct i40e_asq_cmd_details *cmd_details)
5611 struct i40e_aq_desc desc;
5612 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5613 (struct i40e_aqc_add_remove_control_packet_filter *)
5615 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5616 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5618 enum i40e_status_code status;
5621 return I40E_ERR_PARAM;
5624 i40e_fill_default_direct_cmd_desc(&desc,
5625 i40e_aqc_opc_add_control_packet_filter);
5626 cmd->queue = CPU_TO_LE16(queue);
5628 i40e_fill_default_direct_cmd_desc(&desc,
5629 i40e_aqc_opc_remove_control_packet_filter);
5633 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5634 I40E_NONDMA_TO_NONDMA);
5636 cmd->etype = CPU_TO_LE16(ethtype);
5637 cmd->flags = CPU_TO_LE16(flags);
5638 cmd->seid = CPU_TO_LE16(vsi_seid);
5640 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5642 if (!status && stats) {
5643 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5644 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5645 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5646 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5653 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5654 * @hw: pointer to the hw struct
5655 * @seid: VSI seid to add ethertype filter from
5657 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5660 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5661 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5662 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5663 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5664 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5665 enum i40e_status_code status;
5667 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5668 seid, 0, true, NULL,
5671 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5675 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5676 * @filters: list of cloud filters
5677 * @filter_count: length of list
5679 * There's an issue in the device where the Geneve VNI layout needs
5680 * to be shifted 1 byte over from the VxLAN VNI
5682 STATIC void i40e_fix_up_geneve_vni(
5683 struct i40e_aqc_cloud_filters_element_data *filters,
5686 struct i40e_aqc_cloud_filters_element_data *f = filters;
5689 for (i = 0; i < filter_count; i++) {
5693 tnl_type = (LE16_TO_CPU(f[i].flags) &
5694 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5695 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5696 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5697 ti = LE32_TO_CPU(f[i].tenant_id);
5698 f[i].tenant_id = CPU_TO_LE32(ti << 8);
5704 * i40e_aq_add_cloud_filters
5705 * @hw: pointer to the hardware structure
5706 * @seid: VSI seid to add cloud filters from
5707 * @filters: Buffer which contains the filters to be added
5708 * @filter_count: number of filters contained in the buffer
5710 * Set the cloud filters for a given VSI. The contents of the
5711 * i40e_aqc_cloud_filters_element_data are filled
5712 * in by the caller of the function.
5715 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5717 struct i40e_aqc_cloud_filters_element_data *filters,
5720 struct i40e_aq_desc desc;
5721 struct i40e_aqc_add_remove_cloud_filters *cmd =
5722 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5723 enum i40e_status_code status;
5726 i40e_fill_default_direct_cmd_desc(&desc,
5727 i40e_aqc_opc_add_cloud_filters);
5729 buff_len = filter_count * sizeof(*filters);
5730 desc.datalen = CPU_TO_LE16(buff_len);
5731 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5732 cmd->num_filters = filter_count;
5733 cmd->seid = CPU_TO_LE16(seid);
5735 i40e_fix_up_geneve_vni(filters, filter_count);
5737 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5743 * i40e_aq_add_cloud_filters_bb
5744 * @hw: pointer to the hardware structure
5745 * @seid: VSI seid to add cloud filters from
5746 * @filters: Buffer which contains the filters in big buffer to be added
5747 * @filter_count: number of filters contained in the buffer
5749 * Set the cloud filters for a given VSI. The contents of the
5750 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5754 enum i40e_status_code
5755 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5756 struct i40e_aqc_cloud_filters_element_bb *filters,
5759 struct i40e_aq_desc desc;
5760 struct i40e_aqc_add_remove_cloud_filters *cmd =
5761 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5762 enum i40e_status_code status;
5766 i40e_fill_default_direct_cmd_desc(&desc,
5767 i40e_aqc_opc_add_cloud_filters);
5769 buff_len = filter_count * sizeof(*filters);
5770 desc.datalen = CPU_TO_LE16(buff_len);
5771 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5772 cmd->num_filters = filter_count;
5773 cmd->seid = CPU_TO_LE16(seid);
5774 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5776 for (i = 0; i < filter_count; i++) {
5780 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5781 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5782 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5784 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5785 * one more byte further than normally used for Tenant ID in
5786 * other tunnel types.
5788 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5789 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5790 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5794 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5800 * i40e_aq_rem_cloud_filters
5801 * @hw: pointer to the hardware structure
5802 * @seid: VSI seid to remove cloud filters from
5803 * @filters: Buffer which contains the filters to be removed
5804 * @filter_count: number of filters contained in the buffer
5806 * Remove the cloud filters for a given VSI. The contents of the
5807 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5811 enum i40e_status_code
5812 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5813 struct i40e_aqc_cloud_filters_element_data *filters,
5816 struct i40e_aq_desc desc;
5817 struct i40e_aqc_add_remove_cloud_filters *cmd =
5818 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5819 enum i40e_status_code status;
5822 i40e_fill_default_direct_cmd_desc(&desc,
5823 i40e_aqc_opc_remove_cloud_filters);
5825 buff_len = filter_count * sizeof(*filters);
5826 desc.datalen = CPU_TO_LE16(buff_len);
5827 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5828 cmd->num_filters = filter_count;
5829 cmd->seid = CPU_TO_LE16(seid);
5831 i40e_fix_up_geneve_vni(filters, filter_count);
5833 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5839 * i40e_aq_rem_cloud_filters_bb
5840 * @hw: pointer to the hardware structure
5841 * @seid: VSI seid to remove cloud filters from
5842 * @filters: Buffer which contains the filters in big buffer to be removed
5843 * @filter_count: number of filters contained in the buffer
5845 * Remove the big buffer cloud filters for a given VSI. The contents of the
5846 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5850 enum i40e_status_code
5851 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5852 struct i40e_aqc_cloud_filters_element_bb *filters,
5855 struct i40e_aq_desc desc;
5856 struct i40e_aqc_add_remove_cloud_filters *cmd =
5857 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5858 enum i40e_status_code status;
5862 i40e_fill_default_direct_cmd_desc(&desc,
5863 i40e_aqc_opc_remove_cloud_filters);
5865 buff_len = filter_count * sizeof(*filters);
5866 desc.datalen = CPU_TO_LE16(buff_len);
5867 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5868 cmd->num_filters = filter_count;
5869 cmd->seid = CPU_TO_LE16(seid);
5870 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5872 for (i = 0; i < filter_count; i++) {
5876 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5877 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5878 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5880 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5881 * one more byte further than normally used for Tenant ID in
5882 * other tunnel types.
5884 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5885 ti = LE32_TO_CPU(filters[i].element.tenant_id);
5886 filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5890 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5896 * i40e_aq_replace_cloud_filters - Replace cloud filter command
5897 * @hw: pointer to the hw struct
5898 * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5899 * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5903 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5904 struct i40e_aqc_replace_cloud_filters_cmd *filters,
5905 struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5907 struct i40e_aq_desc desc;
5908 struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5909 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5910 enum i40e_status_code status = I40E_SUCCESS;
5913 /* X722 doesn't support this command */
5914 if (hw->mac.type == I40E_MAC_X722)
5915 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5917 /* need FW version greater than 6.00 */
5918 if (hw->aq.fw_maj_ver < 6)
5919 return I40E_NOT_SUPPORTED;
5921 i40e_fill_default_direct_cmd_desc(&desc,
5922 i40e_aqc_opc_replace_cloud_filters);
5924 desc.datalen = CPU_TO_LE16(32);
5925 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5926 cmd->old_filter_type = filters->old_filter_type;
5927 cmd->new_filter_type = filters->new_filter_type;
5928 cmd->valid_flags = filters->valid_flags;
5929 cmd->tr_bit = filters->tr_bit;
5930 cmd->tr_bit2 = filters->tr_bit2;
5932 status = i40e_asq_send_command(hw, &desc, cmd_buf,
5933 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL);
5935 /* for get cloud filters command */
5936 for (i = 0; i < 32; i += 4) {
5937 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5938 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5939 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5940 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5948 * i40e_aq_alternate_write
5949 * @hw: pointer to the hardware structure
5950 * @reg_addr0: address of first dword to be read
5951 * @reg_val0: value to be written under 'reg_addr0'
5952 * @reg_addr1: address of second dword to be read
5953 * @reg_val1: value to be written under 'reg_addr1'
5955 * Write one or two dwords to alternate structure. Fields are indicated
5956 * by 'reg_addr0' and 'reg_addr1' register numbers.
5959 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5960 u32 reg_addr0, u32 reg_val0,
5961 u32 reg_addr1, u32 reg_val1)
5963 struct i40e_aq_desc desc;
5964 struct i40e_aqc_alternate_write *cmd_resp =
5965 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5966 enum i40e_status_code status;
5968 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5969 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5970 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5971 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5972 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5974 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5980 * i40e_aq_alternate_write_indirect
5981 * @hw: pointer to the hardware structure
5982 * @addr: address of a first register to be modified
5983 * @dw_count: number of alternate structure fields to write
5984 * @buffer: pointer to the command buffer
5986 * Write 'dw_count' dwords from 'buffer' to alternate structure
5987 * starting at 'addr'.
5990 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5991 u32 addr, u32 dw_count, void *buffer)
5993 struct i40e_aq_desc desc;
5994 struct i40e_aqc_alternate_ind_write *cmd_resp =
5995 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5996 enum i40e_status_code status;
5999 return I40E_ERR_PARAM;
6001 /* Indirect command */
6002 i40e_fill_default_direct_cmd_desc(&desc,
6003 i40e_aqc_opc_alternate_write_indirect);
6005 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6006 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6007 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6008 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6010 cmd_resp->address = CPU_TO_LE32(addr);
6011 cmd_resp->length = CPU_TO_LE32(dw_count);
6013 status = i40e_asq_send_command(hw, &desc, buffer,
6014 I40E_LO_DWORD(4*dw_count), NULL);
6020 * i40e_aq_alternate_read
6021 * @hw: pointer to the hardware structure
6022 * @reg_addr0: address of first dword to be read
6023 * @reg_val0: pointer for data read from 'reg_addr0'
6024 * @reg_addr1: address of second dword to be read
6025 * @reg_val1: pointer for data read from 'reg_addr1'
6027 * Read one or two dwords from alternate structure. Fields are indicated
6028 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6029 * is not passed then only register at 'reg_addr0' is read.
6032 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6033 u32 reg_addr0, u32 *reg_val0,
6034 u32 reg_addr1, u32 *reg_val1)
6036 struct i40e_aq_desc desc;
6037 struct i40e_aqc_alternate_write *cmd_resp =
6038 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6039 enum i40e_status_code status;
6041 if (reg_val0 == NULL)
6042 return I40E_ERR_PARAM;
6044 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6045 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6046 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6048 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6050 if (status == I40E_SUCCESS) {
6051 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6053 if (reg_val1 != NULL)
6054 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6061 * i40e_aq_alternate_read_indirect
6062 * @hw: pointer to the hardware structure
6063 * @addr: address of the alternate structure field
6064 * @dw_count: number of alternate structure fields to read
6065 * @buffer: pointer to the command buffer
6067 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6068 * place them in 'buffer'. The buffer should be allocated by caller.
6071 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6072 u32 addr, u32 dw_count, void *buffer)
6074 struct i40e_aq_desc desc;
6075 struct i40e_aqc_alternate_ind_write *cmd_resp =
6076 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6077 enum i40e_status_code status;
6080 return I40E_ERR_PARAM;
6082 /* Indirect command */
6083 i40e_fill_default_direct_cmd_desc(&desc,
6084 i40e_aqc_opc_alternate_read_indirect);
6086 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6087 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6088 if (dw_count > (I40E_AQ_LARGE_BUF/4))
6089 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6091 cmd_resp->address = CPU_TO_LE32(addr);
6092 cmd_resp->length = CPU_TO_LE32(dw_count);
6094 status = i40e_asq_send_command(hw, &desc, buffer,
6095 I40E_LO_DWORD(4*dw_count), NULL);
6101 * i40e_aq_alternate_clear
6102 * @hw: pointer to the HW structure.
6104 * Clear the alternate structures of the port from which the function
6108 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6110 struct i40e_aq_desc desc;
6111 enum i40e_status_code status;
6113 i40e_fill_default_direct_cmd_desc(&desc,
6114 i40e_aqc_opc_alternate_clear_port);
6116 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6122 * i40e_aq_alternate_write_done
6123 * @hw: pointer to the HW structure.
6124 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6125 * @reset_needed: indicates the SW should trigger GLOBAL reset
6127 * Indicates to the FW that alternate structures have been changed.
6130 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6131 u8 bios_mode, bool *reset_needed)
6133 struct i40e_aq_desc desc;
6134 struct i40e_aqc_alternate_write_done *cmd =
6135 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6136 enum i40e_status_code status;
6138 if (reset_needed == NULL)
6139 return I40E_ERR_PARAM;
6141 i40e_fill_default_direct_cmd_desc(&desc,
6142 i40e_aqc_opc_alternate_write_done);
6144 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6146 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6147 if (!status && reset_needed)
6148 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6149 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6155 * i40e_aq_set_oem_mode
6156 * @hw: pointer to the HW structure.
6157 * @oem_mode: the OEM mode to be used
6159 * Sets the device to a specific operating mode. Currently the only supported
6160 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
6163 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6166 struct i40e_aq_desc desc;
6167 struct i40e_aqc_alternate_write_done *cmd =
6168 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6169 enum i40e_status_code status;
6171 i40e_fill_default_direct_cmd_desc(&desc,
6172 i40e_aqc_opc_alternate_set_mode);
6174 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6176 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6182 * i40e_aq_resume_port_tx
6183 * @hw: pointer to the hardware structure
6184 * @cmd_details: pointer to command details structure or NULL
6186 * Resume port's Tx traffic
6188 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6189 struct i40e_asq_cmd_details *cmd_details)
6191 struct i40e_aq_desc desc;
6192 enum i40e_status_code status;
6194 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6196 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6202 * i40e_set_pci_config_data - store PCI bus info
6203 * @hw: pointer to hardware structure
6204 * @link_status: the link status word from PCI config space
6206 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6208 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6210 hw->bus.type = i40e_bus_type_pci_express;
6212 switch (link_status & I40E_PCI_LINK_WIDTH) {
6213 case I40E_PCI_LINK_WIDTH_1:
6214 hw->bus.width = i40e_bus_width_pcie_x1;
6216 case I40E_PCI_LINK_WIDTH_2:
6217 hw->bus.width = i40e_bus_width_pcie_x2;
6219 case I40E_PCI_LINK_WIDTH_4:
6220 hw->bus.width = i40e_bus_width_pcie_x4;
6222 case I40E_PCI_LINK_WIDTH_8:
6223 hw->bus.width = i40e_bus_width_pcie_x8;
6226 hw->bus.width = i40e_bus_width_unknown;
6230 switch (link_status & I40E_PCI_LINK_SPEED) {
6231 case I40E_PCI_LINK_SPEED_2500:
6232 hw->bus.speed = i40e_bus_speed_2500;
6234 case I40E_PCI_LINK_SPEED_5000:
6235 hw->bus.speed = i40e_bus_speed_5000;
6237 case I40E_PCI_LINK_SPEED_8000:
6238 hw->bus.speed = i40e_bus_speed_8000;
6241 hw->bus.speed = i40e_bus_speed_unknown;
6247 * i40e_aq_debug_dump
6248 * @hw: pointer to the hardware structure
6249 * @cluster_id: specific cluster to dump
6250 * @table_id: table id within cluster
6251 * @start_index: index of line in the block to read
6252 * @buff_size: dump buffer size
6253 * @buff: dump buffer
6254 * @ret_buff_size: actual buffer size returned
6255 * @ret_next_table: next block to read
6256 * @ret_next_index: next index to read
6257 * @cmd_details: pointer to command details structure or NULL
6259 * Dump internal FW/HW data for debug purposes.
6262 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6263 u8 table_id, u32 start_index, u16 buff_size,
6264 void *buff, u16 *ret_buff_size,
6265 u8 *ret_next_table, u32 *ret_next_index,
6266 struct i40e_asq_cmd_details *cmd_details)
6268 struct i40e_aq_desc desc;
6269 struct i40e_aqc_debug_dump_internals *cmd =
6270 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6271 struct i40e_aqc_debug_dump_internals *resp =
6272 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6273 enum i40e_status_code status;
6275 if (buff_size == 0 || !buff)
6276 return I40E_ERR_PARAM;
6278 i40e_fill_default_direct_cmd_desc(&desc,
6279 i40e_aqc_opc_debug_dump_internals);
6280 /* Indirect Command */
6281 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6282 if (buff_size > I40E_AQ_LARGE_BUF)
6283 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6285 cmd->cluster_id = cluster_id;
6286 cmd->table_id = table_id;
6287 cmd->idx = CPU_TO_LE32(start_index);
6289 desc.datalen = CPU_TO_LE16(buff_size);
6291 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6293 if (ret_buff_size != NULL)
6294 *ret_buff_size = LE16_TO_CPU(desc.datalen);
6295 if (ret_next_table != NULL)
6296 *ret_next_table = resp->table_id;
6297 if (ret_next_index != NULL)
6298 *ret_next_index = LE32_TO_CPU(resp->idx);
6305 * i40e_read_bw_from_alt_ram
6306 * @hw: pointer to the hardware structure
6307 * @max_bw: pointer for max_bw read
6308 * @min_bw: pointer for min_bw read
6309 * @min_valid: pointer for bool that is true if min_bw is a valid value
6310 * @max_valid: pointer for bool that is true if max_bw is a valid value
6312 * Read bw from the alternate ram for the given pf
6314 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6315 u32 *max_bw, u32 *min_bw,
6316 bool *min_valid, bool *max_valid)
6318 enum i40e_status_code status;
6319 u32 max_bw_addr, min_bw_addr;
6321 /* Calculate the address of the min/max bw registers */
6322 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6323 I40E_ALT_STRUCT_MAX_BW_OFFSET +
6324 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6325 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6326 I40E_ALT_STRUCT_MIN_BW_OFFSET +
6327 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6329 /* Read the bandwidths from alt ram */
6330 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6331 min_bw_addr, min_bw);
6333 if (*min_bw & I40E_ALT_BW_VALID_MASK)
6338 if (*max_bw & I40E_ALT_BW_VALID_MASK)
6347 * i40e_aq_configure_partition_bw
6348 * @hw: pointer to the hardware structure
6349 * @bw_data: Buffer holding valid pfs and bw limits
6350 * @cmd_details: pointer to command details
6352 * Configure partitions guaranteed/max bw
6354 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6355 struct i40e_aqc_configure_partition_bw_data *bw_data,
6356 struct i40e_asq_cmd_details *cmd_details)
6358 enum i40e_status_code status;
6359 struct i40e_aq_desc desc;
6360 u16 bwd_size = sizeof(*bw_data);
6362 i40e_fill_default_direct_cmd_desc(&desc,
6363 i40e_aqc_opc_configure_partition_bw);
6365 /* Indirect command */
6366 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6367 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6369 desc.datalen = CPU_TO_LE16(bwd_size);
6371 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6377 * i40e_read_phy_register_clause22
6378 * @hw: pointer to the HW structure
6379 * @reg: register address in the page
6380 * @phy_addr: PHY address on MDIO interface
6381 * @value: PHY register value
6383 * Reads specified PHY register value
6385 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6386 u16 reg, u8 phy_addr, u16 *value)
6388 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6389 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6393 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6394 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6395 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6396 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6397 (I40E_GLGEN_MSCA_MDICMD_MASK);
6398 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6400 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6401 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6402 status = I40E_SUCCESS;
6405 i40e_usec_delay(10);
6410 i40e_debug(hw, I40E_DEBUG_PHY,
6411 "PHY: Can't write command to external PHY.\n");
6413 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6414 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6415 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6422 * i40e_write_phy_register_clause22
6423 * @hw: pointer to the HW structure
6424 * @reg: register address in the page
6425 * @phy_addr: PHY address on MDIO interface
6426 * @value: PHY register value
6428 * Writes specified PHY register value
6430 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6431 u16 reg, u8 phy_addr, u16 value)
6433 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6434 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6438 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6439 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6441 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6442 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6443 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6444 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6445 (I40E_GLGEN_MSCA_MDICMD_MASK);
6447 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6449 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6450 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6451 status = I40E_SUCCESS;
6454 i40e_usec_delay(10);
6462 * i40e_read_phy_register_clause45
6463 * @hw: pointer to the HW structure
6464 * @page: registers page number
6465 * @reg: register address in the page
6466 * @phy_addr: PHY address on MDIO interface
6467 * @value: PHY register value
6469 * Reads specified PHY register value
6471 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6472 u8 page, u16 reg, u8 phy_addr, u16 *value)
6474 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6477 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6479 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6480 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6481 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6482 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6483 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6484 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6485 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6486 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6488 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6489 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6490 status = I40E_SUCCESS;
6493 i40e_usec_delay(10);
6498 i40e_debug(hw, I40E_DEBUG_PHY,
6499 "PHY: Can't write command to external PHY.\n");
6503 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6504 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6505 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6506 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6507 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6508 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6509 status = I40E_ERR_TIMEOUT;
6511 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6513 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6514 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6515 status = I40E_SUCCESS;
6518 i40e_usec_delay(10);
6523 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6524 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6525 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6527 i40e_debug(hw, I40E_DEBUG_PHY,
6528 "PHY: Can't read register value from external PHY.\n");
6536 * i40e_write_phy_register_clause45
6537 * @hw: pointer to the HW structure
6538 * @page: registers page number
6539 * @reg: register address in the page
6540 * @phy_addr: PHY address on MDIO interface
6541 * @value: PHY register value
6543 * Writes value to specified PHY register
6545 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6546 u8 page, u16 reg, u8 phy_addr, u16 value)
6548 enum i40e_status_code status = I40E_ERR_TIMEOUT;
6551 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6553 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6554 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6555 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6556 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6557 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6558 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6559 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6560 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6562 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6563 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6564 status = I40E_SUCCESS;
6567 i40e_usec_delay(10);
6571 i40e_debug(hw, I40E_DEBUG_PHY,
6572 "PHY: Can't write command to external PHY.\n");
6576 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6577 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6579 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6580 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6581 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6582 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6583 (I40E_GLGEN_MSCA_MDICMD_MASK) |
6584 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6585 status = I40E_ERR_TIMEOUT;
6587 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6589 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6590 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6591 status = I40E_SUCCESS;
6594 i40e_usec_delay(10);
6603 * i40e_write_phy_register
6604 * @hw: pointer to the HW structure
6605 * @page: registers page number
6606 * @reg: register address in the page
6607 * @phy_addr: PHY address on MDIO interface
6608 * @value: PHY register value
6610 * Writes value to specified PHY register
6612 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6613 u8 page, u16 reg, u8 phy_addr, u16 value)
6615 enum i40e_status_code status;
6617 switch (hw->device_id) {
6618 case I40E_DEV_ID_1G_BASE_T_X722:
6619 status = i40e_write_phy_register_clause22(hw,
6620 reg, phy_addr, value);
6622 case I40E_DEV_ID_10G_BASE_T:
6623 case I40E_DEV_ID_10G_BASE_T4:
6624 case I40E_DEV_ID_10G_BASE_T_BC:
6625 case I40E_DEV_ID_10G_BASE_T_X722:
6626 case I40E_DEV_ID_25G_B:
6627 case I40E_DEV_ID_25G_SFP28:
6628 status = i40e_write_phy_register_clause45(hw,
6629 page, reg, phy_addr, value);
6632 status = I40E_ERR_UNKNOWN_PHY;
6640 * i40e_read_phy_register
6641 * @hw: pointer to the HW structure
6642 * @page: registers page number
6643 * @reg: register address in the page
6644 * @phy_addr: PHY address on MDIO interface
6645 * @value: PHY register value
6647 * Reads specified PHY register value
6649 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6650 u8 page, u16 reg, u8 phy_addr, u16 *value)
6652 enum i40e_status_code status;
6654 switch (hw->device_id) {
6655 case I40E_DEV_ID_1G_BASE_T_X722:
6656 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6659 case I40E_DEV_ID_10G_BASE_T:
6660 case I40E_DEV_ID_10G_BASE_T4:
6661 case I40E_DEV_ID_10G_BASE_T_X722:
6662 case I40E_DEV_ID_25G_B:
6663 case I40E_DEV_ID_25G_SFP28:
6664 status = i40e_read_phy_register_clause45(hw, page, reg,
6668 status = I40E_ERR_UNKNOWN_PHY;
6676 * i40e_get_phy_address
6677 * @hw: pointer to the HW structure
6678 * @dev_num: PHY port num that address we want
6680 * Gets PHY address for current port
6682 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6684 u8 port_num = (u8)hw->func_caps.mdio_port_num;
6685 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6687 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6691 * i40e_blink_phy_led
6692 * @hw: pointer to the HW structure
6693 * @time: time how long led will blinks in secs
6694 * @interval: gap between LED on and off in msecs
6696 * Blinks PHY link LED
6698 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6699 u32 time, u32 interval)
6701 enum i40e_status_code status = I40E_SUCCESS;
6706 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6710 i = rd32(hw, I40E_PFGEN_PORTNUM);
6711 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6712 phy_addr = i40e_get_phy_address(hw, port_num);
6714 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6716 status = i40e_read_phy_register_clause45(hw,
6717 I40E_PHY_COM_REG_PAGE,
6721 goto phy_blinking_end;
6723 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6725 status = i40e_write_phy_register_clause45(hw,
6726 I40E_PHY_COM_REG_PAGE,
6730 goto phy_blinking_end;
6735 if (time > 0 && interval > 0) {
6736 for (i = 0; i < time * 1000; i += interval) {
6737 status = i40e_read_phy_register_clause45(hw,
6738 I40E_PHY_COM_REG_PAGE,
6739 led_addr, phy_addr, &led_reg);
6741 goto restore_config;
6742 if (led_reg & I40E_PHY_LED_MANUAL_ON)
6745 led_reg = I40E_PHY_LED_MANUAL_ON;
6746 status = i40e_write_phy_register_clause45(hw,
6747 I40E_PHY_COM_REG_PAGE,
6748 led_addr, phy_addr, led_reg);
6750 goto restore_config;
6751 i40e_msec_delay(interval);
6756 status = i40e_write_phy_register_clause45(hw,
6757 I40E_PHY_COM_REG_PAGE,
6758 led_addr, phy_addr, led_ctl);
6765 * i40e_led_get_reg - read LED register
6766 * @hw: pointer to the HW structure
6767 * @led_addr: LED register address
6768 * @reg_val: read register value
6770 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6773 enum i40e_status_code status;
6777 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6778 status = i40e_aq_get_phy_register(hw,
6779 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6780 I40E_PHY_COM_REG_PAGE, true,
6781 I40E_PHY_LED_PROV_REG_1,
6784 phy_addr = i40e_get_phy_address(hw, hw->port);
6785 status = i40e_read_phy_register_clause45(hw,
6786 I40E_PHY_COM_REG_PAGE,
6794 * i40e_led_set_reg - write LED register
6795 * @hw: pointer to the HW structure
6796 * @led_addr: LED register address
6797 * @reg_val: register value to write
6799 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6802 enum i40e_status_code status;
6805 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6806 status = i40e_aq_set_phy_register(hw,
6807 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6808 I40E_PHY_COM_REG_PAGE, true,
6809 I40E_PHY_LED_PROV_REG_1,
6812 phy_addr = i40e_get_phy_address(hw, hw->port);
6813 status = i40e_write_phy_register_clause45(hw,
6814 I40E_PHY_COM_REG_PAGE,
6823 * i40e_led_get_phy - return current on/off mode
6824 * @hw: pointer to the hw struct
6825 * @led_addr: address of led register to use
6826 * @val: original value of register to use
6829 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6832 enum i40e_status_code status = I40E_SUCCESS;
6839 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6840 status = i40e_aq_get_phy_register(hw,
6841 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6842 I40E_PHY_COM_REG_PAGE, true,
6843 I40E_PHY_LED_PROV_REG_1,
6845 if (status == I40E_SUCCESS)
6846 *val = (u16)reg_val_aq;
6849 temp_addr = I40E_PHY_LED_PROV_REG_1;
6850 phy_addr = i40e_get_phy_address(hw, hw->port);
6851 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6853 status = i40e_read_phy_register_clause45(hw,
6854 I40E_PHY_COM_REG_PAGE,
6855 temp_addr, phy_addr,
6860 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6861 *led_addr = temp_addr;
6870 * @hw: pointer to the HW structure
6871 * @on: true or false
6872 * @led_addr: address of led register to use
6873 * @mode: original val plus bit for set or ignore
6875 * Set led's on or off when controlled by the PHY
6878 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6879 u16 led_addr, u32 mode)
6881 enum i40e_status_code status = I40E_SUCCESS;
6885 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6889 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6891 status = i40e_led_set_reg(hw, led_addr, led_reg);
6895 status = i40e_led_get_reg(hw, led_addr, &led_reg);
6897 goto restore_config;
6899 led_reg = I40E_PHY_LED_MANUAL_ON;
6902 status = i40e_led_set_reg(hw, led_addr, led_reg);
6904 goto restore_config;
6905 if (mode & I40E_PHY_LED_MODE_ORIG) {
6906 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6907 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6912 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6915 #endif /* PF_DRIVER */
6918 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6919 * @hw: pointer to the hw struct
6920 * @reg_addr: register address
6921 * @reg_val: ptr to register value
6922 * @cmd_details: pointer to command details structure or NULL
6924 * Use the firmware to read the Rx control register,
6925 * especially useful if the Rx unit is under heavy pressure
6927 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6928 u32 reg_addr, u32 *reg_val,
6929 struct i40e_asq_cmd_details *cmd_details)
6931 struct i40e_aq_desc desc;
6932 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6933 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6934 enum i40e_status_code status;
6936 if (reg_val == NULL)
6937 return I40E_ERR_PARAM;
6939 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6941 cmd_resp->address = CPU_TO_LE32(reg_addr);
6943 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6945 if (status == I40E_SUCCESS)
6946 *reg_val = LE32_TO_CPU(cmd_resp->value);
6952 * i40e_read_rx_ctl - read from an Rx control register
6953 * @hw: pointer to the hw struct
6954 * @reg_addr: register address
6956 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6958 enum i40e_status_code status = I40E_SUCCESS;
6963 use_register = (((hw->aq.api_maj_ver == 1) &&
6964 (hw->aq.api_min_ver < 5)) ||
6965 (hw->mac.type == I40E_MAC_X722));
6966 if (!use_register) {
6968 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6969 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6976 /* if the AQ access failed, try the old-fashioned way */
6977 if (status || use_register)
6978 val = rd32(hw, reg_addr);
6984 * i40e_aq_rx_ctl_write_register
6985 * @hw: pointer to the hw struct
6986 * @reg_addr: register address
6987 * @reg_val: register value
6988 * @cmd_details: pointer to command details structure or NULL
6990 * Use the firmware to write to an Rx control register,
6991 * especially useful if the Rx unit is under heavy pressure
6993 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6994 u32 reg_addr, u32 reg_val,
6995 struct i40e_asq_cmd_details *cmd_details)
6997 struct i40e_aq_desc desc;
6998 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6999 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7000 enum i40e_status_code status;
7002 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7004 cmd->address = CPU_TO_LE32(reg_addr);
7005 cmd->value = CPU_TO_LE32(reg_val);
7007 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7013 * i40e_write_rx_ctl - write to an Rx control register
7014 * @hw: pointer to the hw struct
7015 * @reg_addr: register address
7016 * @reg_val: register value
7018 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7020 enum i40e_status_code status = I40E_SUCCESS;
7024 use_register = (((hw->aq.api_maj_ver == 1) &&
7025 (hw->aq.api_min_ver < 5)) ||
7026 (hw->mac.type == I40E_MAC_X722));
7027 if (!use_register) {
7029 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7031 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7038 /* if the AQ access failed, try the old-fashioned way */
7039 if (status || use_register)
7040 wr32(hw, reg_addr, reg_val);
7045 * i40e_aq_set_phy_register
7046 * @hw: pointer to the hw struct
7047 * @phy_select: select which phy should be accessed
7048 * @dev_addr: PHY device address
7049 * @page_change: enable auto page change
7050 * @reg_addr: PHY register address
7051 * @reg_val: new register value
7052 * @cmd_details: pointer to command details structure or NULL
7054 * Write the external PHY register.
7056 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7057 u8 phy_select, u8 dev_addr, bool page_change,
7058 u32 reg_addr, u32 reg_val,
7059 struct i40e_asq_cmd_details *cmd_details)
7061 struct i40e_aq_desc desc;
7062 struct i40e_aqc_phy_register_access *cmd =
7063 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7064 enum i40e_status_code status;
7066 i40e_fill_default_direct_cmd_desc(&desc,
7067 i40e_aqc_opc_set_phy_register);
7069 cmd->phy_interface = phy_select;
7070 cmd->dev_addres = dev_addr;
7071 cmd->reg_address = CPU_TO_LE32(reg_addr);
7072 cmd->reg_value = CPU_TO_LE32(reg_val);
7075 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7077 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7083 * i40e_aq_get_phy_register
7084 * @hw: pointer to the hw struct
7085 * @phy_select: select which phy should be accessed
7086 * @dev_addr: PHY device address
7087 * @page_change: enable auto page change
7088 * @reg_addr: PHY register address
7089 * @reg_val: read register value
7090 * @cmd_details: pointer to command details structure or NULL
7092 * Read the external PHY register.
7094 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7095 u8 phy_select, u8 dev_addr, bool page_change,
7096 u32 reg_addr, u32 *reg_val,
7097 struct i40e_asq_cmd_details *cmd_details)
7099 struct i40e_aq_desc desc;
7100 struct i40e_aqc_phy_register_access *cmd =
7101 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7102 enum i40e_status_code status;
7104 i40e_fill_default_direct_cmd_desc(&desc,
7105 i40e_aqc_opc_get_phy_register);
7107 cmd->phy_interface = phy_select;
7108 cmd->dev_addres = dev_addr;
7109 cmd->reg_address = CPU_TO_LE32(reg_addr);
7112 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7114 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7116 *reg_val = LE32_TO_CPU(cmd->reg_value);
7121 #endif /* PF_DRIVER */
7125 * i40e_aq_send_msg_to_pf
7126 * @hw: pointer to the hardware structure
7127 * @v_opcode: opcodes for VF-PF communication
7128 * @v_retval: return error code
7129 * @msg: pointer to the msg buffer
7130 * @msglen: msg length
7131 * @cmd_details: pointer to command details
7133 * Send message to PF driver using admin queue. By default, this message
7134 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7135 * completion before returning.
7137 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7138 enum virtchnl_ops v_opcode,
7139 enum i40e_status_code v_retval,
7140 u8 *msg, u16 msglen,
7141 struct i40e_asq_cmd_details *cmd_details)
7143 struct i40e_aq_desc desc;
7144 struct i40e_asq_cmd_details details;
7145 enum i40e_status_code status;
7147 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7148 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7149 desc.cookie_high = CPU_TO_LE32(v_opcode);
7150 desc.cookie_low = CPU_TO_LE32(v_retval);
7152 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7153 | I40E_AQ_FLAG_RD));
7154 if (msglen > I40E_AQ_LARGE_BUF)
7155 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7156 desc.datalen = CPU_TO_LE16(msglen);
7159 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7160 details.async = true;
7161 cmd_details = &details;
7163 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7164 msglen, cmd_details);
7169 * i40e_vf_parse_hw_config
7170 * @hw: pointer to the hardware structure
7171 * @msg: pointer to the virtual channel VF resource structure
7173 * Given a VF resource message from the PF, populate the hw struct
7174 * with appropriate information.
7176 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7177 struct virtchnl_vf_resource *msg)
7179 struct virtchnl_vsi_resource *vsi_res;
7182 vsi_res = &msg->vsi_res[0];
7184 hw->dev_caps.num_vsis = msg->num_vsis;
7185 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7186 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7187 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7188 hw->dev_caps.dcb = msg->vf_cap_flags &
7189 VIRTCHNL_VF_OFFLOAD_L2;
7190 hw->dev_caps.iwarp = (msg->vf_cap_flags &
7191 VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7192 for (i = 0; i < msg->num_vsis; i++) {
7193 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7194 i40e_memcpy(hw->mac.perm_addr,
7195 vsi_res->default_mac_addr,
7197 I40E_NONDMA_TO_NONDMA);
7198 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7200 I40E_NONDMA_TO_NONDMA);
7208 * @hw: pointer to the hardware structure
7210 * Send a VF_RESET message to the PF. Does not wait for response from PF
7211 * as none will be forthcoming. Immediately after calling this function,
7212 * the admin queue should be shut down and (optionally) reinitialized.
7214 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7216 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7217 I40E_SUCCESS, NULL, 0, NULL);
7219 #endif /* VF_DRIVER */
7222 * i40e_aq_set_arp_proxy_config
7223 * @hw: pointer to the HW structure
7224 * @proxy_config: pointer to proxy config command table struct
7225 * @cmd_details: pointer to command details
7227 * Set ARP offload parameters from pre-populated
7228 * i40e_aqc_arp_proxy_data struct
7230 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7231 struct i40e_aqc_arp_proxy_data *proxy_config,
7232 struct i40e_asq_cmd_details *cmd_details)
7234 struct i40e_aq_desc desc;
7235 enum i40e_status_code status;
7238 return I40E_ERR_PARAM;
7240 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7242 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7243 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7244 desc.params.external.addr_high =
7245 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7246 desc.params.external.addr_low =
7247 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7248 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7250 status = i40e_asq_send_command(hw, &desc, proxy_config,
7251 sizeof(struct i40e_aqc_arp_proxy_data),
7258 * i40e_aq_opc_set_ns_proxy_table_entry
7259 * @hw: pointer to the HW structure
7260 * @ns_proxy_table_entry: pointer to NS table entry command struct
7261 * @cmd_details: pointer to command details
7263 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7264 * from pre-populated i40e_aqc_ns_proxy_data struct
7266 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7267 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7268 struct i40e_asq_cmd_details *cmd_details)
7270 struct i40e_aq_desc desc;
7271 enum i40e_status_code status;
7273 if (!ns_proxy_table_entry)
7274 return I40E_ERR_PARAM;
7276 i40e_fill_default_direct_cmd_desc(&desc,
7277 i40e_aqc_opc_set_ns_proxy_table_entry);
7279 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7280 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7281 desc.params.external.addr_high =
7282 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7283 desc.params.external.addr_low =
7284 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7285 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7287 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7288 sizeof(struct i40e_aqc_ns_proxy_data),
7295 * i40e_aq_set_clear_wol_filter
7296 * @hw: pointer to the hw struct
7297 * @filter_index: index of filter to modify (0-7)
7298 * @filter: buffer containing filter to be set
7299 * @set_filter: true to set filter, false to clear filter
7300 * @no_wol_tco: if true, pass through packets cannot cause wake-up
7301 * if false, pass through packets may cause wake-up
7302 * @filter_valid: true if filter action is valid
7303 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7304 * @cmd_details: pointer to command details structure or NULL
7306 * Set or clear WoL filter for port attached to the PF
7308 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7310 struct i40e_aqc_set_wol_filter_data *filter,
7311 bool set_filter, bool no_wol_tco,
7312 bool filter_valid, bool no_wol_tco_valid,
7313 struct i40e_asq_cmd_details *cmd_details)
7315 struct i40e_aq_desc desc;
7316 struct i40e_aqc_set_wol_filter *cmd =
7317 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7318 enum i40e_status_code status;
7320 u16 valid_flags = 0;
7323 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7325 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7326 return I40E_ERR_PARAM;
7327 cmd->filter_index = CPU_TO_LE16(filter_index);
7331 return I40E_ERR_PARAM;
7333 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7334 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7338 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7339 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7342 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7343 if (no_wol_tco_valid)
7344 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7345 cmd->valid_flags = CPU_TO_LE16(valid_flags);
7347 buff_len = sizeof(*filter);
7348 desc.datalen = CPU_TO_LE16(buff_len);
7350 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7351 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7353 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7354 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7356 status = i40e_asq_send_command(hw, &desc, filter,
7357 buff_len, cmd_details);
7363 * i40e_aq_get_wake_event_reason
7364 * @hw: pointer to the hw struct
7365 * @wake_reason: return value, index of matching filter
7366 * @cmd_details: pointer to command details structure or NULL
7368 * Get information for the reason of a Wake Up event
7370 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7372 struct i40e_asq_cmd_details *cmd_details)
7374 struct i40e_aq_desc desc;
7375 struct i40e_aqc_get_wake_reason_completion *resp =
7376 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7377 enum i40e_status_code status;
7379 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7381 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7383 if (status == I40E_SUCCESS)
7384 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7390 * i40e_aq_clear_all_wol_filters
7391 * @hw: pointer to the hw struct
7392 * @cmd_details: pointer to command details structure or NULL
7394 * Get information for the reason of a Wake Up event
7396 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7397 struct i40e_asq_cmd_details *cmd_details)
7399 struct i40e_aq_desc desc;
7400 enum i40e_status_code status;
7402 i40e_fill_default_direct_cmd_desc(&desc,
7403 i40e_aqc_opc_clear_all_wol_filters);
7405 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7411 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7412 * @hw: pointer to the hw struct
7413 * @buff: command buffer (size in bytes = buff_size)
7414 * @buff_size: buffer size in bytes
7415 * @track_id: package tracking id
7416 * @error_offset: returns error offset
7417 * @error_info: returns error information
7418 * @cmd_details: pointer to command details structure or NULL
7421 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7422 u16 buff_size, u32 track_id,
7423 u32 *error_offset, u32 *error_info,
7424 struct i40e_asq_cmd_details *cmd_details)
7426 struct i40e_aq_desc desc;
7427 struct i40e_aqc_write_personalization_profile *cmd =
7428 (struct i40e_aqc_write_personalization_profile *)
7430 struct i40e_aqc_write_ddp_resp *resp;
7431 enum i40e_status_code status;
7433 i40e_fill_default_direct_cmd_desc(&desc,
7434 i40e_aqc_opc_write_personalization_profile);
7436 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7437 if (buff_size > I40E_AQ_LARGE_BUF)
7438 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7440 desc.datalen = CPU_TO_LE16(buff_size);
7442 cmd->profile_track_id = CPU_TO_LE32(track_id);
7444 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7446 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7448 *error_offset = LE32_TO_CPU(resp->error_offset);
7450 *error_info = LE32_TO_CPU(resp->error_info);
7457 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7458 * @hw: pointer to the hw struct
7459 * @buff: command buffer (size in bytes = buff_size)
7460 * @buff_size: buffer size in bytes
7461 * @flags: AdminQ command flags
7462 * @cmd_details: pointer to command details structure or NULL
7465 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7466 u16 buff_size, u8 flags,
7467 struct i40e_asq_cmd_details *cmd_details)
7469 struct i40e_aq_desc desc;
7470 struct i40e_aqc_get_applied_profiles *cmd =
7471 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7472 enum i40e_status_code status;
7474 i40e_fill_default_direct_cmd_desc(&desc,
7475 i40e_aqc_opc_get_personalization_profile_list);
7477 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7478 if (buff_size > I40E_AQ_LARGE_BUF)
7479 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7480 desc.datalen = CPU_TO_LE16(buff_size);
7484 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7490 * i40e_find_segment_in_package
7491 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7492 * @pkg_hdr: pointer to the package header to be searched
7494 * This function searches a package file for a particular segment type. On
7495 * success it returns a pointer to the segment header, otherwise it will
7498 struct i40e_generic_seg_header *
7499 i40e_find_segment_in_package(u32 segment_type,
7500 struct i40e_package_header *pkg_hdr)
7502 struct i40e_generic_seg_header *segment;
7505 /* Search all package segments for the requested segment type */
7506 for (i = 0; i < pkg_hdr->segment_count; i++) {
7508 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7509 pkg_hdr->segment_offset[i]);
7511 if (segment->type == segment_type)
7518 /* Get section table in profile */
7519 #define I40E_SECTION_TABLE(profile, sec_tbl) \
7521 struct i40e_profile_segment *p = (profile); \
7524 count = p->device_table_count; \
7525 nvm = (u32 *)&p->device_table[count]; \
7526 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7529 /* Get section header in profile */
7530 #define I40E_SECTION_HEADER(profile, offset) \
7531 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7534 * i40e_find_section_in_profile
7535 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7536 * @profile: pointer to the i40e segment header to be searched
7538 * This function searches i40e segment for a particular section type. On
7539 * success it returns a pointer to the section header, otherwise it will
7542 struct i40e_profile_section_header *
7543 i40e_find_section_in_profile(u32 section_type,
7544 struct i40e_profile_segment *profile)
7546 struct i40e_profile_section_header *sec;
7547 struct i40e_section_table *sec_tbl;
7551 if (profile->header.type != SEGMENT_TYPE_I40E)
7554 I40E_SECTION_TABLE(profile, sec_tbl);
7556 for (i = 0; i < sec_tbl->section_count; i++) {
7557 sec_off = sec_tbl->section_offset[i];
7558 sec = I40E_SECTION_HEADER(profile, sec_off);
7559 if (sec->section.type == section_type)
7567 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7568 * @hw: pointer to the hw struct
7569 * @aq: command buffer containing all data to execute AQ
7572 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7573 struct i40e_profile_aq_section *aq)
7575 enum i40e_status_code status;
7576 struct i40e_aq_desc desc;
7580 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7581 desc.flags |= CPU_TO_LE16(aq->flags);
7582 i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7583 I40E_NONDMA_TO_NONDMA);
7585 msglen = aq->datalen;
7587 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7589 if (msglen > I40E_AQ_LARGE_BUF)
7590 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7591 desc.datalen = CPU_TO_LE16(msglen);
7595 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7597 if (status != I40E_SUCCESS) {
7598 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7599 "unable to exec DDP AQ opcode %u, error %d\n",
7600 aq->opcode, status);
7604 /* copy returned desc to aq_buf */
7605 i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7606 I40E_NONDMA_TO_NONDMA);
7608 return I40E_SUCCESS;
7612 * i40e_validate_profile
7613 * @hw: pointer to the hardware structure
7614 * @profile: pointer to the profile segment of the package to be validated
7615 * @track_id: package tracking id
7616 * @rollback: flag if the profile is for rollback.
7618 * Validates supported devices and profile's sections.
7620 STATIC enum i40e_status_code
7621 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7622 u32 track_id, bool rollback)
7624 struct i40e_profile_section_header *sec = NULL;
7625 enum i40e_status_code status = I40E_SUCCESS;
7626 struct i40e_section_table *sec_tbl;
7632 if (track_id == I40E_DDP_TRACKID_INVALID) {
7633 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7634 return I40E_NOT_SUPPORTED;
7637 dev_cnt = profile->device_table_count;
7638 for (i = 0; i < dev_cnt; i++) {
7639 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7640 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7641 hw->device_id == (vendor_dev_id & 0xFFFF))
7644 if (dev_cnt && (i == dev_cnt)) {
7645 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7646 "Device doesn't support DDP\n");
7647 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7650 I40E_SECTION_TABLE(profile, sec_tbl);
7652 /* Validate sections types */
7653 for (i = 0; i < sec_tbl->section_count; i++) {
7654 sec_off = sec_tbl->section_offset[i];
7655 sec = I40E_SECTION_HEADER(profile, sec_off);
7657 if (sec->section.type == SECTION_TYPE_MMIO ||
7658 sec->section.type == SECTION_TYPE_AQ ||
7659 sec->section.type == SECTION_TYPE_RB_AQ) {
7660 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7661 "Not a roll-back package\n");
7662 return I40E_NOT_SUPPORTED;
7665 if (sec->section.type == SECTION_TYPE_RB_AQ ||
7666 sec->section.type == SECTION_TYPE_RB_MMIO) {
7667 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7668 "Not an original package\n");
7669 return I40E_NOT_SUPPORTED;
7678 * i40e_write_profile
7679 * @hw: pointer to the hardware structure
7680 * @profile: pointer to the profile segment of the package to be downloaded
7681 * @track_id: package tracking id
7683 * Handles the download of a complete package.
7685 enum i40e_status_code
7686 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7689 enum i40e_status_code status = I40E_SUCCESS;
7690 struct i40e_section_table *sec_tbl;
7691 struct i40e_profile_section_header *sec = NULL;
7692 struct i40e_profile_aq_section *ddp_aq;
7693 u32 section_size = 0;
7694 u32 offset = 0, info = 0;
7698 status = i40e_validate_profile(hw, profile, track_id, false);
7702 I40E_SECTION_TABLE(profile, sec_tbl);
7704 for (i = 0; i < sec_tbl->section_count; i++) {
7705 sec_off = sec_tbl->section_offset[i];
7706 sec = I40E_SECTION_HEADER(profile, sec_off);
7707 /* Process generic admin command */
7708 if (sec->section.type == SECTION_TYPE_AQ) {
7709 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7710 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7712 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7713 "Failed to execute aq: section %d, opcode %u\n",
7717 sec->section.type = SECTION_TYPE_RB_AQ;
7720 /* Skip any non-mmio sections */
7721 if (sec->section.type != SECTION_TYPE_MMIO)
7724 section_size = sec->section.size +
7725 sizeof(struct i40e_profile_section_header);
7727 /* Write MMIO section */
7728 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7729 track_id, &offset, &info, NULL);
7731 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7732 "Failed to write profile: section %d, offset %d, info %d\n",
7741 * i40e_rollback_profile
7742 * @hw: pointer to the hardware structure
7743 * @profile: pointer to the profile segment of the package to be removed
7744 * @track_id: package tracking id
7746 * Rolls back previously loaded package.
7748 enum i40e_status_code
7749 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7752 struct i40e_profile_section_header *sec = NULL;
7753 enum i40e_status_code status = I40E_SUCCESS;
7754 struct i40e_section_table *sec_tbl;
7755 u32 offset = 0, info = 0;
7756 u32 section_size = 0;
7760 status = i40e_validate_profile(hw, profile, track_id, true);
7764 I40E_SECTION_TABLE(profile, sec_tbl);
7766 /* For rollback write sections in reverse */
7767 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7768 sec_off = sec_tbl->section_offset[i];
7769 sec = I40E_SECTION_HEADER(profile, sec_off);
7771 /* Skip any non-rollback sections */
7772 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7775 section_size = sec->section.size +
7776 sizeof(struct i40e_profile_section_header);
7778 /* Write roll-back MMIO section */
7779 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7780 track_id, &offset, &info, NULL);
7782 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7783 "Failed to write profile: section %d, offset %d, info %d\n",
7792 * i40e_add_pinfo_to_list
7793 * @hw: pointer to the hardware structure
7794 * @profile: pointer to the profile segment of the package
7795 * @profile_info_sec: buffer for information section
7796 * @track_id: package tracking id
7798 * Register a profile to the list of loaded profiles.
7800 enum i40e_status_code
7801 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7802 struct i40e_profile_segment *profile,
7803 u8 *profile_info_sec, u32 track_id)
7805 enum i40e_status_code status = I40E_SUCCESS;
7806 struct i40e_profile_section_header *sec = NULL;
7807 struct i40e_profile_info *pinfo;
7808 u32 offset = 0, info = 0;
7810 sec = (struct i40e_profile_section_header *)profile_info_sec;
7812 sec->data_end = sizeof(struct i40e_profile_section_header) +
7813 sizeof(struct i40e_profile_info);
7814 sec->section.type = SECTION_TYPE_INFO;
7815 sec->section.offset = sizeof(struct i40e_profile_section_header);
7816 sec->section.size = sizeof(struct i40e_profile_info);
7817 pinfo = (struct i40e_profile_info *)(profile_info_sec +
7818 sec->section.offset);
7819 pinfo->track_id = track_id;
7820 pinfo->version = profile->version;
7821 pinfo->op = I40E_DDP_ADD_TRACKID;
7822 i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7823 I40E_NONDMA_TO_NONDMA);
7825 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7826 track_id, &offset, &info, NULL);