1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "i40e_type.h"
35 #include "i40e_adminq.h"
36 #include "i40e_prototype.h"
37 #include "i40e_virtchnl.h"
41 * i40e_set_mac_type - Sets MAC type
42 * @hw: pointer to the HW structure
44 * This function sets the mac type of the adapter based on the
45 * vendor ID and device ID stored in the hw structure.
47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
53 enum i40e_status_code status = I40E_SUCCESS;
55 DEBUGFUNC("i40e_set_mac_type\n");
57 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
59 case I40E_DEV_ID_SFP_XL710:
60 case I40E_DEV_ID_QEMU:
61 case I40E_DEV_ID_KX_B:
62 case I40E_DEV_ID_KX_C:
63 case I40E_DEV_ID_QSFP_A:
64 case I40E_DEV_ID_QSFP_B:
65 case I40E_DEV_ID_QSFP_C:
66 case I40E_DEV_ID_10G_BASE_T:
67 case I40E_DEV_ID_10G_BASE_T4:
68 case I40E_DEV_ID_20G_KR2:
69 case I40E_DEV_ID_20G_KR2_A:
70 hw->mac.type = I40E_MAC_XL710;
73 #ifdef X722_A0_SUPPORT
74 case I40E_DEV_ID_X722_A0:
76 case I40E_DEV_ID_KX_X722:
77 case I40E_DEV_ID_QSFP_X722:
78 case I40E_DEV_ID_SFP_X722:
79 case I40E_DEV_ID_1G_BASE_T_X722:
80 case I40E_DEV_ID_10G_BASE_T_X722:
81 hw->mac.type = I40E_MAC_X722;
85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
86 case I40E_DEV_ID_X722_VF:
87 case I40E_DEV_ID_X722_VF_HV:
88 #ifdef X722_A0_SUPPORT
89 case I40E_DEV_ID_X722_A0_VF:
91 hw->mac.type = I40E_MAC_X722_VF;
93 #endif /* INTEGRATED_VF || VF_DRIVER */
94 #endif /* X722_SUPPORT */
95 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
97 case I40E_DEV_ID_VF_HV:
98 hw->mac.type = I40E_MAC_VF;
102 hw->mac.type = I40E_MAC_GENERIC;
106 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
109 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
110 hw->mac.type, status);
114 #ifndef I40E_NDIS_SUPPORT
116 * i40e_aq_str - convert AQ err code to a string
117 * @hw: pointer to the HW structure
118 * @aq_err: the AQ error code to convert
120 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
125 case I40E_AQ_RC_EPERM:
126 return "I40E_AQ_RC_EPERM";
127 case I40E_AQ_RC_ENOENT:
128 return "I40E_AQ_RC_ENOENT";
129 case I40E_AQ_RC_ESRCH:
130 return "I40E_AQ_RC_ESRCH";
131 case I40E_AQ_RC_EINTR:
132 return "I40E_AQ_RC_EINTR";
134 return "I40E_AQ_RC_EIO";
135 case I40E_AQ_RC_ENXIO:
136 return "I40E_AQ_RC_ENXIO";
137 case I40E_AQ_RC_E2BIG:
138 return "I40E_AQ_RC_E2BIG";
139 case I40E_AQ_RC_EAGAIN:
140 return "I40E_AQ_RC_EAGAIN";
141 case I40E_AQ_RC_ENOMEM:
142 return "I40E_AQ_RC_ENOMEM";
143 case I40E_AQ_RC_EACCES:
144 return "I40E_AQ_RC_EACCES";
145 case I40E_AQ_RC_EFAULT:
146 return "I40E_AQ_RC_EFAULT";
147 case I40E_AQ_RC_EBUSY:
148 return "I40E_AQ_RC_EBUSY";
149 case I40E_AQ_RC_EEXIST:
150 return "I40E_AQ_RC_EEXIST";
151 case I40E_AQ_RC_EINVAL:
152 return "I40E_AQ_RC_EINVAL";
153 case I40E_AQ_RC_ENOTTY:
154 return "I40E_AQ_RC_ENOTTY";
155 case I40E_AQ_RC_ENOSPC:
156 return "I40E_AQ_RC_ENOSPC";
157 case I40E_AQ_RC_ENOSYS:
158 return "I40E_AQ_RC_ENOSYS";
159 case I40E_AQ_RC_ERANGE:
160 return "I40E_AQ_RC_ERANGE";
161 case I40E_AQ_RC_EFLUSHED:
162 return "I40E_AQ_RC_EFLUSHED";
163 case I40E_AQ_RC_BAD_ADDR:
164 return "I40E_AQ_RC_BAD_ADDR";
165 case I40E_AQ_RC_EMODE:
166 return "I40E_AQ_RC_EMODE";
167 case I40E_AQ_RC_EFBIG:
168 return "I40E_AQ_RC_EFBIG";
171 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
176 * i40e_stat_str - convert status err code to a string
177 * @hw: pointer to the HW structure
178 * @stat_err: the status error code to convert
180 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
186 return "I40E_ERR_NVM";
187 case I40E_ERR_NVM_CHECKSUM:
188 return "I40E_ERR_NVM_CHECKSUM";
190 return "I40E_ERR_PHY";
191 case I40E_ERR_CONFIG:
192 return "I40E_ERR_CONFIG";
194 return "I40E_ERR_PARAM";
195 case I40E_ERR_MAC_TYPE:
196 return "I40E_ERR_MAC_TYPE";
197 case I40E_ERR_UNKNOWN_PHY:
198 return "I40E_ERR_UNKNOWN_PHY";
199 case I40E_ERR_LINK_SETUP:
200 return "I40E_ERR_LINK_SETUP";
201 case I40E_ERR_ADAPTER_STOPPED:
202 return "I40E_ERR_ADAPTER_STOPPED";
203 case I40E_ERR_INVALID_MAC_ADDR:
204 return "I40E_ERR_INVALID_MAC_ADDR";
205 case I40E_ERR_DEVICE_NOT_SUPPORTED:
206 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
207 case I40E_ERR_MASTER_REQUESTS_PENDING:
208 return "I40E_ERR_MASTER_REQUESTS_PENDING";
209 case I40E_ERR_INVALID_LINK_SETTINGS:
210 return "I40E_ERR_INVALID_LINK_SETTINGS";
211 case I40E_ERR_AUTONEG_NOT_COMPLETE:
212 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
213 case I40E_ERR_RESET_FAILED:
214 return "I40E_ERR_RESET_FAILED";
215 case I40E_ERR_SWFW_SYNC:
216 return "I40E_ERR_SWFW_SYNC";
217 case I40E_ERR_NO_AVAILABLE_VSI:
218 return "I40E_ERR_NO_AVAILABLE_VSI";
219 case I40E_ERR_NO_MEMORY:
220 return "I40E_ERR_NO_MEMORY";
221 case I40E_ERR_BAD_PTR:
222 return "I40E_ERR_BAD_PTR";
223 case I40E_ERR_RING_FULL:
224 return "I40E_ERR_RING_FULL";
225 case I40E_ERR_INVALID_PD_ID:
226 return "I40E_ERR_INVALID_PD_ID";
227 case I40E_ERR_INVALID_QP_ID:
228 return "I40E_ERR_INVALID_QP_ID";
229 case I40E_ERR_INVALID_CQ_ID:
230 return "I40E_ERR_INVALID_CQ_ID";
231 case I40E_ERR_INVALID_CEQ_ID:
232 return "I40E_ERR_INVALID_CEQ_ID";
233 case I40E_ERR_INVALID_AEQ_ID:
234 return "I40E_ERR_INVALID_AEQ_ID";
235 case I40E_ERR_INVALID_SIZE:
236 return "I40E_ERR_INVALID_SIZE";
237 case I40E_ERR_INVALID_ARP_INDEX:
238 return "I40E_ERR_INVALID_ARP_INDEX";
239 case I40E_ERR_INVALID_FPM_FUNC_ID:
240 return "I40E_ERR_INVALID_FPM_FUNC_ID";
241 case I40E_ERR_QP_INVALID_MSG_SIZE:
242 return "I40E_ERR_QP_INVALID_MSG_SIZE";
243 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
244 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
245 case I40E_ERR_INVALID_FRAG_COUNT:
246 return "I40E_ERR_INVALID_FRAG_COUNT";
247 case I40E_ERR_QUEUE_EMPTY:
248 return "I40E_ERR_QUEUE_EMPTY";
249 case I40E_ERR_INVALID_ALIGNMENT:
250 return "I40E_ERR_INVALID_ALIGNMENT";
251 case I40E_ERR_FLUSHED_QUEUE:
252 return "I40E_ERR_FLUSHED_QUEUE";
253 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
254 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
255 case I40E_ERR_INVALID_IMM_DATA_SIZE:
256 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
257 case I40E_ERR_TIMEOUT:
258 return "I40E_ERR_TIMEOUT";
259 case I40E_ERR_OPCODE_MISMATCH:
260 return "I40E_ERR_OPCODE_MISMATCH";
261 case I40E_ERR_CQP_COMPL_ERROR:
262 return "I40E_ERR_CQP_COMPL_ERROR";
263 case I40E_ERR_INVALID_VF_ID:
264 return "I40E_ERR_INVALID_VF_ID";
265 case I40E_ERR_INVALID_HMCFN_ID:
266 return "I40E_ERR_INVALID_HMCFN_ID";
267 case I40E_ERR_BACKING_PAGE_ERROR:
268 return "I40E_ERR_BACKING_PAGE_ERROR";
269 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
270 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
271 case I40E_ERR_INVALID_PBLE_INDEX:
272 return "I40E_ERR_INVALID_PBLE_INDEX";
273 case I40E_ERR_INVALID_SD_INDEX:
274 return "I40E_ERR_INVALID_SD_INDEX";
275 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
276 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
277 case I40E_ERR_INVALID_SD_TYPE:
278 return "I40E_ERR_INVALID_SD_TYPE";
279 case I40E_ERR_MEMCPY_FAILED:
280 return "I40E_ERR_MEMCPY_FAILED";
281 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
282 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
283 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
284 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
285 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
286 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
287 case I40E_ERR_SRQ_ENABLED:
288 return "I40E_ERR_SRQ_ENABLED";
289 case I40E_ERR_ADMIN_QUEUE_ERROR:
290 return "I40E_ERR_ADMIN_QUEUE_ERROR";
291 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
292 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
293 case I40E_ERR_BUF_TOO_SHORT:
294 return "I40E_ERR_BUF_TOO_SHORT";
295 case I40E_ERR_ADMIN_QUEUE_FULL:
296 return "I40E_ERR_ADMIN_QUEUE_FULL";
297 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
298 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
299 case I40E_ERR_BAD_IWARP_CQE:
300 return "I40E_ERR_BAD_IWARP_CQE";
301 case I40E_ERR_NVM_BLANK_MODE:
302 return "I40E_ERR_NVM_BLANK_MODE";
303 case I40E_ERR_NOT_IMPLEMENTED:
304 return "I40E_ERR_NOT_IMPLEMENTED";
305 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
306 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
307 case I40E_ERR_DIAG_TEST_FAILED:
308 return "I40E_ERR_DIAG_TEST_FAILED";
309 case I40E_ERR_NOT_READY:
310 return "I40E_ERR_NOT_READY";
311 case I40E_NOT_SUPPORTED:
312 return "I40E_NOT_SUPPORTED";
313 case I40E_ERR_FIRMWARE_API_VERSION:
314 return "I40E_ERR_FIRMWARE_API_VERSION";
317 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
321 #endif /* I40E_NDIS_SUPPORT */
324 * @hw: debug mask related to admin queue
326 * @desc: pointer to admin queue descriptor
327 * @buffer: pointer to command buffer
328 * @buf_len: max length of buffer
330 * Dumps debug log about adminq command with descriptor contents.
332 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
333 void *buffer, u16 buf_len)
335 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
336 u16 len = LE16_TO_CPU(aq_desc->datalen);
337 u8 *buf = (u8 *)buffer;
340 if ((!(mask & hw->debug_mask)) || (desc == NULL))
344 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
345 LE16_TO_CPU(aq_desc->opcode),
346 LE16_TO_CPU(aq_desc->flags),
347 LE16_TO_CPU(aq_desc->datalen),
348 LE16_TO_CPU(aq_desc->retval));
349 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
350 LE32_TO_CPU(aq_desc->cookie_high),
351 LE32_TO_CPU(aq_desc->cookie_low));
352 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
353 LE32_TO_CPU(aq_desc->params.internal.param0),
354 LE32_TO_CPU(aq_desc->params.internal.param1));
355 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
356 LE32_TO_CPU(aq_desc->params.external.addr_high),
357 LE32_TO_CPU(aq_desc->params.external.addr_low));
359 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
360 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
363 /* write the full 16-byte chunks */
364 for (i = 0; i < (len - 16); i += 16)
366 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
367 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
368 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
369 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
370 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
371 /* the most we could have left is 16 bytes, pad with zeros */
376 memset(d_buf, 0, sizeof(d_buf));
377 for (j = 0; i < len; j++, i++)
380 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
381 i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
382 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
383 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
384 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
390 * i40e_check_asq_alive
391 * @hw: pointer to the hw struct
393 * Returns true if Queue is enabled else false.
395 bool i40e_check_asq_alive(struct i40e_hw *hw)
401 return !!(rd32(hw, hw->aq.asq.len) &
402 I40E_PF_ATQLEN_ATQENABLE_MASK);
404 return !!(rd32(hw, hw->aq.asq.len) &
405 I40E_PF_ATQLEN_ATQENABLE_MASK);
406 #endif /* INTEGRATED_VF */
407 #endif /* PF_DRIVER */
411 return !!(rd32(hw, hw->aq.asq.len) &
412 I40E_VF_ATQLEN1_ATQENABLE_MASK);
414 return !!(rd32(hw, hw->aq.asq.len) &
415 I40E_VF_ATQLEN1_ATQENABLE_MASK);
416 #endif /* INTEGRATED_VF */
417 #endif /* VF_DRIVER */
422 * i40e_aq_queue_shutdown
423 * @hw: pointer to the hw struct
424 * @unloading: is the driver unloading itself
426 * Tell the Firmware that we're shutting down the AdminQ and whether
427 * or not the driver is unloading as well.
429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
432 struct i40e_aq_desc desc;
433 struct i40e_aqc_queue_shutdown *cmd =
434 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
435 enum i40e_status_code status;
437 i40e_fill_default_direct_cmd_desc(&desc,
438 i40e_aqc_opc_queue_shutdown);
441 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
442 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
449 * i40e_aq_get_set_rss_lut
450 * @hw: pointer to the hardware structure
451 * @vsi_id: vsi fw index
452 * @pf_lut: for PF table set true, for VSI table set false
453 * @lut: pointer to the lut buffer provided by the caller
454 * @lut_size: size of the lut buffer
455 * @set: set true to set the table, false to get the table
457 * Internal function to get or set RSS look up table
459 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
460 u16 vsi_id, bool pf_lut,
461 u8 *lut, u16 lut_size,
464 enum i40e_status_code status;
465 struct i40e_aq_desc desc;
466 struct i40e_aqc_get_set_rss_lut *cmd_resp =
467 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
470 i40e_fill_default_direct_cmd_desc(&desc,
471 i40e_aqc_opc_set_rss_lut);
473 i40e_fill_default_direct_cmd_desc(&desc,
474 i40e_aqc_opc_get_rss_lut);
476 /* Indirect command */
477 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
478 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
481 CPU_TO_LE16((u16)((vsi_id <<
482 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
483 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
484 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
487 cmd_resp->flags |= CPU_TO_LE16((u16)
488 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
489 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
490 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
492 cmd_resp->flags |= CPU_TO_LE16((u16)
493 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
494 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
495 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
497 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
503 * i40e_aq_get_rss_lut
504 * @hw: pointer to the hardware structure
505 * @vsi_id: vsi fw index
506 * @pf_lut: for PF table set true, for VSI table set false
507 * @lut: pointer to the lut buffer provided by the caller
508 * @lut_size: size of the lut buffer
510 * get the RSS lookup table, PF or VSI type
512 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
513 bool pf_lut, u8 *lut, u16 lut_size)
515 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
520 * i40e_aq_set_rss_lut
521 * @hw: pointer to the hardware structure
522 * @vsi_id: vsi fw index
523 * @pf_lut: for PF table set true, for VSI table set false
524 * @lut: pointer to the lut buffer provided by the caller
525 * @lut_size: size of the lut buffer
527 * set the RSS lookup table, PF or VSI type
529 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
530 bool pf_lut, u8 *lut, u16 lut_size)
532 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
536 * i40e_aq_get_set_rss_key
537 * @hw: pointer to the hw struct
538 * @vsi_id: vsi fw index
539 * @key: pointer to key info struct
540 * @set: set true to set the key, false to get the key
542 * get the RSS key per VSI
544 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
546 struct i40e_aqc_get_set_rss_key_data *key,
549 enum i40e_status_code status;
550 struct i40e_aq_desc desc;
551 struct i40e_aqc_get_set_rss_key *cmd_resp =
552 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
553 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
556 i40e_fill_default_direct_cmd_desc(&desc,
557 i40e_aqc_opc_set_rss_key);
559 i40e_fill_default_direct_cmd_desc(&desc,
560 i40e_aqc_opc_get_rss_key);
562 /* Indirect command */
563 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
564 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
567 CPU_TO_LE16((u16)((vsi_id <<
568 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
569 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
570 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
572 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
578 * i40e_aq_get_rss_key
579 * @hw: pointer to the hw struct
580 * @vsi_id: vsi fw index
581 * @key: pointer to key info struct
584 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
586 struct i40e_aqc_get_set_rss_key_data *key)
588 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
592 * i40e_aq_set_rss_key
593 * @hw: pointer to the hw struct
594 * @vsi_id: vsi fw index
595 * @key: pointer to key info struct
597 * set the RSS key per VSI
599 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
601 struct i40e_aqc_get_set_rss_key_data *key)
603 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
605 #endif /* X722_SUPPORT */
607 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
608 * hardware to a bit-field that can be used by SW to more easily determine the
611 * Macros are used to shorten the table lines and make this table human
614 * We store the PTYPE in the top byte of the bit field - this is just so that
615 * we can check that the table doesn't have a row missing, as the index into
616 * the table should be the PTYPE.
620 * IF NOT i40e_ptype_lookup[ptype].known
623 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
624 * Use the rest of the fields to look at the tunnels, inner protocols, etc
626 * Use the enum i40e_rx_l2_ptype to decode the packet type
630 /* macro to make the table lines short */
631 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
634 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
635 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
636 I40E_RX_PTYPE_##OUTER_FRAG, \
637 I40E_RX_PTYPE_TUNNEL_##T, \
638 I40E_RX_PTYPE_TUNNEL_END_##TE, \
639 I40E_RX_PTYPE_##TEF, \
640 I40E_RX_PTYPE_INNER_PROT_##I, \
641 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
643 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
644 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
646 /* shorter macros makes the table fit but are terse */
647 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
648 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
649 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
651 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
652 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
653 /* L2 Packet types */
654 I40E_PTT_UNUSED_ENTRY(0),
655 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
656 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
657 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
658 I40E_PTT_UNUSED_ENTRY(4),
659 I40E_PTT_UNUSED_ENTRY(5),
660 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
661 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
662 I40E_PTT_UNUSED_ENTRY(8),
663 I40E_PTT_UNUSED_ENTRY(9),
664 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
665 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
666 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
667 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
668 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
669 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
670 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
671 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
672 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
673 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
674 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
675 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
677 /* Non Tunneled IPv4 */
678 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
679 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
680 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
681 I40E_PTT_UNUSED_ENTRY(25),
682 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
683 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
684 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
687 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
688 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
689 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
690 I40E_PTT_UNUSED_ENTRY(32),
691 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
692 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
693 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
696 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
697 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
698 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
699 I40E_PTT_UNUSED_ENTRY(39),
700 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
701 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
702 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
704 /* IPv4 --> GRE/NAT */
705 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
707 /* IPv4 --> GRE/NAT --> IPv4 */
708 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
709 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
710 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
711 I40E_PTT_UNUSED_ENTRY(47),
712 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
713 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
714 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
716 /* IPv4 --> GRE/NAT --> IPv6 */
717 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
718 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
719 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
720 I40E_PTT_UNUSED_ENTRY(54),
721 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
722 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
723 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
725 /* IPv4 --> GRE/NAT --> MAC */
726 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
728 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
729 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
730 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
731 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
732 I40E_PTT_UNUSED_ENTRY(62),
733 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
734 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
735 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
737 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
738 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
739 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
740 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
741 I40E_PTT_UNUSED_ENTRY(69),
742 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
743 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
744 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
746 /* IPv4 --> GRE/NAT --> MAC/VLAN */
747 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
749 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
750 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
751 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
752 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
753 I40E_PTT_UNUSED_ENTRY(77),
754 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
755 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
756 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
758 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
759 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
760 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
761 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
762 I40E_PTT_UNUSED_ENTRY(84),
763 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
764 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
765 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
767 /* Non Tunneled IPv6 */
768 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
769 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
770 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
771 I40E_PTT_UNUSED_ENTRY(91),
772 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
773 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
774 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
777 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
778 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
779 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
780 I40E_PTT_UNUSED_ENTRY(98),
781 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
782 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
783 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
786 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
787 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
788 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
789 I40E_PTT_UNUSED_ENTRY(105),
790 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
791 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
792 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
794 /* IPv6 --> GRE/NAT */
795 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
797 /* IPv6 --> GRE/NAT -> IPv4 */
798 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
799 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
800 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
801 I40E_PTT_UNUSED_ENTRY(113),
802 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
803 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
804 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
806 /* IPv6 --> GRE/NAT -> IPv6 */
807 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
808 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
809 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
810 I40E_PTT_UNUSED_ENTRY(120),
811 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
812 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
813 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
815 /* IPv6 --> GRE/NAT -> MAC */
816 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
818 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
819 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
820 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
821 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
822 I40E_PTT_UNUSED_ENTRY(128),
823 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
824 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
825 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
827 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
828 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
829 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
830 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
831 I40E_PTT_UNUSED_ENTRY(135),
832 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
833 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
834 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
836 /* IPv6 --> GRE/NAT -> MAC/VLAN */
837 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
839 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
840 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
841 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
842 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
843 I40E_PTT_UNUSED_ENTRY(143),
844 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
845 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
846 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
848 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
849 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
850 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
851 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
852 I40E_PTT_UNUSED_ENTRY(150),
853 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
854 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
855 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
858 I40E_PTT_UNUSED_ENTRY(154),
859 I40E_PTT_UNUSED_ENTRY(155),
860 I40E_PTT_UNUSED_ENTRY(156),
861 I40E_PTT_UNUSED_ENTRY(157),
862 I40E_PTT_UNUSED_ENTRY(158),
863 I40E_PTT_UNUSED_ENTRY(159),
865 I40E_PTT_UNUSED_ENTRY(160),
866 I40E_PTT_UNUSED_ENTRY(161),
867 I40E_PTT_UNUSED_ENTRY(162),
868 I40E_PTT_UNUSED_ENTRY(163),
869 I40E_PTT_UNUSED_ENTRY(164),
870 I40E_PTT_UNUSED_ENTRY(165),
871 I40E_PTT_UNUSED_ENTRY(166),
872 I40E_PTT_UNUSED_ENTRY(167),
873 I40E_PTT_UNUSED_ENTRY(168),
874 I40E_PTT_UNUSED_ENTRY(169),
876 I40E_PTT_UNUSED_ENTRY(170),
877 I40E_PTT_UNUSED_ENTRY(171),
878 I40E_PTT_UNUSED_ENTRY(172),
879 I40E_PTT_UNUSED_ENTRY(173),
880 I40E_PTT_UNUSED_ENTRY(174),
881 I40E_PTT_UNUSED_ENTRY(175),
882 I40E_PTT_UNUSED_ENTRY(176),
883 I40E_PTT_UNUSED_ENTRY(177),
884 I40E_PTT_UNUSED_ENTRY(178),
885 I40E_PTT_UNUSED_ENTRY(179),
887 I40E_PTT_UNUSED_ENTRY(180),
888 I40E_PTT_UNUSED_ENTRY(181),
889 I40E_PTT_UNUSED_ENTRY(182),
890 I40E_PTT_UNUSED_ENTRY(183),
891 I40E_PTT_UNUSED_ENTRY(184),
892 I40E_PTT_UNUSED_ENTRY(185),
893 I40E_PTT_UNUSED_ENTRY(186),
894 I40E_PTT_UNUSED_ENTRY(187),
895 I40E_PTT_UNUSED_ENTRY(188),
896 I40E_PTT_UNUSED_ENTRY(189),
898 I40E_PTT_UNUSED_ENTRY(190),
899 I40E_PTT_UNUSED_ENTRY(191),
900 I40E_PTT_UNUSED_ENTRY(192),
901 I40E_PTT_UNUSED_ENTRY(193),
902 I40E_PTT_UNUSED_ENTRY(194),
903 I40E_PTT_UNUSED_ENTRY(195),
904 I40E_PTT_UNUSED_ENTRY(196),
905 I40E_PTT_UNUSED_ENTRY(197),
906 I40E_PTT_UNUSED_ENTRY(198),
907 I40E_PTT_UNUSED_ENTRY(199),
909 I40E_PTT_UNUSED_ENTRY(200),
910 I40E_PTT_UNUSED_ENTRY(201),
911 I40E_PTT_UNUSED_ENTRY(202),
912 I40E_PTT_UNUSED_ENTRY(203),
913 I40E_PTT_UNUSED_ENTRY(204),
914 I40E_PTT_UNUSED_ENTRY(205),
915 I40E_PTT_UNUSED_ENTRY(206),
916 I40E_PTT_UNUSED_ENTRY(207),
917 I40E_PTT_UNUSED_ENTRY(208),
918 I40E_PTT_UNUSED_ENTRY(209),
920 I40E_PTT_UNUSED_ENTRY(210),
921 I40E_PTT_UNUSED_ENTRY(211),
922 I40E_PTT_UNUSED_ENTRY(212),
923 I40E_PTT_UNUSED_ENTRY(213),
924 I40E_PTT_UNUSED_ENTRY(214),
925 I40E_PTT_UNUSED_ENTRY(215),
926 I40E_PTT_UNUSED_ENTRY(216),
927 I40E_PTT_UNUSED_ENTRY(217),
928 I40E_PTT_UNUSED_ENTRY(218),
929 I40E_PTT_UNUSED_ENTRY(219),
931 I40E_PTT_UNUSED_ENTRY(220),
932 I40E_PTT_UNUSED_ENTRY(221),
933 I40E_PTT_UNUSED_ENTRY(222),
934 I40E_PTT_UNUSED_ENTRY(223),
935 I40E_PTT_UNUSED_ENTRY(224),
936 I40E_PTT_UNUSED_ENTRY(225),
937 I40E_PTT_UNUSED_ENTRY(226),
938 I40E_PTT_UNUSED_ENTRY(227),
939 I40E_PTT_UNUSED_ENTRY(228),
940 I40E_PTT_UNUSED_ENTRY(229),
942 I40E_PTT_UNUSED_ENTRY(230),
943 I40E_PTT_UNUSED_ENTRY(231),
944 I40E_PTT_UNUSED_ENTRY(232),
945 I40E_PTT_UNUSED_ENTRY(233),
946 I40E_PTT_UNUSED_ENTRY(234),
947 I40E_PTT_UNUSED_ENTRY(235),
948 I40E_PTT_UNUSED_ENTRY(236),
949 I40E_PTT_UNUSED_ENTRY(237),
950 I40E_PTT_UNUSED_ENTRY(238),
951 I40E_PTT_UNUSED_ENTRY(239),
953 I40E_PTT_UNUSED_ENTRY(240),
954 I40E_PTT_UNUSED_ENTRY(241),
955 I40E_PTT_UNUSED_ENTRY(242),
956 I40E_PTT_UNUSED_ENTRY(243),
957 I40E_PTT_UNUSED_ENTRY(244),
958 I40E_PTT_UNUSED_ENTRY(245),
959 I40E_PTT_UNUSED_ENTRY(246),
960 I40E_PTT_UNUSED_ENTRY(247),
961 I40E_PTT_UNUSED_ENTRY(248),
962 I40E_PTT_UNUSED_ENTRY(249),
964 I40E_PTT_UNUSED_ENTRY(250),
965 I40E_PTT_UNUSED_ENTRY(251),
966 I40E_PTT_UNUSED_ENTRY(252),
967 I40E_PTT_UNUSED_ENTRY(253),
968 I40E_PTT_UNUSED_ENTRY(254),
969 I40E_PTT_UNUSED_ENTRY(255)
974 * i40e_validate_mac_addr - Validate unicast MAC address
975 * @mac_addr: pointer to MAC address
977 * Tests a MAC address to ensure it is a valid Individual Address
979 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
981 enum i40e_status_code status = I40E_SUCCESS;
983 DEBUGFUNC("i40e_validate_mac_addr");
985 /* Broadcast addresses ARE multicast addresses
986 * Make sure it is not a multicast address
987 * Reject the zero address
989 if (I40E_IS_MULTICAST(mac_addr) ||
990 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
991 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
992 status = I40E_ERR_INVALID_MAC_ADDR;
999 * i40e_init_shared_code - Initialize the shared code
1000 * @hw: pointer to hardware structure
1002 * This assigns the MAC type and PHY code and inits the NVM.
1003 * Does not touch the hardware. This function must be called prior to any
1004 * other function in the shared code. The i40e_hw structure should be
1005 * memset to 0 prior to calling this function. The following fields in
1006 * hw structure should be filled in prior to calling this function:
1007 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1008 * subsystem_vendor_id, and revision_id
1010 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1012 enum i40e_status_code status = I40E_SUCCESS;
1013 u32 port, ari, func_rid;
1015 DEBUGFUNC("i40e_init_shared_code");
1017 i40e_set_mac_type(hw);
1019 switch (hw->mac.type) {
1020 case I40E_MAC_XL710:
1026 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1029 hw->phy.get_link_info = true;
1031 /* Determine port number and PF number*/
1032 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1033 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1034 hw->port = (u8)port;
1035 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1036 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1037 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1039 hw->pf_id = (u8)(func_rid & 0xff);
1041 hw->pf_id = (u8)(func_rid & 0x7);
1044 if (hw->mac.type == I40E_MAC_X722)
1045 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1048 status = i40e_init_nvm(hw);
1053 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1054 * @hw: pointer to the hw struct
1055 * @flags: a return indicator of what addresses were added to the addr store
1056 * @addrs: the requestor's mac addr store
1057 * @cmd_details: pointer to command details structure or NULL
1059 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1061 struct i40e_aqc_mac_address_read_data *addrs,
1062 struct i40e_asq_cmd_details *cmd_details)
1064 struct i40e_aq_desc desc;
1065 struct i40e_aqc_mac_address_read *cmd_data =
1066 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1067 enum i40e_status_code status;
1069 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1070 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1072 status = i40e_asq_send_command(hw, &desc, addrs,
1073 sizeof(*addrs), cmd_details);
1074 *flags = LE16_TO_CPU(cmd_data->command_flags);
1080 * i40e_aq_mac_address_write - Change the MAC addresses
1081 * @hw: pointer to the hw struct
1082 * @flags: indicates which MAC to be written
1083 * @mac_addr: address to write
1084 * @cmd_details: pointer to command details structure or NULL
1086 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1087 u16 flags, u8 *mac_addr,
1088 struct i40e_asq_cmd_details *cmd_details)
1090 struct i40e_aq_desc desc;
1091 struct i40e_aqc_mac_address_write *cmd_data =
1092 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1093 enum i40e_status_code status;
1095 i40e_fill_default_direct_cmd_desc(&desc,
1096 i40e_aqc_opc_mac_address_write);
1097 cmd_data->command_flags = CPU_TO_LE16(flags);
1098 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1099 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1100 ((u32)mac_addr[3] << 16) |
1101 ((u32)mac_addr[4] << 8) |
1104 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1110 * i40e_get_mac_addr - get MAC address
1111 * @hw: pointer to the HW structure
1112 * @mac_addr: pointer to MAC address
1114 * Reads the adapter's MAC address from register
1116 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1118 struct i40e_aqc_mac_address_read_data addrs;
1119 enum i40e_status_code status;
1122 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1124 if (flags & I40E_AQC_LAN_ADDR_VALID)
1125 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1131 * i40e_get_port_mac_addr - get Port MAC address
1132 * @hw: pointer to the HW structure
1133 * @mac_addr: pointer to Port MAC address
1135 * Reads the adapter's Port MAC address
1137 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1139 struct i40e_aqc_mac_address_read_data addrs;
1140 enum i40e_status_code status;
1143 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1147 if (flags & I40E_AQC_PORT_ADDR_VALID)
1148 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1150 status = I40E_ERR_INVALID_MAC_ADDR;
1156 * i40e_pre_tx_queue_cfg - pre tx queue configure
1157 * @hw: pointer to the HW structure
1158 * @queue: target pf queue index
1159 * @enable: state change request
1161 * Handles hw requirement to indicate intention to enable
1162 * or disable target queue.
1164 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1166 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1170 if (abs_queue_idx >= 128) {
1171 reg_block = abs_queue_idx / 128;
1172 abs_queue_idx %= 128;
1175 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1176 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1177 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1180 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1182 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1184 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1188 * i40e_read_pba_string - Reads part number string from EEPROM
1189 * @hw: pointer to hardware structure
1190 * @pba_num: stores the part number string from the EEPROM
1191 * @pba_num_size: part number string buffer length
1193 * Reads the part number string from the EEPROM.
1195 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1198 enum i40e_status_code status = I40E_SUCCESS;
1204 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1205 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1206 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1210 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1211 if (status != I40E_SUCCESS) {
1212 DEBUGOUT("Failed to read PBA Block pointer.\n");
1216 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1217 if (status != I40E_SUCCESS) {
1218 DEBUGOUT("Failed to read PBA Block size.\n");
1222 /* Subtract one to get PBA word count (PBA Size word is included in
1226 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1227 DEBUGOUT("Buffer to small for PBA data.\n");
1228 return I40E_ERR_PARAM;
1231 for (i = 0; i < pba_size; i++) {
1232 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1233 if (status != I40E_SUCCESS) {
1234 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1238 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1239 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1241 pba_num[(pba_size * 2)] = '\0';
1247 * i40e_get_media_type - Gets media type
1248 * @hw: pointer to the hardware structure
1250 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1252 enum i40e_media_type media;
1254 switch (hw->phy.link_info.phy_type) {
1255 case I40E_PHY_TYPE_10GBASE_SR:
1256 case I40E_PHY_TYPE_10GBASE_LR:
1257 case I40E_PHY_TYPE_1000BASE_SX:
1258 case I40E_PHY_TYPE_1000BASE_LX:
1259 case I40E_PHY_TYPE_40GBASE_SR4:
1260 case I40E_PHY_TYPE_40GBASE_LR4:
1261 media = I40E_MEDIA_TYPE_FIBER;
1263 case I40E_PHY_TYPE_100BASE_TX:
1264 case I40E_PHY_TYPE_1000BASE_T:
1265 case I40E_PHY_TYPE_10GBASE_T:
1266 media = I40E_MEDIA_TYPE_BASET;
1268 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1269 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1270 case I40E_PHY_TYPE_10GBASE_CR1:
1271 case I40E_PHY_TYPE_40GBASE_CR4:
1272 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1273 case I40E_PHY_TYPE_40GBASE_AOC:
1274 case I40E_PHY_TYPE_10GBASE_AOC:
1275 media = I40E_MEDIA_TYPE_DA;
1277 case I40E_PHY_TYPE_1000BASE_KX:
1278 case I40E_PHY_TYPE_10GBASE_KX4:
1279 case I40E_PHY_TYPE_10GBASE_KR:
1280 case I40E_PHY_TYPE_40GBASE_KR4:
1281 case I40E_PHY_TYPE_20GBASE_KR2:
1282 media = I40E_MEDIA_TYPE_BACKPLANE;
1284 case I40E_PHY_TYPE_SGMII:
1285 case I40E_PHY_TYPE_XAUI:
1286 case I40E_PHY_TYPE_XFI:
1287 case I40E_PHY_TYPE_XLAUI:
1288 case I40E_PHY_TYPE_XLPPI:
1290 media = I40E_MEDIA_TYPE_UNKNOWN;
1297 #define I40E_PF_RESET_WAIT_COUNT 200
1299 * i40e_pf_reset - Reset the PF
1300 * @hw: pointer to the hardware structure
1302 * Assuming someone else has triggered a global reset,
1303 * assure the global reset is complete and then reset the PF
1305 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1312 /* Poll for Global Reset steady state in case of recent GRST.
1313 * The grst delay value is in 100ms units, and we'll wait a
1314 * couple counts longer to be sure we don't just miss the end.
1316 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1317 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1318 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1319 #ifdef I40E_ESS_SUPPORT
1320 /* It can take upto 15 secs for GRST steady state */
1321 grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */
1323 for (cnt = 0; cnt < grst_del + 10; cnt++) {
1324 reg = rd32(hw, I40E_GLGEN_RSTAT);
1325 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1327 i40e_msec_delay(100);
1329 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1330 DEBUGOUT("Global reset polling failed to complete.\n");
1331 return I40E_ERR_RESET_FAILED;
1334 /* Now Wait for the FW to be ready */
1335 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1336 reg = rd32(hw, I40E_GLNVM_ULD);
1337 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1338 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1339 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1340 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1341 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1344 i40e_msec_delay(10);
1346 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1347 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1348 DEBUGOUT("wait for FW Reset complete timedout\n");
1349 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1350 return I40E_ERR_RESET_FAILED;
1353 /* If there was a Global Reset in progress when we got here,
1354 * we don't need to do the PF Reset
1357 reg = rd32(hw, I40E_PFGEN_CTRL);
1358 wr32(hw, I40E_PFGEN_CTRL,
1359 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1360 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1361 reg = rd32(hw, I40E_PFGEN_CTRL);
1362 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1366 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1367 DEBUGOUT("PF reset polling failed to complete.\n");
1368 return I40E_ERR_RESET_FAILED;
1372 i40e_clear_pxe_mode(hw);
1375 return I40E_SUCCESS;
1379 * i40e_clear_hw - clear out any left over hw state
1380 * @hw: pointer to the hw struct
1382 * Clear queues and interrupts, typically called at init time,
1383 * but after the capabilities have been found so we know how many
1384 * queues and msix vectors have been allocated.
1386 void i40e_clear_hw(struct i40e_hw *hw)
1388 u32 num_queues, base_queue;
1396 /* get number of interrupts, queues, and vfs */
1397 val = rd32(hw, I40E_GLPCI_CNF2);
1398 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1399 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1400 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1401 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1403 val = rd32(hw, I40E_PFLAN_QALLOC);
1404 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1405 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1406 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1407 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1408 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1409 num_queues = (j - base_queue) + 1;
1413 val = rd32(hw, I40E_PF_VT_PFALLOC);
1414 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1415 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1416 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1417 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1418 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1419 num_vfs = (j - i) + 1;
1423 /* stop all the interrupts */
1424 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1425 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1426 for (i = 0; i < num_pf_int - 2; i++)
1427 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1429 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1430 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1431 wr32(hw, I40E_PFINT_LNKLST0, val);
1432 for (i = 0; i < num_pf_int - 2; i++)
1433 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1434 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1435 for (i = 0; i < num_vfs; i++)
1436 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1437 for (i = 0; i < num_vf_int - 2; i++)
1438 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1440 /* warn the HW of the coming Tx disables */
1441 for (i = 0; i < num_queues; i++) {
1442 u32 abs_queue_idx = base_queue + i;
1445 if (abs_queue_idx >= 128) {
1446 reg_block = abs_queue_idx / 128;
1447 abs_queue_idx %= 128;
1450 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1451 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1452 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1453 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1455 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1457 i40e_usec_delay(400);
1459 /* stop all the queues */
1460 for (i = 0; i < num_queues; i++) {
1461 wr32(hw, I40E_QINT_TQCTL(i), 0);
1462 wr32(hw, I40E_QTX_ENA(i), 0);
1463 wr32(hw, I40E_QINT_RQCTL(i), 0);
1464 wr32(hw, I40E_QRX_ENA(i), 0);
1467 /* short wait for all queue disables to settle */
1468 i40e_usec_delay(50);
1472 * i40e_clear_pxe_mode - clear pxe operations mode
1473 * @hw: pointer to the hw struct
1475 * Make sure all PXE mode settings are cleared, including things
1476 * like descriptor fetch/write-back mode.
1478 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1480 if (i40e_check_asq_alive(hw))
1481 i40e_aq_clear_pxe_mode(hw, NULL);
1485 * i40e_led_is_mine - helper to find matching led
1486 * @hw: pointer to the hw struct
1487 * @idx: index into GPIO registers
1489 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1491 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1496 if (!hw->func_caps.led[idx])
1499 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1500 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1501 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1503 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1504 * if it is not our port then ignore
1506 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1513 #define I40E_COMBINED_ACTIVITY 0xA
1514 #define I40E_FILTER_ACTIVITY 0xE
1515 #define I40E_LINK_ACTIVITY 0xC
1516 #define I40E_MAC_ACTIVITY 0xD
1517 #define I40E_LED0 22
1520 * i40e_led_get - return current on/off mode
1521 * @hw: pointer to the hw struct
1523 * The value returned is the 'mode' field as defined in the
1524 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1525 * values are variations of possible behaviors relating to
1526 * blink, link, and wire.
1528 u32 i40e_led_get(struct i40e_hw *hw)
1530 u32 current_mode = 0;
1534 /* as per the documentation GPIO 22-29 are the LED
1535 * GPIO pins named LED0..LED7
1537 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1538 u32 gpio_val = i40e_led_is_mine(hw, i);
1543 /* ignore gpio LED src mode entries related to the activity LEDs */
1544 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1545 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1546 switch (current_mode) {
1547 case I40E_COMBINED_ACTIVITY:
1548 case I40E_FILTER_ACTIVITY:
1549 case I40E_MAC_ACTIVITY:
1555 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1556 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1564 * i40e_led_set - set new on/off mode
1565 * @hw: pointer to the hw struct
1566 * @mode: 0=off, 0xf=on (else see manual for mode details)
1567 * @blink: true if the LED should blink when on, false if steady
1569 * if this function is used to turn on the blink it should
1570 * be used to disable the blink when restoring the original state.
1572 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1574 u32 current_mode = 0;
1577 if (mode & 0xfffffff0)
1578 DEBUGOUT1("invalid mode passed in %X\n", mode);
1580 /* as per the documentation GPIO 22-29 are the LED
1581 * GPIO pins named LED0..LED7
1583 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1584 u32 gpio_val = i40e_led_is_mine(hw, i);
1589 /* ignore gpio LED src mode entries related to the activity LEDs */
1590 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1591 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1592 switch (current_mode) {
1593 case I40E_COMBINED_ACTIVITY:
1594 case I40E_FILTER_ACTIVITY:
1595 case I40E_MAC_ACTIVITY:
1601 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1602 /* this & is a bit of paranoia, but serves as a range check */
1603 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1604 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1606 if (mode == I40E_LINK_ACTIVITY)
1610 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1612 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1614 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1619 /* Admin command wrappers */
1622 * i40e_aq_get_phy_capabilities
1623 * @hw: pointer to the hw struct
1624 * @abilities: structure for PHY capabilities to be filled
1625 * @qualified_modules: report Qualified Modules
1626 * @report_init: report init capabilities (active are default)
1627 * @cmd_details: pointer to command details structure or NULL
1629 * Returns the various PHY abilities supported on the Port.
1631 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1632 bool qualified_modules, bool report_init,
1633 struct i40e_aq_get_phy_abilities_resp *abilities,
1634 struct i40e_asq_cmd_details *cmd_details)
1636 struct i40e_aq_desc desc;
1637 enum i40e_status_code status;
1638 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1641 return I40E_ERR_PARAM;
1643 i40e_fill_default_direct_cmd_desc(&desc,
1644 i40e_aqc_opc_get_phy_abilities);
1646 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1647 if (abilities_size > I40E_AQ_LARGE_BUF)
1648 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1650 if (qualified_modules)
1651 desc.params.external.param0 |=
1652 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1655 desc.params.external.param0 |=
1656 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1658 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1661 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1662 status = I40E_ERR_UNKNOWN_PHY;
1665 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1671 * i40e_aq_set_phy_config
1672 * @hw: pointer to the hw struct
1673 * @config: structure with PHY configuration to be set
1674 * @cmd_details: pointer to command details structure or NULL
1676 * Set the various PHY configuration parameters
1677 * supported on the Port.One or more of the Set PHY config parameters may be
1678 * ignored in an MFP mode as the PF may not have the privilege to set some
1679 * of the PHY Config parameters. This status will be indicated by the
1682 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1683 struct i40e_aq_set_phy_config *config,
1684 struct i40e_asq_cmd_details *cmd_details)
1686 struct i40e_aq_desc desc;
1687 struct i40e_aq_set_phy_config *cmd =
1688 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1689 enum i40e_status_code status;
1692 return I40E_ERR_PARAM;
1694 i40e_fill_default_direct_cmd_desc(&desc,
1695 i40e_aqc_opc_set_phy_config);
1699 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1706 * @hw: pointer to the hw struct
1708 * Set the requested flow control mode using set_phy_config.
1710 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1711 bool atomic_restart)
1713 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1714 struct i40e_aq_get_phy_abilities_resp abilities;
1715 struct i40e_aq_set_phy_config config;
1716 enum i40e_status_code status;
1717 u8 pause_mask = 0x0;
1723 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1724 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1726 case I40E_FC_RX_PAUSE:
1727 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1729 case I40E_FC_TX_PAUSE:
1730 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1736 /* Get the current phy config */
1737 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1740 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1744 memset(&config, 0, sizeof(config));
1745 /* clear the old pause settings */
1746 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1747 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1748 /* set the new abilities */
1749 config.abilities |= pause_mask;
1750 /* If the abilities have changed, then set the new config */
1751 if (config.abilities != abilities.abilities) {
1752 /* Auto restart link so settings take effect */
1754 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1755 /* Copy over all the old settings */
1756 config.phy_type = abilities.phy_type;
1757 config.link_speed = abilities.link_speed;
1758 config.eee_capability = abilities.eee_capability;
1759 config.eeer = abilities.eeer_val;
1760 config.low_power_ctrl = abilities.d3_lpan;
1761 status = i40e_aq_set_phy_config(hw, &config, NULL);
1764 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1766 /* Update the link info */
1767 status = i40e_update_link_info(hw);
1769 /* Wait a little bit (on 40G cards it sometimes takes a really
1770 * long time for link to come back from the atomic reset)
1773 i40e_msec_delay(1000);
1774 status = i40e_update_link_info(hw);
1777 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1783 * i40e_aq_set_mac_config
1784 * @hw: pointer to the hw struct
1785 * @max_frame_size: Maximum Frame Size to be supported by the port
1786 * @crc_en: Tell HW to append a CRC to outgoing frames
1787 * @pacing: Pacing configurations
1788 * @cmd_details: pointer to command details structure or NULL
1790 * Configure MAC settings for frame size, jumbo frame support and the
1791 * addition of a CRC by the hardware.
1793 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1795 bool crc_en, u16 pacing,
1796 struct i40e_asq_cmd_details *cmd_details)
1798 struct i40e_aq_desc desc;
1799 struct i40e_aq_set_mac_config *cmd =
1800 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1801 enum i40e_status_code status;
1803 if (max_frame_size == 0)
1804 return I40E_ERR_PARAM;
1806 i40e_fill_default_direct_cmd_desc(&desc,
1807 i40e_aqc_opc_set_mac_config);
1809 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1810 cmd->params = ((u8)pacing & 0x0F) << 3;
1812 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1814 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1820 * i40e_aq_clear_pxe_mode
1821 * @hw: pointer to the hw struct
1822 * @cmd_details: pointer to command details structure or NULL
1824 * Tell the firmware that the driver is taking over from PXE
1826 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1827 struct i40e_asq_cmd_details *cmd_details)
1829 enum i40e_status_code status;
1830 struct i40e_aq_desc desc;
1831 struct i40e_aqc_clear_pxe *cmd =
1832 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1834 i40e_fill_default_direct_cmd_desc(&desc,
1835 i40e_aqc_opc_clear_pxe_mode);
1839 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1841 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1847 * i40e_aq_set_link_restart_an
1848 * @hw: pointer to the hw struct
1849 * @enable_link: if true: enable link, if false: disable link
1850 * @cmd_details: pointer to command details structure or NULL
1852 * Sets up the link and restarts the Auto-Negotiation over the link.
1854 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1855 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1857 struct i40e_aq_desc desc;
1858 struct i40e_aqc_set_link_restart_an *cmd =
1859 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1860 enum i40e_status_code status;
1862 i40e_fill_default_direct_cmd_desc(&desc,
1863 i40e_aqc_opc_set_link_restart_an);
1865 cmd->command = I40E_AQ_PHY_RESTART_AN;
1867 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1869 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1871 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1877 * i40e_aq_get_link_info
1878 * @hw: pointer to the hw struct
1879 * @enable_lse: enable/disable LinkStatusEvent reporting
1880 * @link: pointer to link status structure - optional
1881 * @cmd_details: pointer to command details structure or NULL
1883 * Returns the link status of the adapter.
1885 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1886 bool enable_lse, struct i40e_link_status *link,
1887 struct i40e_asq_cmd_details *cmd_details)
1889 struct i40e_aq_desc desc;
1890 struct i40e_aqc_get_link_status *resp =
1891 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1892 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1893 enum i40e_status_code status;
1894 bool tx_pause, rx_pause;
1897 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1900 command_flags = I40E_AQ_LSE_ENABLE;
1902 command_flags = I40E_AQ_LSE_DISABLE;
1903 resp->command_flags = CPU_TO_LE16(command_flags);
1905 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1907 if (status != I40E_SUCCESS)
1908 goto aq_get_link_info_exit;
1910 /* save off old link status information */
1911 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1912 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1914 /* update link status */
1915 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1916 hw->phy.media_type = i40e_get_media_type(hw);
1917 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1918 hw_link_info->link_info = resp->link_info;
1919 hw_link_info->an_info = resp->an_info;
1920 hw_link_info->ext_info = resp->ext_info;
1921 hw_link_info->loopback = resp->loopback;
1922 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1923 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1925 /* update fc info */
1926 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1927 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1928 if (tx_pause & rx_pause)
1929 hw->fc.current_mode = I40E_FC_FULL;
1931 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1933 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1935 hw->fc.current_mode = I40E_FC_NONE;
1937 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1938 hw_link_info->crc_enable = true;
1940 hw_link_info->crc_enable = false;
1942 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1943 hw_link_info->lse_enable = true;
1945 hw_link_info->lse_enable = false;
1947 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1948 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1949 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1951 /* save link status information */
1953 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1954 I40E_NONDMA_TO_NONDMA);
1956 /* flag cleared so helper functions don't call AQ again */
1957 hw->phy.get_link_info = false;
1959 aq_get_link_info_exit:
1964 * i40e_aq_set_phy_int_mask
1965 * @hw: pointer to the hw struct
1966 * @mask: interrupt mask to be set
1967 * @cmd_details: pointer to command details structure or NULL
1969 * Set link interrupt mask.
1971 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1973 struct i40e_asq_cmd_details *cmd_details)
1975 struct i40e_aq_desc desc;
1976 struct i40e_aqc_set_phy_int_mask *cmd =
1977 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1978 enum i40e_status_code status;
1980 i40e_fill_default_direct_cmd_desc(&desc,
1981 i40e_aqc_opc_set_phy_int_mask);
1983 cmd->event_mask = CPU_TO_LE16(mask);
1985 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1991 * i40e_aq_get_local_advt_reg
1992 * @hw: pointer to the hw struct
1993 * @advt_reg: local AN advertisement register value
1994 * @cmd_details: pointer to command details structure or NULL
1996 * Get the Local AN advertisement register value.
1998 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2000 struct i40e_asq_cmd_details *cmd_details)
2002 struct i40e_aq_desc desc;
2003 struct i40e_aqc_an_advt_reg *resp =
2004 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2005 enum i40e_status_code status;
2007 i40e_fill_default_direct_cmd_desc(&desc,
2008 i40e_aqc_opc_get_local_advt_reg);
2010 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2012 if (status != I40E_SUCCESS)
2013 goto aq_get_local_advt_reg_exit;
2015 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2016 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2018 aq_get_local_advt_reg_exit:
2023 * i40e_aq_set_local_advt_reg
2024 * @hw: pointer to the hw struct
2025 * @advt_reg: local AN advertisement register value
2026 * @cmd_details: pointer to command details structure or NULL
2028 * Get the Local AN advertisement register value.
2030 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2032 struct i40e_asq_cmd_details *cmd_details)
2034 struct i40e_aq_desc desc;
2035 struct i40e_aqc_an_advt_reg *cmd =
2036 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2037 enum i40e_status_code status;
2039 i40e_fill_default_direct_cmd_desc(&desc,
2040 i40e_aqc_opc_get_local_advt_reg);
2042 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2043 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2045 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2051 * i40e_aq_get_partner_advt
2052 * @hw: pointer to the hw struct
2053 * @advt_reg: AN partner advertisement register value
2054 * @cmd_details: pointer to command details structure or NULL
2056 * Get the link partner AN advertisement register value.
2058 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2060 struct i40e_asq_cmd_details *cmd_details)
2062 struct i40e_aq_desc desc;
2063 struct i40e_aqc_an_advt_reg *resp =
2064 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2065 enum i40e_status_code status;
2067 i40e_fill_default_direct_cmd_desc(&desc,
2068 i40e_aqc_opc_get_partner_advt);
2070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2072 if (status != I40E_SUCCESS)
2073 goto aq_get_partner_advt_exit;
2075 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2076 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2078 aq_get_partner_advt_exit:
2083 * i40e_aq_set_lb_modes
2084 * @hw: pointer to the hw struct
2085 * @lb_modes: loopback mode to be set
2086 * @cmd_details: pointer to command details structure or NULL
2088 * Sets loopback modes.
2090 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2092 struct i40e_asq_cmd_details *cmd_details)
2094 struct i40e_aq_desc desc;
2095 struct i40e_aqc_set_lb_mode *cmd =
2096 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2097 enum i40e_status_code status;
2099 i40e_fill_default_direct_cmd_desc(&desc,
2100 i40e_aqc_opc_set_lb_modes);
2102 cmd->lb_mode = CPU_TO_LE16(lb_modes);
2104 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2110 * i40e_aq_set_phy_debug
2111 * @hw: pointer to the hw struct
2112 * @cmd_flags: debug command flags
2113 * @cmd_details: pointer to command details structure or NULL
2115 * Reset the external PHY.
2117 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2118 struct i40e_asq_cmd_details *cmd_details)
2120 struct i40e_aq_desc desc;
2121 struct i40e_aqc_set_phy_debug *cmd =
2122 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2123 enum i40e_status_code status;
2125 i40e_fill_default_direct_cmd_desc(&desc,
2126 i40e_aqc_opc_set_phy_debug);
2128 cmd->command_flags = cmd_flags;
2130 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2137 * @hw: pointer to the hw struct
2138 * @vsi_ctx: pointer to a vsi context struct
2139 * @cmd_details: pointer to command details structure or NULL
2141 * Add a VSI context to the hardware.
2143 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2144 struct i40e_vsi_context *vsi_ctx,
2145 struct i40e_asq_cmd_details *cmd_details)
2147 struct i40e_aq_desc desc;
2148 struct i40e_aqc_add_get_update_vsi *cmd =
2149 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2150 struct i40e_aqc_add_get_update_vsi_completion *resp =
2151 (struct i40e_aqc_add_get_update_vsi_completion *)
2153 enum i40e_status_code status;
2155 i40e_fill_default_direct_cmd_desc(&desc,
2156 i40e_aqc_opc_add_vsi);
2158 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2159 cmd->connection_type = vsi_ctx->connection_type;
2160 cmd->vf_id = vsi_ctx->vf_num;
2161 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2163 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2165 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2166 sizeof(vsi_ctx->info), cmd_details);
2168 if (status != I40E_SUCCESS)
2169 goto aq_add_vsi_exit;
2171 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2172 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2173 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2174 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2181 * i40e_aq_set_default_vsi
2182 * @hw: pointer to the hw struct
2184 * @cmd_details: pointer to command details structure or NULL
2186 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2188 struct i40e_asq_cmd_details *cmd_details)
2190 struct i40e_aq_desc desc;
2191 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2192 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2194 enum i40e_status_code status;
2196 i40e_fill_default_direct_cmd_desc(&desc,
2197 i40e_aqc_opc_set_vsi_promiscuous_modes);
2199 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2200 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2201 cmd->seid = CPU_TO_LE16(seid);
2203 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2209 * i40e_aq_set_vsi_unicast_promiscuous
2210 * @hw: pointer to the hw struct
2212 * @set: set unicast promiscuous enable/disable
2213 * @cmd_details: pointer to command details structure or NULL
2215 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2217 struct i40e_asq_cmd_details *cmd_details)
2219 struct i40e_aq_desc desc;
2220 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2221 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2222 enum i40e_status_code status;
2225 i40e_fill_default_direct_cmd_desc(&desc,
2226 i40e_aqc_opc_set_vsi_promiscuous_modes);
2229 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2231 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2233 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2235 cmd->seid = CPU_TO_LE16(seid);
2236 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2242 * i40e_aq_set_vsi_multicast_promiscuous
2243 * @hw: pointer to the hw struct
2245 * @set: set multicast promiscuous enable/disable
2246 * @cmd_details: pointer to command details structure or NULL
2248 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2249 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2251 struct i40e_aq_desc desc;
2252 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2253 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2254 enum i40e_status_code status;
2257 i40e_fill_default_direct_cmd_desc(&desc,
2258 i40e_aqc_opc_set_vsi_promiscuous_modes);
2261 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2263 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2265 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2267 cmd->seid = CPU_TO_LE16(seid);
2268 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2274 * i40e_aq_set_vsi_mc_promisc_on_vlan
2275 * @hw: pointer to the hw struct
2277 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2278 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2279 * @cmd_details: pointer to command details structure or NULL
2281 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2282 u16 seid, bool enable, u16 vid,
2283 struct i40e_asq_cmd_details *cmd_details)
2285 struct i40e_aq_desc desc;
2286 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2287 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2288 enum i40e_status_code status;
2291 i40e_fill_default_direct_cmd_desc(&desc,
2292 i40e_aqc_opc_set_vsi_promiscuous_modes);
2295 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2297 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2298 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2299 cmd->seid = CPU_TO_LE16(seid);
2300 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2302 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2308 * i40e_aq_set_vsi_uc_promisc_on_vlan
2309 * @hw: pointer to the hw struct
2311 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2312 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2313 * @cmd_details: pointer to command details structure or NULL
2315 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2316 u16 seid, bool enable, u16 vid,
2317 struct i40e_asq_cmd_details *cmd_details)
2319 struct i40e_aq_desc desc;
2320 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2321 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2322 enum i40e_status_code status;
2325 i40e_fill_default_direct_cmd_desc(&desc,
2326 i40e_aqc_opc_set_vsi_promiscuous_modes);
2329 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2331 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2332 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2333 cmd->seid = CPU_TO_LE16(seid);
2334 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2336 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2342 * i40e_aq_set_vsi_broadcast
2343 * @hw: pointer to the hw struct
2345 * @set_filter: true to set filter, false to clear filter
2346 * @cmd_details: pointer to command details structure or NULL
2348 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2350 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2351 u16 seid, bool set_filter,
2352 struct i40e_asq_cmd_details *cmd_details)
2354 struct i40e_aq_desc desc;
2355 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2356 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2357 enum i40e_status_code status;
2359 i40e_fill_default_direct_cmd_desc(&desc,
2360 i40e_aqc_opc_set_vsi_promiscuous_modes);
2363 cmd->promiscuous_flags
2364 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2366 cmd->promiscuous_flags
2367 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2369 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2370 cmd->seid = CPU_TO_LE16(seid);
2371 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2377 * i40e_get_vsi_params - get VSI configuration info
2378 * @hw: pointer to the hw struct
2379 * @vsi_ctx: pointer to a vsi context struct
2380 * @cmd_details: pointer to command details structure or NULL
2382 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2383 struct i40e_vsi_context *vsi_ctx,
2384 struct i40e_asq_cmd_details *cmd_details)
2386 struct i40e_aq_desc desc;
2387 struct i40e_aqc_add_get_update_vsi *cmd =
2388 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2389 struct i40e_aqc_add_get_update_vsi_completion *resp =
2390 (struct i40e_aqc_add_get_update_vsi_completion *)
2392 enum i40e_status_code status;
2394 UNREFERENCED_1PARAMETER(cmd_details);
2395 i40e_fill_default_direct_cmd_desc(&desc,
2396 i40e_aqc_opc_get_vsi_parameters);
2398 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2400 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2402 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2403 sizeof(vsi_ctx->info), NULL);
2405 if (status != I40E_SUCCESS)
2406 goto aq_get_vsi_params_exit;
2408 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2409 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2410 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2411 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2413 aq_get_vsi_params_exit:
2418 * i40e_aq_update_vsi_params
2419 * @hw: pointer to the hw struct
2420 * @vsi_ctx: pointer to a vsi context struct
2421 * @cmd_details: pointer to command details structure or NULL
2423 * Update a VSI context.
2425 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2426 struct i40e_vsi_context *vsi_ctx,
2427 struct i40e_asq_cmd_details *cmd_details)
2429 struct i40e_aq_desc desc;
2430 struct i40e_aqc_add_get_update_vsi *cmd =
2431 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2432 enum i40e_status_code status;
2434 i40e_fill_default_direct_cmd_desc(&desc,
2435 i40e_aqc_opc_update_vsi_parameters);
2436 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2438 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2440 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2441 sizeof(vsi_ctx->info), cmd_details);
2447 * i40e_aq_get_switch_config
2448 * @hw: pointer to the hardware structure
2449 * @buf: pointer to the result buffer
2450 * @buf_size: length of input buffer
2451 * @start_seid: seid to start for the report, 0 == beginning
2452 * @cmd_details: pointer to command details structure or NULL
2454 * Fill the buf with switch configuration returned from AdminQ command
2456 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2457 struct i40e_aqc_get_switch_config_resp *buf,
2458 u16 buf_size, u16 *start_seid,
2459 struct i40e_asq_cmd_details *cmd_details)
2461 struct i40e_aq_desc desc;
2462 struct i40e_aqc_switch_seid *scfg =
2463 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2464 enum i40e_status_code status;
2466 i40e_fill_default_direct_cmd_desc(&desc,
2467 i40e_aqc_opc_get_switch_config);
2468 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2469 if (buf_size > I40E_AQ_LARGE_BUF)
2470 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2471 scfg->seid = CPU_TO_LE16(*start_seid);
2473 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2474 *start_seid = LE16_TO_CPU(scfg->seid);
2480 * i40e_aq_get_firmware_version
2481 * @hw: pointer to the hw struct
2482 * @fw_major_version: firmware major version
2483 * @fw_minor_version: firmware minor version
2484 * @fw_build: firmware build number
2485 * @api_major_version: major queue version
2486 * @api_minor_version: minor queue version
2487 * @cmd_details: pointer to command details structure or NULL
2489 * Get the firmware version from the admin queue commands
2491 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2492 u16 *fw_major_version, u16 *fw_minor_version,
2494 u16 *api_major_version, u16 *api_minor_version,
2495 struct i40e_asq_cmd_details *cmd_details)
2497 struct i40e_aq_desc desc;
2498 struct i40e_aqc_get_version *resp =
2499 (struct i40e_aqc_get_version *)&desc.params.raw;
2500 enum i40e_status_code status;
2502 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2504 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2506 if (status == I40E_SUCCESS) {
2507 if (fw_major_version != NULL)
2508 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2509 if (fw_minor_version != NULL)
2510 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2511 if (fw_build != NULL)
2512 *fw_build = LE32_TO_CPU(resp->fw_build);
2513 if (api_major_version != NULL)
2514 *api_major_version = LE16_TO_CPU(resp->api_major);
2515 if (api_minor_version != NULL)
2516 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2518 /* A workaround to fix the API version in SW */
2519 if (api_major_version && api_minor_version &&
2520 fw_major_version && fw_minor_version &&
2521 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2522 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2523 (*fw_major_version > 4)))
2524 *api_minor_version = 2;
2531 * i40e_aq_send_driver_version
2532 * @hw: pointer to the hw struct
2533 * @dv: driver's major, minor version
2534 * @cmd_details: pointer to command details structure or NULL
2536 * Send the driver version to the firmware
2538 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2539 struct i40e_driver_version *dv,
2540 struct i40e_asq_cmd_details *cmd_details)
2542 struct i40e_aq_desc desc;
2543 struct i40e_aqc_driver_version *cmd =
2544 (struct i40e_aqc_driver_version *)&desc.params.raw;
2545 enum i40e_status_code status;
2549 return I40E_ERR_PARAM;
2551 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2553 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2554 cmd->driver_major_ver = dv->major_version;
2555 cmd->driver_minor_ver = dv->minor_version;
2556 cmd->driver_build_ver = dv->build_version;
2557 cmd->driver_subbuild_ver = dv->subbuild_version;
2560 while (len < sizeof(dv->driver_string) &&
2561 (dv->driver_string[len] < 0x80) &&
2562 dv->driver_string[len])
2564 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2571 * i40e_get_link_status - get status of the HW network link
2572 * @hw: pointer to the hw struct
2573 * @link_up: pointer to bool (true/false = linkup/linkdown)
2575 * Variable link_up true if link is up, false if link is down.
2576 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2578 * Side effect: LinkStatusEvent reporting becomes enabled
2580 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2582 enum i40e_status_code status = I40E_SUCCESS;
2584 if (hw->phy.get_link_info) {
2585 status = i40e_update_link_info(hw);
2587 if (status != I40E_SUCCESS)
2588 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2592 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2598 * i40e_updatelink_status - update status of the HW network link
2599 * @hw: pointer to the hw struct
2601 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2603 struct i40e_aq_get_phy_abilities_resp abilities;
2604 enum i40e_status_code status = I40E_SUCCESS;
2606 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2610 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2611 status = i40e_aq_get_phy_capabilities(hw, false, false,
2616 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2617 sizeof(hw->phy.link_info.module_type));
2624 * i40e_get_link_speed
2625 * @hw: pointer to the hw struct
2627 * Returns the link speed of the adapter.
2629 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2631 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2632 enum i40e_status_code status = I40E_SUCCESS;
2634 if (hw->phy.get_link_info) {
2635 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2637 if (status != I40E_SUCCESS)
2638 goto i40e_link_speed_exit;
2641 speed = hw->phy.link_info.link_speed;
2643 i40e_link_speed_exit:
2648 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2649 * @hw: pointer to the hw struct
2650 * @uplink_seid: the MAC or other gizmo SEID
2651 * @downlink_seid: the VSI SEID
2652 * @enabled_tc: bitmap of TCs to be enabled
2653 * @default_port: true for default port VSI, false for control port
2654 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
2655 * @veb_seid: pointer to where to put the resulting VEB SEID
2656 * @cmd_details: pointer to command details structure or NULL
2658 * This asks the FW to add a VEB between the uplink and downlink
2659 * elements. If the uplink SEID is 0, this will be a floating VEB.
2661 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2662 u16 downlink_seid, u8 enabled_tc,
2663 bool default_port, bool enable_l2_filtering,
2665 struct i40e_asq_cmd_details *cmd_details)
2667 struct i40e_aq_desc desc;
2668 struct i40e_aqc_add_veb *cmd =
2669 (struct i40e_aqc_add_veb *)&desc.params.raw;
2670 struct i40e_aqc_add_veb_completion *resp =
2671 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2672 enum i40e_status_code status;
2675 /* SEIDs need to either both be set or both be 0 for floating VEB */
2676 if (!!uplink_seid != !!downlink_seid)
2677 return I40E_ERR_PARAM;
2679 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2681 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2682 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2683 cmd->enable_tcs = enabled_tc;
2685 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2687 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2689 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2691 if (enable_l2_filtering)
2692 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
2694 cmd->veb_flags = CPU_TO_LE16(veb_flags);
2696 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2698 if (!status && veb_seid)
2699 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2705 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2706 * @hw: pointer to the hw struct
2707 * @veb_seid: the SEID of the VEB to query
2708 * @switch_id: the uplink switch id
2709 * @floating: set to true if the VEB is floating
2710 * @statistic_index: index of the stats counter block for this VEB
2711 * @vebs_used: number of VEB's used by function
2712 * @vebs_free: total VEB's not reserved by any function
2713 * @cmd_details: pointer to command details structure or NULL
2715 * This retrieves the parameters for a particular VEB, specified by
2716 * uplink_seid, and returns them to the caller.
2718 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2719 u16 veb_seid, u16 *switch_id,
2720 bool *floating, u16 *statistic_index,
2721 u16 *vebs_used, u16 *vebs_free,
2722 struct i40e_asq_cmd_details *cmd_details)
2724 struct i40e_aq_desc desc;
2725 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2726 (struct i40e_aqc_get_veb_parameters_completion *)
2728 enum i40e_status_code status;
2731 return I40E_ERR_PARAM;
2733 i40e_fill_default_direct_cmd_desc(&desc,
2734 i40e_aqc_opc_get_veb_parameters);
2735 cmd_resp->seid = CPU_TO_LE16(veb_seid);
2737 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2742 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2743 if (statistic_index)
2744 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2746 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2748 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2750 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2751 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2762 * i40e_aq_add_macvlan
2763 * @hw: pointer to the hw struct
2764 * @seid: VSI for the mac address
2765 * @mv_list: list of macvlans to be added
2766 * @count: length of the list
2767 * @cmd_details: pointer to command details structure or NULL
2769 * Add MAC/VLAN addresses to the HW filtering
2771 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2772 struct i40e_aqc_add_macvlan_element_data *mv_list,
2773 u16 count, struct i40e_asq_cmd_details *cmd_details)
2775 struct i40e_aq_desc desc;
2776 struct i40e_aqc_macvlan *cmd =
2777 (struct i40e_aqc_macvlan *)&desc.params.raw;
2778 enum i40e_status_code status;
2781 if (count == 0 || !mv_list || !hw)
2782 return I40E_ERR_PARAM;
2784 buf_size = count * sizeof(*mv_list);
2786 /* prep the rest of the request */
2787 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2788 cmd->num_addresses = CPU_TO_LE16(count);
2789 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2793 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2794 if (buf_size > I40E_AQ_LARGE_BUF)
2795 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2797 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2804 * i40e_aq_remove_macvlan
2805 * @hw: pointer to the hw struct
2806 * @seid: VSI for the mac address
2807 * @mv_list: list of macvlans to be removed
2808 * @count: length of the list
2809 * @cmd_details: pointer to command details structure or NULL
2811 * Remove MAC/VLAN addresses from the HW filtering
2813 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2814 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2815 u16 count, struct i40e_asq_cmd_details *cmd_details)
2817 struct i40e_aq_desc desc;
2818 struct i40e_aqc_macvlan *cmd =
2819 (struct i40e_aqc_macvlan *)&desc.params.raw;
2820 enum i40e_status_code status;
2823 if (count == 0 || !mv_list || !hw)
2824 return I40E_ERR_PARAM;
2826 buf_size = count * sizeof(*mv_list);
2828 /* prep the rest of the request */
2829 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2830 cmd->num_addresses = CPU_TO_LE16(count);
2831 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2835 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2836 if (buf_size > I40E_AQ_LARGE_BUF)
2837 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2839 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2846 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
2847 * @hw: pointer to the hw struct
2848 * @seid: VSI for the vlan filters
2849 * @v_list: list of vlan filters to be added
2850 * @count: length of the list
2851 * @cmd_details: pointer to command details structure or NULL
2853 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
2854 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2855 u8 count, struct i40e_asq_cmd_details *cmd_details)
2857 struct i40e_aq_desc desc;
2858 struct i40e_aqc_macvlan *cmd =
2859 (struct i40e_aqc_macvlan *)&desc.params.raw;
2860 enum i40e_status_code status;
2863 if (count == 0 || !v_list || !hw)
2864 return I40E_ERR_PARAM;
2866 buf_size = count * sizeof(*v_list);
2868 /* prep the rest of the request */
2869 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
2870 cmd->num_addresses = CPU_TO_LE16(count);
2871 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2875 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2876 if (buf_size > I40E_AQ_LARGE_BUF)
2877 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2879 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2886 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
2887 * @hw: pointer to the hw struct
2888 * @seid: VSI for the vlan filters
2889 * @v_list: list of macvlans to be removed
2890 * @count: length of the list
2891 * @cmd_details: pointer to command details structure or NULL
2893 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
2894 struct i40e_aqc_add_remove_vlan_element_data *v_list,
2895 u8 count, struct i40e_asq_cmd_details *cmd_details)
2897 struct i40e_aq_desc desc;
2898 struct i40e_aqc_macvlan *cmd =
2899 (struct i40e_aqc_macvlan *)&desc.params.raw;
2900 enum i40e_status_code status;
2903 if (count == 0 || !v_list || !hw)
2904 return I40E_ERR_PARAM;
2906 buf_size = count * sizeof(*v_list);
2908 /* prep the rest of the request */
2909 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
2910 cmd->num_addresses = CPU_TO_LE16(count);
2911 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
2915 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2916 if (buf_size > I40E_AQ_LARGE_BUF)
2917 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2919 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
2926 * i40e_aq_send_msg_to_vf
2927 * @hw: pointer to the hardware structure
2928 * @vfid: vf id to send msg
2929 * @v_opcode: opcodes for VF-PF communication
2930 * @v_retval: return error code
2931 * @msg: pointer to the msg buffer
2932 * @msglen: msg length
2933 * @cmd_details: pointer to command details
2937 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2938 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2939 struct i40e_asq_cmd_details *cmd_details)
2941 struct i40e_aq_desc desc;
2942 struct i40e_aqc_pf_vf_message *cmd =
2943 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2944 enum i40e_status_code status;
2946 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2947 cmd->id = CPU_TO_LE32(vfid);
2948 desc.cookie_high = CPU_TO_LE32(v_opcode);
2949 desc.cookie_low = CPU_TO_LE32(v_retval);
2950 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
2952 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2954 if (msglen > I40E_AQ_LARGE_BUF)
2955 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2956 desc.datalen = CPU_TO_LE16(msglen);
2958 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2964 * i40e_aq_debug_read_register
2965 * @hw: pointer to the hw struct
2966 * @reg_addr: register address
2967 * @reg_val: register value
2968 * @cmd_details: pointer to command details structure or NULL
2970 * Read the register using the admin queue commands
2972 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
2973 u32 reg_addr, u64 *reg_val,
2974 struct i40e_asq_cmd_details *cmd_details)
2976 struct i40e_aq_desc desc;
2977 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2978 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2979 enum i40e_status_code status;
2981 if (reg_val == NULL)
2982 return I40E_ERR_PARAM;
2984 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2986 cmd_resp->address = CPU_TO_LE32(reg_addr);
2988 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2990 if (status == I40E_SUCCESS) {
2991 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
2992 (u64)LE32_TO_CPU(cmd_resp->value_low);
2999 * i40e_aq_debug_write_register
3000 * @hw: pointer to the hw struct
3001 * @reg_addr: register address
3002 * @reg_val: register value
3003 * @cmd_details: pointer to command details structure or NULL
3005 * Write to a register using the admin queue commands
3007 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3008 u32 reg_addr, u64 reg_val,
3009 struct i40e_asq_cmd_details *cmd_details)
3011 struct i40e_aq_desc desc;
3012 struct i40e_aqc_debug_reg_read_write *cmd =
3013 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3014 enum i40e_status_code status;
3016 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3018 cmd->address = CPU_TO_LE32(reg_addr);
3019 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3020 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3022 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3028 * i40e_aq_get_hmc_resource_profile
3029 * @hw: pointer to the hw struct
3030 * @profile: type of profile the HMC is to be set as
3031 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3032 * @cmd_details: pointer to command details structure or NULL
3034 * query the HMC profile of the device.
3036 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
3037 enum i40e_aq_hmc_profile *profile,
3038 u8 *pe_vf_enabled_count,
3039 struct i40e_asq_cmd_details *cmd_details)
3041 struct i40e_aq_desc desc;
3042 struct i40e_aq_get_set_hmc_resource_profile *resp =
3043 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3044 enum i40e_status_code status;
3046 i40e_fill_default_direct_cmd_desc(&desc,
3047 i40e_aqc_opc_query_hmc_resource_profile);
3048 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3050 *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
3051 I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
3052 *pe_vf_enabled_count = resp->pe_vf_enabled &
3053 I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
3059 * i40e_aq_set_hmc_resource_profile
3060 * @hw: pointer to the hw struct
3061 * @profile: type of profile the HMC is to be set as
3062 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3063 * @cmd_details: pointer to command details structure or NULL
3065 * set the HMC profile of the device.
3067 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
3068 enum i40e_aq_hmc_profile profile,
3069 u8 pe_vf_enabled_count,
3070 struct i40e_asq_cmd_details *cmd_details)
3072 struct i40e_aq_desc desc;
3073 struct i40e_aq_get_set_hmc_resource_profile *cmd =
3074 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3075 enum i40e_status_code status;
3077 i40e_fill_default_direct_cmd_desc(&desc,
3078 i40e_aqc_opc_set_hmc_resource_profile);
3080 cmd->pm_profile = (u8)profile;
3081 cmd->pe_vf_enabled = pe_vf_enabled_count;
3083 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3089 * i40e_aq_request_resource
3090 * @hw: pointer to the hw struct
3091 * @resource: resource id
3092 * @access: access type
3093 * @sdp_number: resource number
3094 * @timeout: the maximum time in ms that the driver may hold the resource
3095 * @cmd_details: pointer to command details structure or NULL
3097 * requests common resource using the admin queue commands
3099 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3100 enum i40e_aq_resources_ids resource,
3101 enum i40e_aq_resource_access_type access,
3102 u8 sdp_number, u64 *timeout,
3103 struct i40e_asq_cmd_details *cmd_details)
3105 struct i40e_aq_desc desc;
3106 struct i40e_aqc_request_resource *cmd_resp =
3107 (struct i40e_aqc_request_resource *)&desc.params.raw;
3108 enum i40e_status_code status;
3110 DEBUGFUNC("i40e_aq_request_resource");
3112 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3114 cmd_resp->resource_id = CPU_TO_LE16(resource);
3115 cmd_resp->access_type = CPU_TO_LE16(access);
3116 cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3118 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3119 /* The completion specifies the maximum time in ms that the driver
3120 * may hold the resource in the Timeout field.
3121 * If the resource is held by someone else, the command completes with
3122 * busy return value and the timeout field indicates the maximum time
3123 * the current owner of the resource has to free it.
3125 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3126 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3132 * i40e_aq_release_resource
3133 * @hw: pointer to the hw struct
3134 * @resource: resource id
3135 * @sdp_number: resource number
3136 * @cmd_details: pointer to command details structure or NULL
3138 * release common resource using the admin queue commands
3140 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3141 enum i40e_aq_resources_ids resource,
3143 struct i40e_asq_cmd_details *cmd_details)
3145 struct i40e_aq_desc desc;
3146 struct i40e_aqc_request_resource *cmd =
3147 (struct i40e_aqc_request_resource *)&desc.params.raw;
3148 enum i40e_status_code status;
3150 DEBUGFUNC("i40e_aq_release_resource");
3152 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3154 cmd->resource_id = CPU_TO_LE16(resource);
3155 cmd->resource_number = CPU_TO_LE32(sdp_number);
3157 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3164 * @hw: pointer to the hw struct
3165 * @module_pointer: module pointer location in words from the NVM beginning
3166 * @offset: byte offset from the module beginning
3167 * @length: length of the section to be read (in bytes from the offset)
3168 * @data: command buffer (size [bytes] = length)
3169 * @last_command: tells if this is the last command in a series
3170 * @cmd_details: pointer to command details structure or NULL
3172 * Read the NVM using the admin queue commands
3174 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3175 u32 offset, u16 length, void *data,
3177 struct i40e_asq_cmd_details *cmd_details)
3179 struct i40e_aq_desc desc;
3180 struct i40e_aqc_nvm_update *cmd =
3181 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3182 enum i40e_status_code status;
3184 DEBUGFUNC("i40e_aq_read_nvm");
3186 /* In offset the highest byte must be zeroed. */
3187 if (offset & 0xFF000000) {
3188 status = I40E_ERR_PARAM;
3189 goto i40e_aq_read_nvm_exit;
3192 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3194 /* If this is the last command in a series, set the proper flag. */
3196 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3197 cmd->module_pointer = module_pointer;
3198 cmd->offset = CPU_TO_LE32(offset);
3199 cmd->length = CPU_TO_LE16(length);
3201 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3202 if (length > I40E_AQ_LARGE_BUF)
3203 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3205 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3207 i40e_aq_read_nvm_exit:
3212 * i40e_aq_read_nvm_config - read an nvm config block
3213 * @hw: pointer to the hw struct
3214 * @cmd_flags: NVM access admin command bits
3215 * @field_id: field or feature id
3216 * @data: buffer for result
3217 * @buf_size: buffer size
3218 * @element_count: pointer to count of elements read by FW
3219 * @cmd_details: pointer to command details structure or NULL
3221 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3222 u8 cmd_flags, u32 field_id, void *data,
3223 u16 buf_size, u16 *element_count,
3224 struct i40e_asq_cmd_details *cmd_details)
3226 struct i40e_aq_desc desc;
3227 struct i40e_aqc_nvm_config_read *cmd =
3228 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3229 enum i40e_status_code status;
3231 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3232 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3233 if (buf_size > I40E_AQ_LARGE_BUF)
3234 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3236 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3237 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3238 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3239 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3241 cmd->element_id_msw = 0;
3243 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3245 if (!status && element_count)
3246 *element_count = LE16_TO_CPU(cmd->element_count);
3252 * i40e_aq_write_nvm_config - write an nvm config block
3253 * @hw: pointer to the hw struct
3254 * @cmd_flags: NVM access admin command bits
3255 * @data: buffer for result
3256 * @buf_size: buffer size
3257 * @element_count: count of elements to be written
3258 * @cmd_details: pointer to command details structure or NULL
3260 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3261 u8 cmd_flags, void *data, u16 buf_size,
3263 struct i40e_asq_cmd_details *cmd_details)
3265 struct i40e_aq_desc desc;
3266 struct i40e_aqc_nvm_config_write *cmd =
3267 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3268 enum i40e_status_code status;
3270 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3271 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3272 if (buf_size > I40E_AQ_LARGE_BUF)
3273 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3275 cmd->element_count = CPU_TO_LE16(element_count);
3276 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3277 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3283 * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3284 * @hw: pointer to the hw struct
3285 * @cmd_details: pointer to command details structure or NULL
3287 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3288 void *buff, u16 buff_size,
3289 struct i40e_asq_cmd_details *cmd_details)
3291 struct i40e_aq_desc desc;
3292 enum i40e_status_code status;
3294 UNREFERENCED_2PARAMETER(buff, buff_size);
3296 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3297 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3298 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3299 status = I40E_ERR_NOT_IMPLEMENTED;
3306 * @hw: pointer to the hw struct
3307 * @module_pointer: module pointer location in words from the NVM beginning
3308 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3309 * @length: length of the section to be erased (expressed in 4 KB)
3310 * @last_command: tells if this is the last command in a series
3311 * @cmd_details: pointer to command details structure or NULL
3313 * Erase the NVM sector using the admin queue commands
3315 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3316 u32 offset, u16 length, bool last_command,
3317 struct i40e_asq_cmd_details *cmd_details)
3319 struct i40e_aq_desc desc;
3320 struct i40e_aqc_nvm_update *cmd =
3321 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3322 enum i40e_status_code status;
3324 DEBUGFUNC("i40e_aq_erase_nvm");
3326 /* In offset the highest byte must be zeroed. */
3327 if (offset & 0xFF000000) {
3328 status = I40E_ERR_PARAM;
3329 goto i40e_aq_erase_nvm_exit;
3332 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3334 /* If this is the last command in a series, set the proper flag. */
3336 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3337 cmd->module_pointer = module_pointer;
3338 cmd->offset = CPU_TO_LE32(offset);
3339 cmd->length = CPU_TO_LE16(length);
3341 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3343 i40e_aq_erase_nvm_exit:
3348 * i40e_parse_discover_capabilities
3349 * @hw: pointer to the hw struct
3350 * @buff: pointer to a buffer containing device/function capability records
3351 * @cap_count: number of capability records in the list
3352 * @list_type_opc: type of capabilities list to parse
3354 * Parse the device/function capabilities list.
3356 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3358 enum i40e_admin_queue_opc list_type_opc)
3360 struct i40e_aqc_list_capabilities_element_resp *cap;
3361 u32 valid_functions, num_functions;
3362 u32 number, logical_id, phys_id;
3363 struct i40e_hw_capabilities *p;
3368 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3370 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3371 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3372 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3373 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3377 for (i = 0; i < cap_count; i++, cap++) {
3378 id = LE16_TO_CPU(cap->id);
3379 number = LE32_TO_CPU(cap->number);
3380 logical_id = LE32_TO_CPU(cap->logical_id);
3381 phys_id = LE32_TO_CPU(cap->phys_id);
3382 major_rev = cap->major_rev;
3385 case I40E_AQ_CAP_ID_SWITCH_MODE:
3386 p->switch_mode = number;
3387 i40e_debug(hw, I40E_DEBUG_INIT,
3388 "HW Capability: Switch mode = %d\n",
3391 case I40E_AQ_CAP_ID_MNG_MODE:
3392 p->management_mode = number;
3393 i40e_debug(hw, I40E_DEBUG_INIT,
3394 "HW Capability: Management Mode = %d\n",
3395 p->management_mode);
3397 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3398 p->npar_enable = number;
3399 i40e_debug(hw, I40E_DEBUG_INIT,
3400 "HW Capability: NPAR enable = %d\n",
3403 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3405 i40e_debug(hw, I40E_DEBUG_INIT,
3406 "HW Capability: OS2BMC = %d\n", p->os2bmc);
3408 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3409 p->valid_functions = number;
3410 i40e_debug(hw, I40E_DEBUG_INIT,
3411 "HW Capability: Valid Functions = %d\n",
3412 p->valid_functions);
3414 case I40E_AQ_CAP_ID_SRIOV:
3416 p->sr_iov_1_1 = true;
3417 i40e_debug(hw, I40E_DEBUG_INIT,
3418 "HW Capability: SR-IOV = %d\n",
3421 case I40E_AQ_CAP_ID_VF:
3422 p->num_vfs = number;
3423 p->vf_base_id = logical_id;
3424 i40e_debug(hw, I40E_DEBUG_INIT,
3425 "HW Capability: VF count = %d\n",
3427 i40e_debug(hw, I40E_DEBUG_INIT,
3428 "HW Capability: VF base_id = %d\n",
3431 case I40E_AQ_CAP_ID_VMDQ:
3434 i40e_debug(hw, I40E_DEBUG_INIT,
3435 "HW Capability: VMDQ = %d\n", p->vmdq);
3437 case I40E_AQ_CAP_ID_8021QBG:
3439 p->evb_802_1_qbg = true;
3440 i40e_debug(hw, I40E_DEBUG_INIT,
3441 "HW Capability: 802.1Qbg = %d\n", number);
3443 case I40E_AQ_CAP_ID_8021QBR:
3445 p->evb_802_1_qbh = true;
3446 i40e_debug(hw, I40E_DEBUG_INIT,
3447 "HW Capability: 802.1Qbh = %d\n", number);
3449 case I40E_AQ_CAP_ID_VSI:
3450 p->num_vsis = number;
3451 i40e_debug(hw, I40E_DEBUG_INIT,
3452 "HW Capability: VSI count = %d\n",
3455 case I40E_AQ_CAP_ID_DCB:
3458 p->enabled_tcmap = logical_id;
3461 i40e_debug(hw, I40E_DEBUG_INIT,
3462 "HW Capability: DCB = %d\n", p->dcb);
3463 i40e_debug(hw, I40E_DEBUG_INIT,
3464 "HW Capability: TC Mapping = %d\n",
3466 i40e_debug(hw, I40E_DEBUG_INIT,
3467 "HW Capability: TC Max = %d\n", p->maxtc);
3469 case I40E_AQ_CAP_ID_FCOE:
3472 i40e_debug(hw, I40E_DEBUG_INIT,
3473 "HW Capability: FCOE = %d\n", p->fcoe);
3475 case I40E_AQ_CAP_ID_ISCSI:
3478 i40e_debug(hw, I40E_DEBUG_INIT,
3479 "HW Capability: iSCSI = %d\n", p->iscsi);
3481 case I40E_AQ_CAP_ID_RSS:
3483 p->rss_table_size = number;
3484 p->rss_table_entry_width = logical_id;
3485 i40e_debug(hw, I40E_DEBUG_INIT,
3486 "HW Capability: RSS = %d\n", p->rss);
3487 i40e_debug(hw, I40E_DEBUG_INIT,
3488 "HW Capability: RSS table size = %d\n",
3490 i40e_debug(hw, I40E_DEBUG_INIT,
3491 "HW Capability: RSS table width = %d\n",
3492 p->rss_table_entry_width);
3494 case I40E_AQ_CAP_ID_RXQ:
3495 p->num_rx_qp = number;
3496 p->base_queue = phys_id;
3497 i40e_debug(hw, I40E_DEBUG_INIT,
3498 "HW Capability: Rx QP = %d\n", number);
3499 i40e_debug(hw, I40E_DEBUG_INIT,
3500 "HW Capability: base_queue = %d\n",
3503 case I40E_AQ_CAP_ID_TXQ:
3504 p->num_tx_qp = number;
3505 p->base_queue = phys_id;
3506 i40e_debug(hw, I40E_DEBUG_INIT,
3507 "HW Capability: Tx QP = %d\n", number);
3508 i40e_debug(hw, I40E_DEBUG_INIT,
3509 "HW Capability: base_queue = %d\n",
3512 case I40E_AQ_CAP_ID_MSIX:
3513 p->num_msix_vectors = number;
3514 i40e_debug(hw, I40E_DEBUG_INIT,
3515 "HW Capability: MSIX vector count = %d\n",
3516 p->num_msix_vectors_vf);
3518 case I40E_AQ_CAP_ID_VF_MSIX:
3519 p->num_msix_vectors_vf = number;
3520 i40e_debug(hw, I40E_DEBUG_INIT,
3521 "HW Capability: MSIX VF vector count = %d\n",
3522 p->num_msix_vectors_vf);
3524 case I40E_AQ_CAP_ID_FLEX10:
3525 if (major_rev == 1) {
3527 p->flex10_enable = true;
3528 p->flex10_capable = true;
3531 /* Capability revision >= 2 */
3533 p->flex10_enable = true;
3535 p->flex10_capable = true;
3537 p->flex10_mode = logical_id;
3538 p->flex10_status = phys_id;
3539 i40e_debug(hw, I40E_DEBUG_INIT,
3540 "HW Capability: Flex10 mode = %d\n",
3542 i40e_debug(hw, I40E_DEBUG_INIT,
3543 "HW Capability: Flex10 status = %d\n",
3546 case I40E_AQ_CAP_ID_CEM:
3549 i40e_debug(hw, I40E_DEBUG_INIT,
3550 "HW Capability: CEM = %d\n", p->mgmt_cem);
3552 case I40E_AQ_CAP_ID_IWARP:
3555 i40e_debug(hw, I40E_DEBUG_INIT,
3556 "HW Capability: iWARP = %d\n", p->iwarp);
3558 case I40E_AQ_CAP_ID_LED:
3559 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3560 p->led[phys_id] = true;
3561 i40e_debug(hw, I40E_DEBUG_INIT,
3562 "HW Capability: LED - PIN %d\n", phys_id);
3564 case I40E_AQ_CAP_ID_SDP:
3565 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3566 p->sdp[phys_id] = true;
3567 i40e_debug(hw, I40E_DEBUG_INIT,
3568 "HW Capability: SDP - PIN %d\n", phys_id);
3570 case I40E_AQ_CAP_ID_MDIO:
3572 p->mdio_port_num = phys_id;
3573 p->mdio_port_mode = logical_id;
3575 i40e_debug(hw, I40E_DEBUG_INIT,
3576 "HW Capability: MDIO port number = %d\n",
3578 i40e_debug(hw, I40E_DEBUG_INIT,
3579 "HW Capability: MDIO port mode = %d\n",
3582 case I40E_AQ_CAP_ID_1588:
3584 p->ieee_1588 = true;
3585 i40e_debug(hw, I40E_DEBUG_INIT,
3586 "HW Capability: IEEE 1588 = %d\n",
3589 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3591 p->fd_filters_guaranteed = number;
3592 p->fd_filters_best_effort = logical_id;
3593 i40e_debug(hw, I40E_DEBUG_INIT,
3594 "HW Capability: Flow Director = 1\n");
3595 i40e_debug(hw, I40E_DEBUG_INIT,
3596 "HW Capability: Guaranteed FD filters = %d\n",
3597 p->fd_filters_guaranteed);
3599 case I40E_AQ_CAP_ID_WSR_PROT:
3600 p->wr_csr_prot = (u64)number;
3601 p->wr_csr_prot |= (u64)logical_id << 32;
3602 i40e_debug(hw, I40E_DEBUG_INIT,
3603 "HW Capability: wr_csr_prot = 0x%llX\n\n",
3604 (p->wr_csr_prot & 0xffff));
3607 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3608 hw->num_wol_proxy_filters = (u16)number;
3609 hw->wol_proxy_vsi_seid = (u16)logical_id;
3610 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3611 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3612 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3614 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3615 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3616 p->proxy_support = p->proxy_support;
3617 i40e_debug(hw, I40E_DEBUG_INIT,
3618 "HW Capability: WOL proxy filters = %d\n",
3619 hw->num_wol_proxy_filters);
3628 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3630 #ifdef I40E_FCOE_ENA
3631 /* Software override ensuring FCoE is disabled if npar or mfp
3632 * mode because it is not supported in these modes.
3634 if (p->npar_enable || p->flex10_enable)
3637 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3641 /* count the enabled ports (aka the "not disabled" ports) */
3643 for (i = 0; i < 4; i++) {
3644 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3647 /* use AQ read to get the physical register offset instead
3648 * of the port relative offset
3650 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3651 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3655 valid_functions = p->valid_functions;
3657 while (valid_functions) {
3658 if (valid_functions & 1)
3660 valid_functions >>= 1;
3663 /* partition id is 1-based, and functions are evenly spread
3664 * across the ports as partitions
3666 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3667 hw->num_partitions = num_functions / hw->num_ports;
3669 /* additional HW specific goodies that might
3670 * someday be HW version specific
3672 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3676 * i40e_aq_discover_capabilities
3677 * @hw: pointer to the hw struct
3678 * @buff: a virtual buffer to hold the capabilities
3679 * @buff_size: Size of the virtual buffer
3680 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3681 * @list_type_opc: capabilities type to discover - pass in the command opcode
3682 * @cmd_details: pointer to command details structure or NULL
3684 * Get the device capabilities descriptions from the firmware
3686 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3687 void *buff, u16 buff_size, u16 *data_size,
3688 enum i40e_admin_queue_opc list_type_opc,
3689 struct i40e_asq_cmd_details *cmd_details)
3691 struct i40e_aqc_list_capabilites *cmd;
3692 struct i40e_aq_desc desc;
3693 enum i40e_status_code status = I40E_SUCCESS;
3695 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3697 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3698 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3699 status = I40E_ERR_PARAM;
3703 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3705 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3706 if (buff_size > I40E_AQ_LARGE_BUF)
3707 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3709 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3710 *data_size = LE16_TO_CPU(desc.datalen);
3715 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3723 * i40e_aq_update_nvm
3724 * @hw: pointer to the hw struct
3725 * @module_pointer: module pointer location in words from the NVM beginning
3726 * @offset: byte offset from the module beginning
3727 * @length: length of the section to be written (in bytes from the offset)
3728 * @data: command buffer (size [bytes] = length)
3729 * @last_command: tells if this is the last command in a series
3730 * @cmd_details: pointer to command details structure or NULL
3732 * Update the NVM using the admin queue commands
3734 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3735 u32 offset, u16 length, void *data,
3737 struct i40e_asq_cmd_details *cmd_details)
3739 struct i40e_aq_desc desc;
3740 struct i40e_aqc_nvm_update *cmd =
3741 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3742 enum i40e_status_code status;
3744 DEBUGFUNC("i40e_aq_update_nvm");
3746 /* In offset the highest byte must be zeroed. */
3747 if (offset & 0xFF000000) {
3748 status = I40E_ERR_PARAM;
3749 goto i40e_aq_update_nvm_exit;
3752 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3754 /* If this is the last command in a series, set the proper flag. */
3756 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3757 cmd->module_pointer = module_pointer;
3758 cmd->offset = CPU_TO_LE32(offset);
3759 cmd->length = CPU_TO_LE16(length);
3761 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3762 if (length > I40E_AQ_LARGE_BUF)
3763 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3765 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3767 i40e_aq_update_nvm_exit:
3772 * i40e_aq_get_lldp_mib
3773 * @hw: pointer to the hw struct
3774 * @bridge_type: type of bridge requested
3775 * @mib_type: Local, Remote or both Local and Remote MIBs
3776 * @buff: pointer to a user supplied buffer to store the MIB block
3777 * @buff_size: size of the buffer (in bytes)
3778 * @local_len : length of the returned Local LLDP MIB
3779 * @remote_len: length of the returned Remote LLDP MIB
3780 * @cmd_details: pointer to command details structure or NULL
3782 * Requests the complete LLDP MIB (entire packet).
3784 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3785 u8 mib_type, void *buff, u16 buff_size,
3786 u16 *local_len, u16 *remote_len,
3787 struct i40e_asq_cmd_details *cmd_details)
3789 struct i40e_aq_desc desc;
3790 struct i40e_aqc_lldp_get_mib *cmd =
3791 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3792 struct i40e_aqc_lldp_get_mib *resp =
3793 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3794 enum i40e_status_code status;
3796 if (buff_size == 0 || !buff)
3797 return I40E_ERR_PARAM;
3799 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3800 /* Indirect Command */
3801 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3803 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3804 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3805 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3807 desc.datalen = CPU_TO_LE16(buff_size);
3809 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3810 if (buff_size > I40E_AQ_LARGE_BUF)
3811 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3813 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3815 if (local_len != NULL)
3816 *local_len = LE16_TO_CPU(resp->local_len);
3817 if (remote_len != NULL)
3818 *remote_len = LE16_TO_CPU(resp->remote_len);
3825 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3826 * @hw: pointer to the hw struct
3827 * @mib_type: Local, Remote or both Local and Remote MIBs
3828 * @buff: pointer to a user supplied buffer to store the MIB block
3829 * @buff_size: size of the buffer (in bytes)
3830 * @cmd_details: pointer to command details structure or NULL
3834 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3835 u8 mib_type, void *buff, u16 buff_size,
3836 struct i40e_asq_cmd_details *cmd_details)
3838 struct i40e_aq_desc desc;
3839 struct i40e_aqc_lldp_set_local_mib *cmd =
3840 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3841 enum i40e_status_code status;
3843 if (buff_size == 0 || !buff)
3844 return I40E_ERR_PARAM;
3846 i40e_fill_default_direct_cmd_desc(&desc,
3847 i40e_aqc_opc_lldp_set_local_mib);
3848 /* Indirect Command */
3849 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3850 if (buff_size > I40E_AQ_LARGE_BUF)
3851 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3852 desc.datalen = CPU_TO_LE16(buff_size);
3854 cmd->type = mib_type;
3855 cmd->length = CPU_TO_LE16(buff_size);
3856 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
3857 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
3859 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3864 * i40e_aq_cfg_lldp_mib_change_event
3865 * @hw: pointer to the hw struct
3866 * @enable_update: Enable or Disable event posting
3867 * @cmd_details: pointer to command details structure or NULL
3869 * Enable or Disable posting of an event on ARQ when LLDP MIB
3870 * associated with the interface changes
3872 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3874 struct i40e_asq_cmd_details *cmd_details)
3876 struct i40e_aq_desc desc;
3877 struct i40e_aqc_lldp_update_mib *cmd =
3878 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3879 enum i40e_status_code status;
3881 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3884 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3886 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3892 * i40e_aq_add_lldp_tlv
3893 * @hw: pointer to the hw struct
3894 * @bridge_type: type of bridge
3895 * @buff: buffer with TLV to add
3896 * @buff_size: length of the buffer
3897 * @tlv_len: length of the TLV to be added
3898 * @mib_len: length of the LLDP MIB returned in response
3899 * @cmd_details: pointer to command details structure or NULL
3901 * Add the specified TLV to LLDP Local MIB for the given bridge type,
3902 * it is responsibility of the caller to make sure that the TLV is not
3903 * already present in the LLDPDU.
3904 * In return firmware will write the complete LLDP MIB with the newly
3905 * added TLV in the response buffer.
3907 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
3908 void *buff, u16 buff_size, u16 tlv_len,
3910 struct i40e_asq_cmd_details *cmd_details)
3912 struct i40e_aq_desc desc;
3913 struct i40e_aqc_lldp_add_tlv *cmd =
3914 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
3915 enum i40e_status_code status;
3917 if (buff_size == 0 || !buff || tlv_len == 0)
3918 return I40E_ERR_PARAM;
3920 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
3922 /* Indirect Command */
3923 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3924 if (buff_size > I40E_AQ_LARGE_BUF)
3925 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3926 desc.datalen = CPU_TO_LE16(buff_size);
3928 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3929 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3930 cmd->len = CPU_TO_LE16(tlv_len);
3932 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3934 if (mib_len != NULL)
3935 *mib_len = LE16_TO_CPU(desc.datalen);
3942 * i40e_aq_update_lldp_tlv
3943 * @hw: pointer to the hw struct
3944 * @bridge_type: type of bridge
3945 * @buff: buffer with TLV to update
3946 * @buff_size: size of the buffer holding original and updated TLVs
3947 * @old_len: Length of the Original TLV
3948 * @new_len: Length of the Updated TLV
3949 * @offset: offset of the updated TLV in the buff
3950 * @mib_len: length of the returned LLDP MIB
3951 * @cmd_details: pointer to command details structure or NULL
3953 * Update the specified TLV to the LLDP Local MIB for the given bridge type.
3954 * Firmware will place the complete LLDP MIB in response buffer with the
3957 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
3958 u8 bridge_type, void *buff, u16 buff_size,
3959 u16 old_len, u16 new_len, u16 offset,
3961 struct i40e_asq_cmd_details *cmd_details)
3963 struct i40e_aq_desc desc;
3964 struct i40e_aqc_lldp_update_tlv *cmd =
3965 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
3966 enum i40e_status_code status;
3968 if (buff_size == 0 || !buff || offset == 0 ||
3969 old_len == 0 || new_len == 0)
3970 return I40E_ERR_PARAM;
3972 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
3974 /* Indirect Command */
3975 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3976 if (buff_size > I40E_AQ_LARGE_BUF)
3977 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3978 desc.datalen = CPU_TO_LE16(buff_size);
3980 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3981 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3982 cmd->old_len = CPU_TO_LE16(old_len);
3983 cmd->new_offset = CPU_TO_LE16(offset);
3984 cmd->new_len = CPU_TO_LE16(new_len);
3986 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3988 if (mib_len != NULL)
3989 *mib_len = LE16_TO_CPU(desc.datalen);
3996 * i40e_aq_delete_lldp_tlv
3997 * @hw: pointer to the hw struct
3998 * @bridge_type: type of bridge
3999 * @buff: pointer to a user supplied buffer that has the TLV
4000 * @buff_size: length of the buffer
4001 * @tlv_len: length of the TLV to be deleted
4002 * @mib_len: length of the returned LLDP MIB
4003 * @cmd_details: pointer to command details structure or NULL
4005 * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4006 * The firmware places the entire LLDP MIB in the response buffer.
4008 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4009 u8 bridge_type, void *buff, u16 buff_size,
4010 u16 tlv_len, u16 *mib_len,
4011 struct i40e_asq_cmd_details *cmd_details)
4013 struct i40e_aq_desc desc;
4014 struct i40e_aqc_lldp_add_tlv *cmd =
4015 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4016 enum i40e_status_code status;
4018 if (buff_size == 0 || !buff)
4019 return I40E_ERR_PARAM;
4021 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4023 /* Indirect Command */
4024 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4025 if (buff_size > I40E_AQ_LARGE_BUF)
4026 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4027 desc.datalen = CPU_TO_LE16(buff_size);
4028 cmd->len = CPU_TO_LE16(tlv_len);
4029 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4030 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4032 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4034 if (mib_len != NULL)
4035 *mib_len = LE16_TO_CPU(desc.datalen);
4043 * @hw: pointer to the hw struct
4044 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4045 * @cmd_details: pointer to command details structure or NULL
4047 * Stop or Shutdown the embedded LLDP Agent
4049 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4050 struct i40e_asq_cmd_details *cmd_details)
4052 struct i40e_aq_desc desc;
4053 struct i40e_aqc_lldp_stop *cmd =
4054 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4055 enum i40e_status_code status;
4057 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4060 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4062 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4068 * i40e_aq_start_lldp
4069 * @hw: pointer to the hw struct
4070 * @cmd_details: pointer to command details structure or NULL
4072 * Start the embedded LLDP Agent on all ports.
4074 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4075 struct i40e_asq_cmd_details *cmd_details)
4077 struct i40e_aq_desc desc;
4078 struct i40e_aqc_lldp_start *cmd =
4079 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4080 enum i40e_status_code status;
4082 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4084 cmd->command = I40E_AQ_LLDP_AGENT_START;
4086 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4092 * i40e_aq_get_cee_dcb_config
4093 * @hw: pointer to the hw struct
4094 * @buff: response buffer that stores CEE operational configuration
4095 * @buff_size: size of the buffer passed
4096 * @cmd_details: pointer to command details structure or NULL
4098 * Get CEE DCBX mode operational configuration from firmware
4100 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4101 void *buff, u16 buff_size,
4102 struct i40e_asq_cmd_details *cmd_details)
4104 struct i40e_aq_desc desc;
4105 enum i40e_status_code status;
4107 if (buff_size == 0 || !buff)
4108 return I40E_ERR_PARAM;
4110 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4112 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4113 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4120 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4121 * @hw: pointer to the hw struct
4122 * @start_agent: True if DCBx Agent needs to be Started
4123 * False if DCBx Agent needs to be Stopped
4124 * @cmd_details: pointer to command details structure or NULL
4126 * Start/Stop the embedded dcbx Agent
4128 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4130 struct i40e_asq_cmd_details *cmd_details)
4132 struct i40e_aq_desc desc;
4133 struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4134 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4136 enum i40e_status_code status;
4138 i40e_fill_default_direct_cmd_desc(&desc,
4139 i40e_aqc_opc_lldp_stop_start_spec_agent);
4142 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4144 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4150 * i40e_aq_add_udp_tunnel
4151 * @hw: pointer to the hw struct
4152 * @udp_port: the UDP port to add
4153 * @header_len: length of the tunneling header length in DWords
4154 * @protocol_index: protocol index type
4155 * @filter_index: pointer to filter index
4156 * @cmd_details: pointer to command details structure or NULL
4158 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4159 u16 udp_port, u8 protocol_index,
4161 struct i40e_asq_cmd_details *cmd_details)
4163 struct i40e_aq_desc desc;
4164 struct i40e_aqc_add_udp_tunnel *cmd =
4165 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4166 struct i40e_aqc_del_udp_tunnel_completion *resp =
4167 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4168 enum i40e_status_code status;
4170 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4172 cmd->udp_port = CPU_TO_LE16(udp_port);
4173 cmd->protocol_type = protocol_index;
4175 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4177 if (!status && filter_index)
4178 *filter_index = resp->index;
4184 * i40e_aq_del_udp_tunnel
4185 * @hw: pointer to the hw struct
4186 * @index: filter index
4187 * @cmd_details: pointer to command details structure or NULL
4189 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4190 struct i40e_asq_cmd_details *cmd_details)
4192 struct i40e_aq_desc desc;
4193 struct i40e_aqc_remove_udp_tunnel *cmd =
4194 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4195 enum i40e_status_code status;
4197 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4201 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4207 * i40e_aq_get_switch_resource_alloc (0x0204)
4208 * @hw: pointer to the hw struct
4209 * @num_entries: pointer to u8 to store the number of resource entries returned
4210 * @buf: pointer to a user supplied buffer. This buffer must be large enough
4211 * to store the resource information for all resource types. Each
4212 * resource type is a i40e_aqc_switch_resource_alloc_data structure.
4213 * @count: size, in bytes, of the buffer provided
4214 * @cmd_details: pointer to command details structure or NULL
4216 * Query the resources allocated to a function.
4218 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4220 struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4222 struct i40e_asq_cmd_details *cmd_details)
4224 struct i40e_aq_desc desc;
4225 struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4226 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4227 enum i40e_status_code status;
4228 u16 length = count * sizeof(*buf);
4230 i40e_fill_default_direct_cmd_desc(&desc,
4231 i40e_aqc_opc_get_switch_resource_alloc);
4233 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4234 if (length > I40E_AQ_LARGE_BUF)
4235 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4237 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4239 if (!status && num_entries)
4240 *num_entries = cmd_resp->num_entries;
4246 * i40e_aq_delete_element - Delete switch element
4247 * @hw: pointer to the hw struct
4248 * @seid: the SEID to delete from the switch
4249 * @cmd_details: pointer to command details structure or NULL
4251 * This deletes a switch element from the switch.
4253 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4254 struct i40e_asq_cmd_details *cmd_details)
4256 struct i40e_aq_desc desc;
4257 struct i40e_aqc_switch_seid *cmd =
4258 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4259 enum i40e_status_code status;
4262 return I40E_ERR_PARAM;
4264 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4266 cmd->seid = CPU_TO_LE16(seid);
4268 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4274 * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4275 * @hw: pointer to the hw struct
4276 * @flags: component flags
4277 * @mac_seid: uplink seid (MAC SEID)
4278 * @vsi_seid: connected vsi seid
4279 * @ret_seid: seid of create pv component
4281 * This instantiates an i40e port virtualizer with specified flags.
4282 * Depending on specified flags the port virtualizer can act as a
4283 * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4285 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4286 u16 mac_seid, u16 vsi_seid,
4289 struct i40e_aq_desc desc;
4290 struct i40e_aqc_add_update_pv *cmd =
4291 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4292 struct i40e_aqc_add_update_pv_completion *resp =
4293 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4294 enum i40e_status_code status;
4297 return I40E_ERR_PARAM;
4299 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4300 cmd->command_flags = CPU_TO_LE16(flags);
4301 cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4302 cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4304 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4305 if (!status && ret_seid)
4306 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4312 * i40e_aq_add_tag - Add an S/E-tag
4313 * @hw: pointer to the hw struct
4314 * @direct_to_queue: should s-tag direct flow to a specific queue
4315 * @vsi_seid: VSI SEID to use this tag
4316 * @tag: value of the tag
4317 * @queue_num: queue number, only valid is direct_to_queue is true
4318 * @tags_used: return value, number of tags in use by this PF
4319 * @tags_free: return value, number of unallocated tags
4320 * @cmd_details: pointer to command details structure or NULL
4322 * This associates an S- or E-tag to a VSI in the switch complex. It returns
4323 * the number of tags allocated by the PF, and the number of unallocated
4326 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4327 u16 vsi_seid, u16 tag, u16 queue_num,
4328 u16 *tags_used, u16 *tags_free,
4329 struct i40e_asq_cmd_details *cmd_details)
4331 struct i40e_aq_desc desc;
4332 struct i40e_aqc_add_tag *cmd =
4333 (struct i40e_aqc_add_tag *)&desc.params.raw;
4334 struct i40e_aqc_add_remove_tag_completion *resp =
4335 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4336 enum i40e_status_code status;
4339 return I40E_ERR_PARAM;
4341 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4343 cmd->seid = CPU_TO_LE16(vsi_seid);
4344 cmd->tag = CPU_TO_LE16(tag);
4345 if (direct_to_queue) {
4346 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4347 cmd->queue_number = CPU_TO_LE16(queue_num);
4350 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4353 if (tags_used != NULL)
4354 *tags_used = LE16_TO_CPU(resp->tags_used);
4355 if (tags_free != NULL)
4356 *tags_free = LE16_TO_CPU(resp->tags_free);
4363 * i40e_aq_remove_tag - Remove an S- or E-tag
4364 * @hw: pointer to the hw struct
4365 * @vsi_seid: VSI SEID this tag is associated with
4366 * @tag: value of the S-tag to delete
4367 * @tags_used: return value, number of tags in use by this PF
4368 * @tags_free: return value, number of unallocated tags
4369 * @cmd_details: pointer to command details structure or NULL
4371 * This deletes an S- or E-tag from a VSI in the switch complex. It returns
4372 * the number of tags allocated by the PF, and the number of unallocated
4375 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4376 u16 tag, u16 *tags_used, u16 *tags_free,
4377 struct i40e_asq_cmd_details *cmd_details)
4379 struct i40e_aq_desc desc;
4380 struct i40e_aqc_remove_tag *cmd =
4381 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4382 struct i40e_aqc_add_remove_tag_completion *resp =
4383 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4384 enum i40e_status_code status;
4387 return I40E_ERR_PARAM;
4389 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4391 cmd->seid = CPU_TO_LE16(vsi_seid);
4392 cmd->tag = CPU_TO_LE16(tag);
4394 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4397 if (tags_used != NULL)
4398 *tags_used = LE16_TO_CPU(resp->tags_used);
4399 if (tags_free != NULL)
4400 *tags_free = LE16_TO_CPU(resp->tags_free);
4407 * i40e_aq_add_mcast_etag - Add a multicast E-tag
4408 * @hw: pointer to the hw struct
4409 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4410 * @etag: value of E-tag to add
4411 * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4412 * @buf: address of indirect buffer
4413 * @tags_used: return value, number of E-tags in use by this port
4414 * @tags_free: return value, number of unallocated M-tags
4415 * @cmd_details: pointer to command details structure or NULL
4417 * This associates a multicast E-tag to a port virtualizer. It will return
4418 * the number of tags allocated by the PF, and the number of unallocated
4421 * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4422 * num_tags_in_buf long.
4424 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4425 u16 etag, u8 num_tags_in_buf, void *buf,
4426 u16 *tags_used, u16 *tags_free,
4427 struct i40e_asq_cmd_details *cmd_details)
4429 struct i40e_aq_desc desc;
4430 struct i40e_aqc_add_remove_mcast_etag *cmd =
4431 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4432 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4433 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4434 enum i40e_status_code status;
4435 u16 length = sizeof(u16) * num_tags_in_buf;
4437 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4438 return I40E_ERR_PARAM;
4440 i40e_fill_default_direct_cmd_desc(&desc,
4441 i40e_aqc_opc_add_multicast_etag);
4443 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4444 cmd->etag = CPU_TO_LE16(etag);
4445 cmd->num_unicast_etags = num_tags_in_buf;
4447 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4448 if (length > I40E_AQ_LARGE_BUF)
4449 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4451 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4454 if (tags_used != NULL)
4455 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4456 if (tags_free != NULL)
4457 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4464 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4465 * @hw: pointer to the hw struct
4466 * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4467 * @etag: value of the E-tag to remove
4468 * @tags_used: return value, number of tags in use by this port
4469 * @tags_free: return value, number of unallocated tags
4470 * @cmd_details: pointer to command details structure or NULL
4472 * This deletes an E-tag from the port virtualizer. It will return
4473 * the number of tags allocated by the port, and the number of unallocated
4476 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4477 u16 etag, u16 *tags_used, u16 *tags_free,
4478 struct i40e_asq_cmd_details *cmd_details)
4480 struct i40e_aq_desc desc;
4481 struct i40e_aqc_add_remove_mcast_etag *cmd =
4482 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4483 struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4484 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4485 enum i40e_status_code status;
4489 return I40E_ERR_PARAM;
4491 i40e_fill_default_direct_cmd_desc(&desc,
4492 i40e_aqc_opc_remove_multicast_etag);
4494 cmd->pv_seid = CPU_TO_LE16(pv_seid);
4495 cmd->etag = CPU_TO_LE16(etag);
4497 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4500 if (tags_used != NULL)
4501 *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4502 if (tags_free != NULL)
4503 *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4510 * i40e_aq_update_tag - Update an S/E-tag
4511 * @hw: pointer to the hw struct
4512 * @vsi_seid: VSI SEID using this S-tag
4513 * @old_tag: old tag value
4514 * @new_tag: new tag value
4515 * @tags_used: return value, number of tags in use by this PF
4516 * @tags_free: return value, number of unallocated tags
4517 * @cmd_details: pointer to command details structure or NULL
4519 * This updates the value of the tag currently attached to this VSI
4520 * in the switch complex. It will return the number of tags allocated
4521 * by the PF, and the number of unallocated tags available.
4523 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4524 u16 old_tag, u16 new_tag, u16 *tags_used,
4526 struct i40e_asq_cmd_details *cmd_details)
4528 struct i40e_aq_desc desc;
4529 struct i40e_aqc_update_tag *cmd =
4530 (struct i40e_aqc_update_tag *)&desc.params.raw;
4531 struct i40e_aqc_update_tag_completion *resp =
4532 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4533 enum i40e_status_code status;
4536 return I40E_ERR_PARAM;
4538 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4540 cmd->seid = CPU_TO_LE16(vsi_seid);
4541 cmd->old_tag = CPU_TO_LE16(old_tag);
4542 cmd->new_tag = CPU_TO_LE16(new_tag);
4544 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4547 if (tags_used != NULL)
4548 *tags_used = LE16_TO_CPU(resp->tags_used);
4549 if (tags_free != NULL)
4550 *tags_free = LE16_TO_CPU(resp->tags_free);
4557 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4558 * @hw: pointer to the hw struct
4559 * @tcmap: TC map for request/release any ignore PFC condition
4560 * @request: request or release ignore PFC condition
4561 * @tcmap_ret: return TCs for which PFC is currently ignored
4562 * @cmd_details: pointer to command details structure or NULL
4564 * This sends out request/release to ignore PFC condition for a TC.
4565 * It will return the TCs for which PFC is currently ignored.
4567 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4568 bool request, u8 *tcmap_ret,
4569 struct i40e_asq_cmd_details *cmd_details)
4571 struct i40e_aq_desc desc;
4572 struct i40e_aqc_pfc_ignore *cmd_resp =
4573 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4574 enum i40e_status_code status;
4576 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4579 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4581 cmd_resp->tc_bitmap = tcmap;
4583 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4586 if (tcmap_ret != NULL)
4587 *tcmap_ret = cmd_resp->tc_bitmap;
4594 * i40e_aq_dcb_updated - DCB Updated Command
4595 * @hw: pointer to the hw struct
4596 * @cmd_details: pointer to command details structure or NULL
4598 * When LLDP is handled in PF this command is used by the PF
4599 * to notify EMP that a DCB setting is modified.
4600 * When LLDP is handled in EMP this command is used by the PF
4601 * to notify EMP whenever one of the following parameters get
4603 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4604 * - PCIRTT in PRTDCB_GENC.PCIRTT
4605 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4606 * EMP will return when the shared RPB settings have been
4607 * recomputed and modified. The retval field in the descriptor
4608 * will be set to 0 when RPB is modified.
4610 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4611 struct i40e_asq_cmd_details *cmd_details)
4613 struct i40e_aq_desc desc;
4614 enum i40e_status_code status;
4616 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4618 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4624 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4625 * @hw: pointer to the hw struct
4626 * @seid: defines the SEID of the switch for which the stats are requested
4627 * @vlan_id: the VLAN ID for which the statistics are requested
4628 * @stat_index: index of the statistics counters block assigned to this VLAN
4629 * @cmd_details: pointer to command details structure or NULL
4631 * XL710 supports 128 smonVlanStats counters.This command is used to
4632 * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4635 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4636 u16 vlan_id, u16 *stat_index,
4637 struct i40e_asq_cmd_details *cmd_details)
4639 struct i40e_aq_desc desc;
4640 struct i40e_aqc_add_remove_statistics *cmd_resp =
4641 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4642 enum i40e_status_code status;
4644 if ((seid == 0) || (stat_index == NULL))
4645 return I40E_ERR_PARAM;
4647 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4649 cmd_resp->seid = CPU_TO_LE16(seid);
4650 cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4652 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4654 if (!status && stat_index)
4655 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4661 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4662 * @hw: pointer to the hw struct
4663 * @seid: defines the SEID of the switch for which the stats are requested
4664 * @vlan_id: the VLAN ID for which the statistics are requested
4665 * @stat_index: index of the statistics counters block assigned to this VLAN
4666 * @cmd_details: pointer to command details structure or NULL
4668 * XL710 supports 128 smonVlanStats counters.This command is used to
4669 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4672 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4673 u16 vlan_id, u16 stat_index,
4674 struct i40e_asq_cmd_details *cmd_details)
4676 struct i40e_aq_desc desc;
4677 struct i40e_aqc_add_remove_statistics *cmd =
4678 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4679 enum i40e_status_code status;
4682 return I40E_ERR_PARAM;
4684 i40e_fill_default_direct_cmd_desc(&desc,
4685 i40e_aqc_opc_remove_statistics);
4687 cmd->seid = CPU_TO_LE16(seid);
4688 cmd->vlan = CPU_TO_LE16(vlan_id);
4689 cmd->stat_index = CPU_TO_LE16(stat_index);
4691 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4697 * i40e_aq_set_port_parameters - set physical port parameters.
4698 * @hw: pointer to the hw struct
4699 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4700 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4701 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4702 * @double_vlan: if set double VLAN is enabled
4703 * @cmd_details: pointer to command details structure or NULL
4705 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4706 u16 bad_frame_vsi, bool save_bad_pac,
4707 bool pad_short_pac, bool double_vlan,
4708 struct i40e_asq_cmd_details *cmd_details)
4710 struct i40e_aqc_set_port_parameters *cmd;
4711 enum i40e_status_code status;
4712 struct i40e_aq_desc desc;
4713 u16 command_flags = 0;
4715 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4717 i40e_fill_default_direct_cmd_desc(&desc,
4718 i40e_aqc_opc_set_port_parameters);
4720 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4722 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4724 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4726 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4727 cmd->command_flags = CPU_TO_LE16(command_flags);
4729 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4735 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4736 * @hw: pointer to the hw struct
4737 * @seid: seid for the physical port/switching component/vsi
4738 * @buff: Indirect buffer to hold data parameters and response
4739 * @buff_size: Indirect buffer size
4740 * @opcode: Tx scheduler AQ command opcode
4741 * @cmd_details: pointer to command details structure or NULL
4743 * Generic command handler for Tx scheduler AQ commands
4745 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4746 void *buff, u16 buff_size,
4747 enum i40e_admin_queue_opc opcode,
4748 struct i40e_asq_cmd_details *cmd_details)
4750 struct i40e_aq_desc desc;
4751 struct i40e_aqc_tx_sched_ind *cmd =
4752 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4753 enum i40e_status_code status;
4754 bool cmd_param_flag = false;
4757 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4758 case i40e_aqc_opc_configure_vsi_tc_bw:
4759 case i40e_aqc_opc_enable_switching_comp_ets:
4760 case i40e_aqc_opc_modify_switching_comp_ets:
4761 case i40e_aqc_opc_disable_switching_comp_ets:
4762 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4763 case i40e_aqc_opc_configure_switching_comp_bw_config:
4764 cmd_param_flag = true;
4766 case i40e_aqc_opc_query_vsi_bw_config:
4767 case i40e_aqc_opc_query_vsi_ets_sla_config:
4768 case i40e_aqc_opc_query_switching_comp_ets_config:
4769 case i40e_aqc_opc_query_port_ets_config:
4770 case i40e_aqc_opc_query_switching_comp_bw_config:
4771 cmd_param_flag = false;
4774 return I40E_ERR_PARAM;
4777 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4779 /* Indirect command */
4780 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4782 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4783 if (buff_size > I40E_AQ_LARGE_BUF)
4784 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4786 desc.datalen = CPU_TO_LE16(buff_size);
4788 cmd->vsi_seid = CPU_TO_LE16(seid);
4790 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4796 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4797 * @hw: pointer to the hw struct
4799 * @credit: BW limit credits (0 = disabled)
4800 * @max_credit: Max BW limit credits
4801 * @cmd_details: pointer to command details structure or NULL
4803 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4804 u16 seid, u16 credit, u8 max_credit,
4805 struct i40e_asq_cmd_details *cmd_details)
4807 struct i40e_aq_desc desc;
4808 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4809 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4810 enum i40e_status_code status;
4812 i40e_fill_default_direct_cmd_desc(&desc,
4813 i40e_aqc_opc_configure_vsi_bw_limit);
4815 cmd->vsi_seid = CPU_TO_LE16(seid);
4816 cmd->credit = CPU_TO_LE16(credit);
4817 cmd->max_credit = max_credit;
4819 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4825 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4826 * @hw: pointer to the hw struct
4827 * @seid: switching component seid
4828 * @credit: BW limit credits (0 = disabled)
4829 * @max_bw: Max BW limit credits
4830 * @cmd_details: pointer to command details structure or NULL
4832 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4833 u16 seid, u16 credit, u8 max_bw,
4834 struct i40e_asq_cmd_details *cmd_details)
4836 struct i40e_aq_desc desc;
4837 struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4838 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4839 enum i40e_status_code status;
4841 i40e_fill_default_direct_cmd_desc(&desc,
4842 i40e_aqc_opc_configure_switching_comp_bw_limit);
4844 cmd->seid = CPU_TO_LE16(seid);
4845 cmd->credit = CPU_TO_LE16(credit);
4846 cmd->max_bw = max_bw;
4848 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4854 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4855 * @hw: pointer to the hw struct
4857 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4858 * @cmd_details: pointer to command details structure or NULL
4860 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
4862 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
4863 struct i40e_asq_cmd_details *cmd_details)
4865 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4866 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
4871 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4872 * @hw: pointer to the hw struct
4874 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4875 * @cmd_details: pointer to command details structure or NULL
4877 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4879 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4880 struct i40e_asq_cmd_details *cmd_details)
4882 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4883 i40e_aqc_opc_configure_vsi_tc_bw,
4888 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4889 * @hw: pointer to the hw struct
4890 * @seid: seid of the switching component connected to Physical Port
4891 * @ets_data: Buffer holding ETS parameters
4892 * @cmd_details: pointer to command details structure or NULL
4894 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4896 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4897 enum i40e_admin_queue_opc opcode,
4898 struct i40e_asq_cmd_details *cmd_details)
4900 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4901 sizeof(*ets_data), opcode, cmd_details);
4905 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4906 * @hw: pointer to the hw struct
4907 * @seid: seid of the switching component
4908 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4909 * @cmd_details: pointer to command details structure or NULL
4911 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4913 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4914 struct i40e_asq_cmd_details *cmd_details)
4916 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4917 i40e_aqc_opc_configure_switching_comp_bw_config,
4922 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
4923 * @hw: pointer to the hw struct
4924 * @seid: seid of the switching component
4925 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
4926 * @cmd_details: pointer to command details structure or NULL
4928 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
4929 struct i40e_hw *hw, u16 seid,
4930 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
4931 struct i40e_asq_cmd_details *cmd_details)
4933 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4934 i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
4939 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4940 * @hw: pointer to the hw struct
4941 * @seid: seid of the VSI
4942 * @bw_data: Buffer to hold VSI BW configuration
4943 * @cmd_details: pointer to command details structure or NULL
4945 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4947 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4948 struct i40e_asq_cmd_details *cmd_details)
4950 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4951 i40e_aqc_opc_query_vsi_bw_config,
4956 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4957 * @hw: pointer to the hw struct
4958 * @seid: seid of the VSI
4959 * @bw_data: Buffer to hold VSI BW configuration per TC
4960 * @cmd_details: pointer to command details structure or NULL
4962 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4964 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4965 struct i40e_asq_cmd_details *cmd_details)
4967 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4968 i40e_aqc_opc_query_vsi_ets_sla_config,
4973 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4974 * @hw: pointer to the hw struct
4975 * @seid: seid of the switching component
4976 * @bw_data: Buffer to hold switching component's per TC BW config
4977 * @cmd_details: pointer to command details structure or NULL
4979 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4981 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4982 struct i40e_asq_cmd_details *cmd_details)
4984 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4985 i40e_aqc_opc_query_switching_comp_ets_config,
4990 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4991 * @hw: pointer to the hw struct
4992 * @seid: seid of the VSI or switching component connected to Physical Port
4993 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4994 * @cmd_details: pointer to command details structure or NULL
4996 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4998 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4999 struct i40e_asq_cmd_details *cmd_details)
5001 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5002 i40e_aqc_opc_query_port_ets_config,
5007 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5008 * @hw: pointer to the hw struct
5009 * @seid: seid of the switching component
5010 * @bw_data: Buffer to hold switching component's BW configuration
5011 * @cmd_details: pointer to command details structure or NULL
5013 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5015 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5016 struct i40e_asq_cmd_details *cmd_details)
5018 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5019 i40e_aqc_opc_query_switching_comp_bw_config,
5024 * i40e_validate_filter_settings
5025 * @hw: pointer to the hardware structure
5026 * @settings: Filter control settings
5028 * Check and validate the filter control settings passed.
5029 * The function checks for the valid filter/context sizes being
5030 * passed for FCoE and PE.
5032 * Returns I40E_SUCCESS if the values passed are valid and within
5033 * range else returns an error.
5035 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5036 struct i40e_filter_control_settings *settings)
5038 u32 fcoe_cntx_size, fcoe_filt_size;
5039 u32 pe_cntx_size, pe_filt_size;
5044 /* Validate FCoE settings passed */
5045 switch (settings->fcoe_filt_num) {
5046 case I40E_HASH_FILTER_SIZE_1K:
5047 case I40E_HASH_FILTER_SIZE_2K:
5048 case I40E_HASH_FILTER_SIZE_4K:
5049 case I40E_HASH_FILTER_SIZE_8K:
5050 case I40E_HASH_FILTER_SIZE_16K:
5051 case I40E_HASH_FILTER_SIZE_32K:
5052 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5053 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5056 return I40E_ERR_PARAM;
5059 switch (settings->fcoe_cntx_num) {
5060 case I40E_DMA_CNTX_SIZE_512:
5061 case I40E_DMA_CNTX_SIZE_1K:
5062 case I40E_DMA_CNTX_SIZE_2K:
5063 case I40E_DMA_CNTX_SIZE_4K:
5064 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5065 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5068 return I40E_ERR_PARAM;
5071 /* Validate PE settings passed */
5072 switch (settings->pe_filt_num) {
5073 case I40E_HASH_FILTER_SIZE_1K:
5074 case I40E_HASH_FILTER_SIZE_2K:
5075 case I40E_HASH_FILTER_SIZE_4K:
5076 case I40E_HASH_FILTER_SIZE_8K:
5077 case I40E_HASH_FILTER_SIZE_16K:
5078 case I40E_HASH_FILTER_SIZE_32K:
5079 case I40E_HASH_FILTER_SIZE_64K:
5080 case I40E_HASH_FILTER_SIZE_128K:
5081 case I40E_HASH_FILTER_SIZE_256K:
5082 case I40E_HASH_FILTER_SIZE_512K:
5083 case I40E_HASH_FILTER_SIZE_1M:
5084 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5085 pe_filt_size <<= (u32)settings->pe_filt_num;
5088 return I40E_ERR_PARAM;
5091 switch (settings->pe_cntx_num) {
5092 case I40E_DMA_CNTX_SIZE_512:
5093 case I40E_DMA_CNTX_SIZE_1K:
5094 case I40E_DMA_CNTX_SIZE_2K:
5095 case I40E_DMA_CNTX_SIZE_4K:
5096 case I40E_DMA_CNTX_SIZE_8K:
5097 case I40E_DMA_CNTX_SIZE_16K:
5098 case I40E_DMA_CNTX_SIZE_32K:
5099 case I40E_DMA_CNTX_SIZE_64K:
5100 case I40E_DMA_CNTX_SIZE_128K:
5101 case I40E_DMA_CNTX_SIZE_256K:
5102 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5103 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5106 return I40E_ERR_PARAM;
5109 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5110 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5111 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5112 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5113 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
5114 return I40E_ERR_INVALID_SIZE;
5116 return I40E_SUCCESS;
5120 * i40e_set_filter_control
5121 * @hw: pointer to the hardware structure
5122 * @settings: Filter control settings
5124 * Set the Queue Filters for PE/FCoE and enable filters required
5125 * for a single PF. It is expected that these settings are programmed
5126 * at the driver initialization time.
5128 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5129 struct i40e_filter_control_settings *settings)
5131 enum i40e_status_code ret = I40E_SUCCESS;
5132 u32 hash_lut_size = 0;
5136 return I40E_ERR_PARAM;
5138 /* Validate the input settings */
5139 ret = i40e_validate_filter_settings(hw, settings);
5143 /* Read the PF Queue Filter control register */
5144 val = rd32(hw, I40E_PFQF_CTL_0);
5146 /* Program required PE hash buckets for the PF */
5147 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5148 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5149 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5150 /* Program required PE contexts for the PF */
5151 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5152 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5153 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5155 /* Program required FCoE hash buckets for the PF */
5156 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5157 val |= ((u32)settings->fcoe_filt_num <<
5158 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5159 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5160 /* Program required FCoE DDP contexts for the PF */
5161 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5162 val |= ((u32)settings->fcoe_cntx_num <<
5163 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5164 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5166 /* Program Hash LUT size for the PF */
5167 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5168 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5170 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5171 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5173 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5174 if (settings->enable_fdir)
5175 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5176 if (settings->enable_ethtype)
5177 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5178 if (settings->enable_macvlan)
5179 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5181 wr32(hw, I40E_PFQF_CTL_0, val);
5183 return I40E_SUCCESS;
5187 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5188 * @hw: pointer to the hw struct
5189 * @mac_addr: MAC address to use in the filter
5190 * @ethtype: Ethertype to use in the filter
5191 * @flags: Flags that needs to be applied to the filter
5192 * @vsi_seid: seid of the control VSI
5193 * @queue: VSI queue number to send the packet to
5194 * @is_add: Add control packet filter if True else remove
5195 * @stats: Structure to hold information on control filter counts
5196 * @cmd_details: pointer to command details structure or NULL
5198 * This command will Add or Remove control packet filter for a control VSI.
5199 * In return it will update the total number of perfect filter count in
5202 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5203 u8 *mac_addr, u16 ethtype, u16 flags,
5204 u16 vsi_seid, u16 queue, bool is_add,
5205 struct i40e_control_filter_stats *stats,
5206 struct i40e_asq_cmd_details *cmd_details)
5208 struct i40e_aq_desc desc;
5209 struct i40e_aqc_add_remove_control_packet_filter *cmd =
5210 (struct i40e_aqc_add_remove_control_packet_filter *)
5212 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5213 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5215 enum i40e_status_code status;
5218 return I40E_ERR_PARAM;
5221 i40e_fill_default_direct_cmd_desc(&desc,
5222 i40e_aqc_opc_add_control_packet_filter);
5223 cmd->queue = CPU_TO_LE16(queue);
5225 i40e_fill_default_direct_cmd_desc(&desc,
5226 i40e_aqc_opc_remove_control_packet_filter);
5230 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5231 I40E_NONDMA_TO_NONDMA);
5233 cmd->etype = CPU_TO_LE16(ethtype);
5234 cmd->flags = CPU_TO_LE16(flags);
5235 cmd->seid = CPU_TO_LE16(vsi_seid);
5237 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5239 if (!status && stats) {
5240 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5241 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5242 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5243 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5250 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5251 * @hw: pointer to the hw struct
5252 * @seid: VSI seid to add ethertype filter from
5254 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5255 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5258 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5259 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5260 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5261 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5262 enum i40e_status_code status;
5264 status = i40e_aq_add_rem_control_packet_filter(hw, 0, ethtype, flag,
5265 seid, 0, true, NULL,
5268 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5272 * i40e_aq_add_cloud_filters
5273 * @hw: pointer to the hardware structure
5274 * @seid: VSI seid to add cloud filters from
5275 * @filters: Buffer which contains the filters to be added
5276 * @filter_count: number of filters contained in the buffer
5278 * Set the cloud filters for a given VSI. The contents of the
5279 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5280 * in by the caller of the function.
5283 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5285 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5288 struct i40e_aq_desc desc;
5289 struct i40e_aqc_add_remove_cloud_filters *cmd =
5290 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5292 enum i40e_status_code status;
5294 i40e_fill_default_direct_cmd_desc(&desc,
5295 i40e_aqc_opc_add_cloud_filters);
5297 buff_len = filter_count * sizeof(*filters);
5298 desc.datalen = CPU_TO_LE16(buff_len);
5299 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5300 cmd->num_filters = filter_count;
5301 cmd->seid = CPU_TO_LE16(seid);
5303 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5309 * i40e_aq_remove_cloud_filters
5310 * @hw: pointer to the hardware structure
5311 * @seid: VSI seid to remove cloud filters from
5312 * @filters: Buffer which contains the filters to be removed
5313 * @filter_count: number of filters contained in the buffer
5315 * Remove the cloud filters for a given VSI. The contents of the
5316 * i40e_aqc_add_remove_cloud_filters_element_data are filled
5317 * in by the caller of the function.
5320 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5322 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5325 struct i40e_aq_desc desc;
5326 struct i40e_aqc_add_remove_cloud_filters *cmd =
5327 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5328 enum i40e_status_code status;
5331 i40e_fill_default_direct_cmd_desc(&desc,
5332 i40e_aqc_opc_remove_cloud_filters);
5334 buff_len = filter_count * sizeof(*filters);
5335 desc.datalen = CPU_TO_LE16(buff_len);
5336 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5337 cmd->num_filters = filter_count;
5338 cmd->seid = CPU_TO_LE16(seid);
5340 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5346 * i40e_aq_alternate_write
5347 * @hw: pointer to the hardware structure
5348 * @reg_addr0: address of first dword to be read
5349 * @reg_val0: value to be written under 'reg_addr0'
5350 * @reg_addr1: address of second dword to be read
5351 * @reg_val1: value to be written under 'reg_addr1'
5353 * Write one or two dwords to alternate structure. Fields are indicated
5354 * by 'reg_addr0' and 'reg_addr1' register numbers.
5357 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5358 u32 reg_addr0, u32 reg_val0,
5359 u32 reg_addr1, u32 reg_val1)
5361 struct i40e_aq_desc desc;
5362 struct i40e_aqc_alternate_write *cmd_resp =
5363 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5364 enum i40e_status_code status;
5366 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5367 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5368 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5369 cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5370 cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5372 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5378 * i40e_aq_alternate_write_indirect
5379 * @hw: pointer to the hardware structure
5380 * @addr: address of a first register to be modified
5381 * @dw_count: number of alternate structure fields to write
5382 * @buffer: pointer to the command buffer
5384 * Write 'dw_count' dwords from 'buffer' to alternate structure
5385 * starting at 'addr'.
5388 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5389 u32 addr, u32 dw_count, void *buffer)
5391 struct i40e_aq_desc desc;
5392 struct i40e_aqc_alternate_ind_write *cmd_resp =
5393 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5394 enum i40e_status_code status;
5397 return I40E_ERR_PARAM;
5399 /* Indirect command */
5400 i40e_fill_default_direct_cmd_desc(&desc,
5401 i40e_aqc_opc_alternate_write_indirect);
5403 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5404 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5405 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5406 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5408 cmd_resp->address = CPU_TO_LE32(addr);
5409 cmd_resp->length = CPU_TO_LE32(dw_count);
5411 status = i40e_asq_send_command(hw, &desc, buffer,
5412 I40E_LO_DWORD(4*dw_count), NULL);
5418 * i40e_aq_alternate_read
5419 * @hw: pointer to the hardware structure
5420 * @reg_addr0: address of first dword to be read
5421 * @reg_val0: pointer for data read from 'reg_addr0'
5422 * @reg_addr1: address of second dword to be read
5423 * @reg_val1: pointer for data read from 'reg_addr1'
5425 * Read one or two dwords from alternate structure. Fields are indicated
5426 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5427 * is not passed then only register at 'reg_addr0' is read.
5430 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5431 u32 reg_addr0, u32 *reg_val0,
5432 u32 reg_addr1, u32 *reg_val1)
5434 struct i40e_aq_desc desc;
5435 struct i40e_aqc_alternate_write *cmd_resp =
5436 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5437 enum i40e_status_code status;
5439 if (reg_val0 == NULL)
5440 return I40E_ERR_PARAM;
5442 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5443 cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5444 cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5446 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5448 if (status == I40E_SUCCESS) {
5449 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5451 if (reg_val1 != NULL)
5452 *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5459 * i40e_aq_alternate_read_indirect
5460 * @hw: pointer to the hardware structure
5461 * @addr: address of the alternate structure field
5462 * @dw_count: number of alternate structure fields to read
5463 * @buffer: pointer to the command buffer
5465 * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5466 * place them in 'buffer'. The buffer should be allocated by caller.
5469 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5470 u32 addr, u32 dw_count, void *buffer)
5472 struct i40e_aq_desc desc;
5473 struct i40e_aqc_alternate_ind_write *cmd_resp =
5474 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5475 enum i40e_status_code status;
5478 return I40E_ERR_PARAM;
5480 /* Indirect command */
5481 i40e_fill_default_direct_cmd_desc(&desc,
5482 i40e_aqc_opc_alternate_read_indirect);
5484 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5485 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5486 if (dw_count > (I40E_AQ_LARGE_BUF/4))
5487 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5489 cmd_resp->address = CPU_TO_LE32(addr);
5490 cmd_resp->length = CPU_TO_LE32(dw_count);
5492 status = i40e_asq_send_command(hw, &desc, buffer,
5493 I40E_LO_DWORD(4*dw_count), NULL);
5499 * i40e_aq_alternate_clear
5500 * @hw: pointer to the HW structure.
5502 * Clear the alternate structures of the port from which the function
5506 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5508 struct i40e_aq_desc desc;
5509 enum i40e_status_code status;
5511 i40e_fill_default_direct_cmd_desc(&desc,
5512 i40e_aqc_opc_alternate_clear_port);
5514 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5520 * i40e_aq_alternate_write_done
5521 * @hw: pointer to the HW structure.
5522 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5523 * @reset_needed: indicates the SW should trigger GLOBAL reset
5525 * Indicates to the FW that alternate structures have been changed.
5528 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5529 u8 bios_mode, bool *reset_needed)
5531 struct i40e_aq_desc desc;
5532 struct i40e_aqc_alternate_write_done *cmd =
5533 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5534 enum i40e_status_code status;
5536 if (reset_needed == NULL)
5537 return I40E_ERR_PARAM;
5539 i40e_fill_default_direct_cmd_desc(&desc,
5540 i40e_aqc_opc_alternate_write_done);
5542 cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5544 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5545 if (!status && reset_needed)
5546 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5547 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5553 * i40e_aq_set_oem_mode
5554 * @hw: pointer to the HW structure.
5555 * @oem_mode: the OEM mode to be used
5557 * Sets the device to a specific operating mode. Currently the only supported
5558 * mode is no_clp, which causes FW to refrain from using Alternate RAM.
5561 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5564 struct i40e_aq_desc desc;
5565 struct i40e_aqc_alternate_write_done *cmd =
5566 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5567 enum i40e_status_code status;
5569 i40e_fill_default_direct_cmd_desc(&desc,
5570 i40e_aqc_opc_alternate_set_mode);
5572 cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5574 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5580 * i40e_aq_resume_port_tx
5581 * @hw: pointer to the hardware structure
5582 * @cmd_details: pointer to command details structure or NULL
5584 * Resume port's Tx traffic
5586 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5587 struct i40e_asq_cmd_details *cmd_details)
5589 struct i40e_aq_desc desc;
5590 enum i40e_status_code status;
5592 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5594 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5600 * i40e_set_pci_config_data - store PCI bus info
5601 * @hw: pointer to hardware structure
5602 * @link_status: the link status word from PCI config space
5604 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5606 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5608 hw->bus.type = i40e_bus_type_pci_express;
5610 switch (link_status & I40E_PCI_LINK_WIDTH) {
5611 case I40E_PCI_LINK_WIDTH_1:
5612 hw->bus.width = i40e_bus_width_pcie_x1;
5614 case I40E_PCI_LINK_WIDTH_2:
5615 hw->bus.width = i40e_bus_width_pcie_x2;
5617 case I40E_PCI_LINK_WIDTH_4:
5618 hw->bus.width = i40e_bus_width_pcie_x4;
5620 case I40E_PCI_LINK_WIDTH_8:
5621 hw->bus.width = i40e_bus_width_pcie_x8;
5624 hw->bus.width = i40e_bus_width_unknown;
5628 switch (link_status & I40E_PCI_LINK_SPEED) {
5629 case I40E_PCI_LINK_SPEED_2500:
5630 hw->bus.speed = i40e_bus_speed_2500;
5632 case I40E_PCI_LINK_SPEED_5000:
5633 hw->bus.speed = i40e_bus_speed_5000;
5635 case I40E_PCI_LINK_SPEED_8000:
5636 hw->bus.speed = i40e_bus_speed_8000;
5639 hw->bus.speed = i40e_bus_speed_unknown;
5645 * i40e_aq_debug_dump
5646 * @hw: pointer to the hardware structure
5647 * @cluster_id: specific cluster to dump
5648 * @table_id: table id within cluster
5649 * @start_index: index of line in the block to read
5650 * @buff_size: dump buffer size
5651 * @buff: dump buffer
5652 * @ret_buff_size: actual buffer size returned
5653 * @ret_next_table: next block to read
5654 * @ret_next_index: next index to read
5656 * Dump internal FW/HW data for debug purposes.
5659 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5660 u8 table_id, u32 start_index, u16 buff_size,
5661 void *buff, u16 *ret_buff_size,
5662 u8 *ret_next_table, u32 *ret_next_index,
5663 struct i40e_asq_cmd_details *cmd_details)
5665 struct i40e_aq_desc desc;
5666 struct i40e_aqc_debug_dump_internals *cmd =
5667 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5668 struct i40e_aqc_debug_dump_internals *resp =
5669 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5670 enum i40e_status_code status;
5672 if (buff_size == 0 || !buff)
5673 return I40E_ERR_PARAM;
5675 i40e_fill_default_direct_cmd_desc(&desc,
5676 i40e_aqc_opc_debug_dump_internals);
5677 /* Indirect Command */
5678 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5679 if (buff_size > I40E_AQ_LARGE_BUF)
5680 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5682 cmd->cluster_id = cluster_id;
5683 cmd->table_id = table_id;
5684 cmd->idx = CPU_TO_LE32(start_index);
5686 desc.datalen = CPU_TO_LE16(buff_size);
5688 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5690 if (ret_buff_size != NULL)
5691 *ret_buff_size = LE16_TO_CPU(desc.datalen);
5692 if (ret_next_table != NULL)
5693 *ret_next_table = resp->table_id;
5694 if (ret_next_index != NULL)
5695 *ret_next_index = LE32_TO_CPU(resp->idx);
5702 * i40e_read_bw_from_alt_ram
5703 * @hw: pointer to the hardware structure
5704 * @max_bw: pointer for max_bw read
5705 * @min_bw: pointer for min_bw read
5706 * @min_valid: pointer for bool that is true if min_bw is a valid value
5707 * @max_valid: pointer for bool that is true if max_bw is a valid value
5709 * Read bw from the alternate ram for the given pf
5711 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5712 u32 *max_bw, u32 *min_bw,
5713 bool *min_valid, bool *max_valid)
5715 enum i40e_status_code status;
5716 u32 max_bw_addr, min_bw_addr;
5718 /* Calculate the address of the min/max bw registers */
5719 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5720 I40E_ALT_STRUCT_MAX_BW_OFFSET +
5721 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5722 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5723 I40E_ALT_STRUCT_MIN_BW_OFFSET +
5724 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5726 /* Read the bandwidths from alt ram */
5727 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5728 min_bw_addr, min_bw);
5730 if (*min_bw & I40E_ALT_BW_VALID_MASK)
5735 if (*max_bw & I40E_ALT_BW_VALID_MASK)
5744 * i40e_aq_configure_partition_bw
5745 * @hw: pointer to the hardware structure
5746 * @bw_data: Buffer holding valid pfs and bw limits
5747 * @cmd_details: pointer to command details
5749 * Configure partitions guaranteed/max bw
5751 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5752 struct i40e_aqc_configure_partition_bw_data *bw_data,
5753 struct i40e_asq_cmd_details *cmd_details)
5755 enum i40e_status_code status;
5756 struct i40e_aq_desc desc;
5757 u16 bwd_size = sizeof(*bw_data);
5759 i40e_fill_default_direct_cmd_desc(&desc,
5760 i40e_aqc_opc_configure_partition_bw);
5762 /* Indirect command */
5763 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5764 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5766 if (bwd_size > I40E_AQ_LARGE_BUF)
5767 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5769 desc.datalen = CPU_TO_LE16(bwd_size);
5771 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5775 #endif /* PF_DRIVER */
5779 * i40e_aq_send_msg_to_pf
5780 * @hw: pointer to the hardware structure
5781 * @v_opcode: opcodes for VF-PF communication
5782 * @v_retval: return error code
5783 * @msg: pointer to the msg buffer
5784 * @msglen: msg length
5785 * @cmd_details: pointer to command details
5787 * Send message to PF driver using admin queue. By default, this message
5788 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
5789 * completion before returning.
5791 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
5792 enum i40e_virtchnl_ops v_opcode,
5793 enum i40e_status_code v_retval,
5794 u8 *msg, u16 msglen,
5795 struct i40e_asq_cmd_details *cmd_details)
5797 struct i40e_aq_desc desc;
5798 struct i40e_asq_cmd_details details;
5799 enum i40e_status_code status;
5801 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
5802 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
5803 desc.cookie_high = CPU_TO_LE32(v_opcode);
5804 desc.cookie_low = CPU_TO_LE32(v_retval);
5806 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
5807 | I40E_AQ_FLAG_RD));
5808 if (msglen > I40E_AQ_LARGE_BUF)
5809 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5810 desc.datalen = CPU_TO_LE16(msglen);
5813 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
5814 details.async = true;
5815 cmd_details = &details;
5817 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
5818 msglen, cmd_details);
5823 * i40e_vf_parse_hw_config
5824 * @hw: pointer to the hardware structure
5825 * @msg: pointer to the virtual channel VF resource structure
5827 * Given a VF resource message from the PF, populate the hw struct
5828 * with appropriate information.
5830 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
5831 struct i40e_virtchnl_vf_resource *msg)
5833 struct i40e_virtchnl_vsi_resource *vsi_res;
5836 vsi_res = &msg->vsi_res[0];
5838 hw->dev_caps.num_vsis = msg->num_vsis;
5839 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
5840 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
5841 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
5842 hw->dev_caps.dcb = msg->vf_offload_flags &
5843 I40E_VIRTCHNL_VF_OFFLOAD_L2;
5844 hw->dev_caps.fcoe = (msg->vf_offload_flags &
5845 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
5846 hw->dev_caps.iwarp = (msg->vf_offload_flags &
5847 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
5848 for (i = 0; i < msg->num_vsis; i++) {
5849 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
5850 i40e_memcpy(hw->mac.perm_addr,
5851 vsi_res->default_mac_addr,
5852 I40E_ETH_LENGTH_OF_ADDRESS,
5853 I40E_NONDMA_TO_NONDMA);
5854 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
5855 I40E_ETH_LENGTH_OF_ADDRESS,
5856 I40E_NONDMA_TO_NONDMA);
5864 * @hw: pointer to the hardware structure
5866 * Send a VF_RESET message to the PF. Does not wait for response from PF
5867 * as none will be forthcoming. Immediately after calling this function,
5868 * the admin queue should be shut down and (optionally) reinitialized.
5870 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
5872 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
5873 I40E_SUCCESS, NULL, 0, NULL);
5875 #endif /* VF_DRIVER */
5879 * i40e_aq_set_arp_proxy_config
5880 * @hw: pointer to the HW structure
5881 * @proxy_config - pointer to proxy config command table struct
5882 * @cmd_details: pointer to command details
5884 * Set ARP offload parameters from pre-populated
5885 * i40e_aqc_arp_proxy_data struct
5887 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
5888 struct i40e_aqc_arp_proxy_data *proxy_config,
5889 struct i40e_asq_cmd_details *cmd_details)
5891 struct i40e_aq_desc desc;
5892 enum i40e_status_code status;
5895 return I40E_ERR_PARAM;
5897 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
5899 desc.params.external.addr_high =
5900 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
5901 desc.params.external.addr_low =
5902 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
5904 status = i40e_asq_send_command(hw, &desc, proxy_config,
5905 sizeof(struct i40e_aqc_arp_proxy_data),
5912 * i40e_aq_opc_set_ns_proxy_table_entry
5913 * @hw: pointer to the HW structure
5914 * @ns_proxy_table_entry: pointer to NS table entry command struct
5915 * @cmd_details: pointer to command details
5917 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
5918 * from pre-populated i40e_aqc_ns_proxy_data struct
5920 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
5921 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
5922 struct i40e_asq_cmd_details *cmd_details)
5924 struct i40e_aq_desc desc;
5925 enum i40e_status_code status;
5927 if (!ns_proxy_table_entry)
5928 return I40E_ERR_PARAM;
5930 i40e_fill_default_direct_cmd_desc(&desc,
5931 i40e_aqc_opc_set_ns_proxy_table_entry);
5933 desc.params.external.addr_high =
5934 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
5935 desc.params.external.addr_low =
5936 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
5938 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
5939 sizeof(struct i40e_aqc_ns_proxy_data),
5946 * i40e_aq_set_clear_wol_filter
5947 * @hw: pointer to the hw struct
5948 * @filter_index: index of filter to modify (0-7)
5949 * @filter: buffer containing filter to be set
5950 * @set_filter: true to set filter, false to clear filter
5951 * @no_wol_tco: if true, pass through packets cannot cause wake-up
5952 * if false, pass through packets may cause wake-up
5953 * @filter_valid: true if filter action is valid
5954 * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
5955 * @cmd_details: pointer to command details structure or NULL
5957 * Set or clear WoL filter for port attached to the PF
5959 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
5961 struct i40e_aqc_set_wol_filter_data *filter,
5962 bool set_filter, bool no_wol_tco,
5963 bool filter_valid, bool no_wol_tco_valid,
5964 struct i40e_asq_cmd_details *cmd_details)
5966 struct i40e_aq_desc desc;
5967 struct i40e_aqc_set_wol_filter *cmd =
5968 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
5969 enum i40e_status_code status;
5971 u16 valid_flags = 0;
5974 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
5976 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
5977 return I40E_ERR_PARAM;
5978 cmd->filter_index = CPU_TO_LE16(filter_index);
5982 return I40E_ERR_PARAM;
5983 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
5984 buff_len = sizeof(*filter);
5987 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
5988 cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
5991 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
5992 if (no_wol_tco_valid)
5993 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
5994 cmd->valid_flags = CPU_TO_LE16(valid_flags);
5996 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
5997 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
5999 status = i40e_asq_send_command(hw, &desc, filter,
6000 buff_len, cmd_details);
6006 * i40e_aq_get_wake_event_reason
6007 * @hw: pointer to the hw struct
6008 * @wake_reason: return value, index of matching filter
6009 * @cmd_details: pointer to command details structure or NULL
6011 * Get information for the reason of a Wake Up event
6013 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6015 struct i40e_asq_cmd_details *cmd_details)
6017 struct i40e_aq_desc desc;
6018 struct i40e_aqc_get_wake_reason_completion *resp =
6019 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6020 enum i40e_status_code status;
6022 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6024 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6026 if (status == I40E_SUCCESS)
6027 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6032 #endif /* X722_SUPPORT */