1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "i40e_status.h"
38 #include "i40e_osdep.h"
39 #include "i40e_register.h"
40 #include "i40e_adminq.h"
42 #include "i40e_lan_hmc.h"
43 #include "i40e_devids.h"
45 #define UNREFERENCED_XPARAMETER
46 #define UNREFERENCED_1PARAMETER(_p) (_p);
47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
54 #define BIT(a) (1UL << (a))
57 #define BIT_ULL(a) (1ULL << (a))
59 #endif /* LINUX_MACROS */
62 /* I40E_MASK is a macro used on 32 bit registers */
63 #define I40E_MASK(mask, shift) (mask << shift)
66 #define I40E_MAX_PF 16
67 #define I40E_MAX_PF_VSI 64
68 #define I40E_MAX_PF_QP 128
69 #define I40E_MAX_VSI_QP 16
70 #define I40E_MAX_VF_VSI 3
71 #define I40E_MAX_CHAINED_RX_BUFFERS 5
72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
74 /* something less than 1 minute */
75 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
77 /* Max default timeout in ms, */
78 #define I40E_MAX_NVM_TIMEOUT 18000
80 /* Check whether address is multicast. */
81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
83 /* Check whether an address is broadcast. */
84 #define I40E_IS_BROADCAST(address) \
85 ((((u8 *)(address))[0] == ((u8)0xff)) && \
86 (((u8 *)(address))[1] == ((u8)0xff)))
88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
89 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
91 /* forward declaration */
93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
95 #define I40E_ETH_LENGTH_OF_ADDRESS 6
96 /* Data type manipulation macros. */
97 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
98 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
100 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
101 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
103 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
104 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
106 /* Number of Transmit Descriptors must be a multiple of 8. */
107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
108 /* Number of Receive Descriptors must be a multiple of 32 if
109 * the number of descriptors is greater than 32.
111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
113 #define I40E_DESC_UNUSED(R) \
114 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
115 (R)->next_to_clean - (R)->next_to_use - 1)
117 /* bitfields for Tx queue mapping in QTX_CTL */
118 #define I40E_QTX_CTL_VF_QUEUE 0x0
119 #define I40E_QTX_CTL_VM_QUEUE 0x1
120 #define I40E_QTX_CTL_PF_QUEUE 0x2
122 /* debug masks - set these bits in hw->debug_mask to control output */
123 enum i40e_debug_mask {
124 I40E_DEBUG_INIT = 0x00000001,
125 I40E_DEBUG_RELEASE = 0x00000002,
127 I40E_DEBUG_LINK = 0x00000010,
128 I40E_DEBUG_PHY = 0x00000020,
129 I40E_DEBUG_HMC = 0x00000040,
130 I40E_DEBUG_NVM = 0x00000080,
131 I40E_DEBUG_LAN = 0x00000100,
132 I40E_DEBUG_FLOW = 0x00000200,
133 I40E_DEBUG_DCB = 0x00000400,
134 I40E_DEBUG_DIAG = 0x00000800,
135 I40E_DEBUG_FD = 0x00001000,
137 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
138 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
139 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
140 I40E_DEBUG_AQ_COMMAND = 0x06000000,
141 I40E_DEBUG_AQ = 0x0F000000,
143 I40E_DEBUG_USER = 0xF0000000,
145 I40E_DEBUG_ALL = 0xFFFFFFFF
149 #define I40E_PCI_LINK_STATUS 0xB2
150 #define I40E_PCI_LINK_WIDTH 0x3F0
151 #define I40E_PCI_LINK_WIDTH_1 0x10
152 #define I40E_PCI_LINK_WIDTH_2 0x20
153 #define I40E_PCI_LINK_WIDTH_4 0x40
154 #define I40E_PCI_LINK_WIDTH_8 0x80
155 #define I40E_PCI_LINK_SPEED 0xF
156 #define I40E_PCI_LINK_SPEED_2500 0x1
157 #define I40E_PCI_LINK_SPEED_5000 0x2
158 #define I40E_PCI_LINK_SPEED_8000 0x3
161 enum i40e_memset_type {
167 enum i40e_memcpy_type {
168 I40E_NONDMA_TO_NONDMA = 0,
176 #define I40E_FW_API_VERSION_MINOR_X722 0x0003
178 #define I40E_FW_API_VERSION_MINOR_X710 0x0004
181 /* These are structs for managing the hardware information and the operations.
182 * The structures of function pointers are filled out at init time when we
183 * know for sure exactly which hardware we're working with. This gives us the
184 * flexibility of using the same main driver code but adapting to slightly
185 * different hardware needs as new parts are developed. For this architecture,
186 * the Firmware and AdminQ are intended to insulate the driver from most of the
187 * future changes, but these structures will also do part of the job.
190 I40E_MAC_UNKNOWN = 0,
197 enum i40e_media_type {
198 I40E_MEDIA_TYPE_UNKNOWN = 0,
199 I40E_MEDIA_TYPE_FIBER,
200 I40E_MEDIA_TYPE_BASET,
201 I40E_MEDIA_TYPE_BACKPLANE,
204 I40E_MEDIA_TYPE_VIRTUAL
216 enum i40e_set_fc_aq_failures {
217 I40E_SET_FC_AQ_FAIL_NONE = 0,
218 I40E_SET_FC_AQ_FAIL_GET = 1,
219 I40E_SET_FC_AQ_FAIL_SET = 2,
220 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
221 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
233 I40E_VSI_TYPE_UNKNOWN
236 enum i40e_queue_type {
237 I40E_QUEUE_TYPE_RX = 0,
239 I40E_QUEUE_TYPE_PE_CEQ,
240 I40E_QUEUE_TYPE_UNKNOWN
243 struct i40e_link_status {
244 enum i40e_aq_phy_type phy_type;
245 enum i40e_aq_link_speed link_speed;
250 /* is Link Status Event notification to SW enabled */
257 /* 1st byte: module identifier */
258 #define I40E_MODULE_TYPE_SFP 0x03
259 #define I40E_MODULE_TYPE_QSFP 0x0D
260 /* 2nd byte: ethernet compliance codes for 10/40G */
261 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
262 #define I40E_MODULE_TYPE_40G_LR4 0x02
263 #define I40E_MODULE_TYPE_40G_SR4 0x04
264 #define I40E_MODULE_TYPE_40G_CR4 0x08
265 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
266 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
267 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
268 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
269 /* 3rd byte: ethernet compliance codes for 1G */
270 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
271 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
272 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
273 #define I40E_MODULE_TYPE_1000BASE_T 0x08
276 struct i40e_phy_info {
277 struct i40e_link_status link_info;
278 struct i40e_link_status link_info_old;
279 u32 autoneg_advertised;
283 enum i40e_media_type media_type;
286 #define I40E_HW_CAP_MAX_GPIO 30
287 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
288 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
290 /* Capabilities of a PF or a VF or the whole device */
291 struct i40e_hw_capabilities {
293 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
294 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
295 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
303 bool evb_802_1_qbg; /* Edge Virtual Bridging */
304 bool evb_802_1_qbh; /* Bridge Port Extension */
307 bool iscsi; /* Indicates iSCSI enabled */
313 u32 fd_filters_guaranteed;
314 u32 fd_filters_best_effort;
317 u32 rss_table_entry_width;
318 bool led[I40E_HW_CAP_MAX_GPIO];
319 bool sdp[I40E_HW_CAP_MAX_GPIO];
321 u32 num_flow_director_filters;
328 u32 num_msix_vectors;
329 u32 num_msix_vectors_vf;
339 struct i40e_mac_info {
340 enum i40e_mac_type type;
341 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
342 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
343 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
344 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
348 enum i40e_aq_resources_ids {
349 I40E_NVM_RESOURCE_ID = 1
352 enum i40e_aq_resource_access_type {
353 I40E_RESOURCE_READ = 1,
357 struct i40e_nvm_info {
358 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
359 u32 timeout; /* [ms] */
360 u16 sr_size; /* Shadow RAM size in words */
361 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
362 u16 version; /* NVM package version */
363 u32 eetrack; /* NVM data version */
364 u32 oem_ver; /* OEM version info */
367 /* definitions used in NVM update support */
369 enum i40e_nvmupd_cmd {
371 I40E_NVMUPD_READ_CON,
372 I40E_NVMUPD_READ_SNT,
373 I40E_NVMUPD_READ_LCB,
375 I40E_NVMUPD_WRITE_ERA,
376 I40E_NVMUPD_WRITE_CON,
377 I40E_NVMUPD_WRITE_SNT,
378 I40E_NVMUPD_WRITE_LCB,
379 I40E_NVMUPD_WRITE_SA,
380 I40E_NVMUPD_CSUM_CON,
382 I40E_NVMUPD_CSUM_LCB,
385 I40E_NVMUPD_GET_AQ_RESULT,
388 enum i40e_nvmupd_state {
389 I40E_NVMUPD_STATE_INIT,
390 I40E_NVMUPD_STATE_READING,
391 I40E_NVMUPD_STATE_WRITING,
392 I40E_NVMUPD_STATE_INIT_WAIT,
393 I40E_NVMUPD_STATE_WRITE_WAIT,
396 /* nvm_access definition and its masks/shifts need to be accessible to
397 * application, core driver, and shared code. Where is the right file?
399 #define I40E_NVM_READ 0xB
400 #define I40E_NVM_WRITE 0xC
402 #define I40E_NVM_MOD_PNT_MASK 0xFF
404 #define I40E_NVM_TRANS_SHIFT 8
405 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
406 #define I40E_NVM_CON 0x0
407 #define I40E_NVM_SNT 0x1
408 #define I40E_NVM_LCB 0x2
409 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
410 #define I40E_NVM_ERA 0x4
411 #define I40E_NVM_CSUM 0x8
412 #define I40E_NVM_EXEC 0xf
414 #define I40E_NVM_ADAPT_SHIFT 16
415 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
417 #define I40E_NVMUPD_MAX_DATA 4096
418 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
420 struct i40e_nvm_access {
423 u32 offset; /* in bytes */
424 u32 data_size; /* in bytes */
430 i40e_bus_type_unknown = 0,
433 i40e_bus_type_pci_express,
434 i40e_bus_type_reserved
438 enum i40e_bus_speed {
439 i40e_bus_speed_unknown = 0,
440 i40e_bus_speed_33 = 33,
441 i40e_bus_speed_66 = 66,
442 i40e_bus_speed_100 = 100,
443 i40e_bus_speed_120 = 120,
444 i40e_bus_speed_133 = 133,
445 i40e_bus_speed_2500 = 2500,
446 i40e_bus_speed_5000 = 5000,
447 i40e_bus_speed_8000 = 8000,
448 i40e_bus_speed_reserved
452 enum i40e_bus_width {
453 i40e_bus_width_unknown = 0,
454 i40e_bus_width_pcie_x1 = 1,
455 i40e_bus_width_pcie_x2 = 2,
456 i40e_bus_width_pcie_x4 = 4,
457 i40e_bus_width_pcie_x8 = 8,
458 i40e_bus_width_32 = 32,
459 i40e_bus_width_64 = 64,
460 i40e_bus_width_reserved
464 struct i40e_bus_info {
465 enum i40e_bus_speed speed;
466 enum i40e_bus_width width;
467 enum i40e_bus_type type;
474 /* Flow control (FC) parameters */
475 struct i40e_fc_info {
476 enum i40e_fc_mode current_mode; /* FC mode in effect */
477 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
480 #define I40E_MAX_TRAFFIC_CLASS 8
481 #define I40E_MAX_USER_PRIORITY 8
482 #define I40E_DCBX_MAX_APPS 32
483 #define I40E_LLDPDU_SIZE 1500
484 #define I40E_TLV_STATUS_OPER 0x1
485 #define I40E_TLV_STATUS_SYNC 0x2
486 #define I40E_TLV_STATUS_ERR 0x4
487 #define I40E_CEE_OPER_MAX_APPS 3
488 #define I40E_APP_PROTOID_FCOE 0x8906
489 #define I40E_APP_PROTOID_ISCSI 0x0cbc
490 #define I40E_APP_PROTOID_FIP 0x8914
491 #define I40E_APP_SEL_ETHTYPE 0x1
492 #define I40E_APP_SEL_TCPIP 0x2
494 /* CEE or IEEE 802.1Qaz ETS Configuration data */
495 struct i40e_dcb_ets_config {
499 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
500 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
501 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
504 /* CEE or IEEE 802.1Qaz PFC Configuration data */
505 struct i40e_dcb_pfc_config {
512 /* CEE or IEEE 802.1Qaz Application Priority data */
513 struct i40e_dcb_app_priority_table {
519 struct i40e_dcbx_config {
521 #define I40E_DCBX_MODE_CEE 0x1
522 #define I40E_DCBX_MODE_IEEE 0x2
524 struct i40e_dcb_ets_config etscfg;
525 struct i40e_dcb_ets_config etsrec;
526 struct i40e_dcb_pfc_config pfc;
527 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
530 /* Port hardware description */
535 /* subsystem structs */
536 struct i40e_phy_info phy;
537 struct i40e_mac_info mac;
538 struct i40e_bus_info bus;
539 struct i40e_nvm_info nvm;
540 struct i40e_fc_info fc;
545 u16 subsystem_device_id;
546 u16 subsystem_vendor_id;
549 bool adapter_stopped;
551 /* capabilities for entire device and PCI func */
552 struct i40e_hw_capabilities dev_caps;
553 struct i40e_hw_capabilities func_caps;
555 /* Flow Director shared filter space */
556 u16 fdir_shared_filter_count;
558 /* device profile info */
562 /* for multi-function MACs */
567 /* Closest numa node to the device */
570 /* Admin Queue info */
571 struct i40e_adminq_info aq;
573 /* state of nvm update process */
574 enum i40e_nvmupd_state nvmupd_state;
575 struct i40e_aq_desc nvm_wb_desc;
576 struct i40e_virt_mem nvm_buff;
579 struct i40e_hmc_info hmc; /* HMC info struct */
581 /* LLDP/DCBX Status */
585 struct i40e_dcbx_config local_dcbx_config;
586 struct i40e_dcbx_config remote_dcbx_config;
590 #ifndef I40E_NDIS_SUPPORT
592 #endif /* I40E_NDIS_SUPPORT */
595 static inline bool i40e_is_vf(struct i40e_hw *hw)
597 return hw->mac.type == I40E_MAC_VF;
600 struct i40e_driver_version {
605 u8 driver_string[32];
609 union i40e_16byte_rx_desc {
611 __le64 pkt_addr; /* Packet buffer address */
612 __le64 hdr_addr; /* Header buffer address */
618 __le16 mirroring_status;
624 __le32 rss; /* RSS Hash */
625 __le32 fd_id; /* Flow director filter id */
626 __le32 fcoe_param; /* FCoE DDP Context id */
630 /* ext status/error/pktype/length */
631 __le64 status_error_len;
633 } wb; /* writeback */
636 union i40e_32byte_rx_desc {
638 __le64 pkt_addr; /* Packet buffer address */
639 __le64 hdr_addr; /* Header buffer address */
640 /* bit 0 of hdr_buffer_addr is DD bit */
648 __le16 mirroring_status;
654 __le32 rss; /* RSS Hash */
655 __le32 fcoe_param; /* FCoE DDP Context id */
656 /* Flow director filter id in case of
657 * Programming status desc WB
663 /* status/error/pktype/length */
664 __le64 status_error_len;
667 __le16 ext_status; /* extended status */
674 __le32 flex_bytes_lo;
678 __le32 flex_bytes_hi;
682 } wb; /* writeback */
685 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
686 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
687 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
688 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
689 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
690 I40E_RXD_QW0_FCOEINDX_SHIFT)
692 enum i40e_rx_desc_status_bits {
693 /* Note: These are predefined bit offsets */
694 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
695 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
696 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
697 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
698 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
699 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
700 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
701 I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8,
703 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
704 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
705 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
706 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
707 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
708 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
709 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
710 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
713 #define I40E_RXD_QW1_STATUS_SHIFT 0
714 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
715 I40E_RXD_QW1_STATUS_SHIFT)
717 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
718 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
719 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
721 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
722 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
724 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
725 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
726 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
728 enum i40e_rx_desc_fltstat_values {
729 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
730 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
731 I40E_RX_DESC_FLTSTAT_RSV = 2,
732 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
735 #define I40E_RXD_PACKET_TYPE_UNICAST 0
736 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
737 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
738 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
740 #define I40E_RXD_QW1_ERROR_SHIFT 19
741 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
743 enum i40e_rx_desc_error_bits {
744 /* Note: These are predefined bit offsets */
745 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
746 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
747 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
748 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
749 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
750 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
751 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
752 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
753 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
756 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
757 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
758 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
759 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
760 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
761 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
764 #define I40E_RXD_QW1_PTYPE_SHIFT 30
765 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
767 /* Packet type non-ip values */
768 enum i40e_rx_l2_ptype {
769 I40E_RX_PTYPE_L2_RESERVED = 0,
770 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
771 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
772 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
773 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
774 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
775 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
776 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
777 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
778 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
779 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
780 I40E_RX_PTYPE_L2_ARP = 11,
781 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
782 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
783 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
784 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
785 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
786 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
787 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
788 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
789 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
790 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
791 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
792 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
793 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
794 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
797 struct i40e_rx_ptype_decoded {
804 u32 tunnel_end_prot:2;
805 u32 tunnel_end_frag:1;
810 enum i40e_rx_ptype_outer_ip {
811 I40E_RX_PTYPE_OUTER_L2 = 0,
812 I40E_RX_PTYPE_OUTER_IP = 1
815 enum i40e_rx_ptype_outer_ip_ver {
816 I40E_RX_PTYPE_OUTER_NONE = 0,
817 I40E_RX_PTYPE_OUTER_IPV4 = 0,
818 I40E_RX_PTYPE_OUTER_IPV6 = 1
821 enum i40e_rx_ptype_outer_fragmented {
822 I40E_RX_PTYPE_NOT_FRAG = 0,
823 I40E_RX_PTYPE_FRAG = 1
826 enum i40e_rx_ptype_tunnel_type {
827 I40E_RX_PTYPE_TUNNEL_NONE = 0,
828 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
829 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
830 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
831 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
834 enum i40e_rx_ptype_tunnel_end_prot {
835 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
836 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
837 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
840 enum i40e_rx_ptype_inner_prot {
841 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
842 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
843 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
844 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
845 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
846 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
849 enum i40e_rx_ptype_payload_layer {
850 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
851 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
852 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
853 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
856 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
857 #define I40E_RX_PTYPE_SHIFT 56
859 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
860 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
861 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
863 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
864 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
865 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
867 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
868 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
870 #define I40E_RXD_QW1_NEXTP_SHIFT 38
871 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
873 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
874 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
875 I40E_RXD_QW2_EXT_STATUS_SHIFT)
877 enum i40e_rx_desc_ext_status_bits {
878 /* Note: These are predefined bit offsets */
879 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
880 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
881 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
882 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
883 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
884 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
885 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
888 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
889 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
891 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
892 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
894 enum i40e_rx_desc_pe_status_bits {
895 /* Note: These are predefined bit offsets */
896 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
897 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
898 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
899 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
900 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
901 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
902 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
903 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
904 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
907 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
908 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
910 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
911 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
912 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
914 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
915 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
916 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
918 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
919 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
920 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
922 enum i40e_rx_prog_status_desc_status_bits {
923 /* Note: These are predefined bit offsets */
924 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
925 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
928 enum i40e_rx_prog_status_desc_prog_id_masks {
929 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
930 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
931 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
934 enum i40e_rx_prog_status_desc_error_bits {
935 /* Note: These are predefined bit offsets */
936 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
937 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
938 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
939 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
942 #define I40E_TWO_BIT_MASK 0x3
943 #define I40E_THREE_BIT_MASK 0x7
944 #define I40E_FOUR_BIT_MASK 0xF
945 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
948 struct i40e_tx_desc {
949 __le64 buffer_addr; /* Address of descriptor's data buf */
950 __le64 cmd_type_offset_bsz;
953 #define I40E_TXD_QW1_DTYPE_SHIFT 0
954 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
956 enum i40e_tx_desc_dtype_value {
957 I40E_TX_DESC_DTYPE_DATA = 0x0,
958 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
959 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
960 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
961 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
962 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
963 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
964 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
965 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
966 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
969 #define I40E_TXD_QW1_CMD_SHIFT 4
970 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
972 enum i40e_tx_desc_cmd_bits {
973 I40E_TX_DESC_CMD_EOP = 0x0001,
974 I40E_TX_DESC_CMD_RS = 0x0002,
975 I40E_TX_DESC_CMD_ICRC = 0x0004,
976 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
977 I40E_TX_DESC_CMD_DUMMY = 0x0010,
978 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
979 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
980 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
981 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
982 I40E_TX_DESC_CMD_FCOET = 0x0080,
983 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
984 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
985 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
986 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
987 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
988 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
989 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
990 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
993 #define I40E_TXD_QW1_OFFSET_SHIFT 16
994 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
995 I40E_TXD_QW1_OFFSET_SHIFT)
997 enum i40e_tx_desc_length_fields {
998 /* Note: These are predefined bit offsets */
999 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1000 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1001 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1004 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1005 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1006 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1007 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1009 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1010 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1011 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1013 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1014 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1016 /* Context descriptors */
1017 struct i40e_tx_context_desc {
1018 __le32 tunneling_params;
1021 __le64 type_cmd_tso_mss;
1024 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1025 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1027 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1028 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1030 enum i40e_tx_ctx_desc_cmd_bits {
1031 I40E_TX_CTX_DESC_TSO = 0x01,
1032 I40E_TX_CTX_DESC_TSYN = 0x02,
1033 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1034 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1035 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1036 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1037 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1038 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1039 I40E_TX_CTX_DESC_SWPE = 0x40
1042 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1043 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1044 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1046 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1047 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1048 I40E_TXD_CTX_QW1_MSS_SHIFT)
1050 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1051 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1053 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1054 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1055 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1057 enum i40e_tx_ctx_desc_eipt_offload {
1058 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1059 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1060 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1061 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1064 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1065 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1066 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1068 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1069 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1071 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1072 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1074 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1075 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1077 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1079 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1080 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1081 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1083 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1084 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1085 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1087 struct i40e_nop_desc {
1092 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1093 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1095 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1096 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1098 enum i40e_tx_nop_desc_cmd_bits {
1099 /* Note: These are predefined bit offsets */
1100 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1101 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1102 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1105 struct i40e_filter_program_desc {
1106 __le32 qindex_flex_ptype_vsi;
1108 __le32 dtype_cmd_cntindex;
1111 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1112 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1113 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1114 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1115 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1116 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1117 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1118 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1119 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1121 /* Packet Classifier Types for filters */
1122 enum i40e_filter_pctype {
1123 /* Note: Values 0-30 are reserved for future use */
1124 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1125 /* Note: Value 32 is reserved for future use */
1126 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1127 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1128 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1129 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1130 /* Note: Values 37-40 are reserved for future use */
1131 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1132 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1133 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1134 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1135 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1136 /* Note: Value 47 is reserved for future use */
1137 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1138 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1139 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1140 /* Note: Values 51-62 are reserved for future use */
1141 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1144 enum i40e_filter_program_desc_dest {
1145 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1146 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1147 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1150 enum i40e_filter_program_desc_fd_status {
1151 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1152 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1153 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1154 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1157 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1158 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1159 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1161 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1162 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1164 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1165 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1166 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1168 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1169 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1171 enum i40e_filter_program_desc_pcmd {
1172 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1173 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1176 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1177 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1179 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1180 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1182 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1183 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1184 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1185 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1187 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1188 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1189 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1191 enum i40e_filter_type {
1192 I40E_FLOW_DIRECTOR_FLTR = 0,
1193 I40E_PE_QUAD_HASH_FLTR = 1,
1194 I40E_ETHERTYPE_FLTR,
1200 struct i40e_vsi_context {
1205 u16 vsis_unallocated;
1210 struct i40e_aqc_vsi_properties_data info;
1213 struct i40e_veb_context {
1218 u16 vebs_unallocated;
1220 struct i40e_aqc_get_veb_parameters_completion info;
1223 /* Statistics collected by each port, VSI, VEB, and S-channel */
1224 struct i40e_eth_stats {
1225 u64 rx_bytes; /* gorc */
1226 u64 rx_unicast; /* uprc */
1227 u64 rx_multicast; /* mprc */
1228 u64 rx_broadcast; /* bprc */
1229 u64 rx_discards; /* rdpc */
1230 u64 rx_unknown_protocol; /* rupp */
1231 u64 tx_bytes; /* gotc */
1232 u64 tx_unicast; /* uptc */
1233 u64 tx_multicast; /* mptc */
1234 u64 tx_broadcast; /* bptc */
1235 u64 tx_discards; /* tdpc */
1236 u64 tx_errors; /* tepc */
1239 /* Statistics collected per VEB per TC */
1240 struct i40e_veb_tc_stats {
1241 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1242 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1243 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1244 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1247 /* Statistics collected by the MAC */
1248 struct i40e_hw_port_stats {
1249 /* eth stats collected by the port */
1250 struct i40e_eth_stats eth;
1252 /* additional port specific stats */
1253 u64 tx_dropped_link_down; /* tdold */
1254 u64 crc_errors; /* crcerrs */
1255 u64 illegal_bytes; /* illerrc */
1256 u64 error_bytes; /* errbc */
1257 u64 mac_local_faults; /* mlfc */
1258 u64 mac_remote_faults; /* mrfc */
1259 u64 rx_length_errors; /* rlec */
1260 u64 link_xon_rx; /* lxonrxc */
1261 u64 link_xoff_rx; /* lxoffrxc */
1262 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1263 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1264 u64 link_xon_tx; /* lxontxc */
1265 u64 link_xoff_tx; /* lxofftxc */
1266 u64 priority_xon_tx[8]; /* pxontxc[8] */
1267 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1268 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1269 u64 rx_size_64; /* prc64 */
1270 u64 rx_size_127; /* prc127 */
1271 u64 rx_size_255; /* prc255 */
1272 u64 rx_size_511; /* prc511 */
1273 u64 rx_size_1023; /* prc1023 */
1274 u64 rx_size_1522; /* prc1522 */
1275 u64 rx_size_big; /* prc9522 */
1276 u64 rx_undersize; /* ruc */
1277 u64 rx_fragments; /* rfc */
1278 u64 rx_oversize; /* roc */
1279 u64 rx_jabber; /* rjc */
1280 u64 tx_size_64; /* ptc64 */
1281 u64 tx_size_127; /* ptc127 */
1282 u64 tx_size_255; /* ptc255 */
1283 u64 tx_size_511; /* ptc511 */
1284 u64 tx_size_1023; /* ptc1023 */
1285 u64 tx_size_1522; /* ptc1522 */
1286 u64 tx_size_big; /* ptc9522 */
1287 u64 mac_short_packet_dropped; /* mspdc */
1288 u64 checksum_error; /* xec */
1289 /* flow director stats */
1295 u64 tx_lpi_count; /* etlpic */
1296 u64 rx_lpi_count; /* erlpic */
1299 /* Checksum and Shadow RAM pointers */
1300 #define I40E_SR_NVM_CONTROL_WORD 0x00
1301 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1302 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1303 #define I40E_SR_OPTION_ROM_PTR 0x05
1304 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1305 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1306 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1307 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1308 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1309 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1310 #define I40E_SR_PE_IMAGE_PTR 0x0C
1311 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1312 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1313 #define I40E_SR_EMP_MODULE_PTR 0x0F
1314 #define I40E_SR_PBA_FLAGS 0x15
1315 #define I40E_SR_PBA_BLOCK_PTR 0x16
1316 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1317 #define I40E_NVM_OEM_VER_OFF 0x83
1318 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1319 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1320 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1321 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1322 #define I40E_SR_NVM_MAP_VERSION 0x29
1323 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1324 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1325 #define I40E_SR_NVM_EETRACK_LO 0x2D
1326 #define I40E_SR_NVM_EETRACK_HI 0x2E
1327 #define I40E_SR_VPD_PTR 0x2F
1328 #define I40E_SR_PXE_SETUP_PTR 0x30
1329 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1330 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1331 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1332 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1333 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1334 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1335 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1336 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1337 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1338 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1339 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1340 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1341 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1342 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1343 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1344 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1345 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1346 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1348 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1349 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1350 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1351 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1352 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1354 /* Shadow RAM related */
1355 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1356 #define I40E_SR_BUF_ALIGNMENT 4096
1357 #define I40E_SR_WORDS_IN_1KB 512
1358 /* Checksum should be calculated such that after adding all the words,
1359 * including the checksum word itself, the sum should be 0xBABA.
1361 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1363 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1365 enum i40e_switch_element_types {
1366 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1367 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1368 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1369 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1370 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1371 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1372 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1373 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1374 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1377 /* Supported EtherType filters */
1378 enum i40e_ether_type_index {
1379 I40E_ETHER_TYPE_1588 = 0,
1380 I40E_ETHER_TYPE_FIP = 1,
1381 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1382 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1383 I40E_ETHER_TYPE_LLDP = 4,
1384 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1385 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1386 I40E_ETHER_TYPE_QCN_CNM = 7,
1387 I40E_ETHER_TYPE_8021X = 8,
1388 I40E_ETHER_TYPE_ARP = 9,
1389 I40E_ETHER_TYPE_RSV1 = 10,
1390 I40E_ETHER_TYPE_RSV2 = 11,
1393 /* Filter context base size is 1K */
1394 #define I40E_HASH_FILTER_BASE_SIZE 1024
1395 /* Supported Hash filter values */
1396 enum i40e_hash_filter_size {
1397 I40E_HASH_FILTER_SIZE_1K = 0,
1398 I40E_HASH_FILTER_SIZE_2K = 1,
1399 I40E_HASH_FILTER_SIZE_4K = 2,
1400 I40E_HASH_FILTER_SIZE_8K = 3,
1401 I40E_HASH_FILTER_SIZE_16K = 4,
1402 I40E_HASH_FILTER_SIZE_32K = 5,
1403 I40E_HASH_FILTER_SIZE_64K = 6,
1404 I40E_HASH_FILTER_SIZE_128K = 7,
1405 I40E_HASH_FILTER_SIZE_256K = 8,
1406 I40E_HASH_FILTER_SIZE_512K = 9,
1407 I40E_HASH_FILTER_SIZE_1M = 10,
1410 /* DMA context base size is 0.5K */
1411 #define I40E_DMA_CNTX_BASE_SIZE 512
1412 /* Supported DMA context values */
1413 enum i40e_dma_cntx_size {
1414 I40E_DMA_CNTX_SIZE_512 = 0,
1415 I40E_DMA_CNTX_SIZE_1K = 1,
1416 I40E_DMA_CNTX_SIZE_2K = 2,
1417 I40E_DMA_CNTX_SIZE_4K = 3,
1418 I40E_DMA_CNTX_SIZE_8K = 4,
1419 I40E_DMA_CNTX_SIZE_16K = 5,
1420 I40E_DMA_CNTX_SIZE_32K = 6,
1421 I40E_DMA_CNTX_SIZE_64K = 7,
1422 I40E_DMA_CNTX_SIZE_128K = 8,
1423 I40E_DMA_CNTX_SIZE_256K = 9,
1426 /* Supported Hash look up table (LUT) sizes */
1427 enum i40e_hash_lut_size {
1428 I40E_HASH_LUT_SIZE_128 = 0,
1429 I40E_HASH_LUT_SIZE_512 = 1,
1432 /* Structure to hold a per PF filter control settings */
1433 struct i40e_filter_control_settings {
1434 /* number of PE Quad Hash filter buckets */
1435 enum i40e_hash_filter_size pe_filt_num;
1436 /* number of PE Quad Hash contexts */
1437 enum i40e_dma_cntx_size pe_cntx_num;
1438 /* number of FCoE filter buckets */
1439 enum i40e_hash_filter_size fcoe_filt_num;
1440 /* number of FCoE DDP contexts */
1441 enum i40e_dma_cntx_size fcoe_cntx_num;
1442 /* size of the Hash LUT */
1443 enum i40e_hash_lut_size hash_lut_size;
1444 /* enable FDIR filters for PF and its VFs */
1446 /* enable Ethertype filters for PF and its VFs */
1447 bool enable_ethtype;
1448 /* enable MAC/VLAN filters for PF and its VFs */
1449 bool enable_macvlan;
1452 /* Structure to hold device level control filter counts */
1453 struct i40e_control_filter_stats {
1454 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1455 u16 etype_used; /* Used perfect EtherType filters */
1456 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1457 u16 etype_free; /* Un-used perfect EtherType filters */
1460 enum i40e_reset_type {
1462 I40E_RESET_CORER = 1,
1463 I40E_RESET_GLOBR = 2,
1464 I40E_RESET_EMPR = 3,
1467 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1468 #define I40E_NVM_LLDP_CFG_PTR 0xD
1469 struct i40e_lldp_variables {
1479 /* Offsets into Alternate Ram */
1480 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1481 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1482 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1483 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1484 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1485 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1487 /* Alternate Ram Bandwidth Masks */
1488 #define I40E_ALT_BW_VALUE_MASK 0xFF
1489 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1490 #define I40E_ALT_BW_VALID_MASK 0x80000000
1492 /* RSS Hash Table Size */
1493 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1494 #endif /* _I40E_TYPE_H_ */