1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "i40e_status.h"
38 #include "i40e_osdep.h"
39 #include "i40e_register.h"
40 #include "i40e_adminq.h"
42 #include "i40e_lan_hmc.h"
43 #include "i40e_devids.h"
45 #define UNREFERENCED_XPARAMETER
46 #define UNREFERENCED_1PARAMETER(_p) (_p);
47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
54 #define BIT(a) (1UL << (a))
57 #define BIT_ULL(a) (1ULL << (a))
59 #endif /* LINUX_MACROS */
62 /* I40E_MASK is a macro used on 32 bit registers */
63 #define I40E_MASK(mask, shift) (mask << shift)
66 #define I40E_MAX_PF 16
67 #define I40E_MAX_PF_VSI 64
68 #define I40E_MAX_PF_QP 128
69 #define I40E_MAX_VSI_QP 16
70 #define I40E_MAX_VF_VSI 3
71 #define I40E_MAX_CHAINED_RX_BUFFERS 5
72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
74 /* something less than 1 minute */
75 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
77 /* Max default timeout in ms, */
78 #define I40E_MAX_NVM_TIMEOUT 18000
80 /* Check whether address is multicast. */
81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
83 /* Check whether an address is broadcast. */
84 #define I40E_IS_BROADCAST(address) \
85 ((((u8 *)(address))[0] == ((u8)0xff)) && \
86 (((u8 *)(address))[1] == ((u8)0xff)))
88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
89 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
91 /* forward declaration */
93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
95 #define I40E_ETH_LENGTH_OF_ADDRESS 6
96 /* Data type manipulation macros. */
97 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
98 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
100 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
101 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
103 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
104 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
106 /* Number of Transmit Descriptors must be a multiple of 8. */
107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
108 /* Number of Receive Descriptors must be a multiple of 32 if
109 * the number of descriptors is greater than 32.
111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
113 #define I40E_DESC_UNUSED(R) \
114 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
115 (R)->next_to_clean - (R)->next_to_use - 1)
117 /* bitfields for Tx queue mapping in QTX_CTL */
118 #define I40E_QTX_CTL_VF_QUEUE 0x0
119 #define I40E_QTX_CTL_VM_QUEUE 0x1
120 #define I40E_QTX_CTL_PF_QUEUE 0x2
122 /* debug masks - set these bits in hw->debug_mask to control output */
123 enum i40e_debug_mask {
124 I40E_DEBUG_INIT = 0x00000001,
125 I40E_DEBUG_RELEASE = 0x00000002,
127 I40E_DEBUG_LINK = 0x00000010,
128 I40E_DEBUG_PHY = 0x00000020,
129 I40E_DEBUG_HMC = 0x00000040,
130 I40E_DEBUG_NVM = 0x00000080,
131 I40E_DEBUG_LAN = 0x00000100,
132 I40E_DEBUG_FLOW = 0x00000200,
133 I40E_DEBUG_DCB = 0x00000400,
134 I40E_DEBUG_DIAG = 0x00000800,
135 I40E_DEBUG_FD = 0x00001000,
137 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
138 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
139 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
140 I40E_DEBUG_AQ_COMMAND = 0x06000000,
141 I40E_DEBUG_AQ = 0x0F000000,
143 I40E_DEBUG_USER = 0xF0000000,
145 I40E_DEBUG_ALL = 0xFFFFFFFF
149 #define I40E_PCI_LINK_STATUS 0xB2
150 #define I40E_PCI_LINK_WIDTH 0x3F0
151 #define I40E_PCI_LINK_WIDTH_1 0x10
152 #define I40E_PCI_LINK_WIDTH_2 0x20
153 #define I40E_PCI_LINK_WIDTH_4 0x40
154 #define I40E_PCI_LINK_WIDTH_8 0x80
155 #define I40E_PCI_LINK_SPEED 0xF
156 #define I40E_PCI_LINK_SPEED_2500 0x1
157 #define I40E_PCI_LINK_SPEED_5000 0x2
158 #define I40E_PCI_LINK_SPEED_8000 0x3
161 enum i40e_memset_type {
167 enum i40e_memcpy_type {
168 I40E_NONDMA_TO_NONDMA = 0,
176 #define I40E_FW_API_VERSION_MINOR_X722 0x0003
178 #define I40E_FW_API_VERSION_MINOR_X710 0x0004
181 /* These are structs for managing the hardware information and the operations.
182 * The structures of function pointers are filled out at init time when we
183 * know for sure exactly which hardware we're working with. This gives us the
184 * flexibility of using the same main driver code but adapting to slightly
185 * different hardware needs as new parts are developed. For this architecture,
186 * the Firmware and AdminQ are intended to insulate the driver from most of the
187 * future changes, but these structures will also do part of the job.
190 I40E_MAC_UNKNOWN = 0,
201 enum i40e_media_type {
202 I40E_MEDIA_TYPE_UNKNOWN = 0,
203 I40E_MEDIA_TYPE_FIBER,
204 I40E_MEDIA_TYPE_BASET,
205 I40E_MEDIA_TYPE_BACKPLANE,
208 I40E_MEDIA_TYPE_VIRTUAL
220 enum i40e_set_fc_aq_failures {
221 I40E_SET_FC_AQ_FAIL_NONE = 0,
222 I40E_SET_FC_AQ_FAIL_GET = 1,
223 I40E_SET_FC_AQ_FAIL_SET = 2,
224 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
225 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
237 I40E_VSI_TYPE_UNKNOWN
240 enum i40e_queue_type {
241 I40E_QUEUE_TYPE_RX = 0,
243 I40E_QUEUE_TYPE_PE_CEQ,
244 I40E_QUEUE_TYPE_UNKNOWN
247 struct i40e_link_status {
248 enum i40e_aq_phy_type phy_type;
249 enum i40e_aq_link_speed link_speed;
254 /* is Link Status Event notification to SW enabled */
261 /* 1st byte: module identifier */
262 #define I40E_MODULE_TYPE_SFP 0x03
263 #define I40E_MODULE_TYPE_QSFP 0x0D
264 /* 2nd byte: ethernet compliance codes for 10/40G */
265 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
266 #define I40E_MODULE_TYPE_40G_LR4 0x02
267 #define I40E_MODULE_TYPE_40G_SR4 0x04
268 #define I40E_MODULE_TYPE_40G_CR4 0x08
269 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
270 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
271 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
272 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
273 /* 3rd byte: ethernet compliance codes for 1G */
274 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
275 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
276 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
277 #define I40E_MODULE_TYPE_1000BASE_T 0x08
280 enum i40e_aq_capabilities_phy_type {
281 I40E_CAP_PHY_TYPE_SGMII = BIT(I40E_PHY_TYPE_SGMII),
282 I40E_CAP_PHY_TYPE_1000BASE_KX = BIT(I40E_PHY_TYPE_1000BASE_KX),
283 I40E_CAP_PHY_TYPE_10GBASE_KX4 = BIT(I40E_PHY_TYPE_10GBASE_KX4),
284 I40E_CAP_PHY_TYPE_10GBASE_KR = BIT(I40E_PHY_TYPE_10GBASE_KR),
285 I40E_CAP_PHY_TYPE_40GBASE_KR4 = BIT(I40E_PHY_TYPE_40GBASE_KR4),
286 I40E_CAP_PHY_TYPE_XAUI = BIT(I40E_PHY_TYPE_XAUI),
287 I40E_CAP_PHY_TYPE_XFI = BIT(I40E_PHY_TYPE_XFI),
288 I40E_CAP_PHY_TYPE_SFI = BIT(I40E_PHY_TYPE_SFI),
289 I40E_CAP_PHY_TYPE_XLAUI = BIT(I40E_PHY_TYPE_XLAUI),
290 I40E_CAP_PHY_TYPE_XLPPI = BIT(I40E_PHY_TYPE_XLPPI),
291 I40E_CAP_PHY_TYPE_40GBASE_CR4_CU = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
292 I40E_CAP_PHY_TYPE_10GBASE_CR1_CU = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
293 I40E_CAP_PHY_TYPE_10GBASE_AOC = BIT(I40E_PHY_TYPE_10GBASE_AOC),
294 I40E_CAP_PHY_TYPE_40GBASE_AOC = BIT(I40E_PHY_TYPE_40GBASE_AOC),
295 I40E_CAP_PHY_TYPE_100BASE_TX = BIT(I40E_PHY_TYPE_100BASE_TX),
296 I40E_CAP_PHY_TYPE_1000BASE_T = BIT(I40E_PHY_TYPE_1000BASE_T),
297 I40E_CAP_PHY_TYPE_10GBASE_T = BIT(I40E_PHY_TYPE_10GBASE_T),
298 I40E_CAP_PHY_TYPE_10GBASE_SR = BIT(I40E_PHY_TYPE_10GBASE_SR),
299 I40E_CAP_PHY_TYPE_10GBASE_LR = BIT(I40E_PHY_TYPE_10GBASE_LR),
300 I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
301 I40E_CAP_PHY_TYPE_10GBASE_CR1 = BIT(I40E_PHY_TYPE_10GBASE_CR1),
302 I40E_CAP_PHY_TYPE_40GBASE_CR4 = BIT(I40E_PHY_TYPE_40GBASE_CR4),
303 I40E_CAP_PHY_TYPE_40GBASE_SR4 = BIT(I40E_PHY_TYPE_40GBASE_SR4),
304 I40E_CAP_PHY_TYPE_40GBASE_LR4 = BIT(I40E_PHY_TYPE_40GBASE_LR4),
305 I40E_CAP_PHY_TYPE_1000BASE_SX = BIT(I40E_PHY_TYPE_1000BASE_SX),
306 I40E_CAP_PHY_TYPE_1000BASE_LX = BIT(I40E_PHY_TYPE_1000BASE_LX),
307 I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL = BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
308 I40E_CAP_PHY_TYPE_20GBASE_KR2 = BIT(I40E_PHY_TYPE_20GBASE_KR2)
311 struct i40e_phy_info {
312 struct i40e_link_status link_info;
313 struct i40e_link_status link_info_old;
315 enum i40e_media_type media_type;
316 /* all the phy types the NVM is capable of */
320 #define I40E_HW_CAP_MAX_GPIO 30
321 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
322 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
325 enum i40e_acpi_programming_method {
326 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
327 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
330 #define I40E_WOL_SUPPORT_MASK 1
331 #define I40E_ACPI_PROGRAMMING_METHOD_MASK (1 << 1)
332 #define I40E_PROXY_SUPPORT_MASK (1 << 2)
335 /* Capabilities of a PF or a VF or the whole device */
336 struct i40e_hw_capabilities {
338 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
339 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
340 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
348 bool evb_802_1_qbg; /* Edge Virtual Bridging */
349 bool evb_802_1_qbh; /* Bridge Port Extension */
352 bool iscsi; /* Indicates iSCSI enabled */
356 #define I40E_FLEX10_MODE_UNKNOWN 0x0
357 #define I40E_FLEX10_MODE_DCC 0x1
358 #define I40E_FLEX10_MODE_DCI 0x2
361 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
362 #define I40E_FLEX10_STATUS_VC_MODE 0x2
368 u32 fd_filters_guaranteed;
369 u32 fd_filters_best_effort;
372 u32 rss_table_entry_width;
373 bool led[I40E_HW_CAP_MAX_GPIO];
374 bool sdp[I40E_HW_CAP_MAX_GPIO];
376 u32 num_flow_director_filters;
383 u32 num_msix_vectors;
384 u32 num_msix_vectors_vf;
394 bool apm_wol_support;
395 enum i40e_acpi_programming_method acpi_prog_method;
400 struct i40e_mac_info {
401 enum i40e_mac_type type;
402 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
403 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
404 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
405 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
409 enum i40e_aq_resources_ids {
410 I40E_NVM_RESOURCE_ID = 1
413 enum i40e_aq_resource_access_type {
414 I40E_RESOURCE_READ = 1,
418 struct i40e_nvm_info {
419 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
420 u32 timeout; /* [ms] */
421 u16 sr_size; /* Shadow RAM size in words */
422 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
423 u16 version; /* NVM package version */
424 u32 eetrack; /* NVM data version */
425 u32 oem_ver; /* OEM version info */
428 /* definitions used in NVM update support */
430 enum i40e_nvmupd_cmd {
432 I40E_NVMUPD_READ_CON,
433 I40E_NVMUPD_READ_SNT,
434 I40E_NVMUPD_READ_LCB,
436 I40E_NVMUPD_WRITE_ERA,
437 I40E_NVMUPD_WRITE_CON,
438 I40E_NVMUPD_WRITE_SNT,
439 I40E_NVMUPD_WRITE_LCB,
440 I40E_NVMUPD_WRITE_SA,
441 I40E_NVMUPD_CSUM_CON,
443 I40E_NVMUPD_CSUM_LCB,
446 I40E_NVMUPD_GET_AQ_RESULT,
449 enum i40e_nvmupd_state {
450 I40E_NVMUPD_STATE_INIT,
451 I40E_NVMUPD_STATE_READING,
452 I40E_NVMUPD_STATE_WRITING,
453 I40E_NVMUPD_STATE_INIT_WAIT,
454 I40E_NVMUPD_STATE_WRITE_WAIT,
457 /* nvm_access definition and its masks/shifts need to be accessible to
458 * application, core driver, and shared code. Where is the right file?
460 #define I40E_NVM_READ 0xB
461 #define I40E_NVM_WRITE 0xC
463 #define I40E_NVM_MOD_PNT_MASK 0xFF
465 #define I40E_NVM_TRANS_SHIFT 8
466 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
467 #define I40E_NVM_CON 0x0
468 #define I40E_NVM_SNT 0x1
469 #define I40E_NVM_LCB 0x2
470 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
471 #define I40E_NVM_ERA 0x4
472 #define I40E_NVM_CSUM 0x8
473 #define I40E_NVM_EXEC 0xf
475 #define I40E_NVM_ADAPT_SHIFT 16
476 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
478 #define I40E_NVMUPD_MAX_DATA 4096
479 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
481 struct i40e_nvm_access {
484 u32 offset; /* in bytes */
485 u32 data_size; /* in bytes */
491 i40e_bus_type_unknown = 0,
494 i40e_bus_type_pci_express,
495 i40e_bus_type_reserved
499 enum i40e_bus_speed {
500 i40e_bus_speed_unknown = 0,
501 i40e_bus_speed_33 = 33,
502 i40e_bus_speed_66 = 66,
503 i40e_bus_speed_100 = 100,
504 i40e_bus_speed_120 = 120,
505 i40e_bus_speed_133 = 133,
506 i40e_bus_speed_2500 = 2500,
507 i40e_bus_speed_5000 = 5000,
508 i40e_bus_speed_8000 = 8000,
509 i40e_bus_speed_reserved
513 enum i40e_bus_width {
514 i40e_bus_width_unknown = 0,
515 i40e_bus_width_pcie_x1 = 1,
516 i40e_bus_width_pcie_x2 = 2,
517 i40e_bus_width_pcie_x4 = 4,
518 i40e_bus_width_pcie_x8 = 8,
519 i40e_bus_width_32 = 32,
520 i40e_bus_width_64 = 64,
521 i40e_bus_width_reserved
525 struct i40e_bus_info {
526 enum i40e_bus_speed speed;
527 enum i40e_bus_width width;
528 enum i40e_bus_type type;
535 /* Flow control (FC) parameters */
536 struct i40e_fc_info {
537 enum i40e_fc_mode current_mode; /* FC mode in effect */
538 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
541 #define I40E_MAX_TRAFFIC_CLASS 8
542 #define I40E_MAX_USER_PRIORITY 8
543 #define I40E_DCBX_MAX_APPS 32
544 #define I40E_LLDPDU_SIZE 1500
545 #define I40E_TLV_STATUS_OPER 0x1
546 #define I40E_TLV_STATUS_SYNC 0x2
547 #define I40E_TLV_STATUS_ERR 0x4
548 #define I40E_CEE_OPER_MAX_APPS 3
549 #define I40E_APP_PROTOID_FCOE 0x8906
550 #define I40E_APP_PROTOID_ISCSI 0x0cbc
551 #define I40E_APP_PROTOID_FIP 0x8914
552 #define I40E_APP_SEL_ETHTYPE 0x1
553 #define I40E_APP_SEL_TCPIP 0x2
554 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
555 #define I40E_CEE_APP_SEL_TCPIP 0x1
557 /* CEE or IEEE 802.1Qaz ETS Configuration data */
558 struct i40e_dcb_ets_config {
562 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
563 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
564 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
567 /* CEE or IEEE 802.1Qaz PFC Configuration data */
568 struct i40e_dcb_pfc_config {
575 /* CEE or IEEE 802.1Qaz Application Priority data */
576 struct i40e_dcb_app_priority_table {
582 struct i40e_dcbx_config {
584 #define I40E_DCBX_MODE_CEE 0x1
585 #define I40E_DCBX_MODE_IEEE 0x2
587 #define I40E_DCBX_APPS_NON_WILLING 0x1
589 u32 tlv_status; /* CEE mode TLV status */
590 struct i40e_dcb_ets_config etscfg;
591 struct i40e_dcb_ets_config etsrec;
592 struct i40e_dcb_pfc_config pfc;
593 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
596 /* Port hardware description */
601 /* subsystem structs */
602 struct i40e_phy_info phy;
603 struct i40e_mac_info mac;
604 struct i40e_bus_info bus;
605 struct i40e_nvm_info nvm;
606 struct i40e_fc_info fc;
611 u16 subsystem_device_id;
612 u16 subsystem_vendor_id;
615 bool adapter_stopped;
617 /* capabilities for entire device and PCI func */
618 struct i40e_hw_capabilities dev_caps;
619 struct i40e_hw_capabilities func_caps;
621 /* Flow Director shared filter space */
622 u16 fdir_shared_filter_count;
624 /* device profile info */
628 /* for multi-function MACs */
633 /* Closest numa node to the device */
636 /* Admin Queue info */
637 struct i40e_adminq_info aq;
639 /* state of nvm update process */
640 enum i40e_nvmupd_state nvmupd_state;
641 struct i40e_aq_desc nvm_wb_desc;
642 struct i40e_virt_mem nvm_buff;
645 struct i40e_hmc_info hmc; /* HMC info struct */
647 /* LLDP/DCBX Status */
651 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
652 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
653 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
656 /* WoL and proxy support */
657 u16 num_wol_proxy_filters;
658 u16 wol_proxy_vsi_seid;
663 #ifndef I40E_NDIS_SUPPORT
665 #endif /* I40E_NDIS_SUPPORT */
668 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
671 return (hw->mac.type == I40E_MAC_VF ||
672 hw->mac.type == I40E_MAC_X722_VF);
674 return hw->mac.type == I40E_MAC_VF;
678 struct i40e_driver_version {
683 u8 driver_string[32];
687 union i40e_16byte_rx_desc {
689 __le64 pkt_addr; /* Packet buffer address */
690 __le64 hdr_addr; /* Header buffer address */
696 __le16 mirroring_status;
702 __le32 rss; /* RSS Hash */
703 __le32 fd_id; /* Flow director filter id */
704 __le32 fcoe_param; /* FCoE DDP Context id */
708 /* ext status/error/pktype/length */
709 __le64 status_error_len;
711 } wb; /* writeback */
714 union i40e_32byte_rx_desc {
716 __le64 pkt_addr; /* Packet buffer address */
717 __le64 hdr_addr; /* Header buffer address */
718 /* bit 0 of hdr_buffer_addr is DD bit */
726 __le16 mirroring_status;
732 __le32 rss; /* RSS Hash */
733 __le32 fcoe_param; /* FCoE DDP Context id */
734 /* Flow director filter id in case of
735 * Programming status desc WB
741 /* status/error/pktype/length */
742 __le64 status_error_len;
745 __le16 ext_status; /* extended status */
752 __le32 flex_bytes_lo;
756 __le32 flex_bytes_hi;
760 } wb; /* writeback */
763 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
764 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
765 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
766 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
767 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
768 I40E_RXD_QW0_FCOEINDX_SHIFT)
770 enum i40e_rx_desc_status_bits {
771 /* Note: These are predefined bit offsets */
772 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
773 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
774 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
775 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
776 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
777 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
778 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
780 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
782 I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8,
785 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
786 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
787 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
788 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
789 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
790 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
792 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
794 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
796 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
799 #define I40E_RXD_QW1_STATUS_SHIFT 0
800 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
801 I40E_RXD_QW1_STATUS_SHIFT)
803 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
804 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
805 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
807 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
808 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
810 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
811 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
812 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
814 enum i40e_rx_desc_fltstat_values {
815 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
816 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
817 I40E_RX_DESC_FLTSTAT_RSV = 2,
818 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
821 #define I40E_RXD_PACKET_TYPE_UNICAST 0
822 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
823 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
824 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
826 #define I40E_RXD_QW1_ERROR_SHIFT 19
827 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
829 enum i40e_rx_desc_error_bits {
830 /* Note: These are predefined bit offsets */
831 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
832 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
833 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
834 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
835 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
836 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
837 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
838 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
839 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
842 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
843 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
844 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
845 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
846 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
847 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
850 #define I40E_RXD_QW1_PTYPE_SHIFT 30
851 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
853 /* Packet type non-ip values */
854 enum i40e_rx_l2_ptype {
855 I40E_RX_PTYPE_L2_RESERVED = 0,
856 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
857 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
858 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
859 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
860 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
861 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
862 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
863 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
864 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
865 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
866 I40E_RX_PTYPE_L2_ARP = 11,
867 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
868 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
869 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
870 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
871 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
872 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
873 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
874 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
875 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
876 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
877 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
878 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
879 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
880 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
883 struct i40e_rx_ptype_decoded {
890 u32 tunnel_end_prot:2;
891 u32 tunnel_end_frag:1;
896 enum i40e_rx_ptype_outer_ip {
897 I40E_RX_PTYPE_OUTER_L2 = 0,
898 I40E_RX_PTYPE_OUTER_IP = 1
901 enum i40e_rx_ptype_outer_ip_ver {
902 I40E_RX_PTYPE_OUTER_NONE = 0,
903 I40E_RX_PTYPE_OUTER_IPV4 = 0,
904 I40E_RX_PTYPE_OUTER_IPV6 = 1
907 enum i40e_rx_ptype_outer_fragmented {
908 I40E_RX_PTYPE_NOT_FRAG = 0,
909 I40E_RX_PTYPE_FRAG = 1
912 enum i40e_rx_ptype_tunnel_type {
913 I40E_RX_PTYPE_TUNNEL_NONE = 0,
914 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
915 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
916 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
917 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
920 enum i40e_rx_ptype_tunnel_end_prot {
921 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
922 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
923 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
926 enum i40e_rx_ptype_inner_prot {
927 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
928 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
929 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
930 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
931 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
932 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
935 enum i40e_rx_ptype_payload_layer {
936 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
937 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
938 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
939 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
942 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
943 #define I40E_RX_PTYPE_SHIFT 56
945 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
946 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
947 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
949 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
950 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
951 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
953 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
954 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
956 #define I40E_RXD_QW1_NEXTP_SHIFT 38
957 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
959 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
960 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
961 I40E_RXD_QW2_EXT_STATUS_SHIFT)
963 enum i40e_rx_desc_ext_status_bits {
964 /* Note: These are predefined bit offsets */
965 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
966 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
967 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
968 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
969 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
970 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
971 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
974 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
975 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
977 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
978 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
980 enum i40e_rx_desc_pe_status_bits {
981 /* Note: These are predefined bit offsets */
982 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
983 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
984 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
985 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
986 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
987 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
988 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
989 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
990 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
993 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
994 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
996 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
997 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
998 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1000 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
1001 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
1002 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1004 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
1005 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
1006 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1008 enum i40e_rx_prog_status_desc_status_bits {
1009 /* Note: These are predefined bit offsets */
1010 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
1011 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
1014 enum i40e_rx_prog_status_desc_prog_id_masks {
1015 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
1016 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
1017 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
1020 enum i40e_rx_prog_status_desc_error_bits {
1021 /* Note: These are predefined bit offsets */
1022 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
1023 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
1024 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
1025 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
1028 #define I40E_TWO_BIT_MASK 0x3
1029 #define I40E_THREE_BIT_MASK 0x7
1030 #define I40E_FOUR_BIT_MASK 0xF
1031 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
1034 struct i40e_tx_desc {
1035 __le64 buffer_addr; /* Address of descriptor's data buf */
1036 __le64 cmd_type_offset_bsz;
1039 #define I40E_TXD_QW1_DTYPE_SHIFT 0
1040 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1042 enum i40e_tx_desc_dtype_value {
1043 I40E_TX_DESC_DTYPE_DATA = 0x0,
1044 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
1045 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
1046 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
1047 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
1048 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
1049 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
1050 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
1051 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
1052 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
1055 #define I40E_TXD_QW1_CMD_SHIFT 4
1056 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1058 enum i40e_tx_desc_cmd_bits {
1059 I40E_TX_DESC_CMD_EOP = 0x0001,
1060 I40E_TX_DESC_CMD_RS = 0x0002,
1061 I40E_TX_DESC_CMD_ICRC = 0x0004,
1062 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
1063 I40E_TX_DESC_CMD_DUMMY = 0x0010,
1064 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
1065 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
1066 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
1067 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
1068 I40E_TX_DESC_CMD_FCOET = 0x0080,
1069 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
1070 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
1071 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
1072 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
1073 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
1074 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
1075 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
1076 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
1079 #define I40E_TXD_QW1_OFFSET_SHIFT 16
1080 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
1081 I40E_TXD_QW1_OFFSET_SHIFT)
1083 enum i40e_tx_desc_length_fields {
1084 /* Note: These are predefined bit offsets */
1085 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1086 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1087 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1090 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1091 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1092 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1093 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1095 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1096 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1097 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1099 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1100 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1102 /* Context descriptors */
1103 struct i40e_tx_context_desc {
1104 __le32 tunneling_params;
1107 __le64 type_cmd_tso_mss;
1110 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1111 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1113 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1114 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1116 enum i40e_tx_ctx_desc_cmd_bits {
1117 I40E_TX_CTX_DESC_TSO = 0x01,
1118 I40E_TX_CTX_DESC_TSYN = 0x02,
1119 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1120 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1121 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1122 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1123 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1124 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1125 I40E_TX_CTX_DESC_SWPE = 0x40
1128 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1129 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1130 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1132 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1133 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1134 I40E_TXD_CTX_QW1_MSS_SHIFT)
1136 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1137 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1139 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1140 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1141 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1143 enum i40e_tx_ctx_desc_eipt_offload {
1144 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1145 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1146 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1147 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1150 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1151 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1152 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1154 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1155 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1157 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1158 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1160 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1161 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1163 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1165 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1166 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1167 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1169 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1170 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1171 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1174 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1175 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1177 struct i40e_nop_desc {
1182 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1183 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1185 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1186 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1188 enum i40e_tx_nop_desc_cmd_bits {
1189 /* Note: These are predefined bit offsets */
1190 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1191 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1192 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1195 struct i40e_filter_program_desc {
1196 __le32 qindex_flex_ptype_vsi;
1198 __le32 dtype_cmd_cntindex;
1201 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1202 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1203 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1204 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1205 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1206 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1207 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1208 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1209 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1211 /* Packet Classifier Types for filters */
1212 enum i40e_filter_pctype {
1214 /* Note: Values 0-28 are reserved for future use.
1215 * Value 29, 30, 32 are not supported on XL710 and X710.
1217 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1218 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1220 /* Note: Values 0-30 are reserved for future use */
1222 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1224 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1226 /* Note: Value 32 is reserved for future use */
1228 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1229 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1230 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1231 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1233 /* Note: Values 37-38 are reserved for future use.
1234 * Value 39, 40, 42 are not supported on XL710 and X710.
1236 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1237 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1239 /* Note: Values 37-40 are reserved for future use */
1241 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1243 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1245 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1246 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1247 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1248 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1249 /* Note: Value 47 is reserved for future use */
1250 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1251 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1252 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1253 /* Note: Values 51-62 are reserved for future use */
1254 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1257 enum i40e_filter_program_desc_dest {
1258 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1259 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1260 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1263 enum i40e_filter_program_desc_fd_status {
1264 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1265 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1266 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1267 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1270 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1271 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1272 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1274 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1275 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1277 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1278 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1279 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1281 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1282 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1284 enum i40e_filter_program_desc_pcmd {
1285 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1286 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1289 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1290 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1292 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1293 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1295 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1296 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1297 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1298 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1301 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1302 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1303 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1306 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1307 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1308 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1310 enum i40e_filter_type {
1311 I40E_FLOW_DIRECTOR_FLTR = 0,
1312 I40E_PE_QUAD_HASH_FLTR = 1,
1313 I40E_ETHERTYPE_FLTR,
1319 struct i40e_vsi_context {
1324 u16 vsis_unallocated;
1329 struct i40e_aqc_vsi_properties_data info;
1332 struct i40e_veb_context {
1337 u16 vebs_unallocated;
1339 struct i40e_aqc_get_veb_parameters_completion info;
1342 /* Statistics collected by each port, VSI, VEB, and S-channel */
1343 struct i40e_eth_stats {
1344 u64 rx_bytes; /* gorc */
1345 u64 rx_unicast; /* uprc */
1346 u64 rx_multicast; /* mprc */
1347 u64 rx_broadcast; /* bprc */
1348 u64 rx_discards; /* rdpc */
1349 u64 rx_unknown_protocol; /* rupp */
1350 u64 tx_bytes; /* gotc */
1351 u64 tx_unicast; /* uptc */
1352 u64 tx_multicast; /* mptc */
1353 u64 tx_broadcast; /* bptc */
1354 u64 tx_discards; /* tdpc */
1355 u64 tx_errors; /* tepc */
1358 /* Statistics collected per VEB per TC */
1359 struct i40e_veb_tc_stats {
1360 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1361 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1362 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1363 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1366 /* Statistics collected by the MAC */
1367 struct i40e_hw_port_stats {
1368 /* eth stats collected by the port */
1369 struct i40e_eth_stats eth;
1371 /* additional port specific stats */
1372 u64 tx_dropped_link_down; /* tdold */
1373 u64 crc_errors; /* crcerrs */
1374 u64 illegal_bytes; /* illerrc */
1375 u64 error_bytes; /* errbc */
1376 u64 mac_local_faults; /* mlfc */
1377 u64 mac_remote_faults; /* mrfc */
1378 u64 rx_length_errors; /* rlec */
1379 u64 link_xon_rx; /* lxonrxc */
1380 u64 link_xoff_rx; /* lxoffrxc */
1381 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1382 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1383 u64 link_xon_tx; /* lxontxc */
1384 u64 link_xoff_tx; /* lxofftxc */
1385 u64 priority_xon_tx[8]; /* pxontxc[8] */
1386 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1387 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1388 u64 rx_size_64; /* prc64 */
1389 u64 rx_size_127; /* prc127 */
1390 u64 rx_size_255; /* prc255 */
1391 u64 rx_size_511; /* prc511 */
1392 u64 rx_size_1023; /* prc1023 */
1393 u64 rx_size_1522; /* prc1522 */
1394 u64 rx_size_big; /* prc9522 */
1395 u64 rx_undersize; /* ruc */
1396 u64 rx_fragments; /* rfc */
1397 u64 rx_oversize; /* roc */
1398 u64 rx_jabber; /* rjc */
1399 u64 tx_size_64; /* ptc64 */
1400 u64 tx_size_127; /* ptc127 */
1401 u64 tx_size_255; /* ptc255 */
1402 u64 tx_size_511; /* ptc511 */
1403 u64 tx_size_1023; /* ptc1023 */
1404 u64 tx_size_1522; /* ptc1522 */
1405 u64 tx_size_big; /* ptc9522 */
1406 u64 mac_short_packet_dropped; /* mspdc */
1407 u64 checksum_error; /* xec */
1408 /* flow director stats */
1411 u64 fd_atr_tunnel_match;
1417 u64 tx_lpi_count; /* etlpic */
1418 u64 rx_lpi_count; /* erlpic */
1421 /* Checksum and Shadow RAM pointers */
1422 #define I40E_SR_NVM_CONTROL_WORD 0x00
1423 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1424 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1425 #define I40E_SR_OPTION_ROM_PTR 0x05
1426 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1427 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1428 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1429 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1430 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1431 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1432 #define I40E_SR_PE_IMAGE_PTR 0x0C
1433 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1434 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1435 #define I40E_SR_EMP_MODULE_PTR 0x0F
1436 #define I40E_SR_PBA_FLAGS 0x15
1437 #define I40E_SR_PBA_BLOCK_PTR 0x16
1438 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1439 #define I40E_NVM_OEM_VER_OFF 0x83
1440 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1441 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1442 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1443 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1444 #define I40E_SR_NVM_MAP_VERSION 0x29
1445 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1446 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1447 #define I40E_SR_NVM_EETRACK_LO 0x2D
1448 #define I40E_SR_NVM_EETRACK_HI 0x2E
1449 #define I40E_SR_VPD_PTR 0x2F
1450 #define I40E_SR_PXE_SETUP_PTR 0x30
1451 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1452 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1453 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1454 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1455 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1456 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1457 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1458 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1459 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1460 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1461 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1462 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1463 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1464 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1465 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1466 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1467 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1468 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1470 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1471 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1472 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1473 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1474 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1476 /* Shadow RAM related */
1477 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1478 #define I40E_SR_BUF_ALIGNMENT 4096
1479 #define I40E_SR_WORDS_IN_1KB 512
1480 /* Checksum should be calculated such that after adding all the words,
1481 * including the checksum word itself, the sum should be 0xBABA.
1483 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1485 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1487 enum i40e_switch_element_types {
1488 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1489 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1490 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1491 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1492 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1493 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1494 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1495 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1496 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1499 /* Supported EtherType filters */
1500 enum i40e_ether_type_index {
1501 I40E_ETHER_TYPE_1588 = 0,
1502 I40E_ETHER_TYPE_FIP = 1,
1503 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1504 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1505 I40E_ETHER_TYPE_LLDP = 4,
1506 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1507 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1508 I40E_ETHER_TYPE_QCN_CNM = 7,
1509 I40E_ETHER_TYPE_8021X = 8,
1510 I40E_ETHER_TYPE_ARP = 9,
1511 I40E_ETHER_TYPE_RSV1 = 10,
1512 I40E_ETHER_TYPE_RSV2 = 11,
1515 /* Filter context base size is 1K */
1516 #define I40E_HASH_FILTER_BASE_SIZE 1024
1517 /* Supported Hash filter values */
1518 enum i40e_hash_filter_size {
1519 I40E_HASH_FILTER_SIZE_1K = 0,
1520 I40E_HASH_FILTER_SIZE_2K = 1,
1521 I40E_HASH_FILTER_SIZE_4K = 2,
1522 I40E_HASH_FILTER_SIZE_8K = 3,
1523 I40E_HASH_FILTER_SIZE_16K = 4,
1524 I40E_HASH_FILTER_SIZE_32K = 5,
1525 I40E_HASH_FILTER_SIZE_64K = 6,
1526 I40E_HASH_FILTER_SIZE_128K = 7,
1527 I40E_HASH_FILTER_SIZE_256K = 8,
1528 I40E_HASH_FILTER_SIZE_512K = 9,
1529 I40E_HASH_FILTER_SIZE_1M = 10,
1532 /* DMA context base size is 0.5K */
1533 #define I40E_DMA_CNTX_BASE_SIZE 512
1534 /* Supported DMA context values */
1535 enum i40e_dma_cntx_size {
1536 I40E_DMA_CNTX_SIZE_512 = 0,
1537 I40E_DMA_CNTX_SIZE_1K = 1,
1538 I40E_DMA_CNTX_SIZE_2K = 2,
1539 I40E_DMA_CNTX_SIZE_4K = 3,
1540 I40E_DMA_CNTX_SIZE_8K = 4,
1541 I40E_DMA_CNTX_SIZE_16K = 5,
1542 I40E_DMA_CNTX_SIZE_32K = 6,
1543 I40E_DMA_CNTX_SIZE_64K = 7,
1544 I40E_DMA_CNTX_SIZE_128K = 8,
1545 I40E_DMA_CNTX_SIZE_256K = 9,
1548 /* Supported Hash look up table (LUT) sizes */
1549 enum i40e_hash_lut_size {
1550 I40E_HASH_LUT_SIZE_128 = 0,
1551 I40E_HASH_LUT_SIZE_512 = 1,
1554 /* Structure to hold a per PF filter control settings */
1555 struct i40e_filter_control_settings {
1556 /* number of PE Quad Hash filter buckets */
1557 enum i40e_hash_filter_size pe_filt_num;
1558 /* number of PE Quad Hash contexts */
1559 enum i40e_dma_cntx_size pe_cntx_num;
1560 /* number of FCoE filter buckets */
1561 enum i40e_hash_filter_size fcoe_filt_num;
1562 /* number of FCoE DDP contexts */
1563 enum i40e_dma_cntx_size fcoe_cntx_num;
1564 /* size of the Hash LUT */
1565 enum i40e_hash_lut_size hash_lut_size;
1566 /* enable FDIR filters for PF and its VFs */
1568 /* enable Ethertype filters for PF and its VFs */
1569 bool enable_ethtype;
1570 /* enable MAC/VLAN filters for PF and its VFs */
1571 bool enable_macvlan;
1574 /* Structure to hold device level control filter counts */
1575 struct i40e_control_filter_stats {
1576 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1577 u16 etype_used; /* Used perfect EtherType filters */
1578 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1579 u16 etype_free; /* Un-used perfect EtherType filters */
1582 enum i40e_reset_type {
1584 I40E_RESET_CORER = 1,
1585 I40E_RESET_GLOBR = 2,
1586 I40E_RESET_EMPR = 3,
1589 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1590 #define I40E_NVM_LLDP_CFG_PTR 0xD
1591 struct i40e_lldp_variables {
1601 /* Offsets into Alternate Ram */
1602 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1603 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1604 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1605 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1606 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1607 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1609 /* Alternate Ram Bandwidth Masks */
1610 #define I40E_ALT_BW_VALUE_MASK 0xFF
1611 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1612 #define I40E_ALT_BW_VALID_MASK 0x80000000
1614 /* RSS Hash Table Size */
1615 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1616 #endif /* _I40E_TYPE_H_ */