1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_eth_ctrl.h>
28 #include <rte_tailq.h>
29 #include <rte_hash_crc.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
46 #define I40E_CLEAR_PXE_WAIT_MS 200
48 /* Maximun number of capability elements */
49 #define I40E_MAX_CAP_ELE_NUM 128
51 /* Wait count and interval */
52 #define I40E_CHK_Q_ENA_COUNT 1000
53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
55 /* Maximun number of VSI */
56 #define I40E_MAX_NUM_VSIS (384UL)
58 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
60 /* Flow control default timer */
61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
63 /* Flow control enable fwd bit */
64 #define I40E_PRTMAC_FWD_CTRL 0x00000001
66 /* Receive Packet Buffer size */
67 #define I40E_RXPBSIZE (968 * 1024)
70 #define I40E_KILOSHIFT 10
72 /* Flow control default high water */
73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
75 /* Flow control default low water */
76 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Receive Average Packet Size in Byte*/
79 #define I40E_PACKET_AVERAGE_SIZE 128
81 /* Mask of PF interrupt causes */
82 #define I40E_PFINT_ICR0_ENA_MASK ( \
83 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
84 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
85 I40E_PFINT_ICR0_ENA_GRST_MASK | \
86 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
87 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
89 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
90 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
91 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
93 #define I40E_FLOW_TYPES ( \
94 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
95 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
96 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
99 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
104 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
106 /* Additional timesync values. */
107 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
108 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
109 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
110 #define I40E_PRTTSYN_TSYNENA 0x80000000
111 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
112 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 * Below are values for writing un-exposed registers suggested
118 /* Destination MAC address */
119 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
120 /* Source MAC address */
121 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
123 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
125 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
126 /* Single VLAN tag in the inner L2 header */
127 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
128 /* Source IPv4 address */
129 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
130 /* Destination IPv4 address */
131 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
132 /* Source IPv4 address for X722 */
133 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
134 /* Destination IPv4 address for X722 */
135 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
136 /* IPv4 Protocol for X722 */
137 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
138 /* IPv4 Time to Live for X722 */
139 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
140 /* IPv4 Type of Service (TOS) */
141 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
143 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
144 /* IPv4 Time to Live */
145 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
146 /* Source IPv6 address */
147 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
148 /* Destination IPv6 address */
149 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
150 /* IPv6 Traffic Class (TC) */
151 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
152 /* IPv6 Next Header */
153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
157 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
158 /* Destination L4 port */
159 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
160 /* SCTP verification tag */
161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
164 /* Source port of tunneling UDP */
165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
166 /* Destination port of tunneling UDP */
167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
168 /* UDP Tunneling ID, NVGRE/GRE key */
169 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
170 /* Last ether type */
171 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
172 /* Tunneling outer destination IPv4 address */
173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
174 /* Tunneling outer destination IPv6 address */
175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
176 /* 1st word of flex payload */
177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
178 /* 2nd word of flex payload */
179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
180 /* 3rd word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
182 /* 4th word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
184 /* 5th word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
186 /* 6th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
188 /* 7th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
190 /* 8th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
192 /* all 8 words flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
194 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
196 #define I40E_TRANSLATE_INSET 0
197 #define I40E_TRANSLATE_REG 1
199 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
200 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
201 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
202 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
204 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
206 /* PCI offset for querying capability */
207 #define PCI_DEV_CAP_REG 0xA4
208 /* PCI offset for enabling/disabling Extended Tag */
209 #define PCI_DEV_CTRL_REG 0xA8
210 /* Bit mask of Extended Tag capability */
211 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
212 /* Bit shift of Extended Tag enable/disable */
213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
214 /* Bit mask of Extended Tag enable/disable */
215 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
219 static int i40e_dev_configure(struct rte_eth_dev *dev);
220 static int i40e_dev_start(struct rte_eth_dev *dev);
221 static void i40e_dev_stop(struct rte_eth_dev *dev);
222 static void i40e_dev_close(struct rte_eth_dev *dev);
223 static int i40e_dev_reset(struct rte_eth_dev *dev);
224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
231 struct rte_eth_stats *stats);
232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
233 struct rte_eth_xstat *xstats, unsigned n);
234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
235 struct rte_eth_xstat_name *xstats_names,
237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
243 char *fw_version, size_t fw_size);
244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
245 struct rte_eth_dev_info *dev_info);
246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
250 enum rte_vlan_type vlan_type,
252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
260 struct rte_eth_fc_conf *fc_conf);
261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_pfc_conf *pfc_conf);
265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
266 struct ether_addr *mac_addr,
269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
271 struct rte_eth_rss_reta_entry64 *reta_conf,
273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
277 static int i40e_get_cap(struct i40e_hw *hw);
278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
279 static int i40e_pf_setup(struct i40e_pf *pf);
280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
284 bool offset_loaded, uint64_t *offset, uint64_t *stat);
285 static void i40e_stat_update_48(struct i40e_hw *hw,
291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
292 static void i40e_dev_interrupt_handler(void *param);
293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
294 uint32_t base, uint32_t num);
295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
301 static int i40e_veb_release(struct i40e_veb *veb);
302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
303 struct i40e_vsi *vsi);
304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
307 struct i40e_macvlan_filter *mv_f,
310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
312 struct rte_eth_rss_conf *rss_conf);
313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
316 struct rte_eth_udp_tunnel *udp_tunnel);
317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
324 enum rte_filter_type filter_type,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
330 static void i40e_configure_registers(struct i40e_hw *hw);
331 static void i40e_hw_init(struct rte_eth_dev *dev);
332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
340 struct rte_eth_mirror_conf *mirror_conf,
341 uint8_t sw_id, uint8_t on);
342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
347 struct timespec *timestamp,
349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp);
351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
358 const struct timespec *timestamp);
360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
365 static int i40e_get_regs(struct rte_eth_dev *dev,
366 struct rte_dev_reg_info *regs);
368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
371 struct rte_dev_eeprom_info *eeprom);
373 static int i40e_get_module_info(struct rte_eth_dev *dev,
374 struct rte_eth_dev_module_info *modinfo);
375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
376 struct rte_dev_eeprom_info *info);
378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
379 struct ether_addr *mac_addr);
381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
383 static int i40e_ethertype_filter_convert(
384 const struct rte_eth_ethertype_filter *input,
385 struct i40e_ethertype_filter *filter);
386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
387 struct i40e_ethertype_filter *filter);
389 static int i40e_tunnel_filter_convert(
390 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
391 struct i40e_tunnel_filter *tunnel_filter);
392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
398 static void i40e_filter_restore(struct i40e_pf *pf);
399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
401 int i40e_logtype_init;
402 int i40e_logtype_driver;
404 static const struct rte_pci_id pci_id_i40e_map[] = {
405 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
406 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
407 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
408 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
409 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
410 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
411 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
425 { .vendor_id = 0, /* sentinel */ },
428 static const struct eth_dev_ops i40e_eth_dev_ops = {
429 .dev_configure = i40e_dev_configure,
430 .dev_start = i40e_dev_start,
431 .dev_stop = i40e_dev_stop,
432 .dev_close = i40e_dev_close,
433 .dev_reset = i40e_dev_reset,
434 .promiscuous_enable = i40e_dev_promiscuous_enable,
435 .promiscuous_disable = i40e_dev_promiscuous_disable,
436 .allmulticast_enable = i40e_dev_allmulticast_enable,
437 .allmulticast_disable = i40e_dev_allmulticast_disable,
438 .dev_set_link_up = i40e_dev_set_link_up,
439 .dev_set_link_down = i40e_dev_set_link_down,
440 .link_update = i40e_dev_link_update,
441 .stats_get = i40e_dev_stats_get,
442 .xstats_get = i40e_dev_xstats_get,
443 .xstats_get_names = i40e_dev_xstats_get_names,
444 .stats_reset = i40e_dev_stats_reset,
445 .xstats_reset = i40e_dev_stats_reset,
446 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
447 .fw_version_get = i40e_fw_version_get,
448 .dev_infos_get = i40e_dev_info_get,
449 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
450 .vlan_filter_set = i40e_vlan_filter_set,
451 .vlan_tpid_set = i40e_vlan_tpid_set,
452 .vlan_offload_set = i40e_vlan_offload_set,
453 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
454 .vlan_pvid_set = i40e_vlan_pvid_set,
455 .rx_queue_start = i40e_dev_rx_queue_start,
456 .rx_queue_stop = i40e_dev_rx_queue_stop,
457 .tx_queue_start = i40e_dev_tx_queue_start,
458 .tx_queue_stop = i40e_dev_tx_queue_stop,
459 .rx_queue_setup = i40e_dev_rx_queue_setup,
460 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
461 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
462 .rx_queue_release = i40e_dev_rx_queue_release,
463 .rx_queue_count = i40e_dev_rx_queue_count,
464 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
465 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
466 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
467 .tx_queue_setup = i40e_dev_tx_queue_setup,
468 .tx_queue_release = i40e_dev_tx_queue_release,
469 .dev_led_on = i40e_dev_led_on,
470 .dev_led_off = i40e_dev_led_off,
471 .flow_ctrl_get = i40e_flow_ctrl_get,
472 .flow_ctrl_set = i40e_flow_ctrl_set,
473 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
474 .mac_addr_add = i40e_macaddr_add,
475 .mac_addr_remove = i40e_macaddr_remove,
476 .reta_update = i40e_dev_rss_reta_update,
477 .reta_query = i40e_dev_rss_reta_query,
478 .rss_hash_update = i40e_dev_rss_hash_update,
479 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
480 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
481 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
482 .filter_ctrl = i40e_dev_filter_ctrl,
483 .rxq_info_get = i40e_rxq_info_get,
484 .txq_info_get = i40e_txq_info_get,
485 .mirror_rule_set = i40e_mirror_rule_set,
486 .mirror_rule_reset = i40e_mirror_rule_reset,
487 .timesync_enable = i40e_timesync_enable,
488 .timesync_disable = i40e_timesync_disable,
489 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
490 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
491 .get_dcb_info = i40e_dev_get_dcb_info,
492 .timesync_adjust_time = i40e_timesync_adjust_time,
493 .timesync_read_time = i40e_timesync_read_time,
494 .timesync_write_time = i40e_timesync_write_time,
495 .get_reg = i40e_get_regs,
496 .get_eeprom_length = i40e_get_eeprom_length,
497 .get_eeprom = i40e_get_eeprom,
498 .get_module_info = i40e_get_module_info,
499 .get_module_eeprom = i40e_get_module_eeprom,
500 .mac_addr_set = i40e_set_default_mac_addr,
501 .mtu_set = i40e_dev_mtu_set,
502 .tm_ops_get = i40e_tm_ops_get,
505 /* store statistics names and its offset in stats structure */
506 struct rte_i40e_xstats_name_off {
507 char name[RTE_ETH_XSTATS_NAME_SIZE];
511 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
512 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
513 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
514 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
515 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
516 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
517 rx_unknown_protocol)},
518 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
519 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
520 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
521 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
524 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
525 sizeof(rte_i40e_stats_strings[0]))
527 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
528 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
529 tx_dropped_link_down)},
530 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
531 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
533 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
534 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
536 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
538 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
540 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
541 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
542 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
543 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
544 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
545 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
547 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
549 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
551 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
553 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
555 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
557 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
559 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
561 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
562 mac_short_packet_dropped)},
563 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
565 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
566 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
567 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
569 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
571 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
573 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
575 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
577 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_flow_director_atr_match_packets",
580 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
581 {"rx_flow_director_sb_match_packets",
582 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
583 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
585 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
587 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
589 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
593 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
594 sizeof(rte_i40e_hw_port_strings[0]))
596 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
597 {"xon_packets", offsetof(struct i40e_hw_port_stats,
599 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
603 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
604 sizeof(rte_i40e_rxq_prio_strings[0]))
606 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
607 {"xon_packets", offsetof(struct i40e_hw_port_stats,
609 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
611 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
612 priority_xon_2_xoff)},
615 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
616 sizeof(rte_i40e_txq_prio_strings[0]))
619 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
620 struct rte_pci_device *pci_dev)
622 char name[RTE_ETH_NAME_MAX_LEN];
623 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
626 if (pci_dev->device.devargs) {
627 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
633 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
634 sizeof(struct i40e_adapter),
635 eth_dev_pci_specific_init, pci_dev,
636 eth_i40e_dev_init, NULL);
638 if (retval || eth_da.nb_representor_ports < 1)
641 /* probe VF representor ports */
642 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
643 pci_dev->device.name);
645 if (pf_ethdev == NULL)
648 for (i = 0; i < eth_da.nb_representor_ports; i++) {
649 struct i40e_vf_representor representor = {
650 .vf_id = eth_da.representor_ports[i],
651 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
652 pf_ethdev->data->dev_private)->switch_domain_id,
653 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
654 pf_ethdev->data->dev_private)
657 /* representor port net_bdf_port */
658 snprintf(name, sizeof(name), "net_%s_representor_%d",
659 pci_dev->device.name, eth_da.representor_ports[i]);
661 retval = rte_eth_dev_create(&pci_dev->device, name,
662 sizeof(struct i40e_vf_representor), NULL, NULL,
663 i40e_vf_representor_init, &representor);
666 PMD_DRV_LOG(ERR, "failed to create i40e vf "
667 "representor %s.", name);
673 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
675 struct rte_eth_dev *ethdev;
677 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
682 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
683 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
685 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
688 static struct rte_pci_driver rte_i40e_pmd = {
689 .id_table = pci_id_i40e_map,
690 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
691 RTE_PCI_DRV_IOVA_AS_VA,
692 .probe = eth_i40e_pci_probe,
693 .remove = eth_i40e_pci_remove,
697 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
700 uint32_t ori_reg_val;
701 struct rte_eth_dev *dev;
703 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
704 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
705 i40e_write_rx_ctl(hw, reg_addr, reg_val);
706 if (ori_reg_val != reg_val)
708 "i40e device %s changed global register [0x%08x]."
709 " original: 0x%08x, new: 0x%08x",
710 dev->device->name, reg_addr, ori_reg_val, reg_val);
713 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
714 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
715 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
717 #ifndef I40E_GLQF_ORT
718 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
720 #ifndef I40E_GLQF_PIT
721 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
723 #ifndef I40E_GLQF_L3_MAP
724 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
727 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
730 * Initialize registers for parsing packet type of QinQ
731 * This should be removed from code once proper
732 * configuration API is added to avoid configuration conflicts
733 * between ports of the same device.
735 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
736 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
739 static inline void i40e_config_automask(struct i40e_pf *pf)
741 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
744 /* INTENA flag is not auto-cleared for interrupt */
745 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
746 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
747 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
749 /* If support multi-driver, PF will use INT0. */
750 if (!pf->support_multi_driver)
751 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
753 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
756 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
759 * Add a ethertype filter to drop all flow control frames transmitted
763 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
765 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
766 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
767 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
768 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
771 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
772 I40E_FLOW_CONTROL_ETHERTYPE, flags,
773 pf->main_vsi_seid, 0,
777 "Failed to add filter to drop flow control frames from VSIs.");
781 floating_veb_list_handler(__rte_unused const char *key,
782 const char *floating_veb_value,
786 unsigned int count = 0;
789 bool *vf_floating_veb = opaque;
791 while (isblank(*floating_veb_value))
792 floating_veb_value++;
794 /* Reset floating VEB configuration for VFs */
795 for (idx = 0; idx < I40E_MAX_VF; idx++)
796 vf_floating_veb[idx] = false;
800 while (isblank(*floating_veb_value))
801 floating_veb_value++;
802 if (*floating_veb_value == '\0')
805 idx = strtoul(floating_veb_value, &end, 10);
806 if (errno || end == NULL)
808 while (isblank(*end))
812 } else if ((*end == ';') || (*end == '\0')) {
814 if (min == I40E_MAX_VF)
816 if (max >= I40E_MAX_VF)
817 max = I40E_MAX_VF - 1;
818 for (idx = min; idx <= max; idx++) {
819 vf_floating_veb[idx] = true;
826 floating_veb_value = end + 1;
827 } while (*end != '\0');
836 config_vf_floating_veb(struct rte_devargs *devargs,
837 uint16_t floating_veb,
838 bool *vf_floating_veb)
840 struct rte_kvargs *kvlist;
842 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
846 /* All the VFs attach to the floating VEB by default
847 * when the floating VEB is enabled.
849 for (i = 0; i < I40E_MAX_VF; i++)
850 vf_floating_veb[i] = true;
855 kvlist = rte_kvargs_parse(devargs->args, NULL);
859 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
860 rte_kvargs_free(kvlist);
863 /* When the floating_veb_list parameter exists, all the VFs
864 * will attach to the legacy VEB firstly, then configure VFs
865 * to the floating VEB according to the floating_veb_list.
867 if (rte_kvargs_process(kvlist, floating_veb_list,
868 floating_veb_list_handler,
869 vf_floating_veb) < 0) {
870 rte_kvargs_free(kvlist);
873 rte_kvargs_free(kvlist);
877 i40e_check_floating_handler(__rte_unused const char *key,
879 __rte_unused void *opaque)
881 if (strcmp(value, "1"))
888 is_floating_veb_supported(struct rte_devargs *devargs)
890 struct rte_kvargs *kvlist;
891 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
896 kvlist = rte_kvargs_parse(devargs->args, NULL);
900 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
901 rte_kvargs_free(kvlist);
904 /* Floating VEB is enabled when there's key-value:
905 * enable_floating_veb=1
907 if (rte_kvargs_process(kvlist, floating_veb_key,
908 i40e_check_floating_handler, NULL) < 0) {
909 rte_kvargs_free(kvlist);
912 rte_kvargs_free(kvlist);
918 config_floating_veb(struct rte_eth_dev *dev)
920 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
921 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
922 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
924 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
926 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
928 is_floating_veb_supported(pci_dev->device.devargs);
929 config_vf_floating_veb(pci_dev->device.devargs,
931 pf->floating_veb_list);
933 pf->floating_veb = false;
937 #define I40E_L2_TAGS_S_TAG_SHIFT 1
938 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
941 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
943 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
944 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
945 char ethertype_hash_name[RTE_HASH_NAMESIZE];
948 struct rte_hash_parameters ethertype_hash_params = {
949 .name = ethertype_hash_name,
950 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
951 .key_len = sizeof(struct i40e_ethertype_filter_input),
952 .hash_func = rte_hash_crc,
953 .hash_func_init_val = 0,
954 .socket_id = rte_socket_id(),
957 /* Initialize ethertype filter rule list and hash */
958 TAILQ_INIT(ðertype_rule->ethertype_list);
959 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
960 "ethertype_%s", dev->device->name);
961 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
962 if (!ethertype_rule->hash_table) {
963 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
966 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
967 sizeof(struct i40e_ethertype_filter *) *
968 I40E_MAX_ETHERTYPE_FILTER_NUM,
970 if (!ethertype_rule->hash_map) {
972 "Failed to allocate memory for ethertype hash map!");
974 goto err_ethertype_hash_map_alloc;
979 err_ethertype_hash_map_alloc:
980 rte_hash_free(ethertype_rule->hash_table);
986 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
988 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
989 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
990 char tunnel_hash_name[RTE_HASH_NAMESIZE];
993 struct rte_hash_parameters tunnel_hash_params = {
994 .name = tunnel_hash_name,
995 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
996 .key_len = sizeof(struct i40e_tunnel_filter_input),
997 .hash_func = rte_hash_crc,
998 .hash_func_init_val = 0,
999 .socket_id = rte_socket_id(),
1002 /* Initialize tunnel filter rule list and hash */
1003 TAILQ_INIT(&tunnel_rule->tunnel_list);
1004 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1005 "tunnel_%s", dev->device->name);
1006 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1007 if (!tunnel_rule->hash_table) {
1008 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1011 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1012 sizeof(struct i40e_tunnel_filter *) *
1013 I40E_MAX_TUNNEL_FILTER_NUM,
1015 if (!tunnel_rule->hash_map) {
1017 "Failed to allocate memory for tunnel hash map!");
1019 goto err_tunnel_hash_map_alloc;
1024 err_tunnel_hash_map_alloc:
1025 rte_hash_free(tunnel_rule->hash_table);
1031 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1033 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1034 struct i40e_fdir_info *fdir_info = &pf->fdir;
1035 char fdir_hash_name[RTE_HASH_NAMESIZE];
1038 struct rte_hash_parameters fdir_hash_params = {
1039 .name = fdir_hash_name,
1040 .entries = I40E_MAX_FDIR_FILTER_NUM,
1041 .key_len = sizeof(struct i40e_fdir_input),
1042 .hash_func = rte_hash_crc,
1043 .hash_func_init_val = 0,
1044 .socket_id = rte_socket_id(),
1047 /* Initialize flow director filter rule list and hash */
1048 TAILQ_INIT(&fdir_info->fdir_list);
1049 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1050 "fdir_%s", dev->device->name);
1051 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1052 if (!fdir_info->hash_table) {
1053 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1056 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1057 sizeof(struct i40e_fdir_filter *) *
1058 I40E_MAX_FDIR_FILTER_NUM,
1060 if (!fdir_info->hash_map) {
1062 "Failed to allocate memory for fdir hash map!");
1064 goto err_fdir_hash_map_alloc;
1068 err_fdir_hash_map_alloc:
1069 rte_hash_free(fdir_info->hash_table);
1075 i40e_init_customized_info(struct i40e_pf *pf)
1079 /* Initialize customized pctype */
1080 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1081 pf->customized_pctype[i].index = i;
1082 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1083 pf->customized_pctype[i].valid = false;
1086 pf->gtp_support = false;
1090 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1092 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1094 struct i40e_queue_regions *info = &pf->queue_region;
1097 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1098 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1100 memset(info, 0, sizeof(struct i40e_queue_regions));
1103 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
1106 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1111 unsigned long support_multi_driver;
1114 pf = (struct i40e_pf *)opaque;
1117 support_multi_driver = strtoul(value, &end, 10);
1118 if (errno != 0 || end == value || *end != 0) {
1119 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1123 if (support_multi_driver == 1 || support_multi_driver == 0)
1124 pf->support_multi_driver = (bool)support_multi_driver;
1126 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1127 "enable global configuration by default."
1128 ETH_I40E_SUPPORT_MULTI_DRIVER);
1133 i40e_support_multi_driver(struct rte_eth_dev *dev)
1135 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1136 static const char *const valid_keys[] = {
1137 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1138 struct rte_kvargs *kvlist;
1140 /* Enable global configuration by default */
1141 pf->support_multi_driver = false;
1143 if (!dev->device->devargs)
1146 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1150 if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1151 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1152 "the first invalid or last valid one is used !",
1153 ETH_I40E_SUPPORT_MULTI_DRIVER);
1155 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1156 i40e_parse_multi_drv_handler, pf) < 0) {
1157 rte_kvargs_free(kvlist);
1161 rte_kvargs_free(kvlist);
1166 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1167 uint32_t reg_addr, uint64_t reg_val,
1168 struct i40e_asq_cmd_details *cmd_details)
1170 uint64_t ori_reg_val;
1171 struct rte_eth_dev *dev;
1174 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1175 if (ret != I40E_SUCCESS) {
1177 "Fail to debug read from 0x%08x",
1181 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1183 if (ori_reg_val != reg_val)
1184 PMD_DRV_LOG(WARNING,
1185 "i40e device %s changed global register [0x%08x]."
1186 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1187 dev->device->name, reg_addr, ori_reg_val, reg_val);
1189 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1193 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1195 struct rte_pci_device *pci_dev;
1196 struct rte_intr_handle *intr_handle;
1197 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1198 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1199 struct i40e_vsi *vsi;
1202 uint8_t aq_fail = 0;
1204 PMD_INIT_FUNC_TRACE();
1206 dev->dev_ops = &i40e_eth_dev_ops;
1207 dev->rx_pkt_burst = i40e_recv_pkts;
1208 dev->tx_pkt_burst = i40e_xmit_pkts;
1209 dev->tx_pkt_prepare = i40e_prep_pkts;
1211 /* for secondary processes, we don't initialise any further as primary
1212 * has already done this work. Only check we don't need a different
1214 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1215 i40e_set_rx_function(dev);
1216 i40e_set_tx_function(dev);
1219 i40e_set_default_ptype_table(dev);
1220 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1221 intr_handle = &pci_dev->intr_handle;
1223 rte_eth_copy_pci_info(dev, pci_dev);
1225 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1226 pf->adapter->eth_dev = dev;
1227 pf->dev_data = dev->data;
1229 hw->back = I40E_PF_TO_ADAPTER(pf);
1230 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1233 "Hardware is not available, as address is NULL");
1237 hw->vendor_id = pci_dev->id.vendor_id;
1238 hw->device_id = pci_dev->id.device_id;
1239 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1240 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1241 hw->bus.device = pci_dev->addr.devid;
1242 hw->bus.func = pci_dev->addr.function;
1243 hw->adapter_stopped = 0;
1245 /* Check if need to support multi-driver */
1246 i40e_support_multi_driver(dev);
1248 /* Make sure all is clean before doing PF reset */
1251 /* Initialize the hardware */
1254 /* Reset here to make sure all is clean for each PF */
1255 ret = i40e_pf_reset(hw);
1257 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1261 /* Initialize the shared code (base driver) */
1262 ret = i40e_init_shared_code(hw);
1264 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1268 i40e_config_automask(pf);
1270 i40e_set_default_pctype_table(dev);
1273 * To work around the NVM issue, initialize registers
1274 * for packet type of QinQ by software.
1275 * It should be removed once issues are fixed in NVM.
1277 if (!pf->support_multi_driver)
1278 i40e_GLQF_reg_init(hw);
1280 /* Initialize the input set for filters (hash and fd) to default value */
1281 i40e_filter_input_set_init(pf);
1283 /* Initialize the parameters for adminq */
1284 i40e_init_adminq_parameter(hw);
1285 ret = i40e_init_adminq(hw);
1286 if (ret != I40E_SUCCESS) {
1287 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1290 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1291 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1292 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1293 ((hw->nvm.version >> 12) & 0xf),
1294 ((hw->nvm.version >> 4) & 0xff),
1295 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1297 /* initialise the L3_MAP register */
1298 if (!pf->support_multi_driver) {
1299 ret = i40e_aq_debug_write_global_register(hw,
1300 I40E_GLQF_L3_MAP(40),
1303 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1306 "Global register 0x%08x is changed with 0x28",
1307 I40E_GLQF_L3_MAP(40));
1310 /* Need the special FW version to support floating VEB */
1311 config_floating_veb(dev);
1312 /* Clear PXE mode */
1313 i40e_clear_pxe_mode(hw);
1314 i40e_dev_sync_phy_type(hw);
1317 * On X710, performance number is far from the expectation on recent
1318 * firmware versions. The fix for this issue may not be integrated in
1319 * the following firmware version. So the workaround in software driver
1320 * is needed. It needs to modify the initial values of 3 internal only
1321 * registers. Note that the workaround can be removed when it is fixed
1322 * in firmware in the future.
1324 i40e_configure_registers(hw);
1326 /* Get hw capabilities */
1327 ret = i40e_get_cap(hw);
1328 if (ret != I40E_SUCCESS) {
1329 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1330 goto err_get_capabilities;
1333 /* Initialize parameters for PF */
1334 ret = i40e_pf_parameter_init(dev);
1336 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1337 goto err_parameter_init;
1340 /* Initialize the queue management */
1341 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1343 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1344 goto err_qp_pool_init;
1346 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1347 hw->func_caps.num_msix_vectors - 1);
1349 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1350 goto err_msix_pool_init;
1353 /* Initialize lan hmc */
1354 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1355 hw->func_caps.num_rx_qp, 0, 0);
1356 if (ret != I40E_SUCCESS) {
1357 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1358 goto err_init_lan_hmc;
1361 /* Configure lan hmc */
1362 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1363 if (ret != I40E_SUCCESS) {
1364 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1365 goto err_configure_lan_hmc;
1368 /* Get and check the mac address */
1369 i40e_get_mac_addr(hw, hw->mac.addr);
1370 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1371 PMD_INIT_LOG(ERR, "mac address is not valid");
1373 goto err_get_mac_addr;
1375 /* Copy the permanent MAC address */
1376 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1377 (struct ether_addr *) hw->mac.perm_addr);
1379 /* Disable flow control */
1380 hw->fc.requested_mode = I40E_FC_NONE;
1381 i40e_set_fc(hw, &aq_fail, TRUE);
1383 /* Set the global registers with default ether type value */
1384 if (!pf->support_multi_driver) {
1385 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1387 if (ret != I40E_SUCCESS) {
1389 "Failed to set the default outer "
1391 goto err_setup_pf_switch;
1395 /* PF setup, which includes VSI setup */
1396 ret = i40e_pf_setup(pf);
1398 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1399 goto err_setup_pf_switch;
1402 /* reset all stats of the device, including pf and main vsi */
1403 i40e_dev_stats_reset(dev);
1407 /* Disable double vlan by default */
1408 i40e_vsi_config_double_vlan(vsi, FALSE);
1410 /* Disable S-TAG identification when floating_veb is disabled */
1411 if (!pf->floating_veb) {
1412 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1413 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1414 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1415 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1419 if (!vsi->max_macaddrs)
1420 len = ETHER_ADDR_LEN;
1422 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1424 /* Should be after VSI initialized */
1425 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1426 if (!dev->data->mac_addrs) {
1428 "Failed to allocated memory for storing mac address");
1431 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1432 &dev->data->mac_addrs[0]);
1434 /* Init dcb to sw mode by default */
1435 ret = i40e_dcb_init_configure(dev, TRUE);
1436 if (ret != I40E_SUCCESS) {
1437 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1438 pf->flags &= ~I40E_FLAG_DCB;
1440 /* Update HW struct after DCB configuration */
1443 /* initialize pf host driver to setup SRIOV resource if applicable */
1444 i40e_pf_host_init(dev);
1446 /* register callback func to eal lib */
1447 rte_intr_callback_register(intr_handle,
1448 i40e_dev_interrupt_handler, dev);
1450 /* configure and enable device interrupt */
1451 i40e_pf_config_irq0(hw, TRUE);
1452 i40e_pf_enable_irq0(hw);
1454 /* enable uio intr after callback register */
1455 rte_intr_enable(intr_handle);
1457 /* By default disable flexible payload in global configuration */
1458 if (!pf->support_multi_driver)
1459 i40e_flex_payload_reg_set_default(hw);
1462 * Add an ethertype filter to drop all flow control frames transmitted
1463 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1466 i40e_add_tx_flow_control_drop_filter(pf);
1468 /* Set the max frame size to 0x2600 by default,
1469 * in case other drivers changed the default value.
1471 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1473 /* initialize mirror rule list */
1474 TAILQ_INIT(&pf->mirror_list);
1476 /* initialize Traffic Manager configuration */
1477 i40e_tm_conf_init(dev);
1479 /* Initialize customized information */
1480 i40e_init_customized_info(pf);
1482 ret = i40e_init_ethtype_filter_list(dev);
1484 goto err_init_ethtype_filter_list;
1485 ret = i40e_init_tunnel_filter_list(dev);
1487 goto err_init_tunnel_filter_list;
1488 ret = i40e_init_fdir_filter_list(dev);
1490 goto err_init_fdir_filter_list;
1492 /* initialize queue region configuration */
1493 i40e_init_queue_region_conf(dev);
1495 /* initialize rss configuration from rte_flow */
1496 memset(&pf->rss_info, 0,
1497 sizeof(struct i40e_rte_flow_rss_conf));
1501 err_init_fdir_filter_list:
1502 rte_free(pf->tunnel.hash_table);
1503 rte_free(pf->tunnel.hash_map);
1504 err_init_tunnel_filter_list:
1505 rte_free(pf->ethertype.hash_table);
1506 rte_free(pf->ethertype.hash_map);
1507 err_init_ethtype_filter_list:
1508 rte_free(dev->data->mac_addrs);
1510 i40e_vsi_release(pf->main_vsi);
1511 err_setup_pf_switch:
1513 err_configure_lan_hmc:
1514 (void)i40e_shutdown_lan_hmc(hw);
1516 i40e_res_pool_destroy(&pf->msix_pool);
1518 i40e_res_pool_destroy(&pf->qp_pool);
1521 err_get_capabilities:
1522 (void)i40e_shutdown_adminq(hw);
1528 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1530 struct i40e_ethertype_filter *p_ethertype;
1531 struct i40e_ethertype_rule *ethertype_rule;
1533 ethertype_rule = &pf->ethertype;
1534 /* Remove all ethertype filter rules and hash */
1535 if (ethertype_rule->hash_map)
1536 rte_free(ethertype_rule->hash_map);
1537 if (ethertype_rule->hash_table)
1538 rte_hash_free(ethertype_rule->hash_table);
1540 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1541 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1542 p_ethertype, rules);
1543 rte_free(p_ethertype);
1548 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1550 struct i40e_tunnel_filter *p_tunnel;
1551 struct i40e_tunnel_rule *tunnel_rule;
1553 tunnel_rule = &pf->tunnel;
1554 /* Remove all tunnel director rules and hash */
1555 if (tunnel_rule->hash_map)
1556 rte_free(tunnel_rule->hash_map);
1557 if (tunnel_rule->hash_table)
1558 rte_hash_free(tunnel_rule->hash_table);
1560 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1561 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1567 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1569 struct i40e_fdir_filter *p_fdir;
1570 struct i40e_fdir_info *fdir_info;
1572 fdir_info = &pf->fdir;
1573 /* Remove all flow director rules and hash */
1574 if (fdir_info->hash_map)
1575 rte_free(fdir_info->hash_map);
1576 if (fdir_info->hash_table)
1577 rte_hash_free(fdir_info->hash_table);
1579 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1580 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1585 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1588 * Disable by default flexible payload
1589 * for corresponding L2/L3/L4 layers.
1591 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1592 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1593 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1597 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1600 struct rte_pci_device *pci_dev;
1601 struct rte_intr_handle *intr_handle;
1603 struct i40e_filter_control_settings settings;
1604 struct rte_flow *p_flow;
1606 uint8_t aq_fail = 0;
1609 PMD_INIT_FUNC_TRACE();
1611 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1614 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1615 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1617 intr_handle = &pci_dev->intr_handle;
1619 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1621 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1623 if (hw->adapter_stopped == 0)
1624 i40e_dev_close(dev);
1626 dev->dev_ops = NULL;
1627 dev->rx_pkt_burst = NULL;
1628 dev->tx_pkt_burst = NULL;
1630 /* Clear PXE mode */
1631 i40e_clear_pxe_mode(hw);
1633 /* Unconfigure filter control */
1634 memset(&settings, 0, sizeof(settings));
1635 ret = i40e_set_filter_control(hw, &settings);
1637 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1640 /* Disable flow control */
1641 hw->fc.requested_mode = I40E_FC_NONE;
1642 i40e_set_fc(hw, &aq_fail, TRUE);
1644 /* uninitialize pf host driver */
1645 i40e_pf_host_uninit(dev);
1647 rte_free(dev->data->mac_addrs);
1648 dev->data->mac_addrs = NULL;
1650 /* disable uio intr before callback unregister */
1651 rte_intr_disable(intr_handle);
1653 /* unregister callback func to eal lib */
1655 ret = rte_intr_callback_unregister(intr_handle,
1656 i40e_dev_interrupt_handler, dev);
1659 } else if (ret != -EAGAIN) {
1661 "intr callback unregister failed: %d",
1665 i40e_msec_delay(500);
1666 } while (retries++ < 5);
1668 i40e_rm_ethtype_filter_list(pf);
1669 i40e_rm_tunnel_filter_list(pf);
1670 i40e_rm_fdir_filter_list(pf);
1672 /* Remove all flows */
1673 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1674 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1678 /* Remove all Traffic Manager configuration */
1679 i40e_tm_conf_uninit(dev);
1685 i40e_dev_configure(struct rte_eth_dev *dev)
1687 struct i40e_adapter *ad =
1688 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1689 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1690 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1694 ret = i40e_dev_sync_phy_type(hw);
1698 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1699 * bulk allocation or vector Rx preconditions we will reset it.
1701 ad->rx_bulk_alloc_allowed = true;
1702 ad->rx_vec_allowed = true;
1703 ad->tx_simple_allowed = true;
1704 ad->tx_vec_allowed = true;
1706 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1707 ret = i40e_fdir_setup(pf);
1708 if (ret != I40E_SUCCESS) {
1709 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1712 ret = i40e_fdir_configure(dev);
1714 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1718 i40e_fdir_teardown(pf);
1720 ret = i40e_dev_init_vlan(dev);
1725 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1726 * RSS setting have different requirements.
1727 * General PMD driver call sequence are NIC init, configure,
1728 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1729 * will try to lookup the VSI that specific queue belongs to if VMDQ
1730 * applicable. So, VMDQ setting has to be done before
1731 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1732 * For RSS setting, it will try to calculate actual configured RX queue
1733 * number, which will be available after rx_queue_setup(). dev_start()
1734 * function is good to place RSS setup.
1736 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1737 ret = i40e_vmdq_setup(dev);
1742 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1743 ret = i40e_dcb_setup(dev);
1745 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1750 TAILQ_INIT(&pf->flow_list);
1755 /* need to release vmdq resource if exists */
1756 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1757 i40e_vsi_release(pf->vmdq[i].vsi);
1758 pf->vmdq[i].vsi = NULL;
1763 /* need to release fdir resource if exists */
1764 i40e_fdir_teardown(pf);
1769 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1771 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1772 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1773 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1774 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1775 uint16_t msix_vect = vsi->msix_intr;
1778 for (i = 0; i < vsi->nb_qps; i++) {
1779 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1780 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1784 if (vsi->type != I40E_VSI_SRIOV) {
1785 if (!rte_intr_allow_others(intr_handle)) {
1786 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1787 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1789 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1792 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1793 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1795 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1800 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1801 vsi->user_param + (msix_vect - 1);
1803 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1804 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1806 I40E_WRITE_FLUSH(hw);
1810 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1811 int base_queue, int nb_queue,
1816 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1817 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1819 /* Bind all RX queues to allocated MSIX interrupt */
1820 for (i = 0; i < nb_queue; i++) {
1821 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1822 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1823 ((base_queue + i + 1) <<
1824 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1825 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1826 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1828 if (i == nb_queue - 1)
1829 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1830 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1833 /* Write first RX queue to Link list register as the head element */
1834 if (vsi->type != I40E_VSI_SRIOV) {
1836 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
1837 pf->support_multi_driver);
1839 if (msix_vect == I40E_MISC_VEC_ID) {
1840 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1842 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1844 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1846 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1849 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1851 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1853 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1855 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1862 if (msix_vect == I40E_MISC_VEC_ID) {
1864 I40E_VPINT_LNKLST0(vsi->user_param),
1866 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1868 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1870 /* num_msix_vectors_vf needs to minus irq0 */
1871 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1872 vsi->user_param + (msix_vect - 1);
1874 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1876 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1878 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1882 I40E_WRITE_FLUSH(hw);
1886 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1888 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1889 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1890 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1891 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1892 uint16_t msix_vect = vsi->msix_intr;
1893 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1894 uint16_t queue_idx = 0;
1898 for (i = 0; i < vsi->nb_qps; i++) {
1899 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1900 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1903 /* VF bind interrupt */
1904 if (vsi->type == I40E_VSI_SRIOV) {
1905 __vsi_queues_bind_intr(vsi, msix_vect,
1906 vsi->base_queue, vsi->nb_qps,
1911 /* PF & VMDq bind interrupt */
1912 if (rte_intr_dp_is_en(intr_handle)) {
1913 if (vsi->type == I40E_VSI_MAIN) {
1916 } else if (vsi->type == I40E_VSI_VMDQ2) {
1917 struct i40e_vsi *main_vsi =
1918 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1919 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1924 for (i = 0; i < vsi->nb_used_qps; i++) {
1926 if (!rte_intr_allow_others(intr_handle))
1927 /* allow to share MISC_VEC_ID */
1928 msix_vect = I40E_MISC_VEC_ID;
1930 /* no enough msix_vect, map all to one */
1931 __vsi_queues_bind_intr(vsi, msix_vect,
1932 vsi->base_queue + i,
1933 vsi->nb_used_qps - i,
1935 for (; !!record && i < vsi->nb_used_qps; i++)
1936 intr_handle->intr_vec[queue_idx + i] =
1940 /* 1:1 queue/msix_vect mapping */
1941 __vsi_queues_bind_intr(vsi, msix_vect,
1942 vsi->base_queue + i, 1,
1945 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1953 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1955 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1956 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1957 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1958 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1959 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1960 uint16_t msix_intr, i;
1962 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1963 for (i = 0; i < vsi->nb_msix; i++) {
1964 msix_intr = vsi->msix_intr + i;
1965 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1966 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1967 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1968 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1971 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1972 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1973 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1974 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1976 I40E_WRITE_FLUSH(hw);
1980 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1982 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1983 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1984 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1985 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1986 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1987 uint16_t msix_intr, i;
1989 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1990 for (i = 0; i < vsi->nb_msix; i++) {
1991 msix_intr = vsi->msix_intr + i;
1992 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1993 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1996 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1997 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1999 I40E_WRITE_FLUSH(hw);
2002 static inline uint8_t
2003 i40e_parse_link_speeds(uint16_t link_speeds)
2005 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2007 if (link_speeds & ETH_LINK_SPEED_40G)
2008 link_speed |= I40E_LINK_SPEED_40GB;
2009 if (link_speeds & ETH_LINK_SPEED_25G)
2010 link_speed |= I40E_LINK_SPEED_25GB;
2011 if (link_speeds & ETH_LINK_SPEED_20G)
2012 link_speed |= I40E_LINK_SPEED_20GB;
2013 if (link_speeds & ETH_LINK_SPEED_10G)
2014 link_speed |= I40E_LINK_SPEED_10GB;
2015 if (link_speeds & ETH_LINK_SPEED_1G)
2016 link_speed |= I40E_LINK_SPEED_1GB;
2017 if (link_speeds & ETH_LINK_SPEED_100M)
2018 link_speed |= I40E_LINK_SPEED_100MB;
2024 i40e_phy_conf_link(struct i40e_hw *hw,
2026 uint8_t force_speed,
2029 enum i40e_status_code status;
2030 struct i40e_aq_get_phy_abilities_resp phy_ab;
2031 struct i40e_aq_set_phy_config phy_conf;
2032 enum i40e_aq_phy_type cnt;
2033 uint32_t phy_type_mask = 0;
2035 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2036 I40E_AQ_PHY_FLAG_PAUSE_RX |
2037 I40E_AQ_PHY_FLAG_PAUSE_RX |
2038 I40E_AQ_PHY_FLAG_LOW_POWER;
2039 const uint8_t advt = I40E_LINK_SPEED_40GB |
2040 I40E_LINK_SPEED_25GB |
2041 I40E_LINK_SPEED_10GB |
2042 I40E_LINK_SPEED_1GB |
2043 I40E_LINK_SPEED_100MB;
2047 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2052 /* If link already up, no need to set up again */
2053 if (is_up && phy_ab.phy_type != 0)
2054 return I40E_SUCCESS;
2056 memset(&phy_conf, 0, sizeof(phy_conf));
2058 /* bits 0-2 use the values from get_phy_abilities_resp */
2060 abilities |= phy_ab.abilities & mask;
2062 /* update ablities and speed */
2063 if (abilities & I40E_AQ_PHY_AN_ENABLED)
2064 phy_conf.link_speed = advt;
2066 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
2068 phy_conf.abilities = abilities;
2072 /* PHY type mask needs to include each type except PHY type extension */
2073 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2074 phy_type_mask |= 1 << cnt;
2076 /* use get_phy_abilities_resp value for the rest */
2077 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2078 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2079 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2080 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2081 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2082 phy_conf.eee_capability = phy_ab.eee_capability;
2083 phy_conf.eeer = phy_ab.eeer_val;
2084 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2086 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2087 phy_ab.abilities, phy_ab.link_speed);
2088 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2089 phy_conf.abilities, phy_conf.link_speed);
2091 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2095 return I40E_SUCCESS;
2099 i40e_apply_link_speed(struct rte_eth_dev *dev)
2102 uint8_t abilities = 0;
2103 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2104 struct rte_eth_conf *conf = &dev->data->dev_conf;
2106 speed = i40e_parse_link_speeds(conf->link_speeds);
2107 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2108 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2109 abilities |= I40E_AQ_PHY_AN_ENABLED;
2110 abilities |= I40E_AQ_PHY_LINK_ENABLED;
2112 return i40e_phy_conf_link(hw, abilities, speed, true);
2116 i40e_dev_start(struct rte_eth_dev *dev)
2118 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2119 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120 struct i40e_vsi *main_vsi = pf->main_vsi;
2122 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2123 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2124 uint32_t intr_vector = 0;
2125 struct i40e_vsi *vsi;
2127 hw->adapter_stopped = 0;
2129 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2131 "Invalid link_speeds for port %u, autonegotiation disabled",
2132 dev->data->port_id);
2136 rte_intr_disable(intr_handle);
2138 if ((rte_intr_cap_multiple(intr_handle) ||
2139 !RTE_ETH_DEV_SRIOV(dev).active) &&
2140 dev->data->dev_conf.intr_conf.rxq != 0) {
2141 intr_vector = dev->data->nb_rx_queues;
2142 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2147 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2148 intr_handle->intr_vec =
2149 rte_zmalloc("intr_vec",
2150 dev->data->nb_rx_queues * sizeof(int),
2152 if (!intr_handle->intr_vec) {
2154 "Failed to allocate %d rx_queues intr_vec",
2155 dev->data->nb_rx_queues);
2160 /* Initialize VSI */
2161 ret = i40e_dev_rxtx_init(pf);
2162 if (ret != I40E_SUCCESS) {
2163 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2167 /* Map queues with MSIX interrupt */
2168 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2169 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2170 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2171 i40e_vsi_enable_queues_intr(main_vsi);
2173 /* Map VMDQ VSI queues with MSIX interrupt */
2174 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2175 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2176 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2177 I40E_ITR_INDEX_DEFAULT);
2178 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2181 /* enable FDIR MSIX interrupt */
2182 if (pf->fdir.fdir_vsi) {
2183 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2184 I40E_ITR_INDEX_NONE);
2185 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2188 /* Enable all queues which have been configured */
2189 ret = i40e_dev_switch_queues(pf, TRUE);
2190 if (ret != I40E_SUCCESS) {
2191 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2195 /* Enable receiving broadcast packets */
2196 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2197 if (ret != I40E_SUCCESS)
2198 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2200 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2201 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2203 if (ret != I40E_SUCCESS)
2204 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2207 /* Enable the VLAN promiscuous mode. */
2209 for (i = 0; i < pf->vf_num; i++) {
2210 vsi = pf->vfs[i].vsi;
2211 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2216 /* Enable mac loopback mode */
2217 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2218 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2219 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2220 if (ret != I40E_SUCCESS) {
2221 PMD_DRV_LOG(ERR, "fail to set loopback link");
2226 /* Apply link configure */
2227 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2228 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2229 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2230 ETH_LINK_SPEED_40G)) {
2231 PMD_DRV_LOG(ERR, "Invalid link setting");
2234 ret = i40e_apply_link_speed(dev);
2235 if (I40E_SUCCESS != ret) {
2236 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2240 if (!rte_intr_allow_others(intr_handle)) {
2241 rte_intr_callback_unregister(intr_handle,
2242 i40e_dev_interrupt_handler,
2244 /* configure and enable device interrupt */
2245 i40e_pf_config_irq0(hw, FALSE);
2246 i40e_pf_enable_irq0(hw);
2248 if (dev->data->dev_conf.intr_conf.lsc != 0)
2250 "lsc won't enable because of no intr multiplex");
2252 ret = i40e_aq_set_phy_int_mask(hw,
2253 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2254 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2255 I40E_AQ_EVENT_MEDIA_NA), NULL);
2256 if (ret != I40E_SUCCESS)
2257 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2259 /* Call get_link_info aq commond to enable/disable LSE */
2260 i40e_dev_link_update(dev, 0);
2263 /* enable uio intr after callback register */
2264 rte_intr_enable(intr_handle);
2266 i40e_filter_restore(pf);
2268 if (pf->tm_conf.root && !pf->tm_conf.committed)
2269 PMD_DRV_LOG(WARNING,
2270 "please call hierarchy_commit() "
2271 "before starting the port");
2273 return I40E_SUCCESS;
2276 i40e_dev_switch_queues(pf, FALSE);
2277 i40e_dev_clear_queues(dev);
2283 i40e_dev_stop(struct rte_eth_dev *dev)
2285 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2286 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287 struct i40e_vsi *main_vsi = pf->main_vsi;
2288 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2289 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2292 if (hw->adapter_stopped == 1)
2294 /* Disable all queues */
2295 i40e_dev_switch_queues(pf, FALSE);
2297 /* un-map queues with interrupt registers */
2298 i40e_vsi_disable_queues_intr(main_vsi);
2299 i40e_vsi_queues_unbind_intr(main_vsi);
2301 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2302 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2303 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2306 if (pf->fdir.fdir_vsi) {
2307 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2308 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2310 /* Clear all queues and release memory */
2311 i40e_dev_clear_queues(dev);
2314 i40e_dev_set_link_down(dev);
2316 if (!rte_intr_allow_others(intr_handle))
2317 /* resume to the default handler */
2318 rte_intr_callback_register(intr_handle,
2319 i40e_dev_interrupt_handler,
2322 /* Clean datapath event and queue/vec mapping */
2323 rte_intr_efd_disable(intr_handle);
2324 if (intr_handle->intr_vec) {
2325 rte_free(intr_handle->intr_vec);
2326 intr_handle->intr_vec = NULL;
2329 /* reset hierarchy commit */
2330 pf->tm_conf.committed = false;
2332 hw->adapter_stopped = 1;
2336 i40e_dev_close(struct rte_eth_dev *dev)
2338 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2339 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2340 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2341 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2342 struct i40e_mirror_rule *p_mirror;
2347 PMD_INIT_FUNC_TRACE();
2351 /* Remove all mirror rules */
2352 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2353 ret = i40e_aq_del_mirror_rule(hw,
2354 pf->main_vsi->veb->seid,
2355 p_mirror->rule_type,
2357 p_mirror->num_entries,
2360 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2361 "status = %d, aq_err = %d.", ret,
2362 hw->aq.asq_last_status);
2364 /* remove mirror software resource anyway */
2365 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2367 pf->nb_mirror_rule--;
2370 i40e_dev_free_queues(dev);
2372 /* Disable interrupt */
2373 i40e_pf_disable_irq0(hw);
2374 rte_intr_disable(intr_handle);
2376 i40e_fdir_teardown(pf);
2378 /* shutdown and destroy the HMC */
2379 i40e_shutdown_lan_hmc(hw);
2381 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2382 i40e_vsi_release(pf->vmdq[i].vsi);
2383 pf->vmdq[i].vsi = NULL;
2388 /* release all the existing VSIs and VEBs */
2389 i40e_vsi_release(pf->main_vsi);
2391 /* shutdown the adminq */
2392 i40e_aq_queue_shutdown(hw, true);
2393 i40e_shutdown_adminq(hw);
2395 i40e_res_pool_destroy(&pf->qp_pool);
2396 i40e_res_pool_destroy(&pf->msix_pool);
2398 /* Disable flexible payload in global configuration */
2399 if (!pf->support_multi_driver)
2400 i40e_flex_payload_reg_set_default(hw);
2402 /* force a PF reset to clean anything leftover */
2403 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2404 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2405 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2406 I40E_WRITE_FLUSH(hw);
2410 * Reset PF device only to re-initialize resources in PMD layer
2413 i40e_dev_reset(struct rte_eth_dev *dev)
2417 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2418 * its VF to make them align with it. The detailed notification
2419 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2420 * To avoid unexpected behavior in VF, currently reset of PF with
2421 * SR-IOV activation is not supported. It might be supported later.
2423 if (dev->data->sriov.active)
2426 ret = eth_i40e_dev_uninit(dev);
2430 ret = eth_i40e_dev_init(dev, NULL);
2436 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2438 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2439 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2440 struct i40e_vsi *vsi = pf->main_vsi;
2443 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2445 if (status != I40E_SUCCESS)
2446 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2448 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2450 if (status != I40E_SUCCESS)
2451 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2456 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2458 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2459 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2460 struct i40e_vsi *vsi = pf->main_vsi;
2463 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2465 if (status != I40E_SUCCESS)
2466 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2468 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2470 if (status != I40E_SUCCESS)
2471 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2475 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2477 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2478 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2479 struct i40e_vsi *vsi = pf->main_vsi;
2482 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2483 if (ret != I40E_SUCCESS)
2484 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2488 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2490 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2491 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2492 struct i40e_vsi *vsi = pf->main_vsi;
2495 if (dev->data->promiscuous == 1)
2496 return; /* must remain in all_multicast mode */
2498 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2499 vsi->seid, FALSE, NULL);
2500 if (ret != I40E_SUCCESS)
2501 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2505 * Set device link up.
2508 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2510 /* re-apply link speed setting */
2511 return i40e_apply_link_speed(dev);
2515 * Set device link down.
2518 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2520 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2521 uint8_t abilities = 0;
2522 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2524 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2525 return i40e_phy_conf_link(hw, abilities, speed, false);
2528 static __rte_always_inline void
2529 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2531 /* Link status registers and values*/
2532 #define I40E_PRTMAC_LINKSTA 0x001E2420
2533 #define I40E_REG_LINK_UP 0x40000080
2534 #define I40E_PRTMAC_MACC 0x001E24E0
2535 #define I40E_REG_MACC_25GB 0x00020000
2536 #define I40E_REG_SPEED_MASK 0x38000000
2537 #define I40E_REG_SPEED_100MB 0x00000000
2538 #define I40E_REG_SPEED_1GB 0x08000000
2539 #define I40E_REG_SPEED_10GB 0x10000000
2540 #define I40E_REG_SPEED_20GB 0x20000000
2541 #define I40E_REG_SPEED_25_40GB 0x18000000
2542 uint32_t link_speed;
2545 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2546 link_speed = reg_val & I40E_REG_SPEED_MASK;
2547 reg_val &= I40E_REG_LINK_UP;
2548 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2550 if (unlikely(link->link_status == 0))
2553 /* Parse the link status */
2554 switch (link_speed) {
2555 case I40E_REG_SPEED_100MB:
2556 link->link_speed = ETH_SPEED_NUM_100M;
2558 case I40E_REG_SPEED_1GB:
2559 link->link_speed = ETH_SPEED_NUM_1G;
2561 case I40E_REG_SPEED_10GB:
2562 link->link_speed = ETH_SPEED_NUM_10G;
2564 case I40E_REG_SPEED_20GB:
2565 link->link_speed = ETH_SPEED_NUM_20G;
2567 case I40E_REG_SPEED_25_40GB:
2568 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2570 if (reg_val & I40E_REG_MACC_25GB)
2571 link->link_speed = ETH_SPEED_NUM_25G;
2573 link->link_speed = ETH_SPEED_NUM_40G;
2577 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2582 static __rte_always_inline void
2583 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2584 bool enable_lse, int wait_to_complete)
2586 #define CHECK_INTERVAL 100 /* 100ms */
2587 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2588 uint32_t rep_cnt = MAX_REPEAT_TIME;
2589 struct i40e_link_status link_status;
2592 memset(&link_status, 0, sizeof(link_status));
2595 memset(&link_status, 0, sizeof(link_status));
2597 /* Get link status information from hardware */
2598 status = i40e_aq_get_link_info(hw, enable_lse,
2599 &link_status, NULL);
2600 if (unlikely(status != I40E_SUCCESS)) {
2601 link->link_speed = ETH_SPEED_NUM_100M;
2602 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2603 PMD_DRV_LOG(ERR, "Failed to get link info");
2607 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2608 if (!wait_to_complete || link->link_status)
2611 rte_delay_ms(CHECK_INTERVAL);
2612 } while (--rep_cnt);
2614 /* Parse the link status */
2615 switch (link_status.link_speed) {
2616 case I40E_LINK_SPEED_100MB:
2617 link->link_speed = ETH_SPEED_NUM_100M;
2619 case I40E_LINK_SPEED_1GB:
2620 link->link_speed = ETH_SPEED_NUM_1G;
2622 case I40E_LINK_SPEED_10GB:
2623 link->link_speed = ETH_SPEED_NUM_10G;
2625 case I40E_LINK_SPEED_20GB:
2626 link->link_speed = ETH_SPEED_NUM_20G;
2628 case I40E_LINK_SPEED_25GB:
2629 link->link_speed = ETH_SPEED_NUM_25G;
2631 case I40E_LINK_SPEED_40GB:
2632 link->link_speed = ETH_SPEED_NUM_40G;
2635 link->link_speed = ETH_SPEED_NUM_100M;
2641 i40e_dev_link_update(struct rte_eth_dev *dev,
2642 int wait_to_complete)
2644 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2645 struct rte_eth_link link;
2646 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2649 memset(&link, 0, sizeof(link));
2651 /* i40e uses full duplex only */
2652 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2653 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2654 ETH_LINK_SPEED_FIXED);
2656 if (!wait_to_complete && !enable_lse)
2657 update_link_reg(hw, &link);
2659 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2661 ret = rte_eth_linkstatus_set(dev, &link);
2662 i40e_notify_all_vfs_link_status(dev);
2667 /* Get all the statistics of a VSI */
2669 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2671 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2672 struct i40e_eth_stats *nes = &vsi->eth_stats;
2673 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2674 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2676 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2677 vsi->offset_loaded, &oes->rx_bytes,
2679 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2680 vsi->offset_loaded, &oes->rx_unicast,
2682 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2683 vsi->offset_loaded, &oes->rx_multicast,
2684 &nes->rx_multicast);
2685 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2686 vsi->offset_loaded, &oes->rx_broadcast,
2687 &nes->rx_broadcast);
2688 /* exclude CRC bytes */
2689 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2690 nes->rx_broadcast) * ETHER_CRC_LEN;
2692 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2693 &oes->rx_discards, &nes->rx_discards);
2694 /* GLV_REPC not supported */
2695 /* GLV_RMPC not supported */
2696 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2697 &oes->rx_unknown_protocol,
2698 &nes->rx_unknown_protocol);
2699 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2700 vsi->offset_loaded, &oes->tx_bytes,
2702 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2703 vsi->offset_loaded, &oes->tx_unicast,
2705 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2706 vsi->offset_loaded, &oes->tx_multicast,
2707 &nes->tx_multicast);
2708 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2709 vsi->offset_loaded, &oes->tx_broadcast,
2710 &nes->tx_broadcast);
2711 /* GLV_TDPC not supported */
2712 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2713 &oes->tx_errors, &nes->tx_errors);
2714 vsi->offset_loaded = true;
2716 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2718 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2719 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2720 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2721 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2722 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2723 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2724 nes->rx_unknown_protocol);
2725 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2726 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2727 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2728 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2729 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2730 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2731 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2736 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2739 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2740 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2742 /* Get rx/tx bytes of internal transfer packets */
2743 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2744 I40E_GLV_GORCL(hw->port),
2746 &pf->internal_stats_offset.rx_bytes,
2747 &pf->internal_stats.rx_bytes);
2749 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2750 I40E_GLV_GOTCL(hw->port),
2752 &pf->internal_stats_offset.tx_bytes,
2753 &pf->internal_stats.tx_bytes);
2754 /* Get total internal rx packet count */
2755 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2756 I40E_GLV_UPRCL(hw->port),
2758 &pf->internal_stats_offset.rx_unicast,
2759 &pf->internal_stats.rx_unicast);
2760 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2761 I40E_GLV_MPRCL(hw->port),
2763 &pf->internal_stats_offset.rx_multicast,
2764 &pf->internal_stats.rx_multicast);
2765 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2766 I40E_GLV_BPRCL(hw->port),
2768 &pf->internal_stats_offset.rx_broadcast,
2769 &pf->internal_stats.rx_broadcast);
2770 /* Get total internal tx packet count */
2771 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2772 I40E_GLV_UPTCL(hw->port),
2774 &pf->internal_stats_offset.tx_unicast,
2775 &pf->internal_stats.tx_unicast);
2776 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2777 I40E_GLV_MPTCL(hw->port),
2779 &pf->internal_stats_offset.tx_multicast,
2780 &pf->internal_stats.tx_multicast);
2781 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2782 I40E_GLV_BPTCL(hw->port),
2784 &pf->internal_stats_offset.tx_broadcast,
2785 &pf->internal_stats.tx_broadcast);
2787 /* exclude CRC size */
2788 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2789 pf->internal_stats.rx_multicast +
2790 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2792 /* Get statistics of struct i40e_eth_stats */
2793 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2794 I40E_GLPRT_GORCL(hw->port),
2795 pf->offset_loaded, &os->eth.rx_bytes,
2797 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2798 I40E_GLPRT_UPRCL(hw->port),
2799 pf->offset_loaded, &os->eth.rx_unicast,
2800 &ns->eth.rx_unicast);
2801 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2802 I40E_GLPRT_MPRCL(hw->port),
2803 pf->offset_loaded, &os->eth.rx_multicast,
2804 &ns->eth.rx_multicast);
2805 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2806 I40E_GLPRT_BPRCL(hw->port),
2807 pf->offset_loaded, &os->eth.rx_broadcast,
2808 &ns->eth.rx_broadcast);
2809 /* Workaround: CRC size should not be included in byte statistics,
2810 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2812 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2813 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2815 /* exclude internal rx bytes
2816 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2817 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2819 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2821 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2822 ns->eth.rx_bytes = 0;
2824 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2826 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2827 ns->eth.rx_unicast = 0;
2829 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2831 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2832 ns->eth.rx_multicast = 0;
2834 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2836 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2837 ns->eth.rx_broadcast = 0;
2839 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2841 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2842 pf->offset_loaded, &os->eth.rx_discards,
2843 &ns->eth.rx_discards);
2844 /* GLPRT_REPC not supported */
2845 /* GLPRT_RMPC not supported */
2846 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2848 &os->eth.rx_unknown_protocol,
2849 &ns->eth.rx_unknown_protocol);
2850 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2851 I40E_GLPRT_GOTCL(hw->port),
2852 pf->offset_loaded, &os->eth.tx_bytes,
2854 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2855 I40E_GLPRT_UPTCL(hw->port),
2856 pf->offset_loaded, &os->eth.tx_unicast,
2857 &ns->eth.tx_unicast);
2858 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2859 I40E_GLPRT_MPTCL(hw->port),
2860 pf->offset_loaded, &os->eth.tx_multicast,
2861 &ns->eth.tx_multicast);
2862 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2863 I40E_GLPRT_BPTCL(hw->port),
2864 pf->offset_loaded, &os->eth.tx_broadcast,
2865 &ns->eth.tx_broadcast);
2866 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2867 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2869 /* exclude internal tx bytes
2870 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2871 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2873 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2875 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2876 ns->eth.tx_bytes = 0;
2878 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2880 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2881 ns->eth.tx_unicast = 0;
2883 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2885 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2886 ns->eth.tx_multicast = 0;
2888 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2890 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2891 ns->eth.tx_broadcast = 0;
2893 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2895 /* GLPRT_TEPC not supported */
2897 /* additional port specific stats */
2898 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2899 pf->offset_loaded, &os->tx_dropped_link_down,
2900 &ns->tx_dropped_link_down);
2901 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2902 pf->offset_loaded, &os->crc_errors,
2904 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2905 pf->offset_loaded, &os->illegal_bytes,
2906 &ns->illegal_bytes);
2907 /* GLPRT_ERRBC not supported */
2908 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2909 pf->offset_loaded, &os->mac_local_faults,
2910 &ns->mac_local_faults);
2911 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2912 pf->offset_loaded, &os->mac_remote_faults,
2913 &ns->mac_remote_faults);
2914 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2915 pf->offset_loaded, &os->rx_length_errors,
2916 &ns->rx_length_errors);
2917 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2918 pf->offset_loaded, &os->link_xon_rx,
2920 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2921 pf->offset_loaded, &os->link_xoff_rx,
2923 for (i = 0; i < 8; i++) {
2924 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2926 &os->priority_xon_rx[i],
2927 &ns->priority_xon_rx[i]);
2928 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2930 &os->priority_xoff_rx[i],
2931 &ns->priority_xoff_rx[i]);
2933 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2934 pf->offset_loaded, &os->link_xon_tx,
2936 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2937 pf->offset_loaded, &os->link_xoff_tx,
2939 for (i = 0; i < 8; i++) {
2940 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2942 &os->priority_xon_tx[i],
2943 &ns->priority_xon_tx[i]);
2944 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2946 &os->priority_xoff_tx[i],
2947 &ns->priority_xoff_tx[i]);
2948 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2950 &os->priority_xon_2_xoff[i],
2951 &ns->priority_xon_2_xoff[i]);
2953 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2954 I40E_GLPRT_PRC64L(hw->port),
2955 pf->offset_loaded, &os->rx_size_64,
2957 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2958 I40E_GLPRT_PRC127L(hw->port),
2959 pf->offset_loaded, &os->rx_size_127,
2961 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2962 I40E_GLPRT_PRC255L(hw->port),
2963 pf->offset_loaded, &os->rx_size_255,
2965 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2966 I40E_GLPRT_PRC511L(hw->port),
2967 pf->offset_loaded, &os->rx_size_511,
2969 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2970 I40E_GLPRT_PRC1023L(hw->port),
2971 pf->offset_loaded, &os->rx_size_1023,
2973 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2974 I40E_GLPRT_PRC1522L(hw->port),
2975 pf->offset_loaded, &os->rx_size_1522,
2977 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2978 I40E_GLPRT_PRC9522L(hw->port),
2979 pf->offset_loaded, &os->rx_size_big,
2981 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2982 pf->offset_loaded, &os->rx_undersize,
2984 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2985 pf->offset_loaded, &os->rx_fragments,
2987 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2988 pf->offset_loaded, &os->rx_oversize,
2990 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2991 pf->offset_loaded, &os->rx_jabber,
2993 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2994 I40E_GLPRT_PTC64L(hw->port),
2995 pf->offset_loaded, &os->tx_size_64,
2997 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2998 I40E_GLPRT_PTC127L(hw->port),
2999 pf->offset_loaded, &os->tx_size_127,
3001 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3002 I40E_GLPRT_PTC255L(hw->port),
3003 pf->offset_loaded, &os->tx_size_255,
3005 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3006 I40E_GLPRT_PTC511L(hw->port),
3007 pf->offset_loaded, &os->tx_size_511,
3009 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3010 I40E_GLPRT_PTC1023L(hw->port),
3011 pf->offset_loaded, &os->tx_size_1023,
3013 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3014 I40E_GLPRT_PTC1522L(hw->port),
3015 pf->offset_loaded, &os->tx_size_1522,
3017 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3018 I40E_GLPRT_PTC9522L(hw->port),
3019 pf->offset_loaded, &os->tx_size_big,
3021 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3023 &os->fd_sb_match, &ns->fd_sb_match);
3024 /* GLPRT_MSPDC not supported */
3025 /* GLPRT_XEC not supported */
3027 pf->offset_loaded = true;
3030 i40e_update_vsi_stats(pf->main_vsi);
3033 /* Get all statistics of a port */
3035 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3037 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3038 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3039 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3042 /* call read registers - updates values, now write them to struct */
3043 i40e_read_stats_registers(pf, hw);
3045 stats->ipackets = ns->eth.rx_unicast +
3046 ns->eth.rx_multicast +
3047 ns->eth.rx_broadcast -
3048 ns->eth.rx_discards -
3049 pf->main_vsi->eth_stats.rx_discards;
3050 stats->opackets = ns->eth.tx_unicast +
3051 ns->eth.tx_multicast +
3052 ns->eth.tx_broadcast;
3053 stats->ibytes = ns->eth.rx_bytes;
3054 stats->obytes = ns->eth.tx_bytes;
3055 stats->oerrors = ns->eth.tx_errors +
3056 pf->main_vsi->eth_stats.tx_errors;
3059 stats->imissed = ns->eth.rx_discards +
3060 pf->main_vsi->eth_stats.rx_discards;
3061 stats->ierrors = ns->crc_errors +
3062 ns->rx_length_errors + ns->rx_undersize +
3063 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3065 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3066 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3067 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3068 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3069 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3070 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3071 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3072 ns->eth.rx_unknown_protocol);
3073 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3074 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3075 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3076 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3077 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3078 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3080 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3081 ns->tx_dropped_link_down);
3082 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3083 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3085 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3086 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3087 ns->mac_local_faults);
3088 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3089 ns->mac_remote_faults);
3090 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3091 ns->rx_length_errors);
3092 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3093 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3094 for (i = 0; i < 8; i++) {
3095 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3096 i, ns->priority_xon_rx[i]);
3097 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3098 i, ns->priority_xoff_rx[i]);
3100 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3101 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3102 for (i = 0; i < 8; i++) {
3103 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3104 i, ns->priority_xon_tx[i]);
3105 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3106 i, ns->priority_xoff_tx[i]);
3107 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3108 i, ns->priority_xon_2_xoff[i]);
3110 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3111 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3112 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3113 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3114 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3115 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3116 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3117 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3118 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3119 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3120 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3121 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3122 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3123 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3124 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3125 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3126 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3127 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3128 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3129 ns->mac_short_packet_dropped);
3130 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3131 ns->checksum_error);
3132 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3133 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3137 /* Reset the statistics */
3139 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3142 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3144 /* Mark PF and VSI stats to update the offset, aka "reset" */
3145 pf->offset_loaded = false;
3147 pf->main_vsi->offset_loaded = false;
3149 /* read the stats, reading current register values into offset */
3150 i40e_read_stats_registers(pf, hw);
3154 i40e_xstats_calc_num(void)
3156 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3157 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3158 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3161 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3162 struct rte_eth_xstat_name *xstats_names,
3163 __rte_unused unsigned limit)
3168 if (xstats_names == NULL)
3169 return i40e_xstats_calc_num();
3171 /* Note: limit checked in rte_eth_xstats_names() */
3173 /* Get stats from i40e_eth_stats struct */
3174 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3175 snprintf(xstats_names[count].name,
3176 sizeof(xstats_names[count].name),
3177 "%s", rte_i40e_stats_strings[i].name);
3181 /* Get individiual stats from i40e_hw_port struct */
3182 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3183 snprintf(xstats_names[count].name,
3184 sizeof(xstats_names[count].name),
3185 "%s", rte_i40e_hw_port_strings[i].name);
3189 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3190 for (prio = 0; prio < 8; prio++) {
3191 snprintf(xstats_names[count].name,
3192 sizeof(xstats_names[count].name),
3193 "rx_priority%u_%s", prio,
3194 rte_i40e_rxq_prio_strings[i].name);
3199 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3200 for (prio = 0; prio < 8; prio++) {
3201 snprintf(xstats_names[count].name,
3202 sizeof(xstats_names[count].name),
3203 "tx_priority%u_%s", prio,
3204 rte_i40e_txq_prio_strings[i].name);
3212 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3215 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3216 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3217 unsigned i, count, prio;
3218 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3220 count = i40e_xstats_calc_num();
3224 i40e_read_stats_registers(pf, hw);
3231 /* Get stats from i40e_eth_stats struct */
3232 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3233 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3234 rte_i40e_stats_strings[i].offset);
3235 xstats[count].id = count;
3239 /* Get individiual stats from i40e_hw_port struct */
3240 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3241 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3242 rte_i40e_hw_port_strings[i].offset);
3243 xstats[count].id = count;
3247 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3248 for (prio = 0; prio < 8; prio++) {
3249 xstats[count].value =
3250 *(uint64_t *)(((char *)hw_stats) +
3251 rte_i40e_rxq_prio_strings[i].offset +
3252 (sizeof(uint64_t) * prio));
3253 xstats[count].id = count;
3258 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3259 for (prio = 0; prio < 8; prio++) {
3260 xstats[count].value =
3261 *(uint64_t *)(((char *)hw_stats) +
3262 rte_i40e_txq_prio_strings[i].offset +
3263 (sizeof(uint64_t) * prio));
3264 xstats[count].id = count;
3273 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3274 __rte_unused uint16_t queue_id,
3275 __rte_unused uint8_t stat_idx,
3276 __rte_unused uint8_t is_rx)
3278 PMD_INIT_FUNC_TRACE();
3284 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3286 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3292 full_ver = hw->nvm.oem_ver;
3293 ver = (u8)(full_ver >> 24);
3294 build = (u16)((full_ver >> 8) & 0xffff);
3295 patch = (u8)(full_ver & 0xff);
3297 ret = snprintf(fw_version, fw_size,
3298 "%d.%d%d 0x%08x %d.%d.%d",
3299 ((hw->nvm.version >> 12) & 0xf),
3300 ((hw->nvm.version >> 4) & 0xff),
3301 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3304 ret += 1; /* add the size of '\0' */
3305 if (fw_size < (u32)ret)
3312 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3314 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3315 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3316 struct i40e_vsi *vsi = pf->main_vsi;
3317 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3319 dev_info->max_rx_queues = vsi->nb_qps;
3320 dev_info->max_tx_queues = vsi->nb_qps;
3321 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3322 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3323 dev_info->max_mac_addrs = vsi->max_macaddrs;
3324 dev_info->max_vfs = pci_dev->max_vfs;
3325 dev_info->rx_queue_offload_capa = 0;
3326 dev_info->rx_offload_capa =
3327 DEV_RX_OFFLOAD_VLAN_STRIP |
3328 DEV_RX_OFFLOAD_QINQ_STRIP |
3329 DEV_RX_OFFLOAD_IPV4_CKSUM |
3330 DEV_RX_OFFLOAD_UDP_CKSUM |
3331 DEV_RX_OFFLOAD_TCP_CKSUM |
3332 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3333 DEV_RX_OFFLOAD_CRC_STRIP |
3334 DEV_RX_OFFLOAD_KEEP_CRC |
3335 DEV_RX_OFFLOAD_VLAN_EXTEND |
3336 DEV_RX_OFFLOAD_VLAN_FILTER |
3337 DEV_RX_OFFLOAD_JUMBO_FRAME;
3339 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3340 dev_info->tx_offload_capa =
3341 DEV_TX_OFFLOAD_VLAN_INSERT |
3342 DEV_TX_OFFLOAD_QINQ_INSERT |
3343 DEV_TX_OFFLOAD_IPV4_CKSUM |
3344 DEV_TX_OFFLOAD_UDP_CKSUM |
3345 DEV_TX_OFFLOAD_TCP_CKSUM |
3346 DEV_TX_OFFLOAD_SCTP_CKSUM |
3347 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3348 DEV_TX_OFFLOAD_TCP_TSO |
3349 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3350 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3351 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3352 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3353 DEV_TX_OFFLOAD_MULTI_SEGS |
3354 dev_info->tx_queue_offload_capa;
3355 dev_info->dev_capa =
3356 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3357 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3359 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3361 dev_info->reta_size = pf->hash_lut_size;
3362 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3364 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3366 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3367 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3368 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3370 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3375 dev_info->default_txconf = (struct rte_eth_txconf) {
3377 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3378 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3379 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3381 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3382 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3386 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3387 .nb_max = I40E_MAX_RING_DESC,
3388 .nb_min = I40E_MIN_RING_DESC,
3389 .nb_align = I40E_ALIGN_RING_DESC,
3392 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3393 .nb_max = I40E_MAX_RING_DESC,
3394 .nb_min = I40E_MIN_RING_DESC,
3395 .nb_align = I40E_ALIGN_RING_DESC,
3396 .nb_seg_max = I40E_TX_MAX_SEG,
3397 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3400 if (pf->flags & I40E_FLAG_VMDQ) {
3401 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3402 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3403 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3404 pf->max_nb_vmdq_vsi;
3405 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3406 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3407 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3410 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3412 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3413 dev_info->default_rxportconf.nb_queues = 2;
3414 dev_info->default_txportconf.nb_queues = 2;
3415 if (dev->data->nb_rx_queues == 1)
3416 dev_info->default_rxportconf.ring_size = 2048;
3418 dev_info->default_rxportconf.ring_size = 1024;
3419 if (dev->data->nb_tx_queues == 1)
3420 dev_info->default_txportconf.ring_size = 1024;
3422 dev_info->default_txportconf.ring_size = 512;
3424 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3426 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3427 dev_info->default_rxportconf.nb_queues = 1;
3428 dev_info->default_txportconf.nb_queues = 1;
3429 dev_info->default_rxportconf.ring_size = 256;
3430 dev_info->default_txportconf.ring_size = 256;
3433 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3434 dev_info->default_rxportconf.nb_queues = 1;
3435 dev_info->default_txportconf.nb_queues = 1;
3436 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3437 dev_info->default_rxportconf.ring_size = 512;
3438 dev_info->default_txportconf.ring_size = 256;
3440 dev_info->default_rxportconf.ring_size = 256;
3441 dev_info->default_txportconf.ring_size = 256;
3444 dev_info->default_rxportconf.burst_size = 32;
3445 dev_info->default_txportconf.burst_size = 32;
3449 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3451 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3452 struct i40e_vsi *vsi = pf->main_vsi;
3453 PMD_INIT_FUNC_TRACE();
3456 return i40e_vsi_add_vlan(vsi, vlan_id);
3458 return i40e_vsi_delete_vlan(vsi, vlan_id);
3462 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3463 enum rte_vlan_type vlan_type,
3464 uint16_t tpid, int qinq)
3466 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3469 uint16_t reg_id = 3;
3473 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3477 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3479 if (ret != I40E_SUCCESS) {
3481 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3486 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3489 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3490 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3491 if (reg_r == reg_w) {
3492 PMD_DRV_LOG(DEBUG, "No need to write");
3496 ret = i40e_aq_debug_write_global_register(hw,
3497 I40E_GL_SWT_L2TAGCTRL(reg_id),
3499 if (ret != I40E_SUCCESS) {
3501 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3506 "Global register 0x%08x is changed with value 0x%08x",
3507 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3513 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3514 enum rte_vlan_type vlan_type,
3517 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3519 int qinq = dev->data->dev_conf.rxmode.offloads &
3520 DEV_RX_OFFLOAD_VLAN_EXTEND;
3523 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3524 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3525 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3527 "Unsupported vlan type.");
3531 if (pf->support_multi_driver) {
3532 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3536 /* 802.1ad frames ability is added in NVM API 1.7*/
3537 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3539 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3540 hw->first_tag = rte_cpu_to_le_16(tpid);
3541 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3542 hw->second_tag = rte_cpu_to_le_16(tpid);
3544 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3545 hw->second_tag = rte_cpu_to_le_16(tpid);
3547 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3548 if (ret != I40E_SUCCESS) {
3550 "Set switch config failed aq_err: %d",
3551 hw->aq.asq_last_status);
3555 /* If NVM API < 1.7, keep the register setting */
3556 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3563 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3565 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3566 struct i40e_vsi *vsi = pf->main_vsi;
3567 struct rte_eth_rxmode *rxmode;
3569 rxmode = &dev->data->dev_conf.rxmode;
3570 if (mask & ETH_VLAN_FILTER_MASK) {
3571 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3572 i40e_vsi_config_vlan_filter(vsi, TRUE);
3574 i40e_vsi_config_vlan_filter(vsi, FALSE);
3577 if (mask & ETH_VLAN_STRIP_MASK) {
3578 /* Enable or disable VLAN stripping */
3579 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3580 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3582 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3585 if (mask & ETH_VLAN_EXTEND_MASK) {
3586 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3587 i40e_vsi_config_double_vlan(vsi, TRUE);
3588 /* Set global registers with default ethertype. */
3589 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3591 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3595 i40e_vsi_config_double_vlan(vsi, FALSE);
3602 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3603 __rte_unused uint16_t queue,
3604 __rte_unused int on)
3606 PMD_INIT_FUNC_TRACE();
3610 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3612 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3613 struct i40e_vsi *vsi = pf->main_vsi;
3614 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3615 struct i40e_vsi_vlan_pvid_info info;
3617 memset(&info, 0, sizeof(info));
3620 info.config.pvid = pvid;
3622 info.config.reject.tagged =
3623 data->dev_conf.txmode.hw_vlan_reject_tagged;
3624 info.config.reject.untagged =
3625 data->dev_conf.txmode.hw_vlan_reject_untagged;
3628 return i40e_vsi_vlan_pvid_set(vsi, &info);
3632 i40e_dev_led_on(struct rte_eth_dev *dev)
3634 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3635 uint32_t mode = i40e_led_get(hw);
3638 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3644 i40e_dev_led_off(struct rte_eth_dev *dev)
3646 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3647 uint32_t mode = i40e_led_get(hw);
3650 i40e_led_set(hw, 0, false);
3656 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3658 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3659 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3661 fc_conf->pause_time = pf->fc_conf.pause_time;
3663 /* read out from register, in case they are modified by other port */
3664 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3665 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3666 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3667 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3669 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3670 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3672 /* Return current mode according to actual setting*/
3673 switch (hw->fc.current_mode) {
3675 fc_conf->mode = RTE_FC_FULL;
3677 case I40E_FC_TX_PAUSE:
3678 fc_conf->mode = RTE_FC_TX_PAUSE;
3680 case I40E_FC_RX_PAUSE:
3681 fc_conf->mode = RTE_FC_RX_PAUSE;
3685 fc_conf->mode = RTE_FC_NONE;
3692 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3694 uint32_t mflcn_reg, fctrl_reg, reg;
3695 uint32_t max_high_water;
3696 uint8_t i, aq_failure;
3700 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3701 [RTE_FC_NONE] = I40E_FC_NONE,
3702 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3703 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3704 [RTE_FC_FULL] = I40E_FC_FULL
3707 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3709 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3710 if ((fc_conf->high_water > max_high_water) ||
3711 (fc_conf->high_water < fc_conf->low_water)) {
3713 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3718 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3719 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3720 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3722 pf->fc_conf.pause_time = fc_conf->pause_time;
3723 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3724 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3726 PMD_INIT_FUNC_TRACE();
3728 /* All the link flow control related enable/disable register
3729 * configuration is handle by the F/W
3731 err = i40e_set_fc(hw, &aq_failure, true);
3735 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3736 /* Configure flow control refresh threshold,
3737 * the value for stat_tx_pause_refresh_timer[8]
3738 * is used for global pause operation.
3742 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3743 pf->fc_conf.pause_time);
3745 /* configure the timer value included in transmitted pause
3747 * the value for stat_tx_pause_quanta[8] is used for global
3750 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3751 pf->fc_conf.pause_time);
3753 fctrl_reg = I40E_READ_REG(hw,
3754 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3756 if (fc_conf->mac_ctrl_frame_fwd != 0)
3757 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3759 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3761 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3764 /* Configure pause time (2 TCs per register) */
3765 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3766 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3767 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3769 /* Configure flow control refresh threshold value */
3770 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3771 pf->fc_conf.pause_time / 2);
3773 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3775 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3776 *depending on configuration
3778 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3779 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3780 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3782 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3783 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3786 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3789 if (!pf->support_multi_driver) {
3790 /* config water marker both based on the packets and bytes */
3791 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3792 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3793 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3794 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3795 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3796 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3797 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3798 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3800 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3801 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3805 "Water marker configuration is not supported.");
3808 I40E_WRITE_FLUSH(hw);
3814 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3815 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3817 PMD_INIT_FUNC_TRACE();
3822 /* Add a MAC address, and update filters */
3824 i40e_macaddr_add(struct rte_eth_dev *dev,
3825 struct ether_addr *mac_addr,
3826 __rte_unused uint32_t index,
3829 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3830 struct i40e_mac_filter_info mac_filter;
3831 struct i40e_vsi *vsi;
3832 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3835 /* If VMDQ not enabled or configured, return */
3836 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3837 !pf->nb_cfg_vmdq_vsi)) {
3838 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3839 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3844 if (pool > pf->nb_cfg_vmdq_vsi) {
3845 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3846 pool, pf->nb_cfg_vmdq_vsi);
3850 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3851 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3852 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3854 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3859 vsi = pf->vmdq[pool - 1].vsi;
3861 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3862 if (ret != I40E_SUCCESS) {
3863 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3869 /* Remove a MAC address, and update filters */
3871 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3873 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3874 struct i40e_vsi *vsi;
3875 struct rte_eth_dev_data *data = dev->data;
3876 struct ether_addr *macaddr;
3881 macaddr = &(data->mac_addrs[index]);
3883 pool_sel = dev->data->mac_pool_sel[index];
3885 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3886 if (pool_sel & (1ULL << i)) {
3890 /* No VMDQ pool enabled or configured */
3891 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3892 (i > pf->nb_cfg_vmdq_vsi)) {
3894 "No VMDQ pool enabled/configured");
3897 vsi = pf->vmdq[i - 1].vsi;
3899 ret = i40e_vsi_delete_mac(vsi, macaddr);
3902 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3909 /* Set perfect match or hash match of MAC and VLAN for a VF */
3911 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3912 struct rte_eth_mac_filter *filter,
3916 struct i40e_mac_filter_info mac_filter;
3917 struct ether_addr old_mac;
3918 struct ether_addr *new_mac;
3919 struct i40e_pf_vf *vf = NULL;
3924 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3927 hw = I40E_PF_TO_HW(pf);
3929 if (filter == NULL) {
3930 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3934 new_mac = &filter->mac_addr;
3936 if (is_zero_ether_addr(new_mac)) {
3937 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3941 vf_id = filter->dst_id;
3943 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3944 PMD_DRV_LOG(ERR, "Invalid argument.");
3947 vf = &pf->vfs[vf_id];
3949 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3950 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3955 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3956 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3958 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3961 mac_filter.filter_type = filter->filter_type;
3962 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3963 if (ret != I40E_SUCCESS) {
3964 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3967 ether_addr_copy(new_mac, &pf->dev_addr);
3969 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3971 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3972 if (ret != I40E_SUCCESS) {
3973 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3977 /* Clear device address as it has been removed */
3978 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3979 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3985 /* MAC filter handle */
3987 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3990 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3991 struct rte_eth_mac_filter *filter;
3992 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3993 int ret = I40E_NOT_SUPPORTED;
3995 filter = (struct rte_eth_mac_filter *)(arg);
3997 switch (filter_op) {
3998 case RTE_ETH_FILTER_NOP:
4001 case RTE_ETH_FILTER_ADD:
4002 i40e_pf_disable_irq0(hw);
4004 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4005 i40e_pf_enable_irq0(hw);
4007 case RTE_ETH_FILTER_DELETE:
4008 i40e_pf_disable_irq0(hw);
4010 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4011 i40e_pf_enable_irq0(hw);
4014 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4015 ret = I40E_ERR_PARAM;
4023 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4025 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4026 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4033 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4034 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4037 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4041 uint32_t *lut_dw = (uint32_t *)lut;
4042 uint16_t i, lut_size_dw = lut_size / 4;
4044 if (vsi->type == I40E_VSI_SRIOV) {
4045 for (i = 0; i <= lut_size_dw; i++) {
4046 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4047 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4050 for (i = 0; i < lut_size_dw; i++)
4051 lut_dw[i] = I40E_READ_REG(hw,
4060 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4069 pf = I40E_VSI_TO_PF(vsi);
4070 hw = I40E_VSI_TO_HW(vsi);
4072 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4073 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4076 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4080 uint32_t *lut_dw = (uint32_t *)lut;
4081 uint16_t i, lut_size_dw = lut_size / 4;
4083 if (vsi->type == I40E_VSI_SRIOV) {
4084 for (i = 0; i < lut_size_dw; i++)
4087 I40E_VFQF_HLUT1(i, vsi->user_param),
4090 for (i = 0; i < lut_size_dw; i++)
4091 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4094 I40E_WRITE_FLUSH(hw);
4101 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4102 struct rte_eth_rss_reta_entry64 *reta_conf,
4105 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4106 uint16_t i, lut_size = pf->hash_lut_size;
4107 uint16_t idx, shift;
4111 if (reta_size != lut_size ||
4112 reta_size > ETH_RSS_RETA_SIZE_512) {
4114 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4115 reta_size, lut_size);
4119 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4121 PMD_DRV_LOG(ERR, "No memory can be allocated");
4124 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4127 for (i = 0; i < reta_size; i++) {
4128 idx = i / RTE_RETA_GROUP_SIZE;
4129 shift = i % RTE_RETA_GROUP_SIZE;
4130 if (reta_conf[idx].mask & (1ULL << shift))
4131 lut[i] = reta_conf[idx].reta[shift];
4133 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4142 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4143 struct rte_eth_rss_reta_entry64 *reta_conf,
4146 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4147 uint16_t i, lut_size = pf->hash_lut_size;
4148 uint16_t idx, shift;
4152 if (reta_size != lut_size ||
4153 reta_size > ETH_RSS_RETA_SIZE_512) {
4155 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4156 reta_size, lut_size);
4160 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4162 PMD_DRV_LOG(ERR, "No memory can be allocated");
4166 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4169 for (i = 0; i < reta_size; i++) {
4170 idx = i / RTE_RETA_GROUP_SIZE;
4171 shift = i % RTE_RETA_GROUP_SIZE;
4172 if (reta_conf[idx].mask & (1ULL << shift))
4173 reta_conf[idx].reta[shift] = lut[i];
4183 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4184 * @hw: pointer to the HW structure
4185 * @mem: pointer to mem struct to fill out
4186 * @size: size of memory requested
4187 * @alignment: what to align the allocation to
4189 enum i40e_status_code
4190 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4191 struct i40e_dma_mem *mem,
4195 const struct rte_memzone *mz = NULL;
4196 char z_name[RTE_MEMZONE_NAMESIZE];
4199 return I40E_ERR_PARAM;
4201 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4202 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4203 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4205 return I40E_ERR_NO_MEMORY;
4210 mem->zone = (const void *)mz;
4212 "memzone %s allocated with physical address: %"PRIu64,
4215 return I40E_SUCCESS;
4219 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4220 * @hw: pointer to the HW structure
4221 * @mem: ptr to mem struct to free
4223 enum i40e_status_code
4224 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4225 struct i40e_dma_mem *mem)
4228 return I40E_ERR_PARAM;
4231 "memzone %s to be freed with physical address: %"PRIu64,
4232 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4233 rte_memzone_free((const struct rte_memzone *)mem->zone);
4238 return I40E_SUCCESS;
4242 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4243 * @hw: pointer to the HW structure
4244 * @mem: pointer to mem struct to fill out
4245 * @size: size of memory requested
4247 enum i40e_status_code
4248 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4249 struct i40e_virt_mem *mem,
4253 return I40E_ERR_PARAM;
4256 mem->va = rte_zmalloc("i40e", size, 0);
4259 return I40E_SUCCESS;
4261 return I40E_ERR_NO_MEMORY;
4265 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4266 * @hw: pointer to the HW structure
4267 * @mem: pointer to mem struct to free
4269 enum i40e_status_code
4270 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4271 struct i40e_virt_mem *mem)
4274 return I40E_ERR_PARAM;
4279 return I40E_SUCCESS;
4283 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4285 rte_spinlock_init(&sp->spinlock);
4289 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4291 rte_spinlock_lock(&sp->spinlock);
4295 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4297 rte_spinlock_unlock(&sp->spinlock);
4301 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4307 * Get the hardware capabilities, which will be parsed
4308 * and saved into struct i40e_hw.
4311 i40e_get_cap(struct i40e_hw *hw)
4313 struct i40e_aqc_list_capabilities_element_resp *buf;
4314 uint16_t len, size = 0;
4317 /* Calculate a huge enough buff for saving response data temporarily */
4318 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4319 I40E_MAX_CAP_ELE_NUM;
4320 buf = rte_zmalloc("i40e", len, 0);
4322 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4323 return I40E_ERR_NO_MEMORY;
4326 /* Get, parse the capabilities and save it to hw */
4327 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4328 i40e_aqc_opc_list_func_capabilities, NULL);
4329 if (ret != I40E_SUCCESS)
4330 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4332 /* Free the temporary buffer after being used */
4338 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4339 #define QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
4341 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4349 pf = (struct i40e_pf *)opaque;
4353 num = strtoul(value, &end, 0);
4354 if (errno != 0 || end == value || *end != 0) {
4355 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4356 "kept the value = %hu", value, pf->vf_nb_qp_max);
4360 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4361 pf->vf_nb_qp_max = (uint16_t)num;
4363 /* here return 0 to make next valid same argument work */
4364 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4365 "power of 2 and equal or less than 16 !, Now it is "
4366 "kept the value = %hu", num, pf->vf_nb_qp_max);
4371 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4373 static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4374 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4375 struct rte_kvargs *kvlist;
4377 /* set default queue number per VF as 4 */
4378 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4380 if (dev->device->devargs == NULL)
4383 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4387 if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4388 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4389 "the first invalid or last valid one is used !",
4390 QUEUE_NUM_PER_VF_ARG);
4392 rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4393 i40e_pf_parse_vf_queue_number_handler, pf);
4395 rte_kvargs_free(kvlist);
4401 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4403 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4404 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4405 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4406 uint16_t qp_count = 0, vsi_count = 0;
4408 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4409 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4413 i40e_pf_config_vf_rxq_number(dev);
4415 /* Add the parameter init for LFC */
4416 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4417 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4418 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4420 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4421 pf->max_num_vsi = hw->func_caps.num_vsis;
4422 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4423 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4425 /* FDir queue/VSI allocation */
4426 pf->fdir_qp_offset = 0;
4427 if (hw->func_caps.fd) {
4428 pf->flags |= I40E_FLAG_FDIR;
4429 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4431 pf->fdir_nb_qps = 0;
4433 qp_count += pf->fdir_nb_qps;
4436 /* LAN queue/VSI allocation */
4437 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4438 if (!hw->func_caps.rss) {
4441 pf->flags |= I40E_FLAG_RSS;
4442 if (hw->mac.type == I40E_MAC_X722)
4443 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4444 pf->lan_nb_qps = pf->lan_nb_qp_max;
4446 qp_count += pf->lan_nb_qps;
4449 /* VF queue/VSI allocation */
4450 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4451 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4452 pf->flags |= I40E_FLAG_SRIOV;
4453 pf->vf_nb_qps = pf->vf_nb_qp_max;
4454 pf->vf_num = pci_dev->max_vfs;
4456 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4457 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4462 qp_count += pf->vf_nb_qps * pf->vf_num;
4463 vsi_count += pf->vf_num;
4465 /* VMDq queue/VSI allocation */
4466 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4467 pf->vmdq_nb_qps = 0;
4468 pf->max_nb_vmdq_vsi = 0;
4469 if (hw->func_caps.vmdq) {
4470 if (qp_count < hw->func_caps.num_tx_qp &&
4471 vsi_count < hw->func_caps.num_vsis) {
4472 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4473 qp_count) / pf->vmdq_nb_qp_max;
4475 /* Limit the maximum number of VMDq vsi to the maximum
4476 * ethdev can support
4478 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4479 hw->func_caps.num_vsis - vsi_count);
4480 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4482 if (pf->max_nb_vmdq_vsi) {
4483 pf->flags |= I40E_FLAG_VMDQ;
4484 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4486 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4487 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4488 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4491 "No enough queues left for VMDq");
4494 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4497 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4498 vsi_count += pf->max_nb_vmdq_vsi;
4500 if (hw->func_caps.dcb)
4501 pf->flags |= I40E_FLAG_DCB;
4503 if (qp_count > hw->func_caps.num_tx_qp) {
4505 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4506 qp_count, hw->func_caps.num_tx_qp);
4509 if (vsi_count > hw->func_caps.num_vsis) {
4511 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4512 vsi_count, hw->func_caps.num_vsis);
4520 i40e_pf_get_switch_config(struct i40e_pf *pf)
4522 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4523 struct i40e_aqc_get_switch_config_resp *switch_config;
4524 struct i40e_aqc_switch_config_element_resp *element;
4525 uint16_t start_seid = 0, num_reported;
4528 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4529 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4530 if (!switch_config) {
4531 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4535 /* Get the switch configurations */
4536 ret = i40e_aq_get_switch_config(hw, switch_config,
4537 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4538 if (ret != I40E_SUCCESS) {
4539 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4542 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4543 if (num_reported != 1) { /* The number should be 1 */
4544 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4548 /* Parse the switch configuration elements */
4549 element = &(switch_config->element[0]);
4550 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4551 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4552 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4554 PMD_DRV_LOG(INFO, "Unknown element type");
4557 rte_free(switch_config);
4563 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4566 struct pool_entry *entry;
4568 if (pool == NULL || num == 0)
4571 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4572 if (entry == NULL) {
4573 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4577 /* queue heap initialize */
4578 pool->num_free = num;
4579 pool->num_alloc = 0;
4581 LIST_INIT(&pool->alloc_list);
4582 LIST_INIT(&pool->free_list);
4584 /* Initialize element */
4588 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4593 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4595 struct pool_entry *entry, *next_entry;
4600 for (entry = LIST_FIRST(&pool->alloc_list);
4601 entry && (next_entry = LIST_NEXT(entry, next), 1);
4602 entry = next_entry) {
4603 LIST_REMOVE(entry, next);
4607 for (entry = LIST_FIRST(&pool->free_list);
4608 entry && (next_entry = LIST_NEXT(entry, next), 1);
4609 entry = next_entry) {
4610 LIST_REMOVE(entry, next);
4615 pool->num_alloc = 0;
4617 LIST_INIT(&pool->alloc_list);
4618 LIST_INIT(&pool->free_list);
4622 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4625 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4626 uint32_t pool_offset;
4630 PMD_DRV_LOG(ERR, "Invalid parameter");
4634 pool_offset = base - pool->base;
4635 /* Lookup in alloc list */
4636 LIST_FOREACH(entry, &pool->alloc_list, next) {
4637 if (entry->base == pool_offset) {
4638 valid_entry = entry;
4639 LIST_REMOVE(entry, next);
4644 /* Not find, return */
4645 if (valid_entry == NULL) {
4646 PMD_DRV_LOG(ERR, "Failed to find entry");
4651 * Found it, move it to free list and try to merge.
4652 * In order to make merge easier, always sort it by qbase.
4653 * Find adjacent prev and last entries.
4656 LIST_FOREACH(entry, &pool->free_list, next) {
4657 if (entry->base > valid_entry->base) {
4665 /* Try to merge with next one*/
4667 /* Merge with next one */
4668 if (valid_entry->base + valid_entry->len == next->base) {
4669 next->base = valid_entry->base;
4670 next->len += valid_entry->len;
4671 rte_free(valid_entry);
4678 /* Merge with previous one */
4679 if (prev->base + prev->len == valid_entry->base) {
4680 prev->len += valid_entry->len;
4681 /* If it merge with next one, remove next node */
4683 LIST_REMOVE(valid_entry, next);
4684 rte_free(valid_entry);
4686 rte_free(valid_entry);
4692 /* Not find any entry to merge, insert */
4695 LIST_INSERT_AFTER(prev, valid_entry, next);
4696 else if (next != NULL)
4697 LIST_INSERT_BEFORE(next, valid_entry, next);
4698 else /* It's empty list, insert to head */
4699 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4702 pool->num_free += valid_entry->len;
4703 pool->num_alloc -= valid_entry->len;
4709 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4712 struct pool_entry *entry, *valid_entry;
4714 if (pool == NULL || num == 0) {
4715 PMD_DRV_LOG(ERR, "Invalid parameter");
4719 if (pool->num_free < num) {
4720 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4721 num, pool->num_free);
4726 /* Lookup in free list and find most fit one */
4727 LIST_FOREACH(entry, &pool->free_list, next) {
4728 if (entry->len >= num) {
4730 if (entry->len == num) {
4731 valid_entry = entry;
4734 if (valid_entry == NULL || valid_entry->len > entry->len)
4735 valid_entry = entry;
4739 /* Not find one to satisfy the request, return */
4740 if (valid_entry == NULL) {
4741 PMD_DRV_LOG(ERR, "No valid entry found");
4745 * The entry have equal queue number as requested,
4746 * remove it from alloc_list.
4748 if (valid_entry->len == num) {
4749 LIST_REMOVE(valid_entry, next);
4752 * The entry have more numbers than requested,
4753 * create a new entry for alloc_list and minus its
4754 * queue base and number in free_list.
4756 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4757 if (entry == NULL) {
4759 "Failed to allocate memory for resource pool");
4762 entry->base = valid_entry->base;
4764 valid_entry->base += num;
4765 valid_entry->len -= num;
4766 valid_entry = entry;
4769 /* Insert it into alloc list, not sorted */
4770 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4772 pool->num_free -= valid_entry->len;
4773 pool->num_alloc += valid_entry->len;
4775 return valid_entry->base + pool->base;
4779 * bitmap_is_subset - Check whether src2 is subset of src1
4782 bitmap_is_subset(uint8_t src1, uint8_t src2)
4784 return !((src1 ^ src2) & src2);
4787 static enum i40e_status_code
4788 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4790 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4792 /* If DCB is not supported, only default TC is supported */
4793 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4794 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4795 return I40E_NOT_SUPPORTED;
4798 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4800 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4801 hw->func_caps.enabled_tcmap, enabled_tcmap);
4802 return I40E_NOT_SUPPORTED;
4804 return I40E_SUCCESS;
4808 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4809 struct i40e_vsi_vlan_pvid_info *info)
4812 struct i40e_vsi_context ctxt;
4813 uint8_t vlan_flags = 0;
4816 if (vsi == NULL || info == NULL) {
4817 PMD_DRV_LOG(ERR, "invalid parameters");
4818 return I40E_ERR_PARAM;
4822 vsi->info.pvid = info->config.pvid;
4824 * If insert pvid is enabled, only tagged pkts are
4825 * allowed to be sent out.
4827 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4828 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4831 if (info->config.reject.tagged == 0)
4832 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4834 if (info->config.reject.untagged == 0)
4835 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4837 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4838 I40E_AQ_VSI_PVLAN_MODE_MASK);
4839 vsi->info.port_vlan_flags |= vlan_flags;
4840 vsi->info.valid_sections =
4841 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4842 memset(&ctxt, 0, sizeof(ctxt));
4843 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4844 ctxt.seid = vsi->seid;
4846 hw = I40E_VSI_TO_HW(vsi);
4847 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4848 if (ret != I40E_SUCCESS)
4849 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4855 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4857 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4859 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4861 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4862 if (ret != I40E_SUCCESS)
4866 PMD_DRV_LOG(ERR, "seid not valid");
4870 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4871 tc_bw_data.tc_valid_bits = enabled_tcmap;
4872 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4873 tc_bw_data.tc_bw_credits[i] =
4874 (enabled_tcmap & (1 << i)) ? 1 : 0;
4876 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4877 if (ret != I40E_SUCCESS) {
4878 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4882 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4883 sizeof(vsi->info.qs_handle));
4884 return I40E_SUCCESS;
4887 static enum i40e_status_code
4888 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4889 struct i40e_aqc_vsi_properties_data *info,
4890 uint8_t enabled_tcmap)
4892 enum i40e_status_code ret;
4893 int i, total_tc = 0;
4894 uint16_t qpnum_per_tc, bsf, qp_idx;
4896 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4897 if (ret != I40E_SUCCESS)
4900 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4901 if (enabled_tcmap & (1 << i))
4905 vsi->enabled_tc = enabled_tcmap;
4907 /* Number of queues per enabled TC */
4908 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4909 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4910 bsf = rte_bsf32(qpnum_per_tc);
4912 /* Adjust the queue number to actual queues that can be applied */
4913 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4914 vsi->nb_qps = qpnum_per_tc * total_tc;
4917 * Configure TC and queue mapping parameters, for enabled TC,
4918 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4919 * default queue will serve it.
4922 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4923 if (vsi->enabled_tc & (1 << i)) {
4924 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4925 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4926 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4927 qp_idx += qpnum_per_tc;
4929 info->tc_mapping[i] = 0;
4932 /* Associate queue number with VSI */
4933 if (vsi->type == I40E_VSI_SRIOV) {
4934 info->mapping_flags |=
4935 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4936 for (i = 0; i < vsi->nb_qps; i++)
4937 info->queue_mapping[i] =
4938 rte_cpu_to_le_16(vsi->base_queue + i);
4940 info->mapping_flags |=
4941 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4942 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4944 info->valid_sections |=
4945 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4947 return I40E_SUCCESS;
4951 i40e_veb_release(struct i40e_veb *veb)
4953 struct i40e_vsi *vsi;
4959 if (!TAILQ_EMPTY(&veb->head)) {
4960 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4963 /* associate_vsi field is NULL for floating VEB */
4964 if (veb->associate_vsi != NULL) {
4965 vsi = veb->associate_vsi;
4966 hw = I40E_VSI_TO_HW(vsi);
4968 vsi->uplink_seid = veb->uplink_seid;
4971 veb->associate_pf->main_vsi->floating_veb = NULL;
4972 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4975 i40e_aq_delete_element(hw, veb->seid, NULL);
4977 return I40E_SUCCESS;
4981 static struct i40e_veb *
4982 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4984 struct i40e_veb *veb;
4990 "veb setup failed, associated PF shouldn't null");
4993 hw = I40E_PF_TO_HW(pf);
4995 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4997 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5001 veb->associate_vsi = vsi;
5002 veb->associate_pf = pf;
5003 TAILQ_INIT(&veb->head);
5004 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5006 /* create floating veb if vsi is NULL */
5008 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5009 I40E_DEFAULT_TCMAP, false,
5010 &veb->seid, false, NULL);
5012 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5013 true, &veb->seid, false, NULL);
5016 if (ret != I40E_SUCCESS) {
5017 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5018 hw->aq.asq_last_status);
5021 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5023 /* get statistics index */
5024 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5025 &veb->stats_idx, NULL, NULL, NULL);
5026 if (ret != I40E_SUCCESS) {
5027 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5028 hw->aq.asq_last_status);
5031 /* Get VEB bandwidth, to be implemented */
5032 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5034 vsi->uplink_seid = veb->seid;
5043 i40e_vsi_release(struct i40e_vsi *vsi)
5047 struct i40e_vsi_list *vsi_list;
5050 struct i40e_mac_filter *f;
5051 uint16_t user_param;
5054 return I40E_SUCCESS;
5059 user_param = vsi->user_param;
5061 pf = I40E_VSI_TO_PF(vsi);
5062 hw = I40E_VSI_TO_HW(vsi);
5064 /* VSI has child to attach, release child first */
5066 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5067 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5070 i40e_veb_release(vsi->veb);
5073 if (vsi->floating_veb) {
5074 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5075 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5080 /* Remove all macvlan filters of the VSI */
5081 i40e_vsi_remove_all_macvlan_filter(vsi);
5082 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5085 if (vsi->type != I40E_VSI_MAIN &&
5086 ((vsi->type != I40E_VSI_SRIOV) ||
5087 !pf->floating_veb_list[user_param])) {
5088 /* Remove vsi from parent's sibling list */
5089 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5090 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5091 return I40E_ERR_PARAM;
5093 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5094 &vsi->sib_vsi_list, list);
5096 /* Remove all switch element of the VSI */
5097 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5098 if (ret != I40E_SUCCESS)
5099 PMD_DRV_LOG(ERR, "Failed to delete element");
5102 if ((vsi->type == I40E_VSI_SRIOV) &&
5103 pf->floating_veb_list[user_param]) {
5104 /* Remove vsi from parent's sibling list */
5105 if (vsi->parent_vsi == NULL ||
5106 vsi->parent_vsi->floating_veb == NULL) {
5107 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5108 return I40E_ERR_PARAM;
5110 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5111 &vsi->sib_vsi_list, list);
5113 /* Remove all switch element of the VSI */
5114 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5115 if (ret != I40E_SUCCESS)
5116 PMD_DRV_LOG(ERR, "Failed to delete element");
5119 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5121 if (vsi->type != I40E_VSI_SRIOV)
5122 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5125 return I40E_SUCCESS;
5129 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5131 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5132 struct i40e_aqc_remove_macvlan_element_data def_filter;
5133 struct i40e_mac_filter_info filter;
5136 if (vsi->type != I40E_VSI_MAIN)
5137 return I40E_ERR_CONFIG;
5138 memset(&def_filter, 0, sizeof(def_filter));
5139 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5141 def_filter.vlan_tag = 0;
5142 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5143 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5144 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5145 if (ret != I40E_SUCCESS) {
5146 struct i40e_mac_filter *f;
5147 struct ether_addr *mac;
5150 "Cannot remove the default macvlan filter");
5151 /* It needs to add the permanent mac into mac list */
5152 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5154 PMD_DRV_LOG(ERR, "failed to allocate memory");
5155 return I40E_ERR_NO_MEMORY;
5157 mac = &f->mac_info.mac_addr;
5158 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5160 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5161 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5166 rte_memcpy(&filter.mac_addr,
5167 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5168 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5169 return i40e_vsi_add_mac(vsi, &filter);
5173 * i40e_vsi_get_bw_config - Query VSI BW Information
5174 * @vsi: the VSI to be queried
5176 * Returns 0 on success, negative value on failure
5178 static enum i40e_status_code
5179 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5181 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5182 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5183 struct i40e_hw *hw = &vsi->adapter->hw;
5188 memset(&bw_config, 0, sizeof(bw_config));
5189 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5190 if (ret != I40E_SUCCESS) {
5191 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5192 hw->aq.asq_last_status);
5196 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5197 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5198 &ets_sla_config, NULL);
5199 if (ret != I40E_SUCCESS) {
5201 "VSI failed to get TC bandwdith configuration %u",
5202 hw->aq.asq_last_status);
5206 /* store and print out BW info */
5207 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5208 vsi->bw_info.bw_max = bw_config.max_bw;
5209 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5210 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5211 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5212 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5214 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5215 vsi->bw_info.bw_ets_share_credits[i] =
5216 ets_sla_config.share_credits[i];
5217 vsi->bw_info.bw_ets_credits[i] =
5218 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5219 /* 4 bits per TC, 4th bit is reserved */
5220 vsi->bw_info.bw_ets_max[i] =
5221 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5222 RTE_LEN2MASK(3, uint8_t));
5223 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5224 vsi->bw_info.bw_ets_share_credits[i]);
5225 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5226 vsi->bw_info.bw_ets_credits[i]);
5227 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5228 vsi->bw_info.bw_ets_max[i]);
5231 return I40E_SUCCESS;
5234 /* i40e_enable_pf_lb
5235 * @pf: pointer to the pf structure
5237 * allow loopback on pf
5240 i40e_enable_pf_lb(struct i40e_pf *pf)
5242 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5243 struct i40e_vsi_context ctxt;
5246 /* Use the FW API if FW >= v5.0 */
5247 if (hw->aq.fw_maj_ver < 5) {
5248 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5252 memset(&ctxt, 0, sizeof(ctxt));
5253 ctxt.seid = pf->main_vsi_seid;
5254 ctxt.pf_num = hw->pf_id;
5255 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5257 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5258 ret, hw->aq.asq_last_status);
5261 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5262 ctxt.info.valid_sections =
5263 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5264 ctxt.info.switch_id |=
5265 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5267 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5269 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5270 hw->aq.asq_last_status);
5275 i40e_vsi_setup(struct i40e_pf *pf,
5276 enum i40e_vsi_type type,
5277 struct i40e_vsi *uplink_vsi,
5278 uint16_t user_param)
5280 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5281 struct i40e_vsi *vsi;
5282 struct i40e_mac_filter_info filter;
5284 struct i40e_vsi_context ctxt;
5285 struct ether_addr broadcast =
5286 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5288 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5289 uplink_vsi == NULL) {
5291 "VSI setup failed, VSI link shouldn't be NULL");
5295 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5297 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5302 * 1.type is not MAIN and uplink vsi is not NULL
5303 * If uplink vsi didn't setup VEB, create one first under veb field
5304 * 2.type is SRIOV and the uplink is NULL
5305 * If floating VEB is NULL, create one veb under floating veb field
5308 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5309 uplink_vsi->veb == NULL) {
5310 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5312 if (uplink_vsi->veb == NULL) {
5313 PMD_DRV_LOG(ERR, "VEB setup failed");
5316 /* set ALLOWLOOPBACk on pf, when veb is created */
5317 i40e_enable_pf_lb(pf);
5320 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5321 pf->main_vsi->floating_veb == NULL) {
5322 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5324 if (pf->main_vsi->floating_veb == NULL) {
5325 PMD_DRV_LOG(ERR, "VEB setup failed");
5330 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5332 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5335 TAILQ_INIT(&vsi->mac_list);
5337 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5338 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5339 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5340 vsi->user_param = user_param;
5341 vsi->vlan_anti_spoof_on = 0;
5342 vsi->vlan_filter_on = 0;
5343 /* Allocate queues */
5344 switch (vsi->type) {
5345 case I40E_VSI_MAIN :
5346 vsi->nb_qps = pf->lan_nb_qps;
5348 case I40E_VSI_SRIOV :
5349 vsi->nb_qps = pf->vf_nb_qps;
5351 case I40E_VSI_VMDQ2:
5352 vsi->nb_qps = pf->vmdq_nb_qps;
5355 vsi->nb_qps = pf->fdir_nb_qps;
5361 * The filter status descriptor is reported in rx queue 0,
5362 * while the tx queue for fdir filter programming has no
5363 * such constraints, can be non-zero queues.
5364 * To simplify it, choose FDIR vsi use queue 0 pair.
5365 * To make sure it will use queue 0 pair, queue allocation
5366 * need be done before this function is called
5368 if (type != I40E_VSI_FDIR) {
5369 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5371 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5375 vsi->base_queue = ret;
5377 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5379 /* VF has MSIX interrupt in VF range, don't allocate here */
5380 if (type == I40E_VSI_MAIN) {
5381 if (pf->support_multi_driver) {
5382 /* If support multi-driver, need to use INT0 instead of
5383 * allocating from msix pool. The Msix pool is init from
5384 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5385 * to 1 without calling i40e_res_pool_alloc.
5390 ret = i40e_res_pool_alloc(&pf->msix_pool,
5391 RTE_MIN(vsi->nb_qps,
5392 RTE_MAX_RXTX_INTR_VEC_ID));
5395 "VSI MAIN %d get heap failed %d",
5397 goto fail_queue_alloc;
5399 vsi->msix_intr = ret;
5400 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5401 RTE_MAX_RXTX_INTR_VEC_ID);
5403 } else if (type != I40E_VSI_SRIOV) {
5404 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5406 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5407 goto fail_queue_alloc;
5409 vsi->msix_intr = ret;
5417 if (type == I40E_VSI_MAIN) {
5418 /* For main VSI, no need to add since it's default one */
5419 vsi->uplink_seid = pf->mac_seid;
5420 vsi->seid = pf->main_vsi_seid;
5421 /* Bind queues with specific MSIX interrupt */
5423 * Needs 2 interrupt at least, one for misc cause which will
5424 * enabled from OS side, Another for queues binding the
5425 * interrupt from device side only.
5428 /* Get default VSI parameters from hardware */
5429 memset(&ctxt, 0, sizeof(ctxt));
5430 ctxt.seid = vsi->seid;
5431 ctxt.pf_num = hw->pf_id;
5432 ctxt.uplink_seid = vsi->uplink_seid;
5434 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5435 if (ret != I40E_SUCCESS) {
5436 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5437 goto fail_msix_alloc;
5439 rte_memcpy(&vsi->info, &ctxt.info,
5440 sizeof(struct i40e_aqc_vsi_properties_data));
5441 vsi->vsi_id = ctxt.vsi_number;
5442 vsi->info.valid_sections = 0;
5444 /* Configure tc, enabled TC0 only */
5445 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5447 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5448 goto fail_msix_alloc;
5451 /* TC, queue mapping */
5452 memset(&ctxt, 0, sizeof(ctxt));
5453 vsi->info.valid_sections |=
5454 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5455 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5456 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5457 rte_memcpy(&ctxt.info, &vsi->info,
5458 sizeof(struct i40e_aqc_vsi_properties_data));
5459 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5460 I40E_DEFAULT_TCMAP);
5461 if (ret != I40E_SUCCESS) {
5463 "Failed to configure TC queue mapping");
5464 goto fail_msix_alloc;
5466 ctxt.seid = vsi->seid;
5467 ctxt.pf_num = hw->pf_id;
5468 ctxt.uplink_seid = vsi->uplink_seid;
5471 /* Update VSI parameters */
5472 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5473 if (ret != I40E_SUCCESS) {
5474 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5475 goto fail_msix_alloc;
5478 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5479 sizeof(vsi->info.tc_mapping));
5480 rte_memcpy(&vsi->info.queue_mapping,
5481 &ctxt.info.queue_mapping,
5482 sizeof(vsi->info.queue_mapping));
5483 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5484 vsi->info.valid_sections = 0;
5486 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5490 * Updating default filter settings are necessary to prevent
5491 * reception of tagged packets.
5492 * Some old firmware configurations load a default macvlan
5493 * filter which accepts both tagged and untagged packets.
5494 * The updating is to use a normal filter instead if needed.
5495 * For NVM 4.2.2 or after, the updating is not needed anymore.
5496 * The firmware with correct configurations load the default
5497 * macvlan filter which is expected and cannot be removed.
5499 i40e_update_default_filter_setting(vsi);
5500 i40e_config_qinq(hw, vsi);
5501 } else if (type == I40E_VSI_SRIOV) {
5502 memset(&ctxt, 0, sizeof(ctxt));
5504 * For other VSI, the uplink_seid equals to uplink VSI's
5505 * uplink_seid since they share same VEB
5507 if (uplink_vsi == NULL)
5508 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5510 vsi->uplink_seid = uplink_vsi->uplink_seid;
5511 ctxt.pf_num = hw->pf_id;
5512 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5513 ctxt.uplink_seid = vsi->uplink_seid;
5514 ctxt.connection_type = 0x1;
5515 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5517 /* Use the VEB configuration if FW >= v5.0 */
5518 if (hw->aq.fw_maj_ver >= 5) {
5519 /* Configure switch ID */
5520 ctxt.info.valid_sections |=
5521 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5522 ctxt.info.switch_id =
5523 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5526 /* Configure port/vlan */
5527 ctxt.info.valid_sections |=
5528 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5529 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5530 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5531 hw->func_caps.enabled_tcmap);
5532 if (ret != I40E_SUCCESS) {
5534 "Failed to configure TC queue mapping");
5535 goto fail_msix_alloc;
5538 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5539 ctxt.info.valid_sections |=
5540 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5542 * Since VSI is not created yet, only configure parameter,
5543 * will add vsi below.
5546 i40e_config_qinq(hw, vsi);
5547 } else if (type == I40E_VSI_VMDQ2) {
5548 memset(&ctxt, 0, sizeof(ctxt));
5550 * For other VSI, the uplink_seid equals to uplink VSI's
5551 * uplink_seid since they share same VEB
5553 vsi->uplink_seid = uplink_vsi->uplink_seid;
5554 ctxt.pf_num = hw->pf_id;
5556 ctxt.uplink_seid = vsi->uplink_seid;
5557 ctxt.connection_type = 0x1;
5558 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5560 ctxt.info.valid_sections |=
5561 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5562 /* user_param carries flag to enable loop back */
5564 ctxt.info.switch_id =
5565 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5566 ctxt.info.switch_id |=
5567 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5570 /* Configure port/vlan */
5571 ctxt.info.valid_sections |=
5572 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5573 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5574 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5575 I40E_DEFAULT_TCMAP);
5576 if (ret != I40E_SUCCESS) {
5578 "Failed to configure TC queue mapping");
5579 goto fail_msix_alloc;
5581 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5582 ctxt.info.valid_sections |=
5583 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5584 } else if (type == I40E_VSI_FDIR) {
5585 memset(&ctxt, 0, sizeof(ctxt));
5586 vsi->uplink_seid = uplink_vsi->uplink_seid;
5587 ctxt.pf_num = hw->pf_id;
5589 ctxt.uplink_seid = vsi->uplink_seid;
5590 ctxt.connection_type = 0x1; /* regular data port */
5591 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5592 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5593 I40E_DEFAULT_TCMAP);
5594 if (ret != I40E_SUCCESS) {
5596 "Failed to configure TC queue mapping.");
5597 goto fail_msix_alloc;
5599 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5600 ctxt.info.valid_sections |=
5601 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5603 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5604 goto fail_msix_alloc;
5607 if (vsi->type != I40E_VSI_MAIN) {
5608 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5609 if (ret != I40E_SUCCESS) {
5610 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5611 hw->aq.asq_last_status);
5612 goto fail_msix_alloc;
5614 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5615 vsi->info.valid_sections = 0;
5616 vsi->seid = ctxt.seid;
5617 vsi->vsi_id = ctxt.vsi_number;
5618 vsi->sib_vsi_list.vsi = vsi;
5619 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5620 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5621 &vsi->sib_vsi_list, list);
5623 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5624 &vsi->sib_vsi_list, list);
5628 /* MAC/VLAN configuration */
5629 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5630 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5632 ret = i40e_vsi_add_mac(vsi, &filter);
5633 if (ret != I40E_SUCCESS) {
5634 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5635 goto fail_msix_alloc;
5638 /* Get VSI BW information */
5639 i40e_vsi_get_bw_config(vsi);
5642 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5644 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5650 /* Configure vlan filter on or off */
5652 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5655 struct i40e_mac_filter *f;
5657 struct i40e_mac_filter_info *mac_filter;
5658 enum rte_mac_filter_type desired_filter;
5659 int ret = I40E_SUCCESS;
5662 /* Filter to match MAC and VLAN */
5663 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5665 /* Filter to match only MAC */
5666 desired_filter = RTE_MAC_PERFECT_MATCH;
5671 mac_filter = rte_zmalloc("mac_filter_info_data",
5672 num * sizeof(*mac_filter), 0);
5673 if (mac_filter == NULL) {
5674 PMD_DRV_LOG(ERR, "failed to allocate memory");
5675 return I40E_ERR_NO_MEMORY;
5680 /* Remove all existing mac */
5681 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5682 mac_filter[i] = f->mac_info;
5683 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5685 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5686 on ? "enable" : "disable");
5692 /* Override with new filter */
5693 for (i = 0; i < num; i++) {
5694 mac_filter[i].filter_type = desired_filter;
5695 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5697 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5698 on ? "enable" : "disable");
5704 rte_free(mac_filter);
5708 /* Configure vlan stripping on or off */
5710 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5712 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5713 struct i40e_vsi_context ctxt;
5715 int ret = I40E_SUCCESS;
5717 /* Check if it has been already on or off */
5718 if (vsi->info.valid_sections &
5719 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5721 if ((vsi->info.port_vlan_flags &
5722 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5723 return 0; /* already on */
5725 if ((vsi->info.port_vlan_flags &
5726 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5727 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5728 return 0; /* already off */
5733 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5735 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5736 vsi->info.valid_sections =
5737 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5738 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5739 vsi->info.port_vlan_flags |= vlan_flags;
5740 ctxt.seid = vsi->seid;
5741 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5742 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5744 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5745 on ? "enable" : "disable");
5751 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5753 struct rte_eth_dev_data *data = dev->data;
5757 /* Apply vlan offload setting */
5758 mask = ETH_VLAN_STRIP_MASK |
5759 ETH_VLAN_FILTER_MASK |
5760 ETH_VLAN_EXTEND_MASK;
5761 ret = i40e_vlan_offload_set(dev, mask);
5763 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5767 /* Apply pvid setting */
5768 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5769 data->dev_conf.txmode.hw_vlan_insert_pvid);
5771 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5777 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5779 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5781 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5785 i40e_update_flow_control(struct i40e_hw *hw)
5787 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5788 struct i40e_link_status link_status;
5789 uint32_t rxfc = 0, txfc = 0, reg;
5793 memset(&link_status, 0, sizeof(link_status));
5794 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5795 if (ret != I40E_SUCCESS) {
5796 PMD_DRV_LOG(ERR, "Failed to get link status information");
5797 goto write_reg; /* Disable flow control */
5800 an_info = hw->phy.link_info.an_info;
5801 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5802 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5803 ret = I40E_ERR_NOT_READY;
5804 goto write_reg; /* Disable flow control */
5807 * If link auto negotiation is enabled, flow control needs to
5808 * be configured according to it
5810 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5811 case I40E_LINK_PAUSE_RXTX:
5814 hw->fc.current_mode = I40E_FC_FULL;
5816 case I40E_AQ_LINK_PAUSE_RX:
5818 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5820 case I40E_AQ_LINK_PAUSE_TX:
5822 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5825 hw->fc.current_mode = I40E_FC_NONE;
5830 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5831 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5832 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5833 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5834 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5835 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5842 i40e_pf_setup(struct i40e_pf *pf)
5844 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5845 struct i40e_filter_control_settings settings;
5846 struct i40e_vsi *vsi;
5849 /* Clear all stats counters */
5850 pf->offset_loaded = FALSE;
5851 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5852 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5853 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5854 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5856 ret = i40e_pf_get_switch_config(pf);
5857 if (ret != I40E_SUCCESS) {
5858 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5862 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5864 PMD_INIT_LOG(WARNING,
5865 "failed to allocate switch domain for device %d", ret);
5867 if (pf->flags & I40E_FLAG_FDIR) {
5868 /* make queue allocated first, let FDIR use queue pair 0*/
5869 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5870 if (ret != I40E_FDIR_QUEUE_ID) {
5872 "queue allocation fails for FDIR: ret =%d",
5874 pf->flags &= ~I40E_FLAG_FDIR;
5877 /* main VSI setup */
5878 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5880 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5881 return I40E_ERR_NOT_READY;
5885 /* Configure filter control */
5886 memset(&settings, 0, sizeof(settings));
5887 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5888 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5889 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5890 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5892 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5893 hw->func_caps.rss_table_size);
5894 return I40E_ERR_PARAM;
5896 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5897 hw->func_caps.rss_table_size);
5898 pf->hash_lut_size = hw->func_caps.rss_table_size;
5900 /* Enable ethtype and macvlan filters */
5901 settings.enable_ethtype = TRUE;
5902 settings.enable_macvlan = TRUE;
5903 ret = i40e_set_filter_control(hw, &settings);
5905 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5908 /* Update flow control according to the auto negotiation */
5909 i40e_update_flow_control(hw);
5911 return I40E_SUCCESS;
5915 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5921 * Set or clear TX Queue Disable flags,
5922 * which is required by hardware.
5924 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5925 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5927 /* Wait until the request is finished */
5928 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5929 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5930 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5931 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5932 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5938 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5939 return I40E_SUCCESS; /* already on, skip next steps */
5941 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5942 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5944 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5945 return I40E_SUCCESS; /* already off, skip next steps */
5946 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5948 /* Write the register */
5949 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5950 /* Check the result */
5951 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5952 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5953 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5955 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5956 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5959 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5960 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5964 /* Check if it is timeout */
5965 if (j >= I40E_CHK_Q_ENA_COUNT) {
5966 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5967 (on ? "enable" : "disable"), q_idx);
5968 return I40E_ERR_TIMEOUT;
5971 return I40E_SUCCESS;
5974 /* Swith on or off the tx queues */
5976 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5978 struct rte_eth_dev_data *dev_data = pf->dev_data;
5979 struct i40e_tx_queue *txq;
5980 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5984 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5985 txq = dev_data->tx_queues[i];
5986 /* Don't operate the queue if not configured or
5987 * if starting only per queue */
5988 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5991 ret = i40e_dev_tx_queue_start(dev, i);
5993 ret = i40e_dev_tx_queue_stop(dev, i);
5994 if ( ret != I40E_SUCCESS)
5998 return I40E_SUCCESS;
6002 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6007 /* Wait until the request is finished */
6008 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6009 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6010 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6011 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6012 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6017 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6018 return I40E_SUCCESS; /* Already on, skip next steps */
6019 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6021 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6022 return I40E_SUCCESS; /* Already off, skip next steps */
6023 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6026 /* Write the register */
6027 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6028 /* Check the result */
6029 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6030 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6031 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6033 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6034 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6037 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6038 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6043 /* Check if it is timeout */
6044 if (j >= I40E_CHK_Q_ENA_COUNT) {
6045 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6046 (on ? "enable" : "disable"), q_idx);
6047 return I40E_ERR_TIMEOUT;
6050 return I40E_SUCCESS;
6052 /* Switch on or off the rx queues */
6054 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6056 struct rte_eth_dev_data *dev_data = pf->dev_data;
6057 struct i40e_rx_queue *rxq;
6058 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6062 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6063 rxq = dev_data->rx_queues[i];
6064 /* Don't operate the queue if not configured or
6065 * if starting only per queue */
6066 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6069 ret = i40e_dev_rx_queue_start(dev, i);
6071 ret = i40e_dev_rx_queue_stop(dev, i);
6072 if (ret != I40E_SUCCESS)
6076 return I40E_SUCCESS;
6079 /* Switch on or off all the rx/tx queues */
6081 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6086 /* enable rx queues before enabling tx queues */
6087 ret = i40e_dev_switch_rx_queues(pf, on);
6089 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6092 ret = i40e_dev_switch_tx_queues(pf, on);
6094 /* Stop tx queues before stopping rx queues */
6095 ret = i40e_dev_switch_tx_queues(pf, on);
6097 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6100 ret = i40e_dev_switch_rx_queues(pf, on);
6106 /* Initialize VSI for TX */
6108 i40e_dev_tx_init(struct i40e_pf *pf)
6110 struct rte_eth_dev_data *data = pf->dev_data;
6112 uint32_t ret = I40E_SUCCESS;
6113 struct i40e_tx_queue *txq;
6115 for (i = 0; i < data->nb_tx_queues; i++) {
6116 txq = data->tx_queues[i];
6117 if (!txq || !txq->q_set)
6119 ret = i40e_tx_queue_init(txq);
6120 if (ret != I40E_SUCCESS)
6123 if (ret == I40E_SUCCESS)
6124 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6130 /* Initialize VSI for RX */
6132 i40e_dev_rx_init(struct i40e_pf *pf)
6134 struct rte_eth_dev_data *data = pf->dev_data;
6135 int ret = I40E_SUCCESS;
6137 struct i40e_rx_queue *rxq;
6139 i40e_pf_config_mq_rx(pf);
6140 for (i = 0; i < data->nb_rx_queues; i++) {
6141 rxq = data->rx_queues[i];
6142 if (!rxq || !rxq->q_set)
6145 ret = i40e_rx_queue_init(rxq);
6146 if (ret != I40E_SUCCESS) {
6148 "Failed to do RX queue initialization");
6152 if (ret == I40E_SUCCESS)
6153 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6160 i40e_dev_rxtx_init(struct i40e_pf *pf)
6164 err = i40e_dev_tx_init(pf);
6166 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6169 err = i40e_dev_rx_init(pf);
6171 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6179 i40e_vmdq_setup(struct rte_eth_dev *dev)
6181 struct rte_eth_conf *conf = &dev->data->dev_conf;
6182 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6183 int i, err, conf_vsis, j, loop;
6184 struct i40e_vsi *vsi;
6185 struct i40e_vmdq_info *vmdq_info;
6186 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6187 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6190 * Disable interrupt to avoid message from VF. Furthermore, it will
6191 * avoid race condition in VSI creation/destroy.
6193 i40e_pf_disable_irq0(hw);
6195 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6196 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6200 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6201 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6202 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6203 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6204 pf->max_nb_vmdq_vsi);
6208 if (pf->vmdq != NULL) {
6209 PMD_INIT_LOG(INFO, "VMDQ already configured");
6213 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6214 sizeof(*vmdq_info) * conf_vsis, 0);
6216 if (pf->vmdq == NULL) {
6217 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6221 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6223 /* Create VMDQ VSI */
6224 for (i = 0; i < conf_vsis; i++) {
6225 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6226 vmdq_conf->enable_loop_back);
6228 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6232 vmdq_info = &pf->vmdq[i];
6234 vmdq_info->vsi = vsi;
6236 pf->nb_cfg_vmdq_vsi = conf_vsis;
6238 /* Configure Vlan */
6239 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6240 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6241 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6242 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6243 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6244 vmdq_conf->pool_map[i].vlan_id, j);
6246 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6247 vmdq_conf->pool_map[i].vlan_id);
6249 PMD_INIT_LOG(ERR, "Failed to add vlan");
6257 i40e_pf_enable_irq0(hw);
6262 for (i = 0; i < conf_vsis; i++)
6263 if (pf->vmdq[i].vsi == NULL)
6266 i40e_vsi_release(pf->vmdq[i].vsi);
6270 i40e_pf_enable_irq0(hw);
6275 i40e_stat_update_32(struct i40e_hw *hw,
6283 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6287 if (new_data >= *offset)
6288 *stat = (uint64_t)(new_data - *offset);
6290 *stat = (uint64_t)((new_data +
6291 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6295 i40e_stat_update_48(struct i40e_hw *hw,
6304 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6305 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6306 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6311 if (new_data >= *offset)
6312 *stat = new_data - *offset;
6314 *stat = (uint64_t)((new_data +
6315 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6317 *stat &= I40E_48_BIT_MASK;
6322 i40e_pf_disable_irq0(struct i40e_hw *hw)
6324 /* Disable all interrupt types */
6325 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6326 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6327 I40E_WRITE_FLUSH(hw);
6332 i40e_pf_enable_irq0(struct i40e_hw *hw)
6334 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6335 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6336 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6337 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6338 I40E_WRITE_FLUSH(hw);
6342 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6344 /* read pending request and disable first */
6345 i40e_pf_disable_irq0(hw);
6346 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6347 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6348 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6351 /* Link no queues with irq0 */
6352 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6353 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6357 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6359 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6360 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6363 uint32_t index, offset, val;
6368 * Try to find which VF trigger a reset, use absolute VF id to access
6369 * since the reg is global register.
6371 for (i = 0; i < pf->vf_num; i++) {
6372 abs_vf_id = hw->func_caps.vf_base_id + i;
6373 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6374 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6375 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6376 /* VFR event occurred */
6377 if (val & (0x1 << offset)) {
6380 /* Clear the event first */
6381 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6383 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6385 * Only notify a VF reset event occurred,
6386 * don't trigger another SW reset
6388 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6389 if (ret != I40E_SUCCESS)
6390 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6396 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6398 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6401 for (i = 0; i < pf->vf_num; i++)
6402 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6406 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6408 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6409 struct i40e_arq_event_info info;
6410 uint16_t pending, opcode;
6413 info.buf_len = I40E_AQ_BUF_SZ;
6414 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6415 if (!info.msg_buf) {
6416 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6422 ret = i40e_clean_arq_element(hw, &info, &pending);
6424 if (ret != I40E_SUCCESS) {
6426 "Failed to read msg from AdminQ, aq_err: %u",
6427 hw->aq.asq_last_status);
6430 opcode = rte_le_to_cpu_16(info.desc.opcode);
6433 case i40e_aqc_opc_send_msg_to_pf:
6434 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6435 i40e_pf_host_handle_vf_msg(dev,
6436 rte_le_to_cpu_16(info.desc.retval),
6437 rte_le_to_cpu_32(info.desc.cookie_high),
6438 rte_le_to_cpu_32(info.desc.cookie_low),
6442 case i40e_aqc_opc_get_link_status:
6443 ret = i40e_dev_link_update(dev, 0);
6445 _rte_eth_dev_callback_process(dev,
6446 RTE_ETH_EVENT_INTR_LSC, NULL);
6449 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6454 rte_free(info.msg_buf);
6458 * Interrupt handler triggered by NIC for handling
6459 * specific interrupt.
6462 * Pointer to interrupt handle.
6464 * The address of parameter (struct rte_eth_dev *) regsitered before.
6470 i40e_dev_interrupt_handler(void *param)
6472 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6473 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6476 /* Disable interrupt */
6477 i40e_pf_disable_irq0(hw);
6479 /* read out interrupt causes */
6480 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6482 /* No interrupt event indicated */
6483 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6484 PMD_DRV_LOG(INFO, "No interrupt event");
6487 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6488 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6489 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6490 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6491 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6492 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6493 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6494 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6495 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6496 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6497 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6498 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6499 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6500 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6502 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6503 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6504 i40e_dev_handle_vfr_event(dev);
6506 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6507 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6508 i40e_dev_handle_aq_msg(dev);
6512 /* Enable interrupt */
6513 i40e_pf_enable_irq0(hw);
6514 rte_intr_enable(dev->intr_handle);
6518 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6519 struct i40e_macvlan_filter *filter,
6522 int ele_num, ele_buff_size;
6523 int num, actual_num, i;
6525 int ret = I40E_SUCCESS;
6526 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6527 struct i40e_aqc_add_macvlan_element_data *req_list;
6529 if (filter == NULL || total == 0)
6530 return I40E_ERR_PARAM;
6531 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6532 ele_buff_size = hw->aq.asq_buf_size;
6534 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6535 if (req_list == NULL) {
6536 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6537 return I40E_ERR_NO_MEMORY;
6542 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6543 memset(req_list, 0, ele_buff_size);
6545 for (i = 0; i < actual_num; i++) {
6546 rte_memcpy(req_list[i].mac_addr,
6547 &filter[num + i].macaddr, ETH_ADDR_LEN);
6548 req_list[i].vlan_tag =
6549 rte_cpu_to_le_16(filter[num + i].vlan_id);
6551 switch (filter[num + i].filter_type) {
6552 case RTE_MAC_PERFECT_MATCH:
6553 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6554 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6556 case RTE_MACVLAN_PERFECT_MATCH:
6557 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6559 case RTE_MAC_HASH_MATCH:
6560 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6561 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6563 case RTE_MACVLAN_HASH_MATCH:
6564 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6567 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6568 ret = I40E_ERR_PARAM;
6572 req_list[i].queue_number = 0;
6574 req_list[i].flags = rte_cpu_to_le_16(flags);
6577 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6579 if (ret != I40E_SUCCESS) {
6580 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6584 } while (num < total);
6592 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6593 struct i40e_macvlan_filter *filter,
6596 int ele_num, ele_buff_size;
6597 int num, actual_num, i;
6599 int ret = I40E_SUCCESS;
6600 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6601 struct i40e_aqc_remove_macvlan_element_data *req_list;
6603 if (filter == NULL || total == 0)
6604 return I40E_ERR_PARAM;
6606 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6607 ele_buff_size = hw->aq.asq_buf_size;
6609 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6610 if (req_list == NULL) {
6611 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6612 return I40E_ERR_NO_MEMORY;
6617 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6618 memset(req_list, 0, ele_buff_size);
6620 for (i = 0; i < actual_num; i++) {
6621 rte_memcpy(req_list[i].mac_addr,
6622 &filter[num + i].macaddr, ETH_ADDR_LEN);
6623 req_list[i].vlan_tag =
6624 rte_cpu_to_le_16(filter[num + i].vlan_id);
6626 switch (filter[num + i].filter_type) {
6627 case RTE_MAC_PERFECT_MATCH:
6628 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6629 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6631 case RTE_MACVLAN_PERFECT_MATCH:
6632 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6634 case RTE_MAC_HASH_MATCH:
6635 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6636 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6638 case RTE_MACVLAN_HASH_MATCH:
6639 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6642 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6643 ret = I40E_ERR_PARAM;
6646 req_list[i].flags = rte_cpu_to_le_16(flags);
6649 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6651 if (ret != I40E_SUCCESS) {
6652 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6656 } while (num < total);
6663 /* Find out specific MAC filter */
6664 static struct i40e_mac_filter *
6665 i40e_find_mac_filter(struct i40e_vsi *vsi,
6666 struct ether_addr *macaddr)
6668 struct i40e_mac_filter *f;
6670 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6671 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6679 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6682 uint32_t vid_idx, vid_bit;
6684 if (vlan_id > ETH_VLAN_ID_MAX)
6687 vid_idx = I40E_VFTA_IDX(vlan_id);
6688 vid_bit = I40E_VFTA_BIT(vlan_id);
6690 if (vsi->vfta[vid_idx] & vid_bit)
6697 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6698 uint16_t vlan_id, bool on)
6700 uint32_t vid_idx, vid_bit;
6702 vid_idx = I40E_VFTA_IDX(vlan_id);
6703 vid_bit = I40E_VFTA_BIT(vlan_id);
6706 vsi->vfta[vid_idx] |= vid_bit;
6708 vsi->vfta[vid_idx] &= ~vid_bit;
6712 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6713 uint16_t vlan_id, bool on)
6715 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6716 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6719 if (vlan_id > ETH_VLAN_ID_MAX)
6722 i40e_store_vlan_filter(vsi, vlan_id, on);
6724 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6727 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6730 ret = i40e_aq_add_vlan(hw, vsi->seid,
6731 &vlan_data, 1, NULL);
6732 if (ret != I40E_SUCCESS)
6733 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6735 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6736 &vlan_data, 1, NULL);
6737 if (ret != I40E_SUCCESS)
6739 "Failed to remove vlan filter");
6744 * Find all vlan options for specific mac addr,
6745 * return with actual vlan found.
6748 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6749 struct i40e_macvlan_filter *mv_f,
6750 int num, struct ether_addr *addr)
6756 * Not to use i40e_find_vlan_filter to decrease the loop time,
6757 * although the code looks complex.
6759 if (num < vsi->vlan_num)
6760 return I40E_ERR_PARAM;
6763 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6765 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6766 if (vsi->vfta[j] & (1 << k)) {
6769 "vlan number doesn't match");
6770 return I40E_ERR_PARAM;
6772 rte_memcpy(&mv_f[i].macaddr,
6773 addr, ETH_ADDR_LEN);
6775 j * I40E_UINT32_BIT_SIZE + k;
6781 return I40E_SUCCESS;
6785 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6786 struct i40e_macvlan_filter *mv_f,
6791 struct i40e_mac_filter *f;
6793 if (num < vsi->mac_num)
6794 return I40E_ERR_PARAM;
6796 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6798 PMD_DRV_LOG(ERR, "buffer number not match");
6799 return I40E_ERR_PARAM;
6801 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6803 mv_f[i].vlan_id = vlan;
6804 mv_f[i].filter_type = f->mac_info.filter_type;
6808 return I40E_SUCCESS;
6812 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6815 struct i40e_mac_filter *f;
6816 struct i40e_macvlan_filter *mv_f;
6817 int ret = I40E_SUCCESS;
6819 if (vsi == NULL || vsi->mac_num == 0)
6820 return I40E_ERR_PARAM;
6822 /* Case that no vlan is set */
6823 if (vsi->vlan_num == 0)
6826 num = vsi->mac_num * vsi->vlan_num;
6828 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6830 PMD_DRV_LOG(ERR, "failed to allocate memory");
6831 return I40E_ERR_NO_MEMORY;
6835 if (vsi->vlan_num == 0) {
6836 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6837 rte_memcpy(&mv_f[i].macaddr,
6838 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6839 mv_f[i].filter_type = f->mac_info.filter_type;
6840 mv_f[i].vlan_id = 0;
6844 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6845 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6846 vsi->vlan_num, &f->mac_info.mac_addr);
6847 if (ret != I40E_SUCCESS)
6849 for (j = i; j < i + vsi->vlan_num; j++)
6850 mv_f[j].filter_type = f->mac_info.filter_type;
6855 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6863 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6865 struct i40e_macvlan_filter *mv_f;
6867 int ret = I40E_SUCCESS;
6869 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6870 return I40E_ERR_PARAM;
6872 /* If it's already set, just return */
6873 if (i40e_find_vlan_filter(vsi,vlan))
6874 return I40E_SUCCESS;
6876 mac_num = vsi->mac_num;
6879 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6880 return I40E_ERR_PARAM;
6883 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6886 PMD_DRV_LOG(ERR, "failed to allocate memory");
6887 return I40E_ERR_NO_MEMORY;
6890 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6892 if (ret != I40E_SUCCESS)
6895 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6897 if (ret != I40E_SUCCESS)
6900 i40e_set_vlan_filter(vsi, vlan, 1);
6910 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6912 struct i40e_macvlan_filter *mv_f;
6914 int ret = I40E_SUCCESS;
6917 * Vlan 0 is the generic filter for untagged packets
6918 * and can't be removed.
6920 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6921 return I40E_ERR_PARAM;
6923 /* If can't find it, just return */
6924 if (!i40e_find_vlan_filter(vsi, vlan))
6925 return I40E_ERR_PARAM;
6927 mac_num = vsi->mac_num;
6930 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6931 return I40E_ERR_PARAM;
6934 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6937 PMD_DRV_LOG(ERR, "failed to allocate memory");
6938 return I40E_ERR_NO_MEMORY;
6941 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6943 if (ret != I40E_SUCCESS)
6946 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6948 if (ret != I40E_SUCCESS)
6951 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6952 if (vsi->vlan_num == 1) {
6953 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6954 if (ret != I40E_SUCCESS)
6957 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6958 if (ret != I40E_SUCCESS)
6962 i40e_set_vlan_filter(vsi, vlan, 0);
6972 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6974 struct i40e_mac_filter *f;
6975 struct i40e_macvlan_filter *mv_f;
6976 int i, vlan_num = 0;
6977 int ret = I40E_SUCCESS;
6979 /* If it's add and we've config it, return */
6980 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6982 return I40E_SUCCESS;
6983 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6984 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6987 * If vlan_num is 0, that's the first time to add mac,
6988 * set mask for vlan_id 0.
6990 if (vsi->vlan_num == 0) {
6991 i40e_set_vlan_filter(vsi, 0, 1);
6994 vlan_num = vsi->vlan_num;
6995 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6996 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6999 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7001 PMD_DRV_LOG(ERR, "failed to allocate memory");
7002 return I40E_ERR_NO_MEMORY;
7005 for (i = 0; i < vlan_num; i++) {
7006 mv_f[i].filter_type = mac_filter->filter_type;
7007 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7011 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7012 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7013 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7014 &mac_filter->mac_addr);
7015 if (ret != I40E_SUCCESS)
7019 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7020 if (ret != I40E_SUCCESS)
7023 /* Add the mac addr into mac list */
7024 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7026 PMD_DRV_LOG(ERR, "failed to allocate memory");
7027 ret = I40E_ERR_NO_MEMORY;
7030 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7032 f->mac_info.filter_type = mac_filter->filter_type;
7033 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7044 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7046 struct i40e_mac_filter *f;
7047 struct i40e_macvlan_filter *mv_f;
7049 enum rte_mac_filter_type filter_type;
7050 int ret = I40E_SUCCESS;
7052 /* Can't find it, return an error */
7053 f = i40e_find_mac_filter(vsi, addr);
7055 return I40E_ERR_PARAM;
7057 vlan_num = vsi->vlan_num;
7058 filter_type = f->mac_info.filter_type;
7059 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7060 filter_type == RTE_MACVLAN_HASH_MATCH) {
7061 if (vlan_num == 0) {
7062 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7063 return I40E_ERR_PARAM;
7065 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7066 filter_type == RTE_MAC_HASH_MATCH)
7069 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7071 PMD_DRV_LOG(ERR, "failed to allocate memory");
7072 return I40E_ERR_NO_MEMORY;
7075 for (i = 0; i < vlan_num; i++) {
7076 mv_f[i].filter_type = filter_type;
7077 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7080 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7081 filter_type == RTE_MACVLAN_HASH_MATCH) {
7082 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7083 if (ret != I40E_SUCCESS)
7087 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7088 if (ret != I40E_SUCCESS)
7091 /* Remove the mac addr into mac list */
7092 TAILQ_REMOVE(&vsi->mac_list, f, next);
7102 /* Configure hash enable flags for RSS */
7104 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7112 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7113 if (flags & (1ULL << i))
7114 hena |= adapter->pctypes_tbl[i];
7120 /* Parse the hash enable flags */
7122 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7124 uint64_t rss_hf = 0;
7130 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7131 if (flags & adapter->pctypes_tbl[i])
7132 rss_hf |= (1ULL << i);
7139 i40e_pf_disable_rss(struct i40e_pf *pf)
7141 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7143 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7144 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7145 I40E_WRITE_FLUSH(hw);
7149 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7151 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7152 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7153 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7154 I40E_VFQF_HKEY_MAX_INDEX :
7155 I40E_PFQF_HKEY_MAX_INDEX;
7158 if (!key || key_len == 0) {
7159 PMD_DRV_LOG(DEBUG, "No key to be configured");
7161 } else if (key_len != (key_idx + 1) *
7163 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7167 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7168 struct i40e_aqc_get_set_rss_key_data *key_dw =
7169 (struct i40e_aqc_get_set_rss_key_data *)key;
7171 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7173 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7175 uint32_t *hash_key = (uint32_t *)key;
7178 if (vsi->type == I40E_VSI_SRIOV) {
7179 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7182 I40E_VFQF_HKEY1(i, vsi->user_param),
7186 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7187 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7190 I40E_WRITE_FLUSH(hw);
7197 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7199 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7200 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7204 if (!key || !key_len)
7207 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7208 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7209 (struct i40e_aqc_get_set_rss_key_data *)key);
7211 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7215 uint32_t *key_dw = (uint32_t *)key;
7218 if (vsi->type == I40E_VSI_SRIOV) {
7219 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7220 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7221 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7223 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7226 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7227 reg = I40E_PFQF_HKEY(i);
7228 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7230 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7238 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7240 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7244 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7245 rss_conf->rss_key_len);
7249 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7250 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7251 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7252 I40E_WRITE_FLUSH(hw);
7258 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7259 struct rte_eth_rss_conf *rss_conf)
7261 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7262 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7263 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7266 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7267 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7269 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7270 if (rss_hf != 0) /* Enable RSS */
7272 return 0; /* Nothing to do */
7275 if (rss_hf == 0) /* Disable RSS */
7278 return i40e_hw_rss_hash_set(pf, rss_conf);
7282 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7283 struct rte_eth_rss_conf *rss_conf)
7285 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7286 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7289 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7290 &rss_conf->rss_key_len);
7292 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7293 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7294 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7300 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7302 switch (filter_type) {
7303 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7304 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7306 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7307 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7309 case RTE_TUNNEL_FILTER_IMAC_TENID:
7310 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7312 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7313 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7315 case ETH_TUNNEL_FILTER_IMAC:
7316 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7318 case ETH_TUNNEL_FILTER_OIP:
7319 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7321 case ETH_TUNNEL_FILTER_IIP:
7322 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7325 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7332 /* Convert tunnel filter structure */
7334 i40e_tunnel_filter_convert(
7335 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7336 struct i40e_tunnel_filter *tunnel_filter)
7338 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7339 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7340 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7341 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7342 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7343 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7344 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7345 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7346 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7348 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7349 tunnel_filter->input.flags = cld_filter->element.flags;
7350 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7351 tunnel_filter->queue = cld_filter->element.queue_number;
7352 rte_memcpy(tunnel_filter->input.general_fields,
7353 cld_filter->general_fields,
7354 sizeof(cld_filter->general_fields));
7359 /* Check if there exists the tunnel filter */
7360 struct i40e_tunnel_filter *
7361 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7362 const struct i40e_tunnel_filter_input *input)
7366 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7370 return tunnel_rule->hash_map[ret];
7373 /* Add a tunnel filter into the SW list */
7375 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7376 struct i40e_tunnel_filter *tunnel_filter)
7378 struct i40e_tunnel_rule *rule = &pf->tunnel;
7381 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7384 "Failed to insert tunnel filter to hash table %d!",
7388 rule->hash_map[ret] = tunnel_filter;
7390 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7395 /* Delete a tunnel filter from the SW list */
7397 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7398 struct i40e_tunnel_filter_input *input)
7400 struct i40e_tunnel_rule *rule = &pf->tunnel;
7401 struct i40e_tunnel_filter *tunnel_filter;
7404 ret = rte_hash_del_key(rule->hash_table, input);
7407 "Failed to delete tunnel filter to hash table %d!",
7411 tunnel_filter = rule->hash_map[ret];
7412 rule->hash_map[ret] = NULL;
7414 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7415 rte_free(tunnel_filter);
7421 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7422 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7426 uint32_t ipv4_addr, ipv4_addr_le;
7427 uint8_t i, tun_type = 0;
7428 /* internal varialbe to convert ipv6 byte order */
7429 uint32_t convert_ipv6[4];
7431 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7432 struct i40e_vsi *vsi = pf->main_vsi;
7433 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7434 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7435 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7436 struct i40e_tunnel_filter *tunnel, *node;
7437 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7439 cld_filter = rte_zmalloc("tunnel_filter",
7440 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7443 if (NULL == cld_filter) {
7444 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7447 pfilter = cld_filter;
7449 ether_addr_copy(&tunnel_filter->outer_mac,
7450 (struct ether_addr *)&pfilter->element.outer_mac);
7451 ether_addr_copy(&tunnel_filter->inner_mac,
7452 (struct ether_addr *)&pfilter->element.inner_mac);
7454 pfilter->element.inner_vlan =
7455 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7456 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7457 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7458 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7459 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7460 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7462 sizeof(pfilter->element.ipaddr.v4.data));
7464 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7465 for (i = 0; i < 4; i++) {
7467 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7469 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7471 sizeof(pfilter->element.ipaddr.v6.data));
7474 /* check tunneled type */
7475 switch (tunnel_filter->tunnel_type) {
7476 case RTE_TUNNEL_TYPE_VXLAN:
7477 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7479 case RTE_TUNNEL_TYPE_NVGRE:
7480 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7482 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7483 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7486 /* Other tunnel types is not supported. */
7487 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7488 rte_free(cld_filter);
7492 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7493 &pfilter->element.flags);
7495 rte_free(cld_filter);
7499 pfilter->element.flags |= rte_cpu_to_le_16(
7500 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7501 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7502 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7503 pfilter->element.queue_number =
7504 rte_cpu_to_le_16(tunnel_filter->queue_id);
7506 /* Check if there is the filter in SW list */
7507 memset(&check_filter, 0, sizeof(check_filter));
7508 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7509 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7511 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7512 rte_free(cld_filter);
7516 if (!add && !node) {
7517 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7518 rte_free(cld_filter);
7523 ret = i40e_aq_add_cloud_filters(hw,
7524 vsi->seid, &cld_filter->element, 1);
7526 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7527 rte_free(cld_filter);
7530 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7531 if (tunnel == NULL) {
7532 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7533 rte_free(cld_filter);
7537 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7538 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7542 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7543 &cld_filter->element, 1);
7545 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7546 rte_free(cld_filter);
7549 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7552 rte_free(cld_filter);
7556 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7557 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7558 #define I40E_TR_GENEVE_KEY_MASK 0x8
7559 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7560 #define I40E_TR_GRE_KEY_MASK 0x400
7561 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7562 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7565 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7567 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7568 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7569 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7570 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7571 enum i40e_status_code status = I40E_SUCCESS;
7573 if (pf->support_multi_driver) {
7574 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7575 return I40E_NOT_SUPPORTED;
7578 memset(&filter_replace, 0,
7579 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7580 memset(&filter_replace_buf, 0,
7581 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7583 /* create L1 filter */
7584 filter_replace.old_filter_type =
7585 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7586 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7587 filter_replace.tr_bit = 0;
7589 /* Prepare the buffer, 3 entries */
7590 filter_replace_buf.data[0] =
7591 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7592 filter_replace_buf.data[0] |=
7593 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7594 filter_replace_buf.data[2] = 0xFF;
7595 filter_replace_buf.data[3] = 0xFF;
7596 filter_replace_buf.data[4] =
7597 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7598 filter_replace_buf.data[4] |=
7599 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7600 filter_replace_buf.data[7] = 0xF0;
7601 filter_replace_buf.data[8]
7602 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7603 filter_replace_buf.data[8] |=
7604 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7605 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7606 I40E_TR_GENEVE_KEY_MASK |
7607 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7608 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7609 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7610 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7612 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7613 &filter_replace_buf);
7614 if (!status && (filter_replace.old_filter_type !=
7615 filter_replace.new_filter_type))
7616 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7617 " original: 0x%x, new: 0x%x",
7619 filter_replace.old_filter_type,
7620 filter_replace.new_filter_type);
7626 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7628 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7629 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7630 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7631 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7632 enum i40e_status_code status = I40E_SUCCESS;
7634 if (pf->support_multi_driver) {
7635 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7636 return I40E_NOT_SUPPORTED;
7640 memset(&filter_replace, 0,
7641 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7642 memset(&filter_replace_buf, 0,
7643 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7644 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7645 I40E_AQC_MIRROR_CLOUD_FILTER;
7646 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7647 filter_replace.new_filter_type =
7648 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7649 /* Prepare the buffer, 2 entries */
7650 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7651 filter_replace_buf.data[0] |=
7652 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7653 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7654 filter_replace_buf.data[4] |=
7655 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7656 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7657 &filter_replace_buf);
7660 if (filter_replace.old_filter_type !=
7661 filter_replace.new_filter_type)
7662 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7663 " original: 0x%x, new: 0x%x",
7665 filter_replace.old_filter_type,
7666 filter_replace.new_filter_type);
7669 memset(&filter_replace, 0,
7670 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7671 memset(&filter_replace_buf, 0,
7672 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7674 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7675 I40E_AQC_MIRROR_CLOUD_FILTER;
7676 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7677 filter_replace.new_filter_type =
7678 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7679 /* Prepare the buffer, 2 entries */
7680 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7681 filter_replace_buf.data[0] |=
7682 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7683 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7684 filter_replace_buf.data[4] |=
7685 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7687 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7688 &filter_replace_buf);
7689 if (!status && (filter_replace.old_filter_type !=
7690 filter_replace.new_filter_type))
7691 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7692 " original: 0x%x, new: 0x%x",
7694 filter_replace.old_filter_type,
7695 filter_replace.new_filter_type);
7700 static enum i40e_status_code
7701 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7703 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7704 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7705 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7706 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7707 enum i40e_status_code status = I40E_SUCCESS;
7709 if (pf->support_multi_driver) {
7710 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7711 return I40E_NOT_SUPPORTED;
7715 memset(&filter_replace, 0,
7716 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7717 memset(&filter_replace_buf, 0,
7718 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7719 /* create L1 filter */
7720 filter_replace.old_filter_type =
7721 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7722 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7723 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7724 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7725 /* Prepare the buffer, 2 entries */
7726 filter_replace_buf.data[0] =
7727 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7728 filter_replace_buf.data[0] |=
7729 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7730 filter_replace_buf.data[2] = 0xFF;
7731 filter_replace_buf.data[3] = 0xFF;
7732 filter_replace_buf.data[4] =
7733 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7734 filter_replace_buf.data[4] |=
7735 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7736 filter_replace_buf.data[6] = 0xFF;
7737 filter_replace_buf.data[7] = 0xFF;
7738 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7739 &filter_replace_buf);
7742 if (filter_replace.old_filter_type !=
7743 filter_replace.new_filter_type)
7744 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7745 " original: 0x%x, new: 0x%x",
7747 filter_replace.old_filter_type,
7748 filter_replace.new_filter_type);
7751 memset(&filter_replace, 0,
7752 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7753 memset(&filter_replace_buf, 0,
7754 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7755 /* create L1 filter */
7756 filter_replace.old_filter_type =
7757 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7758 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7759 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7760 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7761 /* Prepare the buffer, 2 entries */
7762 filter_replace_buf.data[0] =
7763 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7764 filter_replace_buf.data[0] |=
7765 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7766 filter_replace_buf.data[2] = 0xFF;
7767 filter_replace_buf.data[3] = 0xFF;
7768 filter_replace_buf.data[4] =
7769 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7770 filter_replace_buf.data[4] |=
7771 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7772 filter_replace_buf.data[6] = 0xFF;
7773 filter_replace_buf.data[7] = 0xFF;
7775 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7776 &filter_replace_buf);
7777 if (!status && (filter_replace.old_filter_type !=
7778 filter_replace.new_filter_type))
7779 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7780 " original: 0x%x, new: 0x%x",
7782 filter_replace.old_filter_type,
7783 filter_replace.new_filter_type);
7789 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7791 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7792 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7793 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7794 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7795 enum i40e_status_code status = I40E_SUCCESS;
7797 if (pf->support_multi_driver) {
7798 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7799 return I40E_NOT_SUPPORTED;
7803 memset(&filter_replace, 0,
7804 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7805 memset(&filter_replace_buf, 0,
7806 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7807 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7808 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7809 filter_replace.new_filter_type =
7810 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7811 /* Prepare the buffer, 2 entries */
7812 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7813 filter_replace_buf.data[0] |=
7814 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7815 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7816 filter_replace_buf.data[4] |=
7817 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7818 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7819 &filter_replace_buf);
7822 if (filter_replace.old_filter_type !=
7823 filter_replace.new_filter_type)
7824 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7825 " original: 0x%x, new: 0x%x",
7827 filter_replace.old_filter_type,
7828 filter_replace.new_filter_type);
7831 memset(&filter_replace, 0,
7832 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7833 memset(&filter_replace_buf, 0,
7834 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7835 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7836 filter_replace.old_filter_type =
7837 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7838 filter_replace.new_filter_type =
7839 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7840 /* Prepare the buffer, 2 entries */
7841 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7842 filter_replace_buf.data[0] |=
7843 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7844 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7845 filter_replace_buf.data[4] |=
7846 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7848 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7849 &filter_replace_buf);
7850 if (!status && (filter_replace.old_filter_type !=
7851 filter_replace.new_filter_type))
7852 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7853 " original: 0x%x, new: 0x%x",
7855 filter_replace.old_filter_type,
7856 filter_replace.new_filter_type);
7862 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7863 struct i40e_tunnel_filter_conf *tunnel_filter,
7867 uint32_t ipv4_addr, ipv4_addr_le;
7868 uint8_t i, tun_type = 0;
7869 /* internal variable to convert ipv6 byte order */
7870 uint32_t convert_ipv6[4];
7872 struct i40e_pf_vf *vf = NULL;
7873 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7874 struct i40e_vsi *vsi;
7875 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7876 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7877 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7878 struct i40e_tunnel_filter *tunnel, *node;
7879 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7881 bool big_buffer = 0;
7883 cld_filter = rte_zmalloc("tunnel_filter",
7884 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7887 if (cld_filter == NULL) {
7888 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7891 pfilter = cld_filter;
7893 ether_addr_copy(&tunnel_filter->outer_mac,
7894 (struct ether_addr *)&pfilter->element.outer_mac);
7895 ether_addr_copy(&tunnel_filter->inner_mac,
7896 (struct ether_addr *)&pfilter->element.inner_mac);
7898 pfilter->element.inner_vlan =
7899 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7900 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7901 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7902 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7903 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7904 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7906 sizeof(pfilter->element.ipaddr.v4.data));
7908 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7909 for (i = 0; i < 4; i++) {
7911 rte_cpu_to_le_32(rte_be_to_cpu_32(
7912 tunnel_filter->ip_addr.ipv6_addr[i]));
7914 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7916 sizeof(pfilter->element.ipaddr.v6.data));
7919 /* check tunneled type */
7920 switch (tunnel_filter->tunnel_type) {
7921 case I40E_TUNNEL_TYPE_VXLAN:
7922 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7924 case I40E_TUNNEL_TYPE_NVGRE:
7925 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7927 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7928 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7930 case I40E_TUNNEL_TYPE_MPLSoUDP:
7931 if (!pf->mpls_replace_flag) {
7932 i40e_replace_mpls_l1_filter(pf);
7933 i40e_replace_mpls_cloud_filter(pf);
7934 pf->mpls_replace_flag = 1;
7936 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7937 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7939 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7940 (teid_le & 0xF) << 12;
7941 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7944 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7946 case I40E_TUNNEL_TYPE_MPLSoGRE:
7947 if (!pf->mpls_replace_flag) {
7948 i40e_replace_mpls_l1_filter(pf);
7949 i40e_replace_mpls_cloud_filter(pf);
7950 pf->mpls_replace_flag = 1;
7952 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7953 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7955 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7956 (teid_le & 0xF) << 12;
7957 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7960 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7962 case I40E_TUNNEL_TYPE_GTPC:
7963 if (!pf->gtp_replace_flag) {
7964 i40e_replace_gtp_l1_filter(pf);
7965 i40e_replace_gtp_cloud_filter(pf);
7966 pf->gtp_replace_flag = 1;
7968 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7969 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7970 (teid_le >> 16) & 0xFFFF;
7971 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7973 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7977 case I40E_TUNNEL_TYPE_GTPU:
7978 if (!pf->gtp_replace_flag) {
7979 i40e_replace_gtp_l1_filter(pf);
7980 i40e_replace_gtp_cloud_filter(pf);
7981 pf->gtp_replace_flag = 1;
7983 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7984 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7985 (teid_le >> 16) & 0xFFFF;
7986 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7988 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7992 case I40E_TUNNEL_TYPE_QINQ:
7993 if (!pf->qinq_replace_flag) {
7994 ret = i40e_cloud_filter_qinq_create(pf);
7997 "QinQ tunnel filter already created.");
7998 pf->qinq_replace_flag = 1;
8000 /* Add in the General fields the values of
8001 * the Outer and Inner VLAN
8002 * Big Buffer should be set, see changes in
8003 * i40e_aq_add_cloud_filters
8005 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8006 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8010 /* Other tunnel types is not supported. */
8011 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8012 rte_free(cld_filter);
8016 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8017 pfilter->element.flags =
8018 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8019 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8020 pfilter->element.flags =
8021 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8022 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8023 pfilter->element.flags =
8024 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8025 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8026 pfilter->element.flags =
8027 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8028 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8029 pfilter->element.flags |=
8030 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8032 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8033 &pfilter->element.flags);
8035 rte_free(cld_filter);
8040 pfilter->element.flags |= rte_cpu_to_le_16(
8041 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8042 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8043 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8044 pfilter->element.queue_number =
8045 rte_cpu_to_le_16(tunnel_filter->queue_id);
8047 if (!tunnel_filter->is_to_vf)
8050 if (tunnel_filter->vf_id >= pf->vf_num) {
8051 PMD_DRV_LOG(ERR, "Invalid argument.");
8052 rte_free(cld_filter);
8055 vf = &pf->vfs[tunnel_filter->vf_id];
8059 /* Check if there is the filter in SW list */
8060 memset(&check_filter, 0, sizeof(check_filter));
8061 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8062 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8063 check_filter.vf_id = tunnel_filter->vf_id;
8064 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8066 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8067 rte_free(cld_filter);
8071 if (!add && !node) {
8072 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8073 rte_free(cld_filter);
8079 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
8080 vsi->seid, cld_filter, 1);
8082 ret = i40e_aq_add_cloud_filters(hw,
8083 vsi->seid, &cld_filter->element, 1);
8085 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8086 rte_free(cld_filter);
8089 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8090 if (tunnel == NULL) {
8091 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8092 rte_free(cld_filter);
8096 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8097 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8102 ret = i40e_aq_remove_cloud_filters_big_buffer(
8103 hw, vsi->seid, cld_filter, 1);
8105 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
8106 &cld_filter->element, 1);
8108 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8109 rte_free(cld_filter);
8112 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8115 rte_free(cld_filter);
8120 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8124 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8125 if (pf->vxlan_ports[i] == port)
8133 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8137 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8139 idx = i40e_get_vxlan_port_idx(pf, port);
8141 /* Check if port already exists */
8143 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8147 /* Now check if there is space to add the new port */
8148 idx = i40e_get_vxlan_port_idx(pf, 0);
8151 "Maximum number of UDP ports reached, not adding port %d",
8156 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8159 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8163 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8166 /* New port: add it and mark its index in the bitmap */
8167 pf->vxlan_ports[idx] = port;
8168 pf->vxlan_bitmap |= (1 << idx);
8170 if (!(pf->flags & I40E_FLAG_VXLAN))
8171 pf->flags |= I40E_FLAG_VXLAN;
8177 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8180 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8182 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8183 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8187 idx = i40e_get_vxlan_port_idx(pf, port);
8190 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8194 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8195 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8199 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8202 pf->vxlan_ports[idx] = 0;
8203 pf->vxlan_bitmap &= ~(1 << idx);
8205 if (!pf->vxlan_bitmap)
8206 pf->flags &= ~I40E_FLAG_VXLAN;
8211 /* Add UDP tunneling port */
8213 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8214 struct rte_eth_udp_tunnel *udp_tunnel)
8217 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8219 if (udp_tunnel == NULL)
8222 switch (udp_tunnel->prot_type) {
8223 case RTE_TUNNEL_TYPE_VXLAN:
8224 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8227 case RTE_TUNNEL_TYPE_GENEVE:
8228 case RTE_TUNNEL_TYPE_TEREDO:
8229 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8234 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8242 /* Remove UDP tunneling port */
8244 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8245 struct rte_eth_udp_tunnel *udp_tunnel)
8248 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8250 if (udp_tunnel == NULL)
8253 switch (udp_tunnel->prot_type) {
8254 case RTE_TUNNEL_TYPE_VXLAN:
8255 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8257 case RTE_TUNNEL_TYPE_GENEVE:
8258 case RTE_TUNNEL_TYPE_TEREDO:
8259 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8263 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8271 /* Calculate the maximum number of contiguous PF queues that are configured */
8273 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8275 struct rte_eth_dev_data *data = pf->dev_data;
8277 struct i40e_rx_queue *rxq;
8280 for (i = 0; i < pf->lan_nb_qps; i++) {
8281 rxq = data->rx_queues[i];
8282 if (rxq && rxq->q_set)
8293 i40e_pf_config_rss(struct i40e_pf *pf)
8295 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8296 struct rte_eth_rss_conf rss_conf;
8297 uint32_t i, lut = 0;
8301 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8302 * It's necessary to calculate the actual PF queues that are configured.
8304 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8305 num = i40e_pf_calc_configured_queues_num(pf);
8307 num = pf->dev_data->nb_rx_queues;
8309 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8310 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8314 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8318 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8321 lut = (lut << 8) | (j & ((0x1 <<
8322 hw->func_caps.rss_table_entry_width) - 1));
8324 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8327 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8328 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8329 i40e_pf_disable_rss(pf);
8332 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8333 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8334 /* Random default keys */
8335 static uint32_t rss_key_default[] = {0x6b793944,
8336 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8337 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8338 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8340 rss_conf.rss_key = (uint8_t *)rss_key_default;
8341 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8345 return i40e_hw_rss_hash_set(pf, &rss_conf);
8349 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8350 struct rte_eth_tunnel_filter_conf *filter)
8352 if (pf == NULL || filter == NULL) {
8353 PMD_DRV_LOG(ERR, "Invalid parameter");
8357 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8358 PMD_DRV_LOG(ERR, "Invalid queue ID");
8362 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8363 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8367 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8368 (is_zero_ether_addr(&filter->outer_mac))) {
8369 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8373 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8374 (is_zero_ether_addr(&filter->inner_mac))) {
8375 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8382 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8383 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8385 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8387 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8391 if (pf->support_multi_driver) {
8392 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8396 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8397 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8400 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8401 } else if (len == 4) {
8402 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8404 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8409 ret = i40e_aq_debug_write_global_register(hw,
8410 I40E_GL_PRS_FVBM(2),
8414 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8415 "with value 0x%08x",
8416 I40E_GL_PRS_FVBM(2), reg);
8420 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8421 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8427 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8434 switch (cfg->cfg_type) {
8435 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8436 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8439 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8447 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8448 enum rte_filter_op filter_op,
8451 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8452 int ret = I40E_ERR_PARAM;
8454 switch (filter_op) {
8455 case RTE_ETH_FILTER_SET:
8456 ret = i40e_dev_global_config_set(hw,
8457 (struct rte_eth_global_cfg *)arg);
8460 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8468 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8469 enum rte_filter_op filter_op,
8472 struct rte_eth_tunnel_filter_conf *filter;
8473 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8474 int ret = I40E_SUCCESS;
8476 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8478 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8479 return I40E_ERR_PARAM;
8481 switch (filter_op) {
8482 case RTE_ETH_FILTER_NOP:
8483 if (!(pf->flags & I40E_FLAG_VXLAN))
8484 ret = I40E_NOT_SUPPORTED;
8486 case RTE_ETH_FILTER_ADD:
8487 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8489 case RTE_ETH_FILTER_DELETE:
8490 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8493 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8494 ret = I40E_ERR_PARAM;
8502 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8505 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8508 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8509 ret = i40e_pf_config_rss(pf);
8511 i40e_pf_disable_rss(pf);
8516 /* Get the symmetric hash enable configurations per port */
8518 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8520 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8522 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8525 /* Set the symmetric hash enable configurations per port */
8527 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8529 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8532 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8534 "Symmetric hash has already been enabled");
8537 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8539 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8541 "Symmetric hash has already been disabled");
8544 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8546 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8547 I40E_WRITE_FLUSH(hw);
8551 * Get global configurations of hash function type and symmetric hash enable
8552 * per flow type (pctype). Note that global configuration means it affects all
8553 * the ports on the same NIC.
8556 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8557 struct rte_eth_hash_global_conf *g_cfg)
8559 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8563 memset(g_cfg, 0, sizeof(*g_cfg));
8564 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8565 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8566 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8568 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8569 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8570 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8573 * As i40e supports less than 64 flow types, only first 64 bits need to
8576 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8577 g_cfg->valid_bit_mask[i] = 0ULL;
8578 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8581 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8583 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8584 if (!adapter->pctypes_tbl[i])
8586 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8587 j < I40E_FILTER_PCTYPE_MAX; j++) {
8588 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8589 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8590 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8591 g_cfg->sym_hash_enable_mask[0] |=
8602 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8603 const struct rte_eth_hash_global_conf *g_cfg)
8606 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8608 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8609 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8610 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8611 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8617 * As i40e supports less than 64 flow types, only first 64 bits need to
8620 mask0 = g_cfg->valid_bit_mask[0];
8621 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8623 /* Check if any unsupported flow type configured */
8624 if ((mask0 | i40e_mask) ^ i40e_mask)
8627 if (g_cfg->valid_bit_mask[i])
8635 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8641 * Set global configurations of hash function type and symmetric hash enable
8642 * per flow type (pctype). Note any modifying global configuration will affect
8643 * all the ports on the same NIC.
8646 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8647 struct rte_eth_hash_global_conf *g_cfg)
8649 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8650 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8654 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8656 if (pf->support_multi_driver) {
8657 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8661 /* Check the input parameters */
8662 ret = i40e_hash_global_config_check(adapter, g_cfg);
8667 * As i40e supports less than 64 flow types, only first 64 bits need to
8670 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8671 if (mask0 & (1UL << i)) {
8672 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8673 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8675 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8676 j < I40E_FILTER_PCTYPE_MAX; j++) {
8677 if (adapter->pctypes_tbl[i] & (1ULL << j))
8678 i40e_write_global_rx_ctl(hw,
8685 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8686 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8688 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8690 "Hash function already set to Toeplitz");
8693 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8694 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8696 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8698 "Hash function already set to Simple XOR");
8701 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8703 /* Use the default, and keep it as it is */
8706 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8709 I40E_WRITE_FLUSH(hw);
8715 * Valid input sets for hash and flow director filters per PCTYPE
8718 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8719 enum rte_filter_type filter)
8723 static const uint64_t valid_hash_inset_table[] = {
8724 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8725 I40E_INSET_DMAC | I40E_INSET_SMAC |
8726 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8727 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8728 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8729 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8730 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8731 I40E_INSET_FLEX_PAYLOAD,
8732 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8733 I40E_INSET_DMAC | I40E_INSET_SMAC |
8734 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8735 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8736 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8737 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8738 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8739 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8740 I40E_INSET_FLEX_PAYLOAD,
8741 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8742 I40E_INSET_DMAC | I40E_INSET_SMAC |
8743 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8744 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8745 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8746 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8747 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8748 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8749 I40E_INSET_FLEX_PAYLOAD,
8750 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8751 I40E_INSET_DMAC | I40E_INSET_SMAC |
8752 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8753 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8754 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8755 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8756 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8757 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8758 I40E_INSET_FLEX_PAYLOAD,
8759 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8760 I40E_INSET_DMAC | I40E_INSET_SMAC |
8761 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8762 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8763 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8764 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8765 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8766 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8767 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8768 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8769 I40E_INSET_DMAC | I40E_INSET_SMAC |
8770 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8771 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8772 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8773 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8774 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8775 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8776 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8777 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8778 I40E_INSET_DMAC | I40E_INSET_SMAC |
8779 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8780 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8781 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8782 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8783 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8784 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8785 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8786 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8787 I40E_INSET_DMAC | I40E_INSET_SMAC |
8788 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8789 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8790 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8791 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8792 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8793 I40E_INSET_FLEX_PAYLOAD,
8794 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8795 I40E_INSET_DMAC | I40E_INSET_SMAC |
8796 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8797 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8798 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8799 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8800 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8801 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8802 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8803 I40E_INSET_DMAC | I40E_INSET_SMAC |
8804 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8805 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8806 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8807 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8808 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8809 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8810 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8811 I40E_INSET_DMAC | I40E_INSET_SMAC |
8812 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8813 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8814 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8815 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8816 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8817 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8818 I40E_INSET_FLEX_PAYLOAD,
8819 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8820 I40E_INSET_DMAC | I40E_INSET_SMAC |
8821 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8822 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8823 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8824 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8825 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8826 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8827 I40E_INSET_FLEX_PAYLOAD,
8828 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8829 I40E_INSET_DMAC | I40E_INSET_SMAC |
8830 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8831 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8832 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8833 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8834 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8835 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8836 I40E_INSET_FLEX_PAYLOAD,
8837 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8838 I40E_INSET_DMAC | I40E_INSET_SMAC |
8839 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8840 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8841 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8842 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8843 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8844 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8845 I40E_INSET_FLEX_PAYLOAD,
8846 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8847 I40E_INSET_DMAC | I40E_INSET_SMAC |
8848 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8849 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8850 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8851 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8852 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8853 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8854 I40E_INSET_FLEX_PAYLOAD,
8855 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8856 I40E_INSET_DMAC | I40E_INSET_SMAC |
8857 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8858 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8859 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8860 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8861 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8862 I40E_INSET_FLEX_PAYLOAD,
8863 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8864 I40E_INSET_DMAC | I40E_INSET_SMAC |
8865 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8866 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8867 I40E_INSET_FLEX_PAYLOAD,
8871 * Flow director supports only fields defined in
8872 * union rte_eth_fdir_flow.
8874 static const uint64_t valid_fdir_inset_table[] = {
8875 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8876 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8877 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8878 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8879 I40E_INSET_IPV4_TTL,
8880 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8881 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8882 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8883 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8884 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8885 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8886 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8887 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8888 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8889 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8890 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8891 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8892 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8893 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8894 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8895 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8896 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8897 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8898 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8899 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8900 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8901 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8902 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8903 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8904 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8905 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8906 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8907 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8908 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8909 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8911 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8912 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8913 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8914 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8915 I40E_INSET_IPV4_TTL,
8916 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8917 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8918 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8919 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8920 I40E_INSET_IPV6_HOP_LIMIT,
8921 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8922 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8923 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8924 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8925 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8926 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8927 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8928 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8929 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8930 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8931 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8932 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8933 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8934 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8935 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8936 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8937 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8938 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8939 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8940 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8941 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8942 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8943 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8944 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8945 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8946 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8947 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8948 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8949 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8950 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8952 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8953 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8954 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8955 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8956 I40E_INSET_IPV6_HOP_LIMIT,
8957 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8958 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8959 I40E_INSET_LAST_ETHER_TYPE,
8962 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8964 if (filter == RTE_ETH_FILTER_HASH)
8965 valid = valid_hash_inset_table[pctype];
8967 valid = valid_fdir_inset_table[pctype];
8973 * Validate if the input set is allowed for a specific PCTYPE
8976 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8977 enum rte_filter_type filter, uint64_t inset)
8981 valid = i40e_get_valid_input_set(pctype, filter);
8982 if (inset & (~valid))
8988 /* default input set fields combination per pctype */
8990 i40e_get_default_input_set(uint16_t pctype)
8992 static const uint64_t default_inset_table[] = {
8993 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8994 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8995 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8996 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8997 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8998 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8999 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9000 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9001 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9002 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9003 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9004 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9005 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9006 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9007 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9008 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9009 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9010 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9011 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9012 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9014 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9015 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9016 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9017 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9018 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9019 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9020 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9021 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9022 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9023 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9024 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9025 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9026 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9027 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9028 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9029 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9030 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9031 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9032 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9033 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9034 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9035 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9037 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9038 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9039 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9040 I40E_INSET_LAST_ETHER_TYPE,
9043 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9046 return default_inset_table[pctype];
9050 * Parse the input set from index to logical bit masks
9053 i40e_parse_input_set(uint64_t *inset,
9054 enum i40e_filter_pctype pctype,
9055 enum rte_eth_input_set_field *field,
9061 static const struct {
9062 enum rte_eth_input_set_field field;
9064 } inset_convert_table[] = {
9065 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9066 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9067 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9068 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9069 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9070 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9071 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9072 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9073 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9074 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9075 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9076 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9077 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9078 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9079 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9080 I40E_INSET_IPV6_NEXT_HDR},
9081 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9082 I40E_INSET_IPV6_HOP_LIMIT},
9083 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9084 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9085 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9086 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9087 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9088 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9089 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9090 I40E_INSET_SCTP_VT},
9091 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9092 I40E_INSET_TUNNEL_DMAC},
9093 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9094 I40E_INSET_VLAN_TUNNEL},
9095 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9096 I40E_INSET_TUNNEL_ID},
9097 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9098 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9099 I40E_INSET_FLEX_PAYLOAD_W1},
9100 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9101 I40E_INSET_FLEX_PAYLOAD_W2},
9102 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9103 I40E_INSET_FLEX_PAYLOAD_W3},
9104 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9105 I40E_INSET_FLEX_PAYLOAD_W4},
9106 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9107 I40E_INSET_FLEX_PAYLOAD_W5},
9108 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9109 I40E_INSET_FLEX_PAYLOAD_W6},
9110 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9111 I40E_INSET_FLEX_PAYLOAD_W7},
9112 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9113 I40E_INSET_FLEX_PAYLOAD_W8},
9116 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9119 /* Only one item allowed for default or all */
9121 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9122 *inset = i40e_get_default_input_set(pctype);
9124 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9125 *inset = I40E_INSET_NONE;
9130 for (i = 0, *inset = 0; i < size; i++) {
9131 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9132 if (field[i] == inset_convert_table[j].field) {
9133 *inset |= inset_convert_table[j].inset;
9138 /* It contains unsupported input set, return immediately */
9139 if (j == RTE_DIM(inset_convert_table))
9147 * Translate the input set from bit masks to register aware bit masks
9151 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9161 static const struct inset_map inset_map_common[] = {
9162 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9163 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9164 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9165 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9166 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9167 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9168 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9169 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9170 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9171 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9172 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9173 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9174 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9175 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9176 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9177 {I40E_INSET_TUNNEL_DMAC,
9178 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9179 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9180 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9181 {I40E_INSET_TUNNEL_SRC_PORT,
9182 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9183 {I40E_INSET_TUNNEL_DST_PORT,
9184 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9185 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9186 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9187 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9188 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9189 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9190 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9191 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9192 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9193 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9196 /* some different registers map in x722*/
9197 static const struct inset_map inset_map_diff_x722[] = {
9198 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9199 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9200 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9201 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9204 static const struct inset_map inset_map_diff_not_x722[] = {
9205 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9206 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9207 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9208 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9214 /* Translate input set to register aware inset */
9215 if (type == I40E_MAC_X722) {
9216 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9217 if (input & inset_map_diff_x722[i].inset)
9218 val |= inset_map_diff_x722[i].inset_reg;
9221 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9222 if (input & inset_map_diff_not_x722[i].inset)
9223 val |= inset_map_diff_not_x722[i].inset_reg;
9227 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9228 if (input & inset_map_common[i].inset)
9229 val |= inset_map_common[i].inset_reg;
9236 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9239 uint64_t inset_need_mask = inset;
9241 static const struct {
9244 } inset_mask_map[] = {
9245 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9246 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9247 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9248 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9249 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9250 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9251 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9252 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9255 if (!inset || !mask || !nb_elem)
9258 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9259 /* Clear the inset bit, if no MASK is required,
9260 * for example proto + ttl
9262 if ((inset & inset_mask_map[i].inset) ==
9263 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9264 inset_need_mask &= ~inset_mask_map[i].inset;
9265 if (!inset_need_mask)
9268 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9269 if ((inset_need_mask & inset_mask_map[i].inset) ==
9270 inset_mask_map[i].inset) {
9271 if (idx >= nb_elem) {
9272 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9275 mask[idx] = inset_mask_map[i].mask;
9284 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9286 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9288 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9290 i40e_write_rx_ctl(hw, addr, val);
9291 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9292 (uint32_t)i40e_read_rx_ctl(hw, addr));
9296 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9298 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9299 struct rte_eth_dev *dev;
9301 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9303 i40e_write_rx_ctl(hw, addr, val);
9304 PMD_DRV_LOG(WARNING,
9305 "i40e device %s changed global register [0x%08x]."
9306 " original: 0x%08x, new: 0x%08x",
9307 dev->device->name, addr, reg,
9308 (uint32_t)i40e_read_rx_ctl(hw, addr));
9313 i40e_filter_input_set_init(struct i40e_pf *pf)
9315 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9316 enum i40e_filter_pctype pctype;
9317 uint64_t input_set, inset_reg;
9318 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9322 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9323 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9324 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9326 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9329 input_set = i40e_get_default_input_set(pctype);
9331 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9332 I40E_INSET_MASK_NUM_REG);
9335 if (pf->support_multi_driver && num > 0) {
9336 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9339 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9342 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9343 (uint32_t)(inset_reg & UINT32_MAX));
9344 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9345 (uint32_t)((inset_reg >>
9346 I40E_32_BIT_WIDTH) & UINT32_MAX));
9347 if (!pf->support_multi_driver) {
9348 i40e_check_write_global_reg(hw,
9349 I40E_GLQF_HASH_INSET(0, pctype),
9350 (uint32_t)(inset_reg & UINT32_MAX));
9351 i40e_check_write_global_reg(hw,
9352 I40E_GLQF_HASH_INSET(1, pctype),
9353 (uint32_t)((inset_reg >>
9354 I40E_32_BIT_WIDTH) & UINT32_MAX));
9356 for (i = 0; i < num; i++) {
9357 i40e_check_write_global_reg(hw,
9358 I40E_GLQF_FD_MSK(i, pctype),
9360 i40e_check_write_global_reg(hw,
9361 I40E_GLQF_HASH_MSK(i, pctype),
9364 /*clear unused mask registers of the pctype */
9365 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9366 i40e_check_write_global_reg(hw,
9367 I40E_GLQF_FD_MSK(i, pctype),
9369 i40e_check_write_global_reg(hw,
9370 I40E_GLQF_HASH_MSK(i, pctype),
9374 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9376 I40E_WRITE_FLUSH(hw);
9378 /* store the default input set */
9379 if (!pf->support_multi_driver)
9380 pf->hash_input_set[pctype] = input_set;
9381 pf->fdir.input_set[pctype] = input_set;
9386 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9387 struct rte_eth_input_set_conf *conf)
9389 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9390 enum i40e_filter_pctype pctype;
9391 uint64_t input_set, inset_reg = 0;
9392 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9396 PMD_DRV_LOG(ERR, "Invalid pointer");
9399 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9400 conf->op != RTE_ETH_INPUT_SET_ADD) {
9401 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9405 if (pf->support_multi_driver) {
9406 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9410 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9411 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9412 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9416 if (hw->mac.type == I40E_MAC_X722) {
9417 /* get translated pctype value in fd pctype register */
9418 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9419 I40E_GLQF_FD_PCTYPES((int)pctype));
9422 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9425 PMD_DRV_LOG(ERR, "Failed to parse input set");
9429 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9430 /* get inset value in register */
9431 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9432 inset_reg <<= I40E_32_BIT_WIDTH;
9433 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9434 input_set |= pf->hash_input_set[pctype];
9436 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9437 I40E_INSET_MASK_NUM_REG);
9441 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9443 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9444 (uint32_t)(inset_reg & UINT32_MAX));
9445 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9446 (uint32_t)((inset_reg >>
9447 I40E_32_BIT_WIDTH) & UINT32_MAX));
9449 for (i = 0; i < num; i++)
9450 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9452 /*clear unused mask registers of the pctype */
9453 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9454 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9456 I40E_WRITE_FLUSH(hw);
9458 pf->hash_input_set[pctype] = input_set;
9463 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9464 struct rte_eth_input_set_conf *conf)
9466 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9467 enum i40e_filter_pctype pctype;
9468 uint64_t input_set, inset_reg = 0;
9469 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9473 PMD_DRV_LOG(ERR, "Invalid pointer");
9476 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9477 conf->op != RTE_ETH_INPUT_SET_ADD) {
9478 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9482 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9484 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9485 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9489 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9492 PMD_DRV_LOG(ERR, "Failed to parse input set");
9496 /* get inset value in register */
9497 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9498 inset_reg <<= I40E_32_BIT_WIDTH;
9499 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9501 /* Can not change the inset reg for flex payload for fdir,
9502 * it is done by writing I40E_PRTQF_FD_FLXINSET
9503 * in i40e_set_flex_mask_on_pctype.
9505 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9506 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9508 input_set |= pf->fdir.input_set[pctype];
9509 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9510 I40E_INSET_MASK_NUM_REG);
9513 if (pf->support_multi_driver && num > 0) {
9514 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9518 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9520 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9521 (uint32_t)(inset_reg & UINT32_MAX));
9522 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9523 (uint32_t)((inset_reg >>
9524 I40E_32_BIT_WIDTH) & UINT32_MAX));
9526 if (!pf->support_multi_driver) {
9527 for (i = 0; i < num; i++)
9528 i40e_check_write_global_reg(hw,
9529 I40E_GLQF_FD_MSK(i, pctype),
9531 /*clear unused mask registers of the pctype */
9532 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9533 i40e_check_write_global_reg(hw,
9534 I40E_GLQF_FD_MSK(i, pctype),
9537 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9539 I40E_WRITE_FLUSH(hw);
9541 pf->fdir.input_set[pctype] = input_set;
9546 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9551 PMD_DRV_LOG(ERR, "Invalid pointer");
9555 switch (info->info_type) {
9556 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9557 i40e_get_symmetric_hash_enable_per_port(hw,
9558 &(info->info.enable));
9560 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9561 ret = i40e_get_hash_filter_global_config(hw,
9562 &(info->info.global_conf));
9565 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9575 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9580 PMD_DRV_LOG(ERR, "Invalid pointer");
9584 switch (info->info_type) {
9585 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9586 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9588 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9589 ret = i40e_set_hash_filter_global_config(hw,
9590 &(info->info.global_conf));
9592 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9593 ret = i40e_hash_filter_inset_select(hw,
9594 &(info->info.input_set_conf));
9598 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9607 /* Operations for hash function */
9609 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9610 enum rte_filter_op filter_op,
9613 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9616 switch (filter_op) {
9617 case RTE_ETH_FILTER_NOP:
9619 case RTE_ETH_FILTER_GET:
9620 ret = i40e_hash_filter_get(hw,
9621 (struct rte_eth_hash_filter_info *)arg);
9623 case RTE_ETH_FILTER_SET:
9624 ret = i40e_hash_filter_set(hw,
9625 (struct rte_eth_hash_filter_info *)arg);
9628 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9637 /* Convert ethertype filter structure */
9639 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9640 struct i40e_ethertype_filter *filter)
9642 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9643 filter->input.ether_type = input->ether_type;
9644 filter->flags = input->flags;
9645 filter->queue = input->queue;
9650 /* Check if there exists the ehtertype filter */
9651 struct i40e_ethertype_filter *
9652 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9653 const struct i40e_ethertype_filter_input *input)
9657 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9661 return ethertype_rule->hash_map[ret];
9664 /* Add ethertype filter in SW list */
9666 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9667 struct i40e_ethertype_filter *filter)
9669 struct i40e_ethertype_rule *rule = &pf->ethertype;
9672 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9675 "Failed to insert ethertype filter"
9676 " to hash table %d!",
9680 rule->hash_map[ret] = filter;
9682 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9687 /* Delete ethertype filter in SW list */
9689 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9690 struct i40e_ethertype_filter_input *input)
9692 struct i40e_ethertype_rule *rule = &pf->ethertype;
9693 struct i40e_ethertype_filter *filter;
9696 ret = rte_hash_del_key(rule->hash_table, input);
9699 "Failed to delete ethertype filter"
9700 " to hash table %d!",
9704 filter = rule->hash_map[ret];
9705 rule->hash_map[ret] = NULL;
9707 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9714 * Configure ethertype filter, which can director packet by filtering
9715 * with mac address and ether_type or only ether_type
9718 i40e_ethertype_filter_set(struct i40e_pf *pf,
9719 struct rte_eth_ethertype_filter *filter,
9722 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9723 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9724 struct i40e_ethertype_filter *ethertype_filter, *node;
9725 struct i40e_ethertype_filter check_filter;
9726 struct i40e_control_filter_stats stats;
9730 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9731 PMD_DRV_LOG(ERR, "Invalid queue ID");
9734 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9735 filter->ether_type == ETHER_TYPE_IPv6) {
9737 "unsupported ether_type(0x%04x) in control packet filter.",
9738 filter->ether_type);
9741 if (filter->ether_type == ETHER_TYPE_VLAN)
9742 PMD_DRV_LOG(WARNING,
9743 "filter vlan ether_type in first tag is not supported.");
9745 /* Check if there is the filter in SW list */
9746 memset(&check_filter, 0, sizeof(check_filter));
9747 i40e_ethertype_filter_convert(filter, &check_filter);
9748 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9749 &check_filter.input);
9751 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9755 if (!add && !node) {
9756 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9760 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9761 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9762 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9763 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9764 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9766 memset(&stats, 0, sizeof(stats));
9767 ret = i40e_aq_add_rem_control_packet_filter(hw,
9768 filter->mac_addr.addr_bytes,
9769 filter->ether_type, flags,
9771 filter->queue, add, &stats, NULL);
9774 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9775 ret, stats.mac_etype_used, stats.etype_used,
9776 stats.mac_etype_free, stats.etype_free);
9780 /* Add or delete a filter in SW list */
9782 ethertype_filter = rte_zmalloc("ethertype_filter",
9783 sizeof(*ethertype_filter), 0);
9784 if (ethertype_filter == NULL) {
9785 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9789 rte_memcpy(ethertype_filter, &check_filter,
9790 sizeof(check_filter));
9791 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9793 rte_free(ethertype_filter);
9795 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9802 * Handle operations for ethertype filter.
9805 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9806 enum rte_filter_op filter_op,
9809 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9812 if (filter_op == RTE_ETH_FILTER_NOP)
9816 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9821 switch (filter_op) {
9822 case RTE_ETH_FILTER_ADD:
9823 ret = i40e_ethertype_filter_set(pf,
9824 (struct rte_eth_ethertype_filter *)arg,
9827 case RTE_ETH_FILTER_DELETE:
9828 ret = i40e_ethertype_filter_set(pf,
9829 (struct rte_eth_ethertype_filter *)arg,
9833 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9841 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9842 enum rte_filter_type filter_type,
9843 enum rte_filter_op filter_op,
9851 switch (filter_type) {
9852 case RTE_ETH_FILTER_NONE:
9853 /* For global configuration */
9854 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9856 case RTE_ETH_FILTER_HASH:
9857 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9859 case RTE_ETH_FILTER_MACVLAN:
9860 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9862 case RTE_ETH_FILTER_ETHERTYPE:
9863 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9865 case RTE_ETH_FILTER_TUNNEL:
9866 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9868 case RTE_ETH_FILTER_FDIR:
9869 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9871 case RTE_ETH_FILTER_GENERIC:
9872 if (filter_op != RTE_ETH_FILTER_GET)
9874 *(const void **)arg = &i40e_flow_ops;
9877 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9887 * Check and enable Extended Tag.
9888 * Enabling Extended Tag is important for 40G performance.
9891 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9893 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9897 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9900 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9904 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9905 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9910 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9913 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9917 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9918 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9921 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9922 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9925 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9932 * As some registers wouldn't be reset unless a global hardware reset,
9933 * hardware initialization is needed to put those registers into an
9934 * expected initial state.
9937 i40e_hw_init(struct rte_eth_dev *dev)
9939 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9941 i40e_enable_extended_tag(dev);
9943 /* clear the PF Queue Filter control register */
9944 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9946 /* Disable symmetric hash per port */
9947 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9951 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9952 * however this function will return only one highest pctype index,
9953 * which is not quite correct. This is known problem of i40e driver
9954 * and needs to be fixed later.
9956 enum i40e_filter_pctype
9957 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9960 uint64_t pctype_mask;
9962 if (flow_type < I40E_FLOW_TYPE_MAX) {
9963 pctype_mask = adapter->pctypes_tbl[flow_type];
9964 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9965 if (pctype_mask & (1ULL << i))
9966 return (enum i40e_filter_pctype)i;
9969 return I40E_FILTER_PCTYPE_INVALID;
9973 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9974 enum i40e_filter_pctype pctype)
9977 uint64_t pctype_mask = 1ULL << pctype;
9979 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9981 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9985 return RTE_ETH_FLOW_UNKNOWN;
9989 * On X710, performance number is far from the expectation on recent firmware
9990 * versions; on XL710, performance number is also far from the expectation on
9991 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9992 * mode is enabled and port MAC address is equal to the packet destination MAC
9993 * address. The fix for this issue may not be integrated in the following
9994 * firmware version. So the workaround in software driver is needed. It needs
9995 * to modify the initial values of 3 internal only registers for both X710 and
9996 * XL710. Note that the values for X710 or XL710 could be different, and the
9997 * workaround can be removed when it is fixed in firmware in the future.
10000 /* For both X710 and XL710 */
10001 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10002 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10003 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10005 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10006 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10009 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10010 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10013 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10015 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10016 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10019 * GL_SWR_PM_UP_THR:
10020 * The value is not impacted from the link speed, its value is set according
10021 * to the total number of ports for a better pipe-monitor configuration.
10024 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10026 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10027 .device_id = (dev), \
10028 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10030 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10031 .device_id = (dev), \
10032 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10034 static const struct {
10035 uint16_t device_id;
10037 } swr_pm_table[] = {
10038 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10039 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10040 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10041 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10043 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10044 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10045 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10046 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10047 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10048 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10049 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10053 if (value == NULL) {
10054 PMD_DRV_LOG(ERR, "value is NULL");
10058 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10059 if (hw->device_id == swr_pm_table[i].device_id) {
10060 *value = swr_pm_table[i].val;
10062 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10064 hw->device_id, *value);
10073 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10075 enum i40e_status_code status;
10076 struct i40e_aq_get_phy_abilities_resp phy_ab;
10077 int ret = -ENOTSUP;
10080 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10084 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10087 rte_delay_us(100000);
10089 status = i40e_aq_get_phy_capabilities(hw, false,
10090 true, &phy_ab, NULL);
10098 i40e_configure_registers(struct i40e_hw *hw)
10104 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10105 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10106 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10112 for (i = 0; i < RTE_DIM(reg_table); i++) {
10113 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10114 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10116 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10117 else /* For X710/XL710/XXV710 */
10118 if (hw->aq.fw_maj_ver < 6)
10120 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10123 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10126 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10127 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10129 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10130 else /* For X710/XL710/XXV710 */
10132 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10135 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10138 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10139 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10140 "GL_SWR_PM_UP_THR value fixup",
10145 reg_table[i].val = cfg_val;
10148 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10151 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10152 reg_table[i].addr);
10155 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10156 reg_table[i].addr, reg);
10157 if (reg == reg_table[i].val)
10160 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10161 reg_table[i].val, NULL);
10164 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10165 reg_table[i].val, reg_table[i].addr);
10168 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10169 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10173 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10174 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10175 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10176 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10178 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10183 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10184 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10188 /* Configure for double VLAN RX stripping */
10189 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10190 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10191 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10192 ret = i40e_aq_debug_write_register(hw,
10193 I40E_VSI_TSR(vsi->vsi_id),
10196 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10198 return I40E_ERR_CONFIG;
10202 /* Configure for double VLAN TX insertion */
10203 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10204 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10205 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10206 ret = i40e_aq_debug_write_register(hw,
10207 I40E_VSI_L2TAGSTXVALID(
10208 vsi->vsi_id), reg, NULL);
10211 "Failed to update VSI_L2TAGSTXVALID[%d]",
10213 return I40E_ERR_CONFIG;
10221 * i40e_aq_add_mirror_rule
10222 * @hw: pointer to the hardware structure
10223 * @seid: VEB seid to add mirror rule to
10224 * @dst_id: destination vsi seid
10225 * @entries: Buffer which contains the entities to be mirrored
10226 * @count: number of entities contained in the buffer
10227 * @rule_id:the rule_id of the rule to be added
10229 * Add a mirror rule for a given veb.
10232 static enum i40e_status_code
10233 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10234 uint16_t seid, uint16_t dst_id,
10235 uint16_t rule_type, uint16_t *entries,
10236 uint16_t count, uint16_t *rule_id)
10238 struct i40e_aq_desc desc;
10239 struct i40e_aqc_add_delete_mirror_rule cmd;
10240 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10241 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10244 enum i40e_status_code status;
10246 i40e_fill_default_direct_cmd_desc(&desc,
10247 i40e_aqc_opc_add_mirror_rule);
10248 memset(&cmd, 0, sizeof(cmd));
10250 buff_len = sizeof(uint16_t) * count;
10251 desc.datalen = rte_cpu_to_le_16(buff_len);
10253 desc.flags |= rte_cpu_to_le_16(
10254 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10255 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10256 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10257 cmd.num_entries = rte_cpu_to_le_16(count);
10258 cmd.seid = rte_cpu_to_le_16(seid);
10259 cmd.destination = rte_cpu_to_le_16(dst_id);
10261 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10262 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10264 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10265 hw->aq.asq_last_status, resp->rule_id,
10266 resp->mirror_rules_used, resp->mirror_rules_free);
10267 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10273 * i40e_aq_del_mirror_rule
10274 * @hw: pointer to the hardware structure
10275 * @seid: VEB seid to add mirror rule to
10276 * @entries: Buffer which contains the entities to be mirrored
10277 * @count: number of entities contained in the buffer
10278 * @rule_id:the rule_id of the rule to be delete
10280 * Delete a mirror rule for a given veb.
10283 static enum i40e_status_code
10284 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10285 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10286 uint16_t count, uint16_t rule_id)
10288 struct i40e_aq_desc desc;
10289 struct i40e_aqc_add_delete_mirror_rule cmd;
10290 uint16_t buff_len = 0;
10291 enum i40e_status_code status;
10294 i40e_fill_default_direct_cmd_desc(&desc,
10295 i40e_aqc_opc_delete_mirror_rule);
10296 memset(&cmd, 0, sizeof(cmd));
10297 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10298 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10300 cmd.num_entries = count;
10301 buff_len = sizeof(uint16_t) * count;
10302 desc.datalen = rte_cpu_to_le_16(buff_len);
10303 buff = (void *)entries;
10305 /* rule id is filled in destination field for deleting mirror rule */
10306 cmd.destination = rte_cpu_to_le_16(rule_id);
10308 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10309 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10310 cmd.seid = rte_cpu_to_le_16(seid);
10312 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10313 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10319 * i40e_mirror_rule_set
10320 * @dev: pointer to the hardware structure
10321 * @mirror_conf: mirror rule info
10322 * @sw_id: mirror rule's sw_id
10323 * @on: enable/disable
10325 * set a mirror rule.
10329 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10330 struct rte_eth_mirror_conf *mirror_conf,
10331 uint8_t sw_id, uint8_t on)
10333 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10334 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10335 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10336 struct i40e_mirror_rule *parent = NULL;
10337 uint16_t seid, dst_seid, rule_id;
10341 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10343 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10345 "mirror rule can not be configured without veb or vfs.");
10348 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10349 PMD_DRV_LOG(ERR, "mirror table is full.");
10352 if (mirror_conf->dst_pool > pf->vf_num) {
10353 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10354 mirror_conf->dst_pool);
10358 seid = pf->main_vsi->veb->seid;
10360 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10361 if (sw_id <= it->index) {
10367 if (mirr_rule && sw_id == mirr_rule->index) {
10369 PMD_DRV_LOG(ERR, "mirror rule exists.");
10372 ret = i40e_aq_del_mirror_rule(hw, seid,
10373 mirr_rule->rule_type,
10374 mirr_rule->entries,
10375 mirr_rule->num_entries, mirr_rule->id);
10378 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10379 ret, hw->aq.asq_last_status);
10382 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10383 rte_free(mirr_rule);
10384 pf->nb_mirror_rule--;
10388 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10392 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10393 sizeof(struct i40e_mirror_rule) , 0);
10395 PMD_DRV_LOG(ERR, "failed to allocate memory");
10396 return I40E_ERR_NO_MEMORY;
10398 switch (mirror_conf->rule_type) {
10399 case ETH_MIRROR_VLAN:
10400 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10401 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10402 mirr_rule->entries[j] =
10403 mirror_conf->vlan.vlan_id[i];
10408 PMD_DRV_LOG(ERR, "vlan is not specified.");
10409 rte_free(mirr_rule);
10412 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10414 case ETH_MIRROR_VIRTUAL_POOL_UP:
10415 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10416 /* check if the specified pool bit is out of range */
10417 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10418 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10419 rte_free(mirr_rule);
10422 for (i = 0, j = 0; i < pf->vf_num; i++) {
10423 if (mirror_conf->pool_mask & (1ULL << i)) {
10424 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10428 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10429 /* add pf vsi to entries */
10430 mirr_rule->entries[j] = pf->main_vsi_seid;
10434 PMD_DRV_LOG(ERR, "pool is not specified.");
10435 rte_free(mirr_rule);
10438 /* egress and ingress in aq commands means from switch but not port */
10439 mirr_rule->rule_type =
10440 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10441 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10442 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10444 case ETH_MIRROR_UPLINK_PORT:
10445 /* egress and ingress in aq commands means from switch but not port*/
10446 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10448 case ETH_MIRROR_DOWNLINK_PORT:
10449 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10452 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10453 mirror_conf->rule_type);
10454 rte_free(mirr_rule);
10458 /* If the dst_pool is equal to vf_num, consider it as PF */
10459 if (mirror_conf->dst_pool == pf->vf_num)
10460 dst_seid = pf->main_vsi_seid;
10462 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10464 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10465 mirr_rule->rule_type, mirr_rule->entries,
10469 "failed to add mirror rule: ret = %d, aq_err = %d.",
10470 ret, hw->aq.asq_last_status);
10471 rte_free(mirr_rule);
10475 mirr_rule->index = sw_id;
10476 mirr_rule->num_entries = j;
10477 mirr_rule->id = rule_id;
10478 mirr_rule->dst_vsi_seid = dst_seid;
10481 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10483 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10485 pf->nb_mirror_rule++;
10490 * i40e_mirror_rule_reset
10491 * @dev: pointer to the device
10492 * @sw_id: mirror rule's sw_id
10494 * reset a mirror rule.
10498 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10500 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10501 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10502 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10506 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10508 seid = pf->main_vsi->veb->seid;
10510 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10511 if (sw_id == it->index) {
10517 ret = i40e_aq_del_mirror_rule(hw, seid,
10518 mirr_rule->rule_type,
10519 mirr_rule->entries,
10520 mirr_rule->num_entries, mirr_rule->id);
10523 "failed to remove mirror rule: status = %d, aq_err = %d.",
10524 ret, hw->aq.asq_last_status);
10527 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10528 rte_free(mirr_rule);
10529 pf->nb_mirror_rule--;
10531 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10538 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10540 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10541 uint64_t systim_cycles;
10543 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10544 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10547 return systim_cycles;
10551 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10553 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10554 uint64_t rx_tstamp;
10556 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10557 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10564 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10566 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10567 uint64_t tx_tstamp;
10569 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10570 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10577 i40e_start_timecounters(struct rte_eth_dev *dev)
10579 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10580 struct i40e_adapter *adapter =
10581 (struct i40e_adapter *)dev->data->dev_private;
10582 struct rte_eth_link link;
10583 uint32_t tsync_inc_l;
10584 uint32_t tsync_inc_h;
10586 /* Get current link speed. */
10587 i40e_dev_link_update(dev, 1);
10588 rte_eth_linkstatus_get(dev, &link);
10590 switch (link.link_speed) {
10591 case ETH_SPEED_NUM_40G:
10592 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10593 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10595 case ETH_SPEED_NUM_10G:
10596 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10597 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10599 case ETH_SPEED_NUM_1G:
10600 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10601 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10608 /* Set the timesync increment value. */
10609 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10610 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10612 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10613 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10614 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10616 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10617 adapter->systime_tc.cc_shift = 0;
10618 adapter->systime_tc.nsec_mask = 0;
10620 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10621 adapter->rx_tstamp_tc.cc_shift = 0;
10622 adapter->rx_tstamp_tc.nsec_mask = 0;
10624 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10625 adapter->tx_tstamp_tc.cc_shift = 0;
10626 adapter->tx_tstamp_tc.nsec_mask = 0;
10630 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10632 struct i40e_adapter *adapter =
10633 (struct i40e_adapter *)dev->data->dev_private;
10635 adapter->systime_tc.nsec += delta;
10636 adapter->rx_tstamp_tc.nsec += delta;
10637 adapter->tx_tstamp_tc.nsec += delta;
10643 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10646 struct i40e_adapter *adapter =
10647 (struct i40e_adapter *)dev->data->dev_private;
10649 ns = rte_timespec_to_ns(ts);
10651 /* Set the timecounters to a new value. */
10652 adapter->systime_tc.nsec = ns;
10653 adapter->rx_tstamp_tc.nsec = ns;
10654 adapter->tx_tstamp_tc.nsec = ns;
10660 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10662 uint64_t ns, systime_cycles;
10663 struct i40e_adapter *adapter =
10664 (struct i40e_adapter *)dev->data->dev_private;
10666 systime_cycles = i40e_read_systime_cyclecounter(dev);
10667 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10668 *ts = rte_ns_to_timespec(ns);
10674 i40e_timesync_enable(struct rte_eth_dev *dev)
10676 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10677 uint32_t tsync_ctl_l;
10678 uint32_t tsync_ctl_h;
10680 /* Stop the timesync system time. */
10681 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10682 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10683 /* Reset the timesync system time value. */
10684 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10685 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10687 i40e_start_timecounters(dev);
10689 /* Clear timesync registers. */
10690 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10691 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10692 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10693 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10694 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10695 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10697 /* Enable timestamping of PTP packets. */
10698 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10699 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10701 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10702 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10703 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10705 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10706 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10712 i40e_timesync_disable(struct rte_eth_dev *dev)
10714 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10715 uint32_t tsync_ctl_l;
10716 uint32_t tsync_ctl_h;
10718 /* Disable timestamping of transmitted PTP packets. */
10719 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10720 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10722 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10723 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10725 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10726 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10728 /* Reset the timesync increment value. */
10729 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10730 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10736 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10737 struct timespec *timestamp, uint32_t flags)
10739 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10740 struct i40e_adapter *adapter =
10741 (struct i40e_adapter *)dev->data->dev_private;
10743 uint32_t sync_status;
10744 uint32_t index = flags & 0x03;
10745 uint64_t rx_tstamp_cycles;
10748 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10749 if ((sync_status & (1 << index)) == 0)
10752 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10753 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10754 *timestamp = rte_ns_to_timespec(ns);
10760 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10761 struct timespec *timestamp)
10763 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10764 struct i40e_adapter *adapter =
10765 (struct i40e_adapter *)dev->data->dev_private;
10767 uint32_t sync_status;
10768 uint64_t tx_tstamp_cycles;
10771 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10772 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10775 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10776 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10777 *timestamp = rte_ns_to_timespec(ns);
10783 * i40e_parse_dcb_configure - parse dcb configure from user
10784 * @dev: the device being configured
10785 * @dcb_cfg: pointer of the result of parse
10786 * @*tc_map: bit map of enabled traffic classes
10788 * Returns 0 on success, negative value on failure
10791 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10792 struct i40e_dcbx_config *dcb_cfg,
10795 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10796 uint8_t i, tc_bw, bw_lf;
10798 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10800 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10801 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10802 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10806 /* assume each tc has the same bw */
10807 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10808 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10809 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10810 /* to ensure the sum of tcbw is equal to 100 */
10811 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10812 for (i = 0; i < bw_lf; i++)
10813 dcb_cfg->etscfg.tcbwtable[i]++;
10815 /* assume each tc has the same Transmission Selection Algorithm */
10816 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10817 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10819 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10820 dcb_cfg->etscfg.prioritytable[i] =
10821 dcb_rx_conf->dcb_tc[i];
10823 /* FW needs one App to configure HW */
10824 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10825 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10826 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10827 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10829 if (dcb_rx_conf->nb_tcs == 0)
10830 *tc_map = 1; /* tc0 only */
10832 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10834 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10835 dcb_cfg->pfc.willing = 0;
10836 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10837 dcb_cfg->pfc.pfcenable = *tc_map;
10843 static enum i40e_status_code
10844 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10845 struct i40e_aqc_vsi_properties_data *info,
10846 uint8_t enabled_tcmap)
10848 enum i40e_status_code ret;
10849 int i, total_tc = 0;
10850 uint16_t qpnum_per_tc, bsf, qp_idx;
10851 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10852 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10853 uint16_t used_queues;
10855 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10856 if (ret != I40E_SUCCESS)
10859 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10860 if (enabled_tcmap & (1 << i))
10865 vsi->enabled_tc = enabled_tcmap;
10867 /* different VSI has different queues assigned */
10868 if (vsi->type == I40E_VSI_MAIN)
10869 used_queues = dev_data->nb_rx_queues -
10870 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10871 else if (vsi->type == I40E_VSI_VMDQ2)
10872 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10874 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10875 return I40E_ERR_NO_AVAILABLE_VSI;
10878 qpnum_per_tc = used_queues / total_tc;
10879 /* Number of queues per enabled TC */
10880 if (qpnum_per_tc == 0) {
10881 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10882 return I40E_ERR_INVALID_QP_ID;
10884 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10885 I40E_MAX_Q_PER_TC);
10886 bsf = rte_bsf32(qpnum_per_tc);
10889 * Configure TC and queue mapping parameters, for enabled TC,
10890 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10891 * default queue will serve it.
10894 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10895 if (vsi->enabled_tc & (1 << i)) {
10896 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10897 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10898 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10899 qp_idx += qpnum_per_tc;
10901 info->tc_mapping[i] = 0;
10904 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10905 if (vsi->type == I40E_VSI_SRIOV) {
10906 info->mapping_flags |=
10907 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10908 for (i = 0; i < vsi->nb_qps; i++)
10909 info->queue_mapping[i] =
10910 rte_cpu_to_le_16(vsi->base_queue + i);
10912 info->mapping_flags |=
10913 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10914 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10916 info->valid_sections |=
10917 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10919 return I40E_SUCCESS;
10923 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10924 * @veb: VEB to be configured
10925 * @tc_map: enabled TC bitmap
10927 * Returns 0 on success, negative value on failure
10929 static enum i40e_status_code
10930 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10932 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10933 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10934 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10935 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10936 enum i40e_status_code ret = I40E_SUCCESS;
10940 /* Check if enabled_tc is same as existing or new TCs */
10941 if (veb->enabled_tc == tc_map)
10944 /* configure tc bandwidth */
10945 memset(&veb_bw, 0, sizeof(veb_bw));
10946 veb_bw.tc_valid_bits = tc_map;
10947 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10948 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10949 if (tc_map & BIT_ULL(i))
10950 veb_bw.tc_bw_share_credits[i] = 1;
10952 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10956 "AQ command Config switch_comp BW allocation per TC failed = %d",
10957 hw->aq.asq_last_status);
10961 memset(&ets_query, 0, sizeof(ets_query));
10962 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10964 if (ret != I40E_SUCCESS) {
10966 "Failed to get switch_comp ETS configuration %u",
10967 hw->aq.asq_last_status);
10970 memset(&bw_query, 0, sizeof(bw_query));
10971 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10973 if (ret != I40E_SUCCESS) {
10975 "Failed to get switch_comp bandwidth configuration %u",
10976 hw->aq.asq_last_status);
10980 /* store and print out BW info */
10981 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10982 veb->bw_info.bw_max = ets_query.tc_bw_max;
10983 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10984 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10985 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10986 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10987 I40E_16_BIT_WIDTH);
10988 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10989 veb->bw_info.bw_ets_share_credits[i] =
10990 bw_query.tc_bw_share_credits[i];
10991 veb->bw_info.bw_ets_credits[i] =
10992 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10993 /* 4 bits per TC, 4th bit is reserved */
10994 veb->bw_info.bw_ets_max[i] =
10995 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10996 RTE_LEN2MASK(3, uint8_t));
10997 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10998 veb->bw_info.bw_ets_share_credits[i]);
10999 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11000 veb->bw_info.bw_ets_credits[i]);
11001 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11002 veb->bw_info.bw_ets_max[i]);
11005 veb->enabled_tc = tc_map;
11012 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11013 * @vsi: VSI to be configured
11014 * @tc_map: enabled TC bitmap
11016 * Returns 0 on success, negative value on failure
11018 static enum i40e_status_code
11019 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11021 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11022 struct i40e_vsi_context ctxt;
11023 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11024 enum i40e_status_code ret = I40E_SUCCESS;
11027 /* Check if enabled_tc is same as existing or new TCs */
11028 if (vsi->enabled_tc == tc_map)
11031 /* configure tc bandwidth */
11032 memset(&bw_data, 0, sizeof(bw_data));
11033 bw_data.tc_valid_bits = tc_map;
11034 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11035 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11036 if (tc_map & BIT_ULL(i))
11037 bw_data.tc_bw_credits[i] = 1;
11039 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11042 "AQ command Config VSI BW allocation per TC failed = %d",
11043 hw->aq.asq_last_status);
11046 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11047 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11049 /* Update Queue Pairs Mapping for currently enabled UPs */
11050 ctxt.seid = vsi->seid;
11051 ctxt.pf_num = hw->pf_id;
11053 ctxt.uplink_seid = vsi->uplink_seid;
11054 ctxt.info = vsi->info;
11056 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11060 /* Update the VSI after updating the VSI queue-mapping information */
11061 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11063 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11064 hw->aq.asq_last_status);
11067 /* update the local VSI info with updated queue map */
11068 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11069 sizeof(vsi->info.tc_mapping));
11070 rte_memcpy(&vsi->info.queue_mapping,
11071 &ctxt.info.queue_mapping,
11072 sizeof(vsi->info.queue_mapping));
11073 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11074 vsi->info.valid_sections = 0;
11076 /* query and update current VSI BW information */
11077 ret = i40e_vsi_get_bw_config(vsi);
11080 "Failed updating vsi bw info, err %s aq_err %s",
11081 i40e_stat_str(hw, ret),
11082 i40e_aq_str(hw, hw->aq.asq_last_status));
11086 vsi->enabled_tc = tc_map;
11093 * i40e_dcb_hw_configure - program the dcb setting to hw
11094 * @pf: pf the configuration is taken on
11095 * @new_cfg: new configuration
11096 * @tc_map: enabled TC bitmap
11098 * Returns 0 on success, negative value on failure
11100 static enum i40e_status_code
11101 i40e_dcb_hw_configure(struct i40e_pf *pf,
11102 struct i40e_dcbx_config *new_cfg,
11105 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11106 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11107 struct i40e_vsi *main_vsi = pf->main_vsi;
11108 struct i40e_vsi_list *vsi_list;
11109 enum i40e_status_code ret;
11113 /* Use the FW API if FW > v4.4*/
11114 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11115 (hw->aq.fw_maj_ver >= 5))) {
11117 "FW < v4.4, can not use FW LLDP API to configure DCB");
11118 return I40E_ERR_FIRMWARE_API_VERSION;
11121 /* Check if need reconfiguration */
11122 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11123 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11124 return I40E_SUCCESS;
11127 /* Copy the new config to the current config */
11128 *old_cfg = *new_cfg;
11129 old_cfg->etsrec = old_cfg->etscfg;
11130 ret = i40e_set_dcb_config(hw);
11132 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11133 i40e_stat_str(hw, ret),
11134 i40e_aq_str(hw, hw->aq.asq_last_status));
11137 /* set receive Arbiter to RR mode and ETS scheme by default */
11138 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11139 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11140 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11141 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11142 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11143 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11144 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11145 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11146 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11147 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11148 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11149 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11150 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11152 /* get local mib to check whether it is configured correctly */
11154 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11155 /* Get Local DCB Config */
11156 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11157 &hw->local_dcbx_config);
11159 /* if Veb is created, need to update TC of it at first */
11160 if (main_vsi->veb) {
11161 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11163 PMD_INIT_LOG(WARNING,
11164 "Failed configuring TC for VEB seid=%d",
11165 main_vsi->veb->seid);
11167 /* Update each VSI */
11168 i40e_vsi_config_tc(main_vsi, tc_map);
11169 if (main_vsi->veb) {
11170 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11171 /* Beside main VSI and VMDQ VSIs, only enable default
11172 * TC for other VSIs
11174 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11175 ret = i40e_vsi_config_tc(vsi_list->vsi,
11178 ret = i40e_vsi_config_tc(vsi_list->vsi,
11179 I40E_DEFAULT_TCMAP);
11181 PMD_INIT_LOG(WARNING,
11182 "Failed configuring TC for VSI seid=%d",
11183 vsi_list->vsi->seid);
11187 return I40E_SUCCESS;
11191 * i40e_dcb_init_configure - initial dcb config
11192 * @dev: device being configured
11193 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11195 * Returns 0 on success, negative value on failure
11198 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11200 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11201 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11204 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11205 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11209 /* DCB initialization:
11210 * Update DCB configuration from the Firmware and configure
11211 * LLDP MIB change event.
11213 if (sw_dcb == TRUE) {
11214 ret = i40e_init_dcb(hw);
11215 /* If lldp agent is stopped, the return value from
11216 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11217 * adminq status. Otherwise, it should return success.
11219 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11220 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11221 memset(&hw->local_dcbx_config, 0,
11222 sizeof(struct i40e_dcbx_config));
11223 /* set dcb default configuration */
11224 hw->local_dcbx_config.etscfg.willing = 0;
11225 hw->local_dcbx_config.etscfg.maxtcs = 0;
11226 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11227 hw->local_dcbx_config.etscfg.tsatable[0] =
11229 /* all UPs mapping to TC0 */
11230 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11231 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11232 hw->local_dcbx_config.etsrec =
11233 hw->local_dcbx_config.etscfg;
11234 hw->local_dcbx_config.pfc.willing = 0;
11235 hw->local_dcbx_config.pfc.pfccap =
11236 I40E_MAX_TRAFFIC_CLASS;
11237 /* FW needs one App to configure HW */
11238 hw->local_dcbx_config.numapps = 1;
11239 hw->local_dcbx_config.app[0].selector =
11240 I40E_APP_SEL_ETHTYPE;
11241 hw->local_dcbx_config.app[0].priority = 3;
11242 hw->local_dcbx_config.app[0].protocolid =
11243 I40E_APP_PROTOID_FCOE;
11244 ret = i40e_set_dcb_config(hw);
11247 "default dcb config fails. err = %d, aq_err = %d.",
11248 ret, hw->aq.asq_last_status);
11253 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11254 ret, hw->aq.asq_last_status);
11258 ret = i40e_aq_start_lldp(hw, NULL);
11259 if (ret != I40E_SUCCESS)
11260 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11262 ret = i40e_init_dcb(hw);
11264 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11266 "HW doesn't support DCBX offload.");
11271 "DCBX configuration failed, err = %d, aq_err = %d.",
11272 ret, hw->aq.asq_last_status);
11280 * i40e_dcb_setup - setup dcb related config
11281 * @dev: device being configured
11283 * Returns 0 on success, negative value on failure
11286 i40e_dcb_setup(struct rte_eth_dev *dev)
11288 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11289 struct i40e_dcbx_config dcb_cfg;
11290 uint8_t tc_map = 0;
11293 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11294 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11298 if (pf->vf_num != 0)
11299 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11301 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11303 PMD_INIT_LOG(ERR, "invalid dcb config");
11306 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11308 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11316 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11317 struct rte_eth_dcb_info *dcb_info)
11319 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11320 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11321 struct i40e_vsi *vsi = pf->main_vsi;
11322 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11323 uint16_t bsf, tc_mapping;
11326 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11327 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11329 dcb_info->nb_tcs = 1;
11330 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11331 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11332 for (i = 0; i < dcb_info->nb_tcs; i++)
11333 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11335 /* get queue mapping if vmdq is disabled */
11336 if (!pf->nb_cfg_vmdq_vsi) {
11337 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11338 if (!(vsi->enabled_tc & (1 << i)))
11340 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11341 dcb_info->tc_queue.tc_rxq[j][i].base =
11342 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11343 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11344 dcb_info->tc_queue.tc_txq[j][i].base =
11345 dcb_info->tc_queue.tc_rxq[j][i].base;
11346 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11347 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11348 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11349 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11350 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11355 /* get queue mapping if vmdq is enabled */
11357 vsi = pf->vmdq[j].vsi;
11358 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11359 if (!(vsi->enabled_tc & (1 << i)))
11361 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11362 dcb_info->tc_queue.tc_rxq[j][i].base =
11363 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11364 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11365 dcb_info->tc_queue.tc_txq[j][i].base =
11366 dcb_info->tc_queue.tc_rxq[j][i].base;
11367 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11368 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11369 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11370 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11371 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11374 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11379 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11381 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11382 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11383 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11384 uint16_t msix_intr;
11386 msix_intr = intr_handle->intr_vec[queue_id];
11387 if (msix_intr == I40E_MISC_VEC_ID)
11388 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11389 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11390 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11391 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11394 I40E_PFINT_DYN_CTLN(msix_intr -
11395 I40E_RX_VEC_START),
11396 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11397 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11398 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11400 I40E_WRITE_FLUSH(hw);
11401 rte_intr_enable(&pci_dev->intr_handle);
11407 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11409 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11410 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11411 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11412 uint16_t msix_intr;
11414 msix_intr = intr_handle->intr_vec[queue_id];
11415 if (msix_intr == I40E_MISC_VEC_ID)
11416 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11417 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11420 I40E_PFINT_DYN_CTLN(msix_intr -
11421 I40E_RX_VEC_START),
11422 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11423 I40E_WRITE_FLUSH(hw);
11428 static int i40e_get_regs(struct rte_eth_dev *dev,
11429 struct rte_dev_reg_info *regs)
11431 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11432 uint32_t *ptr_data = regs->data;
11433 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11434 const struct i40e_reg_info *reg_info;
11436 if (ptr_data == NULL) {
11437 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11438 regs->width = sizeof(uint32_t);
11442 /* The first few registers have to be read using AQ operations */
11444 while (i40e_regs_adminq[reg_idx].name) {
11445 reg_info = &i40e_regs_adminq[reg_idx++];
11446 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11448 arr_idx2 <= reg_info->count2;
11450 reg_offset = arr_idx * reg_info->stride1 +
11451 arr_idx2 * reg_info->stride2;
11452 reg_offset += reg_info->base_addr;
11453 ptr_data[reg_offset >> 2] =
11454 i40e_read_rx_ctl(hw, reg_offset);
11458 /* The remaining registers can be read using primitives */
11460 while (i40e_regs_others[reg_idx].name) {
11461 reg_info = &i40e_regs_others[reg_idx++];
11462 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11464 arr_idx2 <= reg_info->count2;
11466 reg_offset = arr_idx * reg_info->stride1 +
11467 arr_idx2 * reg_info->stride2;
11468 reg_offset += reg_info->base_addr;
11469 ptr_data[reg_offset >> 2] =
11470 I40E_READ_REG(hw, reg_offset);
11477 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11479 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11481 /* Convert word count to byte count */
11482 return hw->nvm.sr_size << 1;
11485 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11486 struct rte_dev_eeprom_info *eeprom)
11488 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11489 uint16_t *data = eeprom->data;
11490 uint16_t offset, length, cnt_words;
11493 offset = eeprom->offset >> 1;
11494 length = eeprom->length >> 1;
11495 cnt_words = length;
11497 if (offset > hw->nvm.sr_size ||
11498 offset + length > hw->nvm.sr_size) {
11499 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11503 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11505 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11506 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11507 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11514 static int i40e_get_module_info(struct rte_eth_dev *dev,
11515 struct rte_eth_dev_module_info *modinfo)
11517 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11518 uint32_t sff8472_comp = 0;
11519 uint32_t sff8472_swap = 0;
11520 uint32_t sff8636_rev = 0;
11521 i40e_status status;
11524 /* Check if firmware supports reading module EEPROM. */
11525 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11527 "Module EEPROM memory read not supported. "
11528 "Please update the NVM image.\n");
11532 status = i40e_update_link_info(hw);
11536 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11538 "Cannot read module EEPROM memory. "
11539 "No module connected.\n");
11543 type = hw->phy.link_info.module_type[0];
11546 case I40E_MODULE_TYPE_SFP:
11547 status = i40e_aq_get_phy_register(hw,
11548 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11549 I40E_I2C_EEPROM_DEV_ADDR,
11550 I40E_MODULE_SFF_8472_COMP,
11551 &sff8472_comp, NULL);
11555 status = i40e_aq_get_phy_register(hw,
11556 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11557 I40E_I2C_EEPROM_DEV_ADDR,
11558 I40E_MODULE_SFF_8472_SWAP,
11559 &sff8472_swap, NULL);
11563 /* Check if the module requires address swap to access
11564 * the other EEPROM memory page.
11566 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11567 PMD_DRV_LOG(WARNING,
11568 "Module address swap to access "
11569 "page 0xA2 is not supported.\n");
11570 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11571 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11572 } else if (sff8472_comp == 0x00) {
11573 /* Module is not SFF-8472 compliant */
11574 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11575 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11577 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11578 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11581 case I40E_MODULE_TYPE_QSFP_PLUS:
11582 /* Read from memory page 0. */
11583 status = i40e_aq_get_phy_register(hw,
11584 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11586 I40E_MODULE_REVISION_ADDR,
11587 &sff8636_rev, NULL);
11590 /* Determine revision compliance byte */
11591 if (sff8636_rev > 0x02) {
11592 /* Module is SFF-8636 compliant */
11593 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11594 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11596 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11597 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11600 case I40E_MODULE_TYPE_QSFP28:
11601 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11602 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11605 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11611 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11612 struct rte_dev_eeprom_info *info)
11614 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11615 bool is_sfp = false;
11616 i40e_status status;
11617 uint8_t *data = info->data;
11618 uint32_t value = 0;
11621 if (!info || !info->length || !data)
11624 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11627 for (i = 0; i < info->length; i++) {
11628 u32 offset = i + info->offset;
11629 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11631 /* Check if we need to access the other memory page */
11633 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11634 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11635 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11638 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11639 /* Compute memory page number and offset. */
11640 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11644 status = i40e_aq_get_phy_register(hw,
11645 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11646 addr, offset, &value, NULL);
11649 data[i] = (uint8_t)value;
11654 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11655 struct ether_addr *mac_addr)
11657 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11658 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11659 struct i40e_vsi *vsi = pf->main_vsi;
11660 struct i40e_mac_filter_info mac_filter;
11661 struct i40e_mac_filter *f;
11664 if (!is_valid_assigned_ether_addr(mac_addr)) {
11665 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11669 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11670 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11675 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11679 mac_filter = f->mac_info;
11680 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11681 if (ret != I40E_SUCCESS) {
11682 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11685 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11686 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11687 if (ret != I40E_SUCCESS) {
11688 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11691 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11693 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11694 mac_addr->addr_bytes, NULL);
11695 if (ret != I40E_SUCCESS) {
11696 PMD_DRV_LOG(ERR, "Failed to change mac");
11704 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11706 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11707 struct rte_eth_dev_data *dev_data = pf->dev_data;
11708 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11711 /* check if mtu is within the allowed range */
11712 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11715 /* mtu setting is forbidden if port is start */
11716 if (dev_data->dev_started) {
11717 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11718 dev_data->port_id);
11722 if (frame_size > ETHER_MAX_LEN)
11723 dev_data->dev_conf.rxmode.offloads |=
11724 DEV_RX_OFFLOAD_JUMBO_FRAME;
11726 dev_data->dev_conf.rxmode.offloads &=
11727 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11729 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11734 /* Restore ethertype filter */
11736 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11738 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11739 struct i40e_ethertype_filter_list
11740 *ethertype_list = &pf->ethertype.ethertype_list;
11741 struct i40e_ethertype_filter *f;
11742 struct i40e_control_filter_stats stats;
11745 TAILQ_FOREACH(f, ethertype_list, rules) {
11747 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11748 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11749 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11750 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11751 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11753 memset(&stats, 0, sizeof(stats));
11754 i40e_aq_add_rem_control_packet_filter(hw,
11755 f->input.mac_addr.addr_bytes,
11756 f->input.ether_type,
11757 flags, pf->main_vsi->seid,
11758 f->queue, 1, &stats, NULL);
11760 PMD_DRV_LOG(INFO, "Ethertype filter:"
11761 " mac_etype_used = %u, etype_used = %u,"
11762 " mac_etype_free = %u, etype_free = %u",
11763 stats.mac_etype_used, stats.etype_used,
11764 stats.mac_etype_free, stats.etype_free);
11767 /* Restore tunnel filter */
11769 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11771 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11772 struct i40e_vsi *vsi;
11773 struct i40e_pf_vf *vf;
11774 struct i40e_tunnel_filter_list
11775 *tunnel_list = &pf->tunnel.tunnel_list;
11776 struct i40e_tunnel_filter *f;
11777 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11778 bool big_buffer = 0;
11780 TAILQ_FOREACH(f, tunnel_list, rules) {
11782 vsi = pf->main_vsi;
11784 vf = &pf->vfs[f->vf_id];
11787 memset(&cld_filter, 0, sizeof(cld_filter));
11788 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11789 (struct ether_addr *)&cld_filter.element.outer_mac);
11790 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11791 (struct ether_addr *)&cld_filter.element.inner_mac);
11792 cld_filter.element.inner_vlan = f->input.inner_vlan;
11793 cld_filter.element.flags = f->input.flags;
11794 cld_filter.element.tenant_id = f->input.tenant_id;
11795 cld_filter.element.queue_number = f->queue;
11796 rte_memcpy(cld_filter.general_fields,
11797 f->input.general_fields,
11798 sizeof(f->input.general_fields));
11800 if (((f->input.flags &
11801 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11802 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11804 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11805 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11807 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11808 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11812 i40e_aq_add_cloud_filters_big_buffer(hw,
11813 vsi->seid, &cld_filter, 1);
11815 i40e_aq_add_cloud_filters(hw, vsi->seid,
11816 &cld_filter.element, 1);
11820 /* Restore rss filter */
11822 i40e_rss_filter_restore(struct i40e_pf *pf)
11824 struct i40e_rte_flow_rss_conf *conf =
11826 if (conf->conf.queue_num)
11827 i40e_config_rss_filter(pf, conf, TRUE);
11831 i40e_filter_restore(struct i40e_pf *pf)
11833 i40e_ethertype_filter_restore(pf);
11834 i40e_tunnel_filter_restore(pf);
11835 i40e_fdir_filter_restore(pf);
11836 i40e_rss_filter_restore(pf);
11840 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11842 if (strcmp(dev->device->driver->name, drv->driver.name))
11849 is_i40e_supported(struct rte_eth_dev *dev)
11851 return is_device_supported(dev, &rte_i40e_pmd);
11854 struct i40e_customized_pctype*
11855 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11859 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11860 if (pf->customized_pctype[i].index == index)
11861 return &pf->customized_pctype[i];
11867 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11868 uint32_t pkg_size, uint32_t proto_num,
11869 struct rte_pmd_i40e_proto_info *proto,
11870 enum rte_pmd_i40e_package_op op)
11872 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11873 uint32_t pctype_num;
11874 struct rte_pmd_i40e_ptype_info *pctype;
11875 uint32_t buff_size;
11876 struct i40e_customized_pctype *new_pctype = NULL;
11878 uint8_t pctype_value;
11883 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11884 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11885 PMD_DRV_LOG(ERR, "Unsupported operation.");
11889 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11890 (uint8_t *)&pctype_num, sizeof(pctype_num),
11891 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11893 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11897 PMD_DRV_LOG(INFO, "No new pctype added");
11901 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11902 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11904 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11907 /* get information about new pctype list */
11908 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11909 (uint8_t *)pctype, buff_size,
11910 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11912 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11917 /* Update customized pctype. */
11918 for (i = 0; i < pctype_num; i++) {
11919 pctype_value = pctype[i].ptype_id;
11920 memset(name, 0, sizeof(name));
11921 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11922 proto_id = pctype[i].protocols[j];
11923 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11925 for (n = 0; n < proto_num; n++) {
11926 if (proto[n].proto_id != proto_id)
11928 strcat(name, proto[n].name);
11933 name[strlen(name) - 1] = '\0';
11934 if (!strcmp(name, "GTPC"))
11936 i40e_find_customized_pctype(pf,
11937 I40E_CUSTOMIZED_GTPC);
11938 else if (!strcmp(name, "GTPU_IPV4"))
11940 i40e_find_customized_pctype(pf,
11941 I40E_CUSTOMIZED_GTPU_IPV4);
11942 else if (!strcmp(name, "GTPU_IPV6"))
11944 i40e_find_customized_pctype(pf,
11945 I40E_CUSTOMIZED_GTPU_IPV6);
11946 else if (!strcmp(name, "GTPU"))
11948 i40e_find_customized_pctype(pf,
11949 I40E_CUSTOMIZED_GTPU);
11951 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11952 new_pctype->pctype = pctype_value;
11953 new_pctype->valid = true;
11955 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11956 new_pctype->valid = false;
11966 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11967 uint32_t pkg_size, uint32_t proto_num,
11968 struct rte_pmd_i40e_proto_info *proto,
11969 enum rte_pmd_i40e_package_op op)
11971 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11972 uint16_t port_id = dev->data->port_id;
11973 uint32_t ptype_num;
11974 struct rte_pmd_i40e_ptype_info *ptype;
11975 uint32_t buff_size;
11977 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11982 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11983 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11984 PMD_DRV_LOG(ERR, "Unsupported operation.");
11988 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11989 rte_pmd_i40e_ptype_mapping_reset(port_id);
11993 /* get information about new ptype num */
11994 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11995 (uint8_t *)&ptype_num, sizeof(ptype_num),
11996 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11998 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12002 PMD_DRV_LOG(INFO, "No new ptype added");
12006 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12007 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12009 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12013 /* get information about new ptype list */
12014 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12015 (uint8_t *)ptype, buff_size,
12016 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12018 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12023 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12024 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12025 if (!ptype_mapping) {
12026 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12031 /* Update ptype mapping table. */
12032 for (i = 0; i < ptype_num; i++) {
12033 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12034 ptype_mapping[i].sw_ptype = 0;
12036 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12037 proto_id = ptype[i].protocols[j];
12038 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12040 for (n = 0; n < proto_num; n++) {
12041 if (proto[n].proto_id != proto_id)
12043 memset(name, 0, sizeof(name));
12044 strcpy(name, proto[n].name);
12045 if (!strncasecmp(name, "PPPOE", 5))
12046 ptype_mapping[i].sw_ptype |=
12047 RTE_PTYPE_L2_ETHER_PPPOE;
12048 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12050 ptype_mapping[i].sw_ptype |=
12051 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12052 ptype_mapping[i].sw_ptype |=
12054 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12056 ptype_mapping[i].sw_ptype |=
12057 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12058 ptype_mapping[i].sw_ptype |=
12059 RTE_PTYPE_INNER_L4_FRAG;
12060 } else if (!strncasecmp(name, "OIPV4", 5)) {
12061 ptype_mapping[i].sw_ptype |=
12062 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12064 } else if (!strncasecmp(name, "IPV4", 4) &&
12066 ptype_mapping[i].sw_ptype |=
12067 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12068 else if (!strncasecmp(name, "IPV4", 4) &&
12070 ptype_mapping[i].sw_ptype |=
12071 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12072 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12074 ptype_mapping[i].sw_ptype |=
12075 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12076 ptype_mapping[i].sw_ptype |=
12078 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12080 ptype_mapping[i].sw_ptype |=
12081 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12082 ptype_mapping[i].sw_ptype |=
12083 RTE_PTYPE_INNER_L4_FRAG;
12084 } else if (!strncasecmp(name, "OIPV6", 5)) {
12085 ptype_mapping[i].sw_ptype |=
12086 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12088 } else if (!strncasecmp(name, "IPV6", 4) &&
12090 ptype_mapping[i].sw_ptype |=
12091 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12092 else if (!strncasecmp(name, "IPV6", 4) &&
12094 ptype_mapping[i].sw_ptype |=
12095 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12096 else if (!strncasecmp(name, "UDP", 3) &&
12098 ptype_mapping[i].sw_ptype |=
12100 else if (!strncasecmp(name, "UDP", 3) &&
12102 ptype_mapping[i].sw_ptype |=
12103 RTE_PTYPE_INNER_L4_UDP;
12104 else if (!strncasecmp(name, "TCP", 3) &&
12106 ptype_mapping[i].sw_ptype |=
12108 else if (!strncasecmp(name, "TCP", 3) &&
12110 ptype_mapping[i].sw_ptype |=
12111 RTE_PTYPE_INNER_L4_TCP;
12112 else if (!strncasecmp(name, "SCTP", 4) &&
12114 ptype_mapping[i].sw_ptype |=
12116 else if (!strncasecmp(name, "SCTP", 4) &&
12118 ptype_mapping[i].sw_ptype |=
12119 RTE_PTYPE_INNER_L4_SCTP;
12120 else if ((!strncasecmp(name, "ICMP", 4) ||
12121 !strncasecmp(name, "ICMPV6", 6)) &&
12123 ptype_mapping[i].sw_ptype |=
12125 else if ((!strncasecmp(name, "ICMP", 4) ||
12126 !strncasecmp(name, "ICMPV6", 6)) &&
12128 ptype_mapping[i].sw_ptype |=
12129 RTE_PTYPE_INNER_L4_ICMP;
12130 else if (!strncasecmp(name, "GTPC", 4)) {
12131 ptype_mapping[i].sw_ptype |=
12132 RTE_PTYPE_TUNNEL_GTPC;
12134 } else if (!strncasecmp(name, "GTPU", 4)) {
12135 ptype_mapping[i].sw_ptype |=
12136 RTE_PTYPE_TUNNEL_GTPU;
12138 } else if (!strncasecmp(name, "GRENAT", 6)) {
12139 ptype_mapping[i].sw_ptype |=
12140 RTE_PTYPE_TUNNEL_GRENAT;
12142 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
12143 ptype_mapping[i].sw_ptype |=
12144 RTE_PTYPE_TUNNEL_L2TP;
12153 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12156 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12158 rte_free(ptype_mapping);
12164 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12165 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12167 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12168 uint32_t proto_num;
12169 struct rte_pmd_i40e_proto_info *proto;
12170 uint32_t buff_size;
12174 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12175 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12176 PMD_DRV_LOG(ERR, "Unsupported operation.");
12180 /* get information about protocol number */
12181 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12182 (uint8_t *)&proto_num, sizeof(proto_num),
12183 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12185 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12189 PMD_DRV_LOG(INFO, "No new protocol added");
12193 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12194 proto = rte_zmalloc("new_proto", buff_size, 0);
12196 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12200 /* get information about protocol list */
12201 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12202 (uint8_t *)proto, buff_size,
12203 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12205 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12210 /* Check if GTP is supported. */
12211 for (i = 0; i < proto_num; i++) {
12212 if (!strncmp(proto[i].name, "GTP", 3)) {
12213 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12214 pf->gtp_support = true;
12216 pf->gtp_support = false;
12221 /* Update customized pctype info */
12222 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12223 proto_num, proto, op);
12225 PMD_DRV_LOG(INFO, "No pctype is updated.");
12227 /* Update customized ptype info */
12228 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12229 proto_num, proto, op);
12231 PMD_DRV_LOG(INFO, "No ptype is updated.");
12236 /* Create a QinQ cloud filter
12238 * The Fortville NIC has limited resources for tunnel filters,
12239 * so we can only reuse existing filters.
12241 * In step 1 we define which Field Vector fields can be used for
12243 * As we do not have the inner tag defined as a field,
12244 * we have to define it first, by reusing one of L1 entries.
12246 * In step 2 we are replacing one of existing filter types with
12247 * a new one for QinQ.
12248 * As we reusing L1 and replacing L2, some of the default filter
12249 * types will disappear,which depends on L1 and L2 entries we reuse.
12251 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12253 * 1. Create L1 filter of outer vlan (12b) which will be in use
12254 * later when we define the cloud filter.
12255 * a. Valid_flags.replace_cloud = 0
12256 * b. Old_filter = 10 (Stag_Inner_Vlan)
12257 * c. New_filter = 0x10
12258 * d. TR bit = 0xff (optional, not used here)
12259 * e. Buffer – 2 entries:
12260 * i. Byte 0 = 8 (outer vlan FV index).
12262 * Byte 2-3 = 0x0fff
12263 * ii. Byte 0 = 37 (inner vlan FV index).
12265 * Byte 2-3 = 0x0fff
12268 * 2. Create cloud filter using two L1 filters entries: stag and
12269 * new filter(outer vlan+ inner vlan)
12270 * a. Valid_flags.replace_cloud = 1
12271 * b. Old_filter = 1 (instead of outer IP)
12272 * c. New_filter = 0x10
12273 * d. Buffer – 2 entries:
12274 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12275 * Byte 1-3 = 0 (rsv)
12276 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12277 * Byte 9-11 = 0 (rsv)
12280 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12282 int ret = -ENOTSUP;
12283 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12284 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12285 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12286 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12288 if (pf->support_multi_driver) {
12289 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12294 memset(&filter_replace, 0,
12295 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12296 memset(&filter_replace_buf, 0,
12297 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12299 /* create L1 filter */
12300 filter_replace.old_filter_type =
12301 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12302 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12303 filter_replace.tr_bit = 0;
12305 /* Prepare the buffer, 2 entries */
12306 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12307 filter_replace_buf.data[0] |=
12308 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12309 /* Field Vector 12b mask */
12310 filter_replace_buf.data[2] = 0xff;
12311 filter_replace_buf.data[3] = 0x0f;
12312 filter_replace_buf.data[4] =
12313 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12314 filter_replace_buf.data[4] |=
12315 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12316 /* Field Vector 12b mask */
12317 filter_replace_buf.data[6] = 0xff;
12318 filter_replace_buf.data[7] = 0x0f;
12319 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12320 &filter_replace_buf);
12321 if (ret != I40E_SUCCESS)
12324 if (filter_replace.old_filter_type !=
12325 filter_replace.new_filter_type)
12326 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12327 " original: 0x%x, new: 0x%x",
12329 filter_replace.old_filter_type,
12330 filter_replace.new_filter_type);
12332 /* Apply the second L2 cloud filter */
12333 memset(&filter_replace, 0,
12334 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12335 memset(&filter_replace_buf, 0,
12336 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12338 /* create L2 filter, input for L2 filter will be L1 filter */
12339 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12340 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12341 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12343 /* Prepare the buffer, 2 entries */
12344 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12345 filter_replace_buf.data[0] |=
12346 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12347 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12348 filter_replace_buf.data[4] |=
12349 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12350 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12351 &filter_replace_buf);
12352 if (!ret && (filter_replace.old_filter_type !=
12353 filter_replace.new_filter_type))
12354 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12355 " original: 0x%x, new: 0x%x",
12357 filter_replace.old_filter_type,
12358 filter_replace.new_filter_type);
12364 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12365 const struct rte_flow_action_rss *in)
12367 if (in->key_len > RTE_DIM(out->key) ||
12368 in->queue_num > RTE_DIM(out->queue))
12370 out->conf = (struct rte_flow_action_rss){
12372 .level = in->level,
12373 .types = in->types,
12374 .key_len = in->key_len,
12375 .queue_num = in->queue_num,
12376 .key = memcpy(out->key, in->key, in->key_len),
12377 .queue = memcpy(out->queue, in->queue,
12378 sizeof(*in->queue) * in->queue_num),
12384 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12385 const struct rte_flow_action_rss *with)
12387 return (comp->func == with->func &&
12388 comp->level == with->level &&
12389 comp->types == with->types &&
12390 comp->key_len == with->key_len &&
12391 comp->queue_num == with->queue_num &&
12392 !memcmp(comp->key, with->key, with->key_len) &&
12393 !memcmp(comp->queue, with->queue,
12394 sizeof(*with->queue) * with->queue_num));
12398 i40e_config_rss_filter(struct i40e_pf *pf,
12399 struct i40e_rte_flow_rss_conf *conf, bool add)
12401 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12402 uint32_t i, lut = 0;
12404 struct rte_eth_rss_conf rss_conf = {
12405 .rss_key = conf->conf.key_len ?
12406 (void *)(uintptr_t)conf->conf.key : NULL,
12407 .rss_key_len = conf->conf.key_len,
12408 .rss_hf = conf->conf.types,
12410 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12413 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12414 i40e_pf_disable_rss(pf);
12415 memset(rss_info, 0,
12416 sizeof(struct i40e_rte_flow_rss_conf));
12422 if (rss_info->conf.queue_num)
12425 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12426 * It's necessary to calculate the actual PF queues that are configured.
12428 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12429 num = i40e_pf_calc_configured_queues_num(pf);
12431 num = pf->dev_data->nb_rx_queues;
12433 num = RTE_MIN(num, conf->conf.queue_num);
12434 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12438 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12442 /* Fill in redirection table */
12443 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12446 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12447 hw->func_caps.rss_table_entry_width) - 1));
12449 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12452 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12453 i40e_pf_disable_rss(pf);
12456 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12457 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12458 /* Random default keys */
12459 static uint32_t rss_key_default[] = {0x6b793944,
12460 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12461 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12462 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12464 rss_conf.rss_key = (uint8_t *)rss_key_default;
12465 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12469 i40e_hw_rss_hash_set(pf, &rss_conf);
12471 if (i40e_rss_conf_init(rss_info, &conf->conf))
12477 RTE_INIT(i40e_init_log);
12479 i40e_init_log(void)
12481 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12482 if (i40e_logtype_init >= 0)
12483 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12484 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12485 if (i40e_logtype_driver >= 0)
12486 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12489 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12490 QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12491 ETH_I40E_SUPPORT_MULTI_DRIVER "=1");