4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memzone.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_alarm.h>
54 #include <rte_eth_ctrl.h>
55 #include <rte_tailq.h>
56 #include <rte_hash_crc.h>
58 #include "i40e_logs.h"
59 #include "base/i40e_prototype.h"
60 #include "base/i40e_adminq_cmd.h"
61 #include "base/i40e_type.h"
62 #include "base/i40e_register.h"
63 #include "base/i40e_dcb.h"
64 #include "i40e_ethdev.h"
65 #include "i40e_rxtx.h"
67 #include "i40e_regs.h"
69 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
70 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
72 #define I40E_CLEAR_PXE_WAIT_MS 200
74 /* Maximun number of capability elements */
75 #define I40E_MAX_CAP_ELE_NUM 128
77 /* Wait count and interval */
78 #define I40E_CHK_Q_ENA_COUNT 1000
79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
81 /* Maximun number of VSI */
82 #define I40E_MAX_NUM_VSIS (384UL)
84 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
86 /* Flow control default timer */
87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
89 /* Flow control enable fwd bit */
90 #define I40E_PRTMAC_FWD_CTRL 0x00000001
92 /* Receive Packet Buffer size */
93 #define I40E_RXPBSIZE (968 * 1024)
96 #define I40E_KILOSHIFT 10
98 /* Flow control default high water */
99 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
101 /* Flow control default low water */
102 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
104 /* Receive Average Packet Size in Byte*/
105 #define I40E_PACKET_AVERAGE_SIZE 128
107 /* Mask of PF interrupt causes */
108 #define I40E_PFINT_ICR0_ENA_MASK ( \
109 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_GRST_MASK | \
112 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
113 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 /* Additional timesync values. */
133 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
134 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
135 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
136 #define I40E_PRTTSYN_TSYNENA 0x80000000
137 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
140 #define I40E_MAX_PERCENT 100
141 #define I40E_DEFAULT_DCB_APP_NUM 1
142 #define I40E_DEFAULT_DCB_APP_PRIO 3
145 * Below are values for writing un-exposed registers suggested
148 /* Destination MAC address */
149 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
150 /* Source MAC address */
151 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
153 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
155 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
156 /* Single VLAN tag in the inner L2 header */
157 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
158 /* Source IPv4 address */
159 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
160 /* Destination IPv4 address */
161 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
162 /* Source IPv4 address for X722 */
163 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
164 /* Destination IPv4 address for X722 */
165 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
166 /* IPv4 Protocol for X722 */
167 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
168 /* IPv4 Time to Live for X722 */
169 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
170 /* IPv4 Type of Service (TOS) */
171 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
173 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
174 /* IPv4 Time to Live */
175 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
176 /* Source IPv6 address */
177 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
178 /* Destination IPv6 address */
179 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
180 /* IPv6 Traffic Class (TC) */
181 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
182 /* IPv6 Next Header */
183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
187 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
188 /* Destination L4 port */
189 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
190 /* SCTP verification tag */
191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
194 /* Source port of tunneling UDP */
195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
196 /* Destination port of tunneling UDP */
197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
198 /* UDP Tunneling ID, NVGRE/GRE key */
199 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
200 /* Last ether type */
201 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
202 /* Tunneling outer destination IPv4 address */
203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
204 /* Tunneling outer destination IPv6 address */
205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
206 /* 1st word of flex payload */
207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
208 /* 2nd word of flex payload */
209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
210 /* 3rd word of flex payload */
211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
212 /* 4th word of flex payload */
213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
214 /* 5th word of flex payload */
215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
216 /* 6th word of flex payload */
217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
218 /* 7th word of flex payload */
219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
220 /* 8th word of flex payload */
221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
222 /* all 8 words flex payload */
223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
224 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
226 #define I40E_TRANSLATE_INSET 0
227 #define I40E_TRANSLATE_REG 1
229 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
230 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
231 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
232 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
234 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
236 /* PCI offset for querying capability */
237 #define PCI_DEV_CAP_REG 0xA4
238 /* PCI offset for enabling/disabling Extended Tag */
239 #define PCI_DEV_CTRL_REG 0xA8
240 /* Bit mask of Extended Tag capability */
241 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
242 /* Bit shift of Extended Tag enable/disable */
243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
244 /* Bit mask of Extended Tag enable/disable */
245 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int i40e_dev_configure(struct rte_eth_dev *dev);
250 static int i40e_dev_start(struct rte_eth_dev *dev);
251 static void i40e_dev_stop(struct rte_eth_dev *dev);
252 static void i40e_dev_close(struct rte_eth_dev *dev);
253 static int i40e_dev_reset(struct rte_eth_dev *dev);
254 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
255 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
256 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
257 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
258 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
259 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
260 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
261 struct rte_eth_stats *stats);
262 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
263 struct rte_eth_xstat *xstats, unsigned n);
264 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
265 struct rte_eth_xstat_name *xstats_names,
267 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
268 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
272 static int i40e_fw_version_get(struct rte_eth_dev *dev,
273 char *fw_version, size_t fw_size);
274 static void i40e_dev_info_get(struct rte_eth_dev *dev,
275 struct rte_eth_dev_info *dev_info);
276 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
279 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
280 enum rte_vlan_type vlan_type,
282 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
283 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
286 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
287 static int i40e_dev_led_on(struct rte_eth_dev *dev);
288 static int i40e_dev_led_off(struct rte_eth_dev *dev);
289 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
290 struct rte_eth_fc_conf *fc_conf);
291 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
292 struct rte_eth_fc_conf *fc_conf);
293 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
294 struct rte_eth_pfc_conf *pfc_conf);
295 static int i40e_macaddr_add(struct rte_eth_dev *dev,
296 struct ether_addr *mac_addr,
299 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
300 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
301 struct rte_eth_rss_reta_entry64 *reta_conf,
303 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
304 struct rte_eth_rss_reta_entry64 *reta_conf,
307 static int i40e_get_cap(struct i40e_hw *hw);
308 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
309 static int i40e_pf_setup(struct i40e_pf *pf);
310 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
311 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
312 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
313 static int i40e_dcb_setup(struct rte_eth_dev *dev);
314 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
315 bool offset_loaded, uint64_t *offset, uint64_t *stat);
316 static void i40e_stat_update_48(struct i40e_hw *hw,
322 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
323 static void i40e_dev_interrupt_handler(void *param);
324 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
325 uint32_t base, uint32_t num);
326 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
327 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
329 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
331 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
332 static int i40e_veb_release(struct i40e_veb *veb);
333 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
334 struct i40e_vsi *vsi);
335 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
336 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
337 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
338 struct i40e_macvlan_filter *mv_f,
341 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
342 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
343 struct rte_eth_rss_conf *rss_conf);
344 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
345 struct rte_eth_rss_conf *rss_conf);
346 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
347 struct rte_eth_udp_tunnel *udp_tunnel);
348 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
349 struct rte_eth_udp_tunnel *udp_tunnel);
350 static void i40e_filter_input_set_init(struct i40e_pf *pf);
351 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
352 enum rte_filter_op filter_op,
354 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
355 enum rte_filter_type filter_type,
356 enum rte_filter_op filter_op,
358 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
359 struct rte_eth_dcb_info *dcb_info);
360 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
361 static void i40e_configure_registers(struct i40e_hw *hw);
362 static void i40e_hw_init(struct rte_eth_dev *dev);
363 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
364 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
370 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
371 struct rte_eth_mirror_conf *mirror_conf,
372 uint8_t sw_id, uint8_t on);
373 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
375 static int i40e_timesync_enable(struct rte_eth_dev *dev);
376 static int i40e_timesync_disable(struct rte_eth_dev *dev);
377 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
378 struct timespec *timestamp,
380 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
381 struct timespec *timestamp);
382 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
384 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
386 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
387 struct timespec *timestamp);
388 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
389 const struct timespec *timestamp);
391 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
393 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
396 static int i40e_get_regs(struct rte_eth_dev *dev,
397 struct rte_dev_reg_info *regs);
399 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
401 static int i40e_get_eeprom(struct rte_eth_dev *dev,
402 struct rte_dev_eeprom_info *eeprom);
404 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
405 struct ether_addr *mac_addr);
407 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
409 static int i40e_ethertype_filter_convert(
410 const struct rte_eth_ethertype_filter *input,
411 struct i40e_ethertype_filter *filter);
412 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
413 struct i40e_ethertype_filter *filter);
415 static int i40e_tunnel_filter_convert(
416 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
417 struct i40e_tunnel_filter *tunnel_filter);
418 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
419 struct i40e_tunnel_filter *tunnel_filter);
420 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
422 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
423 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
424 static void i40e_filter_restore(struct i40e_pf *pf);
425 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
427 int i40e_logtype_init;
428 int i40e_logtype_driver;
430 static const struct rte_pci_id pci_id_i40e_map[] = {
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
449 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
450 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
451 { .vendor_id = 0, /* sentinel */ },
454 static const struct eth_dev_ops i40e_eth_dev_ops = {
455 .dev_configure = i40e_dev_configure,
456 .dev_start = i40e_dev_start,
457 .dev_stop = i40e_dev_stop,
458 .dev_close = i40e_dev_close,
459 .dev_reset = i40e_dev_reset,
460 .promiscuous_enable = i40e_dev_promiscuous_enable,
461 .promiscuous_disable = i40e_dev_promiscuous_disable,
462 .allmulticast_enable = i40e_dev_allmulticast_enable,
463 .allmulticast_disable = i40e_dev_allmulticast_disable,
464 .dev_set_link_up = i40e_dev_set_link_up,
465 .dev_set_link_down = i40e_dev_set_link_down,
466 .link_update = i40e_dev_link_update,
467 .stats_get = i40e_dev_stats_get,
468 .xstats_get = i40e_dev_xstats_get,
469 .xstats_get_names = i40e_dev_xstats_get_names,
470 .stats_reset = i40e_dev_stats_reset,
471 .xstats_reset = i40e_dev_stats_reset,
472 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
473 .fw_version_get = i40e_fw_version_get,
474 .dev_infos_get = i40e_dev_info_get,
475 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
476 .vlan_filter_set = i40e_vlan_filter_set,
477 .vlan_tpid_set = i40e_vlan_tpid_set,
478 .vlan_offload_set = i40e_vlan_offload_set,
479 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
480 .vlan_pvid_set = i40e_vlan_pvid_set,
481 .rx_queue_start = i40e_dev_rx_queue_start,
482 .rx_queue_stop = i40e_dev_rx_queue_stop,
483 .tx_queue_start = i40e_dev_tx_queue_start,
484 .tx_queue_stop = i40e_dev_tx_queue_stop,
485 .rx_queue_setup = i40e_dev_rx_queue_setup,
486 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
487 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
488 .rx_queue_release = i40e_dev_rx_queue_release,
489 .rx_queue_count = i40e_dev_rx_queue_count,
490 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
491 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
492 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
493 .tx_queue_setup = i40e_dev_tx_queue_setup,
494 .tx_queue_release = i40e_dev_tx_queue_release,
495 .dev_led_on = i40e_dev_led_on,
496 .dev_led_off = i40e_dev_led_off,
497 .flow_ctrl_get = i40e_flow_ctrl_get,
498 .flow_ctrl_set = i40e_flow_ctrl_set,
499 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
500 .mac_addr_add = i40e_macaddr_add,
501 .mac_addr_remove = i40e_macaddr_remove,
502 .reta_update = i40e_dev_rss_reta_update,
503 .reta_query = i40e_dev_rss_reta_query,
504 .rss_hash_update = i40e_dev_rss_hash_update,
505 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
506 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
507 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
508 .filter_ctrl = i40e_dev_filter_ctrl,
509 .rxq_info_get = i40e_rxq_info_get,
510 .txq_info_get = i40e_txq_info_get,
511 .mirror_rule_set = i40e_mirror_rule_set,
512 .mirror_rule_reset = i40e_mirror_rule_reset,
513 .timesync_enable = i40e_timesync_enable,
514 .timesync_disable = i40e_timesync_disable,
515 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
516 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
517 .get_dcb_info = i40e_dev_get_dcb_info,
518 .timesync_adjust_time = i40e_timesync_adjust_time,
519 .timesync_read_time = i40e_timesync_read_time,
520 .timesync_write_time = i40e_timesync_write_time,
521 .get_reg = i40e_get_regs,
522 .get_eeprom_length = i40e_get_eeprom_length,
523 .get_eeprom = i40e_get_eeprom,
524 .mac_addr_set = i40e_set_default_mac_addr,
525 .mtu_set = i40e_dev_mtu_set,
526 .tm_ops_get = i40e_tm_ops_get,
529 /* store statistics names and its offset in stats structure */
530 struct rte_i40e_xstats_name_off {
531 char name[RTE_ETH_XSTATS_NAME_SIZE];
535 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
536 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
537 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
538 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
539 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
540 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
541 rx_unknown_protocol)},
542 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
543 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
544 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
545 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
548 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
549 sizeof(rte_i40e_stats_strings[0]))
551 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
552 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
553 tx_dropped_link_down)},
554 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
555 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
557 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
558 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
560 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
562 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
564 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
565 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
566 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
567 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
568 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
569 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
573 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
577 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
581 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
583 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
585 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
586 mac_short_packet_dropped)},
587 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
589 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
590 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
591 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
593 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
595 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
597 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
599 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
601 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
603 {"rx_flow_director_atr_match_packets",
604 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
605 {"rx_flow_director_sb_match_packets",
606 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
607 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
609 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
611 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
613 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
617 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
618 sizeof(rte_i40e_hw_port_strings[0]))
620 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
621 {"xon_packets", offsetof(struct i40e_hw_port_stats,
623 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
627 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
628 sizeof(rte_i40e_rxq_prio_strings[0]))
630 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
631 {"xon_packets", offsetof(struct i40e_hw_port_stats,
633 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
635 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
636 priority_xon_2_xoff)},
639 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
640 sizeof(rte_i40e_txq_prio_strings[0]))
642 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
643 struct rte_pci_device *pci_dev)
645 return rte_eth_dev_pci_generic_probe(pci_dev,
646 sizeof(struct i40e_adapter), eth_i40e_dev_init);
649 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
651 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
654 static struct rte_pci_driver rte_i40e_pmd = {
655 .id_table = pci_id_i40e_map,
656 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
657 .probe = eth_i40e_pci_probe,
658 .remove = eth_i40e_pci_remove,
662 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
663 struct rte_eth_link *link)
665 struct rte_eth_link *dst = link;
666 struct rte_eth_link *src = &(dev->data->dev_link);
668 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
669 *(uint64_t *)src) == 0)
676 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
677 struct rte_eth_link *link)
679 struct rte_eth_link *dst = &(dev->data->dev_link);
680 struct rte_eth_link *src = link;
682 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
683 *(uint64_t *)src) == 0)
689 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
690 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
691 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
693 #ifndef I40E_GLQF_ORT
694 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
696 #ifndef I40E_GLQF_PIT
697 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
699 #ifndef I40E_GLQF_L3_MAP
700 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
703 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
706 * Initialize registers for flexible payload, which should be set by NVM.
707 * This should be removed from code once it is fixed in NVM.
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
710 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
711 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
712 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
713 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
715 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
716 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
717 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
718 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
719 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
720 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
722 /* Initialize registers for parsing packet type of QinQ */
723 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
724 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
727 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
730 * Add a ethertype filter to drop all flow control frames transmitted
734 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
736 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
737 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
738 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
739 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
742 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
743 I40E_FLOW_CONTROL_ETHERTYPE, flags,
744 pf->main_vsi_seid, 0,
748 "Failed to add filter to drop flow control frames from VSIs.");
752 floating_veb_list_handler(__rte_unused const char *key,
753 const char *floating_veb_value,
757 unsigned int count = 0;
760 bool *vf_floating_veb = opaque;
762 while (isblank(*floating_veb_value))
763 floating_veb_value++;
765 /* Reset floating VEB configuration for VFs */
766 for (idx = 0; idx < I40E_MAX_VF; idx++)
767 vf_floating_veb[idx] = false;
771 while (isblank(*floating_veb_value))
772 floating_veb_value++;
773 if (*floating_veb_value == '\0')
776 idx = strtoul(floating_veb_value, &end, 10);
777 if (errno || end == NULL)
779 while (isblank(*end))
783 } else if ((*end == ';') || (*end == '\0')) {
785 if (min == I40E_MAX_VF)
787 if (max >= I40E_MAX_VF)
788 max = I40E_MAX_VF - 1;
789 for (idx = min; idx <= max; idx++) {
790 vf_floating_veb[idx] = true;
797 floating_veb_value = end + 1;
798 } while (*end != '\0');
807 config_vf_floating_veb(struct rte_devargs *devargs,
808 uint16_t floating_veb,
809 bool *vf_floating_veb)
811 struct rte_kvargs *kvlist;
813 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
817 /* All the VFs attach to the floating VEB by default
818 * when the floating VEB is enabled.
820 for (i = 0; i < I40E_MAX_VF; i++)
821 vf_floating_veb[i] = true;
826 kvlist = rte_kvargs_parse(devargs->args, NULL);
830 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
831 rte_kvargs_free(kvlist);
834 /* When the floating_veb_list parameter exists, all the VFs
835 * will attach to the legacy VEB firstly, then configure VFs
836 * to the floating VEB according to the floating_veb_list.
838 if (rte_kvargs_process(kvlist, floating_veb_list,
839 floating_veb_list_handler,
840 vf_floating_veb) < 0) {
841 rte_kvargs_free(kvlist);
844 rte_kvargs_free(kvlist);
848 i40e_check_floating_handler(__rte_unused const char *key,
850 __rte_unused void *opaque)
852 if (strcmp(value, "1"))
859 is_floating_veb_supported(struct rte_devargs *devargs)
861 struct rte_kvargs *kvlist;
862 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
867 kvlist = rte_kvargs_parse(devargs->args, NULL);
871 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
872 rte_kvargs_free(kvlist);
875 /* Floating VEB is enabled when there's key-value:
876 * enable_floating_veb=1
878 if (rte_kvargs_process(kvlist, floating_veb_key,
879 i40e_check_floating_handler, NULL) < 0) {
880 rte_kvargs_free(kvlist);
883 rte_kvargs_free(kvlist);
889 config_floating_veb(struct rte_eth_dev *dev)
891 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
892 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
893 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
895 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
897 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
899 is_floating_veb_supported(pci_dev->device.devargs);
900 config_vf_floating_veb(pci_dev->device.devargs,
902 pf->floating_veb_list);
904 pf->floating_veb = false;
908 #define I40E_L2_TAGS_S_TAG_SHIFT 1
909 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
912 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
914 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
915 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
916 char ethertype_hash_name[RTE_HASH_NAMESIZE];
919 struct rte_hash_parameters ethertype_hash_params = {
920 .name = ethertype_hash_name,
921 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
922 .key_len = sizeof(struct i40e_ethertype_filter_input),
923 .hash_func = rte_hash_crc,
924 .hash_func_init_val = 0,
925 .socket_id = rte_socket_id(),
928 /* Initialize ethertype filter rule list and hash */
929 TAILQ_INIT(ðertype_rule->ethertype_list);
930 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
931 "ethertype_%s", dev->device->name);
932 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
933 if (!ethertype_rule->hash_table) {
934 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
937 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
938 sizeof(struct i40e_ethertype_filter *) *
939 I40E_MAX_ETHERTYPE_FILTER_NUM,
941 if (!ethertype_rule->hash_map) {
943 "Failed to allocate memory for ethertype hash map!");
945 goto err_ethertype_hash_map_alloc;
950 err_ethertype_hash_map_alloc:
951 rte_hash_free(ethertype_rule->hash_table);
957 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
959 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
960 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
961 char tunnel_hash_name[RTE_HASH_NAMESIZE];
964 struct rte_hash_parameters tunnel_hash_params = {
965 .name = tunnel_hash_name,
966 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
967 .key_len = sizeof(struct i40e_tunnel_filter_input),
968 .hash_func = rte_hash_crc,
969 .hash_func_init_val = 0,
970 .socket_id = rte_socket_id(),
973 /* Initialize tunnel filter rule list and hash */
974 TAILQ_INIT(&tunnel_rule->tunnel_list);
975 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
976 "tunnel_%s", dev->device->name);
977 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
978 if (!tunnel_rule->hash_table) {
979 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
982 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
983 sizeof(struct i40e_tunnel_filter *) *
984 I40E_MAX_TUNNEL_FILTER_NUM,
986 if (!tunnel_rule->hash_map) {
988 "Failed to allocate memory for tunnel hash map!");
990 goto err_tunnel_hash_map_alloc;
995 err_tunnel_hash_map_alloc:
996 rte_hash_free(tunnel_rule->hash_table);
1002 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1004 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1005 struct i40e_fdir_info *fdir_info = &pf->fdir;
1006 char fdir_hash_name[RTE_HASH_NAMESIZE];
1009 struct rte_hash_parameters fdir_hash_params = {
1010 .name = fdir_hash_name,
1011 .entries = I40E_MAX_FDIR_FILTER_NUM,
1012 .key_len = sizeof(struct rte_eth_fdir_input),
1013 .hash_func = rte_hash_crc,
1014 .hash_func_init_val = 0,
1015 .socket_id = rte_socket_id(),
1018 /* Initialize flow director filter rule list and hash */
1019 TAILQ_INIT(&fdir_info->fdir_list);
1020 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1021 "fdir_%s", dev->device->name);
1022 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1023 if (!fdir_info->hash_table) {
1024 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1027 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1028 sizeof(struct i40e_fdir_filter *) *
1029 I40E_MAX_FDIR_FILTER_NUM,
1031 if (!fdir_info->hash_map) {
1033 "Failed to allocate memory for fdir hash map!");
1035 goto err_fdir_hash_map_alloc;
1039 err_fdir_hash_map_alloc:
1040 rte_hash_free(fdir_info->hash_table);
1046 eth_i40e_dev_init(struct rte_eth_dev *dev)
1048 struct rte_pci_device *pci_dev;
1049 struct rte_intr_handle *intr_handle;
1050 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1051 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052 struct i40e_vsi *vsi;
1055 uint8_t aq_fail = 0;
1057 PMD_INIT_FUNC_TRACE();
1059 dev->dev_ops = &i40e_eth_dev_ops;
1060 dev->rx_pkt_burst = i40e_recv_pkts;
1061 dev->tx_pkt_burst = i40e_xmit_pkts;
1062 dev->tx_pkt_prepare = i40e_prep_pkts;
1064 /* for secondary processes, we don't initialise any further as primary
1065 * has already done this work. Only check we don't need a different
1067 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1068 i40e_set_rx_function(dev);
1069 i40e_set_tx_function(dev);
1072 i40e_set_default_ptype_table(dev);
1073 i40e_set_default_pctype_table(dev);
1074 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1075 intr_handle = &pci_dev->intr_handle;
1077 rte_eth_copy_pci_info(dev, pci_dev);
1078 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1080 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1081 pf->adapter->eth_dev = dev;
1082 pf->dev_data = dev->data;
1084 hw->back = I40E_PF_TO_ADAPTER(pf);
1085 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1088 "Hardware is not available, as address is NULL");
1092 hw->vendor_id = pci_dev->id.vendor_id;
1093 hw->device_id = pci_dev->id.device_id;
1094 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1095 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1096 hw->bus.device = pci_dev->addr.devid;
1097 hw->bus.func = pci_dev->addr.function;
1098 hw->adapter_stopped = 0;
1100 /* Make sure all is clean before doing PF reset */
1103 /* Initialize the hardware */
1106 /* Reset here to make sure all is clean for each PF */
1107 ret = i40e_pf_reset(hw);
1109 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1113 /* Initialize the shared code (base driver) */
1114 ret = i40e_init_shared_code(hw);
1116 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1121 * To work around the NVM issue, initialize registers
1122 * for flexible payload and packet type of QinQ by
1123 * software. It should be removed once issues are fixed
1126 i40e_GLQF_reg_init(hw);
1128 /* Initialize the input set for filters (hash and fd) to default value */
1129 i40e_filter_input_set_init(pf);
1131 /* Initialize the parameters for adminq */
1132 i40e_init_adminq_parameter(hw);
1133 ret = i40e_init_adminq(hw);
1134 if (ret != I40E_SUCCESS) {
1135 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1138 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1139 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1140 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1141 ((hw->nvm.version >> 12) & 0xf),
1142 ((hw->nvm.version >> 4) & 0xff),
1143 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1145 /* initialise the L3_MAP register */
1146 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1149 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1151 /* Need the special FW version to support floating VEB */
1152 config_floating_veb(dev);
1153 /* Clear PXE mode */
1154 i40e_clear_pxe_mode(hw);
1155 i40e_dev_sync_phy_type(hw);
1158 * On X710, performance number is far from the expectation on recent
1159 * firmware versions. The fix for this issue may not be integrated in
1160 * the following firmware version. So the workaround in software driver
1161 * is needed. It needs to modify the initial values of 3 internal only
1162 * registers. Note that the workaround can be removed when it is fixed
1163 * in firmware in the future.
1165 i40e_configure_registers(hw);
1167 /* Get hw capabilities */
1168 ret = i40e_get_cap(hw);
1169 if (ret != I40E_SUCCESS) {
1170 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1171 goto err_get_capabilities;
1174 /* Initialize parameters for PF */
1175 ret = i40e_pf_parameter_init(dev);
1177 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1178 goto err_parameter_init;
1181 /* Initialize the queue management */
1182 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1184 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1185 goto err_qp_pool_init;
1187 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1188 hw->func_caps.num_msix_vectors - 1);
1190 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1191 goto err_msix_pool_init;
1194 /* Initialize lan hmc */
1195 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1196 hw->func_caps.num_rx_qp, 0, 0);
1197 if (ret != I40E_SUCCESS) {
1198 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1199 goto err_init_lan_hmc;
1202 /* Configure lan hmc */
1203 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1204 if (ret != I40E_SUCCESS) {
1205 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1206 goto err_configure_lan_hmc;
1209 /* Get and check the mac address */
1210 i40e_get_mac_addr(hw, hw->mac.addr);
1211 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1212 PMD_INIT_LOG(ERR, "mac address is not valid");
1214 goto err_get_mac_addr;
1216 /* Copy the permanent MAC address */
1217 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1218 (struct ether_addr *) hw->mac.perm_addr);
1220 /* Disable flow control */
1221 hw->fc.requested_mode = I40E_FC_NONE;
1222 i40e_set_fc(hw, &aq_fail, TRUE);
1224 /* Set the global registers with default ether type value */
1225 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1226 if (ret != I40E_SUCCESS) {
1228 "Failed to set the default outer VLAN ether type");
1229 goto err_setup_pf_switch;
1232 /* PF setup, which includes VSI setup */
1233 ret = i40e_pf_setup(pf);
1235 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1236 goto err_setup_pf_switch;
1239 /* reset all stats of the device, including pf and main vsi */
1240 i40e_dev_stats_reset(dev);
1244 /* Disable double vlan by default */
1245 i40e_vsi_config_double_vlan(vsi, FALSE);
1247 /* Disable S-TAG identification when floating_veb is disabled */
1248 if (!pf->floating_veb) {
1249 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1250 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1251 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1252 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1256 if (!vsi->max_macaddrs)
1257 len = ETHER_ADDR_LEN;
1259 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1261 /* Should be after VSI initialized */
1262 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1263 if (!dev->data->mac_addrs) {
1265 "Failed to allocated memory for storing mac address");
1268 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1269 &dev->data->mac_addrs[0]);
1271 /* Init dcb to sw mode by default */
1272 ret = i40e_dcb_init_configure(dev, TRUE);
1273 if (ret != I40E_SUCCESS) {
1274 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1275 pf->flags &= ~I40E_FLAG_DCB;
1277 /* Update HW struct after DCB configuration */
1280 /* initialize pf host driver to setup SRIOV resource if applicable */
1281 i40e_pf_host_init(dev);
1283 /* register callback func to eal lib */
1284 rte_intr_callback_register(intr_handle,
1285 i40e_dev_interrupt_handler, dev);
1287 /* configure and enable device interrupt */
1288 i40e_pf_config_irq0(hw, TRUE);
1289 i40e_pf_enable_irq0(hw);
1291 /* enable uio intr after callback register */
1292 rte_intr_enable(intr_handle);
1294 * Add an ethertype filter to drop all flow control frames transmitted
1295 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1298 i40e_add_tx_flow_control_drop_filter(pf);
1300 /* Set the max frame size to 0x2600 by default,
1301 * in case other drivers changed the default value.
1303 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1305 /* initialize mirror rule list */
1306 TAILQ_INIT(&pf->mirror_list);
1308 /* initialize Traffic Manager configuration */
1309 i40e_tm_conf_init(dev);
1311 ret = i40e_init_ethtype_filter_list(dev);
1313 goto err_init_ethtype_filter_list;
1314 ret = i40e_init_tunnel_filter_list(dev);
1316 goto err_init_tunnel_filter_list;
1317 ret = i40e_init_fdir_filter_list(dev);
1319 goto err_init_fdir_filter_list;
1323 err_init_fdir_filter_list:
1324 rte_free(pf->tunnel.hash_table);
1325 rte_free(pf->tunnel.hash_map);
1326 err_init_tunnel_filter_list:
1327 rte_free(pf->ethertype.hash_table);
1328 rte_free(pf->ethertype.hash_map);
1329 err_init_ethtype_filter_list:
1330 rte_free(dev->data->mac_addrs);
1332 i40e_vsi_release(pf->main_vsi);
1333 err_setup_pf_switch:
1335 err_configure_lan_hmc:
1336 (void)i40e_shutdown_lan_hmc(hw);
1338 i40e_res_pool_destroy(&pf->msix_pool);
1340 i40e_res_pool_destroy(&pf->qp_pool);
1343 err_get_capabilities:
1344 (void)i40e_shutdown_adminq(hw);
1350 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1352 struct i40e_ethertype_filter *p_ethertype;
1353 struct i40e_ethertype_rule *ethertype_rule;
1355 ethertype_rule = &pf->ethertype;
1356 /* Remove all ethertype filter rules and hash */
1357 if (ethertype_rule->hash_map)
1358 rte_free(ethertype_rule->hash_map);
1359 if (ethertype_rule->hash_table)
1360 rte_hash_free(ethertype_rule->hash_table);
1362 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1363 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1364 p_ethertype, rules);
1365 rte_free(p_ethertype);
1370 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1372 struct i40e_tunnel_filter *p_tunnel;
1373 struct i40e_tunnel_rule *tunnel_rule;
1375 tunnel_rule = &pf->tunnel;
1376 /* Remove all tunnel director rules and hash */
1377 if (tunnel_rule->hash_map)
1378 rte_free(tunnel_rule->hash_map);
1379 if (tunnel_rule->hash_table)
1380 rte_hash_free(tunnel_rule->hash_table);
1382 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1383 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1389 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1391 struct i40e_fdir_filter *p_fdir;
1392 struct i40e_fdir_info *fdir_info;
1394 fdir_info = &pf->fdir;
1395 /* Remove all flow director rules and hash */
1396 if (fdir_info->hash_map)
1397 rte_free(fdir_info->hash_map);
1398 if (fdir_info->hash_table)
1399 rte_hash_free(fdir_info->hash_table);
1401 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1402 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1408 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1411 struct rte_pci_device *pci_dev;
1412 struct rte_intr_handle *intr_handle;
1414 struct i40e_filter_control_settings settings;
1415 struct rte_flow *p_flow;
1417 uint8_t aq_fail = 0;
1419 PMD_INIT_FUNC_TRACE();
1421 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1424 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1425 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1427 intr_handle = &pci_dev->intr_handle;
1429 if (hw->adapter_stopped == 0)
1430 i40e_dev_close(dev);
1432 dev->dev_ops = NULL;
1433 dev->rx_pkt_burst = NULL;
1434 dev->tx_pkt_burst = NULL;
1436 /* Clear PXE mode */
1437 i40e_clear_pxe_mode(hw);
1439 /* Unconfigure filter control */
1440 memset(&settings, 0, sizeof(settings));
1441 ret = i40e_set_filter_control(hw, &settings);
1443 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1446 /* Disable flow control */
1447 hw->fc.requested_mode = I40E_FC_NONE;
1448 i40e_set_fc(hw, &aq_fail, TRUE);
1450 /* uninitialize pf host driver */
1451 i40e_pf_host_uninit(dev);
1453 rte_free(dev->data->mac_addrs);
1454 dev->data->mac_addrs = NULL;
1456 /* disable uio intr before callback unregister */
1457 rte_intr_disable(intr_handle);
1459 /* register callback func to eal lib */
1460 rte_intr_callback_unregister(intr_handle,
1461 i40e_dev_interrupt_handler, dev);
1463 i40e_rm_ethtype_filter_list(pf);
1464 i40e_rm_tunnel_filter_list(pf);
1465 i40e_rm_fdir_filter_list(pf);
1467 /* Remove all flows */
1468 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1469 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1473 /* Remove all Traffic Manager configuration */
1474 i40e_tm_conf_uninit(dev);
1480 i40e_dev_configure(struct rte_eth_dev *dev)
1482 struct i40e_adapter *ad =
1483 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1484 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1485 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1486 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1489 ret = i40e_dev_sync_phy_type(hw);
1493 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1494 * bulk allocation or vector Rx preconditions we will reset it.
1496 ad->rx_bulk_alloc_allowed = true;
1497 ad->rx_vec_allowed = true;
1498 ad->tx_simple_allowed = true;
1499 ad->tx_vec_allowed = true;
1501 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1502 ret = i40e_fdir_setup(pf);
1503 if (ret != I40E_SUCCESS) {
1504 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1507 ret = i40e_fdir_configure(dev);
1509 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1513 i40e_fdir_teardown(pf);
1515 ret = i40e_dev_init_vlan(dev);
1520 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1521 * RSS setting have different requirements.
1522 * General PMD driver call sequence are NIC init, configure,
1523 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1524 * will try to lookup the VSI that specific queue belongs to if VMDQ
1525 * applicable. So, VMDQ setting has to be done before
1526 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1527 * For RSS setting, it will try to calculate actual configured RX queue
1528 * number, which will be available after rx_queue_setup(). dev_start()
1529 * function is good to place RSS setup.
1531 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1532 ret = i40e_vmdq_setup(dev);
1537 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1538 ret = i40e_dcb_setup(dev);
1540 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1545 TAILQ_INIT(&pf->flow_list);
1550 /* need to release vmdq resource if exists */
1551 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1552 i40e_vsi_release(pf->vmdq[i].vsi);
1553 pf->vmdq[i].vsi = NULL;
1558 /* need to release fdir resource if exists */
1559 i40e_fdir_teardown(pf);
1564 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1566 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1567 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1568 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1569 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1570 uint16_t msix_vect = vsi->msix_intr;
1573 for (i = 0; i < vsi->nb_qps; i++) {
1574 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1575 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1579 if (vsi->type != I40E_VSI_SRIOV) {
1580 if (!rte_intr_allow_others(intr_handle)) {
1581 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1582 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1584 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1587 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1588 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1590 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1595 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1596 vsi->user_param + (msix_vect - 1);
1598 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1599 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1601 I40E_WRITE_FLUSH(hw);
1605 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1606 int base_queue, int nb_queue,
1611 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1613 /* Bind all RX queues to allocated MSIX interrupt */
1614 for (i = 0; i < nb_queue; i++) {
1615 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1616 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1617 ((base_queue + i + 1) <<
1618 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1619 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1620 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1622 if (i == nb_queue - 1)
1623 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1624 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1627 /* Write first RX queue to Link list register as the head element */
1628 if (vsi->type != I40E_VSI_SRIOV) {
1630 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1632 if (msix_vect == I40E_MISC_VEC_ID) {
1633 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1635 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1637 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1639 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1642 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1644 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1646 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1648 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1655 if (msix_vect == I40E_MISC_VEC_ID) {
1657 I40E_VPINT_LNKLST0(vsi->user_param),
1659 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1661 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1663 /* num_msix_vectors_vf needs to minus irq0 */
1664 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1665 vsi->user_param + (msix_vect - 1);
1667 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1669 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1671 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1675 I40E_WRITE_FLUSH(hw);
1679 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1681 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1682 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1683 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1684 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1685 uint16_t msix_vect = vsi->msix_intr;
1686 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1687 uint16_t queue_idx = 0;
1692 for (i = 0; i < vsi->nb_qps; i++) {
1693 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1694 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1697 /* INTENA flag is not auto-cleared for interrupt */
1698 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1699 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1700 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1701 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1702 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1704 /* VF bind interrupt */
1705 if (vsi->type == I40E_VSI_SRIOV) {
1706 __vsi_queues_bind_intr(vsi, msix_vect,
1707 vsi->base_queue, vsi->nb_qps,
1712 /* PF & VMDq bind interrupt */
1713 if (rte_intr_dp_is_en(intr_handle)) {
1714 if (vsi->type == I40E_VSI_MAIN) {
1717 } else if (vsi->type == I40E_VSI_VMDQ2) {
1718 struct i40e_vsi *main_vsi =
1719 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1720 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1725 for (i = 0; i < vsi->nb_used_qps; i++) {
1727 if (!rte_intr_allow_others(intr_handle))
1728 /* allow to share MISC_VEC_ID */
1729 msix_vect = I40E_MISC_VEC_ID;
1731 /* no enough msix_vect, map all to one */
1732 __vsi_queues_bind_intr(vsi, msix_vect,
1733 vsi->base_queue + i,
1734 vsi->nb_used_qps - i,
1736 for (; !!record && i < vsi->nb_used_qps; i++)
1737 intr_handle->intr_vec[queue_idx + i] =
1741 /* 1:1 queue/msix_vect mapping */
1742 __vsi_queues_bind_intr(vsi, msix_vect,
1743 vsi->base_queue + i, 1,
1746 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1754 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1756 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1757 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1758 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1759 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1760 uint16_t interval = i40e_calc_itr_interval(\
1761 RTE_LIBRTE_I40E_ITR_INTERVAL);
1762 uint16_t msix_intr, i;
1764 if (rte_intr_allow_others(intr_handle))
1765 for (i = 0; i < vsi->nb_msix; i++) {
1766 msix_intr = vsi->msix_intr + i;
1767 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1768 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1769 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1770 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1772 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1775 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1776 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1777 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1778 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1780 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1782 I40E_WRITE_FLUSH(hw);
1786 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1788 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1789 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1790 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1791 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1792 uint16_t msix_intr, i;
1794 if (rte_intr_allow_others(intr_handle))
1795 for (i = 0; i < vsi->nb_msix; i++) {
1796 msix_intr = vsi->msix_intr + i;
1797 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1801 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1803 I40E_WRITE_FLUSH(hw);
1806 static inline uint8_t
1807 i40e_parse_link_speeds(uint16_t link_speeds)
1809 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1811 if (link_speeds & ETH_LINK_SPEED_40G)
1812 link_speed |= I40E_LINK_SPEED_40GB;
1813 if (link_speeds & ETH_LINK_SPEED_25G)
1814 link_speed |= I40E_LINK_SPEED_25GB;
1815 if (link_speeds & ETH_LINK_SPEED_20G)
1816 link_speed |= I40E_LINK_SPEED_20GB;
1817 if (link_speeds & ETH_LINK_SPEED_10G)
1818 link_speed |= I40E_LINK_SPEED_10GB;
1819 if (link_speeds & ETH_LINK_SPEED_1G)
1820 link_speed |= I40E_LINK_SPEED_1GB;
1821 if (link_speeds & ETH_LINK_SPEED_100M)
1822 link_speed |= I40E_LINK_SPEED_100MB;
1828 i40e_phy_conf_link(struct i40e_hw *hw,
1830 uint8_t force_speed,
1833 enum i40e_status_code status;
1834 struct i40e_aq_get_phy_abilities_resp phy_ab;
1835 struct i40e_aq_set_phy_config phy_conf;
1836 enum i40e_aq_phy_type cnt;
1837 uint32_t phy_type_mask = 0;
1839 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1840 I40E_AQ_PHY_FLAG_PAUSE_RX |
1841 I40E_AQ_PHY_FLAG_PAUSE_RX |
1842 I40E_AQ_PHY_FLAG_LOW_POWER;
1843 const uint8_t advt = I40E_LINK_SPEED_40GB |
1844 I40E_LINK_SPEED_25GB |
1845 I40E_LINK_SPEED_10GB |
1846 I40E_LINK_SPEED_1GB |
1847 I40E_LINK_SPEED_100MB;
1851 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1856 /* If link already up, no need to set up again */
1857 if (is_up && phy_ab.phy_type != 0)
1858 return I40E_SUCCESS;
1860 memset(&phy_conf, 0, sizeof(phy_conf));
1862 /* bits 0-2 use the values from get_phy_abilities_resp */
1864 abilities |= phy_ab.abilities & mask;
1866 /* update ablities and speed */
1867 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1868 phy_conf.link_speed = advt;
1870 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1872 phy_conf.abilities = abilities;
1876 /* To enable link, phy_type mask needs to include each type */
1877 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1878 phy_type_mask |= 1 << cnt;
1880 /* use get_phy_abilities_resp value for the rest */
1881 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1882 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1883 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1884 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1885 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1886 phy_conf.eee_capability = phy_ab.eee_capability;
1887 phy_conf.eeer = phy_ab.eeer_val;
1888 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1890 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1891 phy_ab.abilities, phy_ab.link_speed);
1892 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1893 phy_conf.abilities, phy_conf.link_speed);
1895 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1899 return I40E_SUCCESS;
1903 i40e_apply_link_speed(struct rte_eth_dev *dev)
1906 uint8_t abilities = 0;
1907 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1908 struct rte_eth_conf *conf = &dev->data->dev_conf;
1910 speed = i40e_parse_link_speeds(conf->link_speeds);
1911 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1912 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1913 abilities |= I40E_AQ_PHY_AN_ENABLED;
1914 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1916 return i40e_phy_conf_link(hw, abilities, speed, true);
1920 i40e_dev_start(struct rte_eth_dev *dev)
1922 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1923 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924 struct i40e_vsi *main_vsi = pf->main_vsi;
1926 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1927 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1928 uint32_t intr_vector = 0;
1929 struct i40e_vsi *vsi;
1931 hw->adapter_stopped = 0;
1933 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1934 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1935 dev->data->port_id);
1939 rte_intr_disable(intr_handle);
1941 if ((rte_intr_cap_multiple(intr_handle) ||
1942 !RTE_ETH_DEV_SRIOV(dev).active) &&
1943 dev->data->dev_conf.intr_conf.rxq != 0) {
1944 intr_vector = dev->data->nb_rx_queues;
1945 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1950 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1951 intr_handle->intr_vec =
1952 rte_zmalloc("intr_vec",
1953 dev->data->nb_rx_queues * sizeof(int),
1955 if (!intr_handle->intr_vec) {
1957 "Failed to allocate %d rx_queues intr_vec",
1958 dev->data->nb_rx_queues);
1963 /* Initialize VSI */
1964 ret = i40e_dev_rxtx_init(pf);
1965 if (ret != I40E_SUCCESS) {
1966 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1970 /* Map queues with MSIX interrupt */
1971 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1972 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1973 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1974 i40e_vsi_enable_queues_intr(main_vsi);
1976 /* Map VMDQ VSI queues with MSIX interrupt */
1977 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1978 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1979 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1980 I40E_ITR_INDEX_DEFAULT);
1981 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1984 /* enable FDIR MSIX interrupt */
1985 if (pf->fdir.fdir_vsi) {
1986 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1987 I40E_ITR_INDEX_NONE);
1988 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1991 /* Enable all queues which have been configured */
1992 ret = i40e_dev_switch_queues(pf, TRUE);
1993 if (ret != I40E_SUCCESS) {
1994 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1998 /* Enable receiving broadcast packets */
1999 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2000 if (ret != I40E_SUCCESS)
2001 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2003 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2004 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2006 if (ret != I40E_SUCCESS)
2007 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2010 /* Enable the VLAN promiscuous mode. */
2012 for (i = 0; i < pf->vf_num; i++) {
2013 vsi = pf->vfs[i].vsi;
2014 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2019 /* Apply link configure */
2020 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2021 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2022 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2023 ETH_LINK_SPEED_40G)) {
2024 PMD_DRV_LOG(ERR, "Invalid link setting");
2027 ret = i40e_apply_link_speed(dev);
2028 if (I40E_SUCCESS != ret) {
2029 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2033 if (!rte_intr_allow_others(intr_handle)) {
2034 rte_intr_callback_unregister(intr_handle,
2035 i40e_dev_interrupt_handler,
2037 /* configure and enable device interrupt */
2038 i40e_pf_config_irq0(hw, FALSE);
2039 i40e_pf_enable_irq0(hw);
2041 if (dev->data->dev_conf.intr_conf.lsc != 0)
2043 "lsc won't enable because of no intr multiplex");
2045 ret = i40e_aq_set_phy_int_mask(hw,
2046 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2047 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2048 I40E_AQ_EVENT_MEDIA_NA), NULL);
2049 if (ret != I40E_SUCCESS)
2050 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2052 /* Call get_link_info aq commond to enable/disable LSE */
2053 i40e_dev_link_update(dev, 0);
2056 /* enable uio intr after callback register */
2057 rte_intr_enable(intr_handle);
2059 i40e_filter_restore(pf);
2061 if (pf->tm_conf.root && !pf->tm_conf.committed)
2062 PMD_DRV_LOG(WARNING,
2063 "please call hierarchy_commit() "
2064 "before starting the port");
2066 return I40E_SUCCESS;
2069 i40e_dev_switch_queues(pf, FALSE);
2070 i40e_dev_clear_queues(dev);
2076 i40e_dev_stop(struct rte_eth_dev *dev)
2078 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2079 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080 struct i40e_vsi *main_vsi = pf->main_vsi;
2081 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2082 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2085 if (hw->adapter_stopped == 1)
2087 /* Disable all queues */
2088 i40e_dev_switch_queues(pf, FALSE);
2090 /* un-map queues with interrupt registers */
2091 i40e_vsi_disable_queues_intr(main_vsi);
2092 i40e_vsi_queues_unbind_intr(main_vsi);
2094 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2095 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2096 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2099 if (pf->fdir.fdir_vsi) {
2100 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2101 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2103 /* Clear all queues and release memory */
2104 i40e_dev_clear_queues(dev);
2107 i40e_dev_set_link_down(dev);
2109 if (!rte_intr_allow_others(intr_handle))
2110 /* resume to the default handler */
2111 rte_intr_callback_register(intr_handle,
2112 i40e_dev_interrupt_handler,
2115 /* Clean datapath event and queue/vec mapping */
2116 rte_intr_efd_disable(intr_handle);
2117 if (intr_handle->intr_vec) {
2118 rte_free(intr_handle->intr_vec);
2119 intr_handle->intr_vec = NULL;
2122 /* reset hierarchy commit */
2123 pf->tm_conf.committed = false;
2125 hw->adapter_stopped = 1;
2129 i40e_dev_close(struct rte_eth_dev *dev)
2131 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2132 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2133 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2134 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2135 struct i40e_mirror_rule *p_mirror;
2140 PMD_INIT_FUNC_TRACE();
2144 /* Remove all mirror rules */
2145 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2146 ret = i40e_aq_del_mirror_rule(hw,
2147 pf->main_vsi->veb->seid,
2148 p_mirror->rule_type,
2150 p_mirror->num_entries,
2153 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2154 "status = %d, aq_err = %d.", ret,
2155 hw->aq.asq_last_status);
2157 /* remove mirror software resource anyway */
2158 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2160 pf->nb_mirror_rule--;
2163 i40e_dev_free_queues(dev);
2165 /* Disable interrupt */
2166 i40e_pf_disable_irq0(hw);
2167 rte_intr_disable(intr_handle);
2169 /* shutdown and destroy the HMC */
2170 i40e_shutdown_lan_hmc(hw);
2172 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2173 i40e_vsi_release(pf->vmdq[i].vsi);
2174 pf->vmdq[i].vsi = NULL;
2179 /* release all the existing VSIs and VEBs */
2180 i40e_fdir_teardown(pf);
2181 i40e_vsi_release(pf->main_vsi);
2183 /* shutdown the adminq */
2184 i40e_aq_queue_shutdown(hw, true);
2185 i40e_shutdown_adminq(hw);
2187 i40e_res_pool_destroy(&pf->qp_pool);
2188 i40e_res_pool_destroy(&pf->msix_pool);
2190 /* force a PF reset to clean anything leftover */
2191 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2192 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2193 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2194 I40E_WRITE_FLUSH(hw);
2198 * Reset PF device only to re-initialize resources in PMD layer
2201 i40e_dev_reset(struct rte_eth_dev *dev)
2205 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2206 * its VF to make them align with it. The detailed notification
2207 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2208 * To avoid unexpected behavior in VF, currently reset of PF with
2209 * SR-IOV activation is not supported. It might be supported later.
2211 if (dev->data->sriov.active)
2214 ret = eth_i40e_dev_uninit(dev);
2218 ret = eth_i40e_dev_init(dev);
2224 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2226 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2227 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2228 struct i40e_vsi *vsi = pf->main_vsi;
2231 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2233 if (status != I40E_SUCCESS)
2234 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2236 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2238 if (status != I40E_SUCCESS)
2239 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2244 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2246 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2247 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248 struct i40e_vsi *vsi = pf->main_vsi;
2251 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2253 if (status != I40E_SUCCESS)
2254 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2256 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2258 if (status != I40E_SUCCESS)
2259 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2263 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2265 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2266 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2267 struct i40e_vsi *vsi = pf->main_vsi;
2270 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2271 if (ret != I40E_SUCCESS)
2272 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2276 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2278 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2279 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2280 struct i40e_vsi *vsi = pf->main_vsi;
2283 if (dev->data->promiscuous == 1)
2284 return; /* must remain in all_multicast mode */
2286 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2287 vsi->seid, FALSE, NULL);
2288 if (ret != I40E_SUCCESS)
2289 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2293 * Set device link up.
2296 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2298 /* re-apply link speed setting */
2299 return i40e_apply_link_speed(dev);
2303 * Set device link down.
2306 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2308 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2309 uint8_t abilities = 0;
2310 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2312 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2313 return i40e_phy_conf_link(hw, abilities, speed, false);
2317 i40e_dev_link_update(struct rte_eth_dev *dev,
2318 int wait_to_complete)
2320 #define CHECK_INTERVAL 100 /* 100ms */
2321 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2322 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2323 struct i40e_link_status link_status;
2324 struct rte_eth_link link, old;
2326 unsigned rep_cnt = MAX_REPEAT_TIME;
2327 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2329 memset(&link, 0, sizeof(link));
2330 memset(&old, 0, sizeof(old));
2331 memset(&link_status, 0, sizeof(link_status));
2332 rte_i40e_dev_atomic_read_link_status(dev, &old);
2335 /* Get link status information from hardware */
2336 status = i40e_aq_get_link_info(hw, enable_lse,
2337 &link_status, NULL);
2338 if (status != I40E_SUCCESS) {
2339 link.link_speed = ETH_SPEED_NUM_100M;
2340 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2341 PMD_DRV_LOG(ERR, "Failed to get link info");
2345 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2346 if (!wait_to_complete || link.link_status)
2349 rte_delay_ms(CHECK_INTERVAL);
2350 } while (--rep_cnt);
2352 if (!link.link_status)
2355 /* i40e uses full duplex only */
2356 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2358 /* Parse the link status */
2359 switch (link_status.link_speed) {
2360 case I40E_LINK_SPEED_100MB:
2361 link.link_speed = ETH_SPEED_NUM_100M;
2363 case I40E_LINK_SPEED_1GB:
2364 link.link_speed = ETH_SPEED_NUM_1G;
2366 case I40E_LINK_SPEED_10GB:
2367 link.link_speed = ETH_SPEED_NUM_10G;
2369 case I40E_LINK_SPEED_20GB:
2370 link.link_speed = ETH_SPEED_NUM_20G;
2372 case I40E_LINK_SPEED_25GB:
2373 link.link_speed = ETH_SPEED_NUM_25G;
2375 case I40E_LINK_SPEED_40GB:
2376 link.link_speed = ETH_SPEED_NUM_40G;
2379 link.link_speed = ETH_SPEED_NUM_100M;
2383 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2384 ETH_LINK_SPEED_FIXED);
2387 rte_i40e_dev_atomic_write_link_status(dev, &link);
2388 if (link.link_status == old.link_status)
2391 i40e_notify_all_vfs_link_status(dev);
2396 /* Get all the statistics of a VSI */
2398 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2400 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2401 struct i40e_eth_stats *nes = &vsi->eth_stats;
2402 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2403 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2405 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2406 vsi->offset_loaded, &oes->rx_bytes,
2408 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2409 vsi->offset_loaded, &oes->rx_unicast,
2411 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2412 vsi->offset_loaded, &oes->rx_multicast,
2413 &nes->rx_multicast);
2414 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2415 vsi->offset_loaded, &oes->rx_broadcast,
2416 &nes->rx_broadcast);
2417 /* exclude CRC bytes */
2418 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2419 nes->rx_broadcast) * ETHER_CRC_LEN;
2421 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2422 &oes->rx_discards, &nes->rx_discards);
2423 /* GLV_REPC not supported */
2424 /* GLV_RMPC not supported */
2425 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2426 &oes->rx_unknown_protocol,
2427 &nes->rx_unknown_protocol);
2428 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2429 vsi->offset_loaded, &oes->tx_bytes,
2431 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2432 vsi->offset_loaded, &oes->tx_unicast,
2434 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2435 vsi->offset_loaded, &oes->tx_multicast,
2436 &nes->tx_multicast);
2437 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2438 vsi->offset_loaded, &oes->tx_broadcast,
2439 &nes->tx_broadcast);
2440 /* GLV_TDPC not supported */
2441 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2442 &oes->tx_errors, &nes->tx_errors);
2443 vsi->offset_loaded = true;
2445 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2447 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2448 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2449 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2450 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2451 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2452 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2453 nes->rx_unknown_protocol);
2454 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2455 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2456 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2457 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2458 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2459 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2460 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2465 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2468 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2469 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2471 /* Get rx/tx bytes of internal transfer packets */
2472 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2473 I40E_GLV_GORCL(hw->port),
2475 &pf->internal_stats_offset.rx_bytes,
2476 &pf->internal_stats.rx_bytes);
2478 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2479 I40E_GLV_GOTCL(hw->port),
2481 &pf->internal_stats_offset.tx_bytes,
2482 &pf->internal_stats.tx_bytes);
2483 /* Get total internal rx packet count */
2484 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2485 I40E_GLV_UPRCL(hw->port),
2487 &pf->internal_stats_offset.rx_unicast,
2488 &pf->internal_stats.rx_unicast);
2489 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2490 I40E_GLV_MPRCL(hw->port),
2492 &pf->internal_stats_offset.rx_multicast,
2493 &pf->internal_stats.rx_multicast);
2494 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2495 I40E_GLV_BPRCL(hw->port),
2497 &pf->internal_stats_offset.rx_broadcast,
2498 &pf->internal_stats.rx_broadcast);
2500 /* exclude CRC size */
2501 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2502 pf->internal_stats.rx_multicast +
2503 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2505 /* Get statistics of struct i40e_eth_stats */
2506 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2507 I40E_GLPRT_GORCL(hw->port),
2508 pf->offset_loaded, &os->eth.rx_bytes,
2510 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2511 I40E_GLPRT_UPRCL(hw->port),
2512 pf->offset_loaded, &os->eth.rx_unicast,
2513 &ns->eth.rx_unicast);
2514 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2515 I40E_GLPRT_MPRCL(hw->port),
2516 pf->offset_loaded, &os->eth.rx_multicast,
2517 &ns->eth.rx_multicast);
2518 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2519 I40E_GLPRT_BPRCL(hw->port),
2520 pf->offset_loaded, &os->eth.rx_broadcast,
2521 &ns->eth.rx_broadcast);
2522 /* Workaround: CRC size should not be included in byte statistics,
2523 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2525 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2526 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2528 /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2529 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2532 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2533 ns->eth.rx_bytes = 0;
2534 /* exlude internal rx bytes */
2536 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2538 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2539 pf->offset_loaded, &os->eth.rx_discards,
2540 &ns->eth.rx_discards);
2541 /* GLPRT_REPC not supported */
2542 /* GLPRT_RMPC not supported */
2543 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2545 &os->eth.rx_unknown_protocol,
2546 &ns->eth.rx_unknown_protocol);
2547 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2548 I40E_GLPRT_GOTCL(hw->port),
2549 pf->offset_loaded, &os->eth.tx_bytes,
2551 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2552 I40E_GLPRT_UPTCL(hw->port),
2553 pf->offset_loaded, &os->eth.tx_unicast,
2554 &ns->eth.tx_unicast);
2555 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2556 I40E_GLPRT_MPTCL(hw->port),
2557 pf->offset_loaded, &os->eth.tx_multicast,
2558 &ns->eth.tx_multicast);
2559 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2560 I40E_GLPRT_BPTCL(hw->port),
2561 pf->offset_loaded, &os->eth.tx_broadcast,
2562 &ns->eth.tx_broadcast);
2563 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2564 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2566 /* exclude internal tx bytes */
2567 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2568 ns->eth.tx_bytes = 0;
2570 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2572 /* GLPRT_TEPC not supported */
2574 /* additional port specific stats */
2575 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2576 pf->offset_loaded, &os->tx_dropped_link_down,
2577 &ns->tx_dropped_link_down);
2578 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2579 pf->offset_loaded, &os->crc_errors,
2581 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2582 pf->offset_loaded, &os->illegal_bytes,
2583 &ns->illegal_bytes);
2584 /* GLPRT_ERRBC not supported */
2585 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2586 pf->offset_loaded, &os->mac_local_faults,
2587 &ns->mac_local_faults);
2588 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2589 pf->offset_loaded, &os->mac_remote_faults,
2590 &ns->mac_remote_faults);
2591 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2592 pf->offset_loaded, &os->rx_length_errors,
2593 &ns->rx_length_errors);
2594 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2595 pf->offset_loaded, &os->link_xon_rx,
2597 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2598 pf->offset_loaded, &os->link_xoff_rx,
2600 for (i = 0; i < 8; i++) {
2601 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2603 &os->priority_xon_rx[i],
2604 &ns->priority_xon_rx[i]);
2605 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2607 &os->priority_xoff_rx[i],
2608 &ns->priority_xoff_rx[i]);
2610 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2611 pf->offset_loaded, &os->link_xon_tx,
2613 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2614 pf->offset_loaded, &os->link_xoff_tx,
2616 for (i = 0; i < 8; i++) {
2617 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2619 &os->priority_xon_tx[i],
2620 &ns->priority_xon_tx[i]);
2621 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2623 &os->priority_xoff_tx[i],
2624 &ns->priority_xoff_tx[i]);
2625 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2627 &os->priority_xon_2_xoff[i],
2628 &ns->priority_xon_2_xoff[i]);
2630 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2631 I40E_GLPRT_PRC64L(hw->port),
2632 pf->offset_loaded, &os->rx_size_64,
2634 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2635 I40E_GLPRT_PRC127L(hw->port),
2636 pf->offset_loaded, &os->rx_size_127,
2638 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2639 I40E_GLPRT_PRC255L(hw->port),
2640 pf->offset_loaded, &os->rx_size_255,
2642 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2643 I40E_GLPRT_PRC511L(hw->port),
2644 pf->offset_loaded, &os->rx_size_511,
2646 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2647 I40E_GLPRT_PRC1023L(hw->port),
2648 pf->offset_loaded, &os->rx_size_1023,
2650 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2651 I40E_GLPRT_PRC1522L(hw->port),
2652 pf->offset_loaded, &os->rx_size_1522,
2654 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2655 I40E_GLPRT_PRC9522L(hw->port),
2656 pf->offset_loaded, &os->rx_size_big,
2658 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2659 pf->offset_loaded, &os->rx_undersize,
2661 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2662 pf->offset_loaded, &os->rx_fragments,
2664 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2665 pf->offset_loaded, &os->rx_oversize,
2667 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2668 pf->offset_loaded, &os->rx_jabber,
2670 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2671 I40E_GLPRT_PTC64L(hw->port),
2672 pf->offset_loaded, &os->tx_size_64,
2674 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2675 I40E_GLPRT_PTC127L(hw->port),
2676 pf->offset_loaded, &os->tx_size_127,
2678 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2679 I40E_GLPRT_PTC255L(hw->port),
2680 pf->offset_loaded, &os->tx_size_255,
2682 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2683 I40E_GLPRT_PTC511L(hw->port),
2684 pf->offset_loaded, &os->tx_size_511,
2686 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2687 I40E_GLPRT_PTC1023L(hw->port),
2688 pf->offset_loaded, &os->tx_size_1023,
2690 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2691 I40E_GLPRT_PTC1522L(hw->port),
2692 pf->offset_loaded, &os->tx_size_1522,
2694 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2695 I40E_GLPRT_PTC9522L(hw->port),
2696 pf->offset_loaded, &os->tx_size_big,
2698 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2700 &os->fd_sb_match, &ns->fd_sb_match);
2701 /* GLPRT_MSPDC not supported */
2702 /* GLPRT_XEC not supported */
2704 pf->offset_loaded = true;
2707 i40e_update_vsi_stats(pf->main_vsi);
2710 /* Get all statistics of a port */
2712 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2714 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2715 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2716 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2719 /* call read registers - updates values, now write them to struct */
2720 i40e_read_stats_registers(pf, hw);
2722 stats->ipackets = ns->eth.rx_unicast +
2723 ns->eth.rx_multicast +
2724 ns->eth.rx_broadcast -
2725 ns->eth.rx_discards -
2726 pf->main_vsi->eth_stats.rx_discards;
2727 stats->opackets = ns->eth.tx_unicast +
2728 ns->eth.tx_multicast +
2729 ns->eth.tx_broadcast;
2730 stats->ibytes = ns->eth.rx_bytes;
2731 stats->obytes = ns->eth.tx_bytes;
2732 stats->oerrors = ns->eth.tx_errors +
2733 pf->main_vsi->eth_stats.tx_errors;
2736 stats->imissed = ns->eth.rx_discards +
2737 pf->main_vsi->eth_stats.rx_discards;
2738 stats->ierrors = ns->crc_errors +
2739 ns->rx_length_errors + ns->rx_undersize +
2740 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2742 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2743 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2744 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2745 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2746 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2747 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2748 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2749 ns->eth.rx_unknown_protocol);
2750 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2751 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2752 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2753 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2754 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2755 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2757 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2758 ns->tx_dropped_link_down);
2759 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2760 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2762 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2763 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2764 ns->mac_local_faults);
2765 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2766 ns->mac_remote_faults);
2767 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2768 ns->rx_length_errors);
2769 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2770 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2771 for (i = 0; i < 8; i++) {
2772 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2773 i, ns->priority_xon_rx[i]);
2774 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2775 i, ns->priority_xoff_rx[i]);
2777 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2778 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2779 for (i = 0; i < 8; i++) {
2780 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2781 i, ns->priority_xon_tx[i]);
2782 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2783 i, ns->priority_xoff_tx[i]);
2784 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2785 i, ns->priority_xon_2_xoff[i]);
2787 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2788 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2789 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2790 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2791 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2792 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2793 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2794 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2795 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2796 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2797 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2798 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2799 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2800 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2801 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2802 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2803 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2804 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2805 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2806 ns->mac_short_packet_dropped);
2807 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2808 ns->checksum_error);
2809 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2810 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2813 /* Reset the statistics */
2815 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2817 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2818 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820 /* Mark PF and VSI stats to update the offset, aka "reset" */
2821 pf->offset_loaded = false;
2823 pf->main_vsi->offset_loaded = false;
2825 /* read the stats, reading current register values into offset */
2826 i40e_read_stats_registers(pf, hw);
2830 i40e_xstats_calc_num(void)
2832 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2833 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2834 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2837 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2838 struct rte_eth_xstat_name *xstats_names,
2839 __rte_unused unsigned limit)
2844 if (xstats_names == NULL)
2845 return i40e_xstats_calc_num();
2847 /* Note: limit checked in rte_eth_xstats_names() */
2849 /* Get stats from i40e_eth_stats struct */
2850 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2851 snprintf(xstats_names[count].name,
2852 sizeof(xstats_names[count].name),
2853 "%s", rte_i40e_stats_strings[i].name);
2857 /* Get individiual stats from i40e_hw_port struct */
2858 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2859 snprintf(xstats_names[count].name,
2860 sizeof(xstats_names[count].name),
2861 "%s", rte_i40e_hw_port_strings[i].name);
2865 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2866 for (prio = 0; prio < 8; prio++) {
2867 snprintf(xstats_names[count].name,
2868 sizeof(xstats_names[count].name),
2869 "rx_priority%u_%s", prio,
2870 rte_i40e_rxq_prio_strings[i].name);
2875 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2876 for (prio = 0; prio < 8; prio++) {
2877 snprintf(xstats_names[count].name,
2878 sizeof(xstats_names[count].name),
2879 "tx_priority%u_%s", prio,
2880 rte_i40e_txq_prio_strings[i].name);
2888 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2891 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2892 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2893 unsigned i, count, prio;
2894 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2896 count = i40e_xstats_calc_num();
2900 i40e_read_stats_registers(pf, hw);
2907 /* Get stats from i40e_eth_stats struct */
2908 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2909 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2910 rte_i40e_stats_strings[i].offset);
2911 xstats[count].id = count;
2915 /* Get individiual stats from i40e_hw_port struct */
2916 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2917 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2918 rte_i40e_hw_port_strings[i].offset);
2919 xstats[count].id = count;
2923 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2924 for (prio = 0; prio < 8; prio++) {
2925 xstats[count].value =
2926 *(uint64_t *)(((char *)hw_stats) +
2927 rte_i40e_rxq_prio_strings[i].offset +
2928 (sizeof(uint64_t) * prio));
2929 xstats[count].id = count;
2934 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2935 for (prio = 0; prio < 8; prio++) {
2936 xstats[count].value =
2937 *(uint64_t *)(((char *)hw_stats) +
2938 rte_i40e_txq_prio_strings[i].offset +
2939 (sizeof(uint64_t) * prio));
2940 xstats[count].id = count;
2949 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2950 __rte_unused uint16_t queue_id,
2951 __rte_unused uint8_t stat_idx,
2952 __rte_unused uint8_t is_rx)
2954 PMD_INIT_FUNC_TRACE();
2960 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2962 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2968 full_ver = hw->nvm.oem_ver;
2969 ver = (u8)(full_ver >> 24);
2970 build = (u16)((full_ver >> 8) & 0xffff);
2971 patch = (u8)(full_ver & 0xff);
2973 ret = snprintf(fw_version, fw_size,
2974 "%d.%d%d 0x%08x %d.%d.%d",
2975 ((hw->nvm.version >> 12) & 0xf),
2976 ((hw->nvm.version >> 4) & 0xff),
2977 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2980 ret += 1; /* add the size of '\0' */
2981 if (fw_size < (u32)ret)
2988 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2990 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2991 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2992 struct i40e_vsi *vsi = pf->main_vsi;
2993 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2995 dev_info->pci_dev = pci_dev;
2996 dev_info->max_rx_queues = vsi->nb_qps;
2997 dev_info->max_tx_queues = vsi->nb_qps;
2998 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2999 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3000 dev_info->max_mac_addrs = vsi->max_macaddrs;
3001 dev_info->max_vfs = pci_dev->max_vfs;
3002 dev_info->rx_offload_capa =
3003 DEV_RX_OFFLOAD_VLAN_STRIP |
3004 DEV_RX_OFFLOAD_QINQ_STRIP |
3005 DEV_RX_OFFLOAD_IPV4_CKSUM |
3006 DEV_RX_OFFLOAD_UDP_CKSUM |
3007 DEV_RX_OFFLOAD_TCP_CKSUM;
3008 dev_info->tx_offload_capa =
3009 DEV_TX_OFFLOAD_VLAN_INSERT |
3010 DEV_TX_OFFLOAD_QINQ_INSERT |
3011 DEV_TX_OFFLOAD_IPV4_CKSUM |
3012 DEV_TX_OFFLOAD_UDP_CKSUM |
3013 DEV_TX_OFFLOAD_TCP_CKSUM |
3014 DEV_TX_OFFLOAD_SCTP_CKSUM |
3015 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3016 DEV_TX_OFFLOAD_TCP_TSO |
3017 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3018 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3019 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3020 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3021 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3023 dev_info->reta_size = pf->hash_lut_size;
3024 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3026 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3028 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3029 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3030 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3032 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3036 dev_info->default_txconf = (struct rte_eth_txconf) {
3038 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3039 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3040 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3042 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3043 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3044 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3045 ETH_TXQ_FLAGS_NOOFFLOADS,
3048 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3049 .nb_max = I40E_MAX_RING_DESC,
3050 .nb_min = I40E_MIN_RING_DESC,
3051 .nb_align = I40E_ALIGN_RING_DESC,
3054 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3055 .nb_max = I40E_MAX_RING_DESC,
3056 .nb_min = I40E_MIN_RING_DESC,
3057 .nb_align = I40E_ALIGN_RING_DESC,
3058 .nb_seg_max = I40E_TX_MAX_SEG,
3059 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3062 if (pf->flags & I40E_FLAG_VMDQ) {
3063 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3064 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3065 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3066 pf->max_nb_vmdq_vsi;
3067 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3068 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3069 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3072 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3074 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3075 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3077 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3080 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3084 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3086 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3087 struct i40e_vsi *vsi = pf->main_vsi;
3088 PMD_INIT_FUNC_TRACE();
3091 return i40e_vsi_add_vlan(vsi, vlan_id);
3093 return i40e_vsi_delete_vlan(vsi, vlan_id);
3097 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3098 enum rte_vlan_type vlan_type,
3099 uint16_t tpid, int qinq)
3101 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3104 uint16_t reg_id = 3;
3108 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3112 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3114 if (ret != I40E_SUCCESS) {
3116 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3121 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3124 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3125 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3126 if (reg_r == reg_w) {
3127 PMD_DRV_LOG(DEBUG, "No need to write");
3131 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3133 if (ret != I40E_SUCCESS) {
3135 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3140 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3147 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3148 enum rte_vlan_type vlan_type,
3151 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3152 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3155 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3156 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3157 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3159 "Unsupported vlan type.");
3162 /* 802.1ad frames ability is added in NVM API 1.7*/
3163 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3165 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3166 hw->first_tag = rte_cpu_to_le_16(tpid);
3167 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3168 hw->second_tag = rte_cpu_to_le_16(tpid);
3170 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3171 hw->second_tag = rte_cpu_to_le_16(tpid);
3173 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3174 if (ret != I40E_SUCCESS) {
3176 "Set switch config failed aq_err: %d",
3177 hw->aq.asq_last_status);
3181 /* If NVM API < 1.7, keep the register setting */
3182 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3189 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3191 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3192 struct i40e_vsi *vsi = pf->main_vsi;
3194 if (mask & ETH_VLAN_FILTER_MASK) {
3195 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3196 i40e_vsi_config_vlan_filter(vsi, TRUE);
3198 i40e_vsi_config_vlan_filter(vsi, FALSE);
3201 if (mask & ETH_VLAN_STRIP_MASK) {
3202 /* Enable or disable VLAN stripping */
3203 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3204 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3206 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3209 if (mask & ETH_VLAN_EXTEND_MASK) {
3210 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3211 i40e_vsi_config_double_vlan(vsi, TRUE);
3212 /* Set global registers with default ethertype. */
3213 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3215 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3219 i40e_vsi_config_double_vlan(vsi, FALSE);
3224 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3225 __rte_unused uint16_t queue,
3226 __rte_unused int on)
3228 PMD_INIT_FUNC_TRACE();
3232 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3234 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3235 struct i40e_vsi *vsi = pf->main_vsi;
3236 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3237 struct i40e_vsi_vlan_pvid_info info;
3239 memset(&info, 0, sizeof(info));
3242 info.config.pvid = pvid;
3244 info.config.reject.tagged =
3245 data->dev_conf.txmode.hw_vlan_reject_tagged;
3246 info.config.reject.untagged =
3247 data->dev_conf.txmode.hw_vlan_reject_untagged;
3250 return i40e_vsi_vlan_pvid_set(vsi, &info);
3254 i40e_dev_led_on(struct rte_eth_dev *dev)
3256 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3257 uint32_t mode = i40e_led_get(hw);
3260 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3266 i40e_dev_led_off(struct rte_eth_dev *dev)
3268 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269 uint32_t mode = i40e_led_get(hw);
3272 i40e_led_set(hw, 0, false);
3278 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3280 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3281 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3283 fc_conf->pause_time = pf->fc_conf.pause_time;
3285 /* read out from register, in case they are modified by other port */
3286 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3287 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3288 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3289 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3291 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3292 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3294 /* Return current mode according to actual setting*/
3295 switch (hw->fc.current_mode) {
3297 fc_conf->mode = RTE_FC_FULL;
3299 case I40E_FC_TX_PAUSE:
3300 fc_conf->mode = RTE_FC_TX_PAUSE;
3302 case I40E_FC_RX_PAUSE:
3303 fc_conf->mode = RTE_FC_RX_PAUSE;
3307 fc_conf->mode = RTE_FC_NONE;
3314 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3316 uint32_t mflcn_reg, fctrl_reg, reg;
3317 uint32_t max_high_water;
3318 uint8_t i, aq_failure;
3322 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3323 [RTE_FC_NONE] = I40E_FC_NONE,
3324 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3325 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3326 [RTE_FC_FULL] = I40E_FC_FULL
3329 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3331 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3332 if ((fc_conf->high_water > max_high_water) ||
3333 (fc_conf->high_water < fc_conf->low_water)) {
3335 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3340 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3341 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3342 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3344 pf->fc_conf.pause_time = fc_conf->pause_time;
3345 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3346 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3348 PMD_INIT_FUNC_TRACE();
3350 /* All the link flow control related enable/disable register
3351 * configuration is handle by the F/W
3353 err = i40e_set_fc(hw, &aq_failure, true);
3357 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3358 /* Configure flow control refresh threshold,
3359 * the value for stat_tx_pause_refresh_timer[8]
3360 * is used for global pause operation.
3364 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3365 pf->fc_conf.pause_time);
3367 /* configure the timer value included in transmitted pause
3369 * the value for stat_tx_pause_quanta[8] is used for global
3372 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3373 pf->fc_conf.pause_time);
3375 fctrl_reg = I40E_READ_REG(hw,
3376 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3378 if (fc_conf->mac_ctrl_frame_fwd != 0)
3379 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3381 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3383 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3386 /* Configure pause time (2 TCs per register) */
3387 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3388 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3389 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3391 /* Configure flow control refresh threshold value */
3392 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3393 pf->fc_conf.pause_time / 2);
3395 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3397 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3398 *depending on configuration
3400 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3401 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3402 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3404 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3405 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3408 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3411 /* config the water marker both based on the packets and bytes */
3412 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3413 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3414 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3415 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3416 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3417 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3418 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3419 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3421 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3422 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3425 I40E_WRITE_FLUSH(hw);
3431 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3432 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3434 PMD_INIT_FUNC_TRACE();
3439 /* Add a MAC address, and update filters */
3441 i40e_macaddr_add(struct rte_eth_dev *dev,
3442 struct ether_addr *mac_addr,
3443 __rte_unused uint32_t index,
3446 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3447 struct i40e_mac_filter_info mac_filter;
3448 struct i40e_vsi *vsi;
3451 /* If VMDQ not enabled or configured, return */
3452 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3453 !pf->nb_cfg_vmdq_vsi)) {
3454 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3455 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3460 if (pool > pf->nb_cfg_vmdq_vsi) {
3461 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3462 pool, pf->nb_cfg_vmdq_vsi);
3466 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3467 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3468 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3470 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3475 vsi = pf->vmdq[pool - 1].vsi;
3477 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3478 if (ret != I40E_SUCCESS) {
3479 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3485 /* Remove a MAC address, and update filters */
3487 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3489 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3490 struct i40e_vsi *vsi;
3491 struct rte_eth_dev_data *data = dev->data;
3492 struct ether_addr *macaddr;
3497 macaddr = &(data->mac_addrs[index]);
3499 pool_sel = dev->data->mac_pool_sel[index];
3501 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3502 if (pool_sel & (1ULL << i)) {
3506 /* No VMDQ pool enabled or configured */
3507 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3508 (i > pf->nb_cfg_vmdq_vsi)) {
3510 "No VMDQ pool enabled/configured");
3513 vsi = pf->vmdq[i - 1].vsi;
3515 ret = i40e_vsi_delete_mac(vsi, macaddr);
3518 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3525 /* Set perfect match or hash match of MAC and VLAN for a VF */
3527 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3528 struct rte_eth_mac_filter *filter,
3532 struct i40e_mac_filter_info mac_filter;
3533 struct ether_addr old_mac;
3534 struct ether_addr *new_mac;
3535 struct i40e_pf_vf *vf = NULL;
3540 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3543 hw = I40E_PF_TO_HW(pf);
3545 if (filter == NULL) {
3546 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3550 new_mac = &filter->mac_addr;
3552 if (is_zero_ether_addr(new_mac)) {
3553 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3557 vf_id = filter->dst_id;
3559 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3560 PMD_DRV_LOG(ERR, "Invalid argument.");
3563 vf = &pf->vfs[vf_id];
3565 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3566 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3571 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3572 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3574 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3577 mac_filter.filter_type = filter->filter_type;
3578 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3579 if (ret != I40E_SUCCESS) {
3580 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3583 ether_addr_copy(new_mac, &pf->dev_addr);
3585 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3587 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3588 if (ret != I40E_SUCCESS) {
3589 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3593 /* Clear device address as it has been removed */
3594 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3595 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3601 /* MAC filter handle */
3603 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3606 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3607 struct rte_eth_mac_filter *filter;
3608 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3609 int ret = I40E_NOT_SUPPORTED;
3611 filter = (struct rte_eth_mac_filter *)(arg);
3613 switch (filter_op) {
3614 case RTE_ETH_FILTER_NOP:
3617 case RTE_ETH_FILTER_ADD:
3618 i40e_pf_disable_irq0(hw);
3620 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3621 i40e_pf_enable_irq0(hw);
3623 case RTE_ETH_FILTER_DELETE:
3624 i40e_pf_disable_irq0(hw);
3626 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3627 i40e_pf_enable_irq0(hw);
3630 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3631 ret = I40E_ERR_PARAM;
3639 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3641 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3642 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3648 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3649 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3652 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3656 uint32_t *lut_dw = (uint32_t *)lut;
3657 uint16_t i, lut_size_dw = lut_size / 4;
3659 for (i = 0; i < lut_size_dw; i++)
3660 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3667 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3676 pf = I40E_VSI_TO_PF(vsi);
3677 hw = I40E_VSI_TO_HW(vsi);
3679 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3680 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3683 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3687 uint32_t *lut_dw = (uint32_t *)lut;
3688 uint16_t i, lut_size_dw = lut_size / 4;
3690 for (i = 0; i < lut_size_dw; i++)
3691 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3692 I40E_WRITE_FLUSH(hw);
3699 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3700 struct rte_eth_rss_reta_entry64 *reta_conf,
3703 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3704 uint16_t i, lut_size = pf->hash_lut_size;
3705 uint16_t idx, shift;
3709 if (reta_size != lut_size ||
3710 reta_size > ETH_RSS_RETA_SIZE_512) {
3712 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3713 reta_size, lut_size);
3717 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3719 PMD_DRV_LOG(ERR, "No memory can be allocated");
3722 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3725 for (i = 0; i < reta_size; i++) {
3726 idx = i / RTE_RETA_GROUP_SIZE;
3727 shift = i % RTE_RETA_GROUP_SIZE;
3728 if (reta_conf[idx].mask & (1ULL << shift))
3729 lut[i] = reta_conf[idx].reta[shift];
3731 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3740 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3741 struct rte_eth_rss_reta_entry64 *reta_conf,
3744 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3745 uint16_t i, lut_size = pf->hash_lut_size;
3746 uint16_t idx, shift;
3750 if (reta_size != lut_size ||
3751 reta_size > ETH_RSS_RETA_SIZE_512) {
3753 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3754 reta_size, lut_size);
3758 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3760 PMD_DRV_LOG(ERR, "No memory can be allocated");
3764 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3767 for (i = 0; i < reta_size; i++) {
3768 idx = i / RTE_RETA_GROUP_SIZE;
3769 shift = i % RTE_RETA_GROUP_SIZE;
3770 if (reta_conf[idx].mask & (1ULL << shift))
3771 reta_conf[idx].reta[shift] = lut[i];
3781 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3782 * @hw: pointer to the HW structure
3783 * @mem: pointer to mem struct to fill out
3784 * @size: size of memory requested
3785 * @alignment: what to align the allocation to
3787 enum i40e_status_code
3788 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3789 struct i40e_dma_mem *mem,
3793 const struct rte_memzone *mz = NULL;
3794 char z_name[RTE_MEMZONE_NAMESIZE];
3797 return I40E_ERR_PARAM;
3799 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3800 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3801 alignment, RTE_PGSIZE_2M);
3803 return I40E_ERR_NO_MEMORY;
3807 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3808 mem->zone = (const void *)mz;
3810 "memzone %s allocated with physical address: %"PRIu64,
3813 return I40E_SUCCESS;
3817 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3818 * @hw: pointer to the HW structure
3819 * @mem: ptr to mem struct to free
3821 enum i40e_status_code
3822 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3823 struct i40e_dma_mem *mem)
3826 return I40E_ERR_PARAM;
3829 "memzone %s to be freed with physical address: %"PRIu64,
3830 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3831 rte_memzone_free((const struct rte_memzone *)mem->zone);
3836 return I40E_SUCCESS;
3840 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3841 * @hw: pointer to the HW structure
3842 * @mem: pointer to mem struct to fill out
3843 * @size: size of memory requested
3845 enum i40e_status_code
3846 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3847 struct i40e_virt_mem *mem,
3851 return I40E_ERR_PARAM;
3854 mem->va = rte_zmalloc("i40e", size, 0);
3857 return I40E_SUCCESS;
3859 return I40E_ERR_NO_MEMORY;
3863 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3864 * @hw: pointer to the HW structure
3865 * @mem: pointer to mem struct to free
3867 enum i40e_status_code
3868 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3869 struct i40e_virt_mem *mem)
3872 return I40E_ERR_PARAM;
3877 return I40E_SUCCESS;
3881 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3883 rte_spinlock_init(&sp->spinlock);
3887 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3889 rte_spinlock_lock(&sp->spinlock);
3893 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3895 rte_spinlock_unlock(&sp->spinlock);
3899 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3905 * Get the hardware capabilities, which will be parsed
3906 * and saved into struct i40e_hw.
3909 i40e_get_cap(struct i40e_hw *hw)
3911 struct i40e_aqc_list_capabilities_element_resp *buf;
3912 uint16_t len, size = 0;
3915 /* Calculate a huge enough buff for saving response data temporarily */
3916 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3917 I40E_MAX_CAP_ELE_NUM;
3918 buf = rte_zmalloc("i40e", len, 0);
3920 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3921 return I40E_ERR_NO_MEMORY;
3924 /* Get, parse the capabilities and save it to hw */
3925 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3926 i40e_aqc_opc_list_func_capabilities, NULL);
3927 if (ret != I40E_SUCCESS)
3928 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3930 /* Free the temporary buffer after being used */
3937 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3939 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3940 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3941 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3942 uint16_t qp_count = 0, vsi_count = 0;
3944 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3945 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3948 /* Add the parameter init for LFC */
3949 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3950 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3951 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3953 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3954 pf->max_num_vsi = hw->func_caps.num_vsis;
3955 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3956 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3957 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3959 /* FDir queue/VSI allocation */
3960 pf->fdir_qp_offset = 0;
3961 if (hw->func_caps.fd) {
3962 pf->flags |= I40E_FLAG_FDIR;
3963 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3965 pf->fdir_nb_qps = 0;
3967 qp_count += pf->fdir_nb_qps;
3970 /* LAN queue/VSI allocation */
3971 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3972 if (!hw->func_caps.rss) {
3975 pf->flags |= I40E_FLAG_RSS;
3976 if (hw->mac.type == I40E_MAC_X722)
3977 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3978 pf->lan_nb_qps = pf->lan_nb_qp_max;
3980 qp_count += pf->lan_nb_qps;
3983 /* VF queue/VSI allocation */
3984 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3985 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3986 pf->flags |= I40E_FLAG_SRIOV;
3987 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3988 pf->vf_num = pci_dev->max_vfs;
3990 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3991 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3996 qp_count += pf->vf_nb_qps * pf->vf_num;
3997 vsi_count += pf->vf_num;
3999 /* VMDq queue/VSI allocation */
4000 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4001 pf->vmdq_nb_qps = 0;
4002 pf->max_nb_vmdq_vsi = 0;
4003 if (hw->func_caps.vmdq) {
4004 if (qp_count < hw->func_caps.num_tx_qp &&
4005 vsi_count < hw->func_caps.num_vsis) {
4006 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4007 qp_count) / pf->vmdq_nb_qp_max;
4009 /* Limit the maximum number of VMDq vsi to the maximum
4010 * ethdev can support
4012 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4013 hw->func_caps.num_vsis - vsi_count);
4014 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4016 if (pf->max_nb_vmdq_vsi) {
4017 pf->flags |= I40E_FLAG_VMDQ;
4018 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4020 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4021 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4022 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4025 "No enough queues left for VMDq");
4028 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4031 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4032 vsi_count += pf->max_nb_vmdq_vsi;
4034 if (hw->func_caps.dcb)
4035 pf->flags |= I40E_FLAG_DCB;
4037 if (qp_count > hw->func_caps.num_tx_qp) {
4039 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4040 qp_count, hw->func_caps.num_tx_qp);
4043 if (vsi_count > hw->func_caps.num_vsis) {
4045 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4046 vsi_count, hw->func_caps.num_vsis);
4054 i40e_pf_get_switch_config(struct i40e_pf *pf)
4056 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4057 struct i40e_aqc_get_switch_config_resp *switch_config;
4058 struct i40e_aqc_switch_config_element_resp *element;
4059 uint16_t start_seid = 0, num_reported;
4062 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4063 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4064 if (!switch_config) {
4065 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4069 /* Get the switch configurations */
4070 ret = i40e_aq_get_switch_config(hw, switch_config,
4071 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4072 if (ret != I40E_SUCCESS) {
4073 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4076 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4077 if (num_reported != 1) { /* The number should be 1 */
4078 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4082 /* Parse the switch configuration elements */
4083 element = &(switch_config->element[0]);
4084 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4085 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4086 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4088 PMD_DRV_LOG(INFO, "Unknown element type");
4091 rte_free(switch_config);
4097 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4100 struct pool_entry *entry;
4102 if (pool == NULL || num == 0)
4105 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4106 if (entry == NULL) {
4107 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4111 /* queue heap initialize */
4112 pool->num_free = num;
4113 pool->num_alloc = 0;
4115 LIST_INIT(&pool->alloc_list);
4116 LIST_INIT(&pool->free_list);
4118 /* Initialize element */
4122 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4127 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4129 struct pool_entry *entry, *next_entry;
4134 for (entry = LIST_FIRST(&pool->alloc_list);
4135 entry && (next_entry = LIST_NEXT(entry, next), 1);
4136 entry = next_entry) {
4137 LIST_REMOVE(entry, next);
4141 for (entry = LIST_FIRST(&pool->free_list);
4142 entry && (next_entry = LIST_NEXT(entry, next), 1);
4143 entry = next_entry) {
4144 LIST_REMOVE(entry, next);
4149 pool->num_alloc = 0;
4151 LIST_INIT(&pool->alloc_list);
4152 LIST_INIT(&pool->free_list);
4156 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4159 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4160 uint32_t pool_offset;
4164 PMD_DRV_LOG(ERR, "Invalid parameter");
4168 pool_offset = base - pool->base;
4169 /* Lookup in alloc list */
4170 LIST_FOREACH(entry, &pool->alloc_list, next) {
4171 if (entry->base == pool_offset) {
4172 valid_entry = entry;
4173 LIST_REMOVE(entry, next);
4178 /* Not find, return */
4179 if (valid_entry == NULL) {
4180 PMD_DRV_LOG(ERR, "Failed to find entry");
4185 * Found it, move it to free list and try to merge.
4186 * In order to make merge easier, always sort it by qbase.
4187 * Find adjacent prev and last entries.
4190 LIST_FOREACH(entry, &pool->free_list, next) {
4191 if (entry->base > valid_entry->base) {
4199 /* Try to merge with next one*/
4201 /* Merge with next one */
4202 if (valid_entry->base + valid_entry->len == next->base) {
4203 next->base = valid_entry->base;
4204 next->len += valid_entry->len;
4205 rte_free(valid_entry);
4212 /* Merge with previous one */
4213 if (prev->base + prev->len == valid_entry->base) {
4214 prev->len += valid_entry->len;
4215 /* If it merge with next one, remove next node */
4217 LIST_REMOVE(valid_entry, next);
4218 rte_free(valid_entry);
4220 rte_free(valid_entry);
4226 /* Not find any entry to merge, insert */
4229 LIST_INSERT_AFTER(prev, valid_entry, next);
4230 else if (next != NULL)
4231 LIST_INSERT_BEFORE(next, valid_entry, next);
4232 else /* It's empty list, insert to head */
4233 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4236 pool->num_free += valid_entry->len;
4237 pool->num_alloc -= valid_entry->len;
4243 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4246 struct pool_entry *entry, *valid_entry;
4248 if (pool == NULL || num == 0) {
4249 PMD_DRV_LOG(ERR, "Invalid parameter");
4253 if (pool->num_free < num) {
4254 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4255 num, pool->num_free);
4260 /* Lookup in free list and find most fit one */
4261 LIST_FOREACH(entry, &pool->free_list, next) {
4262 if (entry->len >= num) {
4264 if (entry->len == num) {
4265 valid_entry = entry;
4268 if (valid_entry == NULL || valid_entry->len > entry->len)
4269 valid_entry = entry;
4273 /* Not find one to satisfy the request, return */
4274 if (valid_entry == NULL) {
4275 PMD_DRV_LOG(ERR, "No valid entry found");
4279 * The entry have equal queue number as requested,
4280 * remove it from alloc_list.
4282 if (valid_entry->len == num) {
4283 LIST_REMOVE(valid_entry, next);
4286 * The entry have more numbers than requested,
4287 * create a new entry for alloc_list and minus its
4288 * queue base and number in free_list.
4290 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4291 if (entry == NULL) {
4293 "Failed to allocate memory for resource pool");
4296 entry->base = valid_entry->base;
4298 valid_entry->base += num;
4299 valid_entry->len -= num;
4300 valid_entry = entry;
4303 /* Insert it into alloc list, not sorted */
4304 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4306 pool->num_free -= valid_entry->len;
4307 pool->num_alloc += valid_entry->len;
4309 return valid_entry->base + pool->base;
4313 * bitmap_is_subset - Check whether src2 is subset of src1
4316 bitmap_is_subset(uint8_t src1, uint8_t src2)
4318 return !((src1 ^ src2) & src2);
4321 static enum i40e_status_code
4322 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4324 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4326 /* If DCB is not supported, only default TC is supported */
4327 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4328 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4329 return I40E_NOT_SUPPORTED;
4332 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4334 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4335 hw->func_caps.enabled_tcmap, enabled_tcmap);
4336 return I40E_NOT_SUPPORTED;
4338 return I40E_SUCCESS;
4342 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4343 struct i40e_vsi_vlan_pvid_info *info)
4346 struct i40e_vsi_context ctxt;
4347 uint8_t vlan_flags = 0;
4350 if (vsi == NULL || info == NULL) {
4351 PMD_DRV_LOG(ERR, "invalid parameters");
4352 return I40E_ERR_PARAM;
4356 vsi->info.pvid = info->config.pvid;
4358 * If insert pvid is enabled, only tagged pkts are
4359 * allowed to be sent out.
4361 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4362 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4365 if (info->config.reject.tagged == 0)
4366 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4368 if (info->config.reject.untagged == 0)
4369 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4371 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4372 I40E_AQ_VSI_PVLAN_MODE_MASK);
4373 vsi->info.port_vlan_flags |= vlan_flags;
4374 vsi->info.valid_sections =
4375 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4376 memset(&ctxt, 0, sizeof(ctxt));
4377 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4378 ctxt.seid = vsi->seid;
4380 hw = I40E_VSI_TO_HW(vsi);
4381 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4382 if (ret != I40E_SUCCESS)
4383 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4389 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4391 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4393 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4395 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4396 if (ret != I40E_SUCCESS)
4400 PMD_DRV_LOG(ERR, "seid not valid");
4404 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4405 tc_bw_data.tc_valid_bits = enabled_tcmap;
4406 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4407 tc_bw_data.tc_bw_credits[i] =
4408 (enabled_tcmap & (1 << i)) ? 1 : 0;
4410 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4411 if (ret != I40E_SUCCESS) {
4412 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4416 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4417 sizeof(vsi->info.qs_handle));
4418 return I40E_SUCCESS;
4421 static enum i40e_status_code
4422 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4423 struct i40e_aqc_vsi_properties_data *info,
4424 uint8_t enabled_tcmap)
4426 enum i40e_status_code ret;
4427 int i, total_tc = 0;
4428 uint16_t qpnum_per_tc, bsf, qp_idx;
4430 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4431 if (ret != I40E_SUCCESS)
4434 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4435 if (enabled_tcmap & (1 << i))
4439 vsi->enabled_tc = enabled_tcmap;
4441 /* Number of queues per enabled TC */
4442 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4443 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4444 bsf = rte_bsf32(qpnum_per_tc);
4446 /* Adjust the queue number to actual queues that can be applied */
4447 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4448 vsi->nb_qps = qpnum_per_tc * total_tc;
4451 * Configure TC and queue mapping parameters, for enabled TC,
4452 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4453 * default queue will serve it.
4456 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4457 if (vsi->enabled_tc & (1 << i)) {
4458 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4459 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4460 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4461 qp_idx += qpnum_per_tc;
4463 info->tc_mapping[i] = 0;
4466 /* Associate queue number with VSI */
4467 if (vsi->type == I40E_VSI_SRIOV) {
4468 info->mapping_flags |=
4469 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4470 for (i = 0; i < vsi->nb_qps; i++)
4471 info->queue_mapping[i] =
4472 rte_cpu_to_le_16(vsi->base_queue + i);
4474 info->mapping_flags |=
4475 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4476 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4478 info->valid_sections |=
4479 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4481 return I40E_SUCCESS;
4485 i40e_veb_release(struct i40e_veb *veb)
4487 struct i40e_vsi *vsi;
4493 if (!TAILQ_EMPTY(&veb->head)) {
4494 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4497 /* associate_vsi field is NULL for floating VEB */
4498 if (veb->associate_vsi != NULL) {
4499 vsi = veb->associate_vsi;
4500 hw = I40E_VSI_TO_HW(vsi);
4502 vsi->uplink_seid = veb->uplink_seid;
4505 veb->associate_pf->main_vsi->floating_veb = NULL;
4506 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4509 i40e_aq_delete_element(hw, veb->seid, NULL);
4511 return I40E_SUCCESS;
4515 static struct i40e_veb *
4516 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4518 struct i40e_veb *veb;
4524 "veb setup failed, associated PF shouldn't null");
4527 hw = I40E_PF_TO_HW(pf);
4529 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4531 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4535 veb->associate_vsi = vsi;
4536 veb->associate_pf = pf;
4537 TAILQ_INIT(&veb->head);
4538 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4540 /* create floating veb if vsi is NULL */
4542 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4543 I40E_DEFAULT_TCMAP, false,
4544 &veb->seid, false, NULL);
4546 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4547 true, &veb->seid, false, NULL);
4550 if (ret != I40E_SUCCESS) {
4551 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4552 hw->aq.asq_last_status);
4555 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4557 /* get statistics index */
4558 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4559 &veb->stats_idx, NULL, NULL, NULL);
4560 if (ret != I40E_SUCCESS) {
4561 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4562 hw->aq.asq_last_status);
4565 /* Get VEB bandwidth, to be implemented */
4566 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4568 vsi->uplink_seid = veb->seid;
4577 i40e_vsi_release(struct i40e_vsi *vsi)
4581 struct i40e_vsi_list *vsi_list;
4584 struct i40e_mac_filter *f;
4585 uint16_t user_param;
4588 return I40E_SUCCESS;
4593 user_param = vsi->user_param;
4595 pf = I40E_VSI_TO_PF(vsi);
4596 hw = I40E_VSI_TO_HW(vsi);
4598 /* VSI has child to attach, release child first */
4600 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4601 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4604 i40e_veb_release(vsi->veb);
4607 if (vsi->floating_veb) {
4608 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4609 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4614 /* Remove all macvlan filters of the VSI */
4615 i40e_vsi_remove_all_macvlan_filter(vsi);
4616 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4619 if (vsi->type != I40E_VSI_MAIN &&
4620 ((vsi->type != I40E_VSI_SRIOV) ||
4621 !pf->floating_veb_list[user_param])) {
4622 /* Remove vsi from parent's sibling list */
4623 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4624 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4625 return I40E_ERR_PARAM;
4627 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4628 &vsi->sib_vsi_list, list);
4630 /* Remove all switch element of the VSI */
4631 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4632 if (ret != I40E_SUCCESS)
4633 PMD_DRV_LOG(ERR, "Failed to delete element");
4636 if ((vsi->type == I40E_VSI_SRIOV) &&
4637 pf->floating_veb_list[user_param]) {
4638 /* Remove vsi from parent's sibling list */
4639 if (vsi->parent_vsi == NULL ||
4640 vsi->parent_vsi->floating_veb == NULL) {
4641 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4642 return I40E_ERR_PARAM;
4644 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4645 &vsi->sib_vsi_list, list);
4647 /* Remove all switch element of the VSI */
4648 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4649 if (ret != I40E_SUCCESS)
4650 PMD_DRV_LOG(ERR, "Failed to delete element");
4653 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4655 if (vsi->type != I40E_VSI_SRIOV)
4656 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4659 return I40E_SUCCESS;
4663 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4665 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4666 struct i40e_aqc_remove_macvlan_element_data def_filter;
4667 struct i40e_mac_filter_info filter;
4670 if (vsi->type != I40E_VSI_MAIN)
4671 return I40E_ERR_CONFIG;
4672 memset(&def_filter, 0, sizeof(def_filter));
4673 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4675 def_filter.vlan_tag = 0;
4676 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4677 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4678 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4679 if (ret != I40E_SUCCESS) {
4680 struct i40e_mac_filter *f;
4681 struct ether_addr *mac;
4684 "Cannot remove the default macvlan filter");
4685 /* It needs to add the permanent mac into mac list */
4686 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4688 PMD_DRV_LOG(ERR, "failed to allocate memory");
4689 return I40E_ERR_NO_MEMORY;
4691 mac = &f->mac_info.mac_addr;
4692 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4694 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4695 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4700 rte_memcpy(&filter.mac_addr,
4701 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4702 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4703 return i40e_vsi_add_mac(vsi, &filter);
4707 * i40e_vsi_get_bw_config - Query VSI BW Information
4708 * @vsi: the VSI to be queried
4710 * Returns 0 on success, negative value on failure
4712 static enum i40e_status_code
4713 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4715 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4716 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4717 struct i40e_hw *hw = &vsi->adapter->hw;
4722 memset(&bw_config, 0, sizeof(bw_config));
4723 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4724 if (ret != I40E_SUCCESS) {
4725 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4726 hw->aq.asq_last_status);
4730 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4731 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4732 &ets_sla_config, NULL);
4733 if (ret != I40E_SUCCESS) {
4735 "VSI failed to get TC bandwdith configuration %u",
4736 hw->aq.asq_last_status);
4740 /* store and print out BW info */
4741 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4742 vsi->bw_info.bw_max = bw_config.max_bw;
4743 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4744 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4745 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4746 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4748 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4749 vsi->bw_info.bw_ets_share_credits[i] =
4750 ets_sla_config.share_credits[i];
4751 vsi->bw_info.bw_ets_credits[i] =
4752 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4753 /* 4 bits per TC, 4th bit is reserved */
4754 vsi->bw_info.bw_ets_max[i] =
4755 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4756 RTE_LEN2MASK(3, uint8_t));
4757 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4758 vsi->bw_info.bw_ets_share_credits[i]);
4759 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4760 vsi->bw_info.bw_ets_credits[i]);
4761 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4762 vsi->bw_info.bw_ets_max[i]);
4765 return I40E_SUCCESS;
4768 /* i40e_enable_pf_lb
4769 * @pf: pointer to the pf structure
4771 * allow loopback on pf
4774 i40e_enable_pf_lb(struct i40e_pf *pf)
4776 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4777 struct i40e_vsi_context ctxt;
4780 /* Use the FW API if FW >= v5.0 */
4781 if (hw->aq.fw_maj_ver < 5) {
4782 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4786 memset(&ctxt, 0, sizeof(ctxt));
4787 ctxt.seid = pf->main_vsi_seid;
4788 ctxt.pf_num = hw->pf_id;
4789 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4791 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4792 ret, hw->aq.asq_last_status);
4795 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4796 ctxt.info.valid_sections =
4797 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4798 ctxt.info.switch_id |=
4799 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4801 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4803 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4804 hw->aq.asq_last_status);
4809 i40e_vsi_setup(struct i40e_pf *pf,
4810 enum i40e_vsi_type type,
4811 struct i40e_vsi *uplink_vsi,
4812 uint16_t user_param)
4814 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4815 struct i40e_vsi *vsi;
4816 struct i40e_mac_filter_info filter;
4818 struct i40e_vsi_context ctxt;
4819 struct ether_addr broadcast =
4820 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4822 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4823 uplink_vsi == NULL) {
4825 "VSI setup failed, VSI link shouldn't be NULL");
4829 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4831 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4836 * 1.type is not MAIN and uplink vsi is not NULL
4837 * If uplink vsi didn't setup VEB, create one first under veb field
4838 * 2.type is SRIOV and the uplink is NULL
4839 * If floating VEB is NULL, create one veb under floating veb field
4842 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4843 uplink_vsi->veb == NULL) {
4844 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4846 if (uplink_vsi->veb == NULL) {
4847 PMD_DRV_LOG(ERR, "VEB setup failed");
4850 /* set ALLOWLOOPBACk on pf, when veb is created */
4851 i40e_enable_pf_lb(pf);
4854 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4855 pf->main_vsi->floating_veb == NULL) {
4856 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4858 if (pf->main_vsi->floating_veb == NULL) {
4859 PMD_DRV_LOG(ERR, "VEB setup failed");
4864 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4866 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4869 TAILQ_INIT(&vsi->mac_list);
4871 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4872 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4873 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4874 vsi->user_param = user_param;
4875 vsi->vlan_anti_spoof_on = 0;
4876 vsi->vlan_filter_on = 0;
4877 /* Allocate queues */
4878 switch (vsi->type) {
4879 case I40E_VSI_MAIN :
4880 vsi->nb_qps = pf->lan_nb_qps;
4882 case I40E_VSI_SRIOV :
4883 vsi->nb_qps = pf->vf_nb_qps;
4885 case I40E_VSI_VMDQ2:
4886 vsi->nb_qps = pf->vmdq_nb_qps;
4889 vsi->nb_qps = pf->fdir_nb_qps;
4895 * The filter status descriptor is reported in rx queue 0,
4896 * while the tx queue for fdir filter programming has no
4897 * such constraints, can be non-zero queues.
4898 * To simplify it, choose FDIR vsi use queue 0 pair.
4899 * To make sure it will use queue 0 pair, queue allocation
4900 * need be done before this function is called
4902 if (type != I40E_VSI_FDIR) {
4903 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4905 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4909 vsi->base_queue = ret;
4911 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4913 /* VF has MSIX interrupt in VF range, don't allocate here */
4914 if (type == I40E_VSI_MAIN) {
4915 ret = i40e_res_pool_alloc(&pf->msix_pool,
4916 RTE_MIN(vsi->nb_qps,
4917 RTE_MAX_RXTX_INTR_VEC_ID));
4919 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4921 goto fail_queue_alloc;
4923 vsi->msix_intr = ret;
4924 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4925 } else if (type != I40E_VSI_SRIOV) {
4926 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4928 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4929 goto fail_queue_alloc;
4931 vsi->msix_intr = ret;
4939 if (type == I40E_VSI_MAIN) {
4940 /* For main VSI, no need to add since it's default one */
4941 vsi->uplink_seid = pf->mac_seid;
4942 vsi->seid = pf->main_vsi_seid;
4943 /* Bind queues with specific MSIX interrupt */
4945 * Needs 2 interrupt at least, one for misc cause which will
4946 * enabled from OS side, Another for queues binding the
4947 * interrupt from device side only.
4950 /* Get default VSI parameters from hardware */
4951 memset(&ctxt, 0, sizeof(ctxt));
4952 ctxt.seid = vsi->seid;
4953 ctxt.pf_num = hw->pf_id;
4954 ctxt.uplink_seid = vsi->uplink_seid;
4956 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4957 if (ret != I40E_SUCCESS) {
4958 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4959 goto fail_msix_alloc;
4961 rte_memcpy(&vsi->info, &ctxt.info,
4962 sizeof(struct i40e_aqc_vsi_properties_data));
4963 vsi->vsi_id = ctxt.vsi_number;
4964 vsi->info.valid_sections = 0;
4966 /* Configure tc, enabled TC0 only */
4967 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4969 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4970 goto fail_msix_alloc;
4973 /* TC, queue mapping */
4974 memset(&ctxt, 0, sizeof(ctxt));
4975 vsi->info.valid_sections |=
4976 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4977 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4978 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4979 rte_memcpy(&ctxt.info, &vsi->info,
4980 sizeof(struct i40e_aqc_vsi_properties_data));
4981 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4982 I40E_DEFAULT_TCMAP);
4983 if (ret != I40E_SUCCESS) {
4985 "Failed to configure TC queue mapping");
4986 goto fail_msix_alloc;
4988 ctxt.seid = vsi->seid;
4989 ctxt.pf_num = hw->pf_id;
4990 ctxt.uplink_seid = vsi->uplink_seid;
4993 /* Update VSI parameters */
4994 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4995 if (ret != I40E_SUCCESS) {
4996 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4997 goto fail_msix_alloc;
5000 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5001 sizeof(vsi->info.tc_mapping));
5002 rte_memcpy(&vsi->info.queue_mapping,
5003 &ctxt.info.queue_mapping,
5004 sizeof(vsi->info.queue_mapping));
5005 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5006 vsi->info.valid_sections = 0;
5008 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5012 * Updating default filter settings are necessary to prevent
5013 * reception of tagged packets.
5014 * Some old firmware configurations load a default macvlan
5015 * filter which accepts both tagged and untagged packets.
5016 * The updating is to use a normal filter instead if needed.
5017 * For NVM 4.2.2 or after, the updating is not needed anymore.
5018 * The firmware with correct configurations load the default
5019 * macvlan filter which is expected and cannot be removed.
5021 i40e_update_default_filter_setting(vsi);
5022 i40e_config_qinq(hw, vsi);
5023 } else if (type == I40E_VSI_SRIOV) {
5024 memset(&ctxt, 0, sizeof(ctxt));
5026 * For other VSI, the uplink_seid equals to uplink VSI's
5027 * uplink_seid since they share same VEB
5029 if (uplink_vsi == NULL)
5030 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5032 vsi->uplink_seid = uplink_vsi->uplink_seid;
5033 ctxt.pf_num = hw->pf_id;
5034 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5035 ctxt.uplink_seid = vsi->uplink_seid;
5036 ctxt.connection_type = 0x1;
5037 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5039 /* Use the VEB configuration if FW >= v5.0 */
5040 if (hw->aq.fw_maj_ver >= 5) {
5041 /* Configure switch ID */
5042 ctxt.info.valid_sections |=
5043 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5044 ctxt.info.switch_id =
5045 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5048 /* Configure port/vlan */
5049 ctxt.info.valid_sections |=
5050 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5051 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5052 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5053 hw->func_caps.enabled_tcmap);
5054 if (ret != I40E_SUCCESS) {
5056 "Failed to configure TC queue mapping");
5057 goto fail_msix_alloc;
5060 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5061 ctxt.info.valid_sections |=
5062 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5064 * Since VSI is not created yet, only configure parameter,
5065 * will add vsi below.
5068 i40e_config_qinq(hw, vsi);
5069 } else if (type == I40E_VSI_VMDQ2) {
5070 memset(&ctxt, 0, sizeof(ctxt));
5072 * For other VSI, the uplink_seid equals to uplink VSI's
5073 * uplink_seid since they share same VEB
5075 vsi->uplink_seid = uplink_vsi->uplink_seid;
5076 ctxt.pf_num = hw->pf_id;
5078 ctxt.uplink_seid = vsi->uplink_seid;
5079 ctxt.connection_type = 0x1;
5080 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5082 ctxt.info.valid_sections |=
5083 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5084 /* user_param carries flag to enable loop back */
5086 ctxt.info.switch_id =
5087 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5088 ctxt.info.switch_id |=
5089 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5092 /* Configure port/vlan */
5093 ctxt.info.valid_sections |=
5094 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5095 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5096 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5097 I40E_DEFAULT_TCMAP);
5098 if (ret != I40E_SUCCESS) {
5100 "Failed to configure TC queue mapping");
5101 goto fail_msix_alloc;
5103 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5104 ctxt.info.valid_sections |=
5105 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5106 } else if (type == I40E_VSI_FDIR) {
5107 memset(&ctxt, 0, sizeof(ctxt));
5108 vsi->uplink_seid = uplink_vsi->uplink_seid;
5109 ctxt.pf_num = hw->pf_id;
5111 ctxt.uplink_seid = vsi->uplink_seid;
5112 ctxt.connection_type = 0x1; /* regular data port */
5113 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5114 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5115 I40E_DEFAULT_TCMAP);
5116 if (ret != I40E_SUCCESS) {
5118 "Failed to configure TC queue mapping.");
5119 goto fail_msix_alloc;
5121 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5122 ctxt.info.valid_sections |=
5123 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5125 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5126 goto fail_msix_alloc;
5129 if (vsi->type != I40E_VSI_MAIN) {
5130 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5131 if (ret != I40E_SUCCESS) {
5132 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5133 hw->aq.asq_last_status);
5134 goto fail_msix_alloc;
5136 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5137 vsi->info.valid_sections = 0;
5138 vsi->seid = ctxt.seid;
5139 vsi->vsi_id = ctxt.vsi_number;
5140 vsi->sib_vsi_list.vsi = vsi;
5141 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5142 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5143 &vsi->sib_vsi_list, list);
5145 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5146 &vsi->sib_vsi_list, list);
5150 /* MAC/VLAN configuration */
5151 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5152 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5154 ret = i40e_vsi_add_mac(vsi, &filter);
5155 if (ret != I40E_SUCCESS) {
5156 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5157 goto fail_msix_alloc;
5160 /* Get VSI BW information */
5161 i40e_vsi_get_bw_config(vsi);
5164 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5166 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5172 /* Configure vlan filter on or off */
5174 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5177 struct i40e_mac_filter *f;
5179 struct i40e_mac_filter_info *mac_filter;
5180 enum rte_mac_filter_type desired_filter;
5181 int ret = I40E_SUCCESS;
5184 /* Filter to match MAC and VLAN */
5185 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5187 /* Filter to match only MAC */
5188 desired_filter = RTE_MAC_PERFECT_MATCH;
5193 mac_filter = rte_zmalloc("mac_filter_info_data",
5194 num * sizeof(*mac_filter), 0);
5195 if (mac_filter == NULL) {
5196 PMD_DRV_LOG(ERR, "failed to allocate memory");
5197 return I40E_ERR_NO_MEMORY;
5202 /* Remove all existing mac */
5203 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5204 mac_filter[i] = f->mac_info;
5205 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5207 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5208 on ? "enable" : "disable");
5214 /* Override with new filter */
5215 for (i = 0; i < num; i++) {
5216 mac_filter[i].filter_type = desired_filter;
5217 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5219 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5220 on ? "enable" : "disable");
5226 rte_free(mac_filter);
5230 /* Configure vlan stripping on or off */
5232 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5234 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5235 struct i40e_vsi_context ctxt;
5237 int ret = I40E_SUCCESS;
5239 /* Check if it has been already on or off */
5240 if (vsi->info.valid_sections &
5241 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5243 if ((vsi->info.port_vlan_flags &
5244 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5245 return 0; /* already on */
5247 if ((vsi->info.port_vlan_flags &
5248 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5249 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5250 return 0; /* already off */
5255 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5257 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5258 vsi->info.valid_sections =
5259 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5260 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5261 vsi->info.port_vlan_flags |= vlan_flags;
5262 ctxt.seid = vsi->seid;
5263 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5264 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5266 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5267 on ? "enable" : "disable");
5273 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5275 struct rte_eth_dev_data *data = dev->data;
5279 /* Apply vlan offload setting */
5280 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5281 i40e_vlan_offload_set(dev, mask);
5283 /* Apply double-vlan setting, not implemented yet */
5285 /* Apply pvid setting */
5286 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5287 data->dev_conf.txmode.hw_vlan_insert_pvid);
5289 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5295 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5297 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5299 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5303 i40e_update_flow_control(struct i40e_hw *hw)
5305 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5306 struct i40e_link_status link_status;
5307 uint32_t rxfc = 0, txfc = 0, reg;
5311 memset(&link_status, 0, sizeof(link_status));
5312 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5313 if (ret != I40E_SUCCESS) {
5314 PMD_DRV_LOG(ERR, "Failed to get link status information");
5315 goto write_reg; /* Disable flow control */
5318 an_info = hw->phy.link_info.an_info;
5319 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5320 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5321 ret = I40E_ERR_NOT_READY;
5322 goto write_reg; /* Disable flow control */
5325 * If link auto negotiation is enabled, flow control needs to
5326 * be configured according to it
5328 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5329 case I40E_LINK_PAUSE_RXTX:
5332 hw->fc.current_mode = I40E_FC_FULL;
5334 case I40E_AQ_LINK_PAUSE_RX:
5336 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5338 case I40E_AQ_LINK_PAUSE_TX:
5340 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5343 hw->fc.current_mode = I40E_FC_NONE;
5348 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5349 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5350 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5351 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5352 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5353 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5360 i40e_pf_setup(struct i40e_pf *pf)
5362 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5363 struct i40e_filter_control_settings settings;
5364 struct i40e_vsi *vsi;
5367 /* Clear all stats counters */
5368 pf->offset_loaded = FALSE;
5369 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5370 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5371 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5372 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5374 ret = i40e_pf_get_switch_config(pf);
5375 if (ret != I40E_SUCCESS) {
5376 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5379 if (pf->flags & I40E_FLAG_FDIR) {
5380 /* make queue allocated first, let FDIR use queue pair 0*/
5381 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5382 if (ret != I40E_FDIR_QUEUE_ID) {
5384 "queue allocation fails for FDIR: ret =%d",
5386 pf->flags &= ~I40E_FLAG_FDIR;
5389 /* main VSI setup */
5390 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5392 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5393 return I40E_ERR_NOT_READY;
5397 /* Configure filter control */
5398 memset(&settings, 0, sizeof(settings));
5399 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5400 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5401 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5402 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5404 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5405 hw->func_caps.rss_table_size);
5406 return I40E_ERR_PARAM;
5408 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5409 hw->func_caps.rss_table_size);
5410 pf->hash_lut_size = hw->func_caps.rss_table_size;
5412 /* Enable ethtype and macvlan filters */
5413 settings.enable_ethtype = TRUE;
5414 settings.enable_macvlan = TRUE;
5415 ret = i40e_set_filter_control(hw, &settings);
5417 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5420 /* Update flow control according to the auto negotiation */
5421 i40e_update_flow_control(hw);
5423 return I40E_SUCCESS;
5427 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5433 * Set or clear TX Queue Disable flags,
5434 * which is required by hardware.
5436 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5437 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5439 /* Wait until the request is finished */
5440 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5441 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5442 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5443 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5444 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5450 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5451 return I40E_SUCCESS; /* already on, skip next steps */
5453 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5454 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5456 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5457 return I40E_SUCCESS; /* already off, skip next steps */
5458 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5460 /* Write the register */
5461 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5462 /* Check the result */
5463 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5464 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5465 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5467 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5468 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5471 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5472 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5476 /* Check if it is timeout */
5477 if (j >= I40E_CHK_Q_ENA_COUNT) {
5478 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5479 (on ? "enable" : "disable"), q_idx);
5480 return I40E_ERR_TIMEOUT;
5483 return I40E_SUCCESS;
5486 /* Swith on or off the tx queues */
5488 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5490 struct rte_eth_dev_data *dev_data = pf->dev_data;
5491 struct i40e_tx_queue *txq;
5492 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5496 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5497 txq = dev_data->tx_queues[i];
5498 /* Don't operate the queue if not configured or
5499 * if starting only per queue */
5500 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5503 ret = i40e_dev_tx_queue_start(dev, i);
5505 ret = i40e_dev_tx_queue_stop(dev, i);
5506 if ( ret != I40E_SUCCESS)
5510 return I40E_SUCCESS;
5514 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5519 /* Wait until the request is finished */
5520 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5521 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5522 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5523 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5524 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5529 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5530 return I40E_SUCCESS; /* Already on, skip next steps */
5531 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5533 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5534 return I40E_SUCCESS; /* Already off, skip next steps */
5535 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5538 /* Write the register */
5539 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5540 /* Check the result */
5541 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5542 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5543 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5545 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5546 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5549 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5550 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5555 /* Check if it is timeout */
5556 if (j >= I40E_CHK_Q_ENA_COUNT) {
5557 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5558 (on ? "enable" : "disable"), q_idx);
5559 return I40E_ERR_TIMEOUT;
5562 return I40E_SUCCESS;
5564 /* Switch on or off the rx queues */
5566 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5568 struct rte_eth_dev_data *dev_data = pf->dev_data;
5569 struct i40e_rx_queue *rxq;
5570 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5574 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5575 rxq = dev_data->rx_queues[i];
5576 /* Don't operate the queue if not configured or
5577 * if starting only per queue */
5578 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5581 ret = i40e_dev_rx_queue_start(dev, i);
5583 ret = i40e_dev_rx_queue_stop(dev, i);
5584 if (ret != I40E_SUCCESS)
5588 return I40E_SUCCESS;
5591 /* Switch on or off all the rx/tx queues */
5593 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5598 /* enable rx queues before enabling tx queues */
5599 ret = i40e_dev_switch_rx_queues(pf, on);
5601 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5604 ret = i40e_dev_switch_tx_queues(pf, on);
5606 /* Stop tx queues before stopping rx queues */
5607 ret = i40e_dev_switch_tx_queues(pf, on);
5609 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5612 ret = i40e_dev_switch_rx_queues(pf, on);
5618 /* Initialize VSI for TX */
5620 i40e_dev_tx_init(struct i40e_pf *pf)
5622 struct rte_eth_dev_data *data = pf->dev_data;
5624 uint32_t ret = I40E_SUCCESS;
5625 struct i40e_tx_queue *txq;
5627 for (i = 0; i < data->nb_tx_queues; i++) {
5628 txq = data->tx_queues[i];
5629 if (!txq || !txq->q_set)
5631 ret = i40e_tx_queue_init(txq);
5632 if (ret != I40E_SUCCESS)
5635 if (ret == I40E_SUCCESS)
5636 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5642 /* Initialize VSI for RX */
5644 i40e_dev_rx_init(struct i40e_pf *pf)
5646 struct rte_eth_dev_data *data = pf->dev_data;
5647 int ret = I40E_SUCCESS;
5649 struct i40e_rx_queue *rxq;
5651 i40e_pf_config_mq_rx(pf);
5652 for (i = 0; i < data->nb_rx_queues; i++) {
5653 rxq = data->rx_queues[i];
5654 if (!rxq || !rxq->q_set)
5657 ret = i40e_rx_queue_init(rxq);
5658 if (ret != I40E_SUCCESS) {
5660 "Failed to do RX queue initialization");
5664 if (ret == I40E_SUCCESS)
5665 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5672 i40e_dev_rxtx_init(struct i40e_pf *pf)
5676 err = i40e_dev_tx_init(pf);
5678 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5681 err = i40e_dev_rx_init(pf);
5683 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5691 i40e_vmdq_setup(struct rte_eth_dev *dev)
5693 struct rte_eth_conf *conf = &dev->data->dev_conf;
5694 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5695 int i, err, conf_vsis, j, loop;
5696 struct i40e_vsi *vsi;
5697 struct i40e_vmdq_info *vmdq_info;
5698 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5699 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5702 * Disable interrupt to avoid message from VF. Furthermore, it will
5703 * avoid race condition in VSI creation/destroy.
5705 i40e_pf_disable_irq0(hw);
5707 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5708 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5712 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5713 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5714 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5715 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5716 pf->max_nb_vmdq_vsi);
5720 if (pf->vmdq != NULL) {
5721 PMD_INIT_LOG(INFO, "VMDQ already configured");
5725 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5726 sizeof(*vmdq_info) * conf_vsis, 0);
5728 if (pf->vmdq == NULL) {
5729 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5733 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5735 /* Create VMDQ VSI */
5736 for (i = 0; i < conf_vsis; i++) {
5737 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5738 vmdq_conf->enable_loop_back);
5740 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5744 vmdq_info = &pf->vmdq[i];
5746 vmdq_info->vsi = vsi;
5748 pf->nb_cfg_vmdq_vsi = conf_vsis;
5750 /* Configure Vlan */
5751 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5752 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5753 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5754 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5755 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5756 vmdq_conf->pool_map[i].vlan_id, j);
5758 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5759 vmdq_conf->pool_map[i].vlan_id);
5761 PMD_INIT_LOG(ERR, "Failed to add vlan");
5769 i40e_pf_enable_irq0(hw);
5774 for (i = 0; i < conf_vsis; i++)
5775 if (pf->vmdq[i].vsi == NULL)
5778 i40e_vsi_release(pf->vmdq[i].vsi);
5782 i40e_pf_enable_irq0(hw);
5787 i40e_stat_update_32(struct i40e_hw *hw,
5795 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5799 if (new_data >= *offset)
5800 *stat = (uint64_t)(new_data - *offset);
5802 *stat = (uint64_t)((new_data +
5803 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5807 i40e_stat_update_48(struct i40e_hw *hw,
5816 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5817 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5818 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5823 if (new_data >= *offset)
5824 *stat = new_data - *offset;
5826 *stat = (uint64_t)((new_data +
5827 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5829 *stat &= I40E_48_BIT_MASK;
5834 i40e_pf_disable_irq0(struct i40e_hw *hw)
5836 /* Disable all interrupt types */
5837 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5838 I40E_WRITE_FLUSH(hw);
5843 i40e_pf_enable_irq0(struct i40e_hw *hw)
5845 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5846 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5847 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5848 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5849 I40E_WRITE_FLUSH(hw);
5853 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5855 /* read pending request and disable first */
5856 i40e_pf_disable_irq0(hw);
5857 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5858 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5859 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5862 /* Link no queues with irq0 */
5863 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5864 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5868 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5870 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5871 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5874 uint32_t index, offset, val;
5879 * Try to find which VF trigger a reset, use absolute VF id to access
5880 * since the reg is global register.
5882 for (i = 0; i < pf->vf_num; i++) {
5883 abs_vf_id = hw->func_caps.vf_base_id + i;
5884 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5885 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5886 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5887 /* VFR event occurred */
5888 if (val & (0x1 << offset)) {
5891 /* Clear the event first */
5892 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5894 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5896 * Only notify a VF reset event occurred,
5897 * don't trigger another SW reset
5899 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5900 if (ret != I40E_SUCCESS)
5901 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5907 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5909 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5912 for (i = 0; i < pf->vf_num; i++)
5913 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5917 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5919 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5920 struct i40e_arq_event_info info;
5921 uint16_t pending, opcode;
5924 info.buf_len = I40E_AQ_BUF_SZ;
5925 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5926 if (!info.msg_buf) {
5927 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5933 ret = i40e_clean_arq_element(hw, &info, &pending);
5935 if (ret != I40E_SUCCESS) {
5937 "Failed to read msg from AdminQ, aq_err: %u",
5938 hw->aq.asq_last_status);
5941 opcode = rte_le_to_cpu_16(info.desc.opcode);
5944 case i40e_aqc_opc_send_msg_to_pf:
5945 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5946 i40e_pf_host_handle_vf_msg(dev,
5947 rte_le_to_cpu_16(info.desc.retval),
5948 rte_le_to_cpu_32(info.desc.cookie_high),
5949 rte_le_to_cpu_32(info.desc.cookie_low),
5953 case i40e_aqc_opc_get_link_status:
5954 ret = i40e_dev_link_update(dev, 0);
5956 _rte_eth_dev_callback_process(dev,
5957 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5960 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5965 rte_free(info.msg_buf);
5969 * Interrupt handler triggered by NIC for handling
5970 * specific interrupt.
5973 * Pointer to interrupt handle.
5975 * The address of parameter (struct rte_eth_dev *) regsitered before.
5981 i40e_dev_interrupt_handler(void *param)
5983 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5984 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5987 /* Disable interrupt */
5988 i40e_pf_disable_irq0(hw);
5990 /* read out interrupt causes */
5991 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5993 /* No interrupt event indicated */
5994 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5995 PMD_DRV_LOG(INFO, "No interrupt event");
5998 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5999 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6000 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6001 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6002 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6003 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6004 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6005 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6006 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6007 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6008 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6009 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6010 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6011 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6013 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6014 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6015 i40e_dev_handle_vfr_event(dev);
6017 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6018 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6019 i40e_dev_handle_aq_msg(dev);
6023 /* Enable interrupt */
6024 i40e_pf_enable_irq0(hw);
6025 rte_intr_enable(dev->intr_handle);
6029 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6030 struct i40e_macvlan_filter *filter,
6033 int ele_num, ele_buff_size;
6034 int num, actual_num, i;
6036 int ret = I40E_SUCCESS;
6037 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6038 struct i40e_aqc_add_macvlan_element_data *req_list;
6040 if (filter == NULL || total == 0)
6041 return I40E_ERR_PARAM;
6042 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6043 ele_buff_size = hw->aq.asq_buf_size;
6045 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6046 if (req_list == NULL) {
6047 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6048 return I40E_ERR_NO_MEMORY;
6053 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6054 memset(req_list, 0, ele_buff_size);
6056 for (i = 0; i < actual_num; i++) {
6057 rte_memcpy(req_list[i].mac_addr,
6058 &filter[num + i].macaddr, ETH_ADDR_LEN);
6059 req_list[i].vlan_tag =
6060 rte_cpu_to_le_16(filter[num + i].vlan_id);
6062 switch (filter[num + i].filter_type) {
6063 case RTE_MAC_PERFECT_MATCH:
6064 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6065 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6067 case RTE_MACVLAN_PERFECT_MATCH:
6068 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6070 case RTE_MAC_HASH_MATCH:
6071 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6072 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6074 case RTE_MACVLAN_HASH_MATCH:
6075 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6078 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6079 ret = I40E_ERR_PARAM;
6083 req_list[i].queue_number = 0;
6085 req_list[i].flags = rte_cpu_to_le_16(flags);
6088 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6090 if (ret != I40E_SUCCESS) {
6091 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6095 } while (num < total);
6103 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6104 struct i40e_macvlan_filter *filter,
6107 int ele_num, ele_buff_size;
6108 int num, actual_num, i;
6110 int ret = I40E_SUCCESS;
6111 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6112 struct i40e_aqc_remove_macvlan_element_data *req_list;
6114 if (filter == NULL || total == 0)
6115 return I40E_ERR_PARAM;
6117 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6118 ele_buff_size = hw->aq.asq_buf_size;
6120 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6121 if (req_list == NULL) {
6122 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6123 return I40E_ERR_NO_MEMORY;
6128 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6129 memset(req_list, 0, ele_buff_size);
6131 for (i = 0; i < actual_num; i++) {
6132 rte_memcpy(req_list[i].mac_addr,
6133 &filter[num + i].macaddr, ETH_ADDR_LEN);
6134 req_list[i].vlan_tag =
6135 rte_cpu_to_le_16(filter[num + i].vlan_id);
6137 switch (filter[num + i].filter_type) {
6138 case RTE_MAC_PERFECT_MATCH:
6139 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6140 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6142 case RTE_MACVLAN_PERFECT_MATCH:
6143 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6145 case RTE_MAC_HASH_MATCH:
6146 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6147 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6149 case RTE_MACVLAN_HASH_MATCH:
6150 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6153 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6154 ret = I40E_ERR_PARAM;
6157 req_list[i].flags = rte_cpu_to_le_16(flags);
6160 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6162 if (ret != I40E_SUCCESS) {
6163 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6167 } while (num < total);
6174 /* Find out specific MAC filter */
6175 static struct i40e_mac_filter *
6176 i40e_find_mac_filter(struct i40e_vsi *vsi,
6177 struct ether_addr *macaddr)
6179 struct i40e_mac_filter *f;
6181 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6182 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6190 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6193 uint32_t vid_idx, vid_bit;
6195 if (vlan_id > ETH_VLAN_ID_MAX)
6198 vid_idx = I40E_VFTA_IDX(vlan_id);
6199 vid_bit = I40E_VFTA_BIT(vlan_id);
6201 if (vsi->vfta[vid_idx] & vid_bit)
6208 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6209 uint16_t vlan_id, bool on)
6211 uint32_t vid_idx, vid_bit;
6213 vid_idx = I40E_VFTA_IDX(vlan_id);
6214 vid_bit = I40E_VFTA_BIT(vlan_id);
6217 vsi->vfta[vid_idx] |= vid_bit;
6219 vsi->vfta[vid_idx] &= ~vid_bit;
6223 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6224 uint16_t vlan_id, bool on)
6226 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6227 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6230 if (vlan_id > ETH_VLAN_ID_MAX)
6233 i40e_store_vlan_filter(vsi, vlan_id, on);
6235 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6238 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6241 ret = i40e_aq_add_vlan(hw, vsi->seid,
6242 &vlan_data, 1, NULL);
6243 if (ret != I40E_SUCCESS)
6244 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6246 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6247 &vlan_data, 1, NULL);
6248 if (ret != I40E_SUCCESS)
6250 "Failed to remove vlan filter");
6255 * Find all vlan options for specific mac addr,
6256 * return with actual vlan found.
6259 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6260 struct i40e_macvlan_filter *mv_f,
6261 int num, struct ether_addr *addr)
6267 * Not to use i40e_find_vlan_filter to decrease the loop time,
6268 * although the code looks complex.
6270 if (num < vsi->vlan_num)
6271 return I40E_ERR_PARAM;
6274 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6276 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6277 if (vsi->vfta[j] & (1 << k)) {
6280 "vlan number doesn't match");
6281 return I40E_ERR_PARAM;
6283 rte_memcpy(&mv_f[i].macaddr,
6284 addr, ETH_ADDR_LEN);
6286 j * I40E_UINT32_BIT_SIZE + k;
6292 return I40E_SUCCESS;
6296 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6297 struct i40e_macvlan_filter *mv_f,
6302 struct i40e_mac_filter *f;
6304 if (num < vsi->mac_num)
6305 return I40E_ERR_PARAM;
6307 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6309 PMD_DRV_LOG(ERR, "buffer number not match");
6310 return I40E_ERR_PARAM;
6312 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6314 mv_f[i].vlan_id = vlan;
6315 mv_f[i].filter_type = f->mac_info.filter_type;
6319 return I40E_SUCCESS;
6323 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6326 struct i40e_mac_filter *f;
6327 struct i40e_macvlan_filter *mv_f;
6328 int ret = I40E_SUCCESS;
6330 if (vsi == NULL || vsi->mac_num == 0)
6331 return I40E_ERR_PARAM;
6333 /* Case that no vlan is set */
6334 if (vsi->vlan_num == 0)
6337 num = vsi->mac_num * vsi->vlan_num;
6339 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6341 PMD_DRV_LOG(ERR, "failed to allocate memory");
6342 return I40E_ERR_NO_MEMORY;
6346 if (vsi->vlan_num == 0) {
6347 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6348 rte_memcpy(&mv_f[i].macaddr,
6349 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6350 mv_f[i].filter_type = f->mac_info.filter_type;
6351 mv_f[i].vlan_id = 0;
6355 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6356 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6357 vsi->vlan_num, &f->mac_info.mac_addr);
6358 if (ret != I40E_SUCCESS)
6360 for (j = i; j < i + vsi->vlan_num; j++)
6361 mv_f[j].filter_type = f->mac_info.filter_type;
6366 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6374 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6376 struct i40e_macvlan_filter *mv_f;
6378 int ret = I40E_SUCCESS;
6380 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6381 return I40E_ERR_PARAM;
6383 /* If it's already set, just return */
6384 if (i40e_find_vlan_filter(vsi,vlan))
6385 return I40E_SUCCESS;
6387 mac_num = vsi->mac_num;
6390 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6391 return I40E_ERR_PARAM;
6394 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6397 PMD_DRV_LOG(ERR, "failed to allocate memory");
6398 return I40E_ERR_NO_MEMORY;
6401 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6403 if (ret != I40E_SUCCESS)
6406 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6408 if (ret != I40E_SUCCESS)
6411 i40e_set_vlan_filter(vsi, vlan, 1);
6421 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6423 struct i40e_macvlan_filter *mv_f;
6425 int ret = I40E_SUCCESS;
6428 * Vlan 0 is the generic filter for untagged packets
6429 * and can't be removed.
6431 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6432 return I40E_ERR_PARAM;
6434 /* If can't find it, just return */
6435 if (!i40e_find_vlan_filter(vsi, vlan))
6436 return I40E_ERR_PARAM;
6438 mac_num = vsi->mac_num;
6441 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6442 return I40E_ERR_PARAM;
6445 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6448 PMD_DRV_LOG(ERR, "failed to allocate memory");
6449 return I40E_ERR_NO_MEMORY;
6452 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6454 if (ret != I40E_SUCCESS)
6457 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6459 if (ret != I40E_SUCCESS)
6462 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6463 if (vsi->vlan_num == 1) {
6464 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6465 if (ret != I40E_SUCCESS)
6468 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6469 if (ret != I40E_SUCCESS)
6473 i40e_set_vlan_filter(vsi, vlan, 0);
6483 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6485 struct i40e_mac_filter *f;
6486 struct i40e_macvlan_filter *mv_f;
6487 int i, vlan_num = 0;
6488 int ret = I40E_SUCCESS;
6490 /* If it's add and we've config it, return */
6491 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6493 return I40E_SUCCESS;
6494 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6495 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6498 * If vlan_num is 0, that's the first time to add mac,
6499 * set mask for vlan_id 0.
6501 if (vsi->vlan_num == 0) {
6502 i40e_set_vlan_filter(vsi, 0, 1);
6505 vlan_num = vsi->vlan_num;
6506 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6507 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6510 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6512 PMD_DRV_LOG(ERR, "failed to allocate memory");
6513 return I40E_ERR_NO_MEMORY;
6516 for (i = 0; i < vlan_num; i++) {
6517 mv_f[i].filter_type = mac_filter->filter_type;
6518 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6522 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6523 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6524 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6525 &mac_filter->mac_addr);
6526 if (ret != I40E_SUCCESS)
6530 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6531 if (ret != I40E_SUCCESS)
6534 /* Add the mac addr into mac list */
6535 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6537 PMD_DRV_LOG(ERR, "failed to allocate memory");
6538 ret = I40E_ERR_NO_MEMORY;
6541 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6543 f->mac_info.filter_type = mac_filter->filter_type;
6544 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6555 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6557 struct i40e_mac_filter *f;
6558 struct i40e_macvlan_filter *mv_f;
6560 enum rte_mac_filter_type filter_type;
6561 int ret = I40E_SUCCESS;
6563 /* Can't find it, return an error */
6564 f = i40e_find_mac_filter(vsi, addr);
6566 return I40E_ERR_PARAM;
6568 vlan_num = vsi->vlan_num;
6569 filter_type = f->mac_info.filter_type;
6570 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6571 filter_type == RTE_MACVLAN_HASH_MATCH) {
6572 if (vlan_num == 0) {
6573 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6574 return I40E_ERR_PARAM;
6576 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6577 filter_type == RTE_MAC_HASH_MATCH)
6580 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6582 PMD_DRV_LOG(ERR, "failed to allocate memory");
6583 return I40E_ERR_NO_MEMORY;
6586 for (i = 0; i < vlan_num; i++) {
6587 mv_f[i].filter_type = filter_type;
6588 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6591 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6592 filter_type == RTE_MACVLAN_HASH_MATCH) {
6593 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6594 if (ret != I40E_SUCCESS)
6598 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6599 if (ret != I40E_SUCCESS)
6602 /* Remove the mac addr into mac list */
6603 TAILQ_REMOVE(&vsi->mac_list, f, next);
6613 /* Configure hash enable flags for RSS */
6615 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6623 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6624 if (flags & (1ULL << i))
6625 hena |= adapter->pctypes_tbl[i];
6631 /* Parse the hash enable flags */
6633 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6635 uint64_t rss_hf = 0;
6641 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6642 if (flags & adapter->pctypes_tbl[i])
6643 rss_hf |= (1ULL << i);
6650 i40e_pf_disable_rss(struct i40e_pf *pf)
6652 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6654 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6655 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6656 I40E_WRITE_FLUSH(hw);
6660 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6662 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6663 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6666 if (!key || key_len == 0) {
6667 PMD_DRV_LOG(DEBUG, "No key to be configured");
6669 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6671 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6675 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6676 struct i40e_aqc_get_set_rss_key_data *key_dw =
6677 (struct i40e_aqc_get_set_rss_key_data *)key;
6679 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6681 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6683 uint32_t *hash_key = (uint32_t *)key;
6686 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6687 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6688 I40E_WRITE_FLUSH(hw);
6695 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6697 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6698 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6701 if (!key || !key_len)
6704 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6705 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6706 (struct i40e_aqc_get_set_rss_key_data *)key);
6708 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6712 uint32_t *key_dw = (uint32_t *)key;
6715 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6716 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6718 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6724 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6726 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6730 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6731 rss_conf->rss_key_len);
6735 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6736 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6737 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6738 I40E_WRITE_FLUSH(hw);
6744 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6745 struct rte_eth_rss_conf *rss_conf)
6747 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6748 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6749 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6752 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6753 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6755 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6756 if (rss_hf != 0) /* Enable RSS */
6758 return 0; /* Nothing to do */
6761 if (rss_hf == 0) /* Disable RSS */
6764 return i40e_hw_rss_hash_set(pf, rss_conf);
6768 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6769 struct rte_eth_rss_conf *rss_conf)
6771 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6772 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6775 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6776 &rss_conf->rss_key_len);
6778 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6779 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6780 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6786 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6788 switch (filter_type) {
6789 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6790 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6792 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6793 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6795 case RTE_TUNNEL_FILTER_IMAC_TENID:
6796 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6798 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6799 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6801 case ETH_TUNNEL_FILTER_IMAC:
6802 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6804 case ETH_TUNNEL_FILTER_OIP:
6805 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6807 case ETH_TUNNEL_FILTER_IIP:
6808 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6811 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6818 /* Convert tunnel filter structure */
6820 i40e_tunnel_filter_convert(
6821 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6822 struct i40e_tunnel_filter *tunnel_filter)
6824 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6825 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6826 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6827 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6828 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6829 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6830 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6831 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6832 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6834 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6835 tunnel_filter->input.flags = cld_filter->element.flags;
6836 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6837 tunnel_filter->queue = cld_filter->element.queue_number;
6838 rte_memcpy(tunnel_filter->input.general_fields,
6839 cld_filter->general_fields,
6840 sizeof(cld_filter->general_fields));
6845 /* Check if there exists the tunnel filter */
6846 struct i40e_tunnel_filter *
6847 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6848 const struct i40e_tunnel_filter_input *input)
6852 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6856 return tunnel_rule->hash_map[ret];
6859 /* Add a tunnel filter into the SW list */
6861 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6862 struct i40e_tunnel_filter *tunnel_filter)
6864 struct i40e_tunnel_rule *rule = &pf->tunnel;
6867 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6870 "Failed to insert tunnel filter to hash table %d!",
6874 rule->hash_map[ret] = tunnel_filter;
6876 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6881 /* Delete a tunnel filter from the SW list */
6883 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6884 struct i40e_tunnel_filter_input *input)
6886 struct i40e_tunnel_rule *rule = &pf->tunnel;
6887 struct i40e_tunnel_filter *tunnel_filter;
6890 ret = rte_hash_del_key(rule->hash_table, input);
6893 "Failed to delete tunnel filter to hash table %d!",
6897 tunnel_filter = rule->hash_map[ret];
6898 rule->hash_map[ret] = NULL;
6900 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6901 rte_free(tunnel_filter);
6907 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6908 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6913 uint8_t i, tun_type = 0;
6914 /* internal varialbe to convert ipv6 byte order */
6915 uint32_t convert_ipv6[4];
6917 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6918 struct i40e_vsi *vsi = pf->main_vsi;
6919 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6920 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6921 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6922 struct i40e_tunnel_filter *tunnel, *node;
6923 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6925 cld_filter = rte_zmalloc("tunnel_filter",
6926 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6929 if (NULL == cld_filter) {
6930 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6933 pfilter = cld_filter;
6935 ether_addr_copy(&tunnel_filter->outer_mac,
6936 (struct ether_addr *)&pfilter->element.outer_mac);
6937 ether_addr_copy(&tunnel_filter->inner_mac,
6938 (struct ether_addr *)&pfilter->element.inner_mac);
6940 pfilter->element.inner_vlan =
6941 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6942 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6943 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6944 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6945 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6946 &rte_cpu_to_le_32(ipv4_addr),
6947 sizeof(pfilter->element.ipaddr.v4.data));
6949 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6950 for (i = 0; i < 4; i++) {
6952 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6954 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6956 sizeof(pfilter->element.ipaddr.v6.data));
6959 /* check tunneled type */
6960 switch (tunnel_filter->tunnel_type) {
6961 case RTE_TUNNEL_TYPE_VXLAN:
6962 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6964 case RTE_TUNNEL_TYPE_NVGRE:
6965 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6967 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6968 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6971 /* Other tunnel types is not supported. */
6972 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6973 rte_free(cld_filter);
6977 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6978 &pfilter->element.flags);
6980 rte_free(cld_filter);
6984 pfilter->element.flags |= rte_cpu_to_le_16(
6985 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6986 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6987 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6988 pfilter->element.queue_number =
6989 rte_cpu_to_le_16(tunnel_filter->queue_id);
6991 /* Check if there is the filter in SW list */
6992 memset(&check_filter, 0, sizeof(check_filter));
6993 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6994 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6996 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7000 if (!add && !node) {
7001 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7006 ret = i40e_aq_add_cloud_filters(hw,
7007 vsi->seid, &cld_filter->element, 1);
7009 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7012 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7013 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7014 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7016 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7017 &cld_filter->element, 1);
7019 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7022 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7025 rte_free(cld_filter);
7029 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7030 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7031 #define I40E_TR_GENEVE_KEY_MASK 0x8
7032 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7033 #define I40E_TR_GRE_KEY_MASK 0x400
7034 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7035 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7038 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7040 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7041 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7042 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7043 enum i40e_status_code status = I40E_SUCCESS;
7045 memset(&filter_replace, 0,
7046 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7047 memset(&filter_replace_buf, 0,
7048 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7050 /* create L1 filter */
7051 filter_replace.old_filter_type =
7052 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7053 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7054 filter_replace.tr_bit = 0;
7056 /* Prepare the buffer, 3 entries */
7057 filter_replace_buf.data[0] =
7058 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7059 filter_replace_buf.data[0] |=
7060 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7061 filter_replace_buf.data[2] = 0xFF;
7062 filter_replace_buf.data[3] = 0xFF;
7063 filter_replace_buf.data[4] =
7064 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7065 filter_replace_buf.data[4] |=
7066 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7067 filter_replace_buf.data[7] = 0xF0;
7068 filter_replace_buf.data[8]
7069 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7070 filter_replace_buf.data[8] |=
7071 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7072 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7073 I40E_TR_GENEVE_KEY_MASK |
7074 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7075 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7076 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7077 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7079 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7080 &filter_replace_buf);
7085 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7087 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7088 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7089 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7090 enum i40e_status_code status = I40E_SUCCESS;
7093 memset(&filter_replace, 0,
7094 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7095 memset(&filter_replace_buf, 0,
7096 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7097 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7098 I40E_AQC_MIRROR_CLOUD_FILTER;
7099 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7100 filter_replace.new_filter_type =
7101 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7102 /* Prepare the buffer, 2 entries */
7103 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7104 filter_replace_buf.data[0] |=
7105 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7106 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7107 filter_replace_buf.data[4] |=
7108 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7109 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7110 &filter_replace_buf);
7115 memset(&filter_replace, 0,
7116 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7117 memset(&filter_replace_buf, 0,
7118 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7120 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7121 I40E_AQC_MIRROR_CLOUD_FILTER;
7122 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7123 filter_replace.new_filter_type =
7124 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7125 /* Prepare the buffer, 2 entries */
7126 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7127 filter_replace_buf.data[0] |=
7128 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7129 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7130 filter_replace_buf.data[4] |=
7131 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7133 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7134 &filter_replace_buf);
7139 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7140 struct i40e_tunnel_filter_conf *tunnel_filter,
7145 uint8_t i, tun_type = 0;
7146 /* internal variable to convert ipv6 byte order */
7147 uint32_t convert_ipv6[4];
7149 struct i40e_pf_vf *vf = NULL;
7150 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7151 struct i40e_vsi *vsi;
7152 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7153 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7154 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7155 struct i40e_tunnel_filter *tunnel, *node;
7156 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7158 bool big_buffer = 0;
7160 cld_filter = rte_zmalloc("tunnel_filter",
7161 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7164 if (cld_filter == NULL) {
7165 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7168 pfilter = cld_filter;
7170 ether_addr_copy(&tunnel_filter->outer_mac,
7171 (struct ether_addr *)&pfilter->element.outer_mac);
7172 ether_addr_copy(&tunnel_filter->inner_mac,
7173 (struct ether_addr *)&pfilter->element.inner_mac);
7175 pfilter->element.inner_vlan =
7176 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7177 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7178 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7179 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7180 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7181 &rte_cpu_to_le_32(ipv4_addr),
7182 sizeof(pfilter->element.ipaddr.v4.data));
7184 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7185 for (i = 0; i < 4; i++) {
7187 rte_cpu_to_le_32(rte_be_to_cpu_32(
7188 tunnel_filter->ip_addr.ipv6_addr[i]));
7190 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7192 sizeof(pfilter->element.ipaddr.v6.data));
7195 /* check tunneled type */
7196 switch (tunnel_filter->tunnel_type) {
7197 case I40E_TUNNEL_TYPE_VXLAN:
7198 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7200 case I40E_TUNNEL_TYPE_NVGRE:
7201 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7203 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7204 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7206 case I40E_TUNNEL_TYPE_MPLSoUDP:
7207 if (!pf->mpls_replace_flag) {
7208 i40e_replace_mpls_l1_filter(pf);
7209 i40e_replace_mpls_cloud_filter(pf);
7210 pf->mpls_replace_flag = 1;
7212 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7213 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7215 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7216 (teid_le & 0xF) << 12;
7217 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7220 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7222 case I40E_TUNNEL_TYPE_MPLSoGRE:
7223 if (!pf->mpls_replace_flag) {
7224 i40e_replace_mpls_l1_filter(pf);
7225 i40e_replace_mpls_cloud_filter(pf);
7226 pf->mpls_replace_flag = 1;
7228 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7229 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7231 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7232 (teid_le & 0xF) << 12;
7233 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7236 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7238 case I40E_TUNNEL_TYPE_QINQ:
7239 if (!pf->qinq_replace_flag) {
7240 ret = i40e_cloud_filter_qinq_create(pf);
7243 "QinQ tunnel filter already created.");
7244 pf->qinq_replace_flag = 1;
7246 /* Add in the General fields the values of
7247 * the Outer and Inner VLAN
7248 * Big Buffer should be set, see changes in
7249 * i40e_aq_add_cloud_filters
7251 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7252 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7256 /* Other tunnel types is not supported. */
7257 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7258 rte_free(cld_filter);
7262 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7263 pfilter->element.flags =
7264 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7265 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7266 pfilter->element.flags =
7267 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7268 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7269 pfilter->element.flags |=
7270 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7272 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7273 &pfilter->element.flags);
7275 rte_free(cld_filter);
7280 pfilter->element.flags |= rte_cpu_to_le_16(
7281 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7282 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7283 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7284 pfilter->element.queue_number =
7285 rte_cpu_to_le_16(tunnel_filter->queue_id);
7287 if (!tunnel_filter->is_to_vf)
7290 if (tunnel_filter->vf_id >= pf->vf_num) {
7291 PMD_DRV_LOG(ERR, "Invalid argument.");
7294 vf = &pf->vfs[tunnel_filter->vf_id];
7298 /* Check if there is the filter in SW list */
7299 memset(&check_filter, 0, sizeof(check_filter));
7300 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7301 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7302 check_filter.vf_id = tunnel_filter->vf_id;
7303 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7305 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7309 if (!add && !node) {
7310 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7316 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7317 vsi->seid, cld_filter, 1);
7319 ret = i40e_aq_add_cloud_filters(hw,
7320 vsi->seid, &cld_filter->element, 1);
7322 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7325 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7326 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7327 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7330 ret = i40e_aq_remove_cloud_filters_big_buffer(
7331 hw, vsi->seid, cld_filter, 1);
7333 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7334 &cld_filter->element, 1);
7336 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7339 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7342 rte_free(cld_filter);
7347 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7351 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7352 if (pf->vxlan_ports[i] == port)
7360 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7364 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7366 idx = i40e_get_vxlan_port_idx(pf, port);
7368 /* Check if port already exists */
7370 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7374 /* Now check if there is space to add the new port */
7375 idx = i40e_get_vxlan_port_idx(pf, 0);
7378 "Maximum number of UDP ports reached, not adding port %d",
7383 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7386 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7390 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7393 /* New port: add it and mark its index in the bitmap */
7394 pf->vxlan_ports[idx] = port;
7395 pf->vxlan_bitmap |= (1 << idx);
7397 if (!(pf->flags & I40E_FLAG_VXLAN))
7398 pf->flags |= I40E_FLAG_VXLAN;
7404 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7407 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7409 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7410 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7414 idx = i40e_get_vxlan_port_idx(pf, port);
7417 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7421 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7422 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7426 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7429 pf->vxlan_ports[idx] = 0;
7430 pf->vxlan_bitmap &= ~(1 << idx);
7432 if (!pf->vxlan_bitmap)
7433 pf->flags &= ~I40E_FLAG_VXLAN;
7438 /* Add UDP tunneling port */
7440 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7441 struct rte_eth_udp_tunnel *udp_tunnel)
7444 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7446 if (udp_tunnel == NULL)
7449 switch (udp_tunnel->prot_type) {
7450 case RTE_TUNNEL_TYPE_VXLAN:
7451 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7454 case RTE_TUNNEL_TYPE_GENEVE:
7455 case RTE_TUNNEL_TYPE_TEREDO:
7456 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7461 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7469 /* Remove UDP tunneling port */
7471 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7472 struct rte_eth_udp_tunnel *udp_tunnel)
7475 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7477 if (udp_tunnel == NULL)
7480 switch (udp_tunnel->prot_type) {
7481 case RTE_TUNNEL_TYPE_VXLAN:
7482 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7484 case RTE_TUNNEL_TYPE_GENEVE:
7485 case RTE_TUNNEL_TYPE_TEREDO:
7486 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7490 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7498 /* Calculate the maximum number of contiguous PF queues that are configured */
7500 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7502 struct rte_eth_dev_data *data = pf->dev_data;
7504 struct i40e_rx_queue *rxq;
7507 for (i = 0; i < pf->lan_nb_qps; i++) {
7508 rxq = data->rx_queues[i];
7509 if (rxq && rxq->q_set)
7520 i40e_pf_config_rss(struct i40e_pf *pf)
7522 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7523 struct rte_eth_rss_conf rss_conf;
7524 uint32_t i, lut = 0;
7528 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7529 * It's necessary to calculate the actual PF queues that are configured.
7531 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7532 num = i40e_pf_calc_configured_queues_num(pf);
7534 num = pf->dev_data->nb_rx_queues;
7536 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7537 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7541 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7545 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7548 lut = (lut << 8) | (j & ((0x1 <<
7549 hw->func_caps.rss_table_entry_width) - 1));
7551 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7554 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7555 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7556 i40e_pf_disable_rss(pf);
7559 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7560 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7561 /* Random default keys */
7562 static uint32_t rss_key_default[] = {0x6b793944,
7563 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7564 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7565 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7567 rss_conf.rss_key = (uint8_t *)rss_key_default;
7568 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7572 return i40e_hw_rss_hash_set(pf, &rss_conf);
7576 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7577 struct rte_eth_tunnel_filter_conf *filter)
7579 if (pf == NULL || filter == NULL) {
7580 PMD_DRV_LOG(ERR, "Invalid parameter");
7584 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7585 PMD_DRV_LOG(ERR, "Invalid queue ID");
7589 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7590 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7594 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7595 (is_zero_ether_addr(&filter->outer_mac))) {
7596 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7600 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7601 (is_zero_ether_addr(&filter->inner_mac))) {
7602 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7609 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7610 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7612 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7617 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7618 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7621 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7622 } else if (len == 4) {
7623 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7625 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7630 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7637 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7638 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7644 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7651 switch (cfg->cfg_type) {
7652 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7653 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7656 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7664 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7665 enum rte_filter_op filter_op,
7668 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7669 int ret = I40E_ERR_PARAM;
7671 switch (filter_op) {
7672 case RTE_ETH_FILTER_SET:
7673 ret = i40e_dev_global_config_set(hw,
7674 (struct rte_eth_global_cfg *)arg);
7677 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7685 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7686 enum rte_filter_op filter_op,
7689 struct rte_eth_tunnel_filter_conf *filter;
7690 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7691 int ret = I40E_SUCCESS;
7693 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7695 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7696 return I40E_ERR_PARAM;
7698 switch (filter_op) {
7699 case RTE_ETH_FILTER_NOP:
7700 if (!(pf->flags & I40E_FLAG_VXLAN))
7701 ret = I40E_NOT_SUPPORTED;
7703 case RTE_ETH_FILTER_ADD:
7704 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7706 case RTE_ETH_FILTER_DELETE:
7707 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7710 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7711 ret = I40E_ERR_PARAM;
7719 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7722 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7725 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7726 ret = i40e_pf_config_rss(pf);
7728 i40e_pf_disable_rss(pf);
7733 /* Get the symmetric hash enable configurations per port */
7735 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7737 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7739 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7742 /* Set the symmetric hash enable configurations per port */
7744 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7746 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7749 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7751 "Symmetric hash has already been enabled");
7754 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7756 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7758 "Symmetric hash has already been disabled");
7761 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7763 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7764 I40E_WRITE_FLUSH(hw);
7768 * Get global configurations of hash function type and symmetric hash enable
7769 * per flow type (pctype). Note that global configuration means it affects all
7770 * the ports on the same NIC.
7773 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7774 struct rte_eth_hash_global_conf *g_cfg)
7776 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7780 memset(g_cfg, 0, sizeof(*g_cfg));
7781 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7782 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7783 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7785 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7786 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7787 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7790 * We work only with lowest 32 bits which is not correct, but to work
7791 * properly the valid_bit_mask size should be increased up to 64 bits
7792 * and this will brake ABI. This modification will be done in next
7795 g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
7797 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
7798 if (!adapter->pctypes_tbl[i])
7800 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7801 j < I40E_FILTER_PCTYPE_MAX; j++) {
7802 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
7803 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
7804 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
7805 g_cfg->sym_hash_enable_mask[0] |=
7816 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
7817 const struct rte_eth_hash_global_conf *g_cfg)
7820 uint32_t mask0, i40e_mask = adapter->flow_types_mask;
7822 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7823 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7824 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7825 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7831 * As i40e supports less than 32 flow types, only first 32 bits need to
7834 mask0 = g_cfg->valid_bit_mask[0];
7835 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7837 /* Check if any unsupported flow type configured */
7838 if ((mask0 | i40e_mask) ^ i40e_mask)
7841 if (g_cfg->valid_bit_mask[i])
7849 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7855 * Set global configurations of hash function type and symmetric hash enable
7856 * per flow type (pctype). Note any modifying global configuration will affect
7857 * all the ports on the same NIC.
7860 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7861 struct rte_eth_hash_global_conf *g_cfg)
7863 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7868 * We work only with lowest 32 bits which is not correct, but to work
7869 * properly the valid_bit_mask size should be increased up to 64 bits
7870 * and this will brake ABI. This modification will be done in next
7873 uint32_t mask0 = g_cfg->valid_bit_mask[0] &
7874 (uint32_t)adapter->flow_types_mask;
7876 /* Check the input parameters */
7877 ret = i40e_hash_global_config_check(adapter, g_cfg);
7881 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
7882 if (mask0 & (1UL << i)) {
7883 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7884 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7886 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7887 j < I40E_FILTER_PCTYPE_MAX; j++) {
7888 if (adapter->pctypes_tbl[i] & (1ULL << j))
7889 i40e_write_rx_ctl(hw,
7896 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7897 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7899 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7901 "Hash function already set to Toeplitz");
7904 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7905 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7907 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7909 "Hash function already set to Simple XOR");
7912 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7914 /* Use the default, and keep it as it is */
7917 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7920 I40E_WRITE_FLUSH(hw);
7926 * Valid input sets for hash and flow director filters per PCTYPE
7929 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7930 enum rte_filter_type filter)
7934 static const uint64_t valid_hash_inset_table[] = {
7935 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7936 I40E_INSET_DMAC | I40E_INSET_SMAC |
7937 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7938 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7939 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7940 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7941 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7942 I40E_INSET_FLEX_PAYLOAD,
7943 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7944 I40E_INSET_DMAC | I40E_INSET_SMAC |
7945 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7946 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7947 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7948 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7949 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7950 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7951 I40E_INSET_FLEX_PAYLOAD,
7952 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7953 I40E_INSET_DMAC | I40E_INSET_SMAC |
7954 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7955 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7956 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7957 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7958 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7959 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7960 I40E_INSET_FLEX_PAYLOAD,
7961 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7962 I40E_INSET_DMAC | I40E_INSET_SMAC |
7963 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7964 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7965 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7966 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7967 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7968 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7969 I40E_INSET_FLEX_PAYLOAD,
7970 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7971 I40E_INSET_DMAC | I40E_INSET_SMAC |
7972 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7973 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7974 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7975 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7976 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7977 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7978 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7979 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7980 I40E_INSET_DMAC | I40E_INSET_SMAC |
7981 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7982 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7983 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7984 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7985 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7986 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7987 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7988 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7989 I40E_INSET_DMAC | I40E_INSET_SMAC |
7990 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7991 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7992 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7993 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7994 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7995 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7996 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7997 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7998 I40E_INSET_DMAC | I40E_INSET_SMAC |
7999 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8000 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8001 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8002 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8003 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8004 I40E_INSET_FLEX_PAYLOAD,
8005 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8006 I40E_INSET_DMAC | I40E_INSET_SMAC |
8007 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8008 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8009 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8010 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8011 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8012 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8013 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8014 I40E_INSET_DMAC | I40E_INSET_SMAC |
8015 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8016 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8017 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8018 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8019 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8020 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8021 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8022 I40E_INSET_DMAC | I40E_INSET_SMAC |
8023 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8024 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8025 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8026 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8027 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8028 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8029 I40E_INSET_FLEX_PAYLOAD,
8030 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8031 I40E_INSET_DMAC | I40E_INSET_SMAC |
8032 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8033 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8034 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8035 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8036 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8037 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8038 I40E_INSET_FLEX_PAYLOAD,
8039 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8040 I40E_INSET_DMAC | I40E_INSET_SMAC |
8041 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8042 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8043 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8044 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8045 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8046 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8047 I40E_INSET_FLEX_PAYLOAD,
8048 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8049 I40E_INSET_DMAC | I40E_INSET_SMAC |
8050 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8051 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8052 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8053 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8054 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8055 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8056 I40E_INSET_FLEX_PAYLOAD,
8057 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8058 I40E_INSET_DMAC | I40E_INSET_SMAC |
8059 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8060 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8061 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8062 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8063 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8064 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8065 I40E_INSET_FLEX_PAYLOAD,
8066 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8067 I40E_INSET_DMAC | I40E_INSET_SMAC |
8068 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8069 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8070 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8071 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8072 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8073 I40E_INSET_FLEX_PAYLOAD,
8074 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8075 I40E_INSET_DMAC | I40E_INSET_SMAC |
8076 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8077 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8078 I40E_INSET_FLEX_PAYLOAD,
8082 * Flow director supports only fields defined in
8083 * union rte_eth_fdir_flow.
8085 static const uint64_t valid_fdir_inset_table[] = {
8086 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8087 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8088 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8089 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8090 I40E_INSET_IPV4_TTL,
8091 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8092 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8093 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8094 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8095 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8096 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8097 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8098 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8099 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8100 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8101 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8102 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8103 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8104 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8105 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8106 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8107 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8108 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8109 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8110 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8111 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8112 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8113 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8114 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8115 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8116 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8117 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8118 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8119 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8120 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8122 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8123 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8124 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8125 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8126 I40E_INSET_IPV4_TTL,
8127 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8128 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8129 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8130 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8131 I40E_INSET_IPV6_HOP_LIMIT,
8132 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8133 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8134 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8135 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8136 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8137 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8138 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8139 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8140 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8141 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8142 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8143 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8144 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8145 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8146 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8147 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8148 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8149 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8150 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8151 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8152 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8153 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8154 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8155 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8156 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8157 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8158 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8159 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8160 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8161 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8163 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8164 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8165 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8166 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8167 I40E_INSET_IPV6_HOP_LIMIT,
8168 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8169 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8170 I40E_INSET_LAST_ETHER_TYPE,
8173 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8175 if (filter == RTE_ETH_FILTER_HASH)
8176 valid = valid_hash_inset_table[pctype];
8178 valid = valid_fdir_inset_table[pctype];
8184 * Validate if the input set is allowed for a specific PCTYPE
8187 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8188 enum rte_filter_type filter, uint64_t inset)
8192 valid = i40e_get_valid_input_set(pctype, filter);
8193 if (inset & (~valid))
8199 /* default input set fields combination per pctype */
8201 i40e_get_default_input_set(uint16_t pctype)
8203 static const uint64_t default_inset_table[] = {
8204 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8205 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8206 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8207 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8208 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8209 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8210 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8211 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8212 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8213 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8214 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8215 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8216 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8217 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8218 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8219 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8220 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8221 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8222 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8223 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8225 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8226 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8227 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8228 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8229 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8230 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8231 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8232 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8233 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8234 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8235 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8236 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8237 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8238 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8239 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8240 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8241 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8242 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8243 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8244 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8245 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8246 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8248 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8249 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8250 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8251 I40E_INSET_LAST_ETHER_TYPE,
8254 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8257 return default_inset_table[pctype];
8261 * Parse the input set from index to logical bit masks
8264 i40e_parse_input_set(uint64_t *inset,
8265 enum i40e_filter_pctype pctype,
8266 enum rte_eth_input_set_field *field,
8272 static const struct {
8273 enum rte_eth_input_set_field field;
8275 } inset_convert_table[] = {
8276 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8277 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8278 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8279 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8280 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8281 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8282 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8283 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8284 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8285 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8286 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8287 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8288 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8289 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8290 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8291 I40E_INSET_IPV6_NEXT_HDR},
8292 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8293 I40E_INSET_IPV6_HOP_LIMIT},
8294 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8295 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8296 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8297 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8298 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8299 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8300 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8301 I40E_INSET_SCTP_VT},
8302 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8303 I40E_INSET_TUNNEL_DMAC},
8304 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8305 I40E_INSET_VLAN_TUNNEL},
8306 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8307 I40E_INSET_TUNNEL_ID},
8308 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8309 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8310 I40E_INSET_FLEX_PAYLOAD_W1},
8311 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8312 I40E_INSET_FLEX_PAYLOAD_W2},
8313 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8314 I40E_INSET_FLEX_PAYLOAD_W3},
8315 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8316 I40E_INSET_FLEX_PAYLOAD_W4},
8317 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8318 I40E_INSET_FLEX_PAYLOAD_W5},
8319 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8320 I40E_INSET_FLEX_PAYLOAD_W6},
8321 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8322 I40E_INSET_FLEX_PAYLOAD_W7},
8323 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8324 I40E_INSET_FLEX_PAYLOAD_W8},
8327 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8330 /* Only one item allowed for default or all */
8332 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8333 *inset = i40e_get_default_input_set(pctype);
8335 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8336 *inset = I40E_INSET_NONE;
8341 for (i = 0, *inset = 0; i < size; i++) {
8342 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8343 if (field[i] == inset_convert_table[j].field) {
8344 *inset |= inset_convert_table[j].inset;
8349 /* It contains unsupported input set, return immediately */
8350 if (j == RTE_DIM(inset_convert_table))
8358 * Translate the input set from bit masks to register aware bit masks
8362 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8372 static const struct inset_map inset_map_common[] = {
8373 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8374 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8375 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8376 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8377 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8378 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8379 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8380 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8381 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8382 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8383 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8384 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8385 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8386 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8387 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8388 {I40E_INSET_TUNNEL_DMAC,
8389 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8390 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8391 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8392 {I40E_INSET_TUNNEL_SRC_PORT,
8393 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8394 {I40E_INSET_TUNNEL_DST_PORT,
8395 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8396 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8397 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8398 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8399 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8400 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8401 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8402 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8403 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8404 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8407 /* some different registers map in x722*/
8408 static const struct inset_map inset_map_diff_x722[] = {
8409 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8410 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8411 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8412 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8415 static const struct inset_map inset_map_diff_not_x722[] = {
8416 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8417 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8418 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8419 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8425 /* Translate input set to register aware inset */
8426 if (type == I40E_MAC_X722) {
8427 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8428 if (input & inset_map_diff_x722[i].inset)
8429 val |= inset_map_diff_x722[i].inset_reg;
8432 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8433 if (input & inset_map_diff_not_x722[i].inset)
8434 val |= inset_map_diff_not_x722[i].inset_reg;
8438 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8439 if (input & inset_map_common[i].inset)
8440 val |= inset_map_common[i].inset_reg;
8447 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8450 uint64_t inset_need_mask = inset;
8452 static const struct {
8455 } inset_mask_map[] = {
8456 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8457 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8458 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8459 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8460 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8461 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8462 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8463 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8466 if (!inset || !mask || !nb_elem)
8469 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8470 /* Clear the inset bit, if no MASK is required,
8471 * for example proto + ttl
8473 if ((inset & inset_mask_map[i].inset) ==
8474 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8475 inset_need_mask &= ~inset_mask_map[i].inset;
8476 if (!inset_need_mask)
8479 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8480 if ((inset_need_mask & inset_mask_map[i].inset) ==
8481 inset_mask_map[i].inset) {
8482 if (idx >= nb_elem) {
8483 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8486 mask[idx] = inset_mask_map[i].mask;
8495 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8497 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8499 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8501 i40e_write_rx_ctl(hw, addr, val);
8502 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8503 (uint32_t)i40e_read_rx_ctl(hw, addr));
8507 i40e_filter_input_set_init(struct i40e_pf *pf)
8509 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8510 enum i40e_filter_pctype pctype;
8511 uint64_t input_set, inset_reg;
8512 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8516 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8517 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8518 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8520 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8523 input_set = i40e_get_default_input_set(pctype);
8525 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8526 I40E_INSET_MASK_NUM_REG);
8529 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8532 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8533 (uint32_t)(inset_reg & UINT32_MAX));
8534 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8535 (uint32_t)((inset_reg >>
8536 I40E_32_BIT_WIDTH) & UINT32_MAX));
8537 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8538 (uint32_t)(inset_reg & UINT32_MAX));
8539 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8540 (uint32_t)((inset_reg >>
8541 I40E_32_BIT_WIDTH) & UINT32_MAX));
8543 for (i = 0; i < num; i++) {
8544 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8546 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8549 /*clear unused mask registers of the pctype */
8550 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8551 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8553 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8556 I40E_WRITE_FLUSH(hw);
8558 /* store the default input set */
8559 pf->hash_input_set[pctype] = input_set;
8560 pf->fdir.input_set[pctype] = input_set;
8565 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8566 struct rte_eth_input_set_conf *conf)
8568 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8569 enum i40e_filter_pctype pctype;
8570 uint64_t input_set, inset_reg = 0;
8571 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8575 PMD_DRV_LOG(ERR, "Invalid pointer");
8578 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8579 conf->op != RTE_ETH_INPUT_SET_ADD) {
8580 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8584 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8585 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8586 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8590 if (hw->mac.type == I40E_MAC_X722) {
8591 /* get translated pctype value in fd pctype register */
8592 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8593 I40E_GLQF_FD_PCTYPES((int)pctype));
8596 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8599 PMD_DRV_LOG(ERR, "Failed to parse input set");
8603 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8604 /* get inset value in register */
8605 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8606 inset_reg <<= I40E_32_BIT_WIDTH;
8607 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8608 input_set |= pf->hash_input_set[pctype];
8610 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8611 I40E_INSET_MASK_NUM_REG);
8615 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8617 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8618 (uint32_t)(inset_reg & UINT32_MAX));
8619 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8620 (uint32_t)((inset_reg >>
8621 I40E_32_BIT_WIDTH) & UINT32_MAX));
8623 for (i = 0; i < num; i++)
8624 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8626 /*clear unused mask registers of the pctype */
8627 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8628 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8630 I40E_WRITE_FLUSH(hw);
8632 pf->hash_input_set[pctype] = input_set;
8637 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8638 struct rte_eth_input_set_conf *conf)
8640 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8641 enum i40e_filter_pctype pctype;
8642 uint64_t input_set, inset_reg = 0;
8643 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8647 PMD_DRV_LOG(ERR, "Invalid pointer");
8650 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8651 conf->op != RTE_ETH_INPUT_SET_ADD) {
8652 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8656 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8658 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8659 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8663 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8666 PMD_DRV_LOG(ERR, "Failed to parse input set");
8670 /* get inset value in register */
8671 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8672 inset_reg <<= I40E_32_BIT_WIDTH;
8673 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8675 /* Can not change the inset reg for flex payload for fdir,
8676 * it is done by writing I40E_PRTQF_FD_FLXINSET
8677 * in i40e_set_flex_mask_on_pctype.
8679 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8680 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8682 input_set |= pf->fdir.input_set[pctype];
8683 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8684 I40E_INSET_MASK_NUM_REG);
8688 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8690 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8691 (uint32_t)(inset_reg & UINT32_MAX));
8692 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8693 (uint32_t)((inset_reg >>
8694 I40E_32_BIT_WIDTH) & UINT32_MAX));
8696 for (i = 0; i < num; i++)
8697 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8699 /*clear unused mask registers of the pctype */
8700 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8701 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8703 I40E_WRITE_FLUSH(hw);
8705 pf->fdir.input_set[pctype] = input_set;
8710 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8715 PMD_DRV_LOG(ERR, "Invalid pointer");
8719 switch (info->info_type) {
8720 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8721 i40e_get_symmetric_hash_enable_per_port(hw,
8722 &(info->info.enable));
8724 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8725 ret = i40e_get_hash_filter_global_config(hw,
8726 &(info->info.global_conf));
8729 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8739 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8744 PMD_DRV_LOG(ERR, "Invalid pointer");
8748 switch (info->info_type) {
8749 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8750 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8752 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8753 ret = i40e_set_hash_filter_global_config(hw,
8754 &(info->info.global_conf));
8756 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8757 ret = i40e_hash_filter_inset_select(hw,
8758 &(info->info.input_set_conf));
8762 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8771 /* Operations for hash function */
8773 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8774 enum rte_filter_op filter_op,
8777 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8780 switch (filter_op) {
8781 case RTE_ETH_FILTER_NOP:
8783 case RTE_ETH_FILTER_GET:
8784 ret = i40e_hash_filter_get(hw,
8785 (struct rte_eth_hash_filter_info *)arg);
8787 case RTE_ETH_FILTER_SET:
8788 ret = i40e_hash_filter_set(hw,
8789 (struct rte_eth_hash_filter_info *)arg);
8792 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8801 /* Convert ethertype filter structure */
8803 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8804 struct i40e_ethertype_filter *filter)
8806 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8807 filter->input.ether_type = input->ether_type;
8808 filter->flags = input->flags;
8809 filter->queue = input->queue;
8814 /* Check if there exists the ehtertype filter */
8815 struct i40e_ethertype_filter *
8816 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8817 const struct i40e_ethertype_filter_input *input)
8821 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8825 return ethertype_rule->hash_map[ret];
8828 /* Add ethertype filter in SW list */
8830 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8831 struct i40e_ethertype_filter *filter)
8833 struct i40e_ethertype_rule *rule = &pf->ethertype;
8836 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8839 "Failed to insert ethertype filter"
8840 " to hash table %d!",
8844 rule->hash_map[ret] = filter;
8846 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8851 /* Delete ethertype filter in SW list */
8853 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8854 struct i40e_ethertype_filter_input *input)
8856 struct i40e_ethertype_rule *rule = &pf->ethertype;
8857 struct i40e_ethertype_filter *filter;
8860 ret = rte_hash_del_key(rule->hash_table, input);
8863 "Failed to delete ethertype filter"
8864 " to hash table %d!",
8868 filter = rule->hash_map[ret];
8869 rule->hash_map[ret] = NULL;
8871 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8878 * Configure ethertype filter, which can director packet by filtering
8879 * with mac address and ether_type or only ether_type
8882 i40e_ethertype_filter_set(struct i40e_pf *pf,
8883 struct rte_eth_ethertype_filter *filter,
8886 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8887 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8888 struct i40e_ethertype_filter *ethertype_filter, *node;
8889 struct i40e_ethertype_filter check_filter;
8890 struct i40e_control_filter_stats stats;
8894 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8895 PMD_DRV_LOG(ERR, "Invalid queue ID");
8898 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8899 filter->ether_type == ETHER_TYPE_IPv6) {
8901 "unsupported ether_type(0x%04x) in control packet filter.",
8902 filter->ether_type);
8905 if (filter->ether_type == ETHER_TYPE_VLAN)
8906 PMD_DRV_LOG(WARNING,
8907 "filter vlan ether_type in first tag is not supported.");
8909 /* Check if there is the filter in SW list */
8910 memset(&check_filter, 0, sizeof(check_filter));
8911 i40e_ethertype_filter_convert(filter, &check_filter);
8912 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8913 &check_filter.input);
8915 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8919 if (!add && !node) {
8920 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8924 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8925 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8926 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8927 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8928 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8930 memset(&stats, 0, sizeof(stats));
8931 ret = i40e_aq_add_rem_control_packet_filter(hw,
8932 filter->mac_addr.addr_bytes,
8933 filter->ether_type, flags,
8935 filter->queue, add, &stats, NULL);
8938 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8939 ret, stats.mac_etype_used, stats.etype_used,
8940 stats.mac_etype_free, stats.etype_free);
8944 /* Add or delete a filter in SW list */
8946 ethertype_filter = rte_zmalloc("ethertype_filter",
8947 sizeof(*ethertype_filter), 0);
8948 rte_memcpy(ethertype_filter, &check_filter,
8949 sizeof(check_filter));
8950 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8952 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8959 * Handle operations for ethertype filter.
8962 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8963 enum rte_filter_op filter_op,
8966 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8969 if (filter_op == RTE_ETH_FILTER_NOP)
8973 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8978 switch (filter_op) {
8979 case RTE_ETH_FILTER_ADD:
8980 ret = i40e_ethertype_filter_set(pf,
8981 (struct rte_eth_ethertype_filter *)arg,
8984 case RTE_ETH_FILTER_DELETE:
8985 ret = i40e_ethertype_filter_set(pf,
8986 (struct rte_eth_ethertype_filter *)arg,
8990 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8998 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8999 enum rte_filter_type filter_type,
9000 enum rte_filter_op filter_op,
9008 switch (filter_type) {
9009 case RTE_ETH_FILTER_NONE:
9010 /* For global configuration */
9011 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9013 case RTE_ETH_FILTER_HASH:
9014 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9016 case RTE_ETH_FILTER_MACVLAN:
9017 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9019 case RTE_ETH_FILTER_ETHERTYPE:
9020 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9022 case RTE_ETH_FILTER_TUNNEL:
9023 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9025 case RTE_ETH_FILTER_FDIR:
9026 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9028 case RTE_ETH_FILTER_GENERIC:
9029 if (filter_op != RTE_ETH_FILTER_GET)
9031 *(const void **)arg = &i40e_flow_ops;
9034 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9044 * Check and enable Extended Tag.
9045 * Enabling Extended Tag is important for 40G performance.
9048 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9050 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9054 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9057 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9061 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9062 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9067 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9070 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9074 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9075 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9078 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9079 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9082 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9089 * As some registers wouldn't be reset unless a global hardware reset,
9090 * hardware initialization is needed to put those registers into an
9091 * expected initial state.
9094 i40e_hw_init(struct rte_eth_dev *dev)
9096 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9098 i40e_enable_extended_tag(dev);
9100 /* clear the PF Queue Filter control register */
9101 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9103 /* Disable symmetric hash per port */
9104 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9108 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9109 * however this function will return only one highest pctype index,
9110 * which is not quite correct. This is known problem of i40e driver
9111 * and needs to be fixed later.
9113 enum i40e_filter_pctype
9114 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9117 uint64_t pctype_mask;
9119 if (flow_type < I40E_FLOW_TYPE_MAX) {
9120 pctype_mask = adapter->pctypes_tbl[flow_type];
9121 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9122 if (pctype_mask & (1ULL << i))
9123 return (enum i40e_filter_pctype)i;
9126 return I40E_FILTER_PCTYPE_INVALID;
9130 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9131 enum i40e_filter_pctype pctype)
9134 uint64_t pctype_mask = 1ULL << pctype;
9136 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9138 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9142 return RTE_ETH_FLOW_UNKNOWN;
9146 * On X710, performance number is far from the expectation on recent firmware
9147 * versions; on XL710, performance number is also far from the expectation on
9148 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9149 * mode is enabled and port MAC address is equal to the packet destination MAC
9150 * address. The fix for this issue may not be integrated in the following
9151 * firmware version. So the workaround in software driver is needed. It needs
9152 * to modify the initial values of 3 internal only registers for both X710 and
9153 * XL710. Note that the values for X710 or XL710 could be different, and the
9154 * workaround can be removed when it is fixed in firmware in the future.
9157 /* For both X710 and XL710 */
9158 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9159 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x20000200
9160 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9162 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9163 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9166 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9167 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9170 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9172 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9173 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9176 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9178 enum i40e_status_code status;
9179 struct i40e_aq_get_phy_abilities_resp phy_ab;
9183 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9187 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9190 rte_delay_us(100000);
9192 status = i40e_aq_get_phy_capabilities(hw, false,
9193 true, &phy_ab, NULL);
9201 i40e_configure_registers(struct i40e_hw *hw)
9207 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9208 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9209 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9215 for (i = 0; i < RTE_DIM(reg_table); i++) {
9216 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9217 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9219 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9220 else /* For X710/XL710/XXV710 */
9221 if (hw->aq.fw_maj_ver < 6)
9223 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9226 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9229 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9230 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9232 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9233 else /* For X710/XL710/XXV710 */
9235 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9238 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9239 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9240 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9242 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9245 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9248 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9251 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9255 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9256 reg_table[i].addr, reg);
9257 if (reg == reg_table[i].val)
9260 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9261 reg_table[i].val, NULL);
9264 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9265 reg_table[i].val, reg_table[i].addr);
9268 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9269 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9273 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9274 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9275 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9276 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9278 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9283 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9284 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9288 /* Configure for double VLAN RX stripping */
9289 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9290 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9291 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9292 ret = i40e_aq_debug_write_register(hw,
9293 I40E_VSI_TSR(vsi->vsi_id),
9296 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9298 return I40E_ERR_CONFIG;
9302 /* Configure for double VLAN TX insertion */
9303 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9304 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9305 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9306 ret = i40e_aq_debug_write_register(hw,
9307 I40E_VSI_L2TAGSTXVALID(
9308 vsi->vsi_id), reg, NULL);
9311 "Failed to update VSI_L2TAGSTXVALID[%d]",
9313 return I40E_ERR_CONFIG;
9321 * i40e_aq_add_mirror_rule
9322 * @hw: pointer to the hardware structure
9323 * @seid: VEB seid to add mirror rule to
9324 * @dst_id: destination vsi seid
9325 * @entries: Buffer which contains the entities to be mirrored
9326 * @count: number of entities contained in the buffer
9327 * @rule_id:the rule_id of the rule to be added
9329 * Add a mirror rule for a given veb.
9332 static enum i40e_status_code
9333 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9334 uint16_t seid, uint16_t dst_id,
9335 uint16_t rule_type, uint16_t *entries,
9336 uint16_t count, uint16_t *rule_id)
9338 struct i40e_aq_desc desc;
9339 struct i40e_aqc_add_delete_mirror_rule cmd;
9340 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9341 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9344 enum i40e_status_code status;
9346 i40e_fill_default_direct_cmd_desc(&desc,
9347 i40e_aqc_opc_add_mirror_rule);
9348 memset(&cmd, 0, sizeof(cmd));
9350 buff_len = sizeof(uint16_t) * count;
9351 desc.datalen = rte_cpu_to_le_16(buff_len);
9353 desc.flags |= rte_cpu_to_le_16(
9354 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9355 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9356 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9357 cmd.num_entries = rte_cpu_to_le_16(count);
9358 cmd.seid = rte_cpu_to_le_16(seid);
9359 cmd.destination = rte_cpu_to_le_16(dst_id);
9361 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9362 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9364 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9365 hw->aq.asq_last_status, resp->rule_id,
9366 resp->mirror_rules_used, resp->mirror_rules_free);
9367 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9373 * i40e_aq_del_mirror_rule
9374 * @hw: pointer to the hardware structure
9375 * @seid: VEB seid to add mirror rule to
9376 * @entries: Buffer which contains the entities to be mirrored
9377 * @count: number of entities contained in the buffer
9378 * @rule_id:the rule_id of the rule to be delete
9380 * Delete a mirror rule for a given veb.
9383 static enum i40e_status_code
9384 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9385 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9386 uint16_t count, uint16_t rule_id)
9388 struct i40e_aq_desc desc;
9389 struct i40e_aqc_add_delete_mirror_rule cmd;
9390 uint16_t buff_len = 0;
9391 enum i40e_status_code status;
9394 i40e_fill_default_direct_cmd_desc(&desc,
9395 i40e_aqc_opc_delete_mirror_rule);
9396 memset(&cmd, 0, sizeof(cmd));
9397 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9398 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9400 cmd.num_entries = count;
9401 buff_len = sizeof(uint16_t) * count;
9402 desc.datalen = rte_cpu_to_le_16(buff_len);
9403 buff = (void *)entries;
9405 /* rule id is filled in destination field for deleting mirror rule */
9406 cmd.destination = rte_cpu_to_le_16(rule_id);
9408 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9409 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9410 cmd.seid = rte_cpu_to_le_16(seid);
9412 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9413 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9419 * i40e_mirror_rule_set
9420 * @dev: pointer to the hardware structure
9421 * @mirror_conf: mirror rule info
9422 * @sw_id: mirror rule's sw_id
9423 * @on: enable/disable
9425 * set a mirror rule.
9429 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9430 struct rte_eth_mirror_conf *mirror_conf,
9431 uint8_t sw_id, uint8_t on)
9433 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9434 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9435 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9436 struct i40e_mirror_rule *parent = NULL;
9437 uint16_t seid, dst_seid, rule_id;
9441 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9443 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9445 "mirror rule can not be configured without veb or vfs.");
9448 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9449 PMD_DRV_LOG(ERR, "mirror table is full.");
9452 if (mirror_conf->dst_pool > pf->vf_num) {
9453 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9454 mirror_conf->dst_pool);
9458 seid = pf->main_vsi->veb->seid;
9460 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9461 if (sw_id <= it->index) {
9467 if (mirr_rule && sw_id == mirr_rule->index) {
9469 PMD_DRV_LOG(ERR, "mirror rule exists.");
9472 ret = i40e_aq_del_mirror_rule(hw, seid,
9473 mirr_rule->rule_type,
9475 mirr_rule->num_entries, mirr_rule->id);
9478 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9479 ret, hw->aq.asq_last_status);
9482 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9483 rte_free(mirr_rule);
9484 pf->nb_mirror_rule--;
9488 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9492 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9493 sizeof(struct i40e_mirror_rule) , 0);
9495 PMD_DRV_LOG(ERR, "failed to allocate memory");
9496 return I40E_ERR_NO_MEMORY;
9498 switch (mirror_conf->rule_type) {
9499 case ETH_MIRROR_VLAN:
9500 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9501 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9502 mirr_rule->entries[j] =
9503 mirror_conf->vlan.vlan_id[i];
9508 PMD_DRV_LOG(ERR, "vlan is not specified.");
9509 rte_free(mirr_rule);
9512 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9514 case ETH_MIRROR_VIRTUAL_POOL_UP:
9515 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9516 /* check if the specified pool bit is out of range */
9517 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9518 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9519 rte_free(mirr_rule);
9522 for (i = 0, j = 0; i < pf->vf_num; i++) {
9523 if (mirror_conf->pool_mask & (1ULL << i)) {
9524 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9528 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9529 /* add pf vsi to entries */
9530 mirr_rule->entries[j] = pf->main_vsi_seid;
9534 PMD_DRV_LOG(ERR, "pool is not specified.");
9535 rte_free(mirr_rule);
9538 /* egress and ingress in aq commands means from switch but not port */
9539 mirr_rule->rule_type =
9540 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9541 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9542 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9544 case ETH_MIRROR_UPLINK_PORT:
9545 /* egress and ingress in aq commands means from switch but not port*/
9546 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9548 case ETH_MIRROR_DOWNLINK_PORT:
9549 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9552 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9553 mirror_conf->rule_type);
9554 rte_free(mirr_rule);
9558 /* If the dst_pool is equal to vf_num, consider it as PF */
9559 if (mirror_conf->dst_pool == pf->vf_num)
9560 dst_seid = pf->main_vsi_seid;
9562 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9564 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9565 mirr_rule->rule_type, mirr_rule->entries,
9569 "failed to add mirror rule: ret = %d, aq_err = %d.",
9570 ret, hw->aq.asq_last_status);
9571 rte_free(mirr_rule);
9575 mirr_rule->index = sw_id;
9576 mirr_rule->num_entries = j;
9577 mirr_rule->id = rule_id;
9578 mirr_rule->dst_vsi_seid = dst_seid;
9581 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9583 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9585 pf->nb_mirror_rule++;
9590 * i40e_mirror_rule_reset
9591 * @dev: pointer to the device
9592 * @sw_id: mirror rule's sw_id
9594 * reset a mirror rule.
9598 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9600 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9601 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9602 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9606 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9608 seid = pf->main_vsi->veb->seid;
9610 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9611 if (sw_id == it->index) {
9617 ret = i40e_aq_del_mirror_rule(hw, seid,
9618 mirr_rule->rule_type,
9620 mirr_rule->num_entries, mirr_rule->id);
9623 "failed to remove mirror rule: status = %d, aq_err = %d.",
9624 ret, hw->aq.asq_last_status);
9627 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9628 rte_free(mirr_rule);
9629 pf->nb_mirror_rule--;
9631 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9638 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9640 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9641 uint64_t systim_cycles;
9643 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9644 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9647 return systim_cycles;
9651 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9653 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9656 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9657 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9664 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9666 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9669 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9670 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9677 i40e_start_timecounters(struct rte_eth_dev *dev)
9679 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9680 struct i40e_adapter *adapter =
9681 (struct i40e_adapter *)dev->data->dev_private;
9682 struct rte_eth_link link;
9683 uint32_t tsync_inc_l;
9684 uint32_t tsync_inc_h;
9686 /* Get current link speed. */
9687 memset(&link, 0, sizeof(link));
9688 i40e_dev_link_update(dev, 1);
9689 rte_i40e_dev_atomic_read_link_status(dev, &link);
9691 switch (link.link_speed) {
9692 case ETH_SPEED_NUM_40G:
9693 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9694 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9696 case ETH_SPEED_NUM_10G:
9697 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9698 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9700 case ETH_SPEED_NUM_1G:
9701 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9702 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9709 /* Set the timesync increment value. */
9710 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9711 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9713 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9714 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9715 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9717 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9718 adapter->systime_tc.cc_shift = 0;
9719 adapter->systime_tc.nsec_mask = 0;
9721 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9722 adapter->rx_tstamp_tc.cc_shift = 0;
9723 adapter->rx_tstamp_tc.nsec_mask = 0;
9725 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9726 adapter->tx_tstamp_tc.cc_shift = 0;
9727 adapter->tx_tstamp_tc.nsec_mask = 0;
9731 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9733 struct i40e_adapter *adapter =
9734 (struct i40e_adapter *)dev->data->dev_private;
9736 adapter->systime_tc.nsec += delta;
9737 adapter->rx_tstamp_tc.nsec += delta;
9738 adapter->tx_tstamp_tc.nsec += delta;
9744 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9747 struct i40e_adapter *adapter =
9748 (struct i40e_adapter *)dev->data->dev_private;
9750 ns = rte_timespec_to_ns(ts);
9752 /* Set the timecounters to a new value. */
9753 adapter->systime_tc.nsec = ns;
9754 adapter->rx_tstamp_tc.nsec = ns;
9755 adapter->tx_tstamp_tc.nsec = ns;
9761 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9763 uint64_t ns, systime_cycles;
9764 struct i40e_adapter *adapter =
9765 (struct i40e_adapter *)dev->data->dev_private;
9767 systime_cycles = i40e_read_systime_cyclecounter(dev);
9768 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9769 *ts = rte_ns_to_timespec(ns);
9775 i40e_timesync_enable(struct rte_eth_dev *dev)
9777 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9778 uint32_t tsync_ctl_l;
9779 uint32_t tsync_ctl_h;
9781 /* Stop the timesync system time. */
9782 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9783 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9784 /* Reset the timesync system time value. */
9785 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9786 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9788 i40e_start_timecounters(dev);
9790 /* Clear timesync registers. */
9791 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9792 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9793 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9794 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9795 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9796 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9798 /* Enable timestamping of PTP packets. */
9799 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9800 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9802 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9803 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9804 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9806 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9807 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9813 i40e_timesync_disable(struct rte_eth_dev *dev)
9815 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9816 uint32_t tsync_ctl_l;
9817 uint32_t tsync_ctl_h;
9819 /* Disable timestamping of transmitted PTP packets. */
9820 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9821 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9823 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9824 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9826 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9827 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9829 /* Reset the timesync increment value. */
9830 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9831 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9837 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9838 struct timespec *timestamp, uint32_t flags)
9840 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9841 struct i40e_adapter *adapter =
9842 (struct i40e_adapter *)dev->data->dev_private;
9844 uint32_t sync_status;
9845 uint32_t index = flags & 0x03;
9846 uint64_t rx_tstamp_cycles;
9849 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9850 if ((sync_status & (1 << index)) == 0)
9853 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9854 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9855 *timestamp = rte_ns_to_timespec(ns);
9861 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9862 struct timespec *timestamp)
9864 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9865 struct i40e_adapter *adapter =
9866 (struct i40e_adapter *)dev->data->dev_private;
9868 uint32_t sync_status;
9869 uint64_t tx_tstamp_cycles;
9872 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9873 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9876 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9877 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9878 *timestamp = rte_ns_to_timespec(ns);
9884 * i40e_parse_dcb_configure - parse dcb configure from user
9885 * @dev: the device being configured
9886 * @dcb_cfg: pointer of the result of parse
9887 * @*tc_map: bit map of enabled traffic classes
9889 * Returns 0 on success, negative value on failure
9892 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9893 struct i40e_dcbx_config *dcb_cfg,
9896 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9897 uint8_t i, tc_bw, bw_lf;
9899 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9901 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9902 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9903 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9907 /* assume each tc has the same bw */
9908 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9909 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9910 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9911 /* to ensure the sum of tcbw is equal to 100 */
9912 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9913 for (i = 0; i < bw_lf; i++)
9914 dcb_cfg->etscfg.tcbwtable[i]++;
9916 /* assume each tc has the same Transmission Selection Algorithm */
9917 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9918 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9920 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9921 dcb_cfg->etscfg.prioritytable[i] =
9922 dcb_rx_conf->dcb_tc[i];
9924 /* FW needs one App to configure HW */
9925 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9926 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9927 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9928 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9930 if (dcb_rx_conf->nb_tcs == 0)
9931 *tc_map = 1; /* tc0 only */
9933 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9935 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9936 dcb_cfg->pfc.willing = 0;
9937 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9938 dcb_cfg->pfc.pfcenable = *tc_map;
9944 static enum i40e_status_code
9945 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9946 struct i40e_aqc_vsi_properties_data *info,
9947 uint8_t enabled_tcmap)
9949 enum i40e_status_code ret;
9950 int i, total_tc = 0;
9951 uint16_t qpnum_per_tc, bsf, qp_idx;
9952 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9953 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9954 uint16_t used_queues;
9956 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9957 if (ret != I40E_SUCCESS)
9960 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9961 if (enabled_tcmap & (1 << i))
9966 vsi->enabled_tc = enabled_tcmap;
9968 /* different VSI has different queues assigned */
9969 if (vsi->type == I40E_VSI_MAIN)
9970 used_queues = dev_data->nb_rx_queues -
9971 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9972 else if (vsi->type == I40E_VSI_VMDQ2)
9973 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9975 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9976 return I40E_ERR_NO_AVAILABLE_VSI;
9979 qpnum_per_tc = used_queues / total_tc;
9980 /* Number of queues per enabled TC */
9981 if (qpnum_per_tc == 0) {
9982 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9983 return I40E_ERR_INVALID_QP_ID;
9985 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9987 bsf = rte_bsf32(qpnum_per_tc);
9990 * Configure TC and queue mapping parameters, for enabled TC,
9991 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9992 * default queue will serve it.
9995 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9996 if (vsi->enabled_tc & (1 << i)) {
9997 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9998 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9999 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10000 qp_idx += qpnum_per_tc;
10002 info->tc_mapping[i] = 0;
10005 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10006 if (vsi->type == I40E_VSI_SRIOV) {
10007 info->mapping_flags |=
10008 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10009 for (i = 0; i < vsi->nb_qps; i++)
10010 info->queue_mapping[i] =
10011 rte_cpu_to_le_16(vsi->base_queue + i);
10013 info->mapping_flags |=
10014 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10015 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10017 info->valid_sections |=
10018 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10020 return I40E_SUCCESS;
10024 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10025 * @veb: VEB to be configured
10026 * @tc_map: enabled TC bitmap
10028 * Returns 0 on success, negative value on failure
10030 static enum i40e_status_code
10031 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10033 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10034 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10035 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10036 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10037 enum i40e_status_code ret = I40E_SUCCESS;
10041 /* Check if enabled_tc is same as existing or new TCs */
10042 if (veb->enabled_tc == tc_map)
10045 /* configure tc bandwidth */
10046 memset(&veb_bw, 0, sizeof(veb_bw));
10047 veb_bw.tc_valid_bits = tc_map;
10048 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10049 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10050 if (tc_map & BIT_ULL(i))
10051 veb_bw.tc_bw_share_credits[i] = 1;
10053 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10057 "AQ command Config switch_comp BW allocation per TC failed = %d",
10058 hw->aq.asq_last_status);
10062 memset(&ets_query, 0, sizeof(ets_query));
10063 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10065 if (ret != I40E_SUCCESS) {
10067 "Failed to get switch_comp ETS configuration %u",
10068 hw->aq.asq_last_status);
10071 memset(&bw_query, 0, sizeof(bw_query));
10072 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10074 if (ret != I40E_SUCCESS) {
10076 "Failed to get switch_comp bandwidth configuration %u",
10077 hw->aq.asq_last_status);
10081 /* store and print out BW info */
10082 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10083 veb->bw_info.bw_max = ets_query.tc_bw_max;
10084 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10085 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10086 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10087 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10088 I40E_16_BIT_WIDTH);
10089 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10090 veb->bw_info.bw_ets_share_credits[i] =
10091 bw_query.tc_bw_share_credits[i];
10092 veb->bw_info.bw_ets_credits[i] =
10093 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10094 /* 4 bits per TC, 4th bit is reserved */
10095 veb->bw_info.bw_ets_max[i] =
10096 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10097 RTE_LEN2MASK(3, uint8_t));
10098 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10099 veb->bw_info.bw_ets_share_credits[i]);
10100 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10101 veb->bw_info.bw_ets_credits[i]);
10102 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10103 veb->bw_info.bw_ets_max[i]);
10106 veb->enabled_tc = tc_map;
10113 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10114 * @vsi: VSI to be configured
10115 * @tc_map: enabled TC bitmap
10117 * Returns 0 on success, negative value on failure
10119 static enum i40e_status_code
10120 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10122 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10123 struct i40e_vsi_context ctxt;
10124 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10125 enum i40e_status_code ret = I40E_SUCCESS;
10128 /* Check if enabled_tc is same as existing or new TCs */
10129 if (vsi->enabled_tc == tc_map)
10132 /* configure tc bandwidth */
10133 memset(&bw_data, 0, sizeof(bw_data));
10134 bw_data.tc_valid_bits = tc_map;
10135 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10136 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10137 if (tc_map & BIT_ULL(i))
10138 bw_data.tc_bw_credits[i] = 1;
10140 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10143 "AQ command Config VSI BW allocation per TC failed = %d",
10144 hw->aq.asq_last_status);
10147 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10148 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10150 /* Update Queue Pairs Mapping for currently enabled UPs */
10151 ctxt.seid = vsi->seid;
10152 ctxt.pf_num = hw->pf_id;
10154 ctxt.uplink_seid = vsi->uplink_seid;
10155 ctxt.info = vsi->info;
10157 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10161 /* Update the VSI after updating the VSI queue-mapping information */
10162 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10164 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10165 hw->aq.asq_last_status);
10168 /* update the local VSI info with updated queue map */
10169 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10170 sizeof(vsi->info.tc_mapping));
10171 rte_memcpy(&vsi->info.queue_mapping,
10172 &ctxt.info.queue_mapping,
10173 sizeof(vsi->info.queue_mapping));
10174 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10175 vsi->info.valid_sections = 0;
10177 /* query and update current VSI BW information */
10178 ret = i40e_vsi_get_bw_config(vsi);
10181 "Failed updating vsi bw info, err %s aq_err %s",
10182 i40e_stat_str(hw, ret),
10183 i40e_aq_str(hw, hw->aq.asq_last_status));
10187 vsi->enabled_tc = tc_map;
10194 * i40e_dcb_hw_configure - program the dcb setting to hw
10195 * @pf: pf the configuration is taken on
10196 * @new_cfg: new configuration
10197 * @tc_map: enabled TC bitmap
10199 * Returns 0 on success, negative value on failure
10201 static enum i40e_status_code
10202 i40e_dcb_hw_configure(struct i40e_pf *pf,
10203 struct i40e_dcbx_config *new_cfg,
10206 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10207 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10208 struct i40e_vsi *main_vsi = pf->main_vsi;
10209 struct i40e_vsi_list *vsi_list;
10210 enum i40e_status_code ret;
10214 /* Use the FW API if FW > v4.4*/
10215 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10216 (hw->aq.fw_maj_ver >= 5))) {
10218 "FW < v4.4, can not use FW LLDP API to configure DCB");
10219 return I40E_ERR_FIRMWARE_API_VERSION;
10222 /* Check if need reconfiguration */
10223 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10224 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10225 return I40E_SUCCESS;
10228 /* Copy the new config to the current config */
10229 *old_cfg = *new_cfg;
10230 old_cfg->etsrec = old_cfg->etscfg;
10231 ret = i40e_set_dcb_config(hw);
10233 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10234 i40e_stat_str(hw, ret),
10235 i40e_aq_str(hw, hw->aq.asq_last_status));
10238 /* set receive Arbiter to RR mode and ETS scheme by default */
10239 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10240 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10241 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10242 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10243 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10244 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10245 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10246 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10247 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10248 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10249 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10250 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10251 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10253 /* get local mib to check whether it is configured correctly */
10255 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10256 /* Get Local DCB Config */
10257 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10258 &hw->local_dcbx_config);
10260 /* if Veb is created, need to update TC of it at first */
10261 if (main_vsi->veb) {
10262 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10264 PMD_INIT_LOG(WARNING,
10265 "Failed configuring TC for VEB seid=%d",
10266 main_vsi->veb->seid);
10268 /* Update each VSI */
10269 i40e_vsi_config_tc(main_vsi, tc_map);
10270 if (main_vsi->veb) {
10271 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10272 /* Beside main VSI and VMDQ VSIs, only enable default
10273 * TC for other VSIs
10275 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10276 ret = i40e_vsi_config_tc(vsi_list->vsi,
10279 ret = i40e_vsi_config_tc(vsi_list->vsi,
10280 I40E_DEFAULT_TCMAP);
10282 PMD_INIT_LOG(WARNING,
10283 "Failed configuring TC for VSI seid=%d",
10284 vsi_list->vsi->seid);
10288 return I40E_SUCCESS;
10292 * i40e_dcb_init_configure - initial dcb config
10293 * @dev: device being configured
10294 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10296 * Returns 0 on success, negative value on failure
10299 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10301 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10302 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10305 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10306 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10310 /* DCB initialization:
10311 * Update DCB configuration from the Firmware and configure
10312 * LLDP MIB change event.
10314 if (sw_dcb == TRUE) {
10315 ret = i40e_init_dcb(hw);
10316 /* If lldp agent is stopped, the return value from
10317 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10318 * adminq status. Otherwise, it should return success.
10320 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10321 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10322 memset(&hw->local_dcbx_config, 0,
10323 sizeof(struct i40e_dcbx_config));
10324 /* set dcb default configuration */
10325 hw->local_dcbx_config.etscfg.willing = 0;
10326 hw->local_dcbx_config.etscfg.maxtcs = 0;
10327 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10328 hw->local_dcbx_config.etscfg.tsatable[0] =
10330 /* all UPs mapping to TC0 */
10331 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10332 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10333 hw->local_dcbx_config.etsrec =
10334 hw->local_dcbx_config.etscfg;
10335 hw->local_dcbx_config.pfc.willing = 0;
10336 hw->local_dcbx_config.pfc.pfccap =
10337 I40E_MAX_TRAFFIC_CLASS;
10338 /* FW needs one App to configure HW */
10339 hw->local_dcbx_config.numapps = 1;
10340 hw->local_dcbx_config.app[0].selector =
10341 I40E_APP_SEL_ETHTYPE;
10342 hw->local_dcbx_config.app[0].priority = 3;
10343 hw->local_dcbx_config.app[0].protocolid =
10344 I40E_APP_PROTOID_FCOE;
10345 ret = i40e_set_dcb_config(hw);
10348 "default dcb config fails. err = %d, aq_err = %d.",
10349 ret, hw->aq.asq_last_status);
10354 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10355 ret, hw->aq.asq_last_status);
10359 ret = i40e_aq_start_lldp(hw, NULL);
10360 if (ret != I40E_SUCCESS)
10361 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10363 ret = i40e_init_dcb(hw);
10365 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10367 "HW doesn't support DCBX offload.");
10372 "DCBX configuration failed, err = %d, aq_err = %d.",
10373 ret, hw->aq.asq_last_status);
10381 * i40e_dcb_setup - setup dcb related config
10382 * @dev: device being configured
10384 * Returns 0 on success, negative value on failure
10387 i40e_dcb_setup(struct rte_eth_dev *dev)
10389 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10390 struct i40e_dcbx_config dcb_cfg;
10391 uint8_t tc_map = 0;
10394 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10395 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10399 if (pf->vf_num != 0)
10400 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10402 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10404 PMD_INIT_LOG(ERR, "invalid dcb config");
10407 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10409 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10417 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10418 struct rte_eth_dcb_info *dcb_info)
10420 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10421 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10422 struct i40e_vsi *vsi = pf->main_vsi;
10423 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10424 uint16_t bsf, tc_mapping;
10427 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10428 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10430 dcb_info->nb_tcs = 1;
10431 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10432 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10433 for (i = 0; i < dcb_info->nb_tcs; i++)
10434 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10436 /* get queue mapping if vmdq is disabled */
10437 if (!pf->nb_cfg_vmdq_vsi) {
10438 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10439 if (!(vsi->enabled_tc & (1 << i)))
10441 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10442 dcb_info->tc_queue.tc_rxq[j][i].base =
10443 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10444 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10445 dcb_info->tc_queue.tc_txq[j][i].base =
10446 dcb_info->tc_queue.tc_rxq[j][i].base;
10447 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10448 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10449 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10450 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10451 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10456 /* get queue mapping if vmdq is enabled */
10458 vsi = pf->vmdq[j].vsi;
10459 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10460 if (!(vsi->enabled_tc & (1 << i)))
10462 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10463 dcb_info->tc_queue.tc_rxq[j][i].base =
10464 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10465 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10466 dcb_info->tc_queue.tc_txq[j][i].base =
10467 dcb_info->tc_queue.tc_rxq[j][i].base;
10468 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10469 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10470 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10471 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10472 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10475 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10480 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10482 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10483 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10484 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10485 uint16_t interval =
10486 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10487 uint16_t msix_intr;
10489 msix_intr = intr_handle->intr_vec[queue_id];
10490 if (msix_intr == I40E_MISC_VEC_ID)
10491 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10492 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10493 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10494 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10496 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10499 I40E_PFINT_DYN_CTLN(msix_intr -
10500 I40E_RX_VEC_START),
10501 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10502 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10503 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10505 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10507 I40E_WRITE_FLUSH(hw);
10508 rte_intr_enable(&pci_dev->intr_handle);
10514 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10516 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10517 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10518 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10519 uint16_t msix_intr;
10521 msix_intr = intr_handle->intr_vec[queue_id];
10522 if (msix_intr == I40E_MISC_VEC_ID)
10523 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10526 I40E_PFINT_DYN_CTLN(msix_intr -
10527 I40E_RX_VEC_START),
10529 I40E_WRITE_FLUSH(hw);
10534 static int i40e_get_regs(struct rte_eth_dev *dev,
10535 struct rte_dev_reg_info *regs)
10537 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10538 uint32_t *ptr_data = regs->data;
10539 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10540 const struct i40e_reg_info *reg_info;
10542 if (ptr_data == NULL) {
10543 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10544 regs->width = sizeof(uint32_t);
10548 /* The first few registers have to be read using AQ operations */
10550 while (i40e_regs_adminq[reg_idx].name) {
10551 reg_info = &i40e_regs_adminq[reg_idx++];
10552 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10554 arr_idx2 <= reg_info->count2;
10556 reg_offset = arr_idx * reg_info->stride1 +
10557 arr_idx2 * reg_info->stride2;
10558 reg_offset += reg_info->base_addr;
10559 ptr_data[reg_offset >> 2] =
10560 i40e_read_rx_ctl(hw, reg_offset);
10564 /* The remaining registers can be read using primitives */
10566 while (i40e_regs_others[reg_idx].name) {
10567 reg_info = &i40e_regs_others[reg_idx++];
10568 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10570 arr_idx2 <= reg_info->count2;
10572 reg_offset = arr_idx * reg_info->stride1 +
10573 arr_idx2 * reg_info->stride2;
10574 reg_offset += reg_info->base_addr;
10575 ptr_data[reg_offset >> 2] =
10576 I40E_READ_REG(hw, reg_offset);
10583 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10585 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10587 /* Convert word count to byte count */
10588 return hw->nvm.sr_size << 1;
10591 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10592 struct rte_dev_eeprom_info *eeprom)
10594 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10595 uint16_t *data = eeprom->data;
10596 uint16_t offset, length, cnt_words;
10599 offset = eeprom->offset >> 1;
10600 length = eeprom->length >> 1;
10601 cnt_words = length;
10603 if (offset > hw->nvm.sr_size ||
10604 offset + length > hw->nvm.sr_size) {
10605 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10609 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10611 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10612 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10613 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10620 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10621 struct ether_addr *mac_addr)
10623 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10625 if (!is_valid_assigned_ether_addr(mac_addr)) {
10626 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10630 /* Flags: 0x3 updates port address */
10631 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10635 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10637 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10638 struct rte_eth_dev_data *dev_data = pf->dev_data;
10639 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10642 /* check if mtu is within the allowed range */
10643 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10646 /* mtu setting is forbidden if port is start */
10647 if (dev_data->dev_started) {
10648 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10649 dev_data->port_id);
10653 if (frame_size > ETHER_MAX_LEN)
10654 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10656 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10658 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10663 /* Restore ethertype filter */
10665 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10667 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10668 struct i40e_ethertype_filter_list
10669 *ethertype_list = &pf->ethertype.ethertype_list;
10670 struct i40e_ethertype_filter *f;
10671 struct i40e_control_filter_stats stats;
10674 TAILQ_FOREACH(f, ethertype_list, rules) {
10676 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10677 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10678 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10679 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10680 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10682 memset(&stats, 0, sizeof(stats));
10683 i40e_aq_add_rem_control_packet_filter(hw,
10684 f->input.mac_addr.addr_bytes,
10685 f->input.ether_type,
10686 flags, pf->main_vsi->seid,
10687 f->queue, 1, &stats, NULL);
10689 PMD_DRV_LOG(INFO, "Ethertype filter:"
10690 " mac_etype_used = %u, etype_used = %u,"
10691 " mac_etype_free = %u, etype_free = %u",
10692 stats.mac_etype_used, stats.etype_used,
10693 stats.mac_etype_free, stats.etype_free);
10696 /* Restore tunnel filter */
10698 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10700 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10701 struct i40e_vsi *vsi;
10702 struct i40e_pf_vf *vf;
10703 struct i40e_tunnel_filter_list
10704 *tunnel_list = &pf->tunnel.tunnel_list;
10705 struct i40e_tunnel_filter *f;
10706 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10707 bool big_buffer = 0;
10709 TAILQ_FOREACH(f, tunnel_list, rules) {
10711 vsi = pf->main_vsi;
10713 vf = &pf->vfs[f->vf_id];
10716 memset(&cld_filter, 0, sizeof(cld_filter));
10717 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10718 (struct ether_addr *)&cld_filter.element.outer_mac);
10719 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10720 (struct ether_addr *)&cld_filter.element.inner_mac);
10721 cld_filter.element.inner_vlan = f->input.inner_vlan;
10722 cld_filter.element.flags = f->input.flags;
10723 cld_filter.element.tenant_id = f->input.tenant_id;
10724 cld_filter.element.queue_number = f->queue;
10725 rte_memcpy(cld_filter.general_fields,
10726 f->input.general_fields,
10727 sizeof(f->input.general_fields));
10729 if (((f->input.flags &
10730 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10731 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10733 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10734 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10736 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10737 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10741 i40e_aq_add_cloud_filters_big_buffer(hw,
10742 vsi->seid, &cld_filter, 1);
10744 i40e_aq_add_cloud_filters(hw, vsi->seid,
10745 &cld_filter.element, 1);
10750 i40e_filter_restore(struct i40e_pf *pf)
10752 i40e_ethertype_filter_restore(pf);
10753 i40e_tunnel_filter_restore(pf);
10754 i40e_fdir_filter_restore(pf);
10758 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10760 if (strcmp(dev->device->driver->name, drv->driver.name))
10767 is_i40e_supported(struct rte_eth_dev *dev)
10769 return is_device_supported(dev, &rte_i40e_pmd);
10772 /* Create a QinQ cloud filter
10774 * The Fortville NIC has limited resources for tunnel filters,
10775 * so we can only reuse existing filters.
10777 * In step 1 we define which Field Vector fields can be used for
10779 * As we do not have the inner tag defined as a field,
10780 * we have to define it first, by reusing one of L1 entries.
10782 * In step 2 we are replacing one of existing filter types with
10783 * a new one for QinQ.
10784 * As we reusing L1 and replacing L2, some of the default filter
10785 * types will disappear,which depends on L1 and L2 entries we reuse.
10787 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10789 * 1. Create L1 filter of outer vlan (12b) which will be in use
10790 * later when we define the cloud filter.
10791 * a. Valid_flags.replace_cloud = 0
10792 * b. Old_filter = 10 (Stag_Inner_Vlan)
10793 * c. New_filter = 0x10
10794 * d. TR bit = 0xff (optional, not used here)
10795 * e. Buffer – 2 entries:
10796 * i. Byte 0 = 8 (outer vlan FV index).
10798 * Byte 2-3 = 0x0fff
10799 * ii. Byte 0 = 37 (inner vlan FV index).
10801 * Byte 2-3 = 0x0fff
10804 * 2. Create cloud filter using two L1 filters entries: stag and
10805 * new filter(outer vlan+ inner vlan)
10806 * a. Valid_flags.replace_cloud = 1
10807 * b. Old_filter = 1 (instead of outer IP)
10808 * c. New_filter = 0x10
10809 * d. Buffer – 2 entries:
10810 * i. Byte 0 = 0x80 | 7 (valid | Stag).
10811 * Byte 1-3 = 0 (rsv)
10812 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10813 * Byte 9-11 = 0 (rsv)
10816 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10818 int ret = -ENOTSUP;
10819 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
10820 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
10821 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10824 memset(&filter_replace, 0,
10825 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10826 memset(&filter_replace_buf, 0,
10827 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10829 /* create L1 filter */
10830 filter_replace.old_filter_type =
10831 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10832 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10833 filter_replace.tr_bit = 0;
10835 /* Prepare the buffer, 2 entries */
10836 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10837 filter_replace_buf.data[0] |=
10838 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10839 /* Field Vector 12b mask */
10840 filter_replace_buf.data[2] = 0xff;
10841 filter_replace_buf.data[3] = 0x0f;
10842 filter_replace_buf.data[4] =
10843 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10844 filter_replace_buf.data[4] |=
10845 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10846 /* Field Vector 12b mask */
10847 filter_replace_buf.data[6] = 0xff;
10848 filter_replace_buf.data[7] = 0x0f;
10849 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10850 &filter_replace_buf);
10851 if (ret != I40E_SUCCESS)
10854 /* Apply the second L2 cloud filter */
10855 memset(&filter_replace, 0,
10856 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10857 memset(&filter_replace_buf, 0,
10858 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10860 /* create L2 filter, input for L2 filter will be L1 filter */
10861 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10862 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10863 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10865 /* Prepare the buffer, 2 entries */
10866 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10867 filter_replace_buf.data[0] |=
10868 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10869 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10870 filter_replace_buf.data[4] |=
10871 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10872 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10873 &filter_replace_buf);
10877 RTE_INIT(i40e_init_log);
10879 i40e_init_log(void)
10881 i40e_logtype_init = rte_log_register("pmd.i40e.init");
10882 if (i40e_logtype_init >= 0)
10883 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10884 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10885 if (i40e_logtype_driver >= 0)
10886 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);