1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "i40e_ethdev.h"
37 #include "i40e_rxtx.h"
39 #include "i40e_regs.h"
40 #include "rte_pmd_i40e.h"
42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
44 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
48 #define I40E_CLEAR_PXE_WAIT_MS 200
50 /* Maximun number of capability elements */
51 #define I40E_MAX_CAP_ELE_NUM 128
53 /* Wait count and interval */
54 #define I40E_CHK_Q_ENA_COUNT 1000
55 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
57 /* Maximun number of VSI */
58 #define I40E_MAX_NUM_VSIS (384UL)
60 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
62 /* Flow control default timer */
63 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
65 /* Flow control enable fwd bit */
66 #define I40E_PRTMAC_FWD_CTRL 0x00000001
68 /* Receive Packet Buffer size */
69 #define I40E_RXPBSIZE (968 * 1024)
72 #define I40E_KILOSHIFT 10
74 /* Flow control default high water */
75 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
77 /* Flow control default low water */
78 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
80 /* Receive Average Packet Size in Byte*/
81 #define I40E_PACKET_AVERAGE_SIZE 128
83 /* Mask of PF interrupt causes */
84 #define I40E_PFINT_ICR0_ENA_MASK ( \
85 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
86 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_GRST_MASK | \
88 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
89 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
90 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
91 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
92 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
93 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
95 #define I40E_FLOW_TYPES ( \
96 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
101 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
106 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
108 /* Additional timesync values. */
109 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
110 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
111 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
112 #define I40E_PRTTSYN_TSYNENA 0x80000000
113 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
114 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
117 * Below are values for writing un-exposed registers suggested
120 /* Destination MAC address */
121 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
122 /* Source MAC address */
123 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
124 /* Outer (S-Tag) VLAN tag in the outer L2 header */
125 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
126 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
127 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
128 /* Single VLAN tag in the inner L2 header */
129 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
130 /* Source IPv4 address */
131 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
132 /* Destination IPv4 address */
133 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
134 /* Source IPv4 address for X722 */
135 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
136 /* Destination IPv4 address for X722 */
137 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
138 /* IPv4 Protocol for X722 */
139 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
140 /* IPv4 Time to Live for X722 */
141 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
142 /* IPv4 Type of Service (TOS) */
143 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
145 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
146 /* IPv4 Time to Live */
147 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
148 /* Source IPv6 address */
149 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
150 /* Destination IPv6 address */
151 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
152 /* IPv6 Traffic Class (TC) */
153 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
154 /* IPv6 Next Header */
155 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
157 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
159 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
160 /* Destination L4 port */
161 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
162 /* SCTP verification tag */
163 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
164 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
165 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
166 /* Source port of tunneling UDP */
167 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
168 /* Destination port of tunneling UDP */
169 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
170 /* UDP Tunneling ID, NVGRE/GRE key */
171 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
172 /* Last ether type */
173 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
174 /* Tunneling outer destination IPv4 address */
175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
176 /* Tunneling outer destination IPv6 address */
177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
178 /* 1st word of flex payload */
179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
180 /* 2nd word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
182 /* 3rd word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
184 /* 4th word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
186 /* 5th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
188 /* 6th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
190 /* 7th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
192 /* 8th word of flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
194 /* all 8 words flex payload */
195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
196 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
198 #define I40E_TRANSLATE_INSET 0
199 #define I40E_TRANSLATE_REG 1
201 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
202 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
203 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
204 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
205 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
206 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
208 /* PCI offset for querying capability */
209 #define PCI_DEV_CAP_REG 0xA4
210 /* PCI offset for enabling/disabling Extended Tag */
211 #define PCI_DEV_CTRL_REG 0xA8
212 /* Bit mask of Extended Tag capability */
213 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
214 /* Bit shift of Extended Tag enable/disable */
215 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
216 /* Bit mask of Extended Tag enable/disable */
217 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
219 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
220 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
221 static int i40e_dev_configure(struct rte_eth_dev *dev);
222 static int i40e_dev_start(struct rte_eth_dev *dev);
223 static void i40e_dev_stop(struct rte_eth_dev *dev);
224 static void i40e_dev_close(struct rte_eth_dev *dev);
225 static int i40e_dev_reset(struct rte_eth_dev *dev);
226 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
227 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
228 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
229 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
230 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
232 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
233 struct rte_eth_stats *stats);
234 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
235 struct rte_eth_xstat *xstats, unsigned n);
236 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
237 struct rte_eth_xstat_name *xstats_names,
239 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
240 static int i40e_fw_version_get(struct rte_eth_dev *dev,
241 char *fw_version, size_t fw_size);
242 static int i40e_dev_info_get(struct rte_eth_dev *dev,
243 struct rte_eth_dev_info *dev_info);
244 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
247 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
248 enum rte_vlan_type vlan_type,
250 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
251 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
254 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
255 static int i40e_dev_led_on(struct rte_eth_dev *dev);
256 static int i40e_dev_led_off(struct rte_eth_dev *dev);
257 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
258 struct rte_eth_fc_conf *fc_conf);
259 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
260 struct rte_eth_fc_conf *fc_conf);
261 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
262 struct rte_eth_pfc_conf *pfc_conf);
263 static int i40e_macaddr_add(struct rte_eth_dev *dev,
264 struct rte_ether_addr *mac_addr,
267 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
268 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
269 struct rte_eth_rss_reta_entry64 *reta_conf,
271 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
272 struct rte_eth_rss_reta_entry64 *reta_conf,
275 static int i40e_get_cap(struct i40e_hw *hw);
276 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
277 static int i40e_pf_setup(struct i40e_pf *pf);
278 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
279 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
280 static int i40e_dcb_setup(struct rte_eth_dev *dev);
281 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
282 bool offset_loaded, uint64_t *offset, uint64_t *stat);
283 static void i40e_stat_update_48(struct i40e_hw *hw,
289 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
290 static void i40e_dev_interrupt_handler(void *param);
291 static void i40e_dev_alarm_handler(void *param);
292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
293 uint32_t base, uint32_t num);
294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
300 static int i40e_veb_release(struct i40e_veb *veb);
301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
302 struct i40e_vsi *vsi);
303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
306 struct i40e_macvlan_filter *mv_f,
309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
311 struct rte_eth_rss_conf *rss_conf);
312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
313 struct rte_eth_rss_conf *rss_conf);
314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
315 struct rte_eth_udp_tunnel *udp_tunnel);
316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
317 struct rte_eth_udp_tunnel *udp_tunnel);
318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
320 enum rte_filter_op filter_op,
322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
323 enum rte_filter_type filter_type,
324 enum rte_filter_op filter_op,
326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
327 struct rte_eth_dcb_info *dcb_info);
328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
329 static void i40e_configure_registers(struct i40e_hw *hw);
330 static void i40e_hw_init(struct rte_eth_dev *dev);
331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
339 struct rte_eth_mirror_conf *mirror_conf,
340 uint8_t sw_id, uint8_t on);
341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
346 struct timespec *timestamp,
348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
349 struct timespec *timestamp);
350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
355 struct timespec *timestamp);
356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
357 const struct timespec *timestamp);
359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
364 static int i40e_get_regs(struct rte_eth_dev *dev,
365 struct rte_dev_reg_info *regs);
367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
370 struct rte_dev_eeprom_info *eeprom);
372 static int i40e_get_module_info(struct rte_eth_dev *dev,
373 struct rte_eth_dev_module_info *modinfo);
374 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
375 struct rte_dev_eeprom_info *info);
377 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
378 struct rte_ether_addr *mac_addr);
380 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
382 static int i40e_ethertype_filter_convert(
383 const struct rte_eth_ethertype_filter *input,
384 struct i40e_ethertype_filter *filter);
385 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
386 struct i40e_ethertype_filter *filter);
388 static int i40e_tunnel_filter_convert(
389 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
390 struct i40e_tunnel_filter *tunnel_filter);
391 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
392 struct i40e_tunnel_filter *tunnel_filter);
393 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
395 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
396 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
397 static void i40e_filter_restore(struct i40e_pf *pf);
398 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
400 int i40e_logtype_init;
401 int i40e_logtype_driver;
403 static const char *const valid_keys[] = {
404 ETH_I40E_FLOATING_VEB_ARG,
405 ETH_I40E_FLOATING_VEB_LIST_ARG,
406 ETH_I40E_SUPPORT_MULTI_DRIVER,
407 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
408 ETH_I40E_USE_LATEST_VEC,
411 static const struct rte_pci_id pci_id_i40e_map[] = {
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
435 { .vendor_id = 0, /* sentinel */ },
438 static const struct eth_dev_ops i40e_eth_dev_ops = {
439 .dev_configure = i40e_dev_configure,
440 .dev_start = i40e_dev_start,
441 .dev_stop = i40e_dev_stop,
442 .dev_close = i40e_dev_close,
443 .dev_reset = i40e_dev_reset,
444 .promiscuous_enable = i40e_dev_promiscuous_enable,
445 .promiscuous_disable = i40e_dev_promiscuous_disable,
446 .allmulticast_enable = i40e_dev_allmulticast_enable,
447 .allmulticast_disable = i40e_dev_allmulticast_disable,
448 .dev_set_link_up = i40e_dev_set_link_up,
449 .dev_set_link_down = i40e_dev_set_link_down,
450 .link_update = i40e_dev_link_update,
451 .stats_get = i40e_dev_stats_get,
452 .xstats_get = i40e_dev_xstats_get,
453 .xstats_get_names = i40e_dev_xstats_get_names,
454 .stats_reset = i40e_dev_stats_reset,
455 .xstats_reset = i40e_dev_stats_reset,
456 .fw_version_get = i40e_fw_version_get,
457 .dev_infos_get = i40e_dev_info_get,
458 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
459 .vlan_filter_set = i40e_vlan_filter_set,
460 .vlan_tpid_set = i40e_vlan_tpid_set,
461 .vlan_offload_set = i40e_vlan_offload_set,
462 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
463 .vlan_pvid_set = i40e_vlan_pvid_set,
464 .rx_queue_start = i40e_dev_rx_queue_start,
465 .rx_queue_stop = i40e_dev_rx_queue_stop,
466 .tx_queue_start = i40e_dev_tx_queue_start,
467 .tx_queue_stop = i40e_dev_tx_queue_stop,
468 .rx_queue_setup = i40e_dev_rx_queue_setup,
469 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
470 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
471 .rx_queue_release = i40e_dev_rx_queue_release,
472 .rx_queue_count = i40e_dev_rx_queue_count,
473 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
474 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
475 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
476 .tx_queue_setup = i40e_dev_tx_queue_setup,
477 .tx_queue_release = i40e_dev_tx_queue_release,
478 .dev_led_on = i40e_dev_led_on,
479 .dev_led_off = i40e_dev_led_off,
480 .flow_ctrl_get = i40e_flow_ctrl_get,
481 .flow_ctrl_set = i40e_flow_ctrl_set,
482 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
483 .mac_addr_add = i40e_macaddr_add,
484 .mac_addr_remove = i40e_macaddr_remove,
485 .reta_update = i40e_dev_rss_reta_update,
486 .reta_query = i40e_dev_rss_reta_query,
487 .rss_hash_update = i40e_dev_rss_hash_update,
488 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
489 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
490 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
491 .filter_ctrl = i40e_dev_filter_ctrl,
492 .rxq_info_get = i40e_rxq_info_get,
493 .txq_info_get = i40e_txq_info_get,
494 .mirror_rule_set = i40e_mirror_rule_set,
495 .mirror_rule_reset = i40e_mirror_rule_reset,
496 .timesync_enable = i40e_timesync_enable,
497 .timesync_disable = i40e_timesync_disable,
498 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
499 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
500 .get_dcb_info = i40e_dev_get_dcb_info,
501 .timesync_adjust_time = i40e_timesync_adjust_time,
502 .timesync_read_time = i40e_timesync_read_time,
503 .timesync_write_time = i40e_timesync_write_time,
504 .get_reg = i40e_get_regs,
505 .get_eeprom_length = i40e_get_eeprom_length,
506 .get_eeprom = i40e_get_eeprom,
507 .get_module_info = i40e_get_module_info,
508 .get_module_eeprom = i40e_get_module_eeprom,
509 .mac_addr_set = i40e_set_default_mac_addr,
510 .mtu_set = i40e_dev_mtu_set,
511 .tm_ops_get = i40e_tm_ops_get,
514 /* store statistics names and its offset in stats structure */
515 struct rte_i40e_xstats_name_off {
516 char name[RTE_ETH_XSTATS_NAME_SIZE];
520 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
521 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
522 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
523 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
524 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
525 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
526 rx_unknown_protocol)},
527 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
528 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
529 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
530 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
533 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
534 sizeof(rte_i40e_stats_strings[0]))
536 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
537 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
538 tx_dropped_link_down)},
539 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
540 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
542 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
543 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
545 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
547 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
549 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
550 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
551 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
552 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
553 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
554 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
556 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
558 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
560 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
568 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
570 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
571 mac_short_packet_dropped)},
572 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
574 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
575 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
576 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
578 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
580 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
582 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
588 {"rx_flow_director_atr_match_packets",
589 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
590 {"rx_flow_director_sb_match_packets",
591 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
592 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
594 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
596 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
598 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
602 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
603 sizeof(rte_i40e_hw_port_strings[0]))
605 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
606 {"xon_packets", offsetof(struct i40e_hw_port_stats,
608 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
612 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
613 sizeof(rte_i40e_rxq_prio_strings[0]))
615 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
616 {"xon_packets", offsetof(struct i40e_hw_port_stats,
618 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
620 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
621 priority_xon_2_xoff)},
624 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
625 sizeof(rte_i40e_txq_prio_strings[0]))
628 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
629 struct rte_pci_device *pci_dev)
631 char name[RTE_ETH_NAME_MAX_LEN];
632 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
635 if (pci_dev->device.devargs) {
636 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
642 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
643 sizeof(struct i40e_adapter),
644 eth_dev_pci_specific_init, pci_dev,
645 eth_i40e_dev_init, NULL);
647 if (retval || eth_da.nb_representor_ports < 1)
650 /* probe VF representor ports */
651 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
652 pci_dev->device.name);
654 if (pf_ethdev == NULL)
657 for (i = 0; i < eth_da.nb_representor_ports; i++) {
658 struct i40e_vf_representor representor = {
659 .vf_id = eth_da.representor_ports[i],
660 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
661 pf_ethdev->data->dev_private)->switch_domain_id,
662 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
663 pf_ethdev->data->dev_private)
666 /* representor port net_bdf_port */
667 snprintf(name, sizeof(name), "net_%s_representor_%d",
668 pci_dev->device.name, eth_da.representor_ports[i]);
670 retval = rte_eth_dev_create(&pci_dev->device, name,
671 sizeof(struct i40e_vf_representor), NULL, NULL,
672 i40e_vf_representor_init, &representor);
675 PMD_DRV_LOG(ERR, "failed to create i40e vf "
676 "representor %s.", name);
682 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
684 struct rte_eth_dev *ethdev;
686 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
691 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
692 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
694 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
697 static struct rte_pci_driver rte_i40e_pmd = {
698 .id_table = pci_id_i40e_map,
699 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
700 .probe = eth_i40e_pci_probe,
701 .remove = eth_i40e_pci_remove,
705 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
708 uint32_t ori_reg_val;
709 struct rte_eth_dev *dev;
711 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
712 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
713 i40e_write_rx_ctl(hw, reg_addr, reg_val);
714 if (ori_reg_val != reg_val)
716 "i40e device %s changed global register [0x%08x]."
717 " original: 0x%08x, new: 0x%08x",
718 dev->device->name, reg_addr, ori_reg_val, reg_val);
721 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
722 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
723 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
725 #ifndef I40E_GLQF_ORT
726 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
728 #ifndef I40E_GLQF_PIT
729 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
731 #ifndef I40E_GLQF_L3_MAP
732 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
735 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
738 * Initialize registers for parsing packet type of QinQ
739 * This should be removed from code once proper
740 * configuration API is added to avoid configuration conflicts
741 * between ports of the same device.
743 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
744 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
747 static inline void i40e_config_automask(struct i40e_pf *pf)
749 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
752 /* INTENA flag is not auto-cleared for interrupt */
753 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
754 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
755 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
757 /* If support multi-driver, PF will use INT0. */
758 if (!pf->support_multi_driver)
759 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
761 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
764 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
767 * Add a ethertype filter to drop all flow control frames transmitted
771 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
773 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
774 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
775 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
776 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
779 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
780 I40E_FLOW_CONTROL_ETHERTYPE, flags,
781 pf->main_vsi_seid, 0,
785 "Failed to add filter to drop flow control frames from VSIs.");
789 floating_veb_list_handler(__rte_unused const char *key,
790 const char *floating_veb_value,
794 unsigned int count = 0;
797 bool *vf_floating_veb = opaque;
799 while (isblank(*floating_veb_value))
800 floating_veb_value++;
802 /* Reset floating VEB configuration for VFs */
803 for (idx = 0; idx < I40E_MAX_VF; idx++)
804 vf_floating_veb[idx] = false;
808 while (isblank(*floating_veb_value))
809 floating_veb_value++;
810 if (*floating_veb_value == '\0')
813 idx = strtoul(floating_veb_value, &end, 10);
814 if (errno || end == NULL)
816 while (isblank(*end))
820 } else if ((*end == ';') || (*end == '\0')) {
822 if (min == I40E_MAX_VF)
824 if (max >= I40E_MAX_VF)
825 max = I40E_MAX_VF - 1;
826 for (idx = min; idx <= max; idx++) {
827 vf_floating_veb[idx] = true;
834 floating_veb_value = end + 1;
835 } while (*end != '\0');
844 config_vf_floating_veb(struct rte_devargs *devargs,
845 uint16_t floating_veb,
846 bool *vf_floating_veb)
848 struct rte_kvargs *kvlist;
850 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
854 /* All the VFs attach to the floating VEB by default
855 * when the floating VEB is enabled.
857 for (i = 0; i < I40E_MAX_VF; i++)
858 vf_floating_veb[i] = true;
863 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
867 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
868 rte_kvargs_free(kvlist);
871 /* When the floating_veb_list parameter exists, all the VFs
872 * will attach to the legacy VEB firstly, then configure VFs
873 * to the floating VEB according to the floating_veb_list.
875 if (rte_kvargs_process(kvlist, floating_veb_list,
876 floating_veb_list_handler,
877 vf_floating_veb) < 0) {
878 rte_kvargs_free(kvlist);
881 rte_kvargs_free(kvlist);
885 i40e_check_floating_handler(__rte_unused const char *key,
887 __rte_unused void *opaque)
889 if (strcmp(value, "1"))
896 is_floating_veb_supported(struct rte_devargs *devargs)
898 struct rte_kvargs *kvlist;
899 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
904 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
908 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
909 rte_kvargs_free(kvlist);
912 /* Floating VEB is enabled when there's key-value:
913 * enable_floating_veb=1
915 if (rte_kvargs_process(kvlist, floating_veb_key,
916 i40e_check_floating_handler, NULL) < 0) {
917 rte_kvargs_free(kvlist);
920 rte_kvargs_free(kvlist);
926 config_floating_veb(struct rte_eth_dev *dev)
928 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
929 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
930 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
932 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
934 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
936 is_floating_veb_supported(pci_dev->device.devargs);
937 config_vf_floating_veb(pci_dev->device.devargs,
939 pf->floating_veb_list);
941 pf->floating_veb = false;
945 #define I40E_L2_TAGS_S_TAG_SHIFT 1
946 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
949 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
951 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
952 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
953 char ethertype_hash_name[RTE_HASH_NAMESIZE];
956 struct rte_hash_parameters ethertype_hash_params = {
957 .name = ethertype_hash_name,
958 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
959 .key_len = sizeof(struct i40e_ethertype_filter_input),
960 .hash_func = rte_hash_crc,
961 .hash_func_init_val = 0,
962 .socket_id = rte_socket_id(),
965 /* Initialize ethertype filter rule list and hash */
966 TAILQ_INIT(ðertype_rule->ethertype_list);
967 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
968 "ethertype_%s", dev->device->name);
969 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
970 if (!ethertype_rule->hash_table) {
971 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
974 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
975 sizeof(struct i40e_ethertype_filter *) *
976 I40E_MAX_ETHERTYPE_FILTER_NUM,
978 if (!ethertype_rule->hash_map) {
980 "Failed to allocate memory for ethertype hash map!");
982 goto err_ethertype_hash_map_alloc;
987 err_ethertype_hash_map_alloc:
988 rte_hash_free(ethertype_rule->hash_table);
994 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
996 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
997 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
998 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1001 struct rte_hash_parameters tunnel_hash_params = {
1002 .name = tunnel_hash_name,
1003 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1004 .key_len = sizeof(struct i40e_tunnel_filter_input),
1005 .hash_func = rte_hash_crc,
1006 .hash_func_init_val = 0,
1007 .socket_id = rte_socket_id(),
1010 /* Initialize tunnel filter rule list and hash */
1011 TAILQ_INIT(&tunnel_rule->tunnel_list);
1012 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1013 "tunnel_%s", dev->device->name);
1014 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1015 if (!tunnel_rule->hash_table) {
1016 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1019 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1020 sizeof(struct i40e_tunnel_filter *) *
1021 I40E_MAX_TUNNEL_FILTER_NUM,
1023 if (!tunnel_rule->hash_map) {
1025 "Failed to allocate memory for tunnel hash map!");
1027 goto err_tunnel_hash_map_alloc;
1032 err_tunnel_hash_map_alloc:
1033 rte_hash_free(tunnel_rule->hash_table);
1039 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1042 struct i40e_fdir_info *fdir_info = &pf->fdir;
1043 char fdir_hash_name[RTE_HASH_NAMESIZE];
1046 struct rte_hash_parameters fdir_hash_params = {
1047 .name = fdir_hash_name,
1048 .entries = I40E_MAX_FDIR_FILTER_NUM,
1049 .key_len = sizeof(struct i40e_fdir_input),
1050 .hash_func = rte_hash_crc,
1051 .hash_func_init_val = 0,
1052 .socket_id = rte_socket_id(),
1055 /* Initialize flow director filter rule list and hash */
1056 TAILQ_INIT(&fdir_info->fdir_list);
1057 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1058 "fdir_%s", dev->device->name);
1059 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1060 if (!fdir_info->hash_table) {
1061 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1064 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1065 sizeof(struct i40e_fdir_filter *) *
1066 I40E_MAX_FDIR_FILTER_NUM,
1068 if (!fdir_info->hash_map) {
1070 "Failed to allocate memory for fdir hash map!");
1072 goto err_fdir_hash_map_alloc;
1076 err_fdir_hash_map_alloc:
1077 rte_hash_free(fdir_info->hash_table);
1083 i40e_init_customized_info(struct i40e_pf *pf)
1087 /* Initialize customized pctype */
1088 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1089 pf->customized_pctype[i].index = i;
1090 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1091 pf->customized_pctype[i].valid = false;
1094 pf->gtp_support = false;
1098 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1100 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1101 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1102 struct i40e_queue_regions *info = &pf->queue_region;
1105 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1106 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1108 memset(info, 0, sizeof(struct i40e_queue_regions));
1112 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1117 unsigned long support_multi_driver;
1120 pf = (struct i40e_pf *)opaque;
1123 support_multi_driver = strtoul(value, &end, 10);
1124 if (errno != 0 || end == value || *end != 0) {
1125 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1129 if (support_multi_driver == 1 || support_multi_driver == 0)
1130 pf->support_multi_driver = (bool)support_multi_driver;
1132 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1133 "enable global configuration by default."
1134 ETH_I40E_SUPPORT_MULTI_DRIVER);
1139 i40e_support_multi_driver(struct rte_eth_dev *dev)
1141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1142 struct rte_kvargs *kvlist;
1145 /* Enable global configuration by default */
1146 pf->support_multi_driver = false;
1148 if (!dev->device->devargs)
1151 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1155 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1156 if (!kvargs_count) {
1157 rte_kvargs_free(kvlist);
1161 if (kvargs_count > 1)
1162 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1163 "the first invalid or last valid one is used !",
1164 ETH_I40E_SUPPORT_MULTI_DRIVER);
1166 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1167 i40e_parse_multi_drv_handler, pf) < 0) {
1168 rte_kvargs_free(kvlist);
1172 rte_kvargs_free(kvlist);
1177 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1178 uint32_t reg_addr, uint64_t reg_val,
1179 struct i40e_asq_cmd_details *cmd_details)
1181 uint64_t ori_reg_val;
1182 struct rte_eth_dev *dev;
1185 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1186 if (ret != I40E_SUCCESS) {
1188 "Fail to debug read from 0x%08x",
1192 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1194 if (ori_reg_val != reg_val)
1195 PMD_DRV_LOG(WARNING,
1196 "i40e device %s changed global register [0x%08x]."
1197 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1198 dev->device->name, reg_addr, ori_reg_val, reg_val);
1200 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1204 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1208 struct i40e_adapter *ad = opaque;
1211 use_latest_vec = atoi(value);
1213 if (use_latest_vec != 0 && use_latest_vec != 1)
1214 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1216 ad->use_latest_vec = (uint8_t)use_latest_vec;
1222 i40e_use_latest_vec(struct rte_eth_dev *dev)
1224 struct i40e_adapter *ad =
1225 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1226 struct rte_kvargs *kvlist;
1229 ad->use_latest_vec = false;
1231 if (!dev->device->devargs)
1234 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1238 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1239 if (!kvargs_count) {
1240 rte_kvargs_free(kvlist);
1244 if (kvargs_count > 1)
1245 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1246 "the first invalid or last valid one is used !",
1247 ETH_I40E_USE_LATEST_VEC);
1249 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1250 i40e_parse_latest_vec_handler, ad) < 0) {
1251 rte_kvargs_free(kvlist);
1255 rte_kvargs_free(kvlist);
1259 #define I40E_ALARM_INTERVAL 50000 /* us */
1262 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1264 struct rte_pci_device *pci_dev;
1265 struct rte_intr_handle *intr_handle;
1266 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1267 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1268 struct i40e_vsi *vsi;
1271 uint8_t aq_fail = 0;
1273 PMD_INIT_FUNC_TRACE();
1275 dev->dev_ops = &i40e_eth_dev_ops;
1276 dev->rx_pkt_burst = i40e_recv_pkts;
1277 dev->tx_pkt_burst = i40e_xmit_pkts;
1278 dev->tx_pkt_prepare = i40e_prep_pkts;
1280 /* for secondary processes, we don't initialise any further as primary
1281 * has already done this work. Only check we don't need a different
1283 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1284 i40e_set_rx_function(dev);
1285 i40e_set_tx_function(dev);
1288 i40e_set_default_ptype_table(dev);
1289 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1290 intr_handle = &pci_dev->intr_handle;
1292 rte_eth_copy_pci_info(dev, pci_dev);
1294 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1295 pf->adapter->eth_dev = dev;
1296 pf->dev_data = dev->data;
1298 hw->back = I40E_PF_TO_ADAPTER(pf);
1299 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1302 "Hardware is not available, as address is NULL");
1306 hw->vendor_id = pci_dev->id.vendor_id;
1307 hw->device_id = pci_dev->id.device_id;
1308 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1309 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1310 hw->bus.device = pci_dev->addr.devid;
1311 hw->bus.func = pci_dev->addr.function;
1312 hw->adapter_stopped = 0;
1313 hw->adapter_closed = 0;
1316 * Switch Tag value should not be identical to either the First Tag
1317 * or Second Tag values. So set something other than common Ethertype
1318 * for internal switching.
1320 hw->switch_tag = 0xffff;
1322 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1323 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1324 PMD_INIT_LOG(ERR, "\nERROR: "
1325 "Firmware recovery mode detected. Limiting functionality.\n"
1326 "Refer to the Intel(R) Ethernet Adapters and Devices "
1327 "User Guide for details on firmware recovery mode.");
1331 /* Check if need to support multi-driver */
1332 i40e_support_multi_driver(dev);
1333 /* Check if users want the latest supported vec path */
1334 i40e_use_latest_vec(dev);
1336 /* Make sure all is clean before doing PF reset */
1339 /* Reset here to make sure all is clean for each PF */
1340 ret = i40e_pf_reset(hw);
1342 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1346 /* Initialize the shared code (base driver) */
1347 ret = i40e_init_shared_code(hw);
1349 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1353 /* Initialize the parameters for adminq */
1354 i40e_init_adminq_parameter(hw);
1355 ret = i40e_init_adminq(hw);
1356 if (ret != I40E_SUCCESS) {
1357 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1360 /* Firmware of SFP x722 does not support adminq option */
1361 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1362 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1364 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1365 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1366 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1367 ((hw->nvm.version >> 12) & 0xf),
1368 ((hw->nvm.version >> 4) & 0xff),
1369 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1371 /* Initialize the hardware */
1374 i40e_config_automask(pf);
1376 i40e_set_default_pctype_table(dev);
1379 * To work around the NVM issue, initialize registers
1380 * for packet type of QinQ by software.
1381 * It should be removed once issues are fixed in NVM.
1383 if (!pf->support_multi_driver)
1384 i40e_GLQF_reg_init(hw);
1386 /* Initialize the input set for filters (hash and fd) to default value */
1387 i40e_filter_input_set_init(pf);
1389 /* initialise the L3_MAP register */
1390 if (!pf->support_multi_driver) {
1391 ret = i40e_aq_debug_write_global_register(hw,
1392 I40E_GLQF_L3_MAP(40),
1395 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1398 "Global register 0x%08x is changed with 0x28",
1399 I40E_GLQF_L3_MAP(40));
1402 /* Need the special FW version to support floating VEB */
1403 config_floating_veb(dev);
1404 /* Clear PXE mode */
1405 i40e_clear_pxe_mode(hw);
1406 i40e_dev_sync_phy_type(hw);
1409 * On X710, performance number is far from the expectation on recent
1410 * firmware versions. The fix for this issue may not be integrated in
1411 * the following firmware version. So the workaround in software driver
1412 * is needed. It needs to modify the initial values of 3 internal only
1413 * registers. Note that the workaround can be removed when it is fixed
1414 * in firmware in the future.
1416 i40e_configure_registers(hw);
1418 /* Get hw capabilities */
1419 ret = i40e_get_cap(hw);
1420 if (ret != I40E_SUCCESS) {
1421 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1422 goto err_get_capabilities;
1425 /* Initialize parameters for PF */
1426 ret = i40e_pf_parameter_init(dev);
1428 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1429 goto err_parameter_init;
1432 /* Initialize the queue management */
1433 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1435 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1436 goto err_qp_pool_init;
1438 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1439 hw->func_caps.num_msix_vectors - 1);
1441 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1442 goto err_msix_pool_init;
1445 /* Initialize lan hmc */
1446 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1447 hw->func_caps.num_rx_qp, 0, 0);
1448 if (ret != I40E_SUCCESS) {
1449 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1450 goto err_init_lan_hmc;
1453 /* Configure lan hmc */
1454 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1455 if (ret != I40E_SUCCESS) {
1456 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1457 goto err_configure_lan_hmc;
1460 /* Get and check the mac address */
1461 i40e_get_mac_addr(hw, hw->mac.addr);
1462 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1463 PMD_INIT_LOG(ERR, "mac address is not valid");
1465 goto err_get_mac_addr;
1467 /* Copy the permanent MAC address */
1468 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1469 (struct rte_ether_addr *)hw->mac.perm_addr);
1471 /* Disable flow control */
1472 hw->fc.requested_mode = I40E_FC_NONE;
1473 i40e_set_fc(hw, &aq_fail, TRUE);
1475 /* Set the global registers with default ether type value */
1476 if (!pf->support_multi_driver) {
1477 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1478 RTE_ETHER_TYPE_VLAN);
1479 if (ret != I40E_SUCCESS) {
1481 "Failed to set the default outer "
1483 goto err_setup_pf_switch;
1487 /* PF setup, which includes VSI setup */
1488 ret = i40e_pf_setup(pf);
1490 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1491 goto err_setup_pf_switch;
1496 /* Disable double vlan by default */
1497 i40e_vsi_config_double_vlan(vsi, FALSE);
1499 /* Disable S-TAG identification when floating_veb is disabled */
1500 if (!pf->floating_veb) {
1501 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1502 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1503 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1504 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1508 if (!vsi->max_macaddrs)
1509 len = RTE_ETHER_ADDR_LEN;
1511 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1513 /* Should be after VSI initialized */
1514 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1515 if (!dev->data->mac_addrs) {
1517 "Failed to allocated memory for storing mac address");
1520 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1521 &dev->data->mac_addrs[0]);
1523 /* Init dcb to sw mode by default */
1524 ret = i40e_dcb_init_configure(dev, TRUE);
1525 if (ret != I40E_SUCCESS) {
1526 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1527 pf->flags &= ~I40E_FLAG_DCB;
1529 /* Update HW struct after DCB configuration */
1532 /* initialize pf host driver to setup SRIOV resource if applicable */
1533 i40e_pf_host_init(dev);
1535 /* register callback func to eal lib */
1536 rte_intr_callback_register(intr_handle,
1537 i40e_dev_interrupt_handler, dev);
1539 /* configure and enable device interrupt */
1540 i40e_pf_config_irq0(hw, TRUE);
1541 i40e_pf_enable_irq0(hw);
1543 /* enable uio intr after callback register */
1544 rte_intr_enable(intr_handle);
1546 /* By default disable flexible payload in global configuration */
1547 if (!pf->support_multi_driver)
1548 i40e_flex_payload_reg_set_default(hw);
1551 * Add an ethertype filter to drop all flow control frames transmitted
1552 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1555 i40e_add_tx_flow_control_drop_filter(pf);
1557 /* Set the max frame size to 0x2600 by default,
1558 * in case other drivers changed the default value.
1560 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1562 /* initialize mirror rule list */
1563 TAILQ_INIT(&pf->mirror_list);
1565 /* initialize Traffic Manager configuration */
1566 i40e_tm_conf_init(dev);
1568 /* Initialize customized information */
1569 i40e_init_customized_info(pf);
1571 ret = i40e_init_ethtype_filter_list(dev);
1573 goto err_init_ethtype_filter_list;
1574 ret = i40e_init_tunnel_filter_list(dev);
1576 goto err_init_tunnel_filter_list;
1577 ret = i40e_init_fdir_filter_list(dev);
1579 goto err_init_fdir_filter_list;
1581 /* initialize queue region configuration */
1582 i40e_init_queue_region_conf(dev);
1584 /* initialize rss configuration from rte_flow */
1585 memset(&pf->rss_info, 0,
1586 sizeof(struct i40e_rte_flow_rss_conf));
1588 /* reset all stats of the device, including pf and main vsi */
1589 i40e_dev_stats_reset(dev);
1593 err_init_fdir_filter_list:
1594 rte_free(pf->tunnel.hash_table);
1595 rte_free(pf->tunnel.hash_map);
1596 err_init_tunnel_filter_list:
1597 rte_free(pf->ethertype.hash_table);
1598 rte_free(pf->ethertype.hash_map);
1599 err_init_ethtype_filter_list:
1600 rte_free(dev->data->mac_addrs);
1601 dev->data->mac_addrs = NULL;
1603 i40e_vsi_release(pf->main_vsi);
1604 err_setup_pf_switch:
1606 err_configure_lan_hmc:
1607 (void)i40e_shutdown_lan_hmc(hw);
1609 i40e_res_pool_destroy(&pf->msix_pool);
1611 i40e_res_pool_destroy(&pf->qp_pool);
1614 err_get_capabilities:
1615 (void)i40e_shutdown_adminq(hw);
1621 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1623 struct i40e_ethertype_filter *p_ethertype;
1624 struct i40e_ethertype_rule *ethertype_rule;
1626 ethertype_rule = &pf->ethertype;
1627 /* Remove all ethertype filter rules and hash */
1628 if (ethertype_rule->hash_map)
1629 rte_free(ethertype_rule->hash_map);
1630 if (ethertype_rule->hash_table)
1631 rte_hash_free(ethertype_rule->hash_table);
1633 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1634 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1635 p_ethertype, rules);
1636 rte_free(p_ethertype);
1641 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1643 struct i40e_tunnel_filter *p_tunnel;
1644 struct i40e_tunnel_rule *tunnel_rule;
1646 tunnel_rule = &pf->tunnel;
1647 /* Remove all tunnel director rules and hash */
1648 if (tunnel_rule->hash_map)
1649 rte_free(tunnel_rule->hash_map);
1650 if (tunnel_rule->hash_table)
1651 rte_hash_free(tunnel_rule->hash_table);
1653 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1654 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1660 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1662 struct i40e_fdir_filter *p_fdir;
1663 struct i40e_fdir_info *fdir_info;
1665 fdir_info = &pf->fdir;
1666 /* Remove all flow director rules and hash */
1667 if (fdir_info->hash_map)
1668 rte_free(fdir_info->hash_map);
1669 if (fdir_info->hash_table)
1670 rte_hash_free(fdir_info->hash_table);
1672 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1673 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1678 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1681 * Disable by default flexible payload
1682 * for corresponding L2/L3/L4 layers.
1684 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1685 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1686 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1690 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1693 struct rte_pci_device *pci_dev;
1694 struct rte_intr_handle *intr_handle;
1696 struct i40e_filter_control_settings settings;
1697 struct rte_flow *p_flow;
1699 uint8_t aq_fail = 0;
1702 PMD_INIT_FUNC_TRACE();
1704 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1707 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1708 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1710 intr_handle = &pci_dev->intr_handle;
1712 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1714 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1716 if (hw->adapter_closed == 0)
1717 i40e_dev_close(dev);
1719 dev->dev_ops = NULL;
1720 dev->rx_pkt_burst = NULL;
1721 dev->tx_pkt_burst = NULL;
1723 /* Clear PXE mode */
1724 i40e_clear_pxe_mode(hw);
1726 /* Unconfigure filter control */
1727 memset(&settings, 0, sizeof(settings));
1728 ret = i40e_set_filter_control(hw, &settings);
1730 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1733 /* Disable flow control */
1734 hw->fc.requested_mode = I40E_FC_NONE;
1735 i40e_set_fc(hw, &aq_fail, TRUE);
1737 /* uninitialize pf host driver */
1738 i40e_pf_host_uninit(dev);
1740 /* disable uio intr before callback unregister */
1741 rte_intr_disable(intr_handle);
1743 /* unregister callback func to eal lib */
1745 ret = rte_intr_callback_unregister(intr_handle,
1746 i40e_dev_interrupt_handler, dev);
1749 } else if (ret != -EAGAIN) {
1751 "intr callback unregister failed: %d",
1755 i40e_msec_delay(500);
1756 } while (retries++ < 5);
1758 i40e_rm_ethtype_filter_list(pf);
1759 i40e_rm_tunnel_filter_list(pf);
1760 i40e_rm_fdir_filter_list(pf);
1762 /* Remove all flows */
1763 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1764 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1768 /* Remove all Traffic Manager configuration */
1769 i40e_tm_conf_uninit(dev);
1775 i40e_dev_configure(struct rte_eth_dev *dev)
1777 struct i40e_adapter *ad =
1778 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1779 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1780 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1781 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1784 ret = i40e_dev_sync_phy_type(hw);
1788 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1789 * bulk allocation or vector Rx preconditions we will reset it.
1791 ad->rx_bulk_alloc_allowed = true;
1792 ad->rx_vec_allowed = true;
1793 ad->tx_simple_allowed = true;
1794 ad->tx_vec_allowed = true;
1796 /* Only legacy filter API needs the following fdir config. So when the
1797 * legacy filter API is deprecated, the following codes should also be
1800 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1801 ret = i40e_fdir_setup(pf);
1802 if (ret != I40E_SUCCESS) {
1803 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1806 ret = i40e_fdir_configure(dev);
1808 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1812 i40e_fdir_teardown(pf);
1814 ret = i40e_dev_init_vlan(dev);
1819 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1820 * RSS setting have different requirements.
1821 * General PMD driver call sequence are NIC init, configure,
1822 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1823 * will try to lookup the VSI that specific queue belongs to if VMDQ
1824 * applicable. So, VMDQ setting has to be done before
1825 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1826 * For RSS setting, it will try to calculate actual configured RX queue
1827 * number, which will be available after rx_queue_setup(). dev_start()
1828 * function is good to place RSS setup.
1830 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1831 ret = i40e_vmdq_setup(dev);
1836 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1837 ret = i40e_dcb_setup(dev);
1839 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1844 TAILQ_INIT(&pf->flow_list);
1849 /* need to release vmdq resource if exists */
1850 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1851 i40e_vsi_release(pf->vmdq[i].vsi);
1852 pf->vmdq[i].vsi = NULL;
1857 /* Need to release fdir resource if exists.
1858 * Only legacy filter API needs the following fdir config. So when the
1859 * legacy filter API is deprecated, the following code should also be
1862 i40e_fdir_teardown(pf);
1867 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1869 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1870 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1871 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1872 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1873 uint16_t msix_vect = vsi->msix_intr;
1876 for (i = 0; i < vsi->nb_qps; i++) {
1877 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1878 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1882 if (vsi->type != I40E_VSI_SRIOV) {
1883 if (!rte_intr_allow_others(intr_handle)) {
1884 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1885 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1887 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1890 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1891 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1893 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1898 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1899 vsi->user_param + (msix_vect - 1);
1901 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1902 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1904 I40E_WRITE_FLUSH(hw);
1908 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1909 int base_queue, int nb_queue,
1914 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1915 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1917 /* Bind all RX queues to allocated MSIX interrupt */
1918 for (i = 0; i < nb_queue; i++) {
1919 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1920 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1921 ((base_queue + i + 1) <<
1922 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1923 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1924 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1926 if (i == nb_queue - 1)
1927 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1928 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1931 /* Write first RX queue to Link list register as the head element */
1932 if (vsi->type != I40E_VSI_SRIOV) {
1934 i40e_calc_itr_interval(1, pf->support_multi_driver);
1936 if (msix_vect == I40E_MISC_VEC_ID) {
1937 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1939 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1941 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1943 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1946 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1948 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1950 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1952 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1959 if (msix_vect == I40E_MISC_VEC_ID) {
1961 I40E_VPINT_LNKLST0(vsi->user_param),
1963 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1965 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1967 /* num_msix_vectors_vf needs to minus irq0 */
1968 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1969 vsi->user_param + (msix_vect - 1);
1971 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1973 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1975 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1979 I40E_WRITE_FLUSH(hw);
1983 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1985 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1986 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1987 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1988 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1989 uint16_t msix_vect = vsi->msix_intr;
1990 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1991 uint16_t queue_idx = 0;
1995 for (i = 0; i < vsi->nb_qps; i++) {
1996 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1997 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2000 /* VF bind interrupt */
2001 if (vsi->type == I40E_VSI_SRIOV) {
2002 __vsi_queues_bind_intr(vsi, msix_vect,
2003 vsi->base_queue, vsi->nb_qps,
2008 /* PF & VMDq bind interrupt */
2009 if (rte_intr_dp_is_en(intr_handle)) {
2010 if (vsi->type == I40E_VSI_MAIN) {
2013 } else if (vsi->type == I40E_VSI_VMDQ2) {
2014 struct i40e_vsi *main_vsi =
2015 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2016 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2021 for (i = 0; i < vsi->nb_used_qps; i++) {
2023 if (!rte_intr_allow_others(intr_handle))
2024 /* allow to share MISC_VEC_ID */
2025 msix_vect = I40E_MISC_VEC_ID;
2027 /* no enough msix_vect, map all to one */
2028 __vsi_queues_bind_intr(vsi, msix_vect,
2029 vsi->base_queue + i,
2030 vsi->nb_used_qps - i,
2032 for (; !!record && i < vsi->nb_used_qps; i++)
2033 intr_handle->intr_vec[queue_idx + i] =
2037 /* 1:1 queue/msix_vect mapping */
2038 __vsi_queues_bind_intr(vsi, msix_vect,
2039 vsi->base_queue + i, 1,
2042 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2050 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2052 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2053 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2054 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2055 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2056 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2057 uint16_t msix_intr, i;
2059 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2060 for (i = 0; i < vsi->nb_msix; i++) {
2061 msix_intr = vsi->msix_intr + i;
2062 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2063 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2064 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2065 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2068 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2069 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2070 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2071 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2073 I40E_WRITE_FLUSH(hw);
2077 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2079 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2080 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2081 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2082 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2083 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2084 uint16_t msix_intr, i;
2086 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2087 for (i = 0; i < vsi->nb_msix; i++) {
2088 msix_intr = vsi->msix_intr + i;
2089 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2090 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2093 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2094 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2096 I40E_WRITE_FLUSH(hw);
2099 static inline uint8_t
2100 i40e_parse_link_speeds(uint16_t link_speeds)
2102 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2104 if (link_speeds & ETH_LINK_SPEED_40G)
2105 link_speed |= I40E_LINK_SPEED_40GB;
2106 if (link_speeds & ETH_LINK_SPEED_25G)
2107 link_speed |= I40E_LINK_SPEED_25GB;
2108 if (link_speeds & ETH_LINK_SPEED_20G)
2109 link_speed |= I40E_LINK_SPEED_20GB;
2110 if (link_speeds & ETH_LINK_SPEED_10G)
2111 link_speed |= I40E_LINK_SPEED_10GB;
2112 if (link_speeds & ETH_LINK_SPEED_1G)
2113 link_speed |= I40E_LINK_SPEED_1GB;
2114 if (link_speeds & ETH_LINK_SPEED_100M)
2115 link_speed |= I40E_LINK_SPEED_100MB;
2121 i40e_phy_conf_link(struct i40e_hw *hw,
2123 uint8_t force_speed,
2126 enum i40e_status_code status;
2127 struct i40e_aq_get_phy_abilities_resp phy_ab;
2128 struct i40e_aq_set_phy_config phy_conf;
2129 enum i40e_aq_phy_type cnt;
2130 uint8_t avail_speed;
2131 uint32_t phy_type_mask = 0;
2133 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2134 I40E_AQ_PHY_FLAG_PAUSE_RX |
2135 I40E_AQ_PHY_FLAG_PAUSE_RX |
2136 I40E_AQ_PHY_FLAG_LOW_POWER;
2139 /* To get phy capabilities of available speeds. */
2140 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2143 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2147 avail_speed = phy_ab.link_speed;
2149 /* To get the current phy config. */
2150 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2153 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2158 /* If link needs to go up and it is in autoneg mode the speed is OK,
2159 * no need to set up again.
2161 if (is_up && phy_ab.phy_type != 0 &&
2162 abilities & I40E_AQ_PHY_AN_ENABLED &&
2163 phy_ab.link_speed != 0)
2164 return I40E_SUCCESS;
2166 memset(&phy_conf, 0, sizeof(phy_conf));
2168 /* bits 0-2 use the values from get_phy_abilities_resp */
2170 abilities |= phy_ab.abilities & mask;
2172 phy_conf.abilities = abilities;
2174 /* If link needs to go up, but the force speed is not supported,
2175 * Warn users and config the default available speeds.
2177 if (is_up && !(force_speed & avail_speed)) {
2178 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2179 phy_conf.link_speed = avail_speed;
2181 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2184 /* PHY type mask needs to include each type except PHY type extension */
2185 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2186 phy_type_mask |= 1 << cnt;
2188 /* use get_phy_abilities_resp value for the rest */
2189 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2190 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2191 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2192 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2193 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2194 phy_conf.eee_capability = phy_ab.eee_capability;
2195 phy_conf.eeer = phy_ab.eeer_val;
2196 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2198 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2199 phy_ab.abilities, phy_ab.link_speed);
2200 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2201 phy_conf.abilities, phy_conf.link_speed);
2203 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2207 return I40E_SUCCESS;
2211 i40e_apply_link_speed(struct rte_eth_dev *dev)
2214 uint8_t abilities = 0;
2215 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216 struct rte_eth_conf *conf = &dev->data->dev_conf;
2218 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2219 conf->link_speeds = ETH_LINK_SPEED_40G |
2220 ETH_LINK_SPEED_25G |
2221 ETH_LINK_SPEED_20G |
2222 ETH_LINK_SPEED_10G |
2224 ETH_LINK_SPEED_100M;
2226 speed = i40e_parse_link_speeds(conf->link_speeds);
2227 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2228 I40E_AQ_PHY_AN_ENABLED |
2229 I40E_AQ_PHY_LINK_ENABLED;
2231 return i40e_phy_conf_link(hw, abilities, speed, true);
2235 i40e_dev_start(struct rte_eth_dev *dev)
2237 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2238 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239 struct i40e_vsi *main_vsi = pf->main_vsi;
2241 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2242 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2243 uint32_t intr_vector = 0;
2244 struct i40e_vsi *vsi;
2246 hw->adapter_stopped = 0;
2248 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2250 "Invalid link_speeds for port %u, autonegotiation disabled",
2251 dev->data->port_id);
2255 rte_intr_disable(intr_handle);
2257 if ((rte_intr_cap_multiple(intr_handle) ||
2258 !RTE_ETH_DEV_SRIOV(dev).active) &&
2259 dev->data->dev_conf.intr_conf.rxq != 0) {
2260 intr_vector = dev->data->nb_rx_queues;
2261 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2266 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2267 intr_handle->intr_vec =
2268 rte_zmalloc("intr_vec",
2269 dev->data->nb_rx_queues * sizeof(int),
2271 if (!intr_handle->intr_vec) {
2273 "Failed to allocate %d rx_queues intr_vec",
2274 dev->data->nb_rx_queues);
2279 /* Initialize VSI */
2280 ret = i40e_dev_rxtx_init(pf);
2281 if (ret != I40E_SUCCESS) {
2282 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2286 /* Map queues with MSIX interrupt */
2287 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2288 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2289 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2290 i40e_vsi_enable_queues_intr(main_vsi);
2292 /* Map VMDQ VSI queues with MSIX interrupt */
2293 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2294 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2295 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2296 I40E_ITR_INDEX_DEFAULT);
2297 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2300 /* enable FDIR MSIX interrupt */
2301 if (pf->fdir.fdir_vsi) {
2302 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2303 I40E_ITR_INDEX_NONE);
2304 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2307 /* Enable all queues which have been configured */
2308 ret = i40e_dev_switch_queues(pf, TRUE);
2309 if (ret != I40E_SUCCESS) {
2310 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2314 /* Enable receiving broadcast packets */
2315 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2316 if (ret != I40E_SUCCESS)
2317 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2319 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2320 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2322 if (ret != I40E_SUCCESS)
2323 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2326 /* Enable the VLAN promiscuous mode. */
2328 for (i = 0; i < pf->vf_num; i++) {
2329 vsi = pf->vfs[i].vsi;
2330 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2335 /* Enable mac loopback mode */
2336 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2337 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2338 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2339 if (ret != I40E_SUCCESS) {
2340 PMD_DRV_LOG(ERR, "fail to set loopback link");
2345 /* Apply link configure */
2346 ret = i40e_apply_link_speed(dev);
2347 if (I40E_SUCCESS != ret) {
2348 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2352 if (!rte_intr_allow_others(intr_handle)) {
2353 rte_intr_callback_unregister(intr_handle,
2354 i40e_dev_interrupt_handler,
2356 /* configure and enable device interrupt */
2357 i40e_pf_config_irq0(hw, FALSE);
2358 i40e_pf_enable_irq0(hw);
2360 if (dev->data->dev_conf.intr_conf.lsc != 0)
2362 "lsc won't enable because of no intr multiplex");
2364 ret = i40e_aq_set_phy_int_mask(hw,
2365 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2366 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2367 I40E_AQ_EVENT_MEDIA_NA), NULL);
2368 if (ret != I40E_SUCCESS)
2369 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2371 /* Call get_link_info aq commond to enable/disable LSE */
2372 i40e_dev_link_update(dev, 0);
2375 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2376 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2377 i40e_dev_alarm_handler, dev);
2379 /* enable uio intr after callback register */
2380 rte_intr_enable(intr_handle);
2383 i40e_filter_restore(pf);
2385 if (pf->tm_conf.root && !pf->tm_conf.committed)
2386 PMD_DRV_LOG(WARNING,
2387 "please call hierarchy_commit() "
2388 "before starting the port");
2390 return I40E_SUCCESS;
2393 i40e_dev_switch_queues(pf, FALSE);
2394 i40e_dev_clear_queues(dev);
2400 i40e_dev_stop(struct rte_eth_dev *dev)
2402 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2403 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404 struct i40e_vsi *main_vsi = pf->main_vsi;
2405 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2406 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2409 if (hw->adapter_stopped == 1)
2412 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2413 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2414 rte_intr_enable(intr_handle);
2417 /* Disable all queues */
2418 i40e_dev_switch_queues(pf, FALSE);
2420 /* un-map queues with interrupt registers */
2421 i40e_vsi_disable_queues_intr(main_vsi);
2422 i40e_vsi_queues_unbind_intr(main_vsi);
2424 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2425 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2426 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2429 if (pf->fdir.fdir_vsi) {
2430 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2431 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2433 /* Clear all queues and release memory */
2434 i40e_dev_clear_queues(dev);
2437 i40e_dev_set_link_down(dev);
2439 if (!rte_intr_allow_others(intr_handle))
2440 /* resume to the default handler */
2441 rte_intr_callback_register(intr_handle,
2442 i40e_dev_interrupt_handler,
2445 /* Clean datapath event and queue/vec mapping */
2446 rte_intr_efd_disable(intr_handle);
2447 if (intr_handle->intr_vec) {
2448 rte_free(intr_handle->intr_vec);
2449 intr_handle->intr_vec = NULL;
2452 /* reset hierarchy commit */
2453 pf->tm_conf.committed = false;
2455 hw->adapter_stopped = 1;
2457 pf->adapter->rss_reta_updated = 0;
2461 i40e_dev_close(struct rte_eth_dev *dev)
2463 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2464 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2466 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2467 struct i40e_mirror_rule *p_mirror;
2472 PMD_INIT_FUNC_TRACE();
2476 /* Remove all mirror rules */
2477 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2478 ret = i40e_aq_del_mirror_rule(hw,
2479 pf->main_vsi->veb->seid,
2480 p_mirror->rule_type,
2482 p_mirror->num_entries,
2485 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2486 "status = %d, aq_err = %d.", ret,
2487 hw->aq.asq_last_status);
2489 /* remove mirror software resource anyway */
2490 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2492 pf->nb_mirror_rule--;
2495 i40e_dev_free_queues(dev);
2497 /* Disable interrupt */
2498 i40e_pf_disable_irq0(hw);
2499 rte_intr_disable(intr_handle);
2502 * Only legacy filter API needs the following fdir config. So when the
2503 * legacy filter API is deprecated, the following code should also be
2506 i40e_fdir_teardown(pf);
2508 /* shutdown and destroy the HMC */
2509 i40e_shutdown_lan_hmc(hw);
2511 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2512 i40e_vsi_release(pf->vmdq[i].vsi);
2513 pf->vmdq[i].vsi = NULL;
2518 /* release all the existing VSIs and VEBs */
2519 i40e_vsi_release(pf->main_vsi);
2521 /* shutdown the adminq */
2522 i40e_aq_queue_shutdown(hw, true);
2523 i40e_shutdown_adminq(hw);
2525 i40e_res_pool_destroy(&pf->qp_pool);
2526 i40e_res_pool_destroy(&pf->msix_pool);
2528 /* Disable flexible payload in global configuration */
2529 if (!pf->support_multi_driver)
2530 i40e_flex_payload_reg_set_default(hw);
2532 /* force a PF reset to clean anything leftover */
2533 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2534 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2535 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2536 I40E_WRITE_FLUSH(hw);
2538 hw->adapter_closed = 1;
2542 * Reset PF device only to re-initialize resources in PMD layer
2545 i40e_dev_reset(struct rte_eth_dev *dev)
2549 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2550 * its VF to make them align with it. The detailed notification
2551 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2552 * To avoid unexpected behavior in VF, currently reset of PF with
2553 * SR-IOV activation is not supported. It might be supported later.
2555 if (dev->data->sriov.active)
2558 ret = eth_i40e_dev_uninit(dev);
2562 ret = eth_i40e_dev_init(dev, NULL);
2568 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2570 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2571 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2572 struct i40e_vsi *vsi = pf->main_vsi;
2575 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2577 if (status != I40E_SUCCESS)
2578 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2580 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2582 if (status != I40E_SUCCESS)
2583 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2588 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2590 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2591 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2592 struct i40e_vsi *vsi = pf->main_vsi;
2595 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2597 if (status != I40E_SUCCESS)
2598 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2600 /* must remain in all_multicast mode */
2601 if (dev->data->all_multicast == 1)
2604 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2606 if (status != I40E_SUCCESS)
2607 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2611 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2613 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2614 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615 struct i40e_vsi *vsi = pf->main_vsi;
2618 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2619 if (ret != I40E_SUCCESS)
2620 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2624 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2626 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2627 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2628 struct i40e_vsi *vsi = pf->main_vsi;
2631 if (dev->data->promiscuous == 1)
2632 return; /* must remain in all_multicast mode */
2634 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2635 vsi->seid, FALSE, NULL);
2636 if (ret != I40E_SUCCESS)
2637 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2641 * Set device link up.
2644 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2646 /* re-apply link speed setting */
2647 return i40e_apply_link_speed(dev);
2651 * Set device link down.
2654 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2656 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2657 uint8_t abilities = 0;
2658 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2660 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2661 return i40e_phy_conf_link(hw, abilities, speed, false);
2664 static __rte_always_inline void
2665 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2667 /* Link status registers and values*/
2668 #define I40E_PRTMAC_LINKSTA 0x001E2420
2669 #define I40E_REG_LINK_UP 0x40000080
2670 #define I40E_PRTMAC_MACC 0x001E24E0
2671 #define I40E_REG_MACC_25GB 0x00020000
2672 #define I40E_REG_SPEED_MASK 0x38000000
2673 #define I40E_REG_SPEED_0 0x00000000
2674 #define I40E_REG_SPEED_1 0x08000000
2675 #define I40E_REG_SPEED_2 0x10000000
2676 #define I40E_REG_SPEED_3 0x18000000
2677 #define I40E_REG_SPEED_4 0x20000000
2678 uint32_t link_speed;
2681 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2682 link_speed = reg_val & I40E_REG_SPEED_MASK;
2683 reg_val &= I40E_REG_LINK_UP;
2684 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2686 if (unlikely(link->link_status == 0))
2689 /* Parse the link status */
2690 switch (link_speed) {
2691 case I40E_REG_SPEED_0:
2692 link->link_speed = ETH_SPEED_NUM_100M;
2694 case I40E_REG_SPEED_1:
2695 link->link_speed = ETH_SPEED_NUM_1G;
2697 case I40E_REG_SPEED_2:
2698 if (hw->mac.type == I40E_MAC_X722)
2699 link->link_speed = ETH_SPEED_NUM_2_5G;
2701 link->link_speed = ETH_SPEED_NUM_10G;
2703 case I40E_REG_SPEED_3:
2704 if (hw->mac.type == I40E_MAC_X722) {
2705 link->link_speed = ETH_SPEED_NUM_5G;
2707 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2709 if (reg_val & I40E_REG_MACC_25GB)
2710 link->link_speed = ETH_SPEED_NUM_25G;
2712 link->link_speed = ETH_SPEED_NUM_40G;
2715 case I40E_REG_SPEED_4:
2716 if (hw->mac.type == I40E_MAC_X722)
2717 link->link_speed = ETH_SPEED_NUM_10G;
2719 link->link_speed = ETH_SPEED_NUM_20G;
2722 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2727 static __rte_always_inline void
2728 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2729 bool enable_lse, int wait_to_complete)
2731 #define CHECK_INTERVAL 100 /* 100ms */
2732 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2733 uint32_t rep_cnt = MAX_REPEAT_TIME;
2734 struct i40e_link_status link_status;
2737 memset(&link_status, 0, sizeof(link_status));
2740 memset(&link_status, 0, sizeof(link_status));
2742 /* Get link status information from hardware */
2743 status = i40e_aq_get_link_info(hw, enable_lse,
2744 &link_status, NULL);
2745 if (unlikely(status != I40E_SUCCESS)) {
2746 link->link_speed = ETH_SPEED_NUM_100M;
2747 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2748 PMD_DRV_LOG(ERR, "Failed to get link info");
2752 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2753 if (!wait_to_complete || link->link_status)
2756 rte_delay_ms(CHECK_INTERVAL);
2757 } while (--rep_cnt);
2759 /* Parse the link status */
2760 switch (link_status.link_speed) {
2761 case I40E_LINK_SPEED_100MB:
2762 link->link_speed = ETH_SPEED_NUM_100M;
2764 case I40E_LINK_SPEED_1GB:
2765 link->link_speed = ETH_SPEED_NUM_1G;
2767 case I40E_LINK_SPEED_10GB:
2768 link->link_speed = ETH_SPEED_NUM_10G;
2770 case I40E_LINK_SPEED_20GB:
2771 link->link_speed = ETH_SPEED_NUM_20G;
2773 case I40E_LINK_SPEED_25GB:
2774 link->link_speed = ETH_SPEED_NUM_25G;
2776 case I40E_LINK_SPEED_40GB:
2777 link->link_speed = ETH_SPEED_NUM_40G;
2780 link->link_speed = ETH_SPEED_NUM_100M;
2786 i40e_dev_link_update(struct rte_eth_dev *dev,
2787 int wait_to_complete)
2789 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2790 struct rte_eth_link link;
2791 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2794 memset(&link, 0, sizeof(link));
2796 /* i40e uses full duplex only */
2797 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2798 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2799 ETH_LINK_SPEED_FIXED);
2801 if (!wait_to_complete && !enable_lse)
2802 update_link_reg(hw, &link);
2804 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2806 ret = rte_eth_linkstatus_set(dev, &link);
2807 i40e_notify_all_vfs_link_status(dev);
2812 /* Get all the statistics of a VSI */
2814 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2816 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2817 struct i40e_eth_stats *nes = &vsi->eth_stats;
2818 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2819 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2821 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2822 vsi->offset_loaded, &oes->rx_bytes,
2824 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2825 vsi->offset_loaded, &oes->rx_unicast,
2827 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2828 vsi->offset_loaded, &oes->rx_multicast,
2829 &nes->rx_multicast);
2830 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2831 vsi->offset_loaded, &oes->rx_broadcast,
2832 &nes->rx_broadcast);
2833 /* exclude CRC bytes */
2834 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2835 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2837 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2838 &oes->rx_discards, &nes->rx_discards);
2839 /* GLV_REPC not supported */
2840 /* GLV_RMPC not supported */
2841 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2842 &oes->rx_unknown_protocol,
2843 &nes->rx_unknown_protocol);
2844 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2845 vsi->offset_loaded, &oes->tx_bytes,
2847 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2848 vsi->offset_loaded, &oes->tx_unicast,
2850 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2851 vsi->offset_loaded, &oes->tx_multicast,
2852 &nes->tx_multicast);
2853 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2854 vsi->offset_loaded, &oes->tx_broadcast,
2855 &nes->tx_broadcast);
2856 /* GLV_TDPC not supported */
2857 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2858 &oes->tx_errors, &nes->tx_errors);
2859 vsi->offset_loaded = true;
2861 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2863 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2864 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2865 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2866 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2867 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2868 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2869 nes->rx_unknown_protocol);
2870 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2871 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2872 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2873 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2874 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2875 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2876 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2881 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2884 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2885 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2887 /* Get rx/tx bytes of internal transfer packets */
2888 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2889 I40E_GLV_GORCL(hw->port),
2891 &pf->internal_stats_offset.rx_bytes,
2892 &pf->internal_stats.rx_bytes);
2894 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2895 I40E_GLV_GOTCL(hw->port),
2897 &pf->internal_stats_offset.tx_bytes,
2898 &pf->internal_stats.tx_bytes);
2899 /* Get total internal rx packet count */
2900 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2901 I40E_GLV_UPRCL(hw->port),
2903 &pf->internal_stats_offset.rx_unicast,
2904 &pf->internal_stats.rx_unicast);
2905 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2906 I40E_GLV_MPRCL(hw->port),
2908 &pf->internal_stats_offset.rx_multicast,
2909 &pf->internal_stats.rx_multicast);
2910 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2911 I40E_GLV_BPRCL(hw->port),
2913 &pf->internal_stats_offset.rx_broadcast,
2914 &pf->internal_stats.rx_broadcast);
2915 /* Get total internal tx packet count */
2916 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2917 I40E_GLV_UPTCL(hw->port),
2919 &pf->internal_stats_offset.tx_unicast,
2920 &pf->internal_stats.tx_unicast);
2921 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2922 I40E_GLV_MPTCL(hw->port),
2924 &pf->internal_stats_offset.tx_multicast,
2925 &pf->internal_stats.tx_multicast);
2926 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2927 I40E_GLV_BPTCL(hw->port),
2929 &pf->internal_stats_offset.tx_broadcast,
2930 &pf->internal_stats.tx_broadcast);
2932 /* exclude CRC size */
2933 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2934 pf->internal_stats.rx_multicast +
2935 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
2937 /* Get statistics of struct i40e_eth_stats */
2938 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2939 I40E_GLPRT_GORCL(hw->port),
2940 pf->offset_loaded, &os->eth.rx_bytes,
2942 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2943 I40E_GLPRT_UPRCL(hw->port),
2944 pf->offset_loaded, &os->eth.rx_unicast,
2945 &ns->eth.rx_unicast);
2946 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2947 I40E_GLPRT_MPRCL(hw->port),
2948 pf->offset_loaded, &os->eth.rx_multicast,
2949 &ns->eth.rx_multicast);
2950 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2951 I40E_GLPRT_BPRCL(hw->port),
2952 pf->offset_loaded, &os->eth.rx_broadcast,
2953 &ns->eth.rx_broadcast);
2954 /* Workaround: CRC size should not be included in byte statistics,
2955 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
2958 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2959 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
2961 /* exclude internal rx bytes
2962 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2963 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2965 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2967 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2968 ns->eth.rx_bytes = 0;
2970 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2972 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2973 ns->eth.rx_unicast = 0;
2975 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2977 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2978 ns->eth.rx_multicast = 0;
2980 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2982 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2983 ns->eth.rx_broadcast = 0;
2985 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2987 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2988 pf->offset_loaded, &os->eth.rx_discards,
2989 &ns->eth.rx_discards);
2990 /* GLPRT_REPC not supported */
2991 /* GLPRT_RMPC not supported */
2992 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2994 &os->eth.rx_unknown_protocol,
2995 &ns->eth.rx_unknown_protocol);
2996 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2997 I40E_GLPRT_GOTCL(hw->port),
2998 pf->offset_loaded, &os->eth.tx_bytes,
3000 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3001 I40E_GLPRT_UPTCL(hw->port),
3002 pf->offset_loaded, &os->eth.tx_unicast,
3003 &ns->eth.tx_unicast);
3004 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3005 I40E_GLPRT_MPTCL(hw->port),
3006 pf->offset_loaded, &os->eth.tx_multicast,
3007 &ns->eth.tx_multicast);
3008 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3009 I40E_GLPRT_BPTCL(hw->port),
3010 pf->offset_loaded, &os->eth.tx_broadcast,
3011 &ns->eth.tx_broadcast);
3012 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3013 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3015 /* exclude internal tx bytes
3016 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3017 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3019 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3021 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3022 ns->eth.tx_bytes = 0;
3024 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3026 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3027 ns->eth.tx_unicast = 0;
3029 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3031 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3032 ns->eth.tx_multicast = 0;
3034 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3036 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3037 ns->eth.tx_broadcast = 0;
3039 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3041 /* GLPRT_TEPC not supported */
3043 /* additional port specific stats */
3044 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3045 pf->offset_loaded, &os->tx_dropped_link_down,
3046 &ns->tx_dropped_link_down);
3047 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3048 pf->offset_loaded, &os->crc_errors,
3050 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3051 pf->offset_loaded, &os->illegal_bytes,
3052 &ns->illegal_bytes);
3053 /* GLPRT_ERRBC not supported */
3054 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3055 pf->offset_loaded, &os->mac_local_faults,
3056 &ns->mac_local_faults);
3057 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3058 pf->offset_loaded, &os->mac_remote_faults,
3059 &ns->mac_remote_faults);
3060 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3061 pf->offset_loaded, &os->rx_length_errors,
3062 &ns->rx_length_errors);
3063 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3064 pf->offset_loaded, &os->link_xon_rx,
3066 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3067 pf->offset_loaded, &os->link_xoff_rx,
3069 for (i = 0; i < 8; i++) {
3070 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3072 &os->priority_xon_rx[i],
3073 &ns->priority_xon_rx[i]);
3074 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3076 &os->priority_xoff_rx[i],
3077 &ns->priority_xoff_rx[i]);
3079 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3080 pf->offset_loaded, &os->link_xon_tx,
3082 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3083 pf->offset_loaded, &os->link_xoff_tx,
3085 for (i = 0; i < 8; i++) {
3086 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3088 &os->priority_xon_tx[i],
3089 &ns->priority_xon_tx[i]);
3090 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3092 &os->priority_xoff_tx[i],
3093 &ns->priority_xoff_tx[i]);
3094 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3096 &os->priority_xon_2_xoff[i],
3097 &ns->priority_xon_2_xoff[i]);
3099 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3100 I40E_GLPRT_PRC64L(hw->port),
3101 pf->offset_loaded, &os->rx_size_64,
3103 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3104 I40E_GLPRT_PRC127L(hw->port),
3105 pf->offset_loaded, &os->rx_size_127,
3107 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3108 I40E_GLPRT_PRC255L(hw->port),
3109 pf->offset_loaded, &os->rx_size_255,
3111 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3112 I40E_GLPRT_PRC511L(hw->port),
3113 pf->offset_loaded, &os->rx_size_511,
3115 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3116 I40E_GLPRT_PRC1023L(hw->port),
3117 pf->offset_loaded, &os->rx_size_1023,
3119 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3120 I40E_GLPRT_PRC1522L(hw->port),
3121 pf->offset_loaded, &os->rx_size_1522,
3123 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3124 I40E_GLPRT_PRC9522L(hw->port),
3125 pf->offset_loaded, &os->rx_size_big,
3127 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3128 pf->offset_loaded, &os->rx_undersize,
3130 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3131 pf->offset_loaded, &os->rx_fragments,
3133 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3134 pf->offset_loaded, &os->rx_oversize,
3136 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3137 pf->offset_loaded, &os->rx_jabber,
3139 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3140 I40E_GLPRT_PTC64L(hw->port),
3141 pf->offset_loaded, &os->tx_size_64,
3143 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3144 I40E_GLPRT_PTC127L(hw->port),
3145 pf->offset_loaded, &os->tx_size_127,
3147 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3148 I40E_GLPRT_PTC255L(hw->port),
3149 pf->offset_loaded, &os->tx_size_255,
3151 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3152 I40E_GLPRT_PTC511L(hw->port),
3153 pf->offset_loaded, &os->tx_size_511,
3155 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3156 I40E_GLPRT_PTC1023L(hw->port),
3157 pf->offset_loaded, &os->tx_size_1023,
3159 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3160 I40E_GLPRT_PTC1522L(hw->port),
3161 pf->offset_loaded, &os->tx_size_1522,
3163 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3164 I40E_GLPRT_PTC9522L(hw->port),
3165 pf->offset_loaded, &os->tx_size_big,
3167 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3169 &os->fd_sb_match, &ns->fd_sb_match);
3170 /* GLPRT_MSPDC not supported */
3171 /* GLPRT_XEC not supported */
3173 pf->offset_loaded = true;
3176 i40e_update_vsi_stats(pf->main_vsi);
3179 /* Get all statistics of a port */
3181 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3183 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3184 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3185 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3186 struct i40e_vsi *vsi;
3189 /* call read registers - updates values, now write them to struct */
3190 i40e_read_stats_registers(pf, hw);
3192 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3193 pf->main_vsi->eth_stats.rx_multicast +
3194 pf->main_vsi->eth_stats.rx_broadcast -
3195 pf->main_vsi->eth_stats.rx_discards;
3196 stats->opackets = ns->eth.tx_unicast +
3197 ns->eth.tx_multicast +
3198 ns->eth.tx_broadcast;
3199 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3200 stats->obytes = ns->eth.tx_bytes;
3201 stats->oerrors = ns->eth.tx_errors +
3202 pf->main_vsi->eth_stats.tx_errors;
3205 stats->imissed = ns->eth.rx_discards +
3206 pf->main_vsi->eth_stats.rx_discards;
3207 stats->ierrors = ns->crc_errors +
3208 ns->rx_length_errors + ns->rx_undersize +
3209 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3212 for (i = 0; i < pf->vf_num; i++) {
3213 vsi = pf->vfs[i].vsi;
3214 i40e_update_vsi_stats(vsi);
3216 stats->ipackets += (vsi->eth_stats.rx_unicast +
3217 vsi->eth_stats.rx_multicast +
3218 vsi->eth_stats.rx_broadcast -
3219 vsi->eth_stats.rx_discards);
3220 stats->ibytes += vsi->eth_stats.rx_bytes;
3221 stats->oerrors += vsi->eth_stats.tx_errors;
3222 stats->imissed += vsi->eth_stats.rx_discards;
3226 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3227 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3228 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3229 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3230 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3231 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3232 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3233 ns->eth.rx_unknown_protocol);
3234 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3235 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3236 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3237 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3238 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3239 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3241 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3242 ns->tx_dropped_link_down);
3243 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3244 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3246 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3247 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3248 ns->mac_local_faults);
3249 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3250 ns->mac_remote_faults);
3251 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3252 ns->rx_length_errors);
3253 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3254 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3255 for (i = 0; i < 8; i++) {
3256 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3257 i, ns->priority_xon_rx[i]);
3258 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3259 i, ns->priority_xoff_rx[i]);
3261 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3262 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3263 for (i = 0; i < 8; i++) {
3264 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3265 i, ns->priority_xon_tx[i]);
3266 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3267 i, ns->priority_xoff_tx[i]);
3268 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3269 i, ns->priority_xon_2_xoff[i]);
3271 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3272 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3273 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3274 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3275 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3276 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3277 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3278 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3279 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3280 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3281 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3282 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3283 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3284 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3285 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3286 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3287 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3288 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3289 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3290 ns->mac_short_packet_dropped);
3291 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3292 ns->checksum_error);
3293 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3294 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3298 /* Reset the statistics */
3300 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3302 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3303 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3305 /* Mark PF and VSI stats to update the offset, aka "reset" */
3306 pf->offset_loaded = false;
3308 pf->main_vsi->offset_loaded = false;
3310 /* read the stats, reading current register values into offset */
3311 i40e_read_stats_registers(pf, hw);
3315 i40e_xstats_calc_num(void)
3317 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3318 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3319 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3322 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3323 struct rte_eth_xstat_name *xstats_names,
3324 __rte_unused unsigned limit)
3329 if (xstats_names == NULL)
3330 return i40e_xstats_calc_num();
3332 /* Note: limit checked in rte_eth_xstats_names() */
3334 /* Get stats from i40e_eth_stats struct */
3335 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3336 strlcpy(xstats_names[count].name,
3337 rte_i40e_stats_strings[i].name,
3338 sizeof(xstats_names[count].name));
3342 /* Get individiual stats from i40e_hw_port struct */
3343 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3344 strlcpy(xstats_names[count].name,
3345 rte_i40e_hw_port_strings[i].name,
3346 sizeof(xstats_names[count].name));
3350 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3351 for (prio = 0; prio < 8; prio++) {
3352 snprintf(xstats_names[count].name,
3353 sizeof(xstats_names[count].name),
3354 "rx_priority%u_%s", prio,
3355 rte_i40e_rxq_prio_strings[i].name);
3360 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3361 for (prio = 0; prio < 8; prio++) {
3362 snprintf(xstats_names[count].name,
3363 sizeof(xstats_names[count].name),
3364 "tx_priority%u_%s", prio,
3365 rte_i40e_txq_prio_strings[i].name);
3373 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3376 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3377 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378 unsigned i, count, prio;
3379 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3381 count = i40e_xstats_calc_num();
3385 i40e_read_stats_registers(pf, hw);
3392 /* Get stats from i40e_eth_stats struct */
3393 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3394 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3395 rte_i40e_stats_strings[i].offset);
3396 xstats[count].id = count;
3400 /* Get individiual stats from i40e_hw_port struct */
3401 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3402 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3403 rte_i40e_hw_port_strings[i].offset);
3404 xstats[count].id = count;
3408 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3409 for (prio = 0; prio < 8; prio++) {
3410 xstats[count].value =
3411 *(uint64_t *)(((char *)hw_stats) +
3412 rte_i40e_rxq_prio_strings[i].offset +
3413 (sizeof(uint64_t) * prio));
3414 xstats[count].id = count;
3419 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3420 for (prio = 0; prio < 8; prio++) {
3421 xstats[count].value =
3422 *(uint64_t *)(((char *)hw_stats) +
3423 rte_i40e_txq_prio_strings[i].offset +
3424 (sizeof(uint64_t) * prio));
3425 xstats[count].id = count;
3434 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3436 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442 full_ver = hw->nvm.oem_ver;
3443 ver = (u8)(full_ver >> 24);
3444 build = (u16)((full_ver >> 8) & 0xffff);
3445 patch = (u8)(full_ver & 0xff);
3447 ret = snprintf(fw_version, fw_size,
3448 "%d.%d%d 0x%08x %d.%d.%d",
3449 ((hw->nvm.version >> 12) & 0xf),
3450 ((hw->nvm.version >> 4) & 0xff),
3451 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3454 ret += 1; /* add the size of '\0' */
3455 if (fw_size < (u32)ret)
3462 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3463 * the Rx data path does not hang if the FW LLDP is stopped.
3464 * return true if lldp need to stop
3465 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3468 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3471 char ver_str[64] = {0};
3472 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3474 i40e_fw_version_get(dev, ver_str, 64);
3475 nvm_ver = atof(ver_str);
3476 if ((hw->mac.type == I40E_MAC_X722 ||
3477 hw->mac.type == I40E_MAC_X722_VF) &&
3478 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3480 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3487 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3489 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3490 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3491 struct i40e_vsi *vsi = pf->main_vsi;
3492 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3494 dev_info->max_rx_queues = vsi->nb_qps;
3495 dev_info->max_tx_queues = vsi->nb_qps;
3496 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3497 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3498 dev_info->max_mac_addrs = vsi->max_macaddrs;
3499 dev_info->max_vfs = pci_dev->max_vfs;
3500 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3501 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3502 dev_info->rx_queue_offload_capa = 0;
3503 dev_info->rx_offload_capa =
3504 DEV_RX_OFFLOAD_VLAN_STRIP |
3505 DEV_RX_OFFLOAD_QINQ_STRIP |
3506 DEV_RX_OFFLOAD_IPV4_CKSUM |
3507 DEV_RX_OFFLOAD_UDP_CKSUM |
3508 DEV_RX_OFFLOAD_TCP_CKSUM |
3509 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3510 DEV_RX_OFFLOAD_KEEP_CRC |
3511 DEV_RX_OFFLOAD_SCATTER |
3512 DEV_RX_OFFLOAD_VLAN_EXTEND |
3513 DEV_RX_OFFLOAD_VLAN_FILTER |
3514 DEV_RX_OFFLOAD_JUMBO_FRAME;
3516 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3517 dev_info->tx_offload_capa =
3518 DEV_TX_OFFLOAD_VLAN_INSERT |
3519 DEV_TX_OFFLOAD_QINQ_INSERT |
3520 DEV_TX_OFFLOAD_IPV4_CKSUM |
3521 DEV_TX_OFFLOAD_UDP_CKSUM |
3522 DEV_TX_OFFLOAD_TCP_CKSUM |
3523 DEV_TX_OFFLOAD_SCTP_CKSUM |
3524 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3525 DEV_TX_OFFLOAD_TCP_TSO |
3526 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3527 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3528 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3529 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3530 DEV_TX_OFFLOAD_MULTI_SEGS |
3531 dev_info->tx_queue_offload_capa;
3532 dev_info->dev_capa =
3533 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3534 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3536 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3538 dev_info->reta_size = pf->hash_lut_size;
3539 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3541 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3543 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3544 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3545 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3547 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3552 dev_info->default_txconf = (struct rte_eth_txconf) {
3554 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3555 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3556 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3558 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3559 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3563 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3564 .nb_max = I40E_MAX_RING_DESC,
3565 .nb_min = I40E_MIN_RING_DESC,
3566 .nb_align = I40E_ALIGN_RING_DESC,
3569 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3570 .nb_max = I40E_MAX_RING_DESC,
3571 .nb_min = I40E_MIN_RING_DESC,
3572 .nb_align = I40E_ALIGN_RING_DESC,
3573 .nb_seg_max = I40E_TX_MAX_SEG,
3574 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3577 if (pf->flags & I40E_FLAG_VMDQ) {
3578 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3579 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3580 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3581 pf->max_nb_vmdq_vsi;
3582 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3583 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3584 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3587 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3589 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3590 dev_info->default_rxportconf.nb_queues = 2;
3591 dev_info->default_txportconf.nb_queues = 2;
3592 if (dev->data->nb_rx_queues == 1)
3593 dev_info->default_rxportconf.ring_size = 2048;
3595 dev_info->default_rxportconf.ring_size = 1024;
3596 if (dev->data->nb_tx_queues == 1)
3597 dev_info->default_txportconf.ring_size = 1024;
3599 dev_info->default_txportconf.ring_size = 512;
3601 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3603 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3604 dev_info->default_rxportconf.nb_queues = 1;
3605 dev_info->default_txportconf.nb_queues = 1;
3606 dev_info->default_rxportconf.ring_size = 256;
3607 dev_info->default_txportconf.ring_size = 256;
3610 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3611 dev_info->default_rxportconf.nb_queues = 1;
3612 dev_info->default_txportconf.nb_queues = 1;
3613 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3614 dev_info->default_rxportconf.ring_size = 512;
3615 dev_info->default_txportconf.ring_size = 256;
3617 dev_info->default_rxportconf.ring_size = 256;
3618 dev_info->default_txportconf.ring_size = 256;
3621 dev_info->default_rxportconf.burst_size = 32;
3622 dev_info->default_txportconf.burst_size = 32;
3628 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3630 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3631 struct i40e_vsi *vsi = pf->main_vsi;
3632 PMD_INIT_FUNC_TRACE();
3635 return i40e_vsi_add_vlan(vsi, vlan_id);
3637 return i40e_vsi_delete_vlan(vsi, vlan_id);
3641 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3642 enum rte_vlan_type vlan_type,
3643 uint16_t tpid, int qinq)
3645 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3648 uint16_t reg_id = 3;
3652 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3656 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3658 if (ret != I40E_SUCCESS) {
3660 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3665 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3668 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3669 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3670 if (reg_r == reg_w) {
3671 PMD_DRV_LOG(DEBUG, "No need to write");
3675 ret = i40e_aq_debug_write_global_register(hw,
3676 I40E_GL_SWT_L2TAGCTRL(reg_id),
3678 if (ret != I40E_SUCCESS) {
3680 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3685 "Global register 0x%08x is changed with value 0x%08x",
3686 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3692 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3693 enum rte_vlan_type vlan_type,
3696 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3697 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3698 int qinq = dev->data->dev_conf.rxmode.offloads &
3699 DEV_RX_OFFLOAD_VLAN_EXTEND;
3702 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3703 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3704 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3706 "Unsupported vlan type.");
3710 if (pf->support_multi_driver) {
3711 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3715 /* 802.1ad frames ability is added in NVM API 1.7*/
3716 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3718 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3719 hw->first_tag = rte_cpu_to_le_16(tpid);
3720 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3721 hw->second_tag = rte_cpu_to_le_16(tpid);
3723 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3724 hw->second_tag = rte_cpu_to_le_16(tpid);
3726 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3727 if (ret != I40E_SUCCESS) {
3729 "Set switch config failed aq_err: %d",
3730 hw->aq.asq_last_status);
3734 /* If NVM API < 1.7, keep the register setting */
3735 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3742 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3744 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3745 struct i40e_vsi *vsi = pf->main_vsi;
3746 struct rte_eth_rxmode *rxmode;
3748 rxmode = &dev->data->dev_conf.rxmode;
3749 if (mask & ETH_VLAN_FILTER_MASK) {
3750 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3751 i40e_vsi_config_vlan_filter(vsi, TRUE);
3753 i40e_vsi_config_vlan_filter(vsi, FALSE);
3756 if (mask & ETH_VLAN_STRIP_MASK) {
3757 /* Enable or disable VLAN stripping */
3758 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3759 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3761 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3764 if (mask & ETH_VLAN_EXTEND_MASK) {
3765 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3766 i40e_vsi_config_double_vlan(vsi, TRUE);
3767 /* Set global registers with default ethertype. */
3768 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3769 RTE_ETHER_TYPE_VLAN);
3770 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3771 RTE_ETHER_TYPE_VLAN);
3774 i40e_vsi_config_double_vlan(vsi, FALSE);
3781 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3782 __rte_unused uint16_t queue,
3783 __rte_unused int on)
3785 PMD_INIT_FUNC_TRACE();
3789 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3791 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3792 struct i40e_vsi *vsi = pf->main_vsi;
3793 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3794 struct i40e_vsi_vlan_pvid_info info;
3796 memset(&info, 0, sizeof(info));
3799 info.config.pvid = pvid;
3801 info.config.reject.tagged =
3802 data->dev_conf.txmode.hw_vlan_reject_tagged;
3803 info.config.reject.untagged =
3804 data->dev_conf.txmode.hw_vlan_reject_untagged;
3807 return i40e_vsi_vlan_pvid_set(vsi, &info);
3811 i40e_dev_led_on(struct rte_eth_dev *dev)
3813 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3814 uint32_t mode = i40e_led_get(hw);
3817 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3823 i40e_dev_led_off(struct rte_eth_dev *dev)
3825 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3826 uint32_t mode = i40e_led_get(hw);
3829 i40e_led_set(hw, 0, false);
3835 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3837 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3838 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3840 fc_conf->pause_time = pf->fc_conf.pause_time;
3842 /* read out from register, in case they are modified by other port */
3843 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3844 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3845 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3846 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3848 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3849 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3851 /* Return current mode according to actual setting*/
3852 switch (hw->fc.current_mode) {
3854 fc_conf->mode = RTE_FC_FULL;
3856 case I40E_FC_TX_PAUSE:
3857 fc_conf->mode = RTE_FC_TX_PAUSE;
3859 case I40E_FC_RX_PAUSE:
3860 fc_conf->mode = RTE_FC_RX_PAUSE;
3864 fc_conf->mode = RTE_FC_NONE;
3871 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3873 uint32_t mflcn_reg, fctrl_reg, reg;
3874 uint32_t max_high_water;
3875 uint8_t i, aq_failure;
3879 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3880 [RTE_FC_NONE] = I40E_FC_NONE,
3881 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3882 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3883 [RTE_FC_FULL] = I40E_FC_FULL
3886 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3888 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3889 if ((fc_conf->high_water > max_high_water) ||
3890 (fc_conf->high_water < fc_conf->low_water)) {
3892 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3897 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3898 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3899 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3901 pf->fc_conf.pause_time = fc_conf->pause_time;
3902 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3903 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3905 PMD_INIT_FUNC_TRACE();
3907 /* All the link flow control related enable/disable register
3908 * configuration is handle by the F/W
3910 err = i40e_set_fc(hw, &aq_failure, true);
3914 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3915 /* Configure flow control refresh threshold,
3916 * the value for stat_tx_pause_refresh_timer[8]
3917 * is used for global pause operation.
3921 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3922 pf->fc_conf.pause_time);
3924 /* configure the timer value included in transmitted pause
3926 * the value for stat_tx_pause_quanta[8] is used for global
3929 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3930 pf->fc_conf.pause_time);
3932 fctrl_reg = I40E_READ_REG(hw,
3933 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3935 if (fc_conf->mac_ctrl_frame_fwd != 0)
3936 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3938 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3940 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3943 /* Configure pause time (2 TCs per register) */
3944 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3945 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3946 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3948 /* Configure flow control refresh threshold value */
3949 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3950 pf->fc_conf.pause_time / 2);
3952 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3954 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3955 *depending on configuration
3957 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3958 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3959 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3961 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3962 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3965 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3968 if (!pf->support_multi_driver) {
3969 /* config water marker both based on the packets and bytes */
3970 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3971 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3972 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3973 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3974 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3975 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3976 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3977 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3979 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3980 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3984 "Water marker configuration is not supported.");
3987 I40E_WRITE_FLUSH(hw);
3993 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3994 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3996 PMD_INIT_FUNC_TRACE();
4001 /* Add a MAC address, and update filters */
4003 i40e_macaddr_add(struct rte_eth_dev *dev,
4004 struct rte_ether_addr *mac_addr,
4005 __rte_unused uint32_t index,
4008 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4009 struct i40e_mac_filter_info mac_filter;
4010 struct i40e_vsi *vsi;
4011 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4014 /* If VMDQ not enabled or configured, return */
4015 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4016 !pf->nb_cfg_vmdq_vsi)) {
4017 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4018 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4023 if (pool > pf->nb_cfg_vmdq_vsi) {
4024 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4025 pool, pf->nb_cfg_vmdq_vsi);
4029 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4030 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4031 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4033 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4038 vsi = pf->vmdq[pool - 1].vsi;
4040 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4041 if (ret != I40E_SUCCESS) {
4042 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4048 /* Remove a MAC address, and update filters */
4050 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4052 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4053 struct i40e_vsi *vsi;
4054 struct rte_eth_dev_data *data = dev->data;
4055 struct rte_ether_addr *macaddr;
4060 macaddr = &(data->mac_addrs[index]);
4062 pool_sel = dev->data->mac_pool_sel[index];
4064 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4065 if (pool_sel & (1ULL << i)) {
4069 /* No VMDQ pool enabled or configured */
4070 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4071 (i > pf->nb_cfg_vmdq_vsi)) {
4073 "No VMDQ pool enabled/configured");
4076 vsi = pf->vmdq[i - 1].vsi;
4078 ret = i40e_vsi_delete_mac(vsi, macaddr);
4081 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4088 /* Set perfect match or hash match of MAC and VLAN for a VF */
4090 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4091 struct rte_eth_mac_filter *filter,
4095 struct i40e_mac_filter_info mac_filter;
4096 struct rte_ether_addr old_mac;
4097 struct rte_ether_addr *new_mac;
4098 struct i40e_pf_vf *vf = NULL;
4103 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4106 hw = I40E_PF_TO_HW(pf);
4108 if (filter == NULL) {
4109 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4113 new_mac = &filter->mac_addr;
4115 if (rte_is_zero_ether_addr(new_mac)) {
4116 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4120 vf_id = filter->dst_id;
4122 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4123 PMD_DRV_LOG(ERR, "Invalid argument.");
4126 vf = &pf->vfs[vf_id];
4128 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4129 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4134 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4135 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4136 RTE_ETHER_ADDR_LEN);
4137 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4138 RTE_ETHER_ADDR_LEN);
4140 mac_filter.filter_type = filter->filter_type;
4141 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4142 if (ret != I40E_SUCCESS) {
4143 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4146 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4148 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4149 RTE_ETHER_ADDR_LEN);
4150 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4151 if (ret != I40E_SUCCESS) {
4152 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4156 /* Clear device address as it has been removed */
4157 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4158 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4164 /* MAC filter handle */
4166 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4169 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4170 struct rte_eth_mac_filter *filter;
4171 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4172 int ret = I40E_NOT_SUPPORTED;
4174 filter = (struct rte_eth_mac_filter *)(arg);
4176 switch (filter_op) {
4177 case RTE_ETH_FILTER_NOP:
4180 case RTE_ETH_FILTER_ADD:
4181 i40e_pf_disable_irq0(hw);
4183 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4184 i40e_pf_enable_irq0(hw);
4186 case RTE_ETH_FILTER_DELETE:
4187 i40e_pf_disable_irq0(hw);
4189 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4190 i40e_pf_enable_irq0(hw);
4193 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4194 ret = I40E_ERR_PARAM;
4202 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4204 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4205 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4212 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4213 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4214 vsi->type != I40E_VSI_SRIOV,
4217 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4221 uint32_t *lut_dw = (uint32_t *)lut;
4222 uint16_t i, lut_size_dw = lut_size / 4;
4224 if (vsi->type == I40E_VSI_SRIOV) {
4225 for (i = 0; i <= lut_size_dw; i++) {
4226 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4227 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4230 for (i = 0; i < lut_size_dw; i++)
4231 lut_dw[i] = I40E_READ_REG(hw,
4240 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4249 pf = I40E_VSI_TO_PF(vsi);
4250 hw = I40E_VSI_TO_HW(vsi);
4252 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4253 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4254 vsi->type != I40E_VSI_SRIOV,
4257 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4261 uint32_t *lut_dw = (uint32_t *)lut;
4262 uint16_t i, lut_size_dw = lut_size / 4;
4264 if (vsi->type == I40E_VSI_SRIOV) {
4265 for (i = 0; i < lut_size_dw; i++)
4268 I40E_VFQF_HLUT1(i, vsi->user_param),
4271 for (i = 0; i < lut_size_dw; i++)
4272 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4275 I40E_WRITE_FLUSH(hw);
4282 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4283 struct rte_eth_rss_reta_entry64 *reta_conf,
4286 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4287 uint16_t i, lut_size = pf->hash_lut_size;
4288 uint16_t idx, shift;
4292 if (reta_size != lut_size ||
4293 reta_size > ETH_RSS_RETA_SIZE_512) {
4295 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4296 reta_size, lut_size);
4300 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4302 PMD_DRV_LOG(ERR, "No memory can be allocated");
4305 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4308 for (i = 0; i < reta_size; i++) {
4309 idx = i / RTE_RETA_GROUP_SIZE;
4310 shift = i % RTE_RETA_GROUP_SIZE;
4311 if (reta_conf[idx].mask & (1ULL << shift))
4312 lut[i] = reta_conf[idx].reta[shift];
4314 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4316 pf->adapter->rss_reta_updated = 1;
4325 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4326 struct rte_eth_rss_reta_entry64 *reta_conf,
4329 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4330 uint16_t i, lut_size = pf->hash_lut_size;
4331 uint16_t idx, shift;
4335 if (reta_size != lut_size ||
4336 reta_size > ETH_RSS_RETA_SIZE_512) {
4338 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4339 reta_size, lut_size);
4343 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4345 PMD_DRV_LOG(ERR, "No memory can be allocated");
4349 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4352 for (i = 0; i < reta_size; i++) {
4353 idx = i / RTE_RETA_GROUP_SIZE;
4354 shift = i % RTE_RETA_GROUP_SIZE;
4355 if (reta_conf[idx].mask & (1ULL << shift))
4356 reta_conf[idx].reta[shift] = lut[i];
4366 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4367 * @hw: pointer to the HW structure
4368 * @mem: pointer to mem struct to fill out
4369 * @size: size of memory requested
4370 * @alignment: what to align the allocation to
4372 enum i40e_status_code
4373 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4374 struct i40e_dma_mem *mem,
4378 const struct rte_memzone *mz = NULL;
4379 char z_name[RTE_MEMZONE_NAMESIZE];
4382 return I40E_ERR_PARAM;
4384 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4385 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4386 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4388 return I40E_ERR_NO_MEMORY;
4393 mem->zone = (const void *)mz;
4395 "memzone %s allocated with physical address: %"PRIu64,
4398 return I40E_SUCCESS;
4402 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4403 * @hw: pointer to the HW structure
4404 * @mem: ptr to mem struct to free
4406 enum i40e_status_code
4407 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4408 struct i40e_dma_mem *mem)
4411 return I40E_ERR_PARAM;
4414 "memzone %s to be freed with physical address: %"PRIu64,
4415 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4416 rte_memzone_free((const struct rte_memzone *)mem->zone);
4421 return I40E_SUCCESS;
4425 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4426 * @hw: pointer to the HW structure
4427 * @mem: pointer to mem struct to fill out
4428 * @size: size of memory requested
4430 enum i40e_status_code
4431 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4432 struct i40e_virt_mem *mem,
4436 return I40E_ERR_PARAM;
4439 mem->va = rte_zmalloc("i40e", size, 0);
4442 return I40E_SUCCESS;
4444 return I40E_ERR_NO_MEMORY;
4448 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4449 * @hw: pointer to the HW structure
4450 * @mem: pointer to mem struct to free
4452 enum i40e_status_code
4453 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4454 struct i40e_virt_mem *mem)
4457 return I40E_ERR_PARAM;
4462 return I40E_SUCCESS;
4466 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4468 rte_spinlock_init(&sp->spinlock);
4472 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4474 rte_spinlock_lock(&sp->spinlock);
4478 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4480 rte_spinlock_unlock(&sp->spinlock);
4484 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4490 * Get the hardware capabilities, which will be parsed
4491 * and saved into struct i40e_hw.
4494 i40e_get_cap(struct i40e_hw *hw)
4496 struct i40e_aqc_list_capabilities_element_resp *buf;
4497 uint16_t len, size = 0;
4500 /* Calculate a huge enough buff for saving response data temporarily */
4501 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4502 I40E_MAX_CAP_ELE_NUM;
4503 buf = rte_zmalloc("i40e", len, 0);
4505 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4506 return I40E_ERR_NO_MEMORY;
4509 /* Get, parse the capabilities and save it to hw */
4510 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4511 i40e_aqc_opc_list_func_capabilities, NULL);
4512 if (ret != I40E_SUCCESS)
4513 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4515 /* Free the temporary buffer after being used */
4521 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4523 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4531 pf = (struct i40e_pf *)opaque;
4535 num = strtoul(value, &end, 0);
4536 if (errno != 0 || end == value || *end != 0) {
4537 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4538 "kept the value = %hu", value, pf->vf_nb_qp_max);
4542 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4543 pf->vf_nb_qp_max = (uint16_t)num;
4545 /* here return 0 to make next valid same argument work */
4546 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4547 "power of 2 and equal or less than 16 !, Now it is "
4548 "kept the value = %hu", num, pf->vf_nb_qp_max);
4553 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4555 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4556 struct rte_kvargs *kvlist;
4559 /* set default queue number per VF as 4 */
4560 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4562 if (dev->device->devargs == NULL)
4565 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4569 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4570 if (!kvargs_count) {
4571 rte_kvargs_free(kvlist);
4575 if (kvargs_count > 1)
4576 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4577 "the first invalid or last valid one is used !",
4578 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4580 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4581 i40e_pf_parse_vf_queue_number_handler, pf);
4583 rte_kvargs_free(kvlist);
4589 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4591 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4592 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4593 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4594 uint16_t qp_count = 0, vsi_count = 0;
4596 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4597 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4601 i40e_pf_config_vf_rxq_number(dev);
4603 /* Add the parameter init for LFC */
4604 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4605 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4606 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4608 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4609 pf->max_num_vsi = hw->func_caps.num_vsis;
4610 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4611 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4613 /* FDir queue/VSI allocation */
4614 pf->fdir_qp_offset = 0;
4615 if (hw->func_caps.fd) {
4616 pf->flags |= I40E_FLAG_FDIR;
4617 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4619 pf->fdir_nb_qps = 0;
4621 qp_count += pf->fdir_nb_qps;
4624 /* LAN queue/VSI allocation */
4625 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4626 if (!hw->func_caps.rss) {
4629 pf->flags |= I40E_FLAG_RSS;
4630 if (hw->mac.type == I40E_MAC_X722)
4631 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4632 pf->lan_nb_qps = pf->lan_nb_qp_max;
4634 qp_count += pf->lan_nb_qps;
4637 /* VF queue/VSI allocation */
4638 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4639 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4640 pf->flags |= I40E_FLAG_SRIOV;
4641 pf->vf_nb_qps = pf->vf_nb_qp_max;
4642 pf->vf_num = pci_dev->max_vfs;
4644 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4645 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4650 qp_count += pf->vf_nb_qps * pf->vf_num;
4651 vsi_count += pf->vf_num;
4653 /* VMDq queue/VSI allocation */
4654 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4655 pf->vmdq_nb_qps = 0;
4656 pf->max_nb_vmdq_vsi = 0;
4657 if (hw->func_caps.vmdq) {
4658 if (qp_count < hw->func_caps.num_tx_qp &&
4659 vsi_count < hw->func_caps.num_vsis) {
4660 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4661 qp_count) / pf->vmdq_nb_qp_max;
4663 /* Limit the maximum number of VMDq vsi to the maximum
4664 * ethdev can support
4666 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4667 hw->func_caps.num_vsis - vsi_count);
4668 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4670 if (pf->max_nb_vmdq_vsi) {
4671 pf->flags |= I40E_FLAG_VMDQ;
4672 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4674 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4675 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4676 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4679 "No enough queues left for VMDq");
4682 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4685 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4686 vsi_count += pf->max_nb_vmdq_vsi;
4688 if (hw->func_caps.dcb)
4689 pf->flags |= I40E_FLAG_DCB;
4691 if (qp_count > hw->func_caps.num_tx_qp) {
4693 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4694 qp_count, hw->func_caps.num_tx_qp);
4697 if (vsi_count > hw->func_caps.num_vsis) {
4699 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4700 vsi_count, hw->func_caps.num_vsis);
4708 i40e_pf_get_switch_config(struct i40e_pf *pf)
4710 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4711 struct i40e_aqc_get_switch_config_resp *switch_config;
4712 struct i40e_aqc_switch_config_element_resp *element;
4713 uint16_t start_seid = 0, num_reported;
4716 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4717 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4718 if (!switch_config) {
4719 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4723 /* Get the switch configurations */
4724 ret = i40e_aq_get_switch_config(hw, switch_config,
4725 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4726 if (ret != I40E_SUCCESS) {
4727 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4730 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4731 if (num_reported != 1) { /* The number should be 1 */
4732 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4736 /* Parse the switch configuration elements */
4737 element = &(switch_config->element[0]);
4738 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4739 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4740 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4742 PMD_DRV_LOG(INFO, "Unknown element type");
4745 rte_free(switch_config);
4751 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4754 struct pool_entry *entry;
4756 if (pool == NULL || num == 0)
4759 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4760 if (entry == NULL) {
4761 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4765 /* queue heap initialize */
4766 pool->num_free = num;
4767 pool->num_alloc = 0;
4769 LIST_INIT(&pool->alloc_list);
4770 LIST_INIT(&pool->free_list);
4772 /* Initialize element */
4776 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4781 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4783 struct pool_entry *entry, *next_entry;
4788 for (entry = LIST_FIRST(&pool->alloc_list);
4789 entry && (next_entry = LIST_NEXT(entry, next), 1);
4790 entry = next_entry) {
4791 LIST_REMOVE(entry, next);
4795 for (entry = LIST_FIRST(&pool->free_list);
4796 entry && (next_entry = LIST_NEXT(entry, next), 1);
4797 entry = next_entry) {
4798 LIST_REMOVE(entry, next);
4803 pool->num_alloc = 0;
4805 LIST_INIT(&pool->alloc_list);
4806 LIST_INIT(&pool->free_list);
4810 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4813 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4814 uint32_t pool_offset;
4818 PMD_DRV_LOG(ERR, "Invalid parameter");
4822 pool_offset = base - pool->base;
4823 /* Lookup in alloc list */
4824 LIST_FOREACH(entry, &pool->alloc_list, next) {
4825 if (entry->base == pool_offset) {
4826 valid_entry = entry;
4827 LIST_REMOVE(entry, next);
4832 /* Not find, return */
4833 if (valid_entry == NULL) {
4834 PMD_DRV_LOG(ERR, "Failed to find entry");
4839 * Found it, move it to free list and try to merge.
4840 * In order to make merge easier, always sort it by qbase.
4841 * Find adjacent prev and last entries.
4844 LIST_FOREACH(entry, &pool->free_list, next) {
4845 if (entry->base > valid_entry->base) {
4853 /* Try to merge with next one*/
4855 /* Merge with next one */
4856 if (valid_entry->base + valid_entry->len == next->base) {
4857 next->base = valid_entry->base;
4858 next->len += valid_entry->len;
4859 rte_free(valid_entry);
4866 /* Merge with previous one */
4867 if (prev->base + prev->len == valid_entry->base) {
4868 prev->len += valid_entry->len;
4869 /* If it merge with next one, remove next node */
4871 LIST_REMOVE(valid_entry, next);
4872 rte_free(valid_entry);
4874 rte_free(valid_entry);
4880 /* Not find any entry to merge, insert */
4883 LIST_INSERT_AFTER(prev, valid_entry, next);
4884 else if (next != NULL)
4885 LIST_INSERT_BEFORE(next, valid_entry, next);
4886 else /* It's empty list, insert to head */
4887 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4890 pool->num_free += valid_entry->len;
4891 pool->num_alloc -= valid_entry->len;
4897 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4900 struct pool_entry *entry, *valid_entry;
4902 if (pool == NULL || num == 0) {
4903 PMD_DRV_LOG(ERR, "Invalid parameter");
4907 if (pool->num_free < num) {
4908 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4909 num, pool->num_free);
4914 /* Lookup in free list and find most fit one */
4915 LIST_FOREACH(entry, &pool->free_list, next) {
4916 if (entry->len >= num) {
4918 if (entry->len == num) {
4919 valid_entry = entry;
4922 if (valid_entry == NULL || valid_entry->len > entry->len)
4923 valid_entry = entry;
4927 /* Not find one to satisfy the request, return */
4928 if (valid_entry == NULL) {
4929 PMD_DRV_LOG(ERR, "No valid entry found");
4933 * The entry have equal queue number as requested,
4934 * remove it from alloc_list.
4936 if (valid_entry->len == num) {
4937 LIST_REMOVE(valid_entry, next);
4940 * The entry have more numbers than requested,
4941 * create a new entry for alloc_list and minus its
4942 * queue base and number in free_list.
4944 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4945 if (entry == NULL) {
4947 "Failed to allocate memory for resource pool");
4950 entry->base = valid_entry->base;
4952 valid_entry->base += num;
4953 valid_entry->len -= num;
4954 valid_entry = entry;
4957 /* Insert it into alloc list, not sorted */
4958 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4960 pool->num_free -= valid_entry->len;
4961 pool->num_alloc += valid_entry->len;
4963 return valid_entry->base + pool->base;
4967 * bitmap_is_subset - Check whether src2 is subset of src1
4970 bitmap_is_subset(uint8_t src1, uint8_t src2)
4972 return !((src1 ^ src2) & src2);
4975 static enum i40e_status_code
4976 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4978 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4980 /* If DCB is not supported, only default TC is supported */
4981 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4982 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4983 return I40E_NOT_SUPPORTED;
4986 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4988 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4989 hw->func_caps.enabled_tcmap, enabled_tcmap);
4990 return I40E_NOT_SUPPORTED;
4992 return I40E_SUCCESS;
4996 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4997 struct i40e_vsi_vlan_pvid_info *info)
5000 struct i40e_vsi_context ctxt;
5001 uint8_t vlan_flags = 0;
5004 if (vsi == NULL || info == NULL) {
5005 PMD_DRV_LOG(ERR, "invalid parameters");
5006 return I40E_ERR_PARAM;
5010 vsi->info.pvid = info->config.pvid;
5012 * If insert pvid is enabled, only tagged pkts are
5013 * allowed to be sent out.
5015 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5016 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5019 if (info->config.reject.tagged == 0)
5020 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5022 if (info->config.reject.untagged == 0)
5023 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5025 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5026 I40E_AQ_VSI_PVLAN_MODE_MASK);
5027 vsi->info.port_vlan_flags |= vlan_flags;
5028 vsi->info.valid_sections =
5029 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5030 memset(&ctxt, 0, sizeof(ctxt));
5031 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5032 ctxt.seid = vsi->seid;
5034 hw = I40E_VSI_TO_HW(vsi);
5035 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5036 if (ret != I40E_SUCCESS)
5037 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5043 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5045 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5047 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5049 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5050 if (ret != I40E_SUCCESS)
5054 PMD_DRV_LOG(ERR, "seid not valid");
5058 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5059 tc_bw_data.tc_valid_bits = enabled_tcmap;
5060 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5061 tc_bw_data.tc_bw_credits[i] =
5062 (enabled_tcmap & (1 << i)) ? 1 : 0;
5064 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5065 if (ret != I40E_SUCCESS) {
5066 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5070 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5071 sizeof(vsi->info.qs_handle));
5072 return I40E_SUCCESS;
5075 static enum i40e_status_code
5076 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5077 struct i40e_aqc_vsi_properties_data *info,
5078 uint8_t enabled_tcmap)
5080 enum i40e_status_code ret;
5081 int i, total_tc = 0;
5082 uint16_t qpnum_per_tc, bsf, qp_idx;
5084 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5085 if (ret != I40E_SUCCESS)
5088 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5089 if (enabled_tcmap & (1 << i))
5093 vsi->enabled_tc = enabled_tcmap;
5095 /* Number of queues per enabled TC */
5096 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5097 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5098 bsf = rte_bsf32(qpnum_per_tc);
5100 /* Adjust the queue number to actual queues that can be applied */
5101 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5102 vsi->nb_qps = qpnum_per_tc * total_tc;
5105 * Configure TC and queue mapping parameters, for enabled TC,
5106 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5107 * default queue will serve it.
5110 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5111 if (vsi->enabled_tc & (1 << i)) {
5112 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5113 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5114 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5115 qp_idx += qpnum_per_tc;
5117 info->tc_mapping[i] = 0;
5120 /* Associate queue number with VSI */
5121 if (vsi->type == I40E_VSI_SRIOV) {
5122 info->mapping_flags |=
5123 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5124 for (i = 0; i < vsi->nb_qps; i++)
5125 info->queue_mapping[i] =
5126 rte_cpu_to_le_16(vsi->base_queue + i);
5128 info->mapping_flags |=
5129 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5130 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5132 info->valid_sections |=
5133 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5135 return I40E_SUCCESS;
5139 i40e_veb_release(struct i40e_veb *veb)
5141 struct i40e_vsi *vsi;
5147 if (!TAILQ_EMPTY(&veb->head)) {
5148 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5151 /* associate_vsi field is NULL for floating VEB */
5152 if (veb->associate_vsi != NULL) {
5153 vsi = veb->associate_vsi;
5154 hw = I40E_VSI_TO_HW(vsi);
5156 vsi->uplink_seid = veb->uplink_seid;
5159 veb->associate_pf->main_vsi->floating_veb = NULL;
5160 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5163 i40e_aq_delete_element(hw, veb->seid, NULL);
5165 return I40E_SUCCESS;
5169 static struct i40e_veb *
5170 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5172 struct i40e_veb *veb;
5178 "veb setup failed, associated PF shouldn't null");
5181 hw = I40E_PF_TO_HW(pf);
5183 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5185 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5189 veb->associate_vsi = vsi;
5190 veb->associate_pf = pf;
5191 TAILQ_INIT(&veb->head);
5192 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5194 /* create floating veb if vsi is NULL */
5196 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5197 I40E_DEFAULT_TCMAP, false,
5198 &veb->seid, false, NULL);
5200 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5201 true, &veb->seid, false, NULL);
5204 if (ret != I40E_SUCCESS) {
5205 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5206 hw->aq.asq_last_status);
5209 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5211 /* get statistics index */
5212 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5213 &veb->stats_idx, NULL, NULL, NULL);
5214 if (ret != I40E_SUCCESS) {
5215 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5216 hw->aq.asq_last_status);
5219 /* Get VEB bandwidth, to be implemented */
5220 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5222 vsi->uplink_seid = veb->seid;
5231 i40e_vsi_release(struct i40e_vsi *vsi)
5235 struct i40e_vsi_list *vsi_list;
5238 struct i40e_mac_filter *f;
5239 uint16_t user_param;
5242 return I40E_SUCCESS;
5247 user_param = vsi->user_param;
5249 pf = I40E_VSI_TO_PF(vsi);
5250 hw = I40E_VSI_TO_HW(vsi);
5252 /* VSI has child to attach, release child first */
5254 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5255 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5258 i40e_veb_release(vsi->veb);
5261 if (vsi->floating_veb) {
5262 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5263 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5268 /* Remove all macvlan filters of the VSI */
5269 i40e_vsi_remove_all_macvlan_filter(vsi);
5270 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5273 if (vsi->type != I40E_VSI_MAIN &&
5274 ((vsi->type != I40E_VSI_SRIOV) ||
5275 !pf->floating_veb_list[user_param])) {
5276 /* Remove vsi from parent's sibling list */
5277 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5278 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5279 return I40E_ERR_PARAM;
5281 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5282 &vsi->sib_vsi_list, list);
5284 /* Remove all switch element of the VSI */
5285 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5286 if (ret != I40E_SUCCESS)
5287 PMD_DRV_LOG(ERR, "Failed to delete element");
5290 if ((vsi->type == I40E_VSI_SRIOV) &&
5291 pf->floating_veb_list[user_param]) {
5292 /* Remove vsi from parent's sibling list */
5293 if (vsi->parent_vsi == NULL ||
5294 vsi->parent_vsi->floating_veb == NULL) {
5295 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5296 return I40E_ERR_PARAM;
5298 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5299 &vsi->sib_vsi_list, list);
5301 /* Remove all switch element of the VSI */
5302 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5303 if (ret != I40E_SUCCESS)
5304 PMD_DRV_LOG(ERR, "Failed to delete element");
5307 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5309 if (vsi->type != I40E_VSI_SRIOV)
5310 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5313 return I40E_SUCCESS;
5317 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5319 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5320 struct i40e_aqc_remove_macvlan_element_data def_filter;
5321 struct i40e_mac_filter_info filter;
5324 if (vsi->type != I40E_VSI_MAIN)
5325 return I40E_ERR_CONFIG;
5326 memset(&def_filter, 0, sizeof(def_filter));
5327 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5329 def_filter.vlan_tag = 0;
5330 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5331 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5332 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5333 if (ret != I40E_SUCCESS) {
5334 struct i40e_mac_filter *f;
5335 struct rte_ether_addr *mac;
5338 "Cannot remove the default macvlan filter");
5339 /* It needs to add the permanent mac into mac list */
5340 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5342 PMD_DRV_LOG(ERR, "failed to allocate memory");
5343 return I40E_ERR_NO_MEMORY;
5345 mac = &f->mac_info.mac_addr;
5346 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5348 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5349 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5354 rte_memcpy(&filter.mac_addr,
5355 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5356 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5357 return i40e_vsi_add_mac(vsi, &filter);
5361 * i40e_vsi_get_bw_config - Query VSI BW Information
5362 * @vsi: the VSI to be queried
5364 * Returns 0 on success, negative value on failure
5366 static enum i40e_status_code
5367 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5369 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5370 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5371 struct i40e_hw *hw = &vsi->adapter->hw;
5376 memset(&bw_config, 0, sizeof(bw_config));
5377 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5378 if (ret != I40E_SUCCESS) {
5379 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5380 hw->aq.asq_last_status);
5384 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5385 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5386 &ets_sla_config, NULL);
5387 if (ret != I40E_SUCCESS) {
5389 "VSI failed to get TC bandwdith configuration %u",
5390 hw->aq.asq_last_status);
5394 /* store and print out BW info */
5395 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5396 vsi->bw_info.bw_max = bw_config.max_bw;
5397 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5398 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5399 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5400 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5402 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5403 vsi->bw_info.bw_ets_share_credits[i] =
5404 ets_sla_config.share_credits[i];
5405 vsi->bw_info.bw_ets_credits[i] =
5406 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5407 /* 4 bits per TC, 4th bit is reserved */
5408 vsi->bw_info.bw_ets_max[i] =
5409 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5410 RTE_LEN2MASK(3, uint8_t));
5411 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5412 vsi->bw_info.bw_ets_share_credits[i]);
5413 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5414 vsi->bw_info.bw_ets_credits[i]);
5415 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5416 vsi->bw_info.bw_ets_max[i]);
5419 return I40E_SUCCESS;
5422 /* i40e_enable_pf_lb
5423 * @pf: pointer to the pf structure
5425 * allow loopback on pf
5428 i40e_enable_pf_lb(struct i40e_pf *pf)
5430 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5431 struct i40e_vsi_context ctxt;
5434 /* Use the FW API if FW >= v5.0 */
5435 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5436 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5440 memset(&ctxt, 0, sizeof(ctxt));
5441 ctxt.seid = pf->main_vsi_seid;
5442 ctxt.pf_num = hw->pf_id;
5443 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5445 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5446 ret, hw->aq.asq_last_status);
5449 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5450 ctxt.info.valid_sections =
5451 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5452 ctxt.info.switch_id |=
5453 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5455 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5457 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5458 hw->aq.asq_last_status);
5463 i40e_vsi_setup(struct i40e_pf *pf,
5464 enum i40e_vsi_type type,
5465 struct i40e_vsi *uplink_vsi,
5466 uint16_t user_param)
5468 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5469 struct i40e_vsi *vsi;
5470 struct i40e_mac_filter_info filter;
5472 struct i40e_vsi_context ctxt;
5473 struct rte_ether_addr broadcast =
5474 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5476 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5477 uplink_vsi == NULL) {
5479 "VSI setup failed, VSI link shouldn't be NULL");
5483 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5485 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5490 * 1.type is not MAIN and uplink vsi is not NULL
5491 * If uplink vsi didn't setup VEB, create one first under veb field
5492 * 2.type is SRIOV and the uplink is NULL
5493 * If floating VEB is NULL, create one veb under floating veb field
5496 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5497 uplink_vsi->veb == NULL) {
5498 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5500 if (uplink_vsi->veb == NULL) {
5501 PMD_DRV_LOG(ERR, "VEB setup failed");
5504 /* set ALLOWLOOPBACk on pf, when veb is created */
5505 i40e_enable_pf_lb(pf);
5508 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5509 pf->main_vsi->floating_veb == NULL) {
5510 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5512 if (pf->main_vsi->floating_veb == NULL) {
5513 PMD_DRV_LOG(ERR, "VEB setup failed");
5518 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5520 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5523 TAILQ_INIT(&vsi->mac_list);
5525 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5526 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5527 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5528 vsi->user_param = user_param;
5529 vsi->vlan_anti_spoof_on = 0;
5530 vsi->vlan_filter_on = 0;
5531 /* Allocate queues */
5532 switch (vsi->type) {
5533 case I40E_VSI_MAIN :
5534 vsi->nb_qps = pf->lan_nb_qps;
5536 case I40E_VSI_SRIOV :
5537 vsi->nb_qps = pf->vf_nb_qps;
5539 case I40E_VSI_VMDQ2:
5540 vsi->nb_qps = pf->vmdq_nb_qps;
5543 vsi->nb_qps = pf->fdir_nb_qps;
5549 * The filter status descriptor is reported in rx queue 0,
5550 * while the tx queue for fdir filter programming has no
5551 * such constraints, can be non-zero queues.
5552 * To simplify it, choose FDIR vsi use queue 0 pair.
5553 * To make sure it will use queue 0 pair, queue allocation
5554 * need be done before this function is called
5556 if (type != I40E_VSI_FDIR) {
5557 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5559 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5563 vsi->base_queue = ret;
5565 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5567 /* VF has MSIX interrupt in VF range, don't allocate here */
5568 if (type == I40E_VSI_MAIN) {
5569 if (pf->support_multi_driver) {
5570 /* If support multi-driver, need to use INT0 instead of
5571 * allocating from msix pool. The Msix pool is init from
5572 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5573 * to 1 without calling i40e_res_pool_alloc.
5578 ret = i40e_res_pool_alloc(&pf->msix_pool,
5579 RTE_MIN(vsi->nb_qps,
5580 RTE_MAX_RXTX_INTR_VEC_ID));
5583 "VSI MAIN %d get heap failed %d",
5585 goto fail_queue_alloc;
5587 vsi->msix_intr = ret;
5588 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5589 RTE_MAX_RXTX_INTR_VEC_ID);
5591 } else if (type != I40E_VSI_SRIOV) {
5592 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5594 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5595 goto fail_queue_alloc;
5597 vsi->msix_intr = ret;
5605 if (type == I40E_VSI_MAIN) {
5606 /* For main VSI, no need to add since it's default one */
5607 vsi->uplink_seid = pf->mac_seid;
5608 vsi->seid = pf->main_vsi_seid;
5609 /* Bind queues with specific MSIX interrupt */
5611 * Needs 2 interrupt at least, one for misc cause which will
5612 * enabled from OS side, Another for queues binding the
5613 * interrupt from device side only.
5616 /* Get default VSI parameters from hardware */
5617 memset(&ctxt, 0, sizeof(ctxt));
5618 ctxt.seid = vsi->seid;
5619 ctxt.pf_num = hw->pf_id;
5620 ctxt.uplink_seid = vsi->uplink_seid;
5622 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5623 if (ret != I40E_SUCCESS) {
5624 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5625 goto fail_msix_alloc;
5627 rte_memcpy(&vsi->info, &ctxt.info,
5628 sizeof(struct i40e_aqc_vsi_properties_data));
5629 vsi->vsi_id = ctxt.vsi_number;
5630 vsi->info.valid_sections = 0;
5632 /* Configure tc, enabled TC0 only */
5633 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5635 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5636 goto fail_msix_alloc;
5639 /* TC, queue mapping */
5640 memset(&ctxt, 0, sizeof(ctxt));
5641 vsi->info.valid_sections |=
5642 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5643 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5644 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5645 rte_memcpy(&ctxt.info, &vsi->info,
5646 sizeof(struct i40e_aqc_vsi_properties_data));
5647 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5648 I40E_DEFAULT_TCMAP);
5649 if (ret != I40E_SUCCESS) {
5651 "Failed to configure TC queue mapping");
5652 goto fail_msix_alloc;
5654 ctxt.seid = vsi->seid;
5655 ctxt.pf_num = hw->pf_id;
5656 ctxt.uplink_seid = vsi->uplink_seid;
5659 /* Update VSI parameters */
5660 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5661 if (ret != I40E_SUCCESS) {
5662 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5663 goto fail_msix_alloc;
5666 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5667 sizeof(vsi->info.tc_mapping));
5668 rte_memcpy(&vsi->info.queue_mapping,
5669 &ctxt.info.queue_mapping,
5670 sizeof(vsi->info.queue_mapping));
5671 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5672 vsi->info.valid_sections = 0;
5674 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5678 * Updating default filter settings are necessary to prevent
5679 * reception of tagged packets.
5680 * Some old firmware configurations load a default macvlan
5681 * filter which accepts both tagged and untagged packets.
5682 * The updating is to use a normal filter instead if needed.
5683 * For NVM 4.2.2 or after, the updating is not needed anymore.
5684 * The firmware with correct configurations load the default
5685 * macvlan filter which is expected and cannot be removed.
5687 i40e_update_default_filter_setting(vsi);
5688 i40e_config_qinq(hw, vsi);
5689 } else if (type == I40E_VSI_SRIOV) {
5690 memset(&ctxt, 0, sizeof(ctxt));
5692 * For other VSI, the uplink_seid equals to uplink VSI's
5693 * uplink_seid since they share same VEB
5695 if (uplink_vsi == NULL)
5696 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5698 vsi->uplink_seid = uplink_vsi->uplink_seid;
5699 ctxt.pf_num = hw->pf_id;
5700 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5701 ctxt.uplink_seid = vsi->uplink_seid;
5702 ctxt.connection_type = 0x1;
5703 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5705 /* Use the VEB configuration if FW >= v5.0 */
5706 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5707 /* Configure switch ID */
5708 ctxt.info.valid_sections |=
5709 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5710 ctxt.info.switch_id =
5711 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5714 /* Configure port/vlan */
5715 ctxt.info.valid_sections |=
5716 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5717 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5718 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5719 hw->func_caps.enabled_tcmap);
5720 if (ret != I40E_SUCCESS) {
5722 "Failed to configure TC queue mapping");
5723 goto fail_msix_alloc;
5726 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5727 ctxt.info.valid_sections |=
5728 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5730 * Since VSI is not created yet, only configure parameter,
5731 * will add vsi below.
5734 i40e_config_qinq(hw, vsi);
5735 } else if (type == I40E_VSI_VMDQ2) {
5736 memset(&ctxt, 0, sizeof(ctxt));
5738 * For other VSI, the uplink_seid equals to uplink VSI's
5739 * uplink_seid since they share same VEB
5741 vsi->uplink_seid = uplink_vsi->uplink_seid;
5742 ctxt.pf_num = hw->pf_id;
5744 ctxt.uplink_seid = vsi->uplink_seid;
5745 ctxt.connection_type = 0x1;
5746 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5748 ctxt.info.valid_sections |=
5749 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5750 /* user_param carries flag to enable loop back */
5752 ctxt.info.switch_id =
5753 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5754 ctxt.info.switch_id |=
5755 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5758 /* Configure port/vlan */
5759 ctxt.info.valid_sections |=
5760 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5761 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5762 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5763 I40E_DEFAULT_TCMAP);
5764 if (ret != I40E_SUCCESS) {
5766 "Failed to configure TC queue mapping");
5767 goto fail_msix_alloc;
5769 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5770 ctxt.info.valid_sections |=
5771 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5772 } else if (type == I40E_VSI_FDIR) {
5773 memset(&ctxt, 0, sizeof(ctxt));
5774 vsi->uplink_seid = uplink_vsi->uplink_seid;
5775 ctxt.pf_num = hw->pf_id;
5777 ctxt.uplink_seid = vsi->uplink_seid;
5778 ctxt.connection_type = 0x1; /* regular data port */
5779 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5780 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5781 I40E_DEFAULT_TCMAP);
5782 if (ret != I40E_SUCCESS) {
5784 "Failed to configure TC queue mapping.");
5785 goto fail_msix_alloc;
5787 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5788 ctxt.info.valid_sections |=
5789 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5791 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5792 goto fail_msix_alloc;
5795 if (vsi->type != I40E_VSI_MAIN) {
5796 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5797 if (ret != I40E_SUCCESS) {
5798 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5799 hw->aq.asq_last_status);
5800 goto fail_msix_alloc;
5802 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5803 vsi->info.valid_sections = 0;
5804 vsi->seid = ctxt.seid;
5805 vsi->vsi_id = ctxt.vsi_number;
5806 vsi->sib_vsi_list.vsi = vsi;
5807 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5808 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5809 &vsi->sib_vsi_list, list);
5811 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5812 &vsi->sib_vsi_list, list);
5816 /* MAC/VLAN configuration */
5817 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5818 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5820 ret = i40e_vsi_add_mac(vsi, &filter);
5821 if (ret != I40E_SUCCESS) {
5822 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5823 goto fail_msix_alloc;
5826 /* Get VSI BW information */
5827 i40e_vsi_get_bw_config(vsi);
5830 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5832 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5838 /* Configure vlan filter on or off */
5840 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5843 struct i40e_mac_filter *f;
5845 struct i40e_mac_filter_info *mac_filter;
5846 enum rte_mac_filter_type desired_filter;
5847 int ret = I40E_SUCCESS;
5850 /* Filter to match MAC and VLAN */
5851 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5853 /* Filter to match only MAC */
5854 desired_filter = RTE_MAC_PERFECT_MATCH;
5859 mac_filter = rte_zmalloc("mac_filter_info_data",
5860 num * sizeof(*mac_filter), 0);
5861 if (mac_filter == NULL) {
5862 PMD_DRV_LOG(ERR, "failed to allocate memory");
5863 return I40E_ERR_NO_MEMORY;
5868 /* Remove all existing mac */
5869 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5870 mac_filter[i] = f->mac_info;
5871 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5873 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5874 on ? "enable" : "disable");
5880 /* Override with new filter */
5881 for (i = 0; i < num; i++) {
5882 mac_filter[i].filter_type = desired_filter;
5883 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5885 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5886 on ? "enable" : "disable");
5892 rte_free(mac_filter);
5896 /* Configure vlan stripping on or off */
5898 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5900 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5901 struct i40e_vsi_context ctxt;
5903 int ret = I40E_SUCCESS;
5905 /* Check if it has been already on or off */
5906 if (vsi->info.valid_sections &
5907 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5909 if ((vsi->info.port_vlan_flags &
5910 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5911 return 0; /* already on */
5913 if ((vsi->info.port_vlan_flags &
5914 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5915 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5916 return 0; /* already off */
5921 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5923 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5924 vsi->info.valid_sections =
5925 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5926 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5927 vsi->info.port_vlan_flags |= vlan_flags;
5928 ctxt.seid = vsi->seid;
5929 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5930 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5932 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5933 on ? "enable" : "disable");
5939 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5941 struct rte_eth_dev_data *data = dev->data;
5945 /* Apply vlan offload setting */
5946 mask = ETH_VLAN_STRIP_MASK |
5947 ETH_VLAN_FILTER_MASK |
5948 ETH_VLAN_EXTEND_MASK;
5949 ret = i40e_vlan_offload_set(dev, mask);
5951 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5955 /* Apply pvid setting */
5956 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5957 data->dev_conf.txmode.hw_vlan_insert_pvid);
5959 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5965 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5967 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5969 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5973 i40e_update_flow_control(struct i40e_hw *hw)
5975 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5976 struct i40e_link_status link_status;
5977 uint32_t rxfc = 0, txfc = 0, reg;
5981 memset(&link_status, 0, sizeof(link_status));
5982 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5983 if (ret != I40E_SUCCESS) {
5984 PMD_DRV_LOG(ERR, "Failed to get link status information");
5985 goto write_reg; /* Disable flow control */
5988 an_info = hw->phy.link_info.an_info;
5989 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5990 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5991 ret = I40E_ERR_NOT_READY;
5992 goto write_reg; /* Disable flow control */
5995 * If link auto negotiation is enabled, flow control needs to
5996 * be configured according to it
5998 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5999 case I40E_LINK_PAUSE_RXTX:
6002 hw->fc.current_mode = I40E_FC_FULL;
6004 case I40E_AQ_LINK_PAUSE_RX:
6006 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6008 case I40E_AQ_LINK_PAUSE_TX:
6010 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6013 hw->fc.current_mode = I40E_FC_NONE;
6018 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6019 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6020 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6021 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6022 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6023 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6030 i40e_pf_setup(struct i40e_pf *pf)
6032 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6033 struct i40e_filter_control_settings settings;
6034 struct i40e_vsi *vsi;
6037 /* Clear all stats counters */
6038 pf->offset_loaded = FALSE;
6039 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6040 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6041 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6042 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6044 ret = i40e_pf_get_switch_config(pf);
6045 if (ret != I40E_SUCCESS) {
6046 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6050 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6052 PMD_INIT_LOG(WARNING,
6053 "failed to allocate switch domain for device %d", ret);
6055 if (pf->flags & I40E_FLAG_FDIR) {
6056 /* make queue allocated first, let FDIR use queue pair 0*/
6057 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6058 if (ret != I40E_FDIR_QUEUE_ID) {
6060 "queue allocation fails for FDIR: ret =%d",
6062 pf->flags &= ~I40E_FLAG_FDIR;
6065 /* main VSI setup */
6066 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6068 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6069 return I40E_ERR_NOT_READY;
6073 /* Configure filter control */
6074 memset(&settings, 0, sizeof(settings));
6075 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6076 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6077 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6078 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6080 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6081 hw->func_caps.rss_table_size);
6082 return I40E_ERR_PARAM;
6084 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6085 hw->func_caps.rss_table_size);
6086 pf->hash_lut_size = hw->func_caps.rss_table_size;
6088 /* Enable ethtype and macvlan filters */
6089 settings.enable_ethtype = TRUE;
6090 settings.enable_macvlan = TRUE;
6091 ret = i40e_set_filter_control(hw, &settings);
6093 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6096 /* Update flow control according to the auto negotiation */
6097 i40e_update_flow_control(hw);
6099 return I40E_SUCCESS;
6103 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6109 * Set or clear TX Queue Disable flags,
6110 * which is required by hardware.
6112 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6113 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6115 /* Wait until the request is finished */
6116 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6117 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6118 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6119 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6120 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6126 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6127 return I40E_SUCCESS; /* already on, skip next steps */
6129 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6130 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6132 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6133 return I40E_SUCCESS; /* already off, skip next steps */
6134 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6136 /* Write the register */
6137 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6138 /* Check the result */
6139 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6140 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6141 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6143 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6144 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6147 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6148 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6152 /* Check if it is timeout */
6153 if (j >= I40E_CHK_Q_ENA_COUNT) {
6154 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6155 (on ? "enable" : "disable"), q_idx);
6156 return I40E_ERR_TIMEOUT;
6159 return I40E_SUCCESS;
6162 /* Swith on or off the tx queues */
6164 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6166 struct rte_eth_dev_data *dev_data = pf->dev_data;
6167 struct i40e_tx_queue *txq;
6168 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6172 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6173 txq = dev_data->tx_queues[i];
6174 /* Don't operate the queue if not configured or
6175 * if starting only per queue */
6176 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6179 ret = i40e_dev_tx_queue_start(dev, i);
6181 ret = i40e_dev_tx_queue_stop(dev, i);
6182 if ( ret != I40E_SUCCESS)
6186 return I40E_SUCCESS;
6190 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6195 /* Wait until the request is finished */
6196 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6197 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6198 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6199 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6200 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6205 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6206 return I40E_SUCCESS; /* Already on, skip next steps */
6207 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6209 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6210 return I40E_SUCCESS; /* Already off, skip next steps */
6211 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6214 /* Write the register */
6215 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6216 /* Check the result */
6217 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6218 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6219 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6221 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6222 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6225 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6226 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6231 /* Check if it is timeout */
6232 if (j >= I40E_CHK_Q_ENA_COUNT) {
6233 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6234 (on ? "enable" : "disable"), q_idx);
6235 return I40E_ERR_TIMEOUT;
6238 return I40E_SUCCESS;
6240 /* Switch on or off the rx queues */
6242 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6244 struct rte_eth_dev_data *dev_data = pf->dev_data;
6245 struct i40e_rx_queue *rxq;
6246 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6250 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6251 rxq = dev_data->rx_queues[i];
6252 /* Don't operate the queue if not configured or
6253 * if starting only per queue */
6254 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6257 ret = i40e_dev_rx_queue_start(dev, i);
6259 ret = i40e_dev_rx_queue_stop(dev, i);
6260 if (ret != I40E_SUCCESS)
6264 return I40E_SUCCESS;
6267 /* Switch on or off all the rx/tx queues */
6269 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6274 /* enable rx queues before enabling tx queues */
6275 ret = i40e_dev_switch_rx_queues(pf, on);
6277 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6280 ret = i40e_dev_switch_tx_queues(pf, on);
6282 /* Stop tx queues before stopping rx queues */
6283 ret = i40e_dev_switch_tx_queues(pf, on);
6285 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6288 ret = i40e_dev_switch_rx_queues(pf, on);
6294 /* Initialize VSI for TX */
6296 i40e_dev_tx_init(struct i40e_pf *pf)
6298 struct rte_eth_dev_data *data = pf->dev_data;
6300 uint32_t ret = I40E_SUCCESS;
6301 struct i40e_tx_queue *txq;
6303 for (i = 0; i < data->nb_tx_queues; i++) {
6304 txq = data->tx_queues[i];
6305 if (!txq || !txq->q_set)
6307 ret = i40e_tx_queue_init(txq);
6308 if (ret != I40E_SUCCESS)
6311 if (ret == I40E_SUCCESS)
6312 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6318 /* Initialize VSI for RX */
6320 i40e_dev_rx_init(struct i40e_pf *pf)
6322 struct rte_eth_dev_data *data = pf->dev_data;
6323 int ret = I40E_SUCCESS;
6325 struct i40e_rx_queue *rxq;
6327 i40e_pf_config_mq_rx(pf);
6328 for (i = 0; i < data->nb_rx_queues; i++) {
6329 rxq = data->rx_queues[i];
6330 if (!rxq || !rxq->q_set)
6333 ret = i40e_rx_queue_init(rxq);
6334 if (ret != I40E_SUCCESS) {
6336 "Failed to do RX queue initialization");
6340 if (ret == I40E_SUCCESS)
6341 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6348 i40e_dev_rxtx_init(struct i40e_pf *pf)
6352 err = i40e_dev_tx_init(pf);
6354 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6357 err = i40e_dev_rx_init(pf);
6359 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6367 i40e_vmdq_setup(struct rte_eth_dev *dev)
6369 struct rte_eth_conf *conf = &dev->data->dev_conf;
6370 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6371 int i, err, conf_vsis, j, loop;
6372 struct i40e_vsi *vsi;
6373 struct i40e_vmdq_info *vmdq_info;
6374 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6375 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6378 * Disable interrupt to avoid message from VF. Furthermore, it will
6379 * avoid race condition in VSI creation/destroy.
6381 i40e_pf_disable_irq0(hw);
6383 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6384 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6388 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6389 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6390 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6391 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6392 pf->max_nb_vmdq_vsi);
6396 if (pf->vmdq != NULL) {
6397 PMD_INIT_LOG(INFO, "VMDQ already configured");
6401 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6402 sizeof(*vmdq_info) * conf_vsis, 0);
6404 if (pf->vmdq == NULL) {
6405 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6409 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6411 /* Create VMDQ VSI */
6412 for (i = 0; i < conf_vsis; i++) {
6413 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6414 vmdq_conf->enable_loop_back);
6416 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6420 vmdq_info = &pf->vmdq[i];
6422 vmdq_info->vsi = vsi;
6424 pf->nb_cfg_vmdq_vsi = conf_vsis;
6426 /* Configure Vlan */
6427 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6428 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6429 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6430 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6431 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6432 vmdq_conf->pool_map[i].vlan_id, j);
6434 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6435 vmdq_conf->pool_map[i].vlan_id);
6437 PMD_INIT_LOG(ERR, "Failed to add vlan");
6445 i40e_pf_enable_irq0(hw);
6450 for (i = 0; i < conf_vsis; i++)
6451 if (pf->vmdq[i].vsi == NULL)
6454 i40e_vsi_release(pf->vmdq[i].vsi);
6458 i40e_pf_enable_irq0(hw);
6463 i40e_stat_update_32(struct i40e_hw *hw,
6471 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6475 if (new_data >= *offset)
6476 *stat = (uint64_t)(new_data - *offset);
6478 *stat = (uint64_t)((new_data +
6479 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6483 i40e_stat_update_48(struct i40e_hw *hw,
6492 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6493 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6494 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6499 if (new_data >= *offset)
6500 *stat = new_data - *offset;
6502 *stat = (uint64_t)((new_data +
6503 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6505 *stat &= I40E_48_BIT_MASK;
6510 i40e_pf_disable_irq0(struct i40e_hw *hw)
6512 /* Disable all interrupt types */
6513 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6514 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6515 I40E_WRITE_FLUSH(hw);
6520 i40e_pf_enable_irq0(struct i40e_hw *hw)
6522 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6523 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6524 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6525 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6526 I40E_WRITE_FLUSH(hw);
6530 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6532 /* read pending request and disable first */
6533 i40e_pf_disable_irq0(hw);
6534 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6535 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6536 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6539 /* Link no queues with irq0 */
6540 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6541 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6545 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6547 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6548 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6551 uint32_t index, offset, val;
6556 * Try to find which VF trigger a reset, use absolute VF id to access
6557 * since the reg is global register.
6559 for (i = 0; i < pf->vf_num; i++) {
6560 abs_vf_id = hw->func_caps.vf_base_id + i;
6561 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6562 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6563 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6564 /* VFR event occurred */
6565 if (val & (0x1 << offset)) {
6568 /* Clear the event first */
6569 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6571 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6573 * Only notify a VF reset event occurred,
6574 * don't trigger another SW reset
6576 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6577 if (ret != I40E_SUCCESS)
6578 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6584 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6586 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6589 for (i = 0; i < pf->vf_num; i++)
6590 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6594 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6596 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6597 struct i40e_arq_event_info info;
6598 uint16_t pending, opcode;
6601 info.buf_len = I40E_AQ_BUF_SZ;
6602 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6603 if (!info.msg_buf) {
6604 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6610 ret = i40e_clean_arq_element(hw, &info, &pending);
6612 if (ret != I40E_SUCCESS) {
6614 "Failed to read msg from AdminQ, aq_err: %u",
6615 hw->aq.asq_last_status);
6618 opcode = rte_le_to_cpu_16(info.desc.opcode);
6621 case i40e_aqc_opc_send_msg_to_pf:
6622 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6623 i40e_pf_host_handle_vf_msg(dev,
6624 rte_le_to_cpu_16(info.desc.retval),
6625 rte_le_to_cpu_32(info.desc.cookie_high),
6626 rte_le_to_cpu_32(info.desc.cookie_low),
6630 case i40e_aqc_opc_get_link_status:
6631 ret = i40e_dev_link_update(dev, 0);
6633 _rte_eth_dev_callback_process(dev,
6634 RTE_ETH_EVENT_INTR_LSC, NULL);
6637 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6642 rte_free(info.msg_buf);
6646 * Interrupt handler triggered by NIC for handling
6647 * specific interrupt.
6650 * Pointer to interrupt handle.
6652 * The address of parameter (struct rte_eth_dev *) regsitered before.
6658 i40e_dev_interrupt_handler(void *param)
6660 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6661 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6664 /* Disable interrupt */
6665 i40e_pf_disable_irq0(hw);
6667 /* read out interrupt causes */
6668 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6670 /* No interrupt event indicated */
6671 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6672 PMD_DRV_LOG(INFO, "No interrupt event");
6675 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6676 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6677 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6678 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6679 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6680 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6681 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6682 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6683 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6684 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6685 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6686 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6687 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6688 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6690 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6691 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6692 i40e_dev_handle_vfr_event(dev);
6694 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6695 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6696 i40e_dev_handle_aq_msg(dev);
6700 /* Enable interrupt */
6701 i40e_pf_enable_irq0(hw);
6705 i40e_dev_alarm_handler(void *param)
6707 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6708 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6711 /* Disable interrupt */
6712 i40e_pf_disable_irq0(hw);
6714 /* read out interrupt causes */
6715 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6717 /* No interrupt event indicated */
6718 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6720 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6721 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6722 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6723 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6724 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6725 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6726 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6727 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6728 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6729 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6730 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6731 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6732 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6733 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6735 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6736 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6737 i40e_dev_handle_vfr_event(dev);
6739 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6740 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6741 i40e_dev_handle_aq_msg(dev);
6745 /* Enable interrupt */
6746 i40e_pf_enable_irq0(hw);
6747 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6748 i40e_dev_alarm_handler, dev);
6752 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6753 struct i40e_macvlan_filter *filter,
6756 int ele_num, ele_buff_size;
6757 int num, actual_num, i;
6759 int ret = I40E_SUCCESS;
6760 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6761 struct i40e_aqc_add_macvlan_element_data *req_list;
6763 if (filter == NULL || total == 0)
6764 return I40E_ERR_PARAM;
6765 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6766 ele_buff_size = hw->aq.asq_buf_size;
6768 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6769 if (req_list == NULL) {
6770 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6771 return I40E_ERR_NO_MEMORY;
6776 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6777 memset(req_list, 0, ele_buff_size);
6779 for (i = 0; i < actual_num; i++) {
6780 rte_memcpy(req_list[i].mac_addr,
6781 &filter[num + i].macaddr, ETH_ADDR_LEN);
6782 req_list[i].vlan_tag =
6783 rte_cpu_to_le_16(filter[num + i].vlan_id);
6785 switch (filter[num + i].filter_type) {
6786 case RTE_MAC_PERFECT_MATCH:
6787 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6788 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6790 case RTE_MACVLAN_PERFECT_MATCH:
6791 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6793 case RTE_MAC_HASH_MATCH:
6794 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6795 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6797 case RTE_MACVLAN_HASH_MATCH:
6798 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6801 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6802 ret = I40E_ERR_PARAM;
6806 req_list[i].queue_number = 0;
6808 req_list[i].flags = rte_cpu_to_le_16(flags);
6811 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6813 if (ret != I40E_SUCCESS) {
6814 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6818 } while (num < total);
6826 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6827 struct i40e_macvlan_filter *filter,
6830 int ele_num, ele_buff_size;
6831 int num, actual_num, i;
6833 int ret = I40E_SUCCESS;
6834 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6835 struct i40e_aqc_remove_macvlan_element_data *req_list;
6837 if (filter == NULL || total == 0)
6838 return I40E_ERR_PARAM;
6840 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6841 ele_buff_size = hw->aq.asq_buf_size;
6843 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6844 if (req_list == NULL) {
6845 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6846 return I40E_ERR_NO_MEMORY;
6851 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6852 memset(req_list, 0, ele_buff_size);
6854 for (i = 0; i < actual_num; i++) {
6855 rte_memcpy(req_list[i].mac_addr,
6856 &filter[num + i].macaddr, ETH_ADDR_LEN);
6857 req_list[i].vlan_tag =
6858 rte_cpu_to_le_16(filter[num + i].vlan_id);
6860 switch (filter[num + i].filter_type) {
6861 case RTE_MAC_PERFECT_MATCH:
6862 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6863 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6865 case RTE_MACVLAN_PERFECT_MATCH:
6866 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6868 case RTE_MAC_HASH_MATCH:
6869 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6870 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6872 case RTE_MACVLAN_HASH_MATCH:
6873 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6876 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6877 ret = I40E_ERR_PARAM;
6880 req_list[i].flags = rte_cpu_to_le_16(flags);
6883 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6885 if (ret != I40E_SUCCESS) {
6886 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6890 } while (num < total);
6897 /* Find out specific MAC filter */
6898 static struct i40e_mac_filter *
6899 i40e_find_mac_filter(struct i40e_vsi *vsi,
6900 struct rte_ether_addr *macaddr)
6902 struct i40e_mac_filter *f;
6904 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6905 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6913 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6916 uint32_t vid_idx, vid_bit;
6918 if (vlan_id > ETH_VLAN_ID_MAX)
6921 vid_idx = I40E_VFTA_IDX(vlan_id);
6922 vid_bit = I40E_VFTA_BIT(vlan_id);
6924 if (vsi->vfta[vid_idx] & vid_bit)
6931 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6932 uint16_t vlan_id, bool on)
6934 uint32_t vid_idx, vid_bit;
6936 vid_idx = I40E_VFTA_IDX(vlan_id);
6937 vid_bit = I40E_VFTA_BIT(vlan_id);
6940 vsi->vfta[vid_idx] |= vid_bit;
6942 vsi->vfta[vid_idx] &= ~vid_bit;
6946 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6947 uint16_t vlan_id, bool on)
6949 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6950 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6953 if (vlan_id > ETH_VLAN_ID_MAX)
6956 i40e_store_vlan_filter(vsi, vlan_id, on);
6958 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6961 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6964 ret = i40e_aq_add_vlan(hw, vsi->seid,
6965 &vlan_data, 1, NULL);
6966 if (ret != I40E_SUCCESS)
6967 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6969 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6970 &vlan_data, 1, NULL);
6971 if (ret != I40E_SUCCESS)
6973 "Failed to remove vlan filter");
6978 * Find all vlan options for specific mac addr,
6979 * return with actual vlan found.
6982 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6983 struct i40e_macvlan_filter *mv_f,
6984 int num, struct rte_ether_addr *addr)
6990 * Not to use i40e_find_vlan_filter to decrease the loop time,
6991 * although the code looks complex.
6993 if (num < vsi->vlan_num)
6994 return I40E_ERR_PARAM;
6997 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6999 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7000 if (vsi->vfta[j] & (1 << k)) {
7003 "vlan number doesn't match");
7004 return I40E_ERR_PARAM;
7006 rte_memcpy(&mv_f[i].macaddr,
7007 addr, ETH_ADDR_LEN);
7009 j * I40E_UINT32_BIT_SIZE + k;
7015 return I40E_SUCCESS;
7019 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7020 struct i40e_macvlan_filter *mv_f,
7025 struct i40e_mac_filter *f;
7027 if (num < vsi->mac_num)
7028 return I40E_ERR_PARAM;
7030 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7032 PMD_DRV_LOG(ERR, "buffer number not match");
7033 return I40E_ERR_PARAM;
7035 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7037 mv_f[i].vlan_id = vlan;
7038 mv_f[i].filter_type = f->mac_info.filter_type;
7042 return I40E_SUCCESS;
7046 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7049 struct i40e_mac_filter *f;
7050 struct i40e_macvlan_filter *mv_f;
7051 int ret = I40E_SUCCESS;
7053 if (vsi == NULL || vsi->mac_num == 0)
7054 return I40E_ERR_PARAM;
7056 /* Case that no vlan is set */
7057 if (vsi->vlan_num == 0)
7060 num = vsi->mac_num * vsi->vlan_num;
7062 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7064 PMD_DRV_LOG(ERR, "failed to allocate memory");
7065 return I40E_ERR_NO_MEMORY;
7069 if (vsi->vlan_num == 0) {
7070 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7071 rte_memcpy(&mv_f[i].macaddr,
7072 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7073 mv_f[i].filter_type = f->mac_info.filter_type;
7074 mv_f[i].vlan_id = 0;
7078 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7079 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7080 vsi->vlan_num, &f->mac_info.mac_addr);
7081 if (ret != I40E_SUCCESS)
7083 for (j = i; j < i + vsi->vlan_num; j++)
7084 mv_f[j].filter_type = f->mac_info.filter_type;
7089 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7097 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7099 struct i40e_macvlan_filter *mv_f;
7101 int ret = I40E_SUCCESS;
7103 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7104 return I40E_ERR_PARAM;
7106 /* If it's already set, just return */
7107 if (i40e_find_vlan_filter(vsi,vlan))
7108 return I40E_SUCCESS;
7110 mac_num = vsi->mac_num;
7113 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7114 return I40E_ERR_PARAM;
7117 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7120 PMD_DRV_LOG(ERR, "failed to allocate memory");
7121 return I40E_ERR_NO_MEMORY;
7124 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7126 if (ret != I40E_SUCCESS)
7129 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7131 if (ret != I40E_SUCCESS)
7134 i40e_set_vlan_filter(vsi, vlan, 1);
7144 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7146 struct i40e_macvlan_filter *mv_f;
7148 int ret = I40E_SUCCESS;
7151 * Vlan 0 is the generic filter for untagged packets
7152 * and can't be removed.
7154 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7155 return I40E_ERR_PARAM;
7157 /* If can't find it, just return */
7158 if (!i40e_find_vlan_filter(vsi, vlan))
7159 return I40E_ERR_PARAM;
7161 mac_num = vsi->mac_num;
7164 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7165 return I40E_ERR_PARAM;
7168 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7171 PMD_DRV_LOG(ERR, "failed to allocate memory");
7172 return I40E_ERR_NO_MEMORY;
7175 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7177 if (ret != I40E_SUCCESS)
7180 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7182 if (ret != I40E_SUCCESS)
7185 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7186 if (vsi->vlan_num == 1) {
7187 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7188 if (ret != I40E_SUCCESS)
7191 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7192 if (ret != I40E_SUCCESS)
7196 i40e_set_vlan_filter(vsi, vlan, 0);
7206 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7208 struct i40e_mac_filter *f;
7209 struct i40e_macvlan_filter *mv_f;
7210 int i, vlan_num = 0;
7211 int ret = I40E_SUCCESS;
7213 /* If it's add and we've config it, return */
7214 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7216 return I40E_SUCCESS;
7217 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7218 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7221 * If vlan_num is 0, that's the first time to add mac,
7222 * set mask for vlan_id 0.
7224 if (vsi->vlan_num == 0) {
7225 i40e_set_vlan_filter(vsi, 0, 1);
7228 vlan_num = vsi->vlan_num;
7229 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7230 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7233 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7235 PMD_DRV_LOG(ERR, "failed to allocate memory");
7236 return I40E_ERR_NO_MEMORY;
7239 for (i = 0; i < vlan_num; i++) {
7240 mv_f[i].filter_type = mac_filter->filter_type;
7241 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7245 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7246 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7247 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7248 &mac_filter->mac_addr);
7249 if (ret != I40E_SUCCESS)
7253 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7254 if (ret != I40E_SUCCESS)
7257 /* Add the mac addr into mac list */
7258 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7260 PMD_DRV_LOG(ERR, "failed to allocate memory");
7261 ret = I40E_ERR_NO_MEMORY;
7264 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7266 f->mac_info.filter_type = mac_filter->filter_type;
7267 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7278 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7280 struct i40e_mac_filter *f;
7281 struct i40e_macvlan_filter *mv_f;
7283 enum rte_mac_filter_type filter_type;
7284 int ret = I40E_SUCCESS;
7286 /* Can't find it, return an error */
7287 f = i40e_find_mac_filter(vsi, addr);
7289 return I40E_ERR_PARAM;
7291 vlan_num = vsi->vlan_num;
7292 filter_type = f->mac_info.filter_type;
7293 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7294 filter_type == RTE_MACVLAN_HASH_MATCH) {
7295 if (vlan_num == 0) {
7296 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7297 return I40E_ERR_PARAM;
7299 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7300 filter_type == RTE_MAC_HASH_MATCH)
7303 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7305 PMD_DRV_LOG(ERR, "failed to allocate memory");
7306 return I40E_ERR_NO_MEMORY;
7309 for (i = 0; i < vlan_num; i++) {
7310 mv_f[i].filter_type = filter_type;
7311 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7314 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7315 filter_type == RTE_MACVLAN_HASH_MATCH) {
7316 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7317 if (ret != I40E_SUCCESS)
7321 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7322 if (ret != I40E_SUCCESS)
7325 /* Remove the mac addr into mac list */
7326 TAILQ_REMOVE(&vsi->mac_list, f, next);
7336 /* Configure hash enable flags for RSS */
7338 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7346 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7347 if (flags & (1ULL << i))
7348 hena |= adapter->pctypes_tbl[i];
7354 /* Parse the hash enable flags */
7356 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7358 uint64_t rss_hf = 0;
7364 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7365 if (flags & adapter->pctypes_tbl[i])
7366 rss_hf |= (1ULL << i);
7373 i40e_pf_disable_rss(struct i40e_pf *pf)
7375 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7377 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7378 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7379 I40E_WRITE_FLUSH(hw);
7383 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7385 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7386 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7387 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7388 I40E_VFQF_HKEY_MAX_INDEX :
7389 I40E_PFQF_HKEY_MAX_INDEX;
7392 if (!key || key_len == 0) {
7393 PMD_DRV_LOG(DEBUG, "No key to be configured");
7395 } else if (key_len != (key_idx + 1) *
7397 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7401 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7402 struct i40e_aqc_get_set_rss_key_data *key_dw =
7403 (struct i40e_aqc_get_set_rss_key_data *)key;
7405 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7407 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7409 uint32_t *hash_key = (uint32_t *)key;
7412 if (vsi->type == I40E_VSI_SRIOV) {
7413 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7416 I40E_VFQF_HKEY1(i, vsi->user_param),
7420 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7421 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7424 I40E_WRITE_FLUSH(hw);
7431 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7433 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7434 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7438 if (!key || !key_len)
7441 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7442 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7443 (struct i40e_aqc_get_set_rss_key_data *)key);
7445 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7449 uint32_t *key_dw = (uint32_t *)key;
7452 if (vsi->type == I40E_VSI_SRIOV) {
7453 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7454 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7455 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7457 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7460 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7461 reg = I40E_PFQF_HKEY(i);
7462 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7464 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7472 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7474 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7478 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7479 rss_conf->rss_key_len);
7483 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7484 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7485 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7486 I40E_WRITE_FLUSH(hw);
7492 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7493 struct rte_eth_rss_conf *rss_conf)
7495 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7496 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7497 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7500 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7501 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7503 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7504 if (rss_hf != 0) /* Enable RSS */
7506 return 0; /* Nothing to do */
7509 if (rss_hf == 0) /* Disable RSS */
7512 return i40e_hw_rss_hash_set(pf, rss_conf);
7516 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7517 struct rte_eth_rss_conf *rss_conf)
7519 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7520 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7527 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7528 &rss_conf->rss_key_len);
7532 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7533 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7534 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7540 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7542 switch (filter_type) {
7543 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7544 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7546 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7547 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7549 case RTE_TUNNEL_FILTER_IMAC_TENID:
7550 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7552 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7553 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7555 case ETH_TUNNEL_FILTER_IMAC:
7556 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7558 case ETH_TUNNEL_FILTER_OIP:
7559 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7561 case ETH_TUNNEL_FILTER_IIP:
7562 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7565 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7572 /* Convert tunnel filter structure */
7574 i40e_tunnel_filter_convert(
7575 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7576 struct i40e_tunnel_filter *tunnel_filter)
7578 rte_ether_addr_copy((struct rte_ether_addr *)
7579 &cld_filter->element.outer_mac,
7580 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7581 rte_ether_addr_copy((struct rte_ether_addr *)
7582 &cld_filter->element.inner_mac,
7583 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7584 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7585 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7586 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7587 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7588 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7590 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7591 tunnel_filter->input.flags = cld_filter->element.flags;
7592 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7593 tunnel_filter->queue = cld_filter->element.queue_number;
7594 rte_memcpy(tunnel_filter->input.general_fields,
7595 cld_filter->general_fields,
7596 sizeof(cld_filter->general_fields));
7601 /* Check if there exists the tunnel filter */
7602 struct i40e_tunnel_filter *
7603 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7604 const struct i40e_tunnel_filter_input *input)
7608 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7612 return tunnel_rule->hash_map[ret];
7615 /* Add a tunnel filter into the SW list */
7617 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7618 struct i40e_tunnel_filter *tunnel_filter)
7620 struct i40e_tunnel_rule *rule = &pf->tunnel;
7623 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7626 "Failed to insert tunnel filter to hash table %d!",
7630 rule->hash_map[ret] = tunnel_filter;
7632 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7637 /* Delete a tunnel filter from the SW list */
7639 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7640 struct i40e_tunnel_filter_input *input)
7642 struct i40e_tunnel_rule *rule = &pf->tunnel;
7643 struct i40e_tunnel_filter *tunnel_filter;
7646 ret = rte_hash_del_key(rule->hash_table, input);
7649 "Failed to delete tunnel filter to hash table %d!",
7653 tunnel_filter = rule->hash_map[ret];
7654 rule->hash_map[ret] = NULL;
7656 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7657 rte_free(tunnel_filter);
7663 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7664 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7668 uint32_t ipv4_addr, ipv4_addr_le;
7669 uint8_t i, tun_type = 0;
7670 /* internal varialbe to convert ipv6 byte order */
7671 uint32_t convert_ipv6[4];
7673 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7674 struct i40e_vsi *vsi = pf->main_vsi;
7675 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7676 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7677 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7678 struct i40e_tunnel_filter *tunnel, *node;
7679 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7681 cld_filter = rte_zmalloc("tunnel_filter",
7682 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7685 if (NULL == cld_filter) {
7686 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7689 pfilter = cld_filter;
7691 rte_ether_addr_copy(&tunnel_filter->outer_mac,
7692 (struct rte_ether_addr *)&pfilter->element.outer_mac);
7693 rte_ether_addr_copy(&tunnel_filter->inner_mac,
7694 (struct rte_ether_addr *)&pfilter->element.inner_mac);
7696 pfilter->element.inner_vlan =
7697 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7698 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7699 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7700 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7701 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7702 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7704 sizeof(pfilter->element.ipaddr.v4.data));
7706 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7707 for (i = 0; i < 4; i++) {
7709 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7711 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7713 sizeof(pfilter->element.ipaddr.v6.data));
7716 /* check tunneled type */
7717 switch (tunnel_filter->tunnel_type) {
7718 case RTE_TUNNEL_TYPE_VXLAN:
7719 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7721 case RTE_TUNNEL_TYPE_NVGRE:
7722 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7724 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7725 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7727 case RTE_TUNNEL_TYPE_VXLAN_GPE:
7728 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7731 /* Other tunnel types is not supported. */
7732 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7733 rte_free(cld_filter);
7737 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7738 &pfilter->element.flags);
7740 rte_free(cld_filter);
7744 pfilter->element.flags |= rte_cpu_to_le_16(
7745 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7746 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7747 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7748 pfilter->element.queue_number =
7749 rte_cpu_to_le_16(tunnel_filter->queue_id);
7751 /* Check if there is the filter in SW list */
7752 memset(&check_filter, 0, sizeof(check_filter));
7753 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7754 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7756 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7757 rte_free(cld_filter);
7761 if (!add && !node) {
7762 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7763 rte_free(cld_filter);
7768 ret = i40e_aq_add_cloud_filters(hw,
7769 vsi->seid, &cld_filter->element, 1);
7771 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7772 rte_free(cld_filter);
7775 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7776 if (tunnel == NULL) {
7777 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7778 rte_free(cld_filter);
7782 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7783 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7787 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7788 &cld_filter->element, 1);
7790 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7791 rte_free(cld_filter);
7794 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7797 rte_free(cld_filter);
7801 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7802 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7803 #define I40E_TR_GENEVE_KEY_MASK 0x8
7804 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7805 #define I40E_TR_GRE_KEY_MASK 0x400
7806 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7807 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7810 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7812 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7813 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7814 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7815 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7816 enum i40e_status_code status = I40E_SUCCESS;
7818 if (pf->support_multi_driver) {
7819 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7820 return I40E_NOT_SUPPORTED;
7823 memset(&filter_replace, 0,
7824 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7825 memset(&filter_replace_buf, 0,
7826 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7828 /* create L1 filter */
7829 filter_replace.old_filter_type =
7830 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7831 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7832 filter_replace.tr_bit = 0;
7834 /* Prepare the buffer, 3 entries */
7835 filter_replace_buf.data[0] =
7836 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7837 filter_replace_buf.data[0] |=
7838 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7839 filter_replace_buf.data[2] = 0xFF;
7840 filter_replace_buf.data[3] = 0xFF;
7841 filter_replace_buf.data[4] =
7842 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7843 filter_replace_buf.data[4] |=
7844 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7845 filter_replace_buf.data[7] = 0xF0;
7846 filter_replace_buf.data[8]
7847 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7848 filter_replace_buf.data[8] |=
7849 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7850 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7851 I40E_TR_GENEVE_KEY_MASK |
7852 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7853 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7854 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7855 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7857 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7858 &filter_replace_buf);
7859 if (!status && (filter_replace.old_filter_type !=
7860 filter_replace.new_filter_type))
7861 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7862 " original: 0x%x, new: 0x%x",
7864 filter_replace.old_filter_type,
7865 filter_replace.new_filter_type);
7871 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7873 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7874 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7875 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7876 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7877 enum i40e_status_code status = I40E_SUCCESS;
7879 if (pf->support_multi_driver) {
7880 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7881 return I40E_NOT_SUPPORTED;
7885 memset(&filter_replace, 0,
7886 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7887 memset(&filter_replace_buf, 0,
7888 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7889 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7890 I40E_AQC_MIRROR_CLOUD_FILTER;
7891 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7892 filter_replace.new_filter_type =
7893 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7894 /* Prepare the buffer, 2 entries */
7895 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7896 filter_replace_buf.data[0] |=
7897 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7898 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7899 filter_replace_buf.data[4] |=
7900 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7901 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7902 &filter_replace_buf);
7905 if (filter_replace.old_filter_type !=
7906 filter_replace.new_filter_type)
7907 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7908 " original: 0x%x, new: 0x%x",
7910 filter_replace.old_filter_type,
7911 filter_replace.new_filter_type);
7914 memset(&filter_replace, 0,
7915 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7916 memset(&filter_replace_buf, 0,
7917 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7919 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7920 I40E_AQC_MIRROR_CLOUD_FILTER;
7921 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7922 filter_replace.new_filter_type =
7923 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7924 /* Prepare the buffer, 2 entries */
7925 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7926 filter_replace_buf.data[0] |=
7927 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7928 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7929 filter_replace_buf.data[4] |=
7930 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7932 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7933 &filter_replace_buf);
7934 if (!status && (filter_replace.old_filter_type !=
7935 filter_replace.new_filter_type))
7936 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7937 " original: 0x%x, new: 0x%x",
7939 filter_replace.old_filter_type,
7940 filter_replace.new_filter_type);
7945 static enum i40e_status_code
7946 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7948 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7949 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7950 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7951 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7952 enum i40e_status_code status = I40E_SUCCESS;
7954 if (pf->support_multi_driver) {
7955 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7956 return I40E_NOT_SUPPORTED;
7960 memset(&filter_replace, 0,
7961 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7962 memset(&filter_replace_buf, 0,
7963 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7964 /* create L1 filter */
7965 filter_replace.old_filter_type =
7966 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7967 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7968 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7969 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7970 /* Prepare the buffer, 2 entries */
7971 filter_replace_buf.data[0] =
7972 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7973 filter_replace_buf.data[0] |=
7974 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7975 filter_replace_buf.data[2] = 0xFF;
7976 filter_replace_buf.data[3] = 0xFF;
7977 filter_replace_buf.data[4] =
7978 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7979 filter_replace_buf.data[4] |=
7980 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7981 filter_replace_buf.data[6] = 0xFF;
7982 filter_replace_buf.data[7] = 0xFF;
7983 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7984 &filter_replace_buf);
7987 if (filter_replace.old_filter_type !=
7988 filter_replace.new_filter_type)
7989 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7990 " original: 0x%x, new: 0x%x",
7992 filter_replace.old_filter_type,
7993 filter_replace.new_filter_type);
7996 memset(&filter_replace, 0,
7997 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7998 memset(&filter_replace_buf, 0,
7999 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8000 /* create L1 filter */
8001 filter_replace.old_filter_type =
8002 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8003 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8004 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8005 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8006 /* Prepare the buffer, 2 entries */
8007 filter_replace_buf.data[0] =
8008 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8009 filter_replace_buf.data[0] |=
8010 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8011 filter_replace_buf.data[2] = 0xFF;
8012 filter_replace_buf.data[3] = 0xFF;
8013 filter_replace_buf.data[4] =
8014 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8015 filter_replace_buf.data[4] |=
8016 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8017 filter_replace_buf.data[6] = 0xFF;
8018 filter_replace_buf.data[7] = 0xFF;
8020 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8021 &filter_replace_buf);
8022 if (!status && (filter_replace.old_filter_type !=
8023 filter_replace.new_filter_type))
8024 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8025 " original: 0x%x, new: 0x%x",
8027 filter_replace.old_filter_type,
8028 filter_replace.new_filter_type);
8034 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8036 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8037 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8038 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8039 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8040 enum i40e_status_code status = I40E_SUCCESS;
8042 if (pf->support_multi_driver) {
8043 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8044 return I40E_NOT_SUPPORTED;
8048 memset(&filter_replace, 0,
8049 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8050 memset(&filter_replace_buf, 0,
8051 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8052 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8053 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8054 filter_replace.new_filter_type =
8055 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8056 /* Prepare the buffer, 2 entries */
8057 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8058 filter_replace_buf.data[0] |=
8059 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8060 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8061 filter_replace_buf.data[4] |=
8062 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8063 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8064 &filter_replace_buf);
8067 if (filter_replace.old_filter_type !=
8068 filter_replace.new_filter_type)
8069 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8070 " original: 0x%x, new: 0x%x",
8072 filter_replace.old_filter_type,
8073 filter_replace.new_filter_type);
8076 memset(&filter_replace, 0,
8077 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8078 memset(&filter_replace_buf, 0,
8079 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8080 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8081 filter_replace.old_filter_type =
8082 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8083 filter_replace.new_filter_type =
8084 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8085 /* Prepare the buffer, 2 entries */
8086 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8087 filter_replace_buf.data[0] |=
8088 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8089 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8090 filter_replace_buf.data[4] |=
8091 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8093 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8094 &filter_replace_buf);
8095 if (!status && (filter_replace.old_filter_type !=
8096 filter_replace.new_filter_type))
8097 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8098 " original: 0x%x, new: 0x%x",
8100 filter_replace.old_filter_type,
8101 filter_replace.new_filter_type);
8107 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8108 struct i40e_tunnel_filter_conf *tunnel_filter,
8112 uint32_t ipv4_addr, ipv4_addr_le;
8113 uint8_t i, tun_type = 0;
8114 /* internal variable to convert ipv6 byte order */
8115 uint32_t convert_ipv6[4];
8117 struct i40e_pf_vf *vf = NULL;
8118 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8119 struct i40e_vsi *vsi;
8120 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8121 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8122 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8123 struct i40e_tunnel_filter *tunnel, *node;
8124 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8126 bool big_buffer = 0;
8128 cld_filter = rte_zmalloc("tunnel_filter",
8129 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8132 if (cld_filter == NULL) {
8133 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8136 pfilter = cld_filter;
8138 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8139 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8140 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8141 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8143 pfilter->element.inner_vlan =
8144 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8145 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8146 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8147 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8148 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8149 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8151 sizeof(pfilter->element.ipaddr.v4.data));
8153 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8154 for (i = 0; i < 4; i++) {
8156 rte_cpu_to_le_32(rte_be_to_cpu_32(
8157 tunnel_filter->ip_addr.ipv6_addr[i]));
8159 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8161 sizeof(pfilter->element.ipaddr.v6.data));
8164 /* check tunneled type */
8165 switch (tunnel_filter->tunnel_type) {
8166 case I40E_TUNNEL_TYPE_VXLAN:
8167 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8169 case I40E_TUNNEL_TYPE_NVGRE:
8170 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8172 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8173 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8175 case I40E_TUNNEL_TYPE_MPLSoUDP:
8176 if (!pf->mpls_replace_flag) {
8177 i40e_replace_mpls_l1_filter(pf);
8178 i40e_replace_mpls_cloud_filter(pf);
8179 pf->mpls_replace_flag = 1;
8181 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8182 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8184 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8185 (teid_le & 0xF) << 12;
8186 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8189 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8191 case I40E_TUNNEL_TYPE_MPLSoGRE:
8192 if (!pf->mpls_replace_flag) {
8193 i40e_replace_mpls_l1_filter(pf);
8194 i40e_replace_mpls_cloud_filter(pf);
8195 pf->mpls_replace_flag = 1;
8197 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8198 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8200 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8201 (teid_le & 0xF) << 12;
8202 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8205 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8207 case I40E_TUNNEL_TYPE_GTPC:
8208 if (!pf->gtp_replace_flag) {
8209 i40e_replace_gtp_l1_filter(pf);
8210 i40e_replace_gtp_cloud_filter(pf);
8211 pf->gtp_replace_flag = 1;
8213 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8214 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8215 (teid_le >> 16) & 0xFFFF;
8216 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8218 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8222 case I40E_TUNNEL_TYPE_GTPU:
8223 if (!pf->gtp_replace_flag) {
8224 i40e_replace_gtp_l1_filter(pf);
8225 i40e_replace_gtp_cloud_filter(pf);
8226 pf->gtp_replace_flag = 1;
8228 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8229 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8230 (teid_le >> 16) & 0xFFFF;
8231 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8233 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8237 case I40E_TUNNEL_TYPE_QINQ:
8238 if (!pf->qinq_replace_flag) {
8239 ret = i40e_cloud_filter_qinq_create(pf);
8242 "QinQ tunnel filter already created.");
8243 pf->qinq_replace_flag = 1;
8245 /* Add in the General fields the values of
8246 * the Outer and Inner VLAN
8247 * Big Buffer should be set, see changes in
8248 * i40e_aq_add_cloud_filters
8250 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8251 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8255 /* Other tunnel types is not supported. */
8256 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8257 rte_free(cld_filter);
8261 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8262 pfilter->element.flags =
8263 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8264 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8265 pfilter->element.flags =
8266 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8267 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8268 pfilter->element.flags =
8269 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8270 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8271 pfilter->element.flags =
8272 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8273 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8274 pfilter->element.flags |=
8275 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8277 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8278 &pfilter->element.flags);
8280 rte_free(cld_filter);
8285 pfilter->element.flags |= rte_cpu_to_le_16(
8286 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8287 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8288 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8289 pfilter->element.queue_number =
8290 rte_cpu_to_le_16(tunnel_filter->queue_id);
8292 if (!tunnel_filter->is_to_vf)
8295 if (tunnel_filter->vf_id >= pf->vf_num) {
8296 PMD_DRV_LOG(ERR, "Invalid argument.");
8297 rte_free(cld_filter);
8300 vf = &pf->vfs[tunnel_filter->vf_id];
8304 /* Check if there is the filter in SW list */
8305 memset(&check_filter, 0, sizeof(check_filter));
8306 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8307 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8308 check_filter.vf_id = tunnel_filter->vf_id;
8309 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8311 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8312 rte_free(cld_filter);
8316 if (!add && !node) {
8317 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8318 rte_free(cld_filter);
8324 ret = i40e_aq_add_cloud_filters_bb(hw,
8325 vsi->seid, cld_filter, 1);
8327 ret = i40e_aq_add_cloud_filters(hw,
8328 vsi->seid, &cld_filter->element, 1);
8330 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8331 rte_free(cld_filter);
8334 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8335 if (tunnel == NULL) {
8336 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8337 rte_free(cld_filter);
8341 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8342 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8347 ret = i40e_aq_rem_cloud_filters_bb(
8348 hw, vsi->seid, cld_filter, 1);
8350 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8351 &cld_filter->element, 1);
8353 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8354 rte_free(cld_filter);
8357 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8360 rte_free(cld_filter);
8365 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8369 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8370 if (pf->vxlan_ports[i] == port)
8378 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8382 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8384 idx = i40e_get_vxlan_port_idx(pf, port);
8386 /* Check if port already exists */
8388 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8392 /* Now check if there is space to add the new port */
8393 idx = i40e_get_vxlan_port_idx(pf, 0);
8396 "Maximum number of UDP ports reached, not adding port %d",
8401 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8404 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8408 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8411 /* New port: add it and mark its index in the bitmap */
8412 pf->vxlan_ports[idx] = port;
8413 pf->vxlan_bitmap |= (1 << idx);
8415 if (!(pf->flags & I40E_FLAG_VXLAN))
8416 pf->flags |= I40E_FLAG_VXLAN;
8422 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8425 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8427 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8428 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8432 idx = i40e_get_vxlan_port_idx(pf, port);
8435 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8439 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8440 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8444 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8447 pf->vxlan_ports[idx] = 0;
8448 pf->vxlan_bitmap &= ~(1 << idx);
8450 if (!pf->vxlan_bitmap)
8451 pf->flags &= ~I40E_FLAG_VXLAN;
8456 /* Add UDP tunneling port */
8458 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8459 struct rte_eth_udp_tunnel *udp_tunnel)
8462 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8464 if (udp_tunnel == NULL)
8467 switch (udp_tunnel->prot_type) {
8468 case RTE_TUNNEL_TYPE_VXLAN:
8469 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8470 I40E_AQC_TUNNEL_TYPE_VXLAN);
8472 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8473 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8474 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8476 case RTE_TUNNEL_TYPE_GENEVE:
8477 case RTE_TUNNEL_TYPE_TEREDO:
8478 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8483 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8491 /* Remove UDP tunneling port */
8493 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8494 struct rte_eth_udp_tunnel *udp_tunnel)
8497 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8499 if (udp_tunnel == NULL)
8502 switch (udp_tunnel->prot_type) {
8503 case RTE_TUNNEL_TYPE_VXLAN:
8504 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8505 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8507 case RTE_TUNNEL_TYPE_GENEVE:
8508 case RTE_TUNNEL_TYPE_TEREDO:
8509 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8513 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8521 /* Calculate the maximum number of contiguous PF queues that are configured */
8523 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8525 struct rte_eth_dev_data *data = pf->dev_data;
8527 struct i40e_rx_queue *rxq;
8530 for (i = 0; i < pf->lan_nb_qps; i++) {
8531 rxq = data->rx_queues[i];
8532 if (rxq && rxq->q_set)
8543 i40e_pf_config_rss(struct i40e_pf *pf)
8545 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8546 struct rte_eth_rss_conf rss_conf;
8547 uint32_t i, lut = 0;
8551 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8552 * It's necessary to calculate the actual PF queues that are configured.
8554 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8555 num = i40e_pf_calc_configured_queues_num(pf);
8557 num = pf->dev_data->nb_rx_queues;
8559 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8560 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8564 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8568 if (pf->adapter->rss_reta_updated == 0) {
8569 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8572 lut = (lut << 8) | (j & ((0x1 <<
8573 hw->func_caps.rss_table_entry_width) - 1));
8575 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8580 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8581 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8582 i40e_pf_disable_rss(pf);
8585 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8586 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8587 /* Random default keys */
8588 static uint32_t rss_key_default[] = {0x6b793944,
8589 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8590 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8591 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8593 rss_conf.rss_key = (uint8_t *)rss_key_default;
8594 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8598 return i40e_hw_rss_hash_set(pf, &rss_conf);
8602 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8603 struct rte_eth_tunnel_filter_conf *filter)
8605 if (pf == NULL || filter == NULL) {
8606 PMD_DRV_LOG(ERR, "Invalid parameter");
8610 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8611 PMD_DRV_LOG(ERR, "Invalid queue ID");
8615 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8616 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8620 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8621 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8622 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8626 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8627 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8628 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8635 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8636 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8638 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8640 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8644 if (pf->support_multi_driver) {
8645 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8649 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8650 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8653 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8654 } else if (len == 4) {
8655 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8657 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8662 ret = i40e_aq_debug_write_global_register(hw,
8663 I40E_GL_PRS_FVBM(2),
8667 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8668 "with value 0x%08x",
8669 I40E_GL_PRS_FVBM(2), reg);
8673 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8674 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8680 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8687 switch (cfg->cfg_type) {
8688 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8689 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8692 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8700 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8701 enum rte_filter_op filter_op,
8704 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8705 int ret = I40E_ERR_PARAM;
8707 switch (filter_op) {
8708 case RTE_ETH_FILTER_SET:
8709 ret = i40e_dev_global_config_set(hw,
8710 (struct rte_eth_global_cfg *)arg);
8713 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8721 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8722 enum rte_filter_op filter_op,
8725 struct rte_eth_tunnel_filter_conf *filter;
8726 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8727 int ret = I40E_SUCCESS;
8729 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8731 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8732 return I40E_ERR_PARAM;
8734 switch (filter_op) {
8735 case RTE_ETH_FILTER_NOP:
8736 if (!(pf->flags & I40E_FLAG_VXLAN))
8737 ret = I40E_NOT_SUPPORTED;
8739 case RTE_ETH_FILTER_ADD:
8740 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8742 case RTE_ETH_FILTER_DELETE:
8743 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8746 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8747 ret = I40E_ERR_PARAM;
8755 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8758 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8761 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8762 ret = i40e_pf_config_rss(pf);
8764 i40e_pf_disable_rss(pf);
8769 /* Get the symmetric hash enable configurations per port */
8771 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8773 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8775 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8778 /* Set the symmetric hash enable configurations per port */
8780 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8782 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8785 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8787 "Symmetric hash has already been enabled");
8790 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8792 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8794 "Symmetric hash has already been disabled");
8797 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8799 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8800 I40E_WRITE_FLUSH(hw);
8804 * Get global configurations of hash function type and symmetric hash enable
8805 * per flow type (pctype). Note that global configuration means it affects all
8806 * the ports on the same NIC.
8809 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8810 struct rte_eth_hash_global_conf *g_cfg)
8812 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8816 memset(g_cfg, 0, sizeof(*g_cfg));
8817 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8818 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8819 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8821 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8822 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8823 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8826 * As i40e supports less than 64 flow types, only first 64 bits need to
8829 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8830 g_cfg->valid_bit_mask[i] = 0ULL;
8831 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8834 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8836 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8837 if (!adapter->pctypes_tbl[i])
8839 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8840 j < I40E_FILTER_PCTYPE_MAX; j++) {
8841 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8842 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8843 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8844 g_cfg->sym_hash_enable_mask[0] |=
8855 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8856 const struct rte_eth_hash_global_conf *g_cfg)
8859 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8861 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8862 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8863 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8864 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8870 * As i40e supports less than 64 flow types, only first 64 bits need to
8873 mask0 = g_cfg->valid_bit_mask[0];
8874 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8876 /* Check if any unsupported flow type configured */
8877 if ((mask0 | i40e_mask) ^ i40e_mask)
8880 if (g_cfg->valid_bit_mask[i])
8888 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8894 * Set global configurations of hash function type and symmetric hash enable
8895 * per flow type (pctype). Note any modifying global configuration will affect
8896 * all the ports on the same NIC.
8899 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8900 struct rte_eth_hash_global_conf *g_cfg)
8902 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8903 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8907 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8909 if (pf->support_multi_driver) {
8910 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8914 /* Check the input parameters */
8915 ret = i40e_hash_global_config_check(adapter, g_cfg);
8920 * As i40e supports less than 64 flow types, only first 64 bits need to
8923 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8924 if (mask0 & (1UL << i)) {
8925 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8926 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8928 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8929 j < I40E_FILTER_PCTYPE_MAX; j++) {
8930 if (adapter->pctypes_tbl[i] & (1ULL << j))
8931 i40e_write_global_rx_ctl(hw,
8938 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8939 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8941 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8943 "Hash function already set to Toeplitz");
8946 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8947 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8949 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8951 "Hash function already set to Simple XOR");
8954 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8956 /* Use the default, and keep it as it is */
8959 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8962 I40E_WRITE_FLUSH(hw);
8968 * Valid input sets for hash and flow director filters per PCTYPE
8971 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8972 enum rte_filter_type filter)
8976 static const uint64_t valid_hash_inset_table[] = {
8977 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8978 I40E_INSET_DMAC | I40E_INSET_SMAC |
8979 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8980 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8981 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8982 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8983 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8984 I40E_INSET_FLEX_PAYLOAD,
8985 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8986 I40E_INSET_DMAC | I40E_INSET_SMAC |
8987 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8988 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8989 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8990 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8991 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8992 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8993 I40E_INSET_FLEX_PAYLOAD,
8994 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8995 I40E_INSET_DMAC | I40E_INSET_SMAC |
8996 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8997 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8998 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8999 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9000 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9001 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9002 I40E_INSET_FLEX_PAYLOAD,
9003 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9004 I40E_INSET_DMAC | I40E_INSET_SMAC |
9005 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9006 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9007 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9008 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9009 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9010 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9011 I40E_INSET_FLEX_PAYLOAD,
9012 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9013 I40E_INSET_DMAC | I40E_INSET_SMAC |
9014 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9015 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9016 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9017 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9018 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9019 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9020 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9021 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9022 I40E_INSET_DMAC | I40E_INSET_SMAC |
9023 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9024 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9025 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9026 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9027 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9028 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9029 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9030 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9031 I40E_INSET_DMAC | I40E_INSET_SMAC |
9032 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9033 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9034 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9035 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9036 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9037 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9038 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9039 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9040 I40E_INSET_DMAC | I40E_INSET_SMAC |
9041 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9042 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9043 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9044 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9045 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9046 I40E_INSET_FLEX_PAYLOAD,
9047 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9048 I40E_INSET_DMAC | I40E_INSET_SMAC |
9049 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9050 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9051 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9052 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9053 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9054 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9055 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9056 I40E_INSET_DMAC | I40E_INSET_SMAC |
9057 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9058 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9059 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9060 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9061 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9062 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9063 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9064 I40E_INSET_DMAC | I40E_INSET_SMAC |
9065 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9066 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9067 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9068 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9069 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9070 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9071 I40E_INSET_FLEX_PAYLOAD,
9072 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9073 I40E_INSET_DMAC | I40E_INSET_SMAC |
9074 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9075 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9076 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9077 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9078 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9079 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9080 I40E_INSET_FLEX_PAYLOAD,
9081 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9082 I40E_INSET_DMAC | I40E_INSET_SMAC |
9083 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9084 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9085 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9086 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9087 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9088 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9089 I40E_INSET_FLEX_PAYLOAD,
9090 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9091 I40E_INSET_DMAC | I40E_INSET_SMAC |
9092 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9093 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9094 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9095 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9096 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9097 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9098 I40E_INSET_FLEX_PAYLOAD,
9099 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9100 I40E_INSET_DMAC | I40E_INSET_SMAC |
9101 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9102 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9103 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9104 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9105 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9106 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9107 I40E_INSET_FLEX_PAYLOAD,
9108 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9109 I40E_INSET_DMAC | I40E_INSET_SMAC |
9110 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9111 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9112 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9113 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9114 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9115 I40E_INSET_FLEX_PAYLOAD,
9116 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9117 I40E_INSET_DMAC | I40E_INSET_SMAC |
9118 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9119 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9120 I40E_INSET_FLEX_PAYLOAD,
9124 * Flow director supports only fields defined in
9125 * union rte_eth_fdir_flow.
9127 static const uint64_t valid_fdir_inset_table[] = {
9128 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9129 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9130 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9131 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9132 I40E_INSET_IPV4_TTL,
9133 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9134 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9135 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9136 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9137 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9138 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9139 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9140 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9141 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9142 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9143 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9144 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9145 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9146 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9147 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9148 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9149 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9150 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9151 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9152 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9153 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9154 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9155 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9156 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9157 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9158 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9159 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9160 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9161 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9162 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9164 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9165 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9166 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9167 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9168 I40E_INSET_IPV4_TTL,
9169 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9170 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9171 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9172 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9173 I40E_INSET_IPV6_HOP_LIMIT,
9174 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9175 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9176 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9177 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9178 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9179 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9180 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9181 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9182 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9183 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9184 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9185 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9186 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9187 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9188 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9189 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9190 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9191 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9192 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9193 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9194 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9195 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9196 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9197 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9198 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9199 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9200 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9201 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9202 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9203 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9205 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9206 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9207 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9208 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9209 I40E_INSET_IPV6_HOP_LIMIT,
9210 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9211 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9212 I40E_INSET_LAST_ETHER_TYPE,
9215 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9217 if (filter == RTE_ETH_FILTER_HASH)
9218 valid = valid_hash_inset_table[pctype];
9220 valid = valid_fdir_inset_table[pctype];
9226 * Validate if the input set is allowed for a specific PCTYPE
9229 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9230 enum rte_filter_type filter, uint64_t inset)
9234 valid = i40e_get_valid_input_set(pctype, filter);
9235 if (inset & (~valid))
9241 /* default input set fields combination per pctype */
9243 i40e_get_default_input_set(uint16_t pctype)
9245 static const uint64_t default_inset_table[] = {
9246 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9247 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9248 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9249 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9250 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9251 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9252 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9253 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9254 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9255 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9256 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9257 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9258 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9259 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9260 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9261 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9262 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9263 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9264 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9265 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9267 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9268 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9269 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9270 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9271 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9272 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9273 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9274 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9275 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9276 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9277 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9278 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9279 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9280 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9281 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9282 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9283 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9284 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9285 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9286 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9287 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9288 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9290 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9291 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9292 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9293 I40E_INSET_LAST_ETHER_TYPE,
9296 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9299 return default_inset_table[pctype];
9303 * Parse the input set from index to logical bit masks
9306 i40e_parse_input_set(uint64_t *inset,
9307 enum i40e_filter_pctype pctype,
9308 enum rte_eth_input_set_field *field,
9314 static const struct {
9315 enum rte_eth_input_set_field field;
9317 } inset_convert_table[] = {
9318 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9319 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9320 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9321 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9322 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9323 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9324 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9325 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9326 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9327 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9328 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9329 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9330 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9331 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9332 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9333 I40E_INSET_IPV6_NEXT_HDR},
9334 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9335 I40E_INSET_IPV6_HOP_LIMIT},
9336 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9337 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9338 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9339 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9340 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9341 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9342 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9343 I40E_INSET_SCTP_VT},
9344 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9345 I40E_INSET_TUNNEL_DMAC},
9346 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9347 I40E_INSET_VLAN_TUNNEL},
9348 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9349 I40E_INSET_TUNNEL_ID},
9350 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9351 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9352 I40E_INSET_FLEX_PAYLOAD_W1},
9353 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9354 I40E_INSET_FLEX_PAYLOAD_W2},
9355 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9356 I40E_INSET_FLEX_PAYLOAD_W3},
9357 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9358 I40E_INSET_FLEX_PAYLOAD_W4},
9359 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9360 I40E_INSET_FLEX_PAYLOAD_W5},
9361 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9362 I40E_INSET_FLEX_PAYLOAD_W6},
9363 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9364 I40E_INSET_FLEX_PAYLOAD_W7},
9365 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9366 I40E_INSET_FLEX_PAYLOAD_W8},
9369 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9372 /* Only one item allowed for default or all */
9374 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9375 *inset = i40e_get_default_input_set(pctype);
9377 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9378 *inset = I40E_INSET_NONE;
9383 for (i = 0, *inset = 0; i < size; i++) {
9384 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9385 if (field[i] == inset_convert_table[j].field) {
9386 *inset |= inset_convert_table[j].inset;
9391 /* It contains unsupported input set, return immediately */
9392 if (j == RTE_DIM(inset_convert_table))
9400 * Translate the input set from bit masks to register aware bit masks
9404 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9414 static const struct inset_map inset_map_common[] = {
9415 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9416 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9417 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9418 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9419 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9420 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9421 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9422 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9423 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9424 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9425 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9426 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9427 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9428 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9429 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9430 {I40E_INSET_TUNNEL_DMAC,
9431 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9432 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9433 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9434 {I40E_INSET_TUNNEL_SRC_PORT,
9435 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9436 {I40E_INSET_TUNNEL_DST_PORT,
9437 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9438 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9439 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9440 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9441 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9442 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9443 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9444 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9445 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9446 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9449 /* some different registers map in x722*/
9450 static const struct inset_map inset_map_diff_x722[] = {
9451 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9452 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9453 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9454 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9457 static const struct inset_map inset_map_diff_not_x722[] = {
9458 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9459 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9460 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9461 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9467 /* Translate input set to register aware inset */
9468 if (type == I40E_MAC_X722) {
9469 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9470 if (input & inset_map_diff_x722[i].inset)
9471 val |= inset_map_diff_x722[i].inset_reg;
9474 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9475 if (input & inset_map_diff_not_x722[i].inset)
9476 val |= inset_map_diff_not_x722[i].inset_reg;
9480 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9481 if (input & inset_map_common[i].inset)
9482 val |= inset_map_common[i].inset_reg;
9489 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9492 uint64_t inset_need_mask = inset;
9494 static const struct {
9497 } inset_mask_map[] = {
9498 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9499 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9500 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9501 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9502 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9503 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9504 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9505 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9508 if (!inset || !mask || !nb_elem)
9511 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9512 /* Clear the inset bit, if no MASK is required,
9513 * for example proto + ttl
9515 if ((inset & inset_mask_map[i].inset) ==
9516 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9517 inset_need_mask &= ~inset_mask_map[i].inset;
9518 if (!inset_need_mask)
9521 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9522 if ((inset_need_mask & inset_mask_map[i].inset) ==
9523 inset_mask_map[i].inset) {
9524 if (idx >= nb_elem) {
9525 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9528 mask[idx] = inset_mask_map[i].mask;
9537 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9539 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9541 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9543 i40e_write_rx_ctl(hw, addr, val);
9544 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9545 (uint32_t)i40e_read_rx_ctl(hw, addr));
9549 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9551 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9552 struct rte_eth_dev *dev;
9554 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9556 i40e_write_rx_ctl(hw, addr, val);
9557 PMD_DRV_LOG(WARNING,
9558 "i40e device %s changed global register [0x%08x]."
9559 " original: 0x%08x, new: 0x%08x",
9560 dev->device->name, addr, reg,
9561 (uint32_t)i40e_read_rx_ctl(hw, addr));
9566 i40e_filter_input_set_init(struct i40e_pf *pf)
9568 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9569 enum i40e_filter_pctype pctype;
9570 uint64_t input_set, inset_reg;
9571 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9575 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9576 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9577 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9579 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9582 input_set = i40e_get_default_input_set(pctype);
9584 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9585 I40E_INSET_MASK_NUM_REG);
9588 if (pf->support_multi_driver && num > 0) {
9589 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9592 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9595 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9596 (uint32_t)(inset_reg & UINT32_MAX));
9597 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9598 (uint32_t)((inset_reg >>
9599 I40E_32_BIT_WIDTH) & UINT32_MAX));
9600 if (!pf->support_multi_driver) {
9601 i40e_check_write_global_reg(hw,
9602 I40E_GLQF_HASH_INSET(0, pctype),
9603 (uint32_t)(inset_reg & UINT32_MAX));
9604 i40e_check_write_global_reg(hw,
9605 I40E_GLQF_HASH_INSET(1, pctype),
9606 (uint32_t)((inset_reg >>
9607 I40E_32_BIT_WIDTH) & UINT32_MAX));
9609 for (i = 0; i < num; i++) {
9610 i40e_check_write_global_reg(hw,
9611 I40E_GLQF_FD_MSK(i, pctype),
9613 i40e_check_write_global_reg(hw,
9614 I40E_GLQF_HASH_MSK(i, pctype),
9617 /*clear unused mask registers of the pctype */
9618 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9619 i40e_check_write_global_reg(hw,
9620 I40E_GLQF_FD_MSK(i, pctype),
9622 i40e_check_write_global_reg(hw,
9623 I40E_GLQF_HASH_MSK(i, pctype),
9627 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9629 I40E_WRITE_FLUSH(hw);
9631 /* store the default input set */
9632 if (!pf->support_multi_driver)
9633 pf->hash_input_set[pctype] = input_set;
9634 pf->fdir.input_set[pctype] = input_set;
9639 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9640 struct rte_eth_input_set_conf *conf)
9642 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9643 enum i40e_filter_pctype pctype;
9644 uint64_t input_set, inset_reg = 0;
9645 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9649 PMD_DRV_LOG(ERR, "Invalid pointer");
9652 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9653 conf->op != RTE_ETH_INPUT_SET_ADD) {
9654 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9658 if (pf->support_multi_driver) {
9659 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9663 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9664 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9665 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9669 if (hw->mac.type == I40E_MAC_X722) {
9670 /* get translated pctype value in fd pctype register */
9671 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9672 I40E_GLQF_FD_PCTYPES((int)pctype));
9675 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9678 PMD_DRV_LOG(ERR, "Failed to parse input set");
9682 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9683 /* get inset value in register */
9684 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9685 inset_reg <<= I40E_32_BIT_WIDTH;
9686 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9687 input_set |= pf->hash_input_set[pctype];
9689 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9690 I40E_INSET_MASK_NUM_REG);
9694 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9696 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9697 (uint32_t)(inset_reg & UINT32_MAX));
9698 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9699 (uint32_t)((inset_reg >>
9700 I40E_32_BIT_WIDTH) & UINT32_MAX));
9702 for (i = 0; i < num; i++)
9703 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9705 /*clear unused mask registers of the pctype */
9706 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9707 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9709 I40E_WRITE_FLUSH(hw);
9711 pf->hash_input_set[pctype] = input_set;
9716 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9717 struct rte_eth_input_set_conf *conf)
9719 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9720 enum i40e_filter_pctype pctype;
9721 uint64_t input_set, inset_reg = 0;
9722 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9726 PMD_DRV_LOG(ERR, "Invalid pointer");
9729 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9730 conf->op != RTE_ETH_INPUT_SET_ADD) {
9731 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9735 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9737 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9738 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9742 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9745 PMD_DRV_LOG(ERR, "Failed to parse input set");
9749 /* get inset value in register */
9750 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9751 inset_reg <<= I40E_32_BIT_WIDTH;
9752 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9754 /* Can not change the inset reg for flex payload for fdir,
9755 * it is done by writing I40E_PRTQF_FD_FLXINSET
9756 * in i40e_set_flex_mask_on_pctype.
9758 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9759 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9761 input_set |= pf->fdir.input_set[pctype];
9762 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9763 I40E_INSET_MASK_NUM_REG);
9766 if (pf->support_multi_driver && num > 0) {
9767 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9771 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9773 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9774 (uint32_t)(inset_reg & UINT32_MAX));
9775 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9776 (uint32_t)((inset_reg >>
9777 I40E_32_BIT_WIDTH) & UINT32_MAX));
9779 if (!pf->support_multi_driver) {
9780 for (i = 0; i < num; i++)
9781 i40e_check_write_global_reg(hw,
9782 I40E_GLQF_FD_MSK(i, pctype),
9784 /*clear unused mask registers of the pctype */
9785 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9786 i40e_check_write_global_reg(hw,
9787 I40E_GLQF_FD_MSK(i, pctype),
9790 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9792 I40E_WRITE_FLUSH(hw);
9794 pf->fdir.input_set[pctype] = input_set;
9799 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9804 PMD_DRV_LOG(ERR, "Invalid pointer");
9808 switch (info->info_type) {
9809 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9810 i40e_get_symmetric_hash_enable_per_port(hw,
9811 &(info->info.enable));
9813 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9814 ret = i40e_get_hash_filter_global_config(hw,
9815 &(info->info.global_conf));
9818 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9828 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9833 PMD_DRV_LOG(ERR, "Invalid pointer");
9837 switch (info->info_type) {
9838 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9839 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9841 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9842 ret = i40e_set_hash_filter_global_config(hw,
9843 &(info->info.global_conf));
9845 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9846 ret = i40e_hash_filter_inset_select(hw,
9847 &(info->info.input_set_conf));
9851 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9860 /* Operations for hash function */
9862 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9863 enum rte_filter_op filter_op,
9866 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9869 switch (filter_op) {
9870 case RTE_ETH_FILTER_NOP:
9872 case RTE_ETH_FILTER_GET:
9873 ret = i40e_hash_filter_get(hw,
9874 (struct rte_eth_hash_filter_info *)arg);
9876 case RTE_ETH_FILTER_SET:
9877 ret = i40e_hash_filter_set(hw,
9878 (struct rte_eth_hash_filter_info *)arg);
9881 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9890 /* Convert ethertype filter structure */
9892 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9893 struct i40e_ethertype_filter *filter)
9895 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9896 RTE_ETHER_ADDR_LEN);
9897 filter->input.ether_type = input->ether_type;
9898 filter->flags = input->flags;
9899 filter->queue = input->queue;
9904 /* Check if there exists the ehtertype filter */
9905 struct i40e_ethertype_filter *
9906 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9907 const struct i40e_ethertype_filter_input *input)
9911 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9915 return ethertype_rule->hash_map[ret];
9918 /* Add ethertype filter in SW list */
9920 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9921 struct i40e_ethertype_filter *filter)
9923 struct i40e_ethertype_rule *rule = &pf->ethertype;
9926 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9929 "Failed to insert ethertype filter"
9930 " to hash table %d!",
9934 rule->hash_map[ret] = filter;
9936 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9941 /* Delete ethertype filter in SW list */
9943 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9944 struct i40e_ethertype_filter_input *input)
9946 struct i40e_ethertype_rule *rule = &pf->ethertype;
9947 struct i40e_ethertype_filter *filter;
9950 ret = rte_hash_del_key(rule->hash_table, input);
9953 "Failed to delete ethertype filter"
9954 " to hash table %d!",
9958 filter = rule->hash_map[ret];
9959 rule->hash_map[ret] = NULL;
9961 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9968 * Configure ethertype filter, which can director packet by filtering
9969 * with mac address and ether_type or only ether_type
9972 i40e_ethertype_filter_set(struct i40e_pf *pf,
9973 struct rte_eth_ethertype_filter *filter,
9976 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9977 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9978 struct i40e_ethertype_filter *ethertype_filter, *node;
9979 struct i40e_ethertype_filter check_filter;
9980 struct i40e_control_filter_stats stats;
9984 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9985 PMD_DRV_LOG(ERR, "Invalid queue ID");
9988 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
9989 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
9991 "unsupported ether_type(0x%04x) in control packet filter.",
9992 filter->ether_type);
9995 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
9996 PMD_DRV_LOG(WARNING,
9997 "filter vlan ether_type in first tag is not supported.");
9999 /* Check if there is the filter in SW list */
10000 memset(&check_filter, 0, sizeof(check_filter));
10001 i40e_ethertype_filter_convert(filter, &check_filter);
10002 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10003 &check_filter.input);
10005 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10009 if (!add && !node) {
10010 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10014 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10015 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10016 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10017 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10018 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10020 memset(&stats, 0, sizeof(stats));
10021 ret = i40e_aq_add_rem_control_packet_filter(hw,
10022 filter->mac_addr.addr_bytes,
10023 filter->ether_type, flags,
10024 pf->main_vsi->seid,
10025 filter->queue, add, &stats, NULL);
10028 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10029 ret, stats.mac_etype_used, stats.etype_used,
10030 stats.mac_etype_free, stats.etype_free);
10034 /* Add or delete a filter in SW list */
10036 ethertype_filter = rte_zmalloc("ethertype_filter",
10037 sizeof(*ethertype_filter), 0);
10038 if (ethertype_filter == NULL) {
10039 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10043 rte_memcpy(ethertype_filter, &check_filter,
10044 sizeof(check_filter));
10045 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10047 rte_free(ethertype_filter);
10049 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10056 * Handle operations for ethertype filter.
10059 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10060 enum rte_filter_op filter_op,
10063 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10066 if (filter_op == RTE_ETH_FILTER_NOP)
10070 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10075 switch (filter_op) {
10076 case RTE_ETH_FILTER_ADD:
10077 ret = i40e_ethertype_filter_set(pf,
10078 (struct rte_eth_ethertype_filter *)arg,
10081 case RTE_ETH_FILTER_DELETE:
10082 ret = i40e_ethertype_filter_set(pf,
10083 (struct rte_eth_ethertype_filter *)arg,
10087 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10095 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10096 enum rte_filter_type filter_type,
10097 enum rte_filter_op filter_op,
10105 switch (filter_type) {
10106 case RTE_ETH_FILTER_NONE:
10107 /* For global configuration */
10108 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10110 case RTE_ETH_FILTER_HASH:
10111 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10113 case RTE_ETH_FILTER_MACVLAN:
10114 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10116 case RTE_ETH_FILTER_ETHERTYPE:
10117 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10119 case RTE_ETH_FILTER_TUNNEL:
10120 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10122 case RTE_ETH_FILTER_FDIR:
10123 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10125 case RTE_ETH_FILTER_GENERIC:
10126 if (filter_op != RTE_ETH_FILTER_GET)
10128 *(const void **)arg = &i40e_flow_ops;
10131 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10141 * Check and enable Extended Tag.
10142 * Enabling Extended Tag is important for 40G performance.
10145 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10147 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10151 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10154 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10158 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10159 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10164 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10167 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10171 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10172 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10175 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10176 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10179 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10186 * As some registers wouldn't be reset unless a global hardware reset,
10187 * hardware initialization is needed to put those registers into an
10188 * expected initial state.
10191 i40e_hw_init(struct rte_eth_dev *dev)
10193 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10195 i40e_enable_extended_tag(dev);
10197 /* clear the PF Queue Filter control register */
10198 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10200 /* Disable symmetric hash per port */
10201 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10205 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10206 * however this function will return only one highest pctype index,
10207 * which is not quite correct. This is known problem of i40e driver
10208 * and needs to be fixed later.
10210 enum i40e_filter_pctype
10211 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10214 uint64_t pctype_mask;
10216 if (flow_type < I40E_FLOW_TYPE_MAX) {
10217 pctype_mask = adapter->pctypes_tbl[flow_type];
10218 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10219 if (pctype_mask & (1ULL << i))
10220 return (enum i40e_filter_pctype)i;
10223 return I40E_FILTER_PCTYPE_INVALID;
10227 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10228 enum i40e_filter_pctype pctype)
10231 uint64_t pctype_mask = 1ULL << pctype;
10233 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10235 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10239 return RTE_ETH_FLOW_UNKNOWN;
10243 * On X710, performance number is far from the expectation on recent firmware
10244 * versions; on XL710, performance number is also far from the expectation on
10245 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10246 * mode is enabled and port MAC address is equal to the packet destination MAC
10247 * address. The fix for this issue may not be integrated in the following
10248 * firmware version. So the workaround in software driver is needed. It needs
10249 * to modify the initial values of 3 internal only registers for both X710 and
10250 * XL710. Note that the values for X710 or XL710 could be different, and the
10251 * workaround can be removed when it is fixed in firmware in the future.
10254 /* For both X710 and XL710 */
10255 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10256 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10257 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10259 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10260 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10263 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10264 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10267 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10269 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10270 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10273 * GL_SWR_PM_UP_THR:
10274 * The value is not impacted from the link speed, its value is set according
10275 * to the total number of ports for a better pipe-monitor configuration.
10278 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10280 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10281 .device_id = (dev), \
10282 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10284 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10285 .device_id = (dev), \
10286 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10288 static const struct {
10289 uint16_t device_id;
10291 } swr_pm_table[] = {
10292 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10293 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10294 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10295 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10297 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10298 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10299 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10300 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10301 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10302 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10303 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10307 if (value == NULL) {
10308 PMD_DRV_LOG(ERR, "value is NULL");
10312 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10313 if (hw->device_id == swr_pm_table[i].device_id) {
10314 *value = swr_pm_table[i].val;
10316 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10318 hw->device_id, *value);
10327 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10329 enum i40e_status_code status;
10330 struct i40e_aq_get_phy_abilities_resp phy_ab;
10331 int ret = -ENOTSUP;
10334 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10338 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10341 rte_delay_us(100000);
10343 status = i40e_aq_get_phy_capabilities(hw, false,
10344 true, &phy_ab, NULL);
10352 i40e_configure_registers(struct i40e_hw *hw)
10358 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10359 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10360 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10366 for (i = 0; i < RTE_DIM(reg_table); i++) {
10367 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10368 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10370 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10371 else /* For X710/XL710/XXV710 */
10372 if (hw->aq.fw_maj_ver < 6)
10374 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10377 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10380 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10381 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10383 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10384 else /* For X710/XL710/XXV710 */
10386 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10389 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10392 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10393 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10394 "GL_SWR_PM_UP_THR value fixup",
10399 reg_table[i].val = cfg_val;
10402 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10405 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10406 reg_table[i].addr);
10409 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10410 reg_table[i].addr, reg);
10411 if (reg == reg_table[i].val)
10414 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10415 reg_table[i].val, NULL);
10418 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10419 reg_table[i].val, reg_table[i].addr);
10422 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10423 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10427 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10428 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10429 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10430 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10432 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10437 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10438 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10442 /* Configure for double VLAN RX stripping */
10443 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10444 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10445 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10446 ret = i40e_aq_debug_write_register(hw,
10447 I40E_VSI_TSR(vsi->vsi_id),
10450 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10452 return I40E_ERR_CONFIG;
10456 /* Configure for double VLAN TX insertion */
10457 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10458 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10459 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10460 ret = i40e_aq_debug_write_register(hw,
10461 I40E_VSI_L2TAGSTXVALID(
10462 vsi->vsi_id), reg, NULL);
10465 "Failed to update VSI_L2TAGSTXVALID[%d]",
10467 return I40E_ERR_CONFIG;
10475 * i40e_aq_add_mirror_rule
10476 * @hw: pointer to the hardware structure
10477 * @seid: VEB seid to add mirror rule to
10478 * @dst_id: destination vsi seid
10479 * @entries: Buffer which contains the entities to be mirrored
10480 * @count: number of entities contained in the buffer
10481 * @rule_id:the rule_id of the rule to be added
10483 * Add a mirror rule for a given veb.
10486 static enum i40e_status_code
10487 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10488 uint16_t seid, uint16_t dst_id,
10489 uint16_t rule_type, uint16_t *entries,
10490 uint16_t count, uint16_t *rule_id)
10492 struct i40e_aq_desc desc;
10493 struct i40e_aqc_add_delete_mirror_rule cmd;
10494 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10495 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10498 enum i40e_status_code status;
10500 i40e_fill_default_direct_cmd_desc(&desc,
10501 i40e_aqc_opc_add_mirror_rule);
10502 memset(&cmd, 0, sizeof(cmd));
10504 buff_len = sizeof(uint16_t) * count;
10505 desc.datalen = rte_cpu_to_le_16(buff_len);
10507 desc.flags |= rte_cpu_to_le_16(
10508 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10509 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10510 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10511 cmd.num_entries = rte_cpu_to_le_16(count);
10512 cmd.seid = rte_cpu_to_le_16(seid);
10513 cmd.destination = rte_cpu_to_le_16(dst_id);
10515 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10516 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10518 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10519 hw->aq.asq_last_status, resp->rule_id,
10520 resp->mirror_rules_used, resp->mirror_rules_free);
10521 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10527 * i40e_aq_del_mirror_rule
10528 * @hw: pointer to the hardware structure
10529 * @seid: VEB seid to add mirror rule to
10530 * @entries: Buffer which contains the entities to be mirrored
10531 * @count: number of entities contained in the buffer
10532 * @rule_id:the rule_id of the rule to be delete
10534 * Delete a mirror rule for a given veb.
10537 static enum i40e_status_code
10538 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10539 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10540 uint16_t count, uint16_t rule_id)
10542 struct i40e_aq_desc desc;
10543 struct i40e_aqc_add_delete_mirror_rule cmd;
10544 uint16_t buff_len = 0;
10545 enum i40e_status_code status;
10548 i40e_fill_default_direct_cmd_desc(&desc,
10549 i40e_aqc_opc_delete_mirror_rule);
10550 memset(&cmd, 0, sizeof(cmd));
10551 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10552 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10554 cmd.num_entries = count;
10555 buff_len = sizeof(uint16_t) * count;
10556 desc.datalen = rte_cpu_to_le_16(buff_len);
10557 buff = (void *)entries;
10559 /* rule id is filled in destination field for deleting mirror rule */
10560 cmd.destination = rte_cpu_to_le_16(rule_id);
10562 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10563 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10564 cmd.seid = rte_cpu_to_le_16(seid);
10566 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10567 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10573 * i40e_mirror_rule_set
10574 * @dev: pointer to the hardware structure
10575 * @mirror_conf: mirror rule info
10576 * @sw_id: mirror rule's sw_id
10577 * @on: enable/disable
10579 * set a mirror rule.
10583 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10584 struct rte_eth_mirror_conf *mirror_conf,
10585 uint8_t sw_id, uint8_t on)
10587 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10588 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10589 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10590 struct i40e_mirror_rule *parent = NULL;
10591 uint16_t seid, dst_seid, rule_id;
10595 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10597 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10599 "mirror rule can not be configured without veb or vfs.");
10602 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10603 PMD_DRV_LOG(ERR, "mirror table is full.");
10606 if (mirror_conf->dst_pool > pf->vf_num) {
10607 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10608 mirror_conf->dst_pool);
10612 seid = pf->main_vsi->veb->seid;
10614 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10615 if (sw_id <= it->index) {
10621 if (mirr_rule && sw_id == mirr_rule->index) {
10623 PMD_DRV_LOG(ERR, "mirror rule exists.");
10626 ret = i40e_aq_del_mirror_rule(hw, seid,
10627 mirr_rule->rule_type,
10628 mirr_rule->entries,
10629 mirr_rule->num_entries, mirr_rule->id);
10632 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10633 ret, hw->aq.asq_last_status);
10636 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10637 rte_free(mirr_rule);
10638 pf->nb_mirror_rule--;
10642 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10646 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10647 sizeof(struct i40e_mirror_rule) , 0);
10649 PMD_DRV_LOG(ERR, "failed to allocate memory");
10650 return I40E_ERR_NO_MEMORY;
10652 switch (mirror_conf->rule_type) {
10653 case ETH_MIRROR_VLAN:
10654 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10655 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10656 mirr_rule->entries[j] =
10657 mirror_conf->vlan.vlan_id[i];
10662 PMD_DRV_LOG(ERR, "vlan is not specified.");
10663 rte_free(mirr_rule);
10666 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10668 case ETH_MIRROR_VIRTUAL_POOL_UP:
10669 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10670 /* check if the specified pool bit is out of range */
10671 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10672 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10673 rte_free(mirr_rule);
10676 for (i = 0, j = 0; i < pf->vf_num; i++) {
10677 if (mirror_conf->pool_mask & (1ULL << i)) {
10678 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10682 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10683 /* add pf vsi to entries */
10684 mirr_rule->entries[j] = pf->main_vsi_seid;
10688 PMD_DRV_LOG(ERR, "pool is not specified.");
10689 rte_free(mirr_rule);
10692 /* egress and ingress in aq commands means from switch but not port */
10693 mirr_rule->rule_type =
10694 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10695 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10696 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10698 case ETH_MIRROR_UPLINK_PORT:
10699 /* egress and ingress in aq commands means from switch but not port*/
10700 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10702 case ETH_MIRROR_DOWNLINK_PORT:
10703 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10706 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10707 mirror_conf->rule_type);
10708 rte_free(mirr_rule);
10712 /* If the dst_pool is equal to vf_num, consider it as PF */
10713 if (mirror_conf->dst_pool == pf->vf_num)
10714 dst_seid = pf->main_vsi_seid;
10716 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10718 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10719 mirr_rule->rule_type, mirr_rule->entries,
10723 "failed to add mirror rule: ret = %d, aq_err = %d.",
10724 ret, hw->aq.asq_last_status);
10725 rte_free(mirr_rule);
10729 mirr_rule->index = sw_id;
10730 mirr_rule->num_entries = j;
10731 mirr_rule->id = rule_id;
10732 mirr_rule->dst_vsi_seid = dst_seid;
10735 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10737 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10739 pf->nb_mirror_rule++;
10744 * i40e_mirror_rule_reset
10745 * @dev: pointer to the device
10746 * @sw_id: mirror rule's sw_id
10748 * reset a mirror rule.
10752 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10754 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10755 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10756 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10760 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10762 seid = pf->main_vsi->veb->seid;
10764 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10765 if (sw_id == it->index) {
10771 ret = i40e_aq_del_mirror_rule(hw, seid,
10772 mirr_rule->rule_type,
10773 mirr_rule->entries,
10774 mirr_rule->num_entries, mirr_rule->id);
10777 "failed to remove mirror rule: status = %d, aq_err = %d.",
10778 ret, hw->aq.asq_last_status);
10781 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10782 rte_free(mirr_rule);
10783 pf->nb_mirror_rule--;
10785 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10792 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10794 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10795 uint64_t systim_cycles;
10797 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10798 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10801 return systim_cycles;
10805 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10807 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10808 uint64_t rx_tstamp;
10810 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10811 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10818 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10820 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10821 uint64_t tx_tstamp;
10823 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10824 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10831 i40e_start_timecounters(struct rte_eth_dev *dev)
10833 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10834 struct i40e_adapter *adapter = dev->data->dev_private;
10835 struct rte_eth_link link;
10836 uint32_t tsync_inc_l;
10837 uint32_t tsync_inc_h;
10839 /* Get current link speed. */
10840 i40e_dev_link_update(dev, 1);
10841 rte_eth_linkstatus_get(dev, &link);
10843 switch (link.link_speed) {
10844 case ETH_SPEED_NUM_40G:
10845 case ETH_SPEED_NUM_25G:
10846 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10847 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10849 case ETH_SPEED_NUM_10G:
10850 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10851 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10853 case ETH_SPEED_NUM_1G:
10854 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10855 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10862 /* Set the timesync increment value. */
10863 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10864 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10866 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10867 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10868 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10870 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10871 adapter->systime_tc.cc_shift = 0;
10872 adapter->systime_tc.nsec_mask = 0;
10874 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10875 adapter->rx_tstamp_tc.cc_shift = 0;
10876 adapter->rx_tstamp_tc.nsec_mask = 0;
10878 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10879 adapter->tx_tstamp_tc.cc_shift = 0;
10880 adapter->tx_tstamp_tc.nsec_mask = 0;
10884 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10886 struct i40e_adapter *adapter = dev->data->dev_private;
10888 adapter->systime_tc.nsec += delta;
10889 adapter->rx_tstamp_tc.nsec += delta;
10890 adapter->tx_tstamp_tc.nsec += delta;
10896 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10899 struct i40e_adapter *adapter = dev->data->dev_private;
10901 ns = rte_timespec_to_ns(ts);
10903 /* Set the timecounters to a new value. */
10904 adapter->systime_tc.nsec = ns;
10905 adapter->rx_tstamp_tc.nsec = ns;
10906 adapter->tx_tstamp_tc.nsec = ns;
10912 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10914 uint64_t ns, systime_cycles;
10915 struct i40e_adapter *adapter = dev->data->dev_private;
10917 systime_cycles = i40e_read_systime_cyclecounter(dev);
10918 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10919 *ts = rte_ns_to_timespec(ns);
10925 i40e_timesync_enable(struct rte_eth_dev *dev)
10927 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10928 uint32_t tsync_ctl_l;
10929 uint32_t tsync_ctl_h;
10931 /* Stop the timesync system time. */
10932 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10933 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10934 /* Reset the timesync system time value. */
10935 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10936 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10938 i40e_start_timecounters(dev);
10940 /* Clear timesync registers. */
10941 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10942 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10943 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10944 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10945 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10946 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10948 /* Enable timestamping of PTP packets. */
10949 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10950 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10952 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10953 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10954 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10956 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10957 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10963 i40e_timesync_disable(struct rte_eth_dev *dev)
10965 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10966 uint32_t tsync_ctl_l;
10967 uint32_t tsync_ctl_h;
10969 /* Disable timestamping of transmitted PTP packets. */
10970 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10971 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10973 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10974 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10976 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10977 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10979 /* Reset the timesync increment value. */
10980 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10981 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10987 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10988 struct timespec *timestamp, uint32_t flags)
10990 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10991 struct i40e_adapter *adapter = dev->data->dev_private;
10992 uint32_t sync_status;
10993 uint32_t index = flags & 0x03;
10994 uint64_t rx_tstamp_cycles;
10997 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10998 if ((sync_status & (1 << index)) == 0)
11001 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11002 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11003 *timestamp = rte_ns_to_timespec(ns);
11009 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11010 struct timespec *timestamp)
11012 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11013 struct i40e_adapter *adapter = dev->data->dev_private;
11014 uint32_t sync_status;
11015 uint64_t tx_tstamp_cycles;
11018 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11019 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11022 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11023 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11024 *timestamp = rte_ns_to_timespec(ns);
11030 * i40e_parse_dcb_configure - parse dcb configure from user
11031 * @dev: the device being configured
11032 * @dcb_cfg: pointer of the result of parse
11033 * @*tc_map: bit map of enabled traffic classes
11035 * Returns 0 on success, negative value on failure
11038 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11039 struct i40e_dcbx_config *dcb_cfg,
11042 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11043 uint8_t i, tc_bw, bw_lf;
11045 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11047 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11048 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11049 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11053 /* assume each tc has the same bw */
11054 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11055 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11056 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11057 /* to ensure the sum of tcbw is equal to 100 */
11058 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11059 for (i = 0; i < bw_lf; i++)
11060 dcb_cfg->etscfg.tcbwtable[i]++;
11062 /* assume each tc has the same Transmission Selection Algorithm */
11063 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11064 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11066 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11067 dcb_cfg->etscfg.prioritytable[i] =
11068 dcb_rx_conf->dcb_tc[i];
11070 /* FW needs one App to configure HW */
11071 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11072 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11073 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11074 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11076 if (dcb_rx_conf->nb_tcs == 0)
11077 *tc_map = 1; /* tc0 only */
11079 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11081 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11082 dcb_cfg->pfc.willing = 0;
11083 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11084 dcb_cfg->pfc.pfcenable = *tc_map;
11090 static enum i40e_status_code
11091 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11092 struct i40e_aqc_vsi_properties_data *info,
11093 uint8_t enabled_tcmap)
11095 enum i40e_status_code ret;
11096 int i, total_tc = 0;
11097 uint16_t qpnum_per_tc, bsf, qp_idx;
11098 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11099 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11100 uint16_t used_queues;
11102 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11103 if (ret != I40E_SUCCESS)
11106 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11107 if (enabled_tcmap & (1 << i))
11112 vsi->enabled_tc = enabled_tcmap;
11114 /* different VSI has different queues assigned */
11115 if (vsi->type == I40E_VSI_MAIN)
11116 used_queues = dev_data->nb_rx_queues -
11117 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11118 else if (vsi->type == I40E_VSI_VMDQ2)
11119 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11121 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11122 return I40E_ERR_NO_AVAILABLE_VSI;
11125 qpnum_per_tc = used_queues / total_tc;
11126 /* Number of queues per enabled TC */
11127 if (qpnum_per_tc == 0) {
11128 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11129 return I40E_ERR_INVALID_QP_ID;
11131 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11132 I40E_MAX_Q_PER_TC);
11133 bsf = rte_bsf32(qpnum_per_tc);
11136 * Configure TC and queue mapping parameters, for enabled TC,
11137 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11138 * default queue will serve it.
11141 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11142 if (vsi->enabled_tc & (1 << i)) {
11143 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11144 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11145 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11146 qp_idx += qpnum_per_tc;
11148 info->tc_mapping[i] = 0;
11151 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11152 if (vsi->type == I40E_VSI_SRIOV) {
11153 info->mapping_flags |=
11154 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11155 for (i = 0; i < vsi->nb_qps; i++)
11156 info->queue_mapping[i] =
11157 rte_cpu_to_le_16(vsi->base_queue + i);
11159 info->mapping_flags |=
11160 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11161 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11163 info->valid_sections |=
11164 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11166 return I40E_SUCCESS;
11170 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11171 * @veb: VEB to be configured
11172 * @tc_map: enabled TC bitmap
11174 * Returns 0 on success, negative value on failure
11176 static enum i40e_status_code
11177 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11179 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11180 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11181 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11182 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11183 enum i40e_status_code ret = I40E_SUCCESS;
11187 /* Check if enabled_tc is same as existing or new TCs */
11188 if (veb->enabled_tc == tc_map)
11191 /* configure tc bandwidth */
11192 memset(&veb_bw, 0, sizeof(veb_bw));
11193 veb_bw.tc_valid_bits = tc_map;
11194 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11195 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11196 if (tc_map & BIT_ULL(i))
11197 veb_bw.tc_bw_share_credits[i] = 1;
11199 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11203 "AQ command Config switch_comp BW allocation per TC failed = %d",
11204 hw->aq.asq_last_status);
11208 memset(&ets_query, 0, sizeof(ets_query));
11209 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11211 if (ret != I40E_SUCCESS) {
11213 "Failed to get switch_comp ETS configuration %u",
11214 hw->aq.asq_last_status);
11217 memset(&bw_query, 0, sizeof(bw_query));
11218 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11220 if (ret != I40E_SUCCESS) {
11222 "Failed to get switch_comp bandwidth configuration %u",
11223 hw->aq.asq_last_status);
11227 /* store and print out BW info */
11228 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11229 veb->bw_info.bw_max = ets_query.tc_bw_max;
11230 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11231 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11232 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11233 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11234 I40E_16_BIT_WIDTH);
11235 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11236 veb->bw_info.bw_ets_share_credits[i] =
11237 bw_query.tc_bw_share_credits[i];
11238 veb->bw_info.bw_ets_credits[i] =
11239 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11240 /* 4 bits per TC, 4th bit is reserved */
11241 veb->bw_info.bw_ets_max[i] =
11242 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11243 RTE_LEN2MASK(3, uint8_t));
11244 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11245 veb->bw_info.bw_ets_share_credits[i]);
11246 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11247 veb->bw_info.bw_ets_credits[i]);
11248 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11249 veb->bw_info.bw_ets_max[i]);
11252 veb->enabled_tc = tc_map;
11259 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11260 * @vsi: VSI to be configured
11261 * @tc_map: enabled TC bitmap
11263 * Returns 0 on success, negative value on failure
11265 static enum i40e_status_code
11266 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11268 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11269 struct i40e_vsi_context ctxt;
11270 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11271 enum i40e_status_code ret = I40E_SUCCESS;
11274 /* Check if enabled_tc is same as existing or new TCs */
11275 if (vsi->enabled_tc == tc_map)
11278 /* configure tc bandwidth */
11279 memset(&bw_data, 0, sizeof(bw_data));
11280 bw_data.tc_valid_bits = tc_map;
11281 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11282 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11283 if (tc_map & BIT_ULL(i))
11284 bw_data.tc_bw_credits[i] = 1;
11286 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11289 "AQ command Config VSI BW allocation per TC failed = %d",
11290 hw->aq.asq_last_status);
11293 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11294 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11296 /* Update Queue Pairs Mapping for currently enabled UPs */
11297 ctxt.seid = vsi->seid;
11298 ctxt.pf_num = hw->pf_id;
11300 ctxt.uplink_seid = vsi->uplink_seid;
11301 ctxt.info = vsi->info;
11303 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11307 /* Update the VSI after updating the VSI queue-mapping information */
11308 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11310 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11311 hw->aq.asq_last_status);
11314 /* update the local VSI info with updated queue map */
11315 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11316 sizeof(vsi->info.tc_mapping));
11317 rte_memcpy(&vsi->info.queue_mapping,
11318 &ctxt.info.queue_mapping,
11319 sizeof(vsi->info.queue_mapping));
11320 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11321 vsi->info.valid_sections = 0;
11323 /* query and update current VSI BW information */
11324 ret = i40e_vsi_get_bw_config(vsi);
11327 "Failed updating vsi bw info, err %s aq_err %s",
11328 i40e_stat_str(hw, ret),
11329 i40e_aq_str(hw, hw->aq.asq_last_status));
11333 vsi->enabled_tc = tc_map;
11340 * i40e_dcb_hw_configure - program the dcb setting to hw
11341 * @pf: pf the configuration is taken on
11342 * @new_cfg: new configuration
11343 * @tc_map: enabled TC bitmap
11345 * Returns 0 on success, negative value on failure
11347 static enum i40e_status_code
11348 i40e_dcb_hw_configure(struct i40e_pf *pf,
11349 struct i40e_dcbx_config *new_cfg,
11352 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11353 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11354 struct i40e_vsi *main_vsi = pf->main_vsi;
11355 struct i40e_vsi_list *vsi_list;
11356 enum i40e_status_code ret;
11360 /* Use the FW API if FW > v4.4*/
11361 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11362 (hw->aq.fw_maj_ver >= 5))) {
11364 "FW < v4.4, can not use FW LLDP API to configure DCB");
11365 return I40E_ERR_FIRMWARE_API_VERSION;
11368 /* Check if need reconfiguration */
11369 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11370 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11371 return I40E_SUCCESS;
11374 /* Copy the new config to the current config */
11375 *old_cfg = *new_cfg;
11376 old_cfg->etsrec = old_cfg->etscfg;
11377 ret = i40e_set_dcb_config(hw);
11379 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11380 i40e_stat_str(hw, ret),
11381 i40e_aq_str(hw, hw->aq.asq_last_status));
11384 /* set receive Arbiter to RR mode and ETS scheme by default */
11385 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11386 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11387 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11388 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11389 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11390 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11391 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11392 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11393 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11394 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11395 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11396 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11397 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11399 /* get local mib to check whether it is configured correctly */
11401 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11402 /* Get Local DCB Config */
11403 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11404 &hw->local_dcbx_config);
11406 /* if Veb is created, need to update TC of it at first */
11407 if (main_vsi->veb) {
11408 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11410 PMD_INIT_LOG(WARNING,
11411 "Failed configuring TC for VEB seid=%d",
11412 main_vsi->veb->seid);
11414 /* Update each VSI */
11415 i40e_vsi_config_tc(main_vsi, tc_map);
11416 if (main_vsi->veb) {
11417 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11418 /* Beside main VSI and VMDQ VSIs, only enable default
11419 * TC for other VSIs
11421 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11422 ret = i40e_vsi_config_tc(vsi_list->vsi,
11425 ret = i40e_vsi_config_tc(vsi_list->vsi,
11426 I40E_DEFAULT_TCMAP);
11428 PMD_INIT_LOG(WARNING,
11429 "Failed configuring TC for VSI seid=%d",
11430 vsi_list->vsi->seid);
11434 return I40E_SUCCESS;
11438 * i40e_dcb_init_configure - initial dcb config
11439 * @dev: device being configured
11440 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11442 * Returns 0 on success, negative value on failure
11445 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11447 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11448 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11451 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11452 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11456 /* DCB initialization:
11457 * Update DCB configuration from the Firmware and configure
11458 * LLDP MIB change event.
11460 if (sw_dcb == TRUE) {
11461 if (i40e_need_stop_lldp(dev)) {
11462 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11463 if (ret != I40E_SUCCESS)
11464 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11467 ret = i40e_init_dcb(hw);
11468 /* If lldp agent is stopped, the return value from
11469 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11470 * adminq status. Otherwise, it should return success.
11472 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11473 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11474 memset(&hw->local_dcbx_config, 0,
11475 sizeof(struct i40e_dcbx_config));
11476 /* set dcb default configuration */
11477 hw->local_dcbx_config.etscfg.willing = 0;
11478 hw->local_dcbx_config.etscfg.maxtcs = 0;
11479 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11480 hw->local_dcbx_config.etscfg.tsatable[0] =
11482 /* all UPs mapping to TC0 */
11483 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11484 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11485 hw->local_dcbx_config.etsrec =
11486 hw->local_dcbx_config.etscfg;
11487 hw->local_dcbx_config.pfc.willing = 0;
11488 hw->local_dcbx_config.pfc.pfccap =
11489 I40E_MAX_TRAFFIC_CLASS;
11490 /* FW needs one App to configure HW */
11491 hw->local_dcbx_config.numapps = 1;
11492 hw->local_dcbx_config.app[0].selector =
11493 I40E_APP_SEL_ETHTYPE;
11494 hw->local_dcbx_config.app[0].priority = 3;
11495 hw->local_dcbx_config.app[0].protocolid =
11496 I40E_APP_PROTOID_FCOE;
11497 ret = i40e_set_dcb_config(hw);
11500 "default dcb config fails. err = %d, aq_err = %d.",
11501 ret, hw->aq.asq_last_status);
11506 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11507 ret, hw->aq.asq_last_status);
11511 ret = i40e_aq_start_lldp(hw, NULL);
11512 if (ret != I40E_SUCCESS)
11513 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11515 ret = i40e_init_dcb(hw);
11517 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11519 "HW doesn't support DCBX offload.");
11524 "DCBX configuration failed, err = %d, aq_err = %d.",
11525 ret, hw->aq.asq_last_status);
11533 * i40e_dcb_setup - setup dcb related config
11534 * @dev: device being configured
11536 * Returns 0 on success, negative value on failure
11539 i40e_dcb_setup(struct rte_eth_dev *dev)
11541 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11542 struct i40e_dcbx_config dcb_cfg;
11543 uint8_t tc_map = 0;
11546 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11547 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11551 if (pf->vf_num != 0)
11552 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11554 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11556 PMD_INIT_LOG(ERR, "invalid dcb config");
11559 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11561 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11569 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11570 struct rte_eth_dcb_info *dcb_info)
11572 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11573 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11574 struct i40e_vsi *vsi = pf->main_vsi;
11575 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11576 uint16_t bsf, tc_mapping;
11579 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11580 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11582 dcb_info->nb_tcs = 1;
11583 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11584 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11585 for (i = 0; i < dcb_info->nb_tcs; i++)
11586 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11588 /* get queue mapping if vmdq is disabled */
11589 if (!pf->nb_cfg_vmdq_vsi) {
11590 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11591 if (!(vsi->enabled_tc & (1 << i)))
11593 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11594 dcb_info->tc_queue.tc_rxq[j][i].base =
11595 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11596 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11597 dcb_info->tc_queue.tc_txq[j][i].base =
11598 dcb_info->tc_queue.tc_rxq[j][i].base;
11599 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11600 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11601 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11602 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11603 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11608 /* get queue mapping if vmdq is enabled */
11610 vsi = pf->vmdq[j].vsi;
11611 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11612 if (!(vsi->enabled_tc & (1 << i)))
11614 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11615 dcb_info->tc_queue.tc_rxq[j][i].base =
11616 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11617 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11618 dcb_info->tc_queue.tc_txq[j][i].base =
11619 dcb_info->tc_queue.tc_rxq[j][i].base;
11620 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11621 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11622 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11623 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11624 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11627 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11632 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11634 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11635 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11636 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11637 uint16_t msix_intr;
11639 msix_intr = intr_handle->intr_vec[queue_id];
11640 if (msix_intr == I40E_MISC_VEC_ID)
11641 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11642 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11643 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11644 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11647 I40E_PFINT_DYN_CTLN(msix_intr -
11648 I40E_RX_VEC_START),
11649 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11650 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11651 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11653 I40E_WRITE_FLUSH(hw);
11654 rte_intr_ack(&pci_dev->intr_handle);
11660 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11662 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11663 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11664 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11665 uint16_t msix_intr;
11667 msix_intr = intr_handle->intr_vec[queue_id];
11668 if (msix_intr == I40E_MISC_VEC_ID)
11669 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11670 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11673 I40E_PFINT_DYN_CTLN(msix_intr -
11674 I40E_RX_VEC_START),
11675 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11676 I40E_WRITE_FLUSH(hw);
11682 * This function is used to check if the register is valid.
11683 * Below is the valid registers list for X722 only:
11687 * 0x208e00--0x209000
11688 * 0x20be00--0x20c000
11689 * 0x263c00--0x264000
11690 * 0x265c00--0x266000
11692 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11694 if ((type != I40E_MAC_X722) &&
11695 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11696 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11697 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11698 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11699 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11700 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11701 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11707 static int i40e_get_regs(struct rte_eth_dev *dev,
11708 struct rte_dev_reg_info *regs)
11710 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11711 uint32_t *ptr_data = regs->data;
11712 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11713 const struct i40e_reg_info *reg_info;
11715 if (ptr_data == NULL) {
11716 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11717 regs->width = sizeof(uint32_t);
11721 /* The first few registers have to be read using AQ operations */
11723 while (i40e_regs_adminq[reg_idx].name) {
11724 reg_info = &i40e_regs_adminq[reg_idx++];
11725 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11727 arr_idx2 <= reg_info->count2;
11729 reg_offset = arr_idx * reg_info->stride1 +
11730 arr_idx2 * reg_info->stride2;
11731 reg_offset += reg_info->base_addr;
11732 ptr_data[reg_offset >> 2] =
11733 i40e_read_rx_ctl(hw, reg_offset);
11737 /* The remaining registers can be read using primitives */
11739 while (i40e_regs_others[reg_idx].name) {
11740 reg_info = &i40e_regs_others[reg_idx++];
11741 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11743 arr_idx2 <= reg_info->count2;
11745 reg_offset = arr_idx * reg_info->stride1 +
11746 arr_idx2 * reg_info->stride2;
11747 reg_offset += reg_info->base_addr;
11748 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11749 ptr_data[reg_offset >> 2] = 0;
11751 ptr_data[reg_offset >> 2] =
11752 I40E_READ_REG(hw, reg_offset);
11759 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11761 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11763 /* Convert word count to byte count */
11764 return hw->nvm.sr_size << 1;
11767 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11768 struct rte_dev_eeprom_info *eeprom)
11770 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11771 uint16_t *data = eeprom->data;
11772 uint16_t offset, length, cnt_words;
11775 offset = eeprom->offset >> 1;
11776 length = eeprom->length >> 1;
11777 cnt_words = length;
11779 if (offset > hw->nvm.sr_size ||
11780 offset + length > hw->nvm.sr_size) {
11781 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11785 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11787 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11788 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11789 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11796 static int i40e_get_module_info(struct rte_eth_dev *dev,
11797 struct rte_eth_dev_module_info *modinfo)
11799 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11800 uint32_t sff8472_comp = 0;
11801 uint32_t sff8472_swap = 0;
11802 uint32_t sff8636_rev = 0;
11803 i40e_status status;
11806 /* Check if firmware supports reading module EEPROM. */
11807 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11809 "Module EEPROM memory read not supported. "
11810 "Please update the NVM image.\n");
11814 status = i40e_update_link_info(hw);
11818 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11820 "Cannot read module EEPROM memory. "
11821 "No module connected.\n");
11825 type = hw->phy.link_info.module_type[0];
11828 case I40E_MODULE_TYPE_SFP:
11829 status = i40e_aq_get_phy_register(hw,
11830 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11831 I40E_I2C_EEPROM_DEV_ADDR, 1,
11832 I40E_MODULE_SFF_8472_COMP,
11833 &sff8472_comp, NULL);
11837 status = i40e_aq_get_phy_register(hw,
11838 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11839 I40E_I2C_EEPROM_DEV_ADDR, 1,
11840 I40E_MODULE_SFF_8472_SWAP,
11841 &sff8472_swap, NULL);
11845 /* Check if the module requires address swap to access
11846 * the other EEPROM memory page.
11848 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11849 PMD_DRV_LOG(WARNING,
11850 "Module address swap to access "
11851 "page 0xA2 is not supported.\n");
11852 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11853 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11854 } else if (sff8472_comp == 0x00) {
11855 /* Module is not SFF-8472 compliant */
11856 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11857 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11859 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11860 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11863 case I40E_MODULE_TYPE_QSFP_PLUS:
11864 /* Read from memory page 0. */
11865 status = i40e_aq_get_phy_register(hw,
11866 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11868 I40E_MODULE_REVISION_ADDR,
11869 &sff8636_rev, NULL);
11872 /* Determine revision compliance byte */
11873 if (sff8636_rev > 0x02) {
11874 /* Module is SFF-8636 compliant */
11875 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11876 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11878 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11879 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11882 case I40E_MODULE_TYPE_QSFP28:
11883 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11884 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11887 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11893 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11894 struct rte_dev_eeprom_info *info)
11896 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11897 bool is_sfp = false;
11898 i40e_status status;
11900 uint32_t value = 0;
11903 if (!info || !info->length || !info->data)
11906 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11910 for (i = 0; i < info->length; i++) {
11911 u32 offset = i + info->offset;
11912 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11914 /* Check if we need to access the other memory page */
11916 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11917 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11918 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11921 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11922 /* Compute memory page number and offset. */
11923 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11927 status = i40e_aq_get_phy_register(hw,
11928 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11929 addr, offset, 1, &value, NULL);
11932 data[i] = (uint8_t)value;
11937 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11938 struct rte_ether_addr *mac_addr)
11940 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11941 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11942 struct i40e_vsi *vsi = pf->main_vsi;
11943 struct i40e_mac_filter_info mac_filter;
11944 struct i40e_mac_filter *f;
11947 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11948 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11952 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11953 if (rte_is_same_ether_addr(&pf->dev_addr,
11954 &f->mac_info.mac_addr))
11959 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11963 mac_filter = f->mac_info;
11964 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11965 if (ret != I40E_SUCCESS) {
11966 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11969 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11970 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11971 if (ret != I40E_SUCCESS) {
11972 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11975 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11977 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11978 mac_addr->addr_bytes, NULL);
11979 if (ret != I40E_SUCCESS) {
11980 PMD_DRV_LOG(ERR, "Failed to change mac");
11988 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11990 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11991 struct rte_eth_dev_data *dev_data = pf->dev_data;
11992 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11995 /* check if mtu is within the allowed range */
11996 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
11999 /* mtu setting is forbidden if port is start */
12000 if (dev_data->dev_started) {
12001 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12002 dev_data->port_id);
12006 if (frame_size > RTE_ETHER_MAX_LEN)
12007 dev_data->dev_conf.rxmode.offloads |=
12008 DEV_RX_OFFLOAD_JUMBO_FRAME;
12010 dev_data->dev_conf.rxmode.offloads &=
12011 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12013 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12018 /* Restore ethertype filter */
12020 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12022 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12023 struct i40e_ethertype_filter_list
12024 *ethertype_list = &pf->ethertype.ethertype_list;
12025 struct i40e_ethertype_filter *f;
12026 struct i40e_control_filter_stats stats;
12029 TAILQ_FOREACH(f, ethertype_list, rules) {
12031 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12032 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12033 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12034 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12035 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12037 memset(&stats, 0, sizeof(stats));
12038 i40e_aq_add_rem_control_packet_filter(hw,
12039 f->input.mac_addr.addr_bytes,
12040 f->input.ether_type,
12041 flags, pf->main_vsi->seid,
12042 f->queue, 1, &stats, NULL);
12044 PMD_DRV_LOG(INFO, "Ethertype filter:"
12045 " mac_etype_used = %u, etype_used = %u,"
12046 " mac_etype_free = %u, etype_free = %u",
12047 stats.mac_etype_used, stats.etype_used,
12048 stats.mac_etype_free, stats.etype_free);
12051 /* Restore tunnel filter */
12053 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12055 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12056 struct i40e_vsi *vsi;
12057 struct i40e_pf_vf *vf;
12058 struct i40e_tunnel_filter_list
12059 *tunnel_list = &pf->tunnel.tunnel_list;
12060 struct i40e_tunnel_filter *f;
12061 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12062 bool big_buffer = 0;
12064 TAILQ_FOREACH(f, tunnel_list, rules) {
12066 vsi = pf->main_vsi;
12068 vf = &pf->vfs[f->vf_id];
12071 memset(&cld_filter, 0, sizeof(cld_filter));
12072 rte_ether_addr_copy((struct rte_ether_addr *)
12073 &f->input.outer_mac,
12074 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12075 rte_ether_addr_copy((struct rte_ether_addr *)
12076 &f->input.inner_mac,
12077 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12078 cld_filter.element.inner_vlan = f->input.inner_vlan;
12079 cld_filter.element.flags = f->input.flags;
12080 cld_filter.element.tenant_id = f->input.tenant_id;
12081 cld_filter.element.queue_number = f->queue;
12082 rte_memcpy(cld_filter.general_fields,
12083 f->input.general_fields,
12084 sizeof(f->input.general_fields));
12086 if (((f->input.flags &
12087 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12088 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12090 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12091 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12093 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12094 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12098 i40e_aq_add_cloud_filters_bb(hw,
12099 vsi->seid, &cld_filter, 1);
12101 i40e_aq_add_cloud_filters(hw, vsi->seid,
12102 &cld_filter.element, 1);
12106 /* Restore rss filter */
12108 i40e_rss_filter_restore(struct i40e_pf *pf)
12110 struct i40e_rte_flow_rss_conf *conf =
12112 if (conf->conf.queue_num)
12113 i40e_config_rss_filter(pf, conf, TRUE);
12117 i40e_filter_restore(struct i40e_pf *pf)
12119 i40e_ethertype_filter_restore(pf);
12120 i40e_tunnel_filter_restore(pf);
12121 i40e_fdir_filter_restore(pf);
12122 i40e_rss_filter_restore(pf);
12126 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12128 if (strcmp(dev->device->driver->name, drv->driver.name))
12135 is_i40e_supported(struct rte_eth_dev *dev)
12137 return is_device_supported(dev, &rte_i40e_pmd);
12140 struct i40e_customized_pctype*
12141 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12145 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12146 if (pf->customized_pctype[i].index == index)
12147 return &pf->customized_pctype[i];
12153 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12154 uint32_t pkg_size, uint32_t proto_num,
12155 struct rte_pmd_i40e_proto_info *proto,
12156 enum rte_pmd_i40e_package_op op)
12158 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12159 uint32_t pctype_num;
12160 struct rte_pmd_i40e_ptype_info *pctype;
12161 uint32_t buff_size;
12162 struct i40e_customized_pctype *new_pctype = NULL;
12164 uint8_t pctype_value;
12169 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12170 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12171 PMD_DRV_LOG(ERR, "Unsupported operation.");
12175 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12176 (uint8_t *)&pctype_num, sizeof(pctype_num),
12177 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12179 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12183 PMD_DRV_LOG(INFO, "No new pctype added");
12187 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12188 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12190 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12193 /* get information about new pctype list */
12194 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12195 (uint8_t *)pctype, buff_size,
12196 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12198 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12203 /* Update customized pctype. */
12204 for (i = 0; i < pctype_num; i++) {
12205 pctype_value = pctype[i].ptype_id;
12206 memset(name, 0, sizeof(name));
12207 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12208 proto_id = pctype[i].protocols[j];
12209 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12211 for (n = 0; n < proto_num; n++) {
12212 if (proto[n].proto_id != proto_id)
12214 strlcat(name, proto[n].name, sizeof(name));
12215 strlcat(name, "_", sizeof(name));
12219 name[strlen(name) - 1] = '\0';
12220 if (!strcmp(name, "GTPC"))
12222 i40e_find_customized_pctype(pf,
12223 I40E_CUSTOMIZED_GTPC);
12224 else if (!strcmp(name, "GTPU_IPV4"))
12226 i40e_find_customized_pctype(pf,
12227 I40E_CUSTOMIZED_GTPU_IPV4);
12228 else if (!strcmp(name, "GTPU_IPV6"))
12230 i40e_find_customized_pctype(pf,
12231 I40E_CUSTOMIZED_GTPU_IPV6);
12232 else if (!strcmp(name, "GTPU"))
12234 i40e_find_customized_pctype(pf,
12235 I40E_CUSTOMIZED_GTPU);
12237 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12238 new_pctype->pctype = pctype_value;
12239 new_pctype->valid = true;
12241 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12242 new_pctype->valid = false;
12252 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12253 uint32_t pkg_size, uint32_t proto_num,
12254 struct rte_pmd_i40e_proto_info *proto,
12255 enum rte_pmd_i40e_package_op op)
12257 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12258 uint16_t port_id = dev->data->port_id;
12259 uint32_t ptype_num;
12260 struct rte_pmd_i40e_ptype_info *ptype;
12261 uint32_t buff_size;
12263 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12268 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12269 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12270 PMD_DRV_LOG(ERR, "Unsupported operation.");
12274 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12275 rte_pmd_i40e_ptype_mapping_reset(port_id);
12279 /* get information about new ptype num */
12280 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12281 (uint8_t *)&ptype_num, sizeof(ptype_num),
12282 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12284 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12288 PMD_DRV_LOG(INFO, "No new ptype added");
12292 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12293 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12295 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12299 /* get information about new ptype list */
12300 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12301 (uint8_t *)ptype, buff_size,
12302 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12304 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12309 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12310 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12311 if (!ptype_mapping) {
12312 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12317 /* Update ptype mapping table. */
12318 for (i = 0; i < ptype_num; i++) {
12319 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12320 ptype_mapping[i].sw_ptype = 0;
12322 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12323 proto_id = ptype[i].protocols[j];
12324 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12326 for (n = 0; n < proto_num; n++) {
12327 if (proto[n].proto_id != proto_id)
12329 memset(name, 0, sizeof(name));
12330 strcpy(name, proto[n].name);
12331 if (!strncasecmp(name, "PPPOE", 5))
12332 ptype_mapping[i].sw_ptype |=
12333 RTE_PTYPE_L2_ETHER_PPPOE;
12334 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12336 ptype_mapping[i].sw_ptype |=
12337 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12338 ptype_mapping[i].sw_ptype |=
12340 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12342 ptype_mapping[i].sw_ptype |=
12343 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12344 ptype_mapping[i].sw_ptype |=
12345 RTE_PTYPE_INNER_L4_FRAG;
12346 } else if (!strncasecmp(name, "OIPV4", 5)) {
12347 ptype_mapping[i].sw_ptype |=
12348 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12350 } else if (!strncasecmp(name, "IPV4", 4) &&
12352 ptype_mapping[i].sw_ptype |=
12353 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12354 else if (!strncasecmp(name, "IPV4", 4) &&
12356 ptype_mapping[i].sw_ptype |=
12357 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12358 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12360 ptype_mapping[i].sw_ptype |=
12361 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12362 ptype_mapping[i].sw_ptype |=
12364 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12366 ptype_mapping[i].sw_ptype |=
12367 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12368 ptype_mapping[i].sw_ptype |=
12369 RTE_PTYPE_INNER_L4_FRAG;
12370 } else if (!strncasecmp(name, "OIPV6", 5)) {
12371 ptype_mapping[i].sw_ptype |=
12372 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12374 } else if (!strncasecmp(name, "IPV6", 4) &&
12376 ptype_mapping[i].sw_ptype |=
12377 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12378 else if (!strncasecmp(name, "IPV6", 4) &&
12380 ptype_mapping[i].sw_ptype |=
12381 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12382 else if (!strncasecmp(name, "UDP", 3) &&
12384 ptype_mapping[i].sw_ptype |=
12386 else if (!strncasecmp(name, "UDP", 3) &&
12388 ptype_mapping[i].sw_ptype |=
12389 RTE_PTYPE_INNER_L4_UDP;
12390 else if (!strncasecmp(name, "TCP", 3) &&
12392 ptype_mapping[i].sw_ptype |=
12394 else if (!strncasecmp(name, "TCP", 3) &&
12396 ptype_mapping[i].sw_ptype |=
12397 RTE_PTYPE_INNER_L4_TCP;
12398 else if (!strncasecmp(name, "SCTP", 4) &&
12400 ptype_mapping[i].sw_ptype |=
12402 else if (!strncasecmp(name, "SCTP", 4) &&
12404 ptype_mapping[i].sw_ptype |=
12405 RTE_PTYPE_INNER_L4_SCTP;
12406 else if ((!strncasecmp(name, "ICMP", 4) ||
12407 !strncasecmp(name, "ICMPV6", 6)) &&
12409 ptype_mapping[i].sw_ptype |=
12411 else if ((!strncasecmp(name, "ICMP", 4) ||
12412 !strncasecmp(name, "ICMPV6", 6)) &&
12414 ptype_mapping[i].sw_ptype |=
12415 RTE_PTYPE_INNER_L4_ICMP;
12416 else if (!strncasecmp(name, "GTPC", 4)) {
12417 ptype_mapping[i].sw_ptype |=
12418 RTE_PTYPE_TUNNEL_GTPC;
12420 } else if (!strncasecmp(name, "GTPU", 4)) {
12421 ptype_mapping[i].sw_ptype |=
12422 RTE_PTYPE_TUNNEL_GTPU;
12424 } else if (!strncasecmp(name, "GRENAT", 6)) {
12425 ptype_mapping[i].sw_ptype |=
12426 RTE_PTYPE_TUNNEL_GRENAT;
12428 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12429 !strncasecmp(name, "L2TPV2", 6)) {
12430 ptype_mapping[i].sw_ptype |=
12431 RTE_PTYPE_TUNNEL_L2TP;
12440 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12443 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12445 rte_free(ptype_mapping);
12451 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12452 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12454 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12455 uint32_t proto_num;
12456 struct rte_pmd_i40e_proto_info *proto;
12457 uint32_t buff_size;
12461 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12462 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12463 PMD_DRV_LOG(ERR, "Unsupported operation.");
12467 /* get information about protocol number */
12468 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12469 (uint8_t *)&proto_num, sizeof(proto_num),
12470 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12472 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12476 PMD_DRV_LOG(INFO, "No new protocol added");
12480 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12481 proto = rte_zmalloc("new_proto", buff_size, 0);
12483 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12487 /* get information about protocol list */
12488 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12489 (uint8_t *)proto, buff_size,
12490 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12492 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12497 /* Check if GTP is supported. */
12498 for (i = 0; i < proto_num; i++) {
12499 if (!strncmp(proto[i].name, "GTP", 3)) {
12500 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12501 pf->gtp_support = true;
12503 pf->gtp_support = false;
12508 /* Update customized pctype info */
12509 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12510 proto_num, proto, op);
12512 PMD_DRV_LOG(INFO, "No pctype is updated.");
12514 /* Update customized ptype info */
12515 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12516 proto_num, proto, op);
12518 PMD_DRV_LOG(INFO, "No ptype is updated.");
12523 /* Create a QinQ cloud filter
12525 * The Fortville NIC has limited resources for tunnel filters,
12526 * so we can only reuse existing filters.
12528 * In step 1 we define which Field Vector fields can be used for
12530 * As we do not have the inner tag defined as a field,
12531 * we have to define it first, by reusing one of L1 entries.
12533 * In step 2 we are replacing one of existing filter types with
12534 * a new one for QinQ.
12535 * As we reusing L1 and replacing L2, some of the default filter
12536 * types will disappear,which depends on L1 and L2 entries we reuse.
12538 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12540 * 1. Create L1 filter of outer vlan (12b) which will be in use
12541 * later when we define the cloud filter.
12542 * a. Valid_flags.replace_cloud = 0
12543 * b. Old_filter = 10 (Stag_Inner_Vlan)
12544 * c. New_filter = 0x10
12545 * d. TR bit = 0xff (optional, not used here)
12546 * e. Buffer – 2 entries:
12547 * i. Byte 0 = 8 (outer vlan FV index).
12549 * Byte 2-3 = 0x0fff
12550 * ii. Byte 0 = 37 (inner vlan FV index).
12552 * Byte 2-3 = 0x0fff
12555 * 2. Create cloud filter using two L1 filters entries: stag and
12556 * new filter(outer vlan+ inner vlan)
12557 * a. Valid_flags.replace_cloud = 1
12558 * b. Old_filter = 1 (instead of outer IP)
12559 * c. New_filter = 0x10
12560 * d. Buffer – 2 entries:
12561 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12562 * Byte 1-3 = 0 (rsv)
12563 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12564 * Byte 9-11 = 0 (rsv)
12567 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12569 int ret = -ENOTSUP;
12570 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12571 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12572 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12573 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12575 if (pf->support_multi_driver) {
12576 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12581 memset(&filter_replace, 0,
12582 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12583 memset(&filter_replace_buf, 0,
12584 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12586 /* create L1 filter */
12587 filter_replace.old_filter_type =
12588 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12589 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12590 filter_replace.tr_bit = 0;
12592 /* Prepare the buffer, 2 entries */
12593 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12594 filter_replace_buf.data[0] |=
12595 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12596 /* Field Vector 12b mask */
12597 filter_replace_buf.data[2] = 0xff;
12598 filter_replace_buf.data[3] = 0x0f;
12599 filter_replace_buf.data[4] =
12600 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12601 filter_replace_buf.data[4] |=
12602 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12603 /* Field Vector 12b mask */
12604 filter_replace_buf.data[6] = 0xff;
12605 filter_replace_buf.data[7] = 0x0f;
12606 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12607 &filter_replace_buf);
12608 if (ret != I40E_SUCCESS)
12611 if (filter_replace.old_filter_type !=
12612 filter_replace.new_filter_type)
12613 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12614 " original: 0x%x, new: 0x%x",
12616 filter_replace.old_filter_type,
12617 filter_replace.new_filter_type);
12619 /* Apply the second L2 cloud filter */
12620 memset(&filter_replace, 0,
12621 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12622 memset(&filter_replace_buf, 0,
12623 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12625 /* create L2 filter, input for L2 filter will be L1 filter */
12626 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12627 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12628 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12630 /* Prepare the buffer, 2 entries */
12631 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12632 filter_replace_buf.data[0] |=
12633 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12634 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12635 filter_replace_buf.data[4] |=
12636 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12637 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12638 &filter_replace_buf);
12639 if (!ret && (filter_replace.old_filter_type !=
12640 filter_replace.new_filter_type))
12641 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12642 " original: 0x%x, new: 0x%x",
12644 filter_replace.old_filter_type,
12645 filter_replace.new_filter_type);
12651 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12652 const struct rte_flow_action_rss *in)
12654 if (in->key_len > RTE_DIM(out->key) ||
12655 in->queue_num > RTE_DIM(out->queue))
12657 if (!in->key && in->key_len)
12659 out->conf = (struct rte_flow_action_rss){
12661 .level = in->level,
12662 .types = in->types,
12663 .key_len = in->key_len,
12664 .queue_num = in->queue_num,
12665 .queue = memcpy(out->queue, in->queue,
12666 sizeof(*in->queue) * in->queue_num),
12669 out->conf.key = memcpy(out->key, in->key, in->key_len);
12674 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12675 const struct rte_flow_action_rss *with)
12677 return (comp->func == with->func &&
12678 comp->level == with->level &&
12679 comp->types == with->types &&
12680 comp->key_len == with->key_len &&
12681 comp->queue_num == with->queue_num &&
12682 !memcmp(comp->key, with->key, with->key_len) &&
12683 !memcmp(comp->queue, with->queue,
12684 sizeof(*with->queue) * with->queue_num));
12688 i40e_config_rss_filter(struct i40e_pf *pf,
12689 struct i40e_rte_flow_rss_conf *conf, bool add)
12691 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12692 uint32_t i, lut = 0;
12694 struct rte_eth_rss_conf rss_conf = {
12695 .rss_key = conf->conf.key_len ?
12696 (void *)(uintptr_t)conf->conf.key : NULL,
12697 .rss_key_len = conf->conf.key_len,
12698 .rss_hf = conf->conf.types,
12700 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12703 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12704 i40e_pf_disable_rss(pf);
12705 memset(rss_info, 0,
12706 sizeof(struct i40e_rte_flow_rss_conf));
12712 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12713 * It's necessary to calculate the actual PF queues that are configured.
12715 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12716 num = i40e_pf_calc_configured_queues_num(pf);
12718 num = pf->dev_data->nb_rx_queues;
12720 num = RTE_MIN(num, conf->conf.queue_num);
12721 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12725 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12729 /* Fill in redirection table */
12730 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12733 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12734 hw->func_caps.rss_table_entry_width) - 1));
12736 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12739 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12740 i40e_pf_disable_rss(pf);
12743 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12744 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12745 /* Random default keys */
12746 static uint32_t rss_key_default[] = {0x6b793944,
12747 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12748 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12749 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12751 rss_conf.rss_key = (uint8_t *)rss_key_default;
12752 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12755 "No valid RSS key config for i40e, using default\n");
12758 i40e_hw_rss_hash_set(pf, &rss_conf);
12760 if (i40e_rss_conf_init(rss_info, &conf->conf))
12766 RTE_INIT(i40e_init_log)
12768 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12769 if (i40e_logtype_init >= 0)
12770 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12771 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12772 if (i40e_logtype_driver >= 0)
12773 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12776 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12777 ETH_I40E_FLOATING_VEB_ARG "=1"
12778 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12779 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12780 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12781 ETH_I40E_USE_LATEST_VEC "=0|1");