4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
67 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
69 #define I40E_CLEAR_PXE_WAIT_MS 200
71 /* Maximun number of capability elements */
72 #define I40E_MAX_CAP_ELE_NUM 128
74 /* Wait count and inteval */
75 #define I40E_CHK_Q_ENA_COUNT 1000
76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
78 /* Maximun number of VSI */
79 #define I40E_MAX_NUM_VSIS (384UL)
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Flow control default timer */
84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
86 /* Flow control default high water */
87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
89 /* Flow control default low water */
90 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
92 /* Flow control enable fwd bit */
93 #define I40E_PRTMAC_FWD_CTRL 0x00000001
95 /* Receive Packet Buffer size */
96 #define I40E_RXPBSIZE (968 * 1024)
99 #define I40E_KILOSHIFT 10
101 /* Receive Average Packet Size in Byte*/
102 #define I40E_PACKET_AVERAGE_SIZE 128
104 /* Mask of PF interrupt causes */
105 #define I40E_PFINT_ICR0_ENA_MASK ( \
106 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
107 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_GRST_MASK | \
109 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
110 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
112 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
113 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
114 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
115 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
117 #define I40E_FLOW_TYPES ( \
118 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
123 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
128 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
130 /* Additional timesync values. */
131 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
132 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
133 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
134 #define I40E_PRTTSYN_TSYNENA 0x80000000
135 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
136 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
138 #define I40E_MAX_PERCENT 100
139 #define I40E_DEFAULT_DCB_APP_NUM 1
140 #define I40E_DEFAULT_DCB_APP_PRIO 3
142 #define I40E_INSET_NONE 0x00000000000000000ULL
145 #define I40E_INSET_DMAC 0x0000000000000001ULL
146 #define I40E_INSET_SMAC 0x0000000000000002ULL
147 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
148 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
149 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
152 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
153 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
154 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
155 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
156 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
157 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
158 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
160 /* bit 16 ~ bit 31 */
161 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
162 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
163 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
164 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
165 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
166 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
167 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
168 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
170 /* bit 32 ~ bit 47, tunnel fields */
171 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
172 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
173 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
174 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
175 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
176 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
178 /* bit 48 ~ bit 55 */
179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
181 /* bit 56 ~ bit 63, Flex Payload */
182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
190 #define I40E_INSET_FLEX_PAYLOAD \
191 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
192 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
193 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
194 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
197 * Below are values for writing un-exposed registers suggested
200 /* Destination MAC address */
201 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
202 /* Source MAC address */
203 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
205 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0200000000000000ULL
206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
207 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
208 /* Single VLAN tag in the inner L2 header */
209 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
210 /* Source IPv4 address */
211 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
212 /* Destination IPv4 address */
213 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
214 /* IPv4 Type of Service (TOS) */
215 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
217 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
218 /* IPv4 Time to Live */
219 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
220 /* Source IPv6 address */
221 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
222 /* Destination IPv6 address */
223 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
224 /* IPv6 Traffic Class (TC) */
225 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
226 /* IPv6 Next Header */
227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
231 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
232 /* Destination L4 port */
233 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
234 /* SCTP verification tag */
235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
238 /* Source port of tunneling UDP */
239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
240 /* Destination port of tunneling UDP */
241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
242 /* UDP Tunneling ID, NVGRE/GRE key */
243 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
244 /* Last ether type */
245 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
246 /* Tunneling outer destination IPv4 address */
247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
248 /* Tunneling outer destination IPv6 address */
249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
250 /* 1st word of flex payload */
251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
252 /* 2nd word of flex payload */
253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
254 /* 3rd word of flex payload */
255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
256 /* 4th word of flex payload */
257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
258 /* 5th word of flex payload */
259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
260 /* 6th word of flex payload */
261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
262 /* 7th word of flex payload */
263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
264 /* 8th word of flex payload */
265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
266 /* all 8 words flex payload */
267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
268 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
270 #define I40E_TRANSLATE_INSET 0
271 #define I40E_TRANSLATE_REG 1
273 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
274 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
275 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
276 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
278 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
280 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
283 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
285 /* PCI offset for querying capability */
286 #define PCI_DEV_CAP_REG 0xA4
287 /* PCI offset for enabling/disabling Extended Tag */
288 #define PCI_DEV_CTRL_REG 0xA8
289 /* Bit mask of Extended Tag capability */
290 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
291 /* Bit shift of Extended Tag enable/disable */
292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
293 /* Bit mask of Extended Tag enable/disable */
294 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
298 static int i40e_dev_configure(struct rte_eth_dev *dev);
299 static int i40e_dev_start(struct rte_eth_dev *dev);
300 static void i40e_dev_stop(struct rte_eth_dev *dev);
301 static void i40e_dev_close(struct rte_eth_dev *dev);
302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
309 struct rte_eth_stats *stats);
310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
311 struct rte_eth_xstat *xstats, unsigned n);
312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
313 struct rte_eth_xstat_name *xstats_names,
315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
321 struct rte_eth_dev_info *dev_info);
322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
326 enum rte_vlan_type vlan_type,
328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
336 struct rte_eth_fc_conf *fc_conf);
337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
338 struct rte_eth_fc_conf *fc_conf);
339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
340 struct rte_eth_pfc_conf *pfc_conf);
341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
342 struct ether_addr *mac_addr,
345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
347 struct rte_eth_rss_reta_entry64 *reta_conf,
349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
350 struct rte_eth_rss_reta_entry64 *reta_conf,
353 static int i40e_get_cap(struct i40e_hw *hw);
354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
355 static int i40e_pf_setup(struct i40e_pf *pf);
356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
361 bool offset_loaded, uint64_t *offset, uint64_t *stat);
362 static void i40e_stat_update_48(struct i40e_hw *hw,
368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
369 static void i40e_dev_interrupt_handler(
370 __rte_unused struct rte_intr_handle *handle, void *param);
371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
372 uint32_t base, uint32_t num);
373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
379 static int i40e_veb_release(struct i40e_veb *veb);
380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
381 struct i40e_vsi *vsi);
382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
385 struct i40e_macvlan_filter *mv_f,
387 struct ether_addr *addr);
388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
389 struct i40e_macvlan_filter *mv_f,
392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
394 struct rte_eth_rss_conf *rss_conf);
395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
396 struct rte_eth_rss_conf *rss_conf);
397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
398 struct rte_eth_udp_tunnel *udp_tunnel);
399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
400 struct rte_eth_udp_tunnel *udp_tunnel);
401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
403 struct rte_eth_ethertype_filter *filter,
405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
406 enum rte_filter_op filter_op,
408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
409 enum rte_filter_type filter_type,
410 enum rte_filter_op filter_op,
412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
413 struct rte_eth_dcb_info *dcb_info);
414 static void i40e_configure_registers(struct i40e_hw *hw);
415 static void i40e_hw_init(struct rte_eth_dev *dev);
416 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
417 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
418 struct rte_eth_mirror_conf *mirror_conf,
419 uint8_t sw_id, uint8_t on);
420 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
422 static int i40e_timesync_enable(struct rte_eth_dev *dev);
423 static int i40e_timesync_disable(struct rte_eth_dev *dev);
424 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
425 struct timespec *timestamp,
427 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
428 struct timespec *timestamp);
429 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
431 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
433 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
434 struct timespec *timestamp);
435 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
436 const struct timespec *timestamp);
438 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
440 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
443 static int i40e_get_regs(struct rte_eth_dev *dev,
444 struct rte_dev_reg_info *regs);
446 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
448 static int i40e_get_eeprom(struct rte_eth_dev *dev,
449 struct rte_dev_eeprom_info *eeprom);
451 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
452 struct ether_addr *mac_addr);
454 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
456 static const struct rte_pci_id pci_id_i40e_map[] = {
457 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
458 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
459 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
460 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
461 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
462 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
463 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
464 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
465 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
466 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
467 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
468 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
469 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
470 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
471 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
472 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
473 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
474 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
475 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
476 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
477 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_I_X722) },
478 { .vendor_id = 0, /* sentinel */ },
481 static const struct eth_dev_ops i40e_eth_dev_ops = {
482 .dev_configure = i40e_dev_configure,
483 .dev_start = i40e_dev_start,
484 .dev_stop = i40e_dev_stop,
485 .dev_close = i40e_dev_close,
486 .promiscuous_enable = i40e_dev_promiscuous_enable,
487 .promiscuous_disable = i40e_dev_promiscuous_disable,
488 .allmulticast_enable = i40e_dev_allmulticast_enable,
489 .allmulticast_disable = i40e_dev_allmulticast_disable,
490 .dev_set_link_up = i40e_dev_set_link_up,
491 .dev_set_link_down = i40e_dev_set_link_down,
492 .link_update = i40e_dev_link_update,
493 .stats_get = i40e_dev_stats_get,
494 .xstats_get = i40e_dev_xstats_get,
495 .xstats_get_names = i40e_dev_xstats_get_names,
496 .stats_reset = i40e_dev_stats_reset,
497 .xstats_reset = i40e_dev_stats_reset,
498 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
499 .dev_infos_get = i40e_dev_info_get,
500 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
501 .vlan_filter_set = i40e_vlan_filter_set,
502 .vlan_tpid_set = i40e_vlan_tpid_set,
503 .vlan_offload_set = i40e_vlan_offload_set,
504 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
505 .vlan_pvid_set = i40e_vlan_pvid_set,
506 .rx_queue_start = i40e_dev_rx_queue_start,
507 .rx_queue_stop = i40e_dev_rx_queue_stop,
508 .tx_queue_start = i40e_dev_tx_queue_start,
509 .tx_queue_stop = i40e_dev_tx_queue_stop,
510 .rx_queue_setup = i40e_dev_rx_queue_setup,
511 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
512 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
513 .rx_queue_release = i40e_dev_rx_queue_release,
514 .rx_queue_count = i40e_dev_rx_queue_count,
515 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
516 .tx_queue_setup = i40e_dev_tx_queue_setup,
517 .tx_queue_release = i40e_dev_tx_queue_release,
518 .dev_led_on = i40e_dev_led_on,
519 .dev_led_off = i40e_dev_led_off,
520 .flow_ctrl_get = i40e_flow_ctrl_get,
521 .flow_ctrl_set = i40e_flow_ctrl_set,
522 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
523 .mac_addr_add = i40e_macaddr_add,
524 .mac_addr_remove = i40e_macaddr_remove,
525 .reta_update = i40e_dev_rss_reta_update,
526 .reta_query = i40e_dev_rss_reta_query,
527 .rss_hash_update = i40e_dev_rss_hash_update,
528 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
529 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
530 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
531 .filter_ctrl = i40e_dev_filter_ctrl,
532 .rxq_info_get = i40e_rxq_info_get,
533 .txq_info_get = i40e_txq_info_get,
534 .mirror_rule_set = i40e_mirror_rule_set,
535 .mirror_rule_reset = i40e_mirror_rule_reset,
536 .timesync_enable = i40e_timesync_enable,
537 .timesync_disable = i40e_timesync_disable,
538 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
539 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
540 .get_dcb_info = i40e_dev_get_dcb_info,
541 .timesync_adjust_time = i40e_timesync_adjust_time,
542 .timesync_read_time = i40e_timesync_read_time,
543 .timesync_write_time = i40e_timesync_write_time,
544 .get_reg = i40e_get_regs,
545 .get_eeprom_length = i40e_get_eeprom_length,
546 .get_eeprom = i40e_get_eeprom,
547 .mac_addr_set = i40e_set_default_mac_addr,
548 .mtu_set = i40e_dev_mtu_set,
551 /* store statistics names and its offset in stats structure */
552 struct rte_i40e_xstats_name_off {
553 char name[RTE_ETH_XSTATS_NAME_SIZE];
557 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
558 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
559 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
560 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
561 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
562 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
563 rx_unknown_protocol)},
564 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
565 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
566 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
567 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
570 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
571 sizeof(rte_i40e_stats_strings[0]))
573 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
574 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
575 tx_dropped_link_down)},
576 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
577 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
579 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
580 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
582 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
584 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
586 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
587 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
588 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
589 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
590 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
591 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
593 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
595 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
597 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
599 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
601 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
603 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
605 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
607 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
608 mac_short_packet_dropped)},
609 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
611 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
612 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
613 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
615 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
617 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
619 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
621 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
623 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
625 {"rx_flow_director_atr_match_packets",
626 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
627 {"rx_flow_director_sb_match_packets",
628 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
629 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
631 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
633 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
635 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
639 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
640 sizeof(rte_i40e_hw_port_strings[0]))
642 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
643 {"xon_packets", offsetof(struct i40e_hw_port_stats,
645 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
649 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
650 sizeof(rte_i40e_rxq_prio_strings[0]))
652 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
653 {"xon_packets", offsetof(struct i40e_hw_port_stats,
655 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
657 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
658 priority_xon_2_xoff)},
661 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
662 sizeof(rte_i40e_txq_prio_strings[0]))
664 static struct eth_driver rte_i40e_pmd = {
666 .id_table = pci_id_i40e_map,
667 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
668 RTE_PCI_DRV_DETACHABLE,
669 .probe = rte_eth_dev_pci_probe,
670 .remove = rte_eth_dev_pci_remove,
672 .eth_dev_init = eth_i40e_dev_init,
673 .eth_dev_uninit = eth_i40e_dev_uninit,
674 .dev_private_size = sizeof(struct i40e_adapter),
678 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
679 struct rte_eth_link *link)
681 struct rte_eth_link *dst = link;
682 struct rte_eth_link *src = &(dev->data->dev_link);
684 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
685 *(uint64_t *)src) == 0)
692 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
693 struct rte_eth_link *link)
695 struct rte_eth_link *dst = &(dev->data->dev_link);
696 struct rte_eth_link *src = link;
698 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
699 *(uint64_t *)src) == 0)
705 DRIVER_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
706 DRIVER_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
709 * Initialize registers for flexible payload, which should be set by NVM.
710 * This should be removed from code once it is fixed in NVM.
712 #ifndef I40E_GLQF_ORT
713 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
715 #ifndef I40E_GLQF_PIT
716 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
719 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
721 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
722 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
723 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
724 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
725 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
726 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
727 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
728 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
729 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
730 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
732 /* GLQF_PIT Registers */
733 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
734 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
737 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
740 * Add a ethertype filter to drop all flow control frames transmitted
744 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
746 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
747 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
748 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
749 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
752 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
753 I40E_FLOW_CONTROL_ETHERTYPE, flags,
754 pf->main_vsi_seid, 0,
757 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
758 " frames from VSIs.");
762 floating_veb_list_handler(__rte_unused const char *key,
763 const char *floating_veb_value,
767 unsigned int count = 0;
770 bool *vf_floating_veb = opaque;
772 while (isblank(*floating_veb_value))
773 floating_veb_value++;
775 /* Reset floating VEB configuration for VFs */
776 for (idx = 0; idx < I40E_MAX_VF; idx++)
777 vf_floating_veb[idx] = false;
781 while (isblank(*floating_veb_value))
782 floating_veb_value++;
783 if (*floating_veb_value == '\0')
786 idx = strtoul(floating_veb_value, &end, 10);
787 if (errno || end == NULL)
789 while (isblank(*end))
793 } else if ((*end == ';') || (*end == '\0')) {
795 if (min == I40E_MAX_VF)
797 if (max >= I40E_MAX_VF)
798 max = I40E_MAX_VF - 1;
799 for (idx = min; idx <= max; idx++) {
800 vf_floating_veb[idx] = true;
807 floating_veb_value = end + 1;
808 } while (*end != '\0');
817 config_vf_floating_veb(struct rte_devargs *devargs,
818 uint16_t floating_veb,
819 bool *vf_floating_veb)
821 struct rte_kvargs *kvlist;
823 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
827 /* All the VFs attach to the floating VEB by default
828 * when the floating VEB is enabled.
830 for (i = 0; i < I40E_MAX_VF; i++)
831 vf_floating_veb[i] = true;
836 kvlist = rte_kvargs_parse(devargs->args, NULL);
840 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
841 rte_kvargs_free(kvlist);
844 /* When the floating_veb_list parameter exists, all the VFs
845 * will attach to the legacy VEB firstly, then configure VFs
846 * to the floating VEB according to the floating_veb_list.
848 if (rte_kvargs_process(kvlist, floating_veb_list,
849 floating_veb_list_handler,
850 vf_floating_veb) < 0) {
851 rte_kvargs_free(kvlist);
854 rte_kvargs_free(kvlist);
858 i40e_check_floating_handler(__rte_unused const char *key,
860 __rte_unused void *opaque)
862 if (strcmp(value, "1"))
869 is_floating_veb_supported(struct rte_devargs *devargs)
871 struct rte_kvargs *kvlist;
872 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
877 kvlist = rte_kvargs_parse(devargs->args, NULL);
881 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
882 rte_kvargs_free(kvlist);
885 /* Floating VEB is enabled when there's key-value:
886 * enable_floating_veb=1
888 if (rte_kvargs_process(kvlist, floating_veb_key,
889 i40e_check_floating_handler, NULL) < 0) {
890 rte_kvargs_free(kvlist);
893 rte_kvargs_free(kvlist);
899 config_floating_veb(struct rte_eth_dev *dev)
901 struct rte_pci_device *pci_dev = dev->pci_dev;
902 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
903 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
905 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
907 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
909 is_floating_veb_supported(pci_dev->device.devargs);
910 config_vf_floating_veb(pci_dev->device.devargs,
912 pf->floating_veb_list);
914 pf->floating_veb = false;
918 #define I40E_L2_TAGS_S_TAG_SHIFT 1
919 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
922 eth_i40e_dev_init(struct rte_eth_dev *dev)
924 struct rte_pci_device *pci_dev;
925 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
926 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
927 struct i40e_vsi *vsi;
932 PMD_INIT_FUNC_TRACE();
934 dev->dev_ops = &i40e_eth_dev_ops;
935 dev->rx_pkt_burst = i40e_recv_pkts;
936 dev->tx_pkt_burst = i40e_xmit_pkts;
938 /* for secondary processes, we don't initialise any further as primary
939 * has already done this work. Only check we don't need a different
941 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
942 i40e_set_rx_function(dev);
943 i40e_set_tx_function(dev);
946 pci_dev = dev->pci_dev;
948 rte_eth_copy_pci_info(dev, pci_dev);
950 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
951 pf->adapter->eth_dev = dev;
952 pf->dev_data = dev->data;
954 hw->back = I40E_PF_TO_ADAPTER(pf);
955 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
957 PMD_INIT_LOG(ERR, "Hardware is not available, "
958 "as address is NULL");
962 hw->vendor_id = pci_dev->id.vendor_id;
963 hw->device_id = pci_dev->id.device_id;
964 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
965 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
966 hw->bus.device = pci_dev->addr.devid;
967 hw->bus.func = pci_dev->addr.function;
968 hw->adapter_stopped = 0;
970 /* Make sure all is clean before doing PF reset */
973 /* Initialize the hardware */
976 /* Reset here to make sure all is clean for each PF */
977 ret = i40e_pf_reset(hw);
979 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
983 /* Initialize the shared code (base driver) */
984 ret = i40e_init_shared_code(hw);
986 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
991 * To work around the NVM issue,initialize registers
992 * for flexible payload by software.
993 * It should be removed once issues are fixed in NVM.
995 i40e_flex_payload_reg_init(hw);
997 /* Initialize the input set for filters (hash and fd) to default value */
998 i40e_filter_input_set_init(pf);
1000 /* Initialize the parameters for adminq */
1001 i40e_init_adminq_parameter(hw);
1002 ret = i40e_init_adminq(hw);
1003 if (ret != I40E_SUCCESS) {
1004 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1007 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1008 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1009 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1010 ((hw->nvm.version >> 12) & 0xf),
1011 ((hw->nvm.version >> 4) & 0xff),
1012 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1014 /* Need the special FW version to support floating VEB */
1015 config_floating_veb(dev);
1016 /* Clear PXE mode */
1017 i40e_clear_pxe_mode(hw);
1020 * On X710, performance number is far from the expectation on recent
1021 * firmware versions. The fix for this issue may not be integrated in
1022 * the following firmware version. So the workaround in software driver
1023 * is needed. It needs to modify the initial values of 3 internal only
1024 * registers. Note that the workaround can be removed when it is fixed
1025 * in firmware in the future.
1027 i40e_configure_registers(hw);
1029 /* Get hw capabilities */
1030 ret = i40e_get_cap(hw);
1031 if (ret != I40E_SUCCESS) {
1032 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1033 goto err_get_capabilities;
1036 /* Initialize parameters for PF */
1037 ret = i40e_pf_parameter_init(dev);
1039 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1040 goto err_parameter_init;
1043 /* Initialize the queue management */
1044 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1046 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1047 goto err_qp_pool_init;
1049 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1050 hw->func_caps.num_msix_vectors - 1);
1052 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1053 goto err_msix_pool_init;
1056 /* Initialize lan hmc */
1057 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1058 hw->func_caps.num_rx_qp, 0, 0);
1059 if (ret != I40E_SUCCESS) {
1060 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1061 goto err_init_lan_hmc;
1064 /* Configure lan hmc */
1065 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1066 if (ret != I40E_SUCCESS) {
1067 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1068 goto err_configure_lan_hmc;
1071 /* Get and check the mac address */
1072 i40e_get_mac_addr(hw, hw->mac.addr);
1073 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1074 PMD_INIT_LOG(ERR, "mac address is not valid");
1076 goto err_get_mac_addr;
1078 /* Copy the permanent MAC address */
1079 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1080 (struct ether_addr *) hw->mac.perm_addr);
1082 /* Disable flow control */
1083 hw->fc.requested_mode = I40E_FC_NONE;
1084 i40e_set_fc(hw, &aq_fail, TRUE);
1086 /* Set the global registers with default ether type value */
1087 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1088 if (ret != I40E_SUCCESS) {
1089 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1091 goto err_setup_pf_switch;
1094 /* PF setup, which includes VSI setup */
1095 ret = i40e_pf_setup(pf);
1097 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1098 goto err_setup_pf_switch;
1101 /* reset all stats of the device, including pf and main vsi */
1102 i40e_dev_stats_reset(dev);
1106 /* Disable double vlan by default */
1107 i40e_vsi_config_double_vlan(vsi, FALSE);
1109 /* Disable S-TAG identification by default */
1110 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1111 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1112 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1113 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1116 if (!vsi->max_macaddrs)
1117 len = ETHER_ADDR_LEN;
1119 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1121 /* Should be after VSI initialized */
1122 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1123 if (!dev->data->mac_addrs) {
1124 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1125 "for storing mac address");
1128 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1129 &dev->data->mac_addrs[0]);
1131 /* initialize pf host driver to setup SRIOV resource if applicable */
1132 i40e_pf_host_init(dev);
1134 /* register callback func to eal lib */
1135 rte_intr_callback_register(&(pci_dev->intr_handle),
1136 i40e_dev_interrupt_handler, (void *)dev);
1138 /* configure and enable device interrupt */
1139 i40e_pf_config_irq0(hw, TRUE);
1140 i40e_pf_enable_irq0(hw);
1142 /* enable uio intr after callback register */
1143 rte_intr_enable(&(pci_dev->intr_handle));
1145 * Add an ethertype filter to drop all flow control frames transmitted
1146 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1149 i40e_add_tx_flow_control_drop_filter(pf);
1151 /* Set the max frame size to 0x2600 by default,
1152 * in case other drivers changed the default value.
1154 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1156 /* initialize mirror rule list */
1157 TAILQ_INIT(&pf->mirror_list);
1159 /* Init dcb to sw mode by default */
1160 ret = i40e_dcb_init_configure(dev, TRUE);
1161 if (ret != I40E_SUCCESS) {
1162 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1163 pf->flags &= ~I40E_FLAG_DCB;
1169 i40e_vsi_release(pf->main_vsi);
1170 err_setup_pf_switch:
1172 err_configure_lan_hmc:
1173 (void)i40e_shutdown_lan_hmc(hw);
1175 i40e_res_pool_destroy(&pf->msix_pool);
1177 i40e_res_pool_destroy(&pf->qp_pool);
1180 err_get_capabilities:
1181 (void)i40e_shutdown_adminq(hw);
1187 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1189 struct rte_pci_device *pci_dev;
1191 struct i40e_filter_control_settings settings;
1193 uint8_t aq_fail = 0;
1195 PMD_INIT_FUNC_TRACE();
1197 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1200 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1201 pci_dev = dev->pci_dev;
1203 if (hw->adapter_stopped == 0)
1204 i40e_dev_close(dev);
1206 dev->dev_ops = NULL;
1207 dev->rx_pkt_burst = NULL;
1208 dev->tx_pkt_burst = NULL;
1211 ret = i40e_aq_stop_lldp(hw, true, NULL);
1212 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1213 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1215 /* Clear PXE mode */
1216 i40e_clear_pxe_mode(hw);
1218 /* Unconfigure filter control */
1219 memset(&settings, 0, sizeof(settings));
1220 ret = i40e_set_filter_control(hw, &settings);
1222 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1225 /* Disable flow control */
1226 hw->fc.requested_mode = I40E_FC_NONE;
1227 i40e_set_fc(hw, &aq_fail, TRUE);
1229 /* uninitialize pf host driver */
1230 i40e_pf_host_uninit(dev);
1232 rte_free(dev->data->mac_addrs);
1233 dev->data->mac_addrs = NULL;
1235 /* disable uio intr before callback unregister */
1236 rte_intr_disable(&(pci_dev->intr_handle));
1238 /* register callback func to eal lib */
1239 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1240 i40e_dev_interrupt_handler, (void *)dev);
1246 i40e_dev_configure(struct rte_eth_dev *dev)
1248 struct i40e_adapter *ad =
1249 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1250 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1251 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1254 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1255 * bulk allocation or vector Rx preconditions we will reset it.
1257 ad->rx_bulk_alloc_allowed = true;
1258 ad->rx_vec_allowed = true;
1259 ad->tx_simple_allowed = true;
1260 ad->tx_vec_allowed = true;
1262 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1263 ret = i40e_fdir_setup(pf);
1264 if (ret != I40E_SUCCESS) {
1265 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1268 ret = i40e_fdir_configure(dev);
1270 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1274 i40e_fdir_teardown(pf);
1276 ret = i40e_dev_init_vlan(dev);
1281 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1282 * RSS setting have different requirements.
1283 * General PMD driver call sequence are NIC init, configure,
1284 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1285 * will try to lookup the VSI that specific queue belongs to if VMDQ
1286 * applicable. So, VMDQ setting has to be done before
1287 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1288 * For RSS setting, it will try to calculate actual configured RX queue
1289 * number, which will be available after rx_queue_setup(). dev_start()
1290 * function is good to place RSS setup.
1292 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1293 ret = i40e_vmdq_setup(dev);
1298 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1299 ret = i40e_dcb_setup(dev);
1301 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1309 /* need to release vmdq resource if exists */
1310 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1311 i40e_vsi_release(pf->vmdq[i].vsi);
1312 pf->vmdq[i].vsi = NULL;
1317 /* need to release fdir resource if exists */
1318 i40e_fdir_teardown(pf);
1323 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1325 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1326 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1327 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1328 uint16_t msix_vect = vsi->msix_intr;
1331 for (i = 0; i < vsi->nb_qps; i++) {
1332 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1333 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1337 if (vsi->type != I40E_VSI_SRIOV) {
1338 if (!rte_intr_allow_others(intr_handle)) {
1339 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1340 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1342 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1345 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1346 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1348 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1353 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1354 vsi->user_param + (msix_vect - 1);
1356 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1357 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1359 I40E_WRITE_FLUSH(hw);
1363 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1364 int base_queue, int nb_queue)
1368 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1370 /* Bind all RX queues to allocated MSIX interrupt */
1371 for (i = 0; i < nb_queue; i++) {
1372 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1373 I40E_QINT_RQCTL_ITR_INDX_MASK |
1374 ((base_queue + i + 1) <<
1375 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1376 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1377 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1379 if (i == nb_queue - 1)
1380 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1381 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1384 /* Write first RX queue to Link list register as the head element */
1385 if (vsi->type != I40E_VSI_SRIOV) {
1387 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1389 if (msix_vect == I40E_MISC_VEC_ID) {
1390 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1392 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1394 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1396 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1399 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1401 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1403 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1405 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1412 if (msix_vect == I40E_MISC_VEC_ID) {
1414 I40E_VPINT_LNKLST0(vsi->user_param),
1416 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1418 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1420 /* num_msix_vectors_vf needs to minus irq0 */
1421 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1422 vsi->user_param + (msix_vect - 1);
1424 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1426 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1428 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1432 I40E_WRITE_FLUSH(hw);
1436 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1438 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1439 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1440 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1441 uint16_t msix_vect = vsi->msix_intr;
1442 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1443 uint16_t queue_idx = 0;
1448 for (i = 0; i < vsi->nb_qps; i++) {
1449 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1450 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1453 /* INTENA flag is not auto-cleared for interrupt */
1454 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1455 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1456 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1457 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1458 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1460 /* VF bind interrupt */
1461 if (vsi->type == I40E_VSI_SRIOV) {
1462 __vsi_queues_bind_intr(vsi, msix_vect,
1463 vsi->base_queue, vsi->nb_qps);
1467 /* PF & VMDq bind interrupt */
1468 if (rte_intr_dp_is_en(intr_handle)) {
1469 if (vsi->type == I40E_VSI_MAIN) {
1472 } else if (vsi->type == I40E_VSI_VMDQ2) {
1473 struct i40e_vsi *main_vsi =
1474 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1475 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1480 for (i = 0; i < vsi->nb_used_qps; i++) {
1482 if (!rte_intr_allow_others(intr_handle))
1483 /* allow to share MISC_VEC_ID */
1484 msix_vect = I40E_MISC_VEC_ID;
1486 /* no enough msix_vect, map all to one */
1487 __vsi_queues_bind_intr(vsi, msix_vect,
1488 vsi->base_queue + i,
1489 vsi->nb_used_qps - i);
1490 for (; !!record && i < vsi->nb_used_qps; i++)
1491 intr_handle->intr_vec[queue_idx + i] =
1495 /* 1:1 queue/msix_vect mapping */
1496 __vsi_queues_bind_intr(vsi, msix_vect,
1497 vsi->base_queue + i, 1);
1499 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1507 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1509 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1510 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1511 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1512 uint16_t interval = i40e_calc_itr_interval(\
1513 RTE_LIBRTE_I40E_ITR_INTERVAL);
1514 uint16_t msix_intr, i;
1516 if (rte_intr_allow_others(intr_handle))
1517 for (i = 0; i < vsi->nb_msix; i++) {
1518 msix_intr = vsi->msix_intr + i;
1519 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1520 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1521 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1522 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1524 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1527 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1528 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1529 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1530 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1532 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1534 I40E_WRITE_FLUSH(hw);
1538 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1540 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1541 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1542 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1543 uint16_t msix_intr, i;
1545 if (rte_intr_allow_others(intr_handle))
1546 for (i = 0; i < vsi->nb_msix; i++) {
1547 msix_intr = vsi->msix_intr + i;
1548 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1552 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1554 I40E_WRITE_FLUSH(hw);
1557 static inline uint8_t
1558 i40e_parse_link_speeds(uint16_t link_speeds)
1560 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1562 if (link_speeds & ETH_LINK_SPEED_40G)
1563 link_speed |= I40E_LINK_SPEED_40GB;
1564 if (link_speeds & ETH_LINK_SPEED_20G)
1565 link_speed |= I40E_LINK_SPEED_20GB;
1566 if (link_speeds & ETH_LINK_SPEED_10G)
1567 link_speed |= I40E_LINK_SPEED_10GB;
1568 if (link_speeds & ETH_LINK_SPEED_1G)
1569 link_speed |= I40E_LINK_SPEED_1GB;
1570 if (link_speeds & ETH_LINK_SPEED_100M)
1571 link_speed |= I40E_LINK_SPEED_100MB;
1577 i40e_phy_conf_link(struct i40e_hw *hw,
1579 uint8_t force_speed)
1581 enum i40e_status_code status;
1582 struct i40e_aq_get_phy_abilities_resp phy_ab;
1583 struct i40e_aq_set_phy_config phy_conf;
1584 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1585 I40E_AQ_PHY_FLAG_PAUSE_RX |
1586 I40E_AQ_PHY_FLAG_PAUSE_RX |
1587 I40E_AQ_PHY_FLAG_LOW_POWER;
1588 const uint8_t advt = I40E_LINK_SPEED_40GB |
1589 I40E_LINK_SPEED_10GB |
1590 I40E_LINK_SPEED_1GB |
1591 I40E_LINK_SPEED_100MB;
1595 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1600 memset(&phy_conf, 0, sizeof(phy_conf));
1602 /* bits 0-2 use the values from get_phy_abilities_resp */
1604 abilities |= phy_ab.abilities & mask;
1606 /* update ablities and speed */
1607 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1608 phy_conf.link_speed = advt;
1610 phy_conf.link_speed = force_speed;
1612 phy_conf.abilities = abilities;
1614 /* use get_phy_abilities_resp value for the rest */
1615 phy_conf.phy_type = phy_ab.phy_type;
1616 phy_conf.eee_capability = phy_ab.eee_capability;
1617 phy_conf.eeer = phy_ab.eeer_val;
1618 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1620 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1621 phy_ab.abilities, phy_ab.link_speed);
1622 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1623 phy_conf.abilities, phy_conf.link_speed);
1625 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1629 return I40E_SUCCESS;
1633 i40e_apply_link_speed(struct rte_eth_dev *dev)
1636 uint8_t abilities = 0;
1637 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638 struct rte_eth_conf *conf = &dev->data->dev_conf;
1640 speed = i40e_parse_link_speeds(conf->link_speeds);
1641 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1642 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1643 abilities |= I40E_AQ_PHY_AN_ENABLED;
1644 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1646 /* Skip changing speed on 40G interfaces, FW does not support */
1647 if (i40e_is_40G_device(hw->device_id)) {
1648 speed = I40E_LINK_SPEED_UNKNOWN;
1649 abilities |= I40E_AQ_PHY_AN_ENABLED;
1652 return i40e_phy_conf_link(hw, abilities, speed);
1656 i40e_dev_start(struct rte_eth_dev *dev)
1658 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1659 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660 struct i40e_vsi *main_vsi = pf->main_vsi;
1662 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1663 uint32_t intr_vector = 0;
1665 hw->adapter_stopped = 0;
1667 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1668 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1669 dev->data->port_id);
1673 rte_intr_disable(intr_handle);
1675 if ((rte_intr_cap_multiple(intr_handle) ||
1676 !RTE_ETH_DEV_SRIOV(dev).active) &&
1677 dev->data->dev_conf.intr_conf.rxq != 0) {
1678 intr_vector = dev->data->nb_rx_queues;
1679 if (rte_intr_efd_enable(intr_handle, intr_vector))
1683 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1684 intr_handle->intr_vec =
1685 rte_zmalloc("intr_vec",
1686 dev->data->nb_rx_queues * sizeof(int),
1688 if (!intr_handle->intr_vec) {
1689 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1690 " intr_vec\n", dev->data->nb_rx_queues);
1695 /* Initialize VSI */
1696 ret = i40e_dev_rxtx_init(pf);
1697 if (ret != I40E_SUCCESS) {
1698 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1702 /* Map queues with MSIX interrupt */
1703 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1704 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1705 i40e_vsi_queues_bind_intr(main_vsi);
1706 i40e_vsi_enable_queues_intr(main_vsi);
1708 /* Map VMDQ VSI queues with MSIX interrupt */
1709 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1710 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1711 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1712 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1715 /* enable FDIR MSIX interrupt */
1716 if (pf->fdir.fdir_vsi) {
1717 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1718 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1721 /* Enable all queues which have been configured */
1722 ret = i40e_dev_switch_queues(pf, TRUE);
1723 if (ret != I40E_SUCCESS) {
1724 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1728 /* Enable receiving broadcast packets */
1729 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1730 if (ret != I40E_SUCCESS)
1731 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1733 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1734 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1736 if (ret != I40E_SUCCESS)
1737 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1740 /* Apply link configure */
1741 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1742 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1743 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1744 PMD_DRV_LOG(ERR, "Invalid link setting");
1747 ret = i40e_apply_link_speed(dev);
1748 if (I40E_SUCCESS != ret) {
1749 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1753 if (!rte_intr_allow_others(intr_handle)) {
1754 rte_intr_callback_unregister(intr_handle,
1755 i40e_dev_interrupt_handler,
1757 /* configure and enable device interrupt */
1758 i40e_pf_config_irq0(hw, FALSE);
1759 i40e_pf_enable_irq0(hw);
1761 if (dev->data->dev_conf.intr_conf.lsc != 0)
1762 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1763 " no intr multiplex\n");
1766 /* enable uio intr after callback register */
1767 rte_intr_enable(intr_handle);
1769 return I40E_SUCCESS;
1772 i40e_dev_switch_queues(pf, FALSE);
1773 i40e_dev_clear_queues(dev);
1779 i40e_dev_stop(struct rte_eth_dev *dev)
1781 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1782 struct i40e_vsi *main_vsi = pf->main_vsi;
1783 struct i40e_mirror_rule *p_mirror;
1784 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1787 /* Disable all queues */
1788 i40e_dev_switch_queues(pf, FALSE);
1790 /* un-map queues with interrupt registers */
1791 i40e_vsi_disable_queues_intr(main_vsi);
1792 i40e_vsi_queues_unbind_intr(main_vsi);
1794 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1795 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1796 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1799 if (pf->fdir.fdir_vsi) {
1800 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1801 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1803 /* Clear all queues and release memory */
1804 i40e_dev_clear_queues(dev);
1807 i40e_dev_set_link_down(dev);
1809 /* Remove all mirror rules */
1810 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1811 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1814 pf->nb_mirror_rule = 0;
1816 if (!rte_intr_allow_others(intr_handle))
1817 /* resume to the default handler */
1818 rte_intr_callback_register(intr_handle,
1819 i40e_dev_interrupt_handler,
1822 /* Clean datapath event and queue/vec mapping */
1823 rte_intr_efd_disable(intr_handle);
1824 if (intr_handle->intr_vec) {
1825 rte_free(intr_handle->intr_vec);
1826 intr_handle->intr_vec = NULL;
1831 i40e_dev_close(struct rte_eth_dev *dev)
1833 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1834 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1838 PMD_INIT_FUNC_TRACE();
1841 hw->adapter_stopped = 1;
1842 i40e_dev_free_queues(dev);
1844 /* Disable interrupt */
1845 i40e_pf_disable_irq0(hw);
1846 rte_intr_disable(&(dev->pci_dev->intr_handle));
1848 /* shutdown and destroy the HMC */
1849 i40e_shutdown_lan_hmc(hw);
1851 /* release all the existing VSIs and VEBs */
1852 i40e_fdir_teardown(pf);
1853 i40e_vsi_release(pf->main_vsi);
1855 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1856 i40e_vsi_release(pf->vmdq[i].vsi);
1857 pf->vmdq[i].vsi = NULL;
1863 /* shutdown the adminq */
1864 i40e_aq_queue_shutdown(hw, true);
1865 i40e_shutdown_adminq(hw);
1867 i40e_res_pool_destroy(&pf->qp_pool);
1868 i40e_res_pool_destroy(&pf->msix_pool);
1870 /* force a PF reset to clean anything leftover */
1871 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1872 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1873 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1874 I40E_WRITE_FLUSH(hw);
1878 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1880 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1881 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1882 struct i40e_vsi *vsi = pf->main_vsi;
1885 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1887 if (status != I40E_SUCCESS)
1888 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1890 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1892 if (status != I40E_SUCCESS)
1893 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1898 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1900 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1901 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1902 struct i40e_vsi *vsi = pf->main_vsi;
1905 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1907 if (status != I40E_SUCCESS)
1908 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1910 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1912 if (status != I40E_SUCCESS)
1913 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1917 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1919 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1920 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1921 struct i40e_vsi *vsi = pf->main_vsi;
1924 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1925 if (ret != I40E_SUCCESS)
1926 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1930 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1932 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1933 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1934 struct i40e_vsi *vsi = pf->main_vsi;
1937 if (dev->data->promiscuous == 1)
1938 return; /* must remain in all_multicast mode */
1940 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1941 vsi->seid, FALSE, NULL);
1942 if (ret != I40E_SUCCESS)
1943 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1947 * Set device link up.
1950 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1952 /* re-apply link speed setting */
1953 return i40e_apply_link_speed(dev);
1957 * Set device link down.
1960 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1962 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1963 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1964 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1966 return i40e_phy_conf_link(hw, abilities, speed);
1970 i40e_dev_link_update(struct rte_eth_dev *dev,
1971 int wait_to_complete)
1973 #define CHECK_INTERVAL 100 /* 100ms */
1974 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1975 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1976 struct i40e_link_status link_status;
1977 struct rte_eth_link link, old;
1979 unsigned rep_cnt = MAX_REPEAT_TIME;
1981 memset(&link, 0, sizeof(link));
1982 memset(&old, 0, sizeof(old));
1983 memset(&link_status, 0, sizeof(link_status));
1984 rte_i40e_dev_atomic_read_link_status(dev, &old);
1987 /* Get link status information from hardware */
1988 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1989 if (status != I40E_SUCCESS) {
1990 link.link_speed = ETH_SPEED_NUM_100M;
1991 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1992 PMD_DRV_LOG(ERR, "Failed to get link info");
1996 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1997 if (!wait_to_complete)
2000 rte_delay_ms(CHECK_INTERVAL);
2001 } while (!link.link_status && rep_cnt--);
2003 if (!link.link_status)
2006 /* i40e uses full duplex only */
2007 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2009 /* Parse the link status */
2010 switch (link_status.link_speed) {
2011 case I40E_LINK_SPEED_100MB:
2012 link.link_speed = ETH_SPEED_NUM_100M;
2014 case I40E_LINK_SPEED_1GB:
2015 link.link_speed = ETH_SPEED_NUM_1G;
2017 case I40E_LINK_SPEED_10GB:
2018 link.link_speed = ETH_SPEED_NUM_10G;
2020 case I40E_LINK_SPEED_20GB:
2021 link.link_speed = ETH_SPEED_NUM_20G;
2023 case I40E_LINK_SPEED_40GB:
2024 link.link_speed = ETH_SPEED_NUM_40G;
2027 link.link_speed = ETH_SPEED_NUM_100M;
2031 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2032 ETH_LINK_SPEED_FIXED);
2035 rte_i40e_dev_atomic_write_link_status(dev, &link);
2036 if (link.link_status == old.link_status)
2042 /* Get all the statistics of a VSI */
2044 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2046 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2047 struct i40e_eth_stats *nes = &vsi->eth_stats;
2048 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2049 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2051 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2052 vsi->offset_loaded, &oes->rx_bytes,
2054 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2055 vsi->offset_loaded, &oes->rx_unicast,
2057 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2058 vsi->offset_loaded, &oes->rx_multicast,
2059 &nes->rx_multicast);
2060 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2061 vsi->offset_loaded, &oes->rx_broadcast,
2062 &nes->rx_broadcast);
2063 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2064 &oes->rx_discards, &nes->rx_discards);
2065 /* GLV_REPC not supported */
2066 /* GLV_RMPC not supported */
2067 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2068 &oes->rx_unknown_protocol,
2069 &nes->rx_unknown_protocol);
2070 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2071 vsi->offset_loaded, &oes->tx_bytes,
2073 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2074 vsi->offset_loaded, &oes->tx_unicast,
2076 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2077 vsi->offset_loaded, &oes->tx_multicast,
2078 &nes->tx_multicast);
2079 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2080 vsi->offset_loaded, &oes->tx_broadcast,
2081 &nes->tx_broadcast);
2082 /* GLV_TDPC not supported */
2083 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2084 &oes->tx_errors, &nes->tx_errors);
2085 vsi->offset_loaded = true;
2087 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2089 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2090 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2091 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2092 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2093 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2094 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2095 nes->rx_unknown_protocol);
2096 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2097 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2098 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2099 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2100 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2101 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2102 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2107 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2110 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2111 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2113 /* Get statistics of struct i40e_eth_stats */
2114 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2115 I40E_GLPRT_GORCL(hw->port),
2116 pf->offset_loaded, &os->eth.rx_bytes,
2118 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2119 I40E_GLPRT_UPRCL(hw->port),
2120 pf->offset_loaded, &os->eth.rx_unicast,
2121 &ns->eth.rx_unicast);
2122 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2123 I40E_GLPRT_MPRCL(hw->port),
2124 pf->offset_loaded, &os->eth.rx_multicast,
2125 &ns->eth.rx_multicast);
2126 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2127 I40E_GLPRT_BPRCL(hw->port),
2128 pf->offset_loaded, &os->eth.rx_broadcast,
2129 &ns->eth.rx_broadcast);
2130 /* Workaround: CRC size should not be included in byte statistics,
2131 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2133 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2134 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2136 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2137 pf->offset_loaded, &os->eth.rx_discards,
2138 &ns->eth.rx_discards);
2139 /* GLPRT_REPC not supported */
2140 /* GLPRT_RMPC not supported */
2141 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2143 &os->eth.rx_unknown_protocol,
2144 &ns->eth.rx_unknown_protocol);
2145 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2146 I40E_GLPRT_GOTCL(hw->port),
2147 pf->offset_loaded, &os->eth.tx_bytes,
2149 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2150 I40E_GLPRT_UPTCL(hw->port),
2151 pf->offset_loaded, &os->eth.tx_unicast,
2152 &ns->eth.tx_unicast);
2153 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2154 I40E_GLPRT_MPTCL(hw->port),
2155 pf->offset_loaded, &os->eth.tx_multicast,
2156 &ns->eth.tx_multicast);
2157 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2158 I40E_GLPRT_BPTCL(hw->port),
2159 pf->offset_loaded, &os->eth.tx_broadcast,
2160 &ns->eth.tx_broadcast);
2161 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2162 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2163 /* GLPRT_TEPC not supported */
2165 /* additional port specific stats */
2166 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2167 pf->offset_loaded, &os->tx_dropped_link_down,
2168 &ns->tx_dropped_link_down);
2169 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2170 pf->offset_loaded, &os->crc_errors,
2172 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2173 pf->offset_loaded, &os->illegal_bytes,
2174 &ns->illegal_bytes);
2175 /* GLPRT_ERRBC not supported */
2176 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2177 pf->offset_loaded, &os->mac_local_faults,
2178 &ns->mac_local_faults);
2179 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2180 pf->offset_loaded, &os->mac_remote_faults,
2181 &ns->mac_remote_faults);
2182 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2183 pf->offset_loaded, &os->rx_length_errors,
2184 &ns->rx_length_errors);
2185 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2186 pf->offset_loaded, &os->link_xon_rx,
2188 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2189 pf->offset_loaded, &os->link_xoff_rx,
2191 for (i = 0; i < 8; i++) {
2192 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2194 &os->priority_xon_rx[i],
2195 &ns->priority_xon_rx[i]);
2196 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2198 &os->priority_xoff_rx[i],
2199 &ns->priority_xoff_rx[i]);
2201 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2202 pf->offset_loaded, &os->link_xon_tx,
2204 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2205 pf->offset_loaded, &os->link_xoff_tx,
2207 for (i = 0; i < 8; i++) {
2208 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2210 &os->priority_xon_tx[i],
2211 &ns->priority_xon_tx[i]);
2212 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2214 &os->priority_xoff_tx[i],
2215 &ns->priority_xoff_tx[i]);
2216 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2218 &os->priority_xon_2_xoff[i],
2219 &ns->priority_xon_2_xoff[i]);
2221 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2222 I40E_GLPRT_PRC64L(hw->port),
2223 pf->offset_loaded, &os->rx_size_64,
2225 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2226 I40E_GLPRT_PRC127L(hw->port),
2227 pf->offset_loaded, &os->rx_size_127,
2229 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2230 I40E_GLPRT_PRC255L(hw->port),
2231 pf->offset_loaded, &os->rx_size_255,
2233 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2234 I40E_GLPRT_PRC511L(hw->port),
2235 pf->offset_loaded, &os->rx_size_511,
2237 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2238 I40E_GLPRT_PRC1023L(hw->port),
2239 pf->offset_loaded, &os->rx_size_1023,
2241 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2242 I40E_GLPRT_PRC1522L(hw->port),
2243 pf->offset_loaded, &os->rx_size_1522,
2245 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2246 I40E_GLPRT_PRC9522L(hw->port),
2247 pf->offset_loaded, &os->rx_size_big,
2249 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2250 pf->offset_loaded, &os->rx_undersize,
2252 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2253 pf->offset_loaded, &os->rx_fragments,
2255 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2256 pf->offset_loaded, &os->rx_oversize,
2258 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2259 pf->offset_loaded, &os->rx_jabber,
2261 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2262 I40E_GLPRT_PTC64L(hw->port),
2263 pf->offset_loaded, &os->tx_size_64,
2265 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2266 I40E_GLPRT_PTC127L(hw->port),
2267 pf->offset_loaded, &os->tx_size_127,
2269 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2270 I40E_GLPRT_PTC255L(hw->port),
2271 pf->offset_loaded, &os->tx_size_255,
2273 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2274 I40E_GLPRT_PTC511L(hw->port),
2275 pf->offset_loaded, &os->tx_size_511,
2277 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2278 I40E_GLPRT_PTC1023L(hw->port),
2279 pf->offset_loaded, &os->tx_size_1023,
2281 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2282 I40E_GLPRT_PTC1522L(hw->port),
2283 pf->offset_loaded, &os->tx_size_1522,
2285 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2286 I40E_GLPRT_PTC9522L(hw->port),
2287 pf->offset_loaded, &os->tx_size_big,
2289 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2291 &os->fd_sb_match, &ns->fd_sb_match);
2292 /* GLPRT_MSPDC not supported */
2293 /* GLPRT_XEC not supported */
2295 pf->offset_loaded = true;
2298 i40e_update_vsi_stats(pf->main_vsi);
2301 /* Get all statistics of a port */
2303 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2305 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2306 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2307 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2310 /* call read registers - updates values, now write them to struct */
2311 i40e_read_stats_registers(pf, hw);
2313 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2314 pf->main_vsi->eth_stats.rx_multicast +
2315 pf->main_vsi->eth_stats.rx_broadcast -
2316 pf->main_vsi->eth_stats.rx_discards;
2317 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2318 pf->main_vsi->eth_stats.tx_multicast +
2319 pf->main_vsi->eth_stats.tx_broadcast;
2320 stats->ibytes = ns->eth.rx_bytes;
2321 stats->obytes = ns->eth.tx_bytes;
2322 stats->oerrors = ns->eth.tx_errors +
2323 pf->main_vsi->eth_stats.tx_errors;
2326 stats->imissed = ns->eth.rx_discards +
2327 pf->main_vsi->eth_stats.rx_discards;
2328 stats->ierrors = ns->crc_errors +
2329 ns->rx_length_errors + ns->rx_undersize +
2330 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2332 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2333 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2334 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2335 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2336 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2337 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2338 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2339 ns->eth.rx_unknown_protocol);
2340 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2341 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2342 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2343 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2344 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2345 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2347 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2348 ns->tx_dropped_link_down);
2349 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2350 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2352 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2353 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2354 ns->mac_local_faults);
2355 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2356 ns->mac_remote_faults);
2357 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2358 ns->rx_length_errors);
2359 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2360 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2361 for (i = 0; i < 8; i++) {
2362 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2363 i, ns->priority_xon_rx[i]);
2364 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2365 i, ns->priority_xoff_rx[i]);
2367 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2368 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2369 for (i = 0; i < 8; i++) {
2370 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2371 i, ns->priority_xon_tx[i]);
2372 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2373 i, ns->priority_xoff_tx[i]);
2374 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2375 i, ns->priority_xon_2_xoff[i]);
2377 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2378 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2379 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2380 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2381 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2382 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2383 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2384 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2385 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2386 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2387 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2388 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2389 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2390 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2391 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2392 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2393 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2394 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2395 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2396 ns->mac_short_packet_dropped);
2397 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2398 ns->checksum_error);
2399 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2400 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2403 /* Reset the statistics */
2405 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2407 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2408 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2410 /* Mark PF and VSI stats to update the offset, aka "reset" */
2411 pf->offset_loaded = false;
2413 pf->main_vsi->offset_loaded = false;
2415 /* read the stats, reading current register values into offset */
2416 i40e_read_stats_registers(pf, hw);
2420 i40e_xstats_calc_num(void)
2422 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2423 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2424 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2427 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2428 struct rte_eth_xstat_name *xstats_names,
2429 __rte_unused unsigned limit)
2434 if (xstats_names == NULL)
2435 return i40e_xstats_calc_num();
2437 /* Note: limit checked in rte_eth_xstats_names() */
2439 /* Get stats from i40e_eth_stats struct */
2440 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2441 snprintf(xstats_names[count].name,
2442 sizeof(xstats_names[count].name),
2443 "%s", rte_i40e_stats_strings[i].name);
2447 /* Get individiual stats from i40e_hw_port struct */
2448 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2449 snprintf(xstats_names[count].name,
2450 sizeof(xstats_names[count].name),
2451 "%s", rte_i40e_hw_port_strings[i].name);
2455 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2456 for (prio = 0; prio < 8; prio++) {
2457 snprintf(xstats_names[count].name,
2458 sizeof(xstats_names[count].name),
2459 "rx_priority%u_%s", prio,
2460 rte_i40e_rxq_prio_strings[i].name);
2465 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2466 for (prio = 0; prio < 8; prio++) {
2467 snprintf(xstats_names[count].name,
2468 sizeof(xstats_names[count].name),
2469 "tx_priority%u_%s", prio,
2470 rte_i40e_txq_prio_strings[i].name);
2478 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2481 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2482 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2483 unsigned i, count, prio;
2484 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2486 count = i40e_xstats_calc_num();
2490 i40e_read_stats_registers(pf, hw);
2497 /* Get stats from i40e_eth_stats struct */
2498 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2499 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2500 rte_i40e_stats_strings[i].offset);
2504 /* Get individiual stats from i40e_hw_port struct */
2505 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2506 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2507 rte_i40e_hw_port_strings[i].offset);
2511 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2512 for (prio = 0; prio < 8; prio++) {
2513 xstats[count].value =
2514 *(uint64_t *)(((char *)hw_stats) +
2515 rte_i40e_rxq_prio_strings[i].offset +
2516 (sizeof(uint64_t) * prio));
2521 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2522 for (prio = 0; prio < 8; prio++) {
2523 xstats[count].value =
2524 *(uint64_t *)(((char *)hw_stats) +
2525 rte_i40e_txq_prio_strings[i].offset +
2526 (sizeof(uint64_t) * prio));
2535 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2536 __rte_unused uint16_t queue_id,
2537 __rte_unused uint8_t stat_idx,
2538 __rte_unused uint8_t is_rx)
2540 PMD_INIT_FUNC_TRACE();
2546 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2548 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2549 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2550 struct i40e_vsi *vsi = pf->main_vsi;
2552 dev_info->max_rx_queues = vsi->nb_qps;
2553 dev_info->max_tx_queues = vsi->nb_qps;
2554 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2555 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2556 dev_info->max_mac_addrs = vsi->max_macaddrs;
2557 dev_info->max_vfs = dev->pci_dev->max_vfs;
2558 dev_info->rx_offload_capa =
2559 DEV_RX_OFFLOAD_VLAN_STRIP |
2560 DEV_RX_OFFLOAD_QINQ_STRIP |
2561 DEV_RX_OFFLOAD_IPV4_CKSUM |
2562 DEV_RX_OFFLOAD_UDP_CKSUM |
2563 DEV_RX_OFFLOAD_TCP_CKSUM;
2564 dev_info->tx_offload_capa =
2565 DEV_TX_OFFLOAD_VLAN_INSERT |
2566 DEV_TX_OFFLOAD_QINQ_INSERT |
2567 DEV_TX_OFFLOAD_IPV4_CKSUM |
2568 DEV_TX_OFFLOAD_UDP_CKSUM |
2569 DEV_TX_OFFLOAD_TCP_CKSUM |
2570 DEV_TX_OFFLOAD_SCTP_CKSUM |
2571 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2572 DEV_TX_OFFLOAD_TCP_TSO;
2573 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2575 dev_info->reta_size = pf->hash_lut_size;
2576 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2578 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2580 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2581 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2582 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2584 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2588 dev_info->default_txconf = (struct rte_eth_txconf) {
2590 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2591 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2592 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2594 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2595 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2596 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2597 ETH_TXQ_FLAGS_NOOFFLOADS,
2600 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2601 .nb_max = I40E_MAX_RING_DESC,
2602 .nb_min = I40E_MIN_RING_DESC,
2603 .nb_align = I40E_ALIGN_RING_DESC,
2606 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2607 .nb_max = I40E_MAX_RING_DESC,
2608 .nb_min = I40E_MIN_RING_DESC,
2609 .nb_align = I40E_ALIGN_RING_DESC,
2612 if (pf->flags & I40E_FLAG_VMDQ) {
2613 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2614 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2615 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2616 pf->max_nb_vmdq_vsi;
2617 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2618 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2619 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2622 if (i40e_is_40G_device(hw->device_id))
2624 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2627 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2631 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2633 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2634 struct i40e_vsi *vsi = pf->main_vsi;
2635 PMD_INIT_FUNC_TRACE();
2638 return i40e_vsi_add_vlan(vsi, vlan_id);
2640 return i40e_vsi_delete_vlan(vsi, vlan_id);
2644 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2645 enum rte_vlan_type vlan_type,
2648 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2649 uint64_t reg_r = 0, reg_w = 0;
2650 uint16_t reg_id = 0;
2652 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2654 switch (vlan_type) {
2655 case ETH_VLAN_TYPE_OUTER:
2661 case ETH_VLAN_TYPE_INNER:
2667 "Unsupported vlan type in single vlan.\n");
2673 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2676 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2678 if (ret != I40E_SUCCESS) {
2679 PMD_DRV_LOG(ERR, "Fail to debug read from "
2680 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2684 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2685 "0x%08"PRIx64"", reg_id, reg_r);
2687 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2688 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2689 if (reg_r == reg_w) {
2691 PMD_DRV_LOG(DEBUG, "No need to write");
2695 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2697 if (ret != I40E_SUCCESS) {
2699 PMD_DRV_LOG(ERR, "Fail to debug write to "
2700 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2703 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2704 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2710 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2712 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2713 struct i40e_vsi *vsi = pf->main_vsi;
2715 if (mask & ETH_VLAN_FILTER_MASK) {
2716 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2717 i40e_vsi_config_vlan_filter(vsi, TRUE);
2719 i40e_vsi_config_vlan_filter(vsi, FALSE);
2722 if (mask & ETH_VLAN_STRIP_MASK) {
2723 /* Enable or disable VLAN stripping */
2724 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2725 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2727 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2730 if (mask & ETH_VLAN_EXTEND_MASK) {
2731 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2732 i40e_vsi_config_double_vlan(vsi, TRUE);
2733 /* Set global registers with default ether type value */
2734 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2736 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2740 i40e_vsi_config_double_vlan(vsi, FALSE);
2745 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2746 __rte_unused uint16_t queue,
2747 __rte_unused int on)
2749 PMD_INIT_FUNC_TRACE();
2753 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2755 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2756 struct i40e_vsi *vsi = pf->main_vsi;
2757 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2758 struct i40e_vsi_vlan_pvid_info info;
2760 memset(&info, 0, sizeof(info));
2763 info.config.pvid = pvid;
2765 info.config.reject.tagged =
2766 data->dev_conf.txmode.hw_vlan_reject_tagged;
2767 info.config.reject.untagged =
2768 data->dev_conf.txmode.hw_vlan_reject_untagged;
2771 return i40e_vsi_vlan_pvid_set(vsi, &info);
2775 i40e_dev_led_on(struct rte_eth_dev *dev)
2777 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778 uint32_t mode = i40e_led_get(hw);
2781 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2787 i40e_dev_led_off(struct rte_eth_dev *dev)
2789 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2790 uint32_t mode = i40e_led_get(hw);
2793 i40e_led_set(hw, 0, false);
2799 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2801 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2802 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2804 fc_conf->pause_time = pf->fc_conf.pause_time;
2805 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2806 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2808 /* Return current mode according to actual setting*/
2809 switch (hw->fc.current_mode) {
2811 fc_conf->mode = RTE_FC_FULL;
2813 case I40E_FC_TX_PAUSE:
2814 fc_conf->mode = RTE_FC_TX_PAUSE;
2816 case I40E_FC_RX_PAUSE:
2817 fc_conf->mode = RTE_FC_RX_PAUSE;
2821 fc_conf->mode = RTE_FC_NONE;
2828 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2830 uint32_t mflcn_reg, fctrl_reg, reg;
2831 uint32_t max_high_water;
2832 uint8_t i, aq_failure;
2836 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2837 [RTE_FC_NONE] = I40E_FC_NONE,
2838 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2839 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2840 [RTE_FC_FULL] = I40E_FC_FULL
2843 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2845 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2846 if ((fc_conf->high_water > max_high_water) ||
2847 (fc_conf->high_water < fc_conf->low_water)) {
2848 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2849 "High_water must <= %d.", max_high_water);
2853 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2854 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2855 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2857 pf->fc_conf.pause_time = fc_conf->pause_time;
2858 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2859 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2861 PMD_INIT_FUNC_TRACE();
2863 /* All the link flow control related enable/disable register
2864 * configuration is handle by the F/W
2866 err = i40e_set_fc(hw, &aq_failure, true);
2870 if (i40e_is_40G_device(hw->device_id)) {
2871 /* Configure flow control refresh threshold,
2872 * the value for stat_tx_pause_refresh_timer[8]
2873 * is used for global pause operation.
2877 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2878 pf->fc_conf.pause_time);
2880 /* configure the timer value included in transmitted pause
2882 * the value for stat_tx_pause_quanta[8] is used for global
2885 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2886 pf->fc_conf.pause_time);
2888 fctrl_reg = I40E_READ_REG(hw,
2889 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2891 if (fc_conf->mac_ctrl_frame_fwd != 0)
2892 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2894 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2896 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2899 /* Configure pause time (2 TCs per register) */
2900 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2901 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2902 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2904 /* Configure flow control refresh threshold value */
2905 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2906 pf->fc_conf.pause_time / 2);
2908 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2910 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2911 *depending on configuration
2913 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2914 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2915 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2917 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2918 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2921 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2924 /* config the water marker both based on the packets and bytes */
2925 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2926 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2927 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2928 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2929 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2930 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2931 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2932 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2934 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2935 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2938 I40E_WRITE_FLUSH(hw);
2944 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2945 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2947 PMD_INIT_FUNC_TRACE();
2952 /* Add a MAC address, and update filters */
2954 i40e_macaddr_add(struct rte_eth_dev *dev,
2955 struct ether_addr *mac_addr,
2956 __rte_unused uint32_t index,
2959 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2960 struct i40e_mac_filter_info mac_filter;
2961 struct i40e_vsi *vsi;
2964 /* If VMDQ not enabled or configured, return */
2965 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2966 !pf->nb_cfg_vmdq_vsi)) {
2967 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2968 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
2973 if (pool > pf->nb_cfg_vmdq_vsi) {
2974 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2975 pool, pf->nb_cfg_vmdq_vsi);
2979 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2980 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2981 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2983 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2988 vsi = pf->vmdq[pool - 1].vsi;
2990 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2991 if (ret != I40E_SUCCESS) {
2992 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2997 /* Remove a MAC address, and update filters */
2999 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3001 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3002 struct i40e_vsi *vsi;
3003 struct rte_eth_dev_data *data = dev->data;
3004 struct ether_addr *macaddr;
3009 macaddr = &(data->mac_addrs[index]);
3011 pool_sel = dev->data->mac_pool_sel[index];
3013 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3014 if (pool_sel & (1ULL << i)) {
3018 /* No VMDQ pool enabled or configured */
3019 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3020 (i > pf->nb_cfg_vmdq_vsi)) {
3021 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3025 vsi = pf->vmdq[i - 1].vsi;
3027 ret = i40e_vsi_delete_mac(vsi, macaddr);
3030 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3037 /* Set perfect match or hash match of MAC and VLAN for a VF */
3039 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3040 struct rte_eth_mac_filter *filter,
3044 struct i40e_mac_filter_info mac_filter;
3045 struct ether_addr old_mac;
3046 struct ether_addr *new_mac;
3047 struct i40e_pf_vf *vf = NULL;
3052 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3055 hw = I40E_PF_TO_HW(pf);
3057 if (filter == NULL) {
3058 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3062 new_mac = &filter->mac_addr;
3064 if (is_zero_ether_addr(new_mac)) {
3065 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3069 vf_id = filter->dst_id;
3071 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3072 PMD_DRV_LOG(ERR, "Invalid argument.");
3075 vf = &pf->vfs[vf_id];
3077 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3078 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3083 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3084 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3086 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3089 mac_filter.filter_type = filter->filter_type;
3090 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3091 if (ret != I40E_SUCCESS) {
3092 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3095 ether_addr_copy(new_mac, &pf->dev_addr);
3097 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3099 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3100 if (ret != I40E_SUCCESS) {
3101 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3105 /* Clear device address as it has been removed */
3106 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3107 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3113 /* MAC filter handle */
3115 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3118 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3119 struct rte_eth_mac_filter *filter;
3120 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3121 int ret = I40E_NOT_SUPPORTED;
3123 filter = (struct rte_eth_mac_filter *)(arg);
3125 switch (filter_op) {
3126 case RTE_ETH_FILTER_NOP:
3129 case RTE_ETH_FILTER_ADD:
3130 i40e_pf_disable_irq0(hw);
3132 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3133 i40e_pf_enable_irq0(hw);
3135 case RTE_ETH_FILTER_DELETE:
3136 i40e_pf_disable_irq0(hw);
3138 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3139 i40e_pf_enable_irq0(hw);
3142 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3143 ret = I40E_ERR_PARAM;
3151 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3153 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3154 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3160 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3161 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3164 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3168 uint32_t *lut_dw = (uint32_t *)lut;
3169 uint16_t i, lut_size_dw = lut_size / 4;
3171 for (i = 0; i < lut_size_dw; i++)
3172 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3179 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3188 pf = I40E_VSI_TO_PF(vsi);
3189 hw = I40E_VSI_TO_HW(vsi);
3191 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3192 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3195 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3199 uint32_t *lut_dw = (uint32_t *)lut;
3200 uint16_t i, lut_size_dw = lut_size / 4;
3202 for (i = 0; i < lut_size_dw; i++)
3203 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3204 I40E_WRITE_FLUSH(hw);
3211 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3212 struct rte_eth_rss_reta_entry64 *reta_conf,
3215 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3216 uint16_t i, lut_size = pf->hash_lut_size;
3217 uint16_t idx, shift;
3221 if (reta_size != lut_size ||
3222 reta_size > ETH_RSS_RETA_SIZE_512) {
3223 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3224 "(%d) doesn't match the number hardware can supported "
3225 "(%d)\n", reta_size, lut_size);
3229 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3231 PMD_DRV_LOG(ERR, "No memory can be allocated");
3234 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3237 for (i = 0; i < reta_size; i++) {
3238 idx = i / RTE_RETA_GROUP_SIZE;
3239 shift = i % RTE_RETA_GROUP_SIZE;
3240 if (reta_conf[idx].mask & (1ULL << shift))
3241 lut[i] = reta_conf[idx].reta[shift];
3243 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3252 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3253 struct rte_eth_rss_reta_entry64 *reta_conf,
3256 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3257 uint16_t i, lut_size = pf->hash_lut_size;
3258 uint16_t idx, shift;
3262 if (reta_size != lut_size ||
3263 reta_size > ETH_RSS_RETA_SIZE_512) {
3264 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3265 "(%d) doesn't match the number hardware can supported "
3266 "(%d)\n", reta_size, lut_size);
3270 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3272 PMD_DRV_LOG(ERR, "No memory can be allocated");
3276 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3279 for (i = 0; i < reta_size; i++) {
3280 idx = i / RTE_RETA_GROUP_SIZE;
3281 shift = i % RTE_RETA_GROUP_SIZE;
3282 if (reta_conf[idx].mask & (1ULL << shift))
3283 reta_conf[idx].reta[shift] = lut[i];
3293 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3294 * @hw: pointer to the HW structure
3295 * @mem: pointer to mem struct to fill out
3296 * @size: size of memory requested
3297 * @alignment: what to align the allocation to
3299 enum i40e_status_code
3300 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3301 struct i40e_dma_mem *mem,
3305 const struct rte_memzone *mz = NULL;
3306 char z_name[RTE_MEMZONE_NAMESIZE];
3309 return I40E_ERR_PARAM;
3311 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3312 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3313 alignment, RTE_PGSIZE_2M);
3315 return I40E_ERR_NO_MEMORY;
3319 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3320 mem->zone = (const void *)mz;
3321 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3322 "%"PRIu64, mz->name, mem->pa);
3324 return I40E_SUCCESS;
3328 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3329 * @hw: pointer to the HW structure
3330 * @mem: ptr to mem struct to free
3332 enum i40e_status_code
3333 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3334 struct i40e_dma_mem *mem)
3337 return I40E_ERR_PARAM;
3339 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3340 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3342 rte_memzone_free((const struct rte_memzone *)mem->zone);
3347 return I40E_SUCCESS;
3351 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3352 * @hw: pointer to the HW structure
3353 * @mem: pointer to mem struct to fill out
3354 * @size: size of memory requested
3356 enum i40e_status_code
3357 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3358 struct i40e_virt_mem *mem,
3362 return I40E_ERR_PARAM;
3365 mem->va = rte_zmalloc("i40e", size, 0);
3368 return I40E_SUCCESS;
3370 return I40E_ERR_NO_MEMORY;
3374 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3375 * @hw: pointer to the HW structure
3376 * @mem: pointer to mem struct to free
3378 enum i40e_status_code
3379 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3380 struct i40e_virt_mem *mem)
3383 return I40E_ERR_PARAM;
3388 return I40E_SUCCESS;
3392 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3394 rte_spinlock_init(&sp->spinlock);
3398 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3400 rte_spinlock_lock(&sp->spinlock);
3404 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3406 rte_spinlock_unlock(&sp->spinlock);
3410 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3416 * Get the hardware capabilities, which will be parsed
3417 * and saved into struct i40e_hw.
3420 i40e_get_cap(struct i40e_hw *hw)
3422 struct i40e_aqc_list_capabilities_element_resp *buf;
3423 uint16_t len, size = 0;
3426 /* Calculate a huge enough buff for saving response data temporarily */
3427 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3428 I40E_MAX_CAP_ELE_NUM;
3429 buf = rte_zmalloc("i40e", len, 0);
3431 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3432 return I40E_ERR_NO_MEMORY;
3435 /* Get, parse the capabilities and save it to hw */
3436 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3437 i40e_aqc_opc_list_func_capabilities, NULL);
3438 if (ret != I40E_SUCCESS)
3439 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3441 /* Free the temporary buffer after being used */
3448 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3450 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3451 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3452 uint16_t qp_count = 0, vsi_count = 0;
3454 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3455 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3458 /* Add the parameter init for LFC */
3459 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3460 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3461 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3463 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3464 pf->max_num_vsi = hw->func_caps.num_vsis;
3465 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3466 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3467 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3469 /* FDir queue/VSI allocation */
3470 pf->fdir_qp_offset = 0;
3471 if (hw->func_caps.fd) {
3472 pf->flags |= I40E_FLAG_FDIR;
3473 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3475 pf->fdir_nb_qps = 0;
3477 qp_count += pf->fdir_nb_qps;
3480 /* LAN queue/VSI allocation */
3481 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3482 if (!hw->func_caps.rss) {
3485 pf->flags |= I40E_FLAG_RSS;
3486 if (hw->mac.type == I40E_MAC_X722)
3487 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3488 pf->lan_nb_qps = pf->lan_nb_qp_max;
3490 qp_count += pf->lan_nb_qps;
3493 /* VF queue/VSI allocation */
3494 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3495 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3496 pf->flags |= I40E_FLAG_SRIOV;
3497 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3498 pf->vf_num = dev->pci_dev->max_vfs;
3499 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3500 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3501 pf->vf_nb_qps * pf->vf_num);
3506 qp_count += pf->vf_nb_qps * pf->vf_num;
3507 vsi_count += pf->vf_num;
3509 /* VMDq queue/VSI allocation */
3510 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3511 pf->vmdq_nb_qps = 0;
3512 pf->max_nb_vmdq_vsi = 0;
3513 if (hw->func_caps.vmdq) {
3514 if (qp_count < hw->func_caps.num_tx_qp &&
3515 vsi_count < hw->func_caps.num_vsis) {
3516 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3517 qp_count) / pf->vmdq_nb_qp_max;
3519 /* Limit the maximum number of VMDq vsi to the maximum
3520 * ethdev can support
3522 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3523 hw->func_caps.num_vsis - vsi_count);
3524 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3526 if (pf->max_nb_vmdq_vsi) {
3527 pf->flags |= I40E_FLAG_VMDQ;
3528 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3529 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3530 "per VMDQ VSI, in total %u queues",
3531 pf->max_nb_vmdq_vsi,
3532 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3533 pf->max_nb_vmdq_vsi);
3535 PMD_DRV_LOG(INFO, "No enough queues left for "
3539 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3542 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3543 vsi_count += pf->max_nb_vmdq_vsi;
3545 if (hw->func_caps.dcb)
3546 pf->flags |= I40E_FLAG_DCB;
3548 if (qp_count > hw->func_caps.num_tx_qp) {
3549 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3550 "the hardware maximum %u", qp_count,
3551 hw->func_caps.num_tx_qp);
3554 if (vsi_count > hw->func_caps.num_vsis) {
3555 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3556 "the hardware maximum %u", vsi_count,
3557 hw->func_caps.num_vsis);
3565 i40e_pf_get_switch_config(struct i40e_pf *pf)
3567 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3568 struct i40e_aqc_get_switch_config_resp *switch_config;
3569 struct i40e_aqc_switch_config_element_resp *element;
3570 uint16_t start_seid = 0, num_reported;
3573 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3574 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3575 if (!switch_config) {
3576 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3580 /* Get the switch configurations */
3581 ret = i40e_aq_get_switch_config(hw, switch_config,
3582 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3583 if (ret != I40E_SUCCESS) {
3584 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3587 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3588 if (num_reported != 1) { /* The number should be 1 */
3589 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3593 /* Parse the switch configuration elements */
3594 element = &(switch_config->element[0]);
3595 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3596 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3597 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3599 PMD_DRV_LOG(INFO, "Unknown element type");
3602 rte_free(switch_config);
3608 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3611 struct pool_entry *entry;
3613 if (pool == NULL || num == 0)
3616 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3617 if (entry == NULL) {
3618 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3622 /* queue heap initialize */
3623 pool->num_free = num;
3624 pool->num_alloc = 0;
3626 LIST_INIT(&pool->alloc_list);
3627 LIST_INIT(&pool->free_list);
3629 /* Initialize element */
3633 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3638 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3640 struct pool_entry *entry, *next_entry;
3645 for (entry = LIST_FIRST(&pool->alloc_list);
3646 entry && (next_entry = LIST_NEXT(entry, next), 1);
3647 entry = next_entry) {
3648 LIST_REMOVE(entry, next);
3652 for (entry = LIST_FIRST(&pool->free_list);
3653 entry && (next_entry = LIST_NEXT(entry, next), 1);
3654 entry = next_entry) {
3655 LIST_REMOVE(entry, next);
3660 pool->num_alloc = 0;
3662 LIST_INIT(&pool->alloc_list);
3663 LIST_INIT(&pool->free_list);
3667 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3670 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3671 uint32_t pool_offset;
3675 PMD_DRV_LOG(ERR, "Invalid parameter");
3679 pool_offset = base - pool->base;
3680 /* Lookup in alloc list */
3681 LIST_FOREACH(entry, &pool->alloc_list, next) {
3682 if (entry->base == pool_offset) {
3683 valid_entry = entry;
3684 LIST_REMOVE(entry, next);
3689 /* Not find, return */
3690 if (valid_entry == NULL) {
3691 PMD_DRV_LOG(ERR, "Failed to find entry");
3696 * Found it, move it to free list and try to merge.
3697 * In order to make merge easier, always sort it by qbase.
3698 * Find adjacent prev and last entries.
3701 LIST_FOREACH(entry, &pool->free_list, next) {
3702 if (entry->base > valid_entry->base) {
3710 /* Try to merge with next one*/
3712 /* Merge with next one */
3713 if (valid_entry->base + valid_entry->len == next->base) {
3714 next->base = valid_entry->base;
3715 next->len += valid_entry->len;
3716 rte_free(valid_entry);
3723 /* Merge with previous one */
3724 if (prev->base + prev->len == valid_entry->base) {
3725 prev->len += valid_entry->len;
3726 /* If it merge with next one, remove next node */
3728 LIST_REMOVE(valid_entry, next);
3729 rte_free(valid_entry);
3731 rte_free(valid_entry);
3737 /* Not find any entry to merge, insert */
3740 LIST_INSERT_AFTER(prev, valid_entry, next);
3741 else if (next != NULL)
3742 LIST_INSERT_BEFORE(next, valid_entry, next);
3743 else /* It's empty list, insert to head */
3744 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3747 pool->num_free += valid_entry->len;
3748 pool->num_alloc -= valid_entry->len;
3754 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3757 struct pool_entry *entry, *valid_entry;
3759 if (pool == NULL || num == 0) {
3760 PMD_DRV_LOG(ERR, "Invalid parameter");
3764 if (pool->num_free < num) {
3765 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3766 num, pool->num_free);
3771 /* Lookup in free list and find most fit one */
3772 LIST_FOREACH(entry, &pool->free_list, next) {
3773 if (entry->len >= num) {
3775 if (entry->len == num) {
3776 valid_entry = entry;
3779 if (valid_entry == NULL || valid_entry->len > entry->len)
3780 valid_entry = entry;
3784 /* Not find one to satisfy the request, return */
3785 if (valid_entry == NULL) {
3786 PMD_DRV_LOG(ERR, "No valid entry found");
3790 * The entry have equal queue number as requested,
3791 * remove it from alloc_list.
3793 if (valid_entry->len == num) {
3794 LIST_REMOVE(valid_entry, next);
3797 * The entry have more numbers than requested,
3798 * create a new entry for alloc_list and minus its
3799 * queue base and number in free_list.
3801 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3802 if (entry == NULL) {
3803 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3807 entry->base = valid_entry->base;
3809 valid_entry->base += num;
3810 valid_entry->len -= num;
3811 valid_entry = entry;
3814 /* Insert it into alloc list, not sorted */
3815 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3817 pool->num_free -= valid_entry->len;
3818 pool->num_alloc += valid_entry->len;
3820 return valid_entry->base + pool->base;
3824 * bitmap_is_subset - Check whether src2 is subset of src1
3827 bitmap_is_subset(uint8_t src1, uint8_t src2)
3829 return !((src1 ^ src2) & src2);
3832 static enum i40e_status_code
3833 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3835 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3837 /* If DCB is not supported, only default TC is supported */
3838 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3839 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3840 return I40E_NOT_SUPPORTED;
3843 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3844 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3845 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3847 return I40E_NOT_SUPPORTED;
3849 return I40E_SUCCESS;
3853 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3854 struct i40e_vsi_vlan_pvid_info *info)
3857 struct i40e_vsi_context ctxt;
3858 uint8_t vlan_flags = 0;
3861 if (vsi == NULL || info == NULL) {
3862 PMD_DRV_LOG(ERR, "invalid parameters");
3863 return I40E_ERR_PARAM;
3867 vsi->info.pvid = info->config.pvid;
3869 * If insert pvid is enabled, only tagged pkts are
3870 * allowed to be sent out.
3872 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3873 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3876 if (info->config.reject.tagged == 0)
3877 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3879 if (info->config.reject.untagged == 0)
3880 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3882 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3883 I40E_AQ_VSI_PVLAN_MODE_MASK);
3884 vsi->info.port_vlan_flags |= vlan_flags;
3885 vsi->info.valid_sections =
3886 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3887 memset(&ctxt, 0, sizeof(ctxt));
3888 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3889 ctxt.seid = vsi->seid;
3891 hw = I40E_VSI_TO_HW(vsi);
3892 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3893 if (ret != I40E_SUCCESS)
3894 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3900 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3902 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3904 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3906 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3907 if (ret != I40E_SUCCESS)
3911 PMD_DRV_LOG(ERR, "seid not valid");
3915 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3916 tc_bw_data.tc_valid_bits = enabled_tcmap;
3917 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3918 tc_bw_data.tc_bw_credits[i] =
3919 (enabled_tcmap & (1 << i)) ? 1 : 0;
3921 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3922 if (ret != I40E_SUCCESS) {
3923 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3927 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3928 sizeof(vsi->info.qs_handle));
3929 return I40E_SUCCESS;
3932 static enum i40e_status_code
3933 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3934 struct i40e_aqc_vsi_properties_data *info,
3935 uint8_t enabled_tcmap)
3937 enum i40e_status_code ret;
3938 int i, total_tc = 0;
3939 uint16_t qpnum_per_tc, bsf, qp_idx;
3941 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3942 if (ret != I40E_SUCCESS)
3945 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3946 if (enabled_tcmap & (1 << i))
3948 vsi->enabled_tc = enabled_tcmap;
3950 /* Number of queues per enabled TC */
3951 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3952 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3953 bsf = rte_bsf32(qpnum_per_tc);
3955 /* Adjust the queue number to actual queues that can be applied */
3956 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3957 vsi->nb_qps = qpnum_per_tc * total_tc;
3960 * Configure TC and queue mapping parameters, for enabled TC,
3961 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3962 * default queue will serve it.
3965 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3966 if (vsi->enabled_tc & (1 << i)) {
3967 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3968 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3969 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3970 qp_idx += qpnum_per_tc;
3972 info->tc_mapping[i] = 0;
3975 /* Associate queue number with VSI */
3976 if (vsi->type == I40E_VSI_SRIOV) {
3977 info->mapping_flags |=
3978 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3979 for (i = 0; i < vsi->nb_qps; i++)
3980 info->queue_mapping[i] =
3981 rte_cpu_to_le_16(vsi->base_queue + i);
3983 info->mapping_flags |=
3984 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3985 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3987 info->valid_sections |=
3988 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3990 return I40E_SUCCESS;
3994 i40e_veb_release(struct i40e_veb *veb)
3996 struct i40e_vsi *vsi;
4002 if (!TAILQ_EMPTY(&veb->head)) {
4003 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4006 /* associate_vsi field is NULL for floating VEB */
4007 if (veb->associate_vsi != NULL) {
4008 vsi = veb->associate_vsi;
4009 hw = I40E_VSI_TO_HW(vsi);
4011 vsi->uplink_seid = veb->uplink_seid;
4014 veb->associate_pf->main_vsi->floating_veb = NULL;
4015 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4018 i40e_aq_delete_element(hw, veb->seid, NULL);
4020 return I40E_SUCCESS;
4024 static struct i40e_veb *
4025 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4027 struct i40e_veb *veb;
4033 "veb setup failed, associated PF shouldn't null");
4036 hw = I40E_PF_TO_HW(pf);
4038 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4040 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4044 veb->associate_vsi = vsi;
4045 veb->associate_pf = pf;
4046 TAILQ_INIT(&veb->head);
4047 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4049 /* create floating veb if vsi is NULL */
4051 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4052 I40E_DEFAULT_TCMAP, false,
4053 &veb->seid, false, NULL);
4055 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4056 true, &veb->seid, false, NULL);
4059 if (ret != I40E_SUCCESS) {
4060 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4061 hw->aq.asq_last_status);
4065 /* get statistics index */
4066 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4067 &veb->stats_idx, NULL, NULL, NULL);
4068 if (ret != I40E_SUCCESS) {
4069 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4070 hw->aq.asq_last_status);
4073 /* Get VEB bandwidth, to be implemented */
4074 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4076 vsi->uplink_seid = veb->seid;
4085 i40e_vsi_release(struct i40e_vsi *vsi)
4089 struct i40e_vsi_list *vsi_list;
4092 struct i40e_mac_filter *f;
4093 uint16_t user_param = vsi->user_param;
4096 return I40E_SUCCESS;
4098 pf = I40E_VSI_TO_PF(vsi);
4099 hw = I40E_VSI_TO_HW(vsi);
4101 /* VSI has child to attach, release child first */
4103 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4104 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4107 i40e_veb_release(vsi->veb);
4110 if (vsi->floating_veb) {
4111 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4112 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4117 /* Remove all macvlan filters of the VSI */
4118 i40e_vsi_remove_all_macvlan_filter(vsi);
4119 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4122 if (vsi->type != I40E_VSI_MAIN &&
4123 ((vsi->type != I40E_VSI_SRIOV) ||
4124 !pf->floating_veb_list[user_param])) {
4125 /* Remove vsi from parent's sibling list */
4126 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4127 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4128 return I40E_ERR_PARAM;
4130 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4131 &vsi->sib_vsi_list, list);
4133 /* Remove all switch element of the VSI */
4134 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4135 if (ret != I40E_SUCCESS)
4136 PMD_DRV_LOG(ERR, "Failed to delete element");
4139 if ((vsi->type == I40E_VSI_SRIOV) &&
4140 pf->floating_veb_list[user_param]) {
4141 /* Remove vsi from parent's sibling list */
4142 if (vsi->parent_vsi == NULL ||
4143 vsi->parent_vsi->floating_veb == NULL) {
4144 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4145 return I40E_ERR_PARAM;
4147 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4148 &vsi->sib_vsi_list, list);
4150 /* Remove all switch element of the VSI */
4151 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4152 if (ret != I40E_SUCCESS)
4153 PMD_DRV_LOG(ERR, "Failed to delete element");
4156 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4158 if (vsi->type != I40E_VSI_SRIOV)
4159 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4162 return I40E_SUCCESS;
4166 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4168 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4169 struct i40e_aqc_remove_macvlan_element_data def_filter;
4170 struct i40e_mac_filter_info filter;
4173 if (vsi->type != I40E_VSI_MAIN)
4174 return I40E_ERR_CONFIG;
4175 memset(&def_filter, 0, sizeof(def_filter));
4176 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4178 def_filter.vlan_tag = 0;
4179 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4180 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4181 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4182 if (ret != I40E_SUCCESS) {
4183 struct i40e_mac_filter *f;
4184 struct ether_addr *mac;
4186 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4188 /* It needs to add the permanent mac into mac list */
4189 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4191 PMD_DRV_LOG(ERR, "failed to allocate memory");
4192 return I40E_ERR_NO_MEMORY;
4194 mac = &f->mac_info.mac_addr;
4195 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4197 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4198 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4203 (void)rte_memcpy(&filter.mac_addr,
4204 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4205 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4206 return i40e_vsi_add_mac(vsi, &filter);
4210 * i40e_vsi_get_bw_config - Query VSI BW Information
4211 * @vsi: the VSI to be queried
4213 * Returns 0 on success, negative value on failure
4215 static enum i40e_status_code
4216 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4218 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4219 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4220 struct i40e_hw *hw = &vsi->adapter->hw;
4225 memset(&bw_config, 0, sizeof(bw_config));
4226 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4227 if (ret != I40E_SUCCESS) {
4228 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4229 hw->aq.asq_last_status);
4233 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4234 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4235 &ets_sla_config, NULL);
4236 if (ret != I40E_SUCCESS) {
4237 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4238 "configuration %u", hw->aq.asq_last_status);
4242 /* store and print out BW info */
4243 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4244 vsi->bw_info.bw_max = bw_config.max_bw;
4245 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4246 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4247 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4248 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4250 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4251 vsi->bw_info.bw_ets_share_credits[i] =
4252 ets_sla_config.share_credits[i];
4253 vsi->bw_info.bw_ets_credits[i] =
4254 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4255 /* 4 bits per TC, 4th bit is reserved */
4256 vsi->bw_info.bw_ets_max[i] =
4257 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4258 RTE_LEN2MASK(3, uint8_t));
4259 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4260 vsi->bw_info.bw_ets_share_credits[i]);
4261 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4262 vsi->bw_info.bw_ets_credits[i]);
4263 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4264 vsi->bw_info.bw_ets_max[i]);
4267 return I40E_SUCCESS;
4270 /* i40e_enable_pf_lb
4271 * @pf: pointer to the pf structure
4273 * allow loopback on pf
4276 i40e_enable_pf_lb(struct i40e_pf *pf)
4278 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4279 struct i40e_vsi_context ctxt;
4282 /* Use the FW API if FW >= v5.0 */
4283 if (hw->aq.fw_maj_ver < 5) {
4284 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4288 memset(&ctxt, 0, sizeof(ctxt));
4289 ctxt.seid = pf->main_vsi_seid;
4290 ctxt.pf_num = hw->pf_id;
4291 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4293 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4294 ret, hw->aq.asq_last_status);
4297 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4298 ctxt.info.valid_sections =
4299 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4300 ctxt.info.switch_id |=
4301 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4303 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4305 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4306 hw->aq.asq_last_status);
4311 i40e_vsi_setup(struct i40e_pf *pf,
4312 enum i40e_vsi_type type,
4313 struct i40e_vsi *uplink_vsi,
4314 uint16_t user_param)
4316 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4317 struct i40e_vsi *vsi;
4318 struct i40e_mac_filter_info filter;
4320 struct i40e_vsi_context ctxt;
4321 struct ether_addr broadcast =
4322 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4324 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4325 uplink_vsi == NULL) {
4326 PMD_DRV_LOG(ERR, "VSI setup failed, "
4327 "VSI link shouldn't be NULL");
4331 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4332 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4333 "uplink VSI should be NULL");
4338 * 1.type is not MAIN and uplink vsi is not NULL
4339 * If uplink vsi didn't setup VEB, create one first under veb field
4340 * 2.type is SRIOV and the uplink is NULL
4341 * If floating VEB is NULL, create one veb under floating veb field
4344 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4345 uplink_vsi->veb == NULL) {
4346 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4348 if (uplink_vsi->veb == NULL) {
4349 PMD_DRV_LOG(ERR, "VEB setup failed");
4352 /* set ALLOWLOOPBACk on pf, when veb is created */
4353 i40e_enable_pf_lb(pf);
4356 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4357 pf->main_vsi->floating_veb == NULL) {
4358 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4360 if (pf->main_vsi->floating_veb == NULL) {
4361 PMD_DRV_LOG(ERR, "VEB setup failed");
4366 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4368 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4371 TAILQ_INIT(&vsi->mac_list);
4373 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4374 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4375 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4376 vsi->user_param = user_param;
4377 /* Allocate queues */
4378 switch (vsi->type) {
4379 case I40E_VSI_MAIN :
4380 vsi->nb_qps = pf->lan_nb_qps;
4382 case I40E_VSI_SRIOV :
4383 vsi->nb_qps = pf->vf_nb_qps;
4385 case I40E_VSI_VMDQ2:
4386 vsi->nb_qps = pf->vmdq_nb_qps;
4389 vsi->nb_qps = pf->fdir_nb_qps;
4395 * The filter status descriptor is reported in rx queue 0,
4396 * while the tx queue for fdir filter programming has no
4397 * such constraints, can be non-zero queues.
4398 * To simplify it, choose FDIR vsi use queue 0 pair.
4399 * To make sure it will use queue 0 pair, queue allocation
4400 * need be done before this function is called
4402 if (type != I40E_VSI_FDIR) {
4403 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4405 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4409 vsi->base_queue = ret;
4411 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4413 /* VF has MSIX interrupt in VF range, don't allocate here */
4414 if (type == I40E_VSI_MAIN) {
4415 ret = i40e_res_pool_alloc(&pf->msix_pool,
4416 RTE_MIN(vsi->nb_qps,
4417 RTE_MAX_RXTX_INTR_VEC_ID));
4419 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4421 goto fail_queue_alloc;
4423 vsi->msix_intr = ret;
4424 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4425 } else if (type != I40E_VSI_SRIOV) {
4426 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4428 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4429 goto fail_queue_alloc;
4431 vsi->msix_intr = ret;
4439 if (type == I40E_VSI_MAIN) {
4440 /* For main VSI, no need to add since it's default one */
4441 vsi->uplink_seid = pf->mac_seid;
4442 vsi->seid = pf->main_vsi_seid;
4443 /* Bind queues with specific MSIX interrupt */
4445 * Needs 2 interrupt at least, one for misc cause which will
4446 * enabled from OS side, Another for queues binding the
4447 * interrupt from device side only.
4450 /* Get default VSI parameters from hardware */
4451 memset(&ctxt, 0, sizeof(ctxt));
4452 ctxt.seid = vsi->seid;
4453 ctxt.pf_num = hw->pf_id;
4454 ctxt.uplink_seid = vsi->uplink_seid;
4456 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4457 if (ret != I40E_SUCCESS) {
4458 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4459 goto fail_msix_alloc;
4461 (void)rte_memcpy(&vsi->info, &ctxt.info,
4462 sizeof(struct i40e_aqc_vsi_properties_data));
4463 vsi->vsi_id = ctxt.vsi_number;
4464 vsi->info.valid_sections = 0;
4466 /* Configure tc, enabled TC0 only */
4467 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4469 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4470 goto fail_msix_alloc;
4473 /* TC, queue mapping */
4474 memset(&ctxt, 0, sizeof(ctxt));
4475 vsi->info.valid_sections |=
4476 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4477 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4478 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4479 (void)rte_memcpy(&ctxt.info, &vsi->info,
4480 sizeof(struct i40e_aqc_vsi_properties_data));
4481 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4482 I40E_DEFAULT_TCMAP);
4483 if (ret != I40E_SUCCESS) {
4484 PMD_DRV_LOG(ERR, "Failed to configure "
4485 "TC queue mapping");
4486 goto fail_msix_alloc;
4488 ctxt.seid = vsi->seid;
4489 ctxt.pf_num = hw->pf_id;
4490 ctxt.uplink_seid = vsi->uplink_seid;
4493 /* Update VSI parameters */
4494 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4495 if (ret != I40E_SUCCESS) {
4496 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4497 goto fail_msix_alloc;
4500 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4501 sizeof(vsi->info.tc_mapping));
4502 (void)rte_memcpy(&vsi->info.queue_mapping,
4503 &ctxt.info.queue_mapping,
4504 sizeof(vsi->info.queue_mapping));
4505 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4506 vsi->info.valid_sections = 0;
4508 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4512 * Updating default filter settings are necessary to prevent
4513 * reception of tagged packets.
4514 * Some old firmware configurations load a default macvlan
4515 * filter which accepts both tagged and untagged packets.
4516 * The updating is to use a normal filter instead if needed.
4517 * For NVM 4.2.2 or after, the updating is not needed anymore.
4518 * The firmware with correct configurations load the default
4519 * macvlan filter which is expected and cannot be removed.
4521 i40e_update_default_filter_setting(vsi);
4522 i40e_config_qinq(hw, vsi);
4523 } else if (type == I40E_VSI_SRIOV) {
4524 memset(&ctxt, 0, sizeof(ctxt));
4526 * For other VSI, the uplink_seid equals to uplink VSI's
4527 * uplink_seid since they share same VEB
4529 if (uplink_vsi == NULL)
4530 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4532 vsi->uplink_seid = uplink_vsi->uplink_seid;
4533 ctxt.pf_num = hw->pf_id;
4534 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4535 ctxt.uplink_seid = vsi->uplink_seid;
4536 ctxt.connection_type = 0x1;
4537 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4539 /* Use the VEB configuration if FW >= v5.0 */
4540 if (hw->aq.fw_maj_ver >= 5) {
4541 /* Configure switch ID */
4542 ctxt.info.valid_sections |=
4543 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4544 ctxt.info.switch_id =
4545 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4548 /* Configure port/vlan */
4549 ctxt.info.valid_sections |=
4550 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4551 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4552 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4553 I40E_DEFAULT_TCMAP);
4554 if (ret != I40E_SUCCESS) {
4555 PMD_DRV_LOG(ERR, "Failed to configure "
4556 "TC queue mapping");
4557 goto fail_msix_alloc;
4559 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4560 ctxt.info.valid_sections |=
4561 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4563 * Since VSI is not created yet, only configure parameter,
4564 * will add vsi below.
4567 i40e_config_qinq(hw, vsi);
4568 } else if (type == I40E_VSI_VMDQ2) {
4569 memset(&ctxt, 0, sizeof(ctxt));
4571 * For other VSI, the uplink_seid equals to uplink VSI's
4572 * uplink_seid since they share same VEB
4574 vsi->uplink_seid = uplink_vsi->uplink_seid;
4575 ctxt.pf_num = hw->pf_id;
4577 ctxt.uplink_seid = vsi->uplink_seid;
4578 ctxt.connection_type = 0x1;
4579 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4581 ctxt.info.valid_sections |=
4582 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4583 /* user_param carries flag to enable loop back */
4585 ctxt.info.switch_id =
4586 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4587 ctxt.info.switch_id |=
4588 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4591 /* Configure port/vlan */
4592 ctxt.info.valid_sections |=
4593 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4594 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4595 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4596 I40E_DEFAULT_TCMAP);
4597 if (ret != I40E_SUCCESS) {
4598 PMD_DRV_LOG(ERR, "Failed to configure "
4599 "TC queue mapping");
4600 goto fail_msix_alloc;
4602 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4603 ctxt.info.valid_sections |=
4604 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4605 } else if (type == I40E_VSI_FDIR) {
4606 memset(&ctxt, 0, sizeof(ctxt));
4607 vsi->uplink_seid = uplink_vsi->uplink_seid;
4608 ctxt.pf_num = hw->pf_id;
4610 ctxt.uplink_seid = vsi->uplink_seid;
4611 ctxt.connection_type = 0x1; /* regular data port */
4612 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4613 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4614 I40E_DEFAULT_TCMAP);
4615 if (ret != I40E_SUCCESS) {
4616 PMD_DRV_LOG(ERR, "Failed to configure "
4617 "TC queue mapping.");
4618 goto fail_msix_alloc;
4620 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4621 ctxt.info.valid_sections |=
4622 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4624 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4625 goto fail_msix_alloc;
4628 if (vsi->type != I40E_VSI_MAIN) {
4629 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4630 if (ret != I40E_SUCCESS) {
4631 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4632 hw->aq.asq_last_status);
4633 goto fail_msix_alloc;
4635 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4636 vsi->info.valid_sections = 0;
4637 vsi->seid = ctxt.seid;
4638 vsi->vsi_id = ctxt.vsi_number;
4639 vsi->sib_vsi_list.vsi = vsi;
4640 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4641 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4642 &vsi->sib_vsi_list, list);
4644 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4645 &vsi->sib_vsi_list, list);
4649 /* MAC/VLAN configuration */
4650 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4651 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4653 ret = i40e_vsi_add_mac(vsi, &filter);
4654 if (ret != I40E_SUCCESS) {
4655 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4656 goto fail_msix_alloc;
4659 /* Get VSI BW information */
4660 i40e_vsi_get_bw_config(vsi);
4663 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4665 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4671 /* Configure vlan filter on or off */
4673 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4676 struct i40e_mac_filter *f;
4678 struct i40e_mac_filter_info *mac_filter;
4679 enum rte_mac_filter_type desired_filter;
4680 int ret = I40E_SUCCESS;
4683 /* Filter to match MAC and VLAN */
4684 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4686 /* Filter to match only MAC */
4687 desired_filter = RTE_MAC_PERFECT_MATCH;
4692 mac_filter = rte_zmalloc("mac_filter_info_data",
4693 num * sizeof(*mac_filter), 0);
4694 if (mac_filter == NULL) {
4695 PMD_DRV_LOG(ERR, "failed to allocate memory");
4696 return I40E_ERR_NO_MEMORY;
4701 /* Remove all existing mac */
4702 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4703 mac_filter[i] = f->mac_info;
4704 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4706 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4707 on ? "enable" : "disable");
4713 /* Override with new filter */
4714 for (i = 0; i < num; i++) {
4715 mac_filter[i].filter_type = desired_filter;
4716 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4718 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4719 on ? "enable" : "disable");
4725 rte_free(mac_filter);
4729 /* Configure vlan stripping on or off */
4731 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4733 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4734 struct i40e_vsi_context ctxt;
4736 int ret = I40E_SUCCESS;
4738 /* Check if it has been already on or off */
4739 if (vsi->info.valid_sections &
4740 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4742 if ((vsi->info.port_vlan_flags &
4743 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4744 return 0; /* already on */
4746 if ((vsi->info.port_vlan_flags &
4747 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4748 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4749 return 0; /* already off */
4754 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4756 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4757 vsi->info.valid_sections =
4758 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4759 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4760 vsi->info.port_vlan_flags |= vlan_flags;
4761 ctxt.seid = vsi->seid;
4762 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4763 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4765 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4766 on ? "enable" : "disable");
4772 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4774 struct rte_eth_dev_data *data = dev->data;
4778 /* Apply vlan offload setting */
4779 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4780 i40e_vlan_offload_set(dev, mask);
4782 /* Apply double-vlan setting, not implemented yet */
4784 /* Apply pvid setting */
4785 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4786 data->dev_conf.txmode.hw_vlan_insert_pvid);
4788 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4794 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4796 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4798 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4802 i40e_update_flow_control(struct i40e_hw *hw)
4804 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4805 struct i40e_link_status link_status;
4806 uint32_t rxfc = 0, txfc = 0, reg;
4810 memset(&link_status, 0, sizeof(link_status));
4811 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4812 if (ret != I40E_SUCCESS) {
4813 PMD_DRV_LOG(ERR, "Failed to get link status information");
4814 goto write_reg; /* Disable flow control */
4817 an_info = hw->phy.link_info.an_info;
4818 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4819 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4820 ret = I40E_ERR_NOT_READY;
4821 goto write_reg; /* Disable flow control */
4824 * If link auto negotiation is enabled, flow control needs to
4825 * be configured according to it
4827 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4828 case I40E_LINK_PAUSE_RXTX:
4831 hw->fc.current_mode = I40E_FC_FULL;
4833 case I40E_AQ_LINK_PAUSE_RX:
4835 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4837 case I40E_AQ_LINK_PAUSE_TX:
4839 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4842 hw->fc.current_mode = I40E_FC_NONE;
4847 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4848 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4849 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4850 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4851 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4852 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4859 i40e_pf_setup(struct i40e_pf *pf)
4861 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4862 struct i40e_filter_control_settings settings;
4863 struct i40e_vsi *vsi;
4866 /* Clear all stats counters */
4867 pf->offset_loaded = FALSE;
4868 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4869 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4871 ret = i40e_pf_get_switch_config(pf);
4872 if (ret != I40E_SUCCESS) {
4873 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4876 if (pf->flags & I40E_FLAG_FDIR) {
4877 /* make queue allocated first, let FDIR use queue pair 0*/
4878 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4879 if (ret != I40E_FDIR_QUEUE_ID) {
4880 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4882 pf->flags &= ~I40E_FLAG_FDIR;
4885 /* main VSI setup */
4886 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4888 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4889 return I40E_ERR_NOT_READY;
4893 /* Configure filter control */
4894 memset(&settings, 0, sizeof(settings));
4895 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4896 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4897 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4898 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4900 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4901 hw->func_caps.rss_table_size);
4902 return I40E_ERR_PARAM;
4904 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4905 "size: %u\n", hw->func_caps.rss_table_size);
4906 pf->hash_lut_size = hw->func_caps.rss_table_size;
4908 /* Enable ethtype and macvlan filters */
4909 settings.enable_ethtype = TRUE;
4910 settings.enable_macvlan = TRUE;
4911 ret = i40e_set_filter_control(hw, &settings);
4913 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4916 /* Update flow control according to the auto negotiation */
4917 i40e_update_flow_control(hw);
4919 return I40E_SUCCESS;
4923 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4929 * Set or clear TX Queue Disable flags,
4930 * which is required by hardware.
4932 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4933 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4935 /* Wait until the request is finished */
4936 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4937 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4938 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4939 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4940 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4946 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4947 return I40E_SUCCESS; /* already on, skip next steps */
4949 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4950 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4952 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4953 return I40E_SUCCESS; /* already off, skip next steps */
4954 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4956 /* Write the register */
4957 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4958 /* Check the result */
4959 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4960 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4961 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4963 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4964 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4967 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4968 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4972 /* Check if it is timeout */
4973 if (j >= I40E_CHK_Q_ENA_COUNT) {
4974 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4975 (on ? "enable" : "disable"), q_idx);
4976 return I40E_ERR_TIMEOUT;
4979 return I40E_SUCCESS;
4982 /* Swith on or off the tx queues */
4984 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4986 struct rte_eth_dev_data *dev_data = pf->dev_data;
4987 struct i40e_tx_queue *txq;
4988 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4992 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4993 txq = dev_data->tx_queues[i];
4994 /* Don't operate the queue if not configured or
4995 * if starting only per queue */
4996 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4999 ret = i40e_dev_tx_queue_start(dev, i);
5001 ret = i40e_dev_tx_queue_stop(dev, i);
5002 if ( ret != I40E_SUCCESS)
5006 return I40E_SUCCESS;
5010 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5015 /* Wait until the request is finished */
5016 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5017 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5018 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5019 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5020 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5025 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5026 return I40E_SUCCESS; /* Already on, skip next steps */
5027 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5029 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5030 return I40E_SUCCESS; /* Already off, skip next steps */
5031 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5034 /* Write the register */
5035 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5036 /* Check the result */
5037 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5038 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5039 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5041 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5042 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5045 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5046 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5051 /* Check if it is timeout */
5052 if (j >= I40E_CHK_Q_ENA_COUNT) {
5053 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5054 (on ? "enable" : "disable"), q_idx);
5055 return I40E_ERR_TIMEOUT;
5058 return I40E_SUCCESS;
5060 /* Switch on or off the rx queues */
5062 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5064 struct rte_eth_dev_data *dev_data = pf->dev_data;
5065 struct i40e_rx_queue *rxq;
5066 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5070 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5071 rxq = dev_data->rx_queues[i];
5072 /* Don't operate the queue if not configured or
5073 * if starting only per queue */
5074 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5077 ret = i40e_dev_rx_queue_start(dev, i);
5079 ret = i40e_dev_rx_queue_stop(dev, i);
5080 if (ret != I40E_SUCCESS)
5084 return I40E_SUCCESS;
5087 /* Switch on or off all the rx/tx queues */
5089 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5094 /* enable rx queues before enabling tx queues */
5095 ret = i40e_dev_switch_rx_queues(pf, on);
5097 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5100 ret = i40e_dev_switch_tx_queues(pf, on);
5102 /* Stop tx queues before stopping rx queues */
5103 ret = i40e_dev_switch_tx_queues(pf, on);
5105 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5108 ret = i40e_dev_switch_rx_queues(pf, on);
5114 /* Initialize VSI for TX */
5116 i40e_dev_tx_init(struct i40e_pf *pf)
5118 struct rte_eth_dev_data *data = pf->dev_data;
5120 uint32_t ret = I40E_SUCCESS;
5121 struct i40e_tx_queue *txq;
5123 for (i = 0; i < data->nb_tx_queues; i++) {
5124 txq = data->tx_queues[i];
5125 if (!txq || !txq->q_set)
5127 ret = i40e_tx_queue_init(txq);
5128 if (ret != I40E_SUCCESS)
5131 if (ret == I40E_SUCCESS)
5132 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5138 /* Initialize VSI for RX */
5140 i40e_dev_rx_init(struct i40e_pf *pf)
5142 struct rte_eth_dev_data *data = pf->dev_data;
5143 int ret = I40E_SUCCESS;
5145 struct i40e_rx_queue *rxq;
5147 i40e_pf_config_mq_rx(pf);
5148 for (i = 0; i < data->nb_rx_queues; i++) {
5149 rxq = data->rx_queues[i];
5150 if (!rxq || !rxq->q_set)
5153 ret = i40e_rx_queue_init(rxq);
5154 if (ret != I40E_SUCCESS) {
5155 PMD_DRV_LOG(ERR, "Failed to do RX queue "
5160 if (ret == I40E_SUCCESS)
5161 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5168 i40e_dev_rxtx_init(struct i40e_pf *pf)
5172 err = i40e_dev_tx_init(pf);
5174 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5177 err = i40e_dev_rx_init(pf);
5179 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5187 i40e_vmdq_setup(struct rte_eth_dev *dev)
5189 struct rte_eth_conf *conf = &dev->data->dev_conf;
5190 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5191 int i, err, conf_vsis, j, loop;
5192 struct i40e_vsi *vsi;
5193 struct i40e_vmdq_info *vmdq_info;
5194 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5195 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5198 * Disable interrupt to avoid message from VF. Furthermore, it will
5199 * avoid race condition in VSI creation/destroy.
5201 i40e_pf_disable_irq0(hw);
5203 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5204 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5208 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5209 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5210 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5211 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5212 pf->max_nb_vmdq_vsi);
5216 if (pf->vmdq != NULL) {
5217 PMD_INIT_LOG(INFO, "VMDQ already configured");
5221 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5222 sizeof(*vmdq_info) * conf_vsis, 0);
5224 if (pf->vmdq == NULL) {
5225 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5229 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5231 /* Create VMDQ VSI */
5232 for (i = 0; i < conf_vsis; i++) {
5233 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5234 vmdq_conf->enable_loop_back);
5236 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5240 vmdq_info = &pf->vmdq[i];
5242 vmdq_info->vsi = vsi;
5244 pf->nb_cfg_vmdq_vsi = conf_vsis;
5246 /* Configure Vlan */
5247 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5248 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5249 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5250 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5251 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5252 vmdq_conf->pool_map[i].vlan_id, j);
5254 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5255 vmdq_conf->pool_map[i].vlan_id);
5257 PMD_INIT_LOG(ERR, "Failed to add vlan");
5265 i40e_pf_enable_irq0(hw);
5270 for (i = 0; i < conf_vsis; i++)
5271 if (pf->vmdq[i].vsi == NULL)
5274 i40e_vsi_release(pf->vmdq[i].vsi);
5278 i40e_pf_enable_irq0(hw);
5283 i40e_stat_update_32(struct i40e_hw *hw,
5291 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5295 if (new_data >= *offset)
5296 *stat = (uint64_t)(new_data - *offset);
5298 *stat = (uint64_t)((new_data +
5299 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5303 i40e_stat_update_48(struct i40e_hw *hw,
5312 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5313 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5314 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5319 if (new_data >= *offset)
5320 *stat = new_data - *offset;
5322 *stat = (uint64_t)((new_data +
5323 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5325 *stat &= I40E_48_BIT_MASK;
5330 i40e_pf_disable_irq0(struct i40e_hw *hw)
5332 /* Disable all interrupt types */
5333 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5334 I40E_WRITE_FLUSH(hw);
5339 i40e_pf_enable_irq0(struct i40e_hw *hw)
5341 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5342 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5343 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5344 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5345 I40E_WRITE_FLUSH(hw);
5349 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5351 /* read pending request and disable first */
5352 i40e_pf_disable_irq0(hw);
5353 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5354 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5355 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5358 /* Link no queues with irq0 */
5359 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5360 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5364 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5366 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5367 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5370 uint32_t index, offset, val;
5375 * Try to find which VF trigger a reset, use absolute VF id to access
5376 * since the reg is global register.
5378 for (i = 0; i < pf->vf_num; i++) {
5379 abs_vf_id = hw->func_caps.vf_base_id + i;
5380 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5381 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5382 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5383 /* VFR event occured */
5384 if (val & (0x1 << offset)) {
5387 /* Clear the event first */
5388 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5390 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5392 * Only notify a VF reset event occured,
5393 * don't trigger another SW reset
5395 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5396 if (ret != I40E_SUCCESS)
5397 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5403 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5405 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5406 struct i40e_arq_event_info info;
5407 uint16_t pending, opcode;
5410 info.buf_len = I40E_AQ_BUF_SZ;
5411 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5412 if (!info.msg_buf) {
5413 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5419 ret = i40e_clean_arq_element(hw, &info, &pending);
5421 if (ret != I40E_SUCCESS) {
5422 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5423 "aq_err: %u", hw->aq.asq_last_status);
5426 opcode = rte_le_to_cpu_16(info.desc.opcode);
5429 case i40e_aqc_opc_send_msg_to_pf:
5430 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5431 i40e_pf_host_handle_vf_msg(dev,
5432 rte_le_to_cpu_16(info.desc.retval),
5433 rte_le_to_cpu_32(info.desc.cookie_high),
5434 rte_le_to_cpu_32(info.desc.cookie_low),
5439 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5444 rte_free(info.msg_buf);
5448 * Interrupt handler is registered as the alarm callback for handling LSC
5449 * interrupt in a definite of time, in order to wait the NIC into a stable
5450 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5451 * no need for link down interrupt.
5454 i40e_dev_interrupt_delayed_handler(void *param)
5456 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5457 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5460 /* read interrupt causes again */
5461 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5463 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5464 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5465 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5466 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5467 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5468 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5469 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5470 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5471 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5472 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5473 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5475 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5476 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5477 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5478 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5479 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5481 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5482 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5483 i40e_dev_handle_vfr_event(dev);
5485 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5486 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5487 i40e_dev_handle_aq_msg(dev);
5490 /* handle the link up interrupt in an alarm callback */
5491 i40e_dev_link_update(dev, 0);
5492 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5494 i40e_pf_enable_irq0(hw);
5495 rte_intr_enable(&(dev->pci_dev->intr_handle));
5499 * Interrupt handler triggered by NIC for handling
5500 * specific interrupt.
5503 * Pointer to interrupt handle.
5505 * The address of parameter (struct rte_eth_dev *) regsitered before.
5511 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5514 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5515 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5518 /* Disable interrupt */
5519 i40e_pf_disable_irq0(hw);
5521 /* read out interrupt causes */
5522 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5524 /* No interrupt event indicated */
5525 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5526 PMD_DRV_LOG(INFO, "No interrupt event");
5529 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5530 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5531 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5532 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5533 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5534 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5535 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5536 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5537 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5538 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5539 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5540 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5541 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5542 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5543 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5544 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5546 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5547 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5548 i40e_dev_handle_vfr_event(dev);
5550 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5551 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5552 i40e_dev_handle_aq_msg(dev);
5555 /* Link Status Change interrupt */
5556 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5557 #define I40E_US_PER_SECOND 1000000
5558 struct rte_eth_link link;
5560 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5561 memset(&link, 0, sizeof(link));
5562 rte_i40e_dev_atomic_read_link_status(dev, &link);
5563 i40e_dev_link_update(dev, 0);
5566 * For link up interrupt, it needs to wait 1 second to let the
5567 * hardware be a stable state. Otherwise several consecutive
5568 * interrupts can be observed.
5569 * For link down interrupt, no need to wait.
5571 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5572 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5575 _rte_eth_dev_callback_process(dev,
5576 RTE_ETH_EVENT_INTR_LSC);
5580 /* Enable interrupt */
5581 i40e_pf_enable_irq0(hw);
5582 rte_intr_enable(&(dev->pci_dev->intr_handle));
5586 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5587 struct i40e_macvlan_filter *filter,
5590 int ele_num, ele_buff_size;
5591 int num, actual_num, i;
5593 int ret = I40E_SUCCESS;
5594 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5595 struct i40e_aqc_add_macvlan_element_data *req_list;
5597 if (filter == NULL || total == 0)
5598 return I40E_ERR_PARAM;
5599 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5600 ele_buff_size = hw->aq.asq_buf_size;
5602 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5603 if (req_list == NULL) {
5604 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5605 return I40E_ERR_NO_MEMORY;
5610 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5611 memset(req_list, 0, ele_buff_size);
5613 for (i = 0; i < actual_num; i++) {
5614 (void)rte_memcpy(req_list[i].mac_addr,
5615 &filter[num + i].macaddr, ETH_ADDR_LEN);
5616 req_list[i].vlan_tag =
5617 rte_cpu_to_le_16(filter[num + i].vlan_id);
5619 switch (filter[num + i].filter_type) {
5620 case RTE_MAC_PERFECT_MATCH:
5621 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5622 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5624 case RTE_MACVLAN_PERFECT_MATCH:
5625 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5627 case RTE_MAC_HASH_MATCH:
5628 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5629 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5631 case RTE_MACVLAN_HASH_MATCH:
5632 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5635 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5636 ret = I40E_ERR_PARAM;
5640 req_list[i].queue_number = 0;
5642 req_list[i].flags = rte_cpu_to_le_16(flags);
5645 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5647 if (ret != I40E_SUCCESS) {
5648 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5652 } while (num < total);
5660 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5661 struct i40e_macvlan_filter *filter,
5664 int ele_num, ele_buff_size;
5665 int num, actual_num, i;
5667 int ret = I40E_SUCCESS;
5668 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5669 struct i40e_aqc_remove_macvlan_element_data *req_list;
5671 if (filter == NULL || total == 0)
5672 return I40E_ERR_PARAM;
5674 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5675 ele_buff_size = hw->aq.asq_buf_size;
5677 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5678 if (req_list == NULL) {
5679 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5680 return I40E_ERR_NO_MEMORY;
5685 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5686 memset(req_list, 0, ele_buff_size);
5688 for (i = 0; i < actual_num; i++) {
5689 (void)rte_memcpy(req_list[i].mac_addr,
5690 &filter[num + i].macaddr, ETH_ADDR_LEN);
5691 req_list[i].vlan_tag =
5692 rte_cpu_to_le_16(filter[num + i].vlan_id);
5694 switch (filter[num + i].filter_type) {
5695 case RTE_MAC_PERFECT_MATCH:
5696 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5697 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5699 case RTE_MACVLAN_PERFECT_MATCH:
5700 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5702 case RTE_MAC_HASH_MATCH:
5703 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5704 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5706 case RTE_MACVLAN_HASH_MATCH:
5707 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5710 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5711 ret = I40E_ERR_PARAM;
5714 req_list[i].flags = rte_cpu_to_le_16(flags);
5717 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5719 if (ret != I40E_SUCCESS) {
5720 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5724 } while (num < total);
5731 /* Find out specific MAC filter */
5732 static struct i40e_mac_filter *
5733 i40e_find_mac_filter(struct i40e_vsi *vsi,
5734 struct ether_addr *macaddr)
5736 struct i40e_mac_filter *f;
5738 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5739 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5747 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5750 uint32_t vid_idx, vid_bit;
5752 if (vlan_id > ETH_VLAN_ID_MAX)
5755 vid_idx = I40E_VFTA_IDX(vlan_id);
5756 vid_bit = I40E_VFTA_BIT(vlan_id);
5758 if (vsi->vfta[vid_idx] & vid_bit)
5765 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5766 uint16_t vlan_id, bool on)
5768 uint32_t vid_idx, vid_bit;
5770 if (vlan_id > ETH_VLAN_ID_MAX)
5773 vid_idx = I40E_VFTA_IDX(vlan_id);
5774 vid_bit = I40E_VFTA_BIT(vlan_id);
5777 vsi->vfta[vid_idx] |= vid_bit;
5779 vsi->vfta[vid_idx] &= ~vid_bit;
5783 * Find all vlan options for specific mac addr,
5784 * return with actual vlan found.
5787 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5788 struct i40e_macvlan_filter *mv_f,
5789 int num, struct ether_addr *addr)
5795 * Not to use i40e_find_vlan_filter to decrease the loop time,
5796 * although the code looks complex.
5798 if (num < vsi->vlan_num)
5799 return I40E_ERR_PARAM;
5802 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5804 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5805 if (vsi->vfta[j] & (1 << k)) {
5807 PMD_DRV_LOG(ERR, "vlan number "
5809 return I40E_ERR_PARAM;
5811 (void)rte_memcpy(&mv_f[i].macaddr,
5812 addr, ETH_ADDR_LEN);
5814 j * I40E_UINT32_BIT_SIZE + k;
5820 return I40E_SUCCESS;
5824 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5825 struct i40e_macvlan_filter *mv_f,
5830 struct i40e_mac_filter *f;
5832 if (num < vsi->mac_num)
5833 return I40E_ERR_PARAM;
5835 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5837 PMD_DRV_LOG(ERR, "buffer number not match");
5838 return I40E_ERR_PARAM;
5840 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5842 mv_f[i].vlan_id = vlan;
5843 mv_f[i].filter_type = f->mac_info.filter_type;
5847 return I40E_SUCCESS;
5851 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5854 struct i40e_mac_filter *f;
5855 struct i40e_macvlan_filter *mv_f;
5856 int ret = I40E_SUCCESS;
5858 if (vsi == NULL || vsi->mac_num == 0)
5859 return I40E_ERR_PARAM;
5861 /* Case that no vlan is set */
5862 if (vsi->vlan_num == 0)
5865 num = vsi->mac_num * vsi->vlan_num;
5867 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5869 PMD_DRV_LOG(ERR, "failed to allocate memory");
5870 return I40E_ERR_NO_MEMORY;
5874 if (vsi->vlan_num == 0) {
5875 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5876 (void)rte_memcpy(&mv_f[i].macaddr,
5877 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5878 mv_f[i].vlan_id = 0;
5882 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5883 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5884 vsi->vlan_num, &f->mac_info.mac_addr);
5885 if (ret != I40E_SUCCESS)
5891 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5899 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5901 struct i40e_macvlan_filter *mv_f;
5903 int ret = I40E_SUCCESS;
5905 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5906 return I40E_ERR_PARAM;
5908 /* If it's already set, just return */
5909 if (i40e_find_vlan_filter(vsi,vlan))
5910 return I40E_SUCCESS;
5912 mac_num = vsi->mac_num;
5915 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5916 return I40E_ERR_PARAM;
5919 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5922 PMD_DRV_LOG(ERR, "failed to allocate memory");
5923 return I40E_ERR_NO_MEMORY;
5926 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5928 if (ret != I40E_SUCCESS)
5931 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5933 if (ret != I40E_SUCCESS)
5936 i40e_set_vlan_filter(vsi, vlan, 1);
5946 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5948 struct i40e_macvlan_filter *mv_f;
5950 int ret = I40E_SUCCESS;
5953 * Vlan 0 is the generic filter for untagged packets
5954 * and can't be removed.
5956 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5957 return I40E_ERR_PARAM;
5959 /* If can't find it, just return */
5960 if (!i40e_find_vlan_filter(vsi, vlan))
5961 return I40E_ERR_PARAM;
5963 mac_num = vsi->mac_num;
5966 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5967 return I40E_ERR_PARAM;
5970 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5973 PMD_DRV_LOG(ERR, "failed to allocate memory");
5974 return I40E_ERR_NO_MEMORY;
5977 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5979 if (ret != I40E_SUCCESS)
5982 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5984 if (ret != I40E_SUCCESS)
5987 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5988 if (vsi->vlan_num == 1) {
5989 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5990 if (ret != I40E_SUCCESS)
5993 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5994 if (ret != I40E_SUCCESS)
5998 i40e_set_vlan_filter(vsi, vlan, 0);
6008 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6010 struct i40e_mac_filter *f;
6011 struct i40e_macvlan_filter *mv_f;
6012 int i, vlan_num = 0;
6013 int ret = I40E_SUCCESS;
6015 /* If it's add and we've config it, return */
6016 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6018 return I40E_SUCCESS;
6019 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6020 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6023 * If vlan_num is 0, that's the first time to add mac,
6024 * set mask for vlan_id 0.
6026 if (vsi->vlan_num == 0) {
6027 i40e_set_vlan_filter(vsi, 0, 1);
6030 vlan_num = vsi->vlan_num;
6031 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6032 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6035 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6037 PMD_DRV_LOG(ERR, "failed to allocate memory");
6038 return I40E_ERR_NO_MEMORY;
6041 for (i = 0; i < vlan_num; i++) {
6042 mv_f[i].filter_type = mac_filter->filter_type;
6043 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6047 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6048 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6049 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6050 &mac_filter->mac_addr);
6051 if (ret != I40E_SUCCESS)
6055 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6056 if (ret != I40E_SUCCESS)
6059 /* Add the mac addr into mac list */
6060 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6062 PMD_DRV_LOG(ERR, "failed to allocate memory");
6063 ret = I40E_ERR_NO_MEMORY;
6066 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6068 f->mac_info.filter_type = mac_filter->filter_type;
6069 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6080 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6082 struct i40e_mac_filter *f;
6083 struct i40e_macvlan_filter *mv_f;
6085 enum rte_mac_filter_type filter_type;
6086 int ret = I40E_SUCCESS;
6088 /* Can't find it, return an error */
6089 f = i40e_find_mac_filter(vsi, addr);
6091 return I40E_ERR_PARAM;
6093 vlan_num = vsi->vlan_num;
6094 filter_type = f->mac_info.filter_type;
6095 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6096 filter_type == RTE_MACVLAN_HASH_MATCH) {
6097 if (vlan_num == 0) {
6098 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6099 return I40E_ERR_PARAM;
6101 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6102 filter_type == RTE_MAC_HASH_MATCH)
6105 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6107 PMD_DRV_LOG(ERR, "failed to allocate memory");
6108 return I40E_ERR_NO_MEMORY;
6111 for (i = 0; i < vlan_num; i++) {
6112 mv_f[i].filter_type = filter_type;
6113 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6116 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6117 filter_type == RTE_MACVLAN_HASH_MATCH) {
6118 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6119 if (ret != I40E_SUCCESS)
6123 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6124 if (ret != I40E_SUCCESS)
6127 /* Remove the mac addr into mac list */
6128 TAILQ_REMOVE(&vsi->mac_list, f, next);
6138 /* Configure hash enable flags for RSS */
6140 i40e_config_hena(uint64_t flags)
6147 if (flags & ETH_RSS_FRAG_IPV4)
6148 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6149 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6151 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6152 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6154 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6156 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6158 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6159 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6160 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6162 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6164 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6165 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6166 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6167 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6168 if (flags & ETH_RSS_FRAG_IPV6)
6169 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6170 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6172 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6173 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6175 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6177 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6179 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6180 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6181 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6183 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6185 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6186 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6187 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6188 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6189 if (flags & ETH_RSS_L2_PAYLOAD)
6190 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6195 /* Parse the hash enable flags */
6197 i40e_parse_hena(uint64_t flags)
6199 uint64_t rss_hf = 0;
6203 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6204 rss_hf |= ETH_RSS_FRAG_IPV4;
6205 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6206 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6208 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6209 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6211 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6212 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6214 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6215 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6216 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6217 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6219 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6220 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6221 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6222 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6223 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6224 rss_hf |= ETH_RSS_FRAG_IPV6;
6225 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6226 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6228 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6229 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6231 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6232 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6234 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6235 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6236 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6237 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6239 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6240 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6241 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6242 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6243 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6244 rss_hf |= ETH_RSS_L2_PAYLOAD;
6251 i40e_pf_disable_rss(struct i40e_pf *pf)
6253 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6256 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6257 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6258 hena &= ~I40E_RSS_HENA_ALL;
6259 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6260 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6261 I40E_WRITE_FLUSH(hw);
6265 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6267 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6268 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6271 if (!key || key_len == 0) {
6272 PMD_DRV_LOG(DEBUG, "No key to be configured");
6274 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6276 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6280 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6281 struct i40e_aqc_get_set_rss_key_data *key_dw =
6282 (struct i40e_aqc_get_set_rss_key_data *)key;
6284 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6286 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6289 uint32_t *hash_key = (uint32_t *)key;
6292 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6293 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6294 I40E_WRITE_FLUSH(hw);
6301 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6303 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6304 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6307 if (!key || !key_len)
6310 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6311 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6312 (struct i40e_aqc_get_set_rss_key_data *)key);
6314 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6318 uint32_t *key_dw = (uint32_t *)key;
6321 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6322 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6324 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6330 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6332 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6337 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6338 rss_conf->rss_key_len);
6342 rss_hf = rss_conf->rss_hf;
6343 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6344 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6345 hena &= ~I40E_RSS_HENA_ALL;
6346 hena |= i40e_config_hena(rss_hf);
6347 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6348 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6349 I40E_WRITE_FLUSH(hw);
6355 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6356 struct rte_eth_rss_conf *rss_conf)
6358 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6359 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6360 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6363 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6364 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6365 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6366 if (rss_hf != 0) /* Enable RSS */
6368 return 0; /* Nothing to do */
6371 if (rss_hf == 0) /* Disable RSS */
6374 return i40e_hw_rss_hash_set(pf, rss_conf);
6378 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6379 struct rte_eth_rss_conf *rss_conf)
6381 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6382 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6385 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6386 &rss_conf->rss_key_len);
6388 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6389 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6390 rss_conf->rss_hf = i40e_parse_hena(hena);
6396 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6398 switch (filter_type) {
6399 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6400 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6402 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6403 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6405 case RTE_TUNNEL_FILTER_IMAC_TENID:
6406 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6408 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6409 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6411 case ETH_TUNNEL_FILTER_IMAC:
6412 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6414 case ETH_TUNNEL_FILTER_OIP:
6415 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6417 case ETH_TUNNEL_FILTER_IIP:
6418 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6421 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6429 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6430 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6435 uint8_t i, tun_type = 0;
6436 /* internal varialbe to convert ipv6 byte order */
6437 uint32_t convert_ipv6[4];
6439 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6440 struct i40e_vsi *vsi = pf->main_vsi;
6441 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6442 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6444 cld_filter = rte_zmalloc("tunnel_filter",
6445 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6448 if (NULL == cld_filter) {
6449 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6452 pfilter = cld_filter;
6454 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6455 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6457 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6458 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6459 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6460 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6461 rte_memcpy(&pfilter->ipaddr.v4.data,
6462 &rte_cpu_to_le_32(ipv4_addr),
6463 sizeof(pfilter->ipaddr.v4.data));
6465 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6466 for (i = 0; i < 4; i++) {
6468 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6470 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6471 sizeof(pfilter->ipaddr.v6.data));
6474 /* check tunneled type */
6475 switch (tunnel_filter->tunnel_type) {
6476 case RTE_TUNNEL_TYPE_VXLAN:
6477 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6479 case RTE_TUNNEL_TYPE_NVGRE:
6480 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6482 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6483 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6486 /* Other tunnel types is not supported. */
6487 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6488 rte_free(cld_filter);
6492 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6495 rte_free(cld_filter);
6499 pfilter->flags |= rte_cpu_to_le_16(
6500 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6501 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6502 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6503 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6506 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6508 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6511 rte_free(cld_filter);
6516 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6520 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6521 if (pf->vxlan_ports[i] == port)
6529 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6533 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6535 idx = i40e_get_vxlan_port_idx(pf, port);
6537 /* Check if port already exists */
6539 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6543 /* Now check if there is space to add the new port */
6544 idx = i40e_get_vxlan_port_idx(pf, 0);
6546 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6547 "not adding port %d", port);
6551 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6554 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6558 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6561 /* New port: add it and mark its index in the bitmap */
6562 pf->vxlan_ports[idx] = port;
6563 pf->vxlan_bitmap |= (1 << idx);
6565 if (!(pf->flags & I40E_FLAG_VXLAN))
6566 pf->flags |= I40E_FLAG_VXLAN;
6572 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6575 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6577 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6578 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6582 idx = i40e_get_vxlan_port_idx(pf, port);
6585 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6589 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6590 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6594 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6597 pf->vxlan_ports[idx] = 0;
6598 pf->vxlan_bitmap &= ~(1 << idx);
6600 if (!pf->vxlan_bitmap)
6601 pf->flags &= ~I40E_FLAG_VXLAN;
6606 /* Add UDP tunneling port */
6608 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6609 struct rte_eth_udp_tunnel *udp_tunnel)
6612 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6614 if (udp_tunnel == NULL)
6617 switch (udp_tunnel->prot_type) {
6618 case RTE_TUNNEL_TYPE_VXLAN:
6619 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6622 case RTE_TUNNEL_TYPE_GENEVE:
6623 case RTE_TUNNEL_TYPE_TEREDO:
6624 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6629 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6637 /* Remove UDP tunneling port */
6639 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6640 struct rte_eth_udp_tunnel *udp_tunnel)
6643 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6645 if (udp_tunnel == NULL)
6648 switch (udp_tunnel->prot_type) {
6649 case RTE_TUNNEL_TYPE_VXLAN:
6650 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6652 case RTE_TUNNEL_TYPE_GENEVE:
6653 case RTE_TUNNEL_TYPE_TEREDO:
6654 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6658 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6666 /* Calculate the maximum number of contiguous PF queues that are configured */
6668 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6670 struct rte_eth_dev_data *data = pf->dev_data;
6672 struct i40e_rx_queue *rxq;
6675 for (i = 0; i < pf->lan_nb_qps; i++) {
6676 rxq = data->rx_queues[i];
6677 if (rxq && rxq->q_set)
6688 i40e_pf_config_rss(struct i40e_pf *pf)
6690 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6691 struct rte_eth_rss_conf rss_conf;
6692 uint32_t i, lut = 0;
6696 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6697 * It's necessary to calulate the actual PF queues that are configured.
6699 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6700 num = i40e_pf_calc_configured_queues_num(pf);
6702 num = pf->dev_data->nb_rx_queues;
6704 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6705 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6709 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6713 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6716 lut = (lut << 8) | (j & ((0x1 <<
6717 hw->func_caps.rss_table_entry_width) - 1));
6719 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6722 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6723 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6724 i40e_pf_disable_rss(pf);
6727 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6728 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6729 /* Random default keys */
6730 static uint32_t rss_key_default[] = {0x6b793944,
6731 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6732 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6733 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6735 rss_conf.rss_key = (uint8_t *)rss_key_default;
6736 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6740 return i40e_hw_rss_hash_set(pf, &rss_conf);
6744 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6745 struct rte_eth_tunnel_filter_conf *filter)
6747 if (pf == NULL || filter == NULL) {
6748 PMD_DRV_LOG(ERR, "Invalid parameter");
6752 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6753 PMD_DRV_LOG(ERR, "Invalid queue ID");
6757 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6758 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6762 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6763 (is_zero_ether_addr(&filter->outer_mac))) {
6764 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6768 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6769 (is_zero_ether_addr(&filter->inner_mac))) {
6770 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6777 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6778 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6780 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6785 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6786 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6789 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6790 } else if (len == 4) {
6791 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6793 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6798 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6805 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6806 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6812 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6819 switch (cfg->cfg_type) {
6820 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6821 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6824 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6832 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6833 enum rte_filter_op filter_op,
6836 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6837 int ret = I40E_ERR_PARAM;
6839 switch (filter_op) {
6840 case RTE_ETH_FILTER_SET:
6841 ret = i40e_dev_global_config_set(hw,
6842 (struct rte_eth_global_cfg *)arg);
6845 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6853 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6854 enum rte_filter_op filter_op,
6857 struct rte_eth_tunnel_filter_conf *filter;
6858 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6859 int ret = I40E_SUCCESS;
6861 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6863 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6864 return I40E_ERR_PARAM;
6866 switch (filter_op) {
6867 case RTE_ETH_FILTER_NOP:
6868 if (!(pf->flags & I40E_FLAG_VXLAN))
6869 ret = I40E_NOT_SUPPORTED;
6871 case RTE_ETH_FILTER_ADD:
6872 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6874 case RTE_ETH_FILTER_DELETE:
6875 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6878 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6879 ret = I40E_ERR_PARAM;
6887 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6890 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6893 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6894 ret = i40e_pf_config_rss(pf);
6896 i40e_pf_disable_rss(pf);
6901 /* Get the symmetric hash enable configurations per port */
6903 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6905 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6907 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6910 /* Set the symmetric hash enable configurations per port */
6912 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6914 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6917 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6918 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6922 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6924 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6925 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6929 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6931 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6932 I40E_WRITE_FLUSH(hw);
6936 * Get global configurations of hash function type and symmetric hash enable
6937 * per flow type (pctype). Note that global configuration means it affects all
6938 * the ports on the same NIC.
6941 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6942 struct rte_eth_hash_global_conf *g_cfg)
6944 uint32_t reg, mask = I40E_FLOW_TYPES;
6946 enum i40e_filter_pctype pctype;
6948 memset(g_cfg, 0, sizeof(*g_cfg));
6949 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6950 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6951 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6953 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6954 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6955 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6957 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6958 if (!(mask & (1UL << i)))
6960 mask &= ~(1UL << i);
6961 /* Bit set indicats the coresponding flow type is supported */
6962 g_cfg->valid_bit_mask[0] |= (1UL << i);
6963 /* if flowtype is invalid, continue */
6964 if (!I40E_VALID_FLOW(i))
6966 pctype = i40e_flowtype_to_pctype(i);
6967 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6968 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6969 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6976 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6979 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6981 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6982 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6983 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6984 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6990 * As i40e supports less than 32 flow types, only first 32 bits need to
6993 mask0 = g_cfg->valid_bit_mask[0];
6994 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6996 /* Check if any unsupported flow type configured */
6997 if ((mask0 | i40e_mask) ^ i40e_mask)
7000 if (g_cfg->valid_bit_mask[i])
7008 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7014 * Set global configurations of hash function type and symmetric hash enable
7015 * per flow type (pctype). Note any modifying global configuration will affect
7016 * all the ports on the same NIC.
7019 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7020 struct rte_eth_hash_global_conf *g_cfg)
7025 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7026 enum i40e_filter_pctype pctype;
7028 /* Check the input parameters */
7029 ret = i40e_hash_global_config_check(g_cfg);
7033 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7034 if (!(mask0 & (1UL << i)))
7036 mask0 &= ~(1UL << i);
7037 /* if flowtype is invalid, continue */
7038 if (!I40E_VALID_FLOW(i))
7040 pctype = i40e_flowtype_to_pctype(i);
7041 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7042 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7043 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7046 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7047 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7049 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7050 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7054 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7055 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7057 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7058 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7062 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7064 /* Use the default, and keep it as it is */
7067 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7070 I40E_WRITE_FLUSH(hw);
7076 * Valid input sets for hash and flow director filters per PCTYPE
7079 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7080 enum rte_filter_type filter)
7084 static const uint64_t valid_hash_inset_table[] = {
7085 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7086 I40E_INSET_DMAC | I40E_INSET_SMAC |
7087 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7088 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7089 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7090 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7091 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7092 I40E_INSET_FLEX_PAYLOAD,
7093 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7094 I40E_INSET_DMAC | I40E_INSET_SMAC |
7095 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7096 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7097 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7098 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7099 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7100 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7101 I40E_INSET_FLEX_PAYLOAD,
7103 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7104 I40E_INSET_DMAC | I40E_INSET_SMAC |
7105 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7106 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7107 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7108 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7109 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7110 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7111 I40E_INSET_FLEX_PAYLOAD,
7112 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7113 I40E_INSET_DMAC | I40E_INSET_SMAC |
7114 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7115 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7116 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7117 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7118 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7119 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7120 I40E_INSET_FLEX_PAYLOAD,
7122 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7123 I40E_INSET_DMAC | I40E_INSET_SMAC |
7124 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7125 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7126 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7127 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7128 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7129 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7130 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7132 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7133 I40E_INSET_DMAC | I40E_INSET_SMAC |
7134 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7135 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7136 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7137 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7138 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7139 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7140 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7142 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7143 I40E_INSET_DMAC | I40E_INSET_SMAC |
7144 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7145 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7146 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7147 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7148 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7149 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7150 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7151 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7152 I40E_INSET_DMAC | I40E_INSET_SMAC |
7153 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7154 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7155 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7156 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7157 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7158 I40E_INSET_FLEX_PAYLOAD,
7159 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7160 I40E_INSET_DMAC | I40E_INSET_SMAC |
7161 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7162 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7163 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7164 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7165 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7166 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7167 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7168 I40E_INSET_DMAC | I40E_INSET_SMAC |
7169 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7170 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7171 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7172 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7173 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7174 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7176 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7177 I40E_INSET_DMAC | I40E_INSET_SMAC |
7178 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7179 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7180 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7181 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7182 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7183 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7184 I40E_INSET_FLEX_PAYLOAD,
7185 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7186 I40E_INSET_DMAC | I40E_INSET_SMAC |
7187 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7188 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7189 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7190 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7191 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7192 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7193 I40E_INSET_FLEX_PAYLOAD,
7195 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7196 I40E_INSET_DMAC | I40E_INSET_SMAC |
7197 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7198 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7199 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7200 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7201 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7202 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7203 I40E_INSET_FLEX_PAYLOAD,
7205 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7206 I40E_INSET_DMAC | I40E_INSET_SMAC |
7207 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7208 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7209 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7210 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7211 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7212 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7213 I40E_INSET_FLEX_PAYLOAD,
7215 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7216 I40E_INSET_DMAC | I40E_INSET_SMAC |
7217 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7218 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7219 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7220 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7221 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7222 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7223 I40E_INSET_FLEX_PAYLOAD,
7224 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7225 I40E_INSET_DMAC | I40E_INSET_SMAC |
7226 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7227 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7228 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7229 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7230 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7231 I40E_INSET_FLEX_PAYLOAD,
7232 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7233 I40E_INSET_DMAC | I40E_INSET_SMAC |
7234 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7235 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7236 I40E_INSET_FLEX_PAYLOAD,
7240 * Flow director supports only fields defined in
7241 * union rte_eth_fdir_flow.
7243 static const uint64_t valid_fdir_inset_table[] = {
7244 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7245 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7246 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7247 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7248 I40E_INSET_IPV4_TTL,
7249 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7250 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7251 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7252 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7253 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7255 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7256 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7257 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7258 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7259 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7260 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7261 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7262 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7263 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7264 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7266 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7267 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7268 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7269 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7270 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7272 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7273 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7274 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7275 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7276 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7278 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7279 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7280 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7281 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7282 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7284 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7285 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7286 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7287 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7288 I40E_INSET_IPV4_TTL,
7289 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7290 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7291 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7292 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7293 I40E_INSET_IPV6_HOP_LIMIT,
7294 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7295 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7296 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7297 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7298 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7300 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7301 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7302 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7303 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7304 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7305 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7306 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7307 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7308 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7309 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7311 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7312 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7313 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7314 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7315 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7317 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7318 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7319 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7320 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7321 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7323 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7324 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7325 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7326 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7327 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7329 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7330 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7331 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7332 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7333 I40E_INSET_IPV6_HOP_LIMIT,
7334 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7335 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7336 I40E_INSET_LAST_ETHER_TYPE,
7339 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7341 if (filter == RTE_ETH_FILTER_HASH)
7342 valid = valid_hash_inset_table[pctype];
7344 valid = valid_fdir_inset_table[pctype];
7350 * Validate if the input set is allowed for a specific PCTYPE
7353 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7354 enum rte_filter_type filter, uint64_t inset)
7358 valid = i40e_get_valid_input_set(pctype, filter);
7359 if (inset & (~valid))
7365 /* default input set fields combination per pctype */
7367 i40e_get_default_input_set(uint16_t pctype)
7369 static const uint64_t default_inset_table[] = {
7370 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7371 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7372 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7373 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7374 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7376 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7377 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7378 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7379 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7380 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7381 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7383 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7384 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7385 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7387 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7388 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7389 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7391 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7392 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7393 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7395 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7396 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7397 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7398 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7399 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7400 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7401 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7403 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7404 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7405 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7406 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7407 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7408 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7410 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7411 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7412 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7414 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7415 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7416 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7418 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7419 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7420 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7422 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7423 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7424 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7425 I40E_INSET_LAST_ETHER_TYPE,
7428 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7431 return default_inset_table[pctype];
7435 * Parse the input set from index to logical bit masks
7438 i40e_parse_input_set(uint64_t *inset,
7439 enum i40e_filter_pctype pctype,
7440 enum rte_eth_input_set_field *field,
7446 static const struct {
7447 enum rte_eth_input_set_field field;
7449 } inset_convert_table[] = {
7450 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7451 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7452 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7453 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7454 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7455 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7456 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7457 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7458 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7459 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7460 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7461 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7462 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7463 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7464 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7465 I40E_INSET_IPV6_NEXT_HDR},
7466 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7467 I40E_INSET_IPV6_HOP_LIMIT},
7468 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7469 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7470 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7471 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7472 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7473 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7474 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7475 I40E_INSET_SCTP_VT},
7476 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7477 I40E_INSET_TUNNEL_DMAC},
7478 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7479 I40E_INSET_VLAN_TUNNEL},
7480 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7481 I40E_INSET_TUNNEL_ID},
7482 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7483 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7484 I40E_INSET_FLEX_PAYLOAD_W1},
7485 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7486 I40E_INSET_FLEX_PAYLOAD_W2},
7487 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7488 I40E_INSET_FLEX_PAYLOAD_W3},
7489 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7490 I40E_INSET_FLEX_PAYLOAD_W4},
7491 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7492 I40E_INSET_FLEX_PAYLOAD_W5},
7493 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7494 I40E_INSET_FLEX_PAYLOAD_W6},
7495 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7496 I40E_INSET_FLEX_PAYLOAD_W7},
7497 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7498 I40E_INSET_FLEX_PAYLOAD_W8},
7501 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7504 /* Only one item allowed for default or all */
7506 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7507 *inset = i40e_get_default_input_set(pctype);
7509 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7510 *inset = I40E_INSET_NONE;
7515 for (i = 0, *inset = 0; i < size; i++) {
7516 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7517 if (field[i] == inset_convert_table[j].field) {
7518 *inset |= inset_convert_table[j].inset;
7523 /* It contains unsupported input set, return immediately */
7524 if (j == RTE_DIM(inset_convert_table))
7532 * Translate the input set from bit masks to register aware bit masks
7536 i40e_translate_input_set_reg(uint64_t input)
7541 static const struct {
7545 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7546 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7547 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7548 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7549 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7550 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7551 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7552 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7553 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7554 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7555 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7556 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7557 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7558 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7559 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7560 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7561 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7562 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7563 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7564 {I40E_INSET_TUNNEL_DMAC,
7565 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7566 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7567 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7568 {I40E_INSET_TUNNEL_SRC_PORT,
7569 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7570 {I40E_INSET_TUNNEL_DST_PORT,
7571 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7572 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7573 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7574 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7575 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7576 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7577 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7578 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7579 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7580 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7586 /* Translate input set to register aware inset */
7587 for (i = 0; i < RTE_DIM(inset_map); i++) {
7588 if (input & inset_map[i].inset)
7589 val |= inset_map[i].inset_reg;
7596 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7599 uint64_t inset_need_mask = inset;
7601 static const struct {
7604 } inset_mask_map[] = {
7605 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7606 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7607 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7608 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7609 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7610 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7611 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7612 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7615 if (!inset || !mask || !nb_elem)
7618 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7619 /* Clear the inset bit, if no MASK is required,
7620 * for example proto + ttl
7622 if ((inset & inset_mask_map[i].inset) ==
7623 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7624 inset_need_mask &= ~inset_mask_map[i].inset;
7625 if (!inset_need_mask)
7628 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7629 if ((inset_need_mask & inset_mask_map[i].inset) ==
7630 inset_mask_map[i].inset) {
7631 if (idx >= nb_elem) {
7632 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7635 mask[idx] = inset_mask_map[i].mask;
7644 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7646 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7648 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7650 i40e_write_rx_ctl(hw, addr, val);
7651 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7652 (uint32_t)i40e_read_rx_ctl(hw, addr));
7656 i40e_filter_input_set_init(struct i40e_pf *pf)
7658 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7659 enum i40e_filter_pctype pctype;
7660 uint64_t input_set, inset_reg;
7661 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7664 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7665 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7666 if (!I40E_VALID_PCTYPE(pctype))
7668 input_set = i40e_get_default_input_set(pctype);
7670 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7671 I40E_INSET_MASK_NUM_REG);
7674 inset_reg = i40e_translate_input_set_reg(input_set);
7676 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7677 (uint32_t)(inset_reg & UINT32_MAX));
7678 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7679 (uint32_t)((inset_reg >>
7680 I40E_32_BIT_WIDTH) & UINT32_MAX));
7681 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7682 (uint32_t)(inset_reg & UINT32_MAX));
7683 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7684 (uint32_t)((inset_reg >>
7685 I40E_32_BIT_WIDTH) & UINT32_MAX));
7687 for (i = 0; i < num; i++) {
7688 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7690 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7693 /*clear unused mask registers of the pctype */
7694 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7695 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7697 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7700 I40E_WRITE_FLUSH(hw);
7702 /* store the default input set */
7703 pf->hash_input_set[pctype] = input_set;
7704 pf->fdir.input_set[pctype] = input_set;
7709 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7710 struct rte_eth_input_set_conf *conf)
7712 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7713 enum i40e_filter_pctype pctype;
7714 uint64_t input_set, inset_reg = 0;
7715 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7719 PMD_DRV_LOG(ERR, "Invalid pointer");
7722 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7723 conf->op != RTE_ETH_INPUT_SET_ADD) {
7724 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7728 if (!I40E_VALID_FLOW(conf->flow_type)) {
7729 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7734 /* get translated pctype value in fd pctype register */
7735 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7736 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7739 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7742 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7745 PMD_DRV_LOG(ERR, "Failed to parse input set");
7748 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7750 PMD_DRV_LOG(ERR, "Invalid input set");
7753 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7754 /* get inset value in register */
7755 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7756 inset_reg <<= I40E_32_BIT_WIDTH;
7757 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7758 input_set |= pf->hash_input_set[pctype];
7760 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7761 I40E_INSET_MASK_NUM_REG);
7765 inset_reg |= i40e_translate_input_set_reg(input_set);
7767 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7768 (uint32_t)(inset_reg & UINT32_MAX));
7769 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7770 (uint32_t)((inset_reg >>
7771 I40E_32_BIT_WIDTH) & UINT32_MAX));
7773 for (i = 0; i < num; i++)
7774 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7776 /*clear unused mask registers of the pctype */
7777 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7778 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7780 I40E_WRITE_FLUSH(hw);
7782 pf->hash_input_set[pctype] = input_set;
7787 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7788 struct rte_eth_input_set_conf *conf)
7790 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7791 enum i40e_filter_pctype pctype;
7792 uint64_t input_set, inset_reg = 0;
7793 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7797 PMD_DRV_LOG(ERR, "Invalid pointer");
7800 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7801 conf->op != RTE_ETH_INPUT_SET_ADD) {
7802 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7806 if (!I40E_VALID_FLOW(conf->flow_type)) {
7807 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7811 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7813 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7816 PMD_DRV_LOG(ERR, "Failed to parse input set");
7819 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7821 PMD_DRV_LOG(ERR, "Invalid input set");
7825 /* get inset value in register */
7826 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7827 inset_reg <<= I40E_32_BIT_WIDTH;
7828 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7830 /* Can not change the inset reg for flex payload for fdir,
7831 * it is done by writing I40E_PRTQF_FD_FLXINSET
7832 * in i40e_set_flex_mask_on_pctype.
7834 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7835 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7837 input_set |= pf->fdir.input_set[pctype];
7838 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7839 I40E_INSET_MASK_NUM_REG);
7843 inset_reg |= i40e_translate_input_set_reg(input_set);
7845 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7846 (uint32_t)(inset_reg & UINT32_MAX));
7847 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7848 (uint32_t)((inset_reg >>
7849 I40E_32_BIT_WIDTH) & UINT32_MAX));
7851 for (i = 0; i < num; i++)
7852 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7854 /*clear unused mask registers of the pctype */
7855 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7856 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7858 I40E_WRITE_FLUSH(hw);
7860 pf->fdir.input_set[pctype] = input_set;
7865 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7870 PMD_DRV_LOG(ERR, "Invalid pointer");
7874 switch (info->info_type) {
7875 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7876 i40e_get_symmetric_hash_enable_per_port(hw,
7877 &(info->info.enable));
7879 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7880 ret = i40e_get_hash_filter_global_config(hw,
7881 &(info->info.global_conf));
7884 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7894 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7899 PMD_DRV_LOG(ERR, "Invalid pointer");
7903 switch (info->info_type) {
7904 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7905 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7907 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7908 ret = i40e_set_hash_filter_global_config(hw,
7909 &(info->info.global_conf));
7911 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7912 ret = i40e_hash_filter_inset_select(hw,
7913 &(info->info.input_set_conf));
7917 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7926 /* Operations for hash function */
7928 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7929 enum rte_filter_op filter_op,
7932 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7935 switch (filter_op) {
7936 case RTE_ETH_FILTER_NOP:
7938 case RTE_ETH_FILTER_GET:
7939 ret = i40e_hash_filter_get(hw,
7940 (struct rte_eth_hash_filter_info *)arg);
7942 case RTE_ETH_FILTER_SET:
7943 ret = i40e_hash_filter_set(hw,
7944 (struct rte_eth_hash_filter_info *)arg);
7947 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7957 * Configure ethertype filter, which can director packet by filtering
7958 * with mac address and ether_type or only ether_type
7961 i40e_ethertype_filter_set(struct i40e_pf *pf,
7962 struct rte_eth_ethertype_filter *filter,
7965 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7966 struct i40e_control_filter_stats stats;
7970 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7971 PMD_DRV_LOG(ERR, "Invalid queue ID");
7974 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7975 filter->ether_type == ETHER_TYPE_IPv6) {
7976 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7977 " control packet filter.", filter->ether_type);
7980 if (filter->ether_type == ETHER_TYPE_VLAN)
7981 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7984 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7985 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7986 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7987 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7988 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7990 memset(&stats, 0, sizeof(stats));
7991 ret = i40e_aq_add_rem_control_packet_filter(hw,
7992 filter->mac_addr.addr_bytes,
7993 filter->ether_type, flags,
7995 filter->queue, add, &stats, NULL);
7997 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7998 " mac_etype_used = %u, etype_used = %u,"
7999 " mac_etype_free = %u, etype_free = %u\n",
8000 ret, stats.mac_etype_used, stats.etype_used,
8001 stats.mac_etype_free, stats.etype_free);
8008 * Handle operations for ethertype filter.
8011 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8012 enum rte_filter_op filter_op,
8015 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8018 if (filter_op == RTE_ETH_FILTER_NOP)
8022 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8027 switch (filter_op) {
8028 case RTE_ETH_FILTER_ADD:
8029 ret = i40e_ethertype_filter_set(pf,
8030 (struct rte_eth_ethertype_filter *)arg,
8033 case RTE_ETH_FILTER_DELETE:
8034 ret = i40e_ethertype_filter_set(pf,
8035 (struct rte_eth_ethertype_filter *)arg,
8039 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8047 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8048 enum rte_filter_type filter_type,
8049 enum rte_filter_op filter_op,
8057 switch (filter_type) {
8058 case RTE_ETH_FILTER_NONE:
8059 /* For global configuration */
8060 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8062 case RTE_ETH_FILTER_HASH:
8063 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8065 case RTE_ETH_FILTER_MACVLAN:
8066 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8068 case RTE_ETH_FILTER_ETHERTYPE:
8069 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8071 case RTE_ETH_FILTER_TUNNEL:
8072 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8074 case RTE_ETH_FILTER_FDIR:
8075 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8078 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8088 * Check and enable Extended Tag.
8089 * Enabling Extended Tag is important for 40G performance.
8092 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8097 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8100 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8104 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8105 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8110 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8113 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8117 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8118 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8121 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8122 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8125 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8132 * As some registers wouldn't be reset unless a global hardware reset,
8133 * hardware initialization is needed to put those registers into an
8134 * expected initial state.
8137 i40e_hw_init(struct rte_eth_dev *dev)
8139 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8141 i40e_enable_extended_tag(dev);
8143 /* clear the PF Queue Filter control register */
8144 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8146 /* Disable symmetric hash per port */
8147 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8150 enum i40e_filter_pctype
8151 i40e_flowtype_to_pctype(uint16_t flow_type)
8153 static const enum i40e_filter_pctype pctype_table[] = {
8154 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8155 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8156 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8157 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8158 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8159 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8160 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8161 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8162 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8163 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8164 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8165 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8166 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8167 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8168 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8169 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8170 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8171 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8172 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8175 return pctype_table[flow_type];
8179 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8181 static const uint16_t flowtype_table[] = {
8182 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8183 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8184 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8186 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8187 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8188 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8189 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8191 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8192 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8194 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8195 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8197 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8198 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8199 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8200 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8201 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8202 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8203 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8205 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8206 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8207 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8208 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8210 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8211 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8213 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8214 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8216 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8217 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8218 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8219 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8220 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8223 return flowtype_table[pctype];
8227 * On X710, performance number is far from the expectation on recent firmware
8228 * versions; on XL710, performance number is also far from the expectation on
8229 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8230 * mode is enabled and port MAC address is equal to the packet destination MAC
8231 * address. The fix for this issue may not be integrated in the following
8232 * firmware version. So the workaround in software driver is needed. It needs
8233 * to modify the initial values of 3 internal only registers for both X710 and
8234 * XL710. Note that the values for X710 or XL710 could be different, and the
8235 * workaround can be removed when it is fixed in firmware in the future.
8238 /* For both X710 and XL710 */
8239 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8240 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
8242 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8243 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
8246 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
8248 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
8249 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
8252 i40e_configure_registers(struct i40e_hw *hw)
8258 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8259 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8260 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8266 for (i = 0; i < RTE_DIM(reg_table); i++) {
8267 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8268 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8270 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8273 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8276 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8279 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8283 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8284 reg_table[i].addr, reg);
8285 if (reg == reg_table[i].val)
8288 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8289 reg_table[i].val, NULL);
8291 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8292 "address of 0x%"PRIx32, reg_table[i].val,
8296 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8297 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8301 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
8302 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
8303 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
8304 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8306 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8311 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8312 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8316 /* Configure for double VLAN RX stripping */
8317 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8318 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8319 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8320 ret = i40e_aq_debug_write_register(hw,
8321 I40E_VSI_TSR(vsi->vsi_id),
8324 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8326 return I40E_ERR_CONFIG;
8330 /* Configure for double VLAN TX insertion */
8331 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8332 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8333 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8334 ret = i40e_aq_debug_write_register(hw,
8335 I40E_VSI_L2TAGSTXVALID(
8336 vsi->vsi_id), reg, NULL);
8338 PMD_DRV_LOG(ERR, "Failed to update "
8339 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8340 return I40E_ERR_CONFIG;
8348 * i40e_aq_add_mirror_rule
8349 * @hw: pointer to the hardware structure
8350 * @seid: VEB seid to add mirror rule to
8351 * @dst_id: destination vsi seid
8352 * @entries: Buffer which contains the entities to be mirrored
8353 * @count: number of entities contained in the buffer
8354 * @rule_id:the rule_id of the rule to be added
8356 * Add a mirror rule for a given veb.
8359 static enum i40e_status_code
8360 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8361 uint16_t seid, uint16_t dst_id,
8362 uint16_t rule_type, uint16_t *entries,
8363 uint16_t count, uint16_t *rule_id)
8365 struct i40e_aq_desc desc;
8366 struct i40e_aqc_add_delete_mirror_rule cmd;
8367 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8368 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8371 enum i40e_status_code status;
8373 i40e_fill_default_direct_cmd_desc(&desc,
8374 i40e_aqc_opc_add_mirror_rule);
8375 memset(&cmd, 0, sizeof(cmd));
8377 buff_len = sizeof(uint16_t) * count;
8378 desc.datalen = rte_cpu_to_le_16(buff_len);
8380 desc.flags |= rte_cpu_to_le_16(
8381 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8382 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8383 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8384 cmd.num_entries = rte_cpu_to_le_16(count);
8385 cmd.seid = rte_cpu_to_le_16(seid);
8386 cmd.destination = rte_cpu_to_le_16(dst_id);
8388 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8389 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8390 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8392 " mirror_rules_used = %u, mirror_rules_free = %u,",
8393 hw->aq.asq_last_status, resp->rule_id,
8394 resp->mirror_rules_used, resp->mirror_rules_free);
8395 *rule_id = rte_le_to_cpu_16(resp->rule_id);
8401 * i40e_aq_del_mirror_rule
8402 * @hw: pointer to the hardware structure
8403 * @seid: VEB seid to add mirror rule to
8404 * @entries: Buffer which contains the entities to be mirrored
8405 * @count: number of entities contained in the buffer
8406 * @rule_id:the rule_id of the rule to be delete
8408 * Delete a mirror rule for a given veb.
8411 static enum i40e_status_code
8412 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8413 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8414 uint16_t count, uint16_t rule_id)
8416 struct i40e_aq_desc desc;
8417 struct i40e_aqc_add_delete_mirror_rule cmd;
8418 uint16_t buff_len = 0;
8419 enum i40e_status_code status;
8422 i40e_fill_default_direct_cmd_desc(&desc,
8423 i40e_aqc_opc_delete_mirror_rule);
8424 memset(&cmd, 0, sizeof(cmd));
8425 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8426 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8428 cmd.num_entries = count;
8429 buff_len = sizeof(uint16_t) * count;
8430 desc.datalen = rte_cpu_to_le_16(buff_len);
8431 buff = (void *)entries;
8433 /* rule id is filled in destination field for deleting mirror rule */
8434 cmd.destination = rte_cpu_to_le_16(rule_id);
8436 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8437 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8438 cmd.seid = rte_cpu_to_le_16(seid);
8440 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8441 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8447 * i40e_mirror_rule_set
8448 * @dev: pointer to the hardware structure
8449 * @mirror_conf: mirror rule info
8450 * @sw_id: mirror rule's sw_id
8451 * @on: enable/disable
8453 * set a mirror rule.
8457 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8458 struct rte_eth_mirror_conf *mirror_conf,
8459 uint8_t sw_id, uint8_t on)
8461 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8462 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8463 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8464 struct i40e_mirror_rule *parent = NULL;
8465 uint16_t seid, dst_seid, rule_id;
8469 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8471 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8472 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8473 " without veb or vfs.");
8476 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8477 PMD_DRV_LOG(ERR, "mirror table is full.");
8480 if (mirror_conf->dst_pool > pf->vf_num) {
8481 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8482 mirror_conf->dst_pool);
8486 seid = pf->main_vsi->veb->seid;
8488 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8489 if (sw_id <= it->index) {
8495 if (mirr_rule && sw_id == mirr_rule->index) {
8497 PMD_DRV_LOG(ERR, "mirror rule exists.");
8500 ret = i40e_aq_del_mirror_rule(hw, seid,
8501 mirr_rule->rule_type,
8503 mirr_rule->num_entries, mirr_rule->id);
8505 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8506 " ret = %d, aq_err = %d.",
8507 ret, hw->aq.asq_last_status);
8510 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8511 rte_free(mirr_rule);
8512 pf->nb_mirror_rule--;
8516 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8520 mirr_rule = rte_zmalloc("i40e_mirror_rule",
8521 sizeof(struct i40e_mirror_rule) , 0);
8523 PMD_DRV_LOG(ERR, "failed to allocate memory");
8524 return I40E_ERR_NO_MEMORY;
8526 switch (mirror_conf->rule_type) {
8527 case ETH_MIRROR_VLAN:
8528 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8529 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8530 mirr_rule->entries[j] =
8531 mirror_conf->vlan.vlan_id[i];
8536 PMD_DRV_LOG(ERR, "vlan is not specified.");
8537 rte_free(mirr_rule);
8540 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8542 case ETH_MIRROR_VIRTUAL_POOL_UP:
8543 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8544 /* check if the specified pool bit is out of range */
8545 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8546 PMD_DRV_LOG(ERR, "pool mask is out of range.");
8547 rte_free(mirr_rule);
8550 for (i = 0, j = 0; i < pf->vf_num; i++) {
8551 if (mirror_conf->pool_mask & (1ULL << i)) {
8552 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8556 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8557 /* add pf vsi to entries */
8558 mirr_rule->entries[j] = pf->main_vsi_seid;
8562 PMD_DRV_LOG(ERR, "pool is not specified.");
8563 rte_free(mirr_rule);
8566 /* egress and ingress in aq commands means from switch but not port */
8567 mirr_rule->rule_type =
8568 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8569 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8570 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8572 case ETH_MIRROR_UPLINK_PORT:
8573 /* egress and ingress in aq commands means from switch but not port*/
8574 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8576 case ETH_MIRROR_DOWNLINK_PORT:
8577 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8580 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8581 mirror_conf->rule_type);
8582 rte_free(mirr_rule);
8586 /* If the dst_pool is equal to vf_num, consider it as PF */
8587 if (mirror_conf->dst_pool == pf->vf_num)
8588 dst_seid = pf->main_vsi_seid;
8590 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8592 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8593 mirr_rule->rule_type, mirr_rule->entries,
8596 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8597 " ret = %d, aq_err = %d.",
8598 ret, hw->aq.asq_last_status);
8599 rte_free(mirr_rule);
8603 mirr_rule->index = sw_id;
8604 mirr_rule->num_entries = j;
8605 mirr_rule->id = rule_id;
8606 mirr_rule->dst_vsi_seid = dst_seid;
8609 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8611 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8613 pf->nb_mirror_rule++;
8618 * i40e_mirror_rule_reset
8619 * @dev: pointer to the device
8620 * @sw_id: mirror rule's sw_id
8622 * reset a mirror rule.
8626 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8628 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8629 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8630 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8634 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8636 seid = pf->main_vsi->veb->seid;
8638 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8639 if (sw_id == it->index) {
8645 ret = i40e_aq_del_mirror_rule(hw, seid,
8646 mirr_rule->rule_type,
8648 mirr_rule->num_entries, mirr_rule->id);
8650 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8651 " status = %d, aq_err = %d.",
8652 ret, hw->aq.asq_last_status);
8655 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8656 rte_free(mirr_rule);
8657 pf->nb_mirror_rule--;
8659 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8666 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8668 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8669 uint64_t systim_cycles;
8671 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8672 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8675 return systim_cycles;
8679 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8681 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8684 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8685 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8692 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8694 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8697 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8698 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8705 i40e_start_timecounters(struct rte_eth_dev *dev)
8707 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8708 struct i40e_adapter *adapter =
8709 (struct i40e_adapter *)dev->data->dev_private;
8710 struct rte_eth_link link;
8711 uint32_t tsync_inc_l;
8712 uint32_t tsync_inc_h;
8714 /* Get current link speed. */
8715 memset(&link, 0, sizeof(link));
8716 i40e_dev_link_update(dev, 1);
8717 rte_i40e_dev_atomic_read_link_status(dev, &link);
8719 switch (link.link_speed) {
8720 case ETH_SPEED_NUM_40G:
8721 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8722 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8724 case ETH_SPEED_NUM_10G:
8725 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8726 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8728 case ETH_SPEED_NUM_1G:
8729 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8730 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8737 /* Set the timesync increment value. */
8738 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8739 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8741 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8742 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8743 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8745 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8746 adapter->systime_tc.cc_shift = 0;
8747 adapter->systime_tc.nsec_mask = 0;
8749 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8750 adapter->rx_tstamp_tc.cc_shift = 0;
8751 adapter->rx_tstamp_tc.nsec_mask = 0;
8753 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8754 adapter->tx_tstamp_tc.cc_shift = 0;
8755 adapter->tx_tstamp_tc.nsec_mask = 0;
8759 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8761 struct i40e_adapter *adapter =
8762 (struct i40e_adapter *)dev->data->dev_private;
8764 adapter->systime_tc.nsec += delta;
8765 adapter->rx_tstamp_tc.nsec += delta;
8766 adapter->tx_tstamp_tc.nsec += delta;
8772 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8775 struct i40e_adapter *adapter =
8776 (struct i40e_adapter *)dev->data->dev_private;
8778 ns = rte_timespec_to_ns(ts);
8780 /* Set the timecounters to a new value. */
8781 adapter->systime_tc.nsec = ns;
8782 adapter->rx_tstamp_tc.nsec = ns;
8783 adapter->tx_tstamp_tc.nsec = ns;
8789 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8791 uint64_t ns, systime_cycles;
8792 struct i40e_adapter *adapter =
8793 (struct i40e_adapter *)dev->data->dev_private;
8795 systime_cycles = i40e_read_systime_cyclecounter(dev);
8796 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8797 *ts = rte_ns_to_timespec(ns);
8803 i40e_timesync_enable(struct rte_eth_dev *dev)
8805 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8806 uint32_t tsync_ctl_l;
8807 uint32_t tsync_ctl_h;
8809 /* Stop the timesync system time. */
8810 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8811 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8812 /* Reset the timesync system time value. */
8813 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8814 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8816 i40e_start_timecounters(dev);
8818 /* Clear timesync registers. */
8819 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8820 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8821 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8822 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8823 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8824 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8826 /* Enable timestamping of PTP packets. */
8827 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8828 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8830 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8831 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8832 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8834 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8835 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8841 i40e_timesync_disable(struct rte_eth_dev *dev)
8843 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8844 uint32_t tsync_ctl_l;
8845 uint32_t tsync_ctl_h;
8847 /* Disable timestamping of transmitted PTP packets. */
8848 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8849 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8851 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8852 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8854 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8855 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8857 /* Reset the timesync increment value. */
8858 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8859 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8865 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8866 struct timespec *timestamp, uint32_t flags)
8868 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8869 struct i40e_adapter *adapter =
8870 (struct i40e_adapter *)dev->data->dev_private;
8872 uint32_t sync_status;
8873 uint32_t index = flags & 0x03;
8874 uint64_t rx_tstamp_cycles;
8877 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8878 if ((sync_status & (1 << index)) == 0)
8881 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8882 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8883 *timestamp = rte_ns_to_timespec(ns);
8889 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8890 struct timespec *timestamp)
8892 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8893 struct i40e_adapter *adapter =
8894 (struct i40e_adapter *)dev->data->dev_private;
8896 uint32_t sync_status;
8897 uint64_t tx_tstamp_cycles;
8900 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8901 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8904 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8905 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8906 *timestamp = rte_ns_to_timespec(ns);
8912 * i40e_parse_dcb_configure - parse dcb configure from user
8913 * @dev: the device being configured
8914 * @dcb_cfg: pointer of the result of parse
8915 * @*tc_map: bit map of enabled traffic classes
8917 * Returns 0 on success, negative value on failure
8920 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8921 struct i40e_dcbx_config *dcb_cfg,
8924 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8925 uint8_t i, tc_bw, bw_lf;
8927 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8929 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8930 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8931 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8935 /* assume each tc has the same bw */
8936 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8937 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8938 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8939 /* to ensure the sum of tcbw is equal to 100 */
8940 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8941 for (i = 0; i < bw_lf; i++)
8942 dcb_cfg->etscfg.tcbwtable[i]++;
8944 /* assume each tc has the same Transmission Selection Algorithm */
8945 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8946 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8948 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8949 dcb_cfg->etscfg.prioritytable[i] =
8950 dcb_rx_conf->dcb_tc[i];
8952 /* FW needs one App to configure HW */
8953 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8954 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8955 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8956 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8958 if (dcb_rx_conf->nb_tcs == 0)
8959 *tc_map = 1; /* tc0 only */
8961 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8963 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8964 dcb_cfg->pfc.willing = 0;
8965 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8966 dcb_cfg->pfc.pfcenable = *tc_map;
8972 static enum i40e_status_code
8973 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8974 struct i40e_aqc_vsi_properties_data *info,
8975 uint8_t enabled_tcmap)
8977 enum i40e_status_code ret;
8978 int i, total_tc = 0;
8979 uint16_t qpnum_per_tc, bsf, qp_idx;
8980 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8981 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8982 uint16_t used_queues;
8984 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8985 if (ret != I40E_SUCCESS)
8988 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8989 if (enabled_tcmap & (1 << i))
8994 vsi->enabled_tc = enabled_tcmap;
8996 /* different VSI has different queues assigned */
8997 if (vsi->type == I40E_VSI_MAIN)
8998 used_queues = dev_data->nb_rx_queues -
8999 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9000 else if (vsi->type == I40E_VSI_VMDQ2)
9001 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9003 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9004 return I40E_ERR_NO_AVAILABLE_VSI;
9007 qpnum_per_tc = used_queues / total_tc;
9008 /* Number of queues per enabled TC */
9009 if (qpnum_per_tc == 0) {
9010 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9011 return I40E_ERR_INVALID_QP_ID;
9013 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9015 bsf = rte_bsf32(qpnum_per_tc);
9018 * Configure TC and queue mapping parameters, for enabled TC,
9019 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9020 * default queue will serve it.
9023 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9024 if (vsi->enabled_tc & (1 << i)) {
9025 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9026 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9027 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9028 qp_idx += qpnum_per_tc;
9030 info->tc_mapping[i] = 0;
9033 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9034 if (vsi->type == I40E_VSI_SRIOV) {
9035 info->mapping_flags |=
9036 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9037 for (i = 0; i < vsi->nb_qps; i++)
9038 info->queue_mapping[i] =
9039 rte_cpu_to_le_16(vsi->base_queue + i);
9041 info->mapping_flags |=
9042 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9043 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9045 info->valid_sections |=
9046 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9048 return I40E_SUCCESS;
9052 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9053 * @veb: VEB to be configured
9054 * @tc_map: enabled TC bitmap
9056 * Returns 0 on success, negative value on failure
9058 static enum i40e_status_code
9059 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9061 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9062 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9063 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9064 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9065 enum i40e_status_code ret = I40E_SUCCESS;
9069 /* Check if enabled_tc is same as existing or new TCs */
9070 if (veb->enabled_tc == tc_map)
9073 /* configure tc bandwidth */
9074 memset(&veb_bw, 0, sizeof(veb_bw));
9075 veb_bw.tc_valid_bits = tc_map;
9076 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9077 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9078 if (tc_map & BIT_ULL(i))
9079 veb_bw.tc_bw_share_credits[i] = 1;
9081 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9084 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9085 " per TC failed = %d",
9086 hw->aq.asq_last_status);
9090 memset(&ets_query, 0, sizeof(ets_query));
9091 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9093 if (ret != I40E_SUCCESS) {
9094 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9095 " configuration %u", hw->aq.asq_last_status);
9098 memset(&bw_query, 0, sizeof(bw_query));
9099 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9101 if (ret != I40E_SUCCESS) {
9102 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9103 " configuration %u", hw->aq.asq_last_status);
9107 /* store and print out BW info */
9108 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9109 veb->bw_info.bw_max = ets_query.tc_bw_max;
9110 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9111 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9112 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9113 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9115 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9116 veb->bw_info.bw_ets_share_credits[i] =
9117 bw_query.tc_bw_share_credits[i];
9118 veb->bw_info.bw_ets_credits[i] =
9119 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9120 /* 4 bits per TC, 4th bit is reserved */
9121 veb->bw_info.bw_ets_max[i] =
9122 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9123 RTE_LEN2MASK(3, uint8_t));
9124 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9125 veb->bw_info.bw_ets_share_credits[i]);
9126 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9127 veb->bw_info.bw_ets_credits[i]);
9128 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9129 veb->bw_info.bw_ets_max[i]);
9132 veb->enabled_tc = tc_map;
9139 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9140 * @vsi: VSI to be configured
9141 * @tc_map: enabled TC bitmap
9143 * Returns 0 on success, negative value on failure
9145 static enum i40e_status_code
9146 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9148 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9149 struct i40e_vsi_context ctxt;
9150 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9151 enum i40e_status_code ret = I40E_SUCCESS;
9154 /* Check if enabled_tc is same as existing or new TCs */
9155 if (vsi->enabled_tc == tc_map)
9158 /* configure tc bandwidth */
9159 memset(&bw_data, 0, sizeof(bw_data));
9160 bw_data.tc_valid_bits = tc_map;
9161 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9162 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9163 if (tc_map & BIT_ULL(i))
9164 bw_data.tc_bw_credits[i] = 1;
9166 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9168 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9169 " per TC failed = %d",
9170 hw->aq.asq_last_status);
9173 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9174 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9176 /* Update Queue Pairs Mapping for currently enabled UPs */
9177 ctxt.seid = vsi->seid;
9178 ctxt.pf_num = hw->pf_id;
9180 ctxt.uplink_seid = vsi->uplink_seid;
9181 ctxt.info = vsi->info;
9183 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9187 /* Update the VSI after updating the VSI queue-mapping information */
9188 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9190 PMD_INIT_LOG(ERR, "Failed to configure "
9191 "TC queue mapping = %d",
9192 hw->aq.asq_last_status);
9195 /* update the local VSI info with updated queue map */
9196 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9197 sizeof(vsi->info.tc_mapping));
9198 (void)rte_memcpy(&vsi->info.queue_mapping,
9199 &ctxt.info.queue_mapping,
9200 sizeof(vsi->info.queue_mapping));
9201 vsi->info.mapping_flags = ctxt.info.mapping_flags;
9202 vsi->info.valid_sections = 0;
9204 /* query and update current VSI BW information */
9205 ret = i40e_vsi_get_bw_config(vsi);
9208 "Failed updating vsi bw info, err %s aq_err %s",
9209 i40e_stat_str(hw, ret),
9210 i40e_aq_str(hw, hw->aq.asq_last_status));
9214 vsi->enabled_tc = tc_map;
9221 * i40e_dcb_hw_configure - program the dcb setting to hw
9222 * @pf: pf the configuration is taken on
9223 * @new_cfg: new configuration
9224 * @tc_map: enabled TC bitmap
9226 * Returns 0 on success, negative value on failure
9228 static enum i40e_status_code
9229 i40e_dcb_hw_configure(struct i40e_pf *pf,
9230 struct i40e_dcbx_config *new_cfg,
9233 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9234 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9235 struct i40e_vsi *main_vsi = pf->main_vsi;
9236 struct i40e_vsi_list *vsi_list;
9237 enum i40e_status_code ret;
9241 /* Use the FW API if FW > v4.4*/
9242 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9243 (hw->aq.fw_maj_ver >= 5))) {
9244 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9245 " to configure DCB");
9246 return I40E_ERR_FIRMWARE_API_VERSION;
9249 /* Check if need reconfiguration */
9250 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9251 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9252 return I40E_SUCCESS;
9255 /* Copy the new config to the current config */
9256 *old_cfg = *new_cfg;
9257 old_cfg->etsrec = old_cfg->etscfg;
9258 ret = i40e_set_dcb_config(hw);
9261 "Set DCB Config failed, err %s aq_err %s\n",
9262 i40e_stat_str(hw, ret),
9263 i40e_aq_str(hw, hw->aq.asq_last_status));
9266 /* set receive Arbiter to RR mode and ETS scheme by default */
9267 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9268 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9269 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
9270 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9271 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9272 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9273 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9274 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9275 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9276 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9277 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9278 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9279 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9281 /* get local mib to check whether it is configured correctly */
9283 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9284 /* Get Local DCB Config */
9285 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9286 &hw->local_dcbx_config);
9288 /* if Veb is created, need to update TC of it at first */
9289 if (main_vsi->veb) {
9290 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9292 PMD_INIT_LOG(WARNING,
9293 "Failed configuring TC for VEB seid=%d\n",
9294 main_vsi->veb->seid);
9296 /* Update each VSI */
9297 i40e_vsi_config_tc(main_vsi, tc_map);
9298 if (main_vsi->veb) {
9299 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9300 /* Beside main VSI and VMDQ VSIs, only enable default
9303 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9304 ret = i40e_vsi_config_tc(vsi_list->vsi,
9307 ret = i40e_vsi_config_tc(vsi_list->vsi,
9308 I40E_DEFAULT_TCMAP);
9310 PMD_INIT_LOG(WARNING,
9311 "Failed configuring TC for VSI seid=%d\n",
9312 vsi_list->vsi->seid);
9316 return I40E_SUCCESS;
9320 * i40e_dcb_init_configure - initial dcb config
9321 * @dev: device being configured
9322 * @sw_dcb: indicate whether dcb is sw configured or hw offload
9324 * Returns 0 on success, negative value on failure
9327 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9329 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9330 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9333 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9334 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9338 /* DCB initialization:
9339 * Update DCB configuration from the Firmware and configure
9340 * LLDP MIB change event.
9342 if (sw_dcb == TRUE) {
9343 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9344 if (ret != I40E_SUCCESS)
9345 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9347 ret = i40e_init_dcb(hw);
9348 /* if sw_dcb, lldp agent is stopped, the return from
9349 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9352 if (ret != I40E_SUCCESS &&
9353 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9354 memset(&hw->local_dcbx_config, 0,
9355 sizeof(struct i40e_dcbx_config));
9356 /* set dcb default configuration */
9357 hw->local_dcbx_config.etscfg.willing = 0;
9358 hw->local_dcbx_config.etscfg.maxtcs = 0;
9359 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9360 hw->local_dcbx_config.etscfg.tsatable[0] =
9362 hw->local_dcbx_config.etsrec =
9363 hw->local_dcbx_config.etscfg;
9364 hw->local_dcbx_config.pfc.willing = 0;
9365 hw->local_dcbx_config.pfc.pfccap =
9366 I40E_MAX_TRAFFIC_CLASS;
9367 /* FW needs one App to configure HW */
9368 hw->local_dcbx_config.numapps = 1;
9369 hw->local_dcbx_config.app[0].selector =
9370 I40E_APP_SEL_ETHTYPE;
9371 hw->local_dcbx_config.app[0].priority = 3;
9372 hw->local_dcbx_config.app[0].protocolid =
9373 I40E_APP_PROTOID_FCOE;
9374 ret = i40e_set_dcb_config(hw);
9376 PMD_INIT_LOG(ERR, "default dcb config fails."
9377 " err = %d, aq_err = %d.", ret,
9378 hw->aq.asq_last_status);
9382 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9383 " aq_err = %d.", ret,
9384 hw->aq.asq_last_status);
9388 ret = i40e_aq_start_lldp(hw, NULL);
9389 if (ret != I40E_SUCCESS)
9390 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9392 ret = i40e_init_dcb(hw);
9394 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9395 PMD_INIT_LOG(ERR, "HW doesn't support"
9400 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9401 " aq_err = %d.", ret,
9402 hw->aq.asq_last_status);
9410 * i40e_dcb_setup - setup dcb related config
9411 * @dev: device being configured
9413 * Returns 0 on success, negative value on failure
9416 i40e_dcb_setup(struct rte_eth_dev *dev)
9418 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9419 struct i40e_dcbx_config dcb_cfg;
9423 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9424 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9428 if (pf->vf_num != 0)
9429 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9431 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9433 PMD_INIT_LOG(ERR, "invalid dcb config");
9436 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9438 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9446 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9447 struct rte_eth_dcb_info *dcb_info)
9449 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9450 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9451 struct i40e_vsi *vsi = pf->main_vsi;
9452 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9453 uint16_t bsf, tc_mapping;
9456 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9457 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9459 dcb_info->nb_tcs = 1;
9460 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9461 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9462 for (i = 0; i < dcb_info->nb_tcs; i++)
9463 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9465 /* get queue mapping if vmdq is disabled */
9466 if (!pf->nb_cfg_vmdq_vsi) {
9467 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9468 if (!(vsi->enabled_tc & (1 << i)))
9470 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9471 dcb_info->tc_queue.tc_rxq[j][i].base =
9472 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9473 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9474 dcb_info->tc_queue.tc_txq[j][i].base =
9475 dcb_info->tc_queue.tc_rxq[j][i].base;
9476 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9477 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9478 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9479 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9480 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9485 /* get queue mapping if vmdq is enabled */
9487 vsi = pf->vmdq[j].vsi;
9488 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9489 if (!(vsi->enabled_tc & (1 << i)))
9491 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9492 dcb_info->tc_queue.tc_rxq[j][i].base =
9493 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9494 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9495 dcb_info->tc_queue.tc_txq[j][i].base =
9496 dcb_info->tc_queue.tc_rxq[j][i].base;
9497 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9498 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9499 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9500 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9501 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9504 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9509 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9511 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9512 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9514 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9517 msix_intr = intr_handle->intr_vec[queue_id];
9518 if (msix_intr == I40E_MISC_VEC_ID)
9519 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9520 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9521 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9522 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9524 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9527 I40E_PFINT_DYN_CTLN(msix_intr -
9529 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9530 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9531 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9533 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9535 I40E_WRITE_FLUSH(hw);
9536 rte_intr_enable(&dev->pci_dev->intr_handle);
9542 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9544 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9545 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9548 msix_intr = intr_handle->intr_vec[queue_id];
9549 if (msix_intr == I40E_MISC_VEC_ID)
9550 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9553 I40E_PFINT_DYN_CTLN(msix_intr -
9556 I40E_WRITE_FLUSH(hw);
9561 static int i40e_get_regs(struct rte_eth_dev *dev,
9562 struct rte_dev_reg_info *regs)
9564 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9565 uint32_t *ptr_data = regs->data;
9566 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9567 const struct i40e_reg_info *reg_info;
9569 if (ptr_data == NULL) {
9570 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9571 regs->width = sizeof(uint32_t);
9575 /* The first few registers have to be read using AQ operations */
9577 while (i40e_regs_adminq[reg_idx].name) {
9578 reg_info = &i40e_regs_adminq[reg_idx++];
9579 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9581 arr_idx2 <= reg_info->count2;
9583 reg_offset = arr_idx * reg_info->stride1 +
9584 arr_idx2 * reg_info->stride2;
9585 reg_offset += reg_info->base_addr;
9586 ptr_data[reg_offset >> 2] =
9587 i40e_read_rx_ctl(hw, reg_offset);
9591 /* The remaining registers can be read using primitives */
9593 while (i40e_regs_others[reg_idx].name) {
9594 reg_info = &i40e_regs_others[reg_idx++];
9595 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9597 arr_idx2 <= reg_info->count2;
9599 reg_offset = arr_idx * reg_info->stride1 +
9600 arr_idx2 * reg_info->stride2;
9601 reg_offset += reg_info->base_addr;
9602 ptr_data[reg_offset >> 2] =
9603 I40E_READ_REG(hw, reg_offset);
9610 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9612 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9614 /* Convert word count to byte count */
9615 return hw->nvm.sr_size << 1;
9618 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9619 struct rte_dev_eeprom_info *eeprom)
9621 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9622 uint16_t *data = eeprom->data;
9623 uint16_t offset, length, cnt_words;
9626 offset = eeprom->offset >> 1;
9627 length = eeprom->length >> 1;
9630 if (offset > hw->nvm.sr_size ||
9631 offset + length > hw->nvm.sr_size) {
9632 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9636 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9638 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9639 if (ret_code != I40E_SUCCESS || cnt_words != length) {
9640 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9647 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9648 struct ether_addr *mac_addr)
9650 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9652 if (!is_valid_assigned_ether_addr(mac_addr)) {
9653 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9657 /* Flags: 0x3 updates port address */
9658 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9662 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9664 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9665 struct rte_eth_dev_data *dev_data = pf->dev_data;
9666 uint32_t frame_size = mtu + ETHER_HDR_LEN
9667 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9670 /* check if mtu is within the allowed range */
9671 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9674 /* mtu setting is forbidden if port is start */
9675 if (dev_data->dev_started) {
9677 "port %d must be stopped before configuration\n",
9682 if (frame_size > ETHER_MAX_LEN)
9683 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9685 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9687 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;