1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
29 #include <rte_bitmap.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
45 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
48 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
50 #define I40E_CLEAR_PXE_WAIT_MS 200
52 /* Maximun number of capability elements */
53 #define I40E_MAX_CAP_ELE_NUM 128
55 /* Wait count and interval */
56 #define I40E_CHK_Q_ENA_COUNT 1000
57 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
59 /* Maximun number of VSI */
60 #define I40E_MAX_NUM_VSIS (384UL)
62 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
64 /* Flow control default timer */
65 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
67 /* Flow control enable fwd bit */
68 #define I40E_PRTMAC_FWD_CTRL 0x00000001
70 /* Receive Packet Buffer size */
71 #define I40E_RXPBSIZE (968 * 1024)
74 #define I40E_KILOSHIFT 10
76 /* Flow control default high water */
77 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
79 /* Flow control default low water */
80 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
82 /* Receive Average Packet Size in Byte*/
83 #define I40E_PACKET_AVERAGE_SIZE 128
85 /* Mask of PF interrupt causes */
86 #define I40E_PFINT_ICR0_ENA_MASK ( \
87 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
88 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
89 I40E_PFINT_ICR0_ENA_GRST_MASK | \
90 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
91 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
92 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
93 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
94 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
95 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
97 #define I40E_FLOW_TYPES ( \
98 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
103 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
107 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
108 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
110 /* Additional timesync values. */
111 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
112 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
113 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
114 #define I40E_PRTTSYN_TSYNENA 0x80000000
115 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
116 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
119 * Below are values for writing un-exposed registers suggested
122 /* Destination MAC address */
123 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
124 /* Source MAC address */
125 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
126 /* Outer (S-Tag) VLAN tag in the outer L2 header */
127 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
128 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
129 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
130 /* Single VLAN tag in the inner L2 header */
131 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
132 /* Source IPv4 address */
133 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
134 /* Destination IPv4 address */
135 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
136 /* Source IPv4 address for X722 */
137 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
138 /* Destination IPv4 address for X722 */
139 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
140 /* IPv4 Protocol for X722 */
141 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
142 /* IPv4 Time to Live for X722 */
143 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
144 /* IPv4 Type of Service (TOS) */
145 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
147 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
148 /* IPv4 Time to Live */
149 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
150 /* Source IPv6 address */
151 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
152 /* Destination IPv6 address */
153 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
154 /* IPv6 Traffic Class (TC) */
155 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
156 /* IPv6 Next Header */
157 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
159 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
161 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
162 /* Destination L4 port */
163 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
164 /* SCTP verification tag */
165 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
166 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
167 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
168 /* Source port of tunneling UDP */
169 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
170 /* Destination port of tunneling UDP */
171 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
172 /* UDP Tunneling ID, NVGRE/GRE key */
173 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
174 /* Last ether type */
175 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
176 /* Tunneling outer destination IPv4 address */
177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
178 /* Tunneling outer destination IPv6 address */
179 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
180 /* 1st word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
182 /* 2nd word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
184 /* 3rd word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
186 /* 4th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
188 /* 5th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
190 /* 6th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
192 /* 7th word of flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
194 /* 8th word of flex payload */
195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
196 /* all 8 words flex payload */
197 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
198 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
200 #define I40E_TRANSLATE_INSET 0
201 #define I40E_TRANSLATE_REG 1
203 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
204 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
205 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
206 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
207 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
208 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
210 /* PCI offset for querying capability */
211 #define PCI_DEV_CAP_REG 0xA4
212 /* PCI offset for enabling/disabling Extended Tag */
213 #define PCI_DEV_CTRL_REG 0xA8
214 /* Bit mask of Extended Tag capability */
215 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
216 /* Bit shift of Extended Tag enable/disable */
217 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
218 /* Bit mask of Extended Tag enable/disable */
219 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
221 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
222 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
223 static int i40e_dev_configure(struct rte_eth_dev *dev);
224 static int i40e_dev_start(struct rte_eth_dev *dev);
225 static void i40e_dev_stop(struct rte_eth_dev *dev);
226 static void i40e_dev_close(struct rte_eth_dev *dev);
227 static int i40e_dev_reset(struct rte_eth_dev *dev);
228 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
229 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
230 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
231 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
232 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
233 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
234 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
235 struct rte_eth_stats *stats);
236 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
237 struct rte_eth_xstat *xstats, unsigned n);
238 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
239 struct rte_eth_xstat_name *xstats_names,
241 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
243 char *fw_version, size_t fw_size);
244 static int i40e_dev_info_get(struct rte_eth_dev *dev,
245 struct rte_eth_dev_info *dev_info);
246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
250 enum rte_vlan_type vlan_type,
252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
260 struct rte_eth_fc_conf *fc_conf);
261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_pfc_conf *pfc_conf);
265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
266 struct rte_ether_addr *mac_addr,
269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
271 struct rte_eth_rss_reta_entry64 *reta_conf,
273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
277 static int i40e_get_cap(struct i40e_hw *hw);
278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
279 static int i40e_pf_setup(struct i40e_pf *pf);
280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
284 bool offset_loaded, uint64_t *offset, uint64_t *stat);
285 static void i40e_stat_update_48(struct i40e_hw *hw,
291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
292 static void i40e_dev_interrupt_handler(void *param);
293 static void i40e_dev_alarm_handler(void *param);
294 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
295 uint32_t base, uint32_t num);
296 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
297 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
299 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
301 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
302 static int i40e_veb_release(struct i40e_veb *veb);
303 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
304 struct i40e_vsi *vsi);
305 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
306 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
307 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
308 struct i40e_macvlan_filter *mv_f,
311 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
312 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
313 struct rte_eth_rss_conf *rss_conf);
314 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
315 struct rte_eth_rss_conf *rss_conf);
316 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
317 struct rte_eth_udp_tunnel *udp_tunnel);
318 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
319 struct rte_eth_udp_tunnel *udp_tunnel);
320 static void i40e_filter_input_set_init(struct i40e_pf *pf);
321 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
322 enum rte_filter_op filter_op,
324 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
325 enum rte_filter_type filter_type,
326 enum rte_filter_op filter_op,
328 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
329 struct rte_eth_dcb_info *dcb_info);
330 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
331 static void i40e_configure_registers(struct i40e_hw *hw);
332 static void i40e_hw_init(struct rte_eth_dev *dev);
333 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
334 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
340 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
341 struct rte_eth_mirror_conf *mirror_conf,
342 uint8_t sw_id, uint8_t on);
343 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
345 static int i40e_timesync_enable(struct rte_eth_dev *dev);
346 static int i40e_timesync_disable(struct rte_eth_dev *dev);
347 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
348 struct timespec *timestamp,
350 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
351 struct timespec *timestamp);
352 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
354 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
356 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
357 struct timespec *timestamp);
358 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
359 const struct timespec *timestamp);
361 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
363 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
366 static int i40e_get_regs(struct rte_eth_dev *dev,
367 struct rte_dev_reg_info *regs);
369 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
371 static int i40e_get_eeprom(struct rte_eth_dev *dev,
372 struct rte_dev_eeprom_info *eeprom);
374 static int i40e_get_module_info(struct rte_eth_dev *dev,
375 struct rte_eth_dev_module_info *modinfo);
376 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
377 struct rte_dev_eeprom_info *info);
379 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
380 struct rte_ether_addr *mac_addr);
382 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
384 static int i40e_ethertype_filter_convert(
385 const struct rte_eth_ethertype_filter *input,
386 struct i40e_ethertype_filter *filter);
387 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
388 struct i40e_ethertype_filter *filter);
390 static int i40e_tunnel_filter_convert(
391 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
392 struct i40e_tunnel_filter *tunnel_filter);
393 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
394 struct i40e_tunnel_filter *tunnel_filter);
395 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
397 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
398 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
399 static void i40e_filter_restore(struct i40e_pf *pf);
400 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
402 static const char *const valid_keys[] = {
403 ETH_I40E_FLOATING_VEB_ARG,
404 ETH_I40E_FLOATING_VEB_LIST_ARG,
405 ETH_I40E_SUPPORT_MULTI_DRIVER,
406 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
407 ETH_I40E_USE_LATEST_VEC,
411 static const struct rte_pci_id pci_id_i40e_map[] = {
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
438 { .vendor_id = 0, /* sentinel */ },
441 static const struct eth_dev_ops i40e_eth_dev_ops = {
442 .dev_configure = i40e_dev_configure,
443 .dev_start = i40e_dev_start,
444 .dev_stop = i40e_dev_stop,
445 .dev_close = i40e_dev_close,
446 .dev_reset = i40e_dev_reset,
447 .promiscuous_enable = i40e_dev_promiscuous_enable,
448 .promiscuous_disable = i40e_dev_promiscuous_disable,
449 .allmulticast_enable = i40e_dev_allmulticast_enable,
450 .allmulticast_disable = i40e_dev_allmulticast_disable,
451 .dev_set_link_up = i40e_dev_set_link_up,
452 .dev_set_link_down = i40e_dev_set_link_down,
453 .link_update = i40e_dev_link_update,
454 .stats_get = i40e_dev_stats_get,
455 .xstats_get = i40e_dev_xstats_get,
456 .xstats_get_names = i40e_dev_xstats_get_names,
457 .stats_reset = i40e_dev_stats_reset,
458 .xstats_reset = i40e_dev_stats_reset,
459 .fw_version_get = i40e_fw_version_get,
460 .dev_infos_get = i40e_dev_info_get,
461 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
462 .vlan_filter_set = i40e_vlan_filter_set,
463 .vlan_tpid_set = i40e_vlan_tpid_set,
464 .vlan_offload_set = i40e_vlan_offload_set,
465 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
466 .vlan_pvid_set = i40e_vlan_pvid_set,
467 .rx_queue_start = i40e_dev_rx_queue_start,
468 .rx_queue_stop = i40e_dev_rx_queue_stop,
469 .tx_queue_start = i40e_dev_tx_queue_start,
470 .tx_queue_stop = i40e_dev_tx_queue_stop,
471 .rx_queue_setup = i40e_dev_rx_queue_setup,
472 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
473 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
474 .rx_queue_release = i40e_dev_rx_queue_release,
475 .rx_queue_count = i40e_dev_rx_queue_count,
476 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
477 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
478 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
479 .tx_queue_setup = i40e_dev_tx_queue_setup,
480 .tx_queue_release = i40e_dev_tx_queue_release,
481 .dev_led_on = i40e_dev_led_on,
482 .dev_led_off = i40e_dev_led_off,
483 .flow_ctrl_get = i40e_flow_ctrl_get,
484 .flow_ctrl_set = i40e_flow_ctrl_set,
485 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
486 .mac_addr_add = i40e_macaddr_add,
487 .mac_addr_remove = i40e_macaddr_remove,
488 .reta_update = i40e_dev_rss_reta_update,
489 .reta_query = i40e_dev_rss_reta_query,
490 .rss_hash_update = i40e_dev_rss_hash_update,
491 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
492 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
493 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
494 .filter_ctrl = i40e_dev_filter_ctrl,
495 .rxq_info_get = i40e_rxq_info_get,
496 .txq_info_get = i40e_txq_info_get,
497 .rx_burst_mode_get = i40e_rx_burst_mode_get,
498 .tx_burst_mode_get = i40e_tx_burst_mode_get,
499 .mirror_rule_set = i40e_mirror_rule_set,
500 .mirror_rule_reset = i40e_mirror_rule_reset,
501 .timesync_enable = i40e_timesync_enable,
502 .timesync_disable = i40e_timesync_disable,
503 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
504 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
505 .get_dcb_info = i40e_dev_get_dcb_info,
506 .timesync_adjust_time = i40e_timesync_adjust_time,
507 .timesync_read_time = i40e_timesync_read_time,
508 .timesync_write_time = i40e_timesync_write_time,
509 .get_reg = i40e_get_regs,
510 .get_eeprom_length = i40e_get_eeprom_length,
511 .get_eeprom = i40e_get_eeprom,
512 .get_module_info = i40e_get_module_info,
513 .get_module_eeprom = i40e_get_module_eeprom,
514 .mac_addr_set = i40e_set_default_mac_addr,
515 .mtu_set = i40e_dev_mtu_set,
516 .tm_ops_get = i40e_tm_ops_get,
517 .tx_done_cleanup = i40e_tx_done_cleanup,
520 /* store statistics names and its offset in stats structure */
521 struct rte_i40e_xstats_name_off {
522 char name[RTE_ETH_XSTATS_NAME_SIZE];
526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
527 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
528 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
529 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
530 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
531 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
532 rx_unknown_protocol)},
533 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
534 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
535 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
536 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
539 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
540 sizeof(rte_i40e_stats_strings[0]))
542 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
543 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
544 tx_dropped_link_down)},
545 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
546 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
548 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
549 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
551 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
553 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
555 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
556 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
557 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
558 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
559 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
560 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
574 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
576 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
577 mac_short_packet_dropped)},
578 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
580 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
581 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
582 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
592 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
594 {"rx_flow_director_atr_match_packets",
595 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
596 {"rx_flow_director_sb_match_packets",
597 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
598 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
600 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
602 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
604 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
608 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
609 sizeof(rte_i40e_hw_port_strings[0]))
611 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
612 {"xon_packets", offsetof(struct i40e_hw_port_stats,
614 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
618 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
619 sizeof(rte_i40e_rxq_prio_strings[0]))
621 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
622 {"xon_packets", offsetof(struct i40e_hw_port_stats,
624 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
626 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
627 priority_xon_2_xoff)},
630 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
631 sizeof(rte_i40e_txq_prio_strings[0]))
634 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
635 struct rte_pci_device *pci_dev)
637 char name[RTE_ETH_NAME_MAX_LEN];
638 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
641 if (pci_dev->device.devargs) {
642 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
648 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
649 sizeof(struct i40e_adapter),
650 eth_dev_pci_specific_init, pci_dev,
651 eth_i40e_dev_init, NULL);
653 if (retval || eth_da.nb_representor_ports < 1)
656 /* probe VF representor ports */
657 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
658 pci_dev->device.name);
660 if (pf_ethdev == NULL)
663 for (i = 0; i < eth_da.nb_representor_ports; i++) {
664 struct i40e_vf_representor representor = {
665 .vf_id = eth_da.representor_ports[i],
666 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
667 pf_ethdev->data->dev_private)->switch_domain_id,
668 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
669 pf_ethdev->data->dev_private)
672 /* representor port net_bdf_port */
673 snprintf(name, sizeof(name), "net_%s_representor_%d",
674 pci_dev->device.name, eth_da.representor_ports[i]);
676 retval = rte_eth_dev_create(&pci_dev->device, name,
677 sizeof(struct i40e_vf_representor), NULL, NULL,
678 i40e_vf_representor_init, &representor);
681 PMD_DRV_LOG(ERR, "failed to create i40e vf "
682 "representor %s.", name);
688 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
690 struct rte_eth_dev *ethdev;
692 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
696 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
697 return rte_eth_dev_pci_generic_remove(pci_dev,
698 i40e_vf_representor_uninit);
700 return rte_eth_dev_pci_generic_remove(pci_dev,
701 eth_i40e_dev_uninit);
704 static struct rte_pci_driver rte_i40e_pmd = {
705 .id_table = pci_id_i40e_map,
706 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
707 .probe = eth_i40e_pci_probe,
708 .remove = eth_i40e_pci_remove,
712 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
715 uint32_t ori_reg_val;
716 struct rte_eth_dev *dev;
718 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
719 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
720 i40e_write_rx_ctl(hw, reg_addr, reg_val);
721 if (ori_reg_val != reg_val)
723 "i40e device %s changed global register [0x%08x]."
724 " original: 0x%08x, new: 0x%08x",
725 dev->device->name, reg_addr, ori_reg_val, reg_val);
728 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
729 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
730 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
732 #ifndef I40E_GLQF_ORT
733 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
735 #ifndef I40E_GLQF_PIT
736 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
738 #ifndef I40E_GLQF_L3_MAP
739 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
742 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
745 * Initialize registers for parsing packet type of QinQ
746 * This should be removed from code once proper
747 * configuration API is added to avoid configuration conflicts
748 * between ports of the same device.
750 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
751 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
754 static inline void i40e_config_automask(struct i40e_pf *pf)
756 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
759 /* INTENA flag is not auto-cleared for interrupt */
760 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
761 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
762 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
764 /* If support multi-driver, PF will use INT0. */
765 if (!pf->support_multi_driver)
766 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
768 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
771 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
774 * Add a ethertype filter to drop all flow control frames transmitted
778 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
780 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
781 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
782 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
783 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
786 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
787 I40E_FLOW_CONTROL_ETHERTYPE, flags,
788 pf->main_vsi_seid, 0,
792 "Failed to add filter to drop flow control frames from VSIs.");
796 floating_veb_list_handler(__rte_unused const char *key,
797 const char *floating_veb_value,
801 unsigned int count = 0;
804 bool *vf_floating_veb = opaque;
806 while (isblank(*floating_veb_value))
807 floating_veb_value++;
809 /* Reset floating VEB configuration for VFs */
810 for (idx = 0; idx < I40E_MAX_VF; idx++)
811 vf_floating_veb[idx] = false;
815 while (isblank(*floating_veb_value))
816 floating_veb_value++;
817 if (*floating_veb_value == '\0')
820 idx = strtoul(floating_veb_value, &end, 10);
821 if (errno || end == NULL)
823 while (isblank(*end))
827 } else if ((*end == ';') || (*end == '\0')) {
829 if (min == I40E_MAX_VF)
831 if (max >= I40E_MAX_VF)
832 max = I40E_MAX_VF - 1;
833 for (idx = min; idx <= max; idx++) {
834 vf_floating_veb[idx] = true;
841 floating_veb_value = end + 1;
842 } while (*end != '\0');
851 config_vf_floating_veb(struct rte_devargs *devargs,
852 uint16_t floating_veb,
853 bool *vf_floating_veb)
855 struct rte_kvargs *kvlist;
857 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
861 /* All the VFs attach to the floating VEB by default
862 * when the floating VEB is enabled.
864 for (i = 0; i < I40E_MAX_VF; i++)
865 vf_floating_veb[i] = true;
870 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
874 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
875 rte_kvargs_free(kvlist);
878 /* When the floating_veb_list parameter exists, all the VFs
879 * will attach to the legacy VEB firstly, then configure VFs
880 * to the floating VEB according to the floating_veb_list.
882 if (rte_kvargs_process(kvlist, floating_veb_list,
883 floating_veb_list_handler,
884 vf_floating_veb) < 0) {
885 rte_kvargs_free(kvlist);
888 rte_kvargs_free(kvlist);
892 i40e_check_floating_handler(__rte_unused const char *key,
894 __rte_unused void *opaque)
896 if (strcmp(value, "1"))
903 is_floating_veb_supported(struct rte_devargs *devargs)
905 struct rte_kvargs *kvlist;
906 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
911 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
915 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
916 rte_kvargs_free(kvlist);
919 /* Floating VEB is enabled when there's key-value:
920 * enable_floating_veb=1
922 if (rte_kvargs_process(kvlist, floating_veb_key,
923 i40e_check_floating_handler, NULL) < 0) {
924 rte_kvargs_free(kvlist);
927 rte_kvargs_free(kvlist);
933 config_floating_veb(struct rte_eth_dev *dev)
935 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
936 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
937 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
939 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
941 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
943 is_floating_veb_supported(pci_dev->device.devargs);
944 config_vf_floating_veb(pci_dev->device.devargs,
946 pf->floating_veb_list);
948 pf->floating_veb = false;
952 #define I40E_L2_TAGS_S_TAG_SHIFT 1
953 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
956 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
958 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
959 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
960 char ethertype_hash_name[RTE_HASH_NAMESIZE];
963 struct rte_hash_parameters ethertype_hash_params = {
964 .name = ethertype_hash_name,
965 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
966 .key_len = sizeof(struct i40e_ethertype_filter_input),
967 .hash_func = rte_hash_crc,
968 .hash_func_init_val = 0,
969 .socket_id = rte_socket_id(),
972 /* Initialize ethertype filter rule list and hash */
973 TAILQ_INIT(ðertype_rule->ethertype_list);
974 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
975 "ethertype_%s", dev->device->name);
976 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
977 if (!ethertype_rule->hash_table) {
978 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
981 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
982 sizeof(struct i40e_ethertype_filter *) *
983 I40E_MAX_ETHERTYPE_FILTER_NUM,
985 if (!ethertype_rule->hash_map) {
987 "Failed to allocate memory for ethertype hash map!");
989 goto err_ethertype_hash_map_alloc;
994 err_ethertype_hash_map_alloc:
995 rte_hash_free(ethertype_rule->hash_table);
1001 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1003 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1004 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1005 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1008 struct rte_hash_parameters tunnel_hash_params = {
1009 .name = tunnel_hash_name,
1010 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1011 .key_len = sizeof(struct i40e_tunnel_filter_input),
1012 .hash_func = rte_hash_crc,
1013 .hash_func_init_val = 0,
1014 .socket_id = rte_socket_id(),
1017 /* Initialize tunnel filter rule list and hash */
1018 TAILQ_INIT(&tunnel_rule->tunnel_list);
1019 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1020 "tunnel_%s", dev->device->name);
1021 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1022 if (!tunnel_rule->hash_table) {
1023 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1026 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1027 sizeof(struct i40e_tunnel_filter *) *
1028 I40E_MAX_TUNNEL_FILTER_NUM,
1030 if (!tunnel_rule->hash_map) {
1032 "Failed to allocate memory for tunnel hash map!");
1034 goto err_tunnel_hash_map_alloc;
1039 err_tunnel_hash_map_alloc:
1040 rte_hash_free(tunnel_rule->hash_table);
1046 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1048 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1049 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1050 struct i40e_fdir_info *fdir_info = &pf->fdir;
1051 char fdir_hash_name[RTE_HASH_NAMESIZE];
1052 uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1053 uint32_t best = hw->func_caps.fd_filters_best_effort;
1054 struct rte_bitmap *bmp = NULL;
1060 struct rte_hash_parameters fdir_hash_params = {
1061 .name = fdir_hash_name,
1062 .entries = I40E_MAX_FDIR_FILTER_NUM,
1063 .key_len = sizeof(struct i40e_fdir_input),
1064 .hash_func = rte_hash_crc,
1065 .hash_func_init_val = 0,
1066 .socket_id = rte_socket_id(),
1069 /* Initialize flow director filter rule list and hash */
1070 TAILQ_INIT(&fdir_info->fdir_list);
1071 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1072 "fdir_%s", dev->device->name);
1073 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1074 if (!fdir_info->hash_table) {
1075 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1079 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1080 sizeof(struct i40e_fdir_filter *) *
1081 I40E_MAX_FDIR_FILTER_NUM,
1083 if (!fdir_info->hash_map) {
1085 "Failed to allocate memory for fdir hash map!");
1087 goto err_fdir_hash_map_alloc;
1090 fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1091 sizeof(struct i40e_fdir_filter) *
1092 I40E_MAX_FDIR_FILTER_NUM,
1095 if (!fdir_info->fdir_filter_array) {
1097 "Failed to allocate memory for fdir filter array!");
1099 goto err_fdir_filter_array_alloc;
1102 fdir_info->fdir_space_size = alloc + best;
1103 fdir_info->fdir_actual_cnt = 0;
1104 fdir_info->fdir_guarantee_total_space = alloc;
1105 fdir_info->fdir_guarantee_free_space =
1106 fdir_info->fdir_guarantee_total_space;
1108 PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1110 fdir_info->fdir_flow_pool.pool =
1111 rte_zmalloc("i40e_fdir_entry",
1112 sizeof(struct i40e_fdir_entry) *
1113 fdir_info->fdir_space_size,
1116 if (!fdir_info->fdir_flow_pool.pool) {
1118 "Failed to allocate memory for bitmap flow!");
1120 goto err_fdir_bitmap_flow_alloc;
1123 for (i = 0; i < fdir_info->fdir_space_size; i++)
1124 fdir_info->fdir_flow_pool.pool[i].idx = i;
1127 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1128 mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1131 "Failed to allocate memory for fdir bitmap!");
1133 goto err_fdir_mem_alloc;
1135 bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1138 "Failed to initialization fdir bitmap!");
1140 goto err_fdir_bmp_alloc;
1142 for (i = 0; i < fdir_info->fdir_space_size; i++)
1143 rte_bitmap_set(bmp, i);
1145 fdir_info->fdir_flow_pool.bitmap = bmp;
1152 rte_free(fdir_info->fdir_flow_pool.pool);
1153 err_fdir_bitmap_flow_alloc:
1154 rte_free(fdir_info->fdir_filter_array);
1155 err_fdir_filter_array_alloc:
1156 rte_free(fdir_info->hash_map);
1157 err_fdir_hash_map_alloc:
1158 rte_hash_free(fdir_info->hash_table);
1164 i40e_init_customized_info(struct i40e_pf *pf)
1168 /* Initialize customized pctype */
1169 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1170 pf->customized_pctype[i].index = i;
1171 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1172 pf->customized_pctype[i].valid = false;
1175 pf->gtp_support = false;
1176 pf->esp_support = false;
1180 i40e_init_filter_invalidation(struct i40e_pf *pf)
1182 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1183 struct i40e_fdir_info *fdir_info = &pf->fdir;
1184 uint32_t glqf_ctl_reg = 0;
1186 glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1187 if (!pf->support_multi_driver) {
1188 fdir_info->fdir_invalprio = 1;
1189 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1190 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1191 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1193 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1194 fdir_info->fdir_invalprio = 1;
1195 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1197 fdir_info->fdir_invalprio = 0;
1198 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1204 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1206 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1207 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1208 struct i40e_queue_regions *info = &pf->queue_region;
1211 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1212 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1214 memset(info, 0, sizeof(struct i40e_queue_regions));
1218 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1223 unsigned long support_multi_driver;
1226 pf = (struct i40e_pf *)opaque;
1229 support_multi_driver = strtoul(value, &end, 10);
1230 if (errno != 0 || end == value || *end != 0) {
1231 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1235 if (support_multi_driver == 1 || support_multi_driver == 0)
1236 pf->support_multi_driver = (bool)support_multi_driver;
1238 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1239 "enable global configuration by default."
1240 ETH_I40E_SUPPORT_MULTI_DRIVER);
1245 i40e_support_multi_driver(struct rte_eth_dev *dev)
1247 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1248 struct rte_kvargs *kvlist;
1251 /* Enable global configuration by default */
1252 pf->support_multi_driver = false;
1254 if (!dev->device->devargs)
1257 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1261 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1262 if (!kvargs_count) {
1263 rte_kvargs_free(kvlist);
1267 if (kvargs_count > 1)
1268 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1269 "the first invalid or last valid one is used !",
1270 ETH_I40E_SUPPORT_MULTI_DRIVER);
1272 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1273 i40e_parse_multi_drv_handler, pf) < 0) {
1274 rte_kvargs_free(kvlist);
1278 rte_kvargs_free(kvlist);
1283 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1284 uint32_t reg_addr, uint64_t reg_val,
1285 struct i40e_asq_cmd_details *cmd_details)
1287 uint64_t ori_reg_val;
1288 struct rte_eth_dev *dev;
1291 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1292 if (ret != I40E_SUCCESS) {
1294 "Fail to debug read from 0x%08x",
1298 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1300 if (ori_reg_val != reg_val)
1301 PMD_DRV_LOG(WARNING,
1302 "i40e device %s changed global register [0x%08x]."
1303 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1304 dev->device->name, reg_addr, ori_reg_val, reg_val);
1306 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1310 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1314 struct i40e_adapter *ad = opaque;
1317 use_latest_vec = atoi(value);
1319 if (use_latest_vec != 0 && use_latest_vec != 1)
1320 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1322 ad->use_latest_vec = (uint8_t)use_latest_vec;
1328 i40e_use_latest_vec(struct rte_eth_dev *dev)
1330 struct i40e_adapter *ad =
1331 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1332 struct rte_kvargs *kvlist;
1335 ad->use_latest_vec = false;
1337 if (!dev->device->devargs)
1340 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1344 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1345 if (!kvargs_count) {
1346 rte_kvargs_free(kvlist);
1350 if (kvargs_count > 1)
1351 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1352 "the first invalid or last valid one is used !",
1353 ETH_I40E_USE_LATEST_VEC);
1355 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1356 i40e_parse_latest_vec_handler, ad) < 0) {
1357 rte_kvargs_free(kvlist);
1361 rte_kvargs_free(kvlist);
1366 read_vf_msg_config(__rte_unused const char *key,
1370 struct i40e_vf_msg_cfg *cfg = opaque;
1372 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1373 &cfg->ignore_second) != 3) {
1374 memset(cfg, 0, sizeof(*cfg));
1375 PMD_DRV_LOG(ERR, "format error! example: "
1376 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1381 * If the message validation function been enabled, the 'period'
1382 * and 'ignore_second' must greater than 0.
1384 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1385 memset(cfg, 0, sizeof(*cfg));
1386 PMD_DRV_LOG(ERR, "%s error! the second and third"
1387 " number must be greater than 0!",
1388 ETH_I40E_VF_MSG_CFG);
1396 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1397 struct i40e_vf_msg_cfg *msg_cfg)
1399 struct rte_kvargs *kvlist;
1403 memset(msg_cfg, 0, sizeof(*msg_cfg));
1405 if (!dev->device->devargs)
1408 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1412 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1416 if (kvargs_count > 1) {
1417 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1418 ETH_I40E_VF_MSG_CFG);
1423 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1424 read_vf_msg_config, msg_cfg) < 0)
1428 rte_kvargs_free(kvlist);
1432 #define I40E_ALARM_INTERVAL 50000 /* us */
1435 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1437 struct rte_pci_device *pci_dev;
1438 struct rte_intr_handle *intr_handle;
1439 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1440 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1441 struct i40e_vsi *vsi;
1444 uint8_t aq_fail = 0;
1446 PMD_INIT_FUNC_TRACE();
1448 dev->dev_ops = &i40e_eth_dev_ops;
1449 dev->rx_pkt_burst = i40e_recv_pkts;
1450 dev->tx_pkt_burst = i40e_xmit_pkts;
1451 dev->tx_pkt_prepare = i40e_prep_pkts;
1453 /* for secondary processes, we don't initialise any further as primary
1454 * has already done this work. Only check we don't need a different
1456 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1457 i40e_set_rx_function(dev);
1458 i40e_set_tx_function(dev);
1461 i40e_set_default_ptype_table(dev);
1462 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1463 intr_handle = &pci_dev->intr_handle;
1465 rte_eth_copy_pci_info(dev, pci_dev);
1467 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1468 pf->adapter->eth_dev = dev;
1469 pf->dev_data = dev->data;
1471 hw->back = I40E_PF_TO_ADAPTER(pf);
1472 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1475 "Hardware is not available, as address is NULL");
1479 hw->vendor_id = pci_dev->id.vendor_id;
1480 hw->device_id = pci_dev->id.device_id;
1481 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1482 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1483 hw->bus.device = pci_dev->addr.devid;
1484 hw->bus.func = pci_dev->addr.function;
1485 hw->adapter_stopped = 0;
1486 hw->adapter_closed = 0;
1488 /* Init switch device pointer */
1489 hw->switch_dev = NULL;
1492 * Switch Tag value should not be identical to either the First Tag
1493 * or Second Tag values. So set something other than common Ethertype
1494 * for internal switching.
1496 hw->switch_tag = 0xffff;
1498 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1499 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1500 PMD_INIT_LOG(ERR, "\nERROR: "
1501 "Firmware recovery mode detected. Limiting functionality.\n"
1502 "Refer to the Intel(R) Ethernet Adapters and Devices "
1503 "User Guide for details on firmware recovery mode.");
1507 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1508 /* Check if need to support multi-driver */
1509 i40e_support_multi_driver(dev);
1510 /* Check if users want the latest supported vec path */
1511 i40e_use_latest_vec(dev);
1513 /* Make sure all is clean before doing PF reset */
1516 /* Reset here to make sure all is clean for each PF */
1517 ret = i40e_pf_reset(hw);
1519 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1523 /* Initialize the shared code (base driver) */
1524 ret = i40e_init_shared_code(hw);
1526 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1530 /* Initialize the parameters for adminq */
1531 i40e_init_adminq_parameter(hw);
1532 ret = i40e_init_adminq(hw);
1533 if (ret != I40E_SUCCESS) {
1534 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1537 /* Firmware of SFP x722 does not support adminq option */
1538 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1539 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1541 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1542 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1543 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1544 ((hw->nvm.version >> 12) & 0xf),
1545 ((hw->nvm.version >> 4) & 0xff),
1546 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1548 /* Initialize the hardware */
1551 i40e_config_automask(pf);
1553 i40e_set_default_pctype_table(dev);
1556 * To work around the NVM issue, initialize registers
1557 * for packet type of QinQ by software.
1558 * It should be removed once issues are fixed in NVM.
1560 if (!pf->support_multi_driver)
1561 i40e_GLQF_reg_init(hw);
1563 /* Initialize the input set for filters (hash and fd) to default value */
1564 i40e_filter_input_set_init(pf);
1566 /* initialise the L3_MAP register */
1567 if (!pf->support_multi_driver) {
1568 ret = i40e_aq_debug_write_global_register(hw,
1569 I40E_GLQF_L3_MAP(40),
1572 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1575 "Global register 0x%08x is changed with 0x28",
1576 I40E_GLQF_L3_MAP(40));
1579 /* Need the special FW version to support floating VEB */
1580 config_floating_veb(dev);
1581 /* Clear PXE mode */
1582 i40e_clear_pxe_mode(hw);
1583 i40e_dev_sync_phy_type(hw);
1586 * On X710, performance number is far from the expectation on recent
1587 * firmware versions. The fix for this issue may not be integrated in
1588 * the following firmware version. So the workaround in software driver
1589 * is needed. It needs to modify the initial values of 3 internal only
1590 * registers. Note that the workaround can be removed when it is fixed
1591 * in firmware in the future.
1593 i40e_configure_registers(hw);
1595 /* Get hw capabilities */
1596 ret = i40e_get_cap(hw);
1597 if (ret != I40E_SUCCESS) {
1598 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1599 goto err_get_capabilities;
1602 /* Initialize parameters for PF */
1603 ret = i40e_pf_parameter_init(dev);
1605 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1606 goto err_parameter_init;
1609 /* Initialize the queue management */
1610 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1612 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1613 goto err_qp_pool_init;
1615 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1616 hw->func_caps.num_msix_vectors - 1);
1618 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1619 goto err_msix_pool_init;
1622 /* Initialize lan hmc */
1623 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1624 hw->func_caps.num_rx_qp, 0, 0);
1625 if (ret != I40E_SUCCESS) {
1626 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1627 goto err_init_lan_hmc;
1630 /* Configure lan hmc */
1631 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1632 if (ret != I40E_SUCCESS) {
1633 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1634 goto err_configure_lan_hmc;
1637 /* Get and check the mac address */
1638 i40e_get_mac_addr(hw, hw->mac.addr);
1639 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1640 PMD_INIT_LOG(ERR, "mac address is not valid");
1642 goto err_get_mac_addr;
1644 /* Copy the permanent MAC address */
1645 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1646 (struct rte_ether_addr *)hw->mac.perm_addr);
1648 /* Disable flow control */
1649 hw->fc.requested_mode = I40E_FC_NONE;
1650 i40e_set_fc(hw, &aq_fail, TRUE);
1652 /* Set the global registers with default ether type value */
1653 if (!pf->support_multi_driver) {
1654 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1655 RTE_ETHER_TYPE_VLAN);
1656 if (ret != I40E_SUCCESS) {
1658 "Failed to set the default outer "
1660 goto err_setup_pf_switch;
1664 /* PF setup, which includes VSI setup */
1665 ret = i40e_pf_setup(pf);
1667 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1668 goto err_setup_pf_switch;
1673 /* Disable double vlan by default */
1674 i40e_vsi_config_double_vlan(vsi, FALSE);
1676 /* Disable S-TAG identification when floating_veb is disabled */
1677 if (!pf->floating_veb) {
1678 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1679 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1680 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1681 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1685 if (!vsi->max_macaddrs)
1686 len = RTE_ETHER_ADDR_LEN;
1688 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1690 /* Should be after VSI initialized */
1691 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1692 if (!dev->data->mac_addrs) {
1694 "Failed to allocated memory for storing mac address");
1697 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1698 &dev->data->mac_addrs[0]);
1700 /* Pass the information to the rte_eth_dev_close() that it should also
1701 * release the private port resources.
1703 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1705 /* Init dcb to sw mode by default */
1706 ret = i40e_dcb_init_configure(dev, TRUE);
1707 if (ret != I40E_SUCCESS) {
1708 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1709 pf->flags &= ~I40E_FLAG_DCB;
1711 /* Update HW struct after DCB configuration */
1714 /* initialize pf host driver to setup SRIOV resource if applicable */
1715 i40e_pf_host_init(dev);
1717 /* register callback func to eal lib */
1718 rte_intr_callback_register(intr_handle,
1719 i40e_dev_interrupt_handler, dev);
1721 /* configure and enable device interrupt */
1722 i40e_pf_config_irq0(hw, TRUE);
1723 i40e_pf_enable_irq0(hw);
1725 /* enable uio intr after callback register */
1726 rte_intr_enable(intr_handle);
1728 /* By default disable flexible payload in global configuration */
1729 if (!pf->support_multi_driver)
1730 i40e_flex_payload_reg_set_default(hw);
1733 * Add an ethertype filter to drop all flow control frames transmitted
1734 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1737 i40e_add_tx_flow_control_drop_filter(pf);
1739 /* Set the max frame size to 0x2600 by default,
1740 * in case other drivers changed the default value.
1742 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1744 /* initialize mirror rule list */
1745 TAILQ_INIT(&pf->mirror_list);
1747 /* initialize RSS rule list */
1748 TAILQ_INIT(&pf->rss_config_list);
1750 /* initialize Traffic Manager configuration */
1751 i40e_tm_conf_init(dev);
1753 /* Initialize customized information */
1754 i40e_init_customized_info(pf);
1756 /* Initialize the filter invalidation configuration */
1757 i40e_init_filter_invalidation(pf);
1759 ret = i40e_init_ethtype_filter_list(dev);
1761 goto err_init_ethtype_filter_list;
1762 ret = i40e_init_tunnel_filter_list(dev);
1764 goto err_init_tunnel_filter_list;
1765 ret = i40e_init_fdir_filter_list(dev);
1767 goto err_init_fdir_filter_list;
1769 /* initialize queue region configuration */
1770 i40e_init_queue_region_conf(dev);
1772 /* initialize RSS configuration from rte_flow */
1773 memset(&pf->rss_info, 0,
1774 sizeof(struct i40e_rte_flow_rss_conf));
1776 /* reset all stats of the device, including pf and main vsi */
1777 i40e_dev_stats_reset(dev);
1781 err_init_fdir_filter_list:
1782 rte_free(pf->tunnel.hash_table);
1783 rte_free(pf->tunnel.hash_map);
1784 err_init_tunnel_filter_list:
1785 rte_free(pf->ethertype.hash_table);
1786 rte_free(pf->ethertype.hash_map);
1787 err_init_ethtype_filter_list:
1788 rte_free(dev->data->mac_addrs);
1789 dev->data->mac_addrs = NULL;
1791 i40e_vsi_release(pf->main_vsi);
1792 err_setup_pf_switch:
1794 err_configure_lan_hmc:
1795 (void)i40e_shutdown_lan_hmc(hw);
1797 i40e_res_pool_destroy(&pf->msix_pool);
1799 i40e_res_pool_destroy(&pf->qp_pool);
1802 err_get_capabilities:
1803 (void)i40e_shutdown_adminq(hw);
1809 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1811 struct i40e_ethertype_filter *p_ethertype;
1812 struct i40e_ethertype_rule *ethertype_rule;
1814 ethertype_rule = &pf->ethertype;
1815 /* Remove all ethertype filter rules and hash */
1816 if (ethertype_rule->hash_map)
1817 rte_free(ethertype_rule->hash_map);
1818 if (ethertype_rule->hash_table)
1819 rte_hash_free(ethertype_rule->hash_table);
1821 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1822 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1823 p_ethertype, rules);
1824 rte_free(p_ethertype);
1829 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1831 struct i40e_tunnel_filter *p_tunnel;
1832 struct i40e_tunnel_rule *tunnel_rule;
1834 tunnel_rule = &pf->tunnel;
1835 /* Remove all tunnel director rules and hash */
1836 if (tunnel_rule->hash_map)
1837 rte_free(tunnel_rule->hash_map);
1838 if (tunnel_rule->hash_table)
1839 rte_hash_free(tunnel_rule->hash_table);
1841 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1842 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1848 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1850 struct i40e_fdir_filter *p_fdir;
1851 struct i40e_fdir_info *fdir_info;
1853 fdir_info = &pf->fdir;
1855 /* Remove all flow director rules */
1856 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1857 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1861 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1863 struct i40e_fdir_info *fdir_info;
1865 fdir_info = &pf->fdir;
1867 /* flow director memory cleanup */
1868 if (fdir_info->hash_map)
1869 rte_free(fdir_info->hash_map);
1870 if (fdir_info->hash_table)
1871 rte_hash_free(fdir_info->hash_table);
1872 if (fdir_info->fdir_flow_pool.bitmap)
1873 rte_bitmap_free(fdir_info->fdir_flow_pool.bitmap);
1874 if (fdir_info->fdir_flow_pool.pool)
1875 rte_free(fdir_info->fdir_flow_pool.pool);
1876 if (fdir_info->fdir_filter_array)
1877 rte_free(fdir_info->fdir_filter_array);
1880 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1883 * Disable by default flexible payload
1884 * for corresponding L2/L3/L4 layers.
1886 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1887 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1888 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1892 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1896 PMD_INIT_FUNC_TRACE();
1898 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1901 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1903 if (hw->adapter_closed == 0)
1904 i40e_dev_close(dev);
1910 i40e_dev_configure(struct rte_eth_dev *dev)
1912 struct i40e_adapter *ad =
1913 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1914 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1915 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1916 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1919 ret = i40e_dev_sync_phy_type(hw);
1923 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1924 * bulk allocation or vector Rx preconditions we will reset it.
1926 ad->rx_bulk_alloc_allowed = true;
1927 ad->rx_vec_allowed = true;
1928 ad->tx_simple_allowed = true;
1929 ad->tx_vec_allowed = true;
1931 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1932 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1934 /* Only legacy filter API needs the following fdir config. So when the
1935 * legacy filter API is deprecated, the following codes should also be
1938 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1939 ret = i40e_fdir_setup(pf);
1940 if (ret != I40E_SUCCESS) {
1941 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1944 ret = i40e_fdir_configure(dev);
1946 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1950 i40e_fdir_teardown(pf);
1952 ret = i40e_dev_init_vlan(dev);
1957 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1958 * RSS setting have different requirements.
1959 * General PMD driver call sequence are NIC init, configure,
1960 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1961 * will try to lookup the VSI that specific queue belongs to if VMDQ
1962 * applicable. So, VMDQ setting has to be done before
1963 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1964 * For RSS setting, it will try to calculate actual configured RX queue
1965 * number, which will be available after rx_queue_setup(). dev_start()
1966 * function is good to place RSS setup.
1968 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1969 ret = i40e_vmdq_setup(dev);
1974 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1975 ret = i40e_dcb_setup(dev);
1977 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1982 TAILQ_INIT(&pf->flow_list);
1987 /* need to release vmdq resource if exists */
1988 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1989 i40e_vsi_release(pf->vmdq[i].vsi);
1990 pf->vmdq[i].vsi = NULL;
1995 /* Need to release fdir resource if exists.
1996 * Only legacy filter API needs the following fdir config. So when the
1997 * legacy filter API is deprecated, the following code should also be
2000 i40e_fdir_teardown(pf);
2005 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
2007 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2008 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2009 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2010 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2011 uint16_t msix_vect = vsi->msix_intr;
2014 for (i = 0; i < vsi->nb_qps; i++) {
2015 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2016 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2020 if (vsi->type != I40E_VSI_SRIOV) {
2021 if (!rte_intr_allow_others(intr_handle)) {
2022 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2023 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2025 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2028 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2029 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2031 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2036 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2037 vsi->user_param + (msix_vect - 1);
2039 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2040 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2042 I40E_WRITE_FLUSH(hw);
2046 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2047 int base_queue, int nb_queue,
2052 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2053 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2055 /* Bind all RX queues to allocated MSIX interrupt */
2056 for (i = 0; i < nb_queue; i++) {
2057 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2058 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2059 ((base_queue + i + 1) <<
2060 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2061 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2062 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2064 if (i == nb_queue - 1)
2065 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2066 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2069 /* Write first RX queue to Link list register as the head element */
2070 if (vsi->type != I40E_VSI_SRIOV) {
2072 i40e_calc_itr_interval(1, pf->support_multi_driver);
2074 if (msix_vect == I40E_MISC_VEC_ID) {
2075 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2077 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2079 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2081 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2084 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2086 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2088 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2090 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2097 if (msix_vect == I40E_MISC_VEC_ID) {
2099 I40E_VPINT_LNKLST0(vsi->user_param),
2101 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2103 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2105 /* num_msix_vectors_vf needs to minus irq0 */
2106 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2107 vsi->user_param + (msix_vect - 1);
2109 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2111 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2113 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2117 I40E_WRITE_FLUSH(hw);
2121 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2123 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2124 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2125 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2126 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2127 uint16_t msix_vect = vsi->msix_intr;
2128 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2129 uint16_t queue_idx = 0;
2133 for (i = 0; i < vsi->nb_qps; i++) {
2134 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2135 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2138 /* VF bind interrupt */
2139 if (vsi->type == I40E_VSI_SRIOV) {
2140 __vsi_queues_bind_intr(vsi, msix_vect,
2141 vsi->base_queue, vsi->nb_qps,
2146 /* PF & VMDq bind interrupt */
2147 if (rte_intr_dp_is_en(intr_handle)) {
2148 if (vsi->type == I40E_VSI_MAIN) {
2151 } else if (vsi->type == I40E_VSI_VMDQ2) {
2152 struct i40e_vsi *main_vsi =
2153 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2154 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2159 for (i = 0; i < vsi->nb_used_qps; i++) {
2161 if (!rte_intr_allow_others(intr_handle))
2162 /* allow to share MISC_VEC_ID */
2163 msix_vect = I40E_MISC_VEC_ID;
2165 /* no enough msix_vect, map all to one */
2166 __vsi_queues_bind_intr(vsi, msix_vect,
2167 vsi->base_queue + i,
2168 vsi->nb_used_qps - i,
2170 for (; !!record && i < vsi->nb_used_qps; i++)
2171 intr_handle->intr_vec[queue_idx + i] =
2175 /* 1:1 queue/msix_vect mapping */
2176 __vsi_queues_bind_intr(vsi, msix_vect,
2177 vsi->base_queue + i, 1,
2180 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2188 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2190 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2191 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2192 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2193 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2194 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2195 uint16_t msix_intr, i;
2197 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2198 for (i = 0; i < vsi->nb_msix; i++) {
2199 msix_intr = vsi->msix_intr + i;
2200 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2201 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2202 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2203 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2206 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2207 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2208 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2209 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2211 I40E_WRITE_FLUSH(hw);
2215 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2217 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2218 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2219 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2220 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2221 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2222 uint16_t msix_intr, i;
2224 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2225 for (i = 0; i < vsi->nb_msix; i++) {
2226 msix_intr = vsi->msix_intr + i;
2227 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2228 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2231 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2232 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2234 I40E_WRITE_FLUSH(hw);
2237 static inline uint8_t
2238 i40e_parse_link_speeds(uint16_t link_speeds)
2240 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2242 if (link_speeds & ETH_LINK_SPEED_40G)
2243 link_speed |= I40E_LINK_SPEED_40GB;
2244 if (link_speeds & ETH_LINK_SPEED_25G)
2245 link_speed |= I40E_LINK_SPEED_25GB;
2246 if (link_speeds & ETH_LINK_SPEED_20G)
2247 link_speed |= I40E_LINK_SPEED_20GB;
2248 if (link_speeds & ETH_LINK_SPEED_10G)
2249 link_speed |= I40E_LINK_SPEED_10GB;
2250 if (link_speeds & ETH_LINK_SPEED_1G)
2251 link_speed |= I40E_LINK_SPEED_1GB;
2252 if (link_speeds & ETH_LINK_SPEED_100M)
2253 link_speed |= I40E_LINK_SPEED_100MB;
2259 i40e_phy_conf_link(struct i40e_hw *hw,
2261 uint8_t force_speed,
2264 enum i40e_status_code status;
2265 struct i40e_aq_get_phy_abilities_resp phy_ab;
2266 struct i40e_aq_set_phy_config phy_conf;
2267 enum i40e_aq_phy_type cnt;
2268 uint8_t avail_speed;
2269 uint32_t phy_type_mask = 0;
2271 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2272 I40E_AQ_PHY_FLAG_PAUSE_RX |
2273 I40E_AQ_PHY_FLAG_PAUSE_RX |
2274 I40E_AQ_PHY_FLAG_LOW_POWER;
2277 /* To get phy capabilities of available speeds. */
2278 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2281 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2285 avail_speed = phy_ab.link_speed;
2287 /* To get the current phy config. */
2288 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2291 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2296 /* If link needs to go up and it is in autoneg mode the speed is OK,
2297 * no need to set up again.
2299 if (is_up && phy_ab.phy_type != 0 &&
2300 abilities & I40E_AQ_PHY_AN_ENABLED &&
2301 phy_ab.link_speed != 0)
2302 return I40E_SUCCESS;
2304 memset(&phy_conf, 0, sizeof(phy_conf));
2306 /* bits 0-2 use the values from get_phy_abilities_resp */
2308 abilities |= phy_ab.abilities & mask;
2310 phy_conf.abilities = abilities;
2312 /* If link needs to go up, but the force speed is not supported,
2313 * Warn users and config the default available speeds.
2315 if (is_up && !(force_speed & avail_speed)) {
2316 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2317 phy_conf.link_speed = avail_speed;
2319 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2322 /* PHY type mask needs to include each type except PHY type extension */
2323 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2324 phy_type_mask |= 1 << cnt;
2326 /* use get_phy_abilities_resp value for the rest */
2327 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2328 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2329 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2330 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2331 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2332 phy_conf.eee_capability = phy_ab.eee_capability;
2333 phy_conf.eeer = phy_ab.eeer_val;
2334 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2336 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2337 phy_ab.abilities, phy_ab.link_speed);
2338 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2339 phy_conf.abilities, phy_conf.link_speed);
2341 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2345 return I40E_SUCCESS;
2349 i40e_apply_link_speed(struct rte_eth_dev *dev)
2352 uint8_t abilities = 0;
2353 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354 struct rte_eth_conf *conf = &dev->data->dev_conf;
2356 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2357 I40E_AQ_PHY_LINK_ENABLED;
2359 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2360 conf->link_speeds = ETH_LINK_SPEED_40G |
2361 ETH_LINK_SPEED_25G |
2362 ETH_LINK_SPEED_20G |
2363 ETH_LINK_SPEED_10G |
2365 ETH_LINK_SPEED_100M;
2367 abilities |= I40E_AQ_PHY_AN_ENABLED;
2369 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2371 speed = i40e_parse_link_speeds(conf->link_speeds);
2373 return i40e_phy_conf_link(hw, abilities, speed, true);
2377 i40e_dev_start(struct rte_eth_dev *dev)
2379 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2380 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2381 struct i40e_vsi *main_vsi = pf->main_vsi;
2383 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2384 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2385 uint32_t intr_vector = 0;
2386 struct i40e_vsi *vsi;
2387 uint16_t nb_rxq, nb_txq;
2389 hw->adapter_stopped = 0;
2391 rte_intr_disable(intr_handle);
2393 if ((rte_intr_cap_multiple(intr_handle) ||
2394 !RTE_ETH_DEV_SRIOV(dev).active) &&
2395 dev->data->dev_conf.intr_conf.rxq != 0) {
2396 intr_vector = dev->data->nb_rx_queues;
2397 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2402 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2403 intr_handle->intr_vec =
2404 rte_zmalloc("intr_vec",
2405 dev->data->nb_rx_queues * sizeof(int),
2407 if (!intr_handle->intr_vec) {
2409 "Failed to allocate %d rx_queues intr_vec",
2410 dev->data->nb_rx_queues);
2415 /* Initialize VSI */
2416 ret = i40e_dev_rxtx_init(pf);
2417 if (ret != I40E_SUCCESS) {
2418 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2422 /* Map queues with MSIX interrupt */
2423 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2424 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2425 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2426 i40e_vsi_enable_queues_intr(main_vsi);
2428 /* Map VMDQ VSI queues with MSIX interrupt */
2429 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2430 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2431 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2432 I40E_ITR_INDEX_DEFAULT);
2433 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2436 /* enable FDIR MSIX interrupt */
2437 if (pf->fdir.fdir_vsi) {
2438 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2439 I40E_ITR_INDEX_NONE);
2440 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2443 /* Enable all queues which have been configured */
2444 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2445 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2450 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2451 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2456 /* Enable receiving broadcast packets */
2457 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2458 if (ret != I40E_SUCCESS)
2459 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2461 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2462 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2464 if (ret != I40E_SUCCESS)
2465 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2468 /* Enable the VLAN promiscuous mode. */
2470 for (i = 0; i < pf->vf_num; i++) {
2471 vsi = pf->vfs[i].vsi;
2472 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2477 /* Enable mac loopback mode */
2478 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2479 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2480 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2481 if (ret != I40E_SUCCESS) {
2482 PMD_DRV_LOG(ERR, "fail to set loopback link");
2487 /* Apply link configure */
2488 ret = i40e_apply_link_speed(dev);
2489 if (I40E_SUCCESS != ret) {
2490 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2494 if (!rte_intr_allow_others(intr_handle)) {
2495 rte_intr_callback_unregister(intr_handle,
2496 i40e_dev_interrupt_handler,
2498 /* configure and enable device interrupt */
2499 i40e_pf_config_irq0(hw, FALSE);
2500 i40e_pf_enable_irq0(hw);
2502 if (dev->data->dev_conf.intr_conf.lsc != 0)
2504 "lsc won't enable because of no intr multiplex");
2506 ret = i40e_aq_set_phy_int_mask(hw,
2507 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2508 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2509 I40E_AQ_EVENT_MEDIA_NA), NULL);
2510 if (ret != I40E_SUCCESS)
2511 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2513 /* Call get_link_info aq commond to enable/disable LSE */
2514 i40e_dev_link_update(dev, 0);
2517 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2518 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2519 i40e_dev_alarm_handler, dev);
2521 /* enable uio intr after callback register */
2522 rte_intr_enable(intr_handle);
2525 i40e_filter_restore(pf);
2527 if (pf->tm_conf.root && !pf->tm_conf.committed)
2528 PMD_DRV_LOG(WARNING,
2529 "please call hierarchy_commit() "
2530 "before starting the port");
2532 return I40E_SUCCESS;
2535 for (i = 0; i < nb_txq; i++)
2536 i40e_dev_tx_queue_stop(dev, i);
2538 for (i = 0; i < nb_rxq; i++)
2539 i40e_dev_rx_queue_stop(dev, i);
2545 i40e_dev_stop(struct rte_eth_dev *dev)
2547 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2548 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549 struct i40e_vsi *main_vsi = pf->main_vsi;
2550 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2551 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2554 if (hw->adapter_stopped == 1)
2557 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2558 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2559 rte_intr_enable(intr_handle);
2562 /* Disable all queues */
2563 for (i = 0; i < dev->data->nb_tx_queues; i++)
2564 i40e_dev_tx_queue_stop(dev, i);
2566 for (i = 0; i < dev->data->nb_rx_queues; i++)
2567 i40e_dev_rx_queue_stop(dev, i);
2569 /* un-map queues with interrupt registers */
2570 i40e_vsi_disable_queues_intr(main_vsi);
2571 i40e_vsi_queues_unbind_intr(main_vsi);
2573 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2574 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2575 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2578 if (pf->fdir.fdir_vsi) {
2579 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2580 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2582 /* Clear all queues and release memory */
2583 i40e_dev_clear_queues(dev);
2586 i40e_dev_set_link_down(dev);
2588 if (!rte_intr_allow_others(intr_handle))
2589 /* resume to the default handler */
2590 rte_intr_callback_register(intr_handle,
2591 i40e_dev_interrupt_handler,
2594 /* Clean datapath event and queue/vec mapping */
2595 rte_intr_efd_disable(intr_handle);
2596 if (intr_handle->intr_vec) {
2597 rte_free(intr_handle->intr_vec);
2598 intr_handle->intr_vec = NULL;
2601 /* reset hierarchy commit */
2602 pf->tm_conf.committed = false;
2604 hw->adapter_stopped = 1;
2606 pf->adapter->rss_reta_updated = 0;
2610 i40e_dev_close(struct rte_eth_dev *dev)
2612 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2613 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2614 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2615 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2616 struct i40e_mirror_rule *p_mirror;
2617 struct i40e_filter_control_settings settings;
2618 struct rte_flow *p_flow;
2622 uint8_t aq_fail = 0;
2625 PMD_INIT_FUNC_TRACE();
2627 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2629 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2634 /* Remove all mirror rules */
2635 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2636 ret = i40e_aq_del_mirror_rule(hw,
2637 pf->main_vsi->veb->seid,
2638 p_mirror->rule_type,
2640 p_mirror->num_entries,
2643 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2644 "status = %d, aq_err = %d.", ret,
2645 hw->aq.asq_last_status);
2647 /* remove mirror software resource anyway */
2648 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2650 pf->nb_mirror_rule--;
2653 i40e_dev_free_queues(dev);
2655 /* Disable interrupt */
2656 i40e_pf_disable_irq0(hw);
2657 rte_intr_disable(intr_handle);
2660 * Only legacy filter API needs the following fdir config. So when the
2661 * legacy filter API is deprecated, the following code should also be
2664 i40e_fdir_teardown(pf);
2666 /* shutdown and destroy the HMC */
2667 i40e_shutdown_lan_hmc(hw);
2669 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2670 i40e_vsi_release(pf->vmdq[i].vsi);
2671 pf->vmdq[i].vsi = NULL;
2676 /* release all the existing VSIs and VEBs */
2677 i40e_vsi_release(pf->main_vsi);
2679 /* shutdown the adminq */
2680 i40e_aq_queue_shutdown(hw, true);
2681 i40e_shutdown_adminq(hw);
2683 i40e_res_pool_destroy(&pf->qp_pool);
2684 i40e_res_pool_destroy(&pf->msix_pool);
2686 /* Disable flexible payload in global configuration */
2687 if (!pf->support_multi_driver)
2688 i40e_flex_payload_reg_set_default(hw);
2690 /* force a PF reset to clean anything leftover */
2691 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2692 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2693 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2694 I40E_WRITE_FLUSH(hw);
2696 dev->dev_ops = NULL;
2697 dev->rx_pkt_burst = NULL;
2698 dev->tx_pkt_burst = NULL;
2700 /* Clear PXE mode */
2701 i40e_clear_pxe_mode(hw);
2703 /* Unconfigure filter control */
2704 memset(&settings, 0, sizeof(settings));
2705 ret = i40e_set_filter_control(hw, &settings);
2707 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2710 /* Disable flow control */
2711 hw->fc.requested_mode = I40E_FC_NONE;
2712 i40e_set_fc(hw, &aq_fail, TRUE);
2714 /* uninitialize pf host driver */
2715 i40e_pf_host_uninit(dev);
2718 ret = rte_intr_callback_unregister(intr_handle,
2719 i40e_dev_interrupt_handler, dev);
2720 if (ret >= 0 || ret == -ENOENT) {
2722 } else if (ret != -EAGAIN) {
2724 "intr callback unregister failed: %d",
2727 i40e_msec_delay(500);
2728 } while (retries++ < 5);
2730 i40e_rm_ethtype_filter_list(pf);
2731 i40e_rm_tunnel_filter_list(pf);
2732 i40e_rm_fdir_filter_list(pf);
2734 /* Remove all flows */
2735 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2736 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2737 /* Do not free FDIR flows since they are static allocated */
2738 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2742 /* release the fdir static allocated memory */
2743 i40e_fdir_memory_cleanup(pf);
2745 /* Remove all Traffic Manager configuration */
2746 i40e_tm_conf_uninit(dev);
2748 hw->adapter_closed = 1;
2752 * Reset PF device only to re-initialize resources in PMD layer
2755 i40e_dev_reset(struct rte_eth_dev *dev)
2759 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2760 * its VF to make them align with it. The detailed notification
2761 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2762 * To avoid unexpected behavior in VF, currently reset of PF with
2763 * SR-IOV activation is not supported. It might be supported later.
2765 if (dev->data->sriov.active)
2768 ret = eth_i40e_dev_uninit(dev);
2772 ret = eth_i40e_dev_init(dev, NULL);
2778 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2780 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782 struct i40e_vsi *vsi = pf->main_vsi;
2785 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2787 if (status != I40E_SUCCESS) {
2788 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2792 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2794 if (status != I40E_SUCCESS) {
2795 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2796 /* Rollback unicast promiscuous mode */
2797 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2806 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2808 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2809 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2810 struct i40e_vsi *vsi = pf->main_vsi;
2813 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2815 if (status != I40E_SUCCESS) {
2816 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2820 /* must remain in all_multicast mode */
2821 if (dev->data->all_multicast == 1)
2824 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2826 if (status != I40E_SUCCESS) {
2827 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2828 /* Rollback unicast promiscuous mode */
2829 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2838 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2840 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2841 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842 struct i40e_vsi *vsi = pf->main_vsi;
2845 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2846 if (ret != I40E_SUCCESS) {
2847 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2855 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2857 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2858 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2859 struct i40e_vsi *vsi = pf->main_vsi;
2862 if (dev->data->promiscuous == 1)
2863 return 0; /* must remain in all_multicast mode */
2865 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2866 vsi->seid, FALSE, NULL);
2867 if (ret != I40E_SUCCESS) {
2868 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2876 * Set device link up.
2879 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2881 /* re-apply link speed setting */
2882 return i40e_apply_link_speed(dev);
2886 * Set device link down.
2889 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2891 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2892 uint8_t abilities = 0;
2893 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2895 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2896 return i40e_phy_conf_link(hw, abilities, speed, false);
2899 static __rte_always_inline void
2900 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2902 /* Link status registers and values*/
2903 #define I40E_PRTMAC_LINKSTA 0x001E2420
2904 #define I40E_REG_LINK_UP 0x40000080
2905 #define I40E_PRTMAC_MACC 0x001E24E0
2906 #define I40E_REG_MACC_25GB 0x00020000
2907 #define I40E_REG_SPEED_MASK 0x38000000
2908 #define I40E_REG_SPEED_0 0x00000000
2909 #define I40E_REG_SPEED_1 0x08000000
2910 #define I40E_REG_SPEED_2 0x10000000
2911 #define I40E_REG_SPEED_3 0x18000000
2912 #define I40E_REG_SPEED_4 0x20000000
2913 uint32_t link_speed;
2916 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2917 link_speed = reg_val & I40E_REG_SPEED_MASK;
2918 reg_val &= I40E_REG_LINK_UP;
2919 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2921 if (unlikely(link->link_status == 0))
2924 /* Parse the link status */
2925 switch (link_speed) {
2926 case I40E_REG_SPEED_0:
2927 link->link_speed = ETH_SPEED_NUM_100M;
2929 case I40E_REG_SPEED_1:
2930 link->link_speed = ETH_SPEED_NUM_1G;
2932 case I40E_REG_SPEED_2:
2933 if (hw->mac.type == I40E_MAC_X722)
2934 link->link_speed = ETH_SPEED_NUM_2_5G;
2936 link->link_speed = ETH_SPEED_NUM_10G;
2938 case I40E_REG_SPEED_3:
2939 if (hw->mac.type == I40E_MAC_X722) {
2940 link->link_speed = ETH_SPEED_NUM_5G;
2942 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2944 if (reg_val & I40E_REG_MACC_25GB)
2945 link->link_speed = ETH_SPEED_NUM_25G;
2947 link->link_speed = ETH_SPEED_NUM_40G;
2950 case I40E_REG_SPEED_4:
2951 if (hw->mac.type == I40E_MAC_X722)
2952 link->link_speed = ETH_SPEED_NUM_10G;
2954 link->link_speed = ETH_SPEED_NUM_20G;
2957 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2962 static __rte_always_inline void
2963 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2964 bool enable_lse, int wait_to_complete)
2966 #define CHECK_INTERVAL 100 /* 100ms */
2967 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2968 uint32_t rep_cnt = MAX_REPEAT_TIME;
2969 struct i40e_link_status link_status;
2972 memset(&link_status, 0, sizeof(link_status));
2975 memset(&link_status, 0, sizeof(link_status));
2977 /* Get link status information from hardware */
2978 status = i40e_aq_get_link_info(hw, enable_lse,
2979 &link_status, NULL);
2980 if (unlikely(status != I40E_SUCCESS)) {
2981 link->link_speed = ETH_SPEED_NUM_NONE;
2982 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2983 PMD_DRV_LOG(ERR, "Failed to get link info");
2987 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2988 if (!wait_to_complete || link->link_status)
2991 rte_delay_ms(CHECK_INTERVAL);
2992 } while (--rep_cnt);
2994 /* Parse the link status */
2995 switch (link_status.link_speed) {
2996 case I40E_LINK_SPEED_100MB:
2997 link->link_speed = ETH_SPEED_NUM_100M;
2999 case I40E_LINK_SPEED_1GB:
3000 link->link_speed = ETH_SPEED_NUM_1G;
3002 case I40E_LINK_SPEED_10GB:
3003 link->link_speed = ETH_SPEED_NUM_10G;
3005 case I40E_LINK_SPEED_20GB:
3006 link->link_speed = ETH_SPEED_NUM_20G;
3008 case I40E_LINK_SPEED_25GB:
3009 link->link_speed = ETH_SPEED_NUM_25G;
3011 case I40E_LINK_SPEED_40GB:
3012 link->link_speed = ETH_SPEED_NUM_40G;
3015 link->link_speed = ETH_SPEED_NUM_NONE;
3021 i40e_dev_link_update(struct rte_eth_dev *dev,
3022 int wait_to_complete)
3024 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3025 struct rte_eth_link link;
3026 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3029 memset(&link, 0, sizeof(link));
3031 /* i40e uses full duplex only */
3032 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3033 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3034 ETH_LINK_SPEED_FIXED);
3036 if (!wait_to_complete && !enable_lse)
3037 update_link_reg(hw, &link);
3039 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3042 rte_eth_linkstatus_get(hw->switch_dev, &link);
3044 ret = rte_eth_linkstatus_set(dev, &link);
3045 i40e_notify_all_vfs_link_status(dev);
3050 /* Get all the statistics of a VSI */
3052 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3054 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3055 struct i40e_eth_stats *nes = &vsi->eth_stats;
3056 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3057 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3059 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3060 vsi->offset_loaded, &oes->rx_bytes,
3062 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3063 vsi->offset_loaded, &oes->rx_unicast,
3065 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3066 vsi->offset_loaded, &oes->rx_multicast,
3067 &nes->rx_multicast);
3068 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3069 vsi->offset_loaded, &oes->rx_broadcast,
3070 &nes->rx_broadcast);
3071 /* exclude CRC bytes */
3072 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3073 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3075 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3076 &oes->rx_discards, &nes->rx_discards);
3077 /* GLV_REPC not supported */
3078 /* GLV_RMPC not supported */
3079 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3080 &oes->rx_unknown_protocol,
3081 &nes->rx_unknown_protocol);
3082 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3083 vsi->offset_loaded, &oes->tx_bytes,
3085 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3086 vsi->offset_loaded, &oes->tx_unicast,
3088 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3089 vsi->offset_loaded, &oes->tx_multicast,
3090 &nes->tx_multicast);
3091 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3092 vsi->offset_loaded, &oes->tx_broadcast,
3093 &nes->tx_broadcast);
3094 /* GLV_TDPC not supported */
3095 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3096 &oes->tx_errors, &nes->tx_errors);
3097 vsi->offset_loaded = true;
3099 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3101 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3102 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3103 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3104 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3105 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3106 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3107 nes->rx_unknown_protocol);
3108 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3109 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3110 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3111 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3112 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3113 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3114 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3119 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3122 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3123 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3125 /* Get rx/tx bytes of internal transfer packets */
3126 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
3127 I40E_GLV_GORCL(hw->port),
3129 &pf->internal_stats_offset.rx_bytes,
3130 &pf->internal_stats.rx_bytes);
3132 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
3133 I40E_GLV_GOTCL(hw->port),
3135 &pf->internal_stats_offset.tx_bytes,
3136 &pf->internal_stats.tx_bytes);
3137 /* Get total internal rx packet count */
3138 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3139 I40E_GLV_UPRCL(hw->port),
3141 &pf->internal_stats_offset.rx_unicast,
3142 &pf->internal_stats.rx_unicast);
3143 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3144 I40E_GLV_MPRCL(hw->port),
3146 &pf->internal_stats_offset.rx_multicast,
3147 &pf->internal_stats.rx_multicast);
3148 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3149 I40E_GLV_BPRCL(hw->port),
3151 &pf->internal_stats_offset.rx_broadcast,
3152 &pf->internal_stats.rx_broadcast);
3153 /* Get total internal tx packet count */
3154 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3155 I40E_GLV_UPTCL(hw->port),
3157 &pf->internal_stats_offset.tx_unicast,
3158 &pf->internal_stats.tx_unicast);
3159 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3160 I40E_GLV_MPTCL(hw->port),
3162 &pf->internal_stats_offset.tx_multicast,
3163 &pf->internal_stats.tx_multicast);
3164 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3165 I40E_GLV_BPTCL(hw->port),
3167 &pf->internal_stats_offset.tx_broadcast,
3168 &pf->internal_stats.tx_broadcast);
3170 /* exclude CRC size */
3171 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3172 pf->internal_stats.rx_multicast +
3173 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3175 /* Get statistics of struct i40e_eth_stats */
3176 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3177 I40E_GLPRT_GORCL(hw->port),
3178 pf->offset_loaded, &os->eth.rx_bytes,
3180 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3181 I40E_GLPRT_UPRCL(hw->port),
3182 pf->offset_loaded, &os->eth.rx_unicast,
3183 &ns->eth.rx_unicast);
3184 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3185 I40E_GLPRT_MPRCL(hw->port),
3186 pf->offset_loaded, &os->eth.rx_multicast,
3187 &ns->eth.rx_multicast);
3188 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3189 I40E_GLPRT_BPRCL(hw->port),
3190 pf->offset_loaded, &os->eth.rx_broadcast,
3191 &ns->eth.rx_broadcast);
3192 /* Workaround: CRC size should not be included in byte statistics,
3193 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3196 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3197 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3199 /* exclude internal rx bytes
3200 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3201 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3203 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3205 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3206 ns->eth.rx_bytes = 0;
3208 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3210 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3211 ns->eth.rx_unicast = 0;
3213 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3215 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3216 ns->eth.rx_multicast = 0;
3218 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3220 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3221 ns->eth.rx_broadcast = 0;
3223 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3225 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3226 pf->offset_loaded, &os->eth.rx_discards,
3227 &ns->eth.rx_discards);
3228 /* GLPRT_REPC not supported */
3229 /* GLPRT_RMPC not supported */
3230 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3232 &os->eth.rx_unknown_protocol,
3233 &ns->eth.rx_unknown_protocol);
3234 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3235 I40E_GLPRT_GOTCL(hw->port),
3236 pf->offset_loaded, &os->eth.tx_bytes,
3238 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3239 I40E_GLPRT_UPTCL(hw->port),
3240 pf->offset_loaded, &os->eth.tx_unicast,
3241 &ns->eth.tx_unicast);
3242 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3243 I40E_GLPRT_MPTCL(hw->port),
3244 pf->offset_loaded, &os->eth.tx_multicast,
3245 &ns->eth.tx_multicast);
3246 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3247 I40E_GLPRT_BPTCL(hw->port),
3248 pf->offset_loaded, &os->eth.tx_broadcast,
3249 &ns->eth.tx_broadcast);
3250 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3251 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3253 /* exclude internal tx bytes
3254 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3255 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3257 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3259 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3260 ns->eth.tx_bytes = 0;
3262 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3264 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3265 ns->eth.tx_unicast = 0;
3267 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3269 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3270 ns->eth.tx_multicast = 0;
3272 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3274 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3275 ns->eth.tx_broadcast = 0;
3277 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3279 /* GLPRT_TEPC not supported */
3281 /* additional port specific stats */
3282 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3283 pf->offset_loaded, &os->tx_dropped_link_down,
3284 &ns->tx_dropped_link_down);
3285 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3286 pf->offset_loaded, &os->crc_errors,
3288 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3289 pf->offset_loaded, &os->illegal_bytes,
3290 &ns->illegal_bytes);
3291 /* GLPRT_ERRBC not supported */
3292 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3293 pf->offset_loaded, &os->mac_local_faults,
3294 &ns->mac_local_faults);
3295 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3296 pf->offset_loaded, &os->mac_remote_faults,
3297 &ns->mac_remote_faults);
3298 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3299 pf->offset_loaded, &os->rx_length_errors,
3300 &ns->rx_length_errors);
3301 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3302 pf->offset_loaded, &os->link_xon_rx,
3304 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3305 pf->offset_loaded, &os->link_xoff_rx,
3307 for (i = 0; i < 8; i++) {
3308 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3310 &os->priority_xon_rx[i],
3311 &ns->priority_xon_rx[i]);
3312 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3314 &os->priority_xoff_rx[i],
3315 &ns->priority_xoff_rx[i]);
3317 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3318 pf->offset_loaded, &os->link_xon_tx,
3320 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3321 pf->offset_loaded, &os->link_xoff_tx,
3323 for (i = 0; i < 8; i++) {
3324 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3326 &os->priority_xon_tx[i],
3327 &ns->priority_xon_tx[i]);
3328 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3330 &os->priority_xoff_tx[i],
3331 &ns->priority_xoff_tx[i]);
3332 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3334 &os->priority_xon_2_xoff[i],
3335 &ns->priority_xon_2_xoff[i]);
3337 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3338 I40E_GLPRT_PRC64L(hw->port),
3339 pf->offset_loaded, &os->rx_size_64,
3341 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3342 I40E_GLPRT_PRC127L(hw->port),
3343 pf->offset_loaded, &os->rx_size_127,
3345 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3346 I40E_GLPRT_PRC255L(hw->port),
3347 pf->offset_loaded, &os->rx_size_255,
3349 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3350 I40E_GLPRT_PRC511L(hw->port),
3351 pf->offset_loaded, &os->rx_size_511,
3353 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3354 I40E_GLPRT_PRC1023L(hw->port),
3355 pf->offset_loaded, &os->rx_size_1023,
3357 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3358 I40E_GLPRT_PRC1522L(hw->port),
3359 pf->offset_loaded, &os->rx_size_1522,
3361 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3362 I40E_GLPRT_PRC9522L(hw->port),
3363 pf->offset_loaded, &os->rx_size_big,
3365 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3366 pf->offset_loaded, &os->rx_undersize,
3368 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3369 pf->offset_loaded, &os->rx_fragments,
3371 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3372 pf->offset_loaded, &os->rx_oversize,
3374 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3375 pf->offset_loaded, &os->rx_jabber,
3377 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3378 I40E_GLPRT_PTC64L(hw->port),
3379 pf->offset_loaded, &os->tx_size_64,
3381 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3382 I40E_GLPRT_PTC127L(hw->port),
3383 pf->offset_loaded, &os->tx_size_127,
3385 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3386 I40E_GLPRT_PTC255L(hw->port),
3387 pf->offset_loaded, &os->tx_size_255,
3389 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3390 I40E_GLPRT_PTC511L(hw->port),
3391 pf->offset_loaded, &os->tx_size_511,
3393 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3394 I40E_GLPRT_PTC1023L(hw->port),
3395 pf->offset_loaded, &os->tx_size_1023,
3397 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3398 I40E_GLPRT_PTC1522L(hw->port),
3399 pf->offset_loaded, &os->tx_size_1522,
3401 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3402 I40E_GLPRT_PTC9522L(hw->port),
3403 pf->offset_loaded, &os->tx_size_big,
3405 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3407 &os->fd_sb_match, &ns->fd_sb_match);
3408 /* GLPRT_MSPDC not supported */
3409 /* GLPRT_XEC not supported */
3411 pf->offset_loaded = true;
3414 i40e_update_vsi_stats(pf->main_vsi);
3417 /* Get all statistics of a port */
3419 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3421 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3422 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3423 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3424 struct i40e_vsi *vsi;
3427 /* call read registers - updates values, now write them to struct */
3428 i40e_read_stats_registers(pf, hw);
3430 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3431 pf->main_vsi->eth_stats.rx_multicast +
3432 pf->main_vsi->eth_stats.rx_broadcast -
3433 pf->main_vsi->eth_stats.rx_discards;
3434 stats->opackets = ns->eth.tx_unicast +
3435 ns->eth.tx_multicast +
3436 ns->eth.tx_broadcast;
3437 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3438 stats->obytes = ns->eth.tx_bytes;
3439 stats->oerrors = ns->eth.tx_errors +
3440 pf->main_vsi->eth_stats.tx_errors;
3443 stats->imissed = ns->eth.rx_discards +
3444 pf->main_vsi->eth_stats.rx_discards;
3445 stats->ierrors = ns->crc_errors +
3446 ns->rx_length_errors + ns->rx_undersize +
3447 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3450 for (i = 0; i < pf->vf_num; i++) {
3451 vsi = pf->vfs[i].vsi;
3452 i40e_update_vsi_stats(vsi);
3454 stats->ipackets += (vsi->eth_stats.rx_unicast +
3455 vsi->eth_stats.rx_multicast +
3456 vsi->eth_stats.rx_broadcast -
3457 vsi->eth_stats.rx_discards);
3458 stats->ibytes += vsi->eth_stats.rx_bytes;
3459 stats->oerrors += vsi->eth_stats.tx_errors;
3460 stats->imissed += vsi->eth_stats.rx_discards;
3464 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3465 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3466 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3467 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3468 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3469 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3470 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3471 ns->eth.rx_unknown_protocol);
3472 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3473 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3474 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3475 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3476 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3477 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3479 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3480 ns->tx_dropped_link_down);
3481 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3482 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3484 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3485 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3486 ns->mac_local_faults);
3487 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3488 ns->mac_remote_faults);
3489 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3490 ns->rx_length_errors);
3491 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3492 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3493 for (i = 0; i < 8; i++) {
3494 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3495 i, ns->priority_xon_rx[i]);
3496 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3497 i, ns->priority_xoff_rx[i]);
3499 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3500 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3501 for (i = 0; i < 8; i++) {
3502 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3503 i, ns->priority_xon_tx[i]);
3504 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3505 i, ns->priority_xoff_tx[i]);
3506 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3507 i, ns->priority_xon_2_xoff[i]);
3509 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3510 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3511 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3512 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3513 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3514 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3515 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3516 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3517 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3518 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3519 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3520 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3521 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3522 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3523 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3524 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3525 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3526 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3527 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3528 ns->mac_short_packet_dropped);
3529 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3530 ns->checksum_error);
3531 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3532 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3536 /* Reset the statistics */
3538 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3540 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3541 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3543 /* Mark PF and VSI stats to update the offset, aka "reset" */
3544 pf->offset_loaded = false;
3546 pf->main_vsi->offset_loaded = false;
3548 /* read the stats, reading current register values into offset */
3549 i40e_read_stats_registers(pf, hw);
3555 i40e_xstats_calc_num(void)
3557 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3558 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3559 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3562 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3563 struct rte_eth_xstat_name *xstats_names,
3564 __rte_unused unsigned limit)
3569 if (xstats_names == NULL)
3570 return i40e_xstats_calc_num();
3572 /* Note: limit checked in rte_eth_xstats_names() */
3574 /* Get stats from i40e_eth_stats struct */
3575 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3576 strlcpy(xstats_names[count].name,
3577 rte_i40e_stats_strings[i].name,
3578 sizeof(xstats_names[count].name));
3582 /* Get individiual stats from i40e_hw_port struct */
3583 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3584 strlcpy(xstats_names[count].name,
3585 rte_i40e_hw_port_strings[i].name,
3586 sizeof(xstats_names[count].name));
3590 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3591 for (prio = 0; prio < 8; prio++) {
3592 snprintf(xstats_names[count].name,
3593 sizeof(xstats_names[count].name),
3594 "rx_priority%u_%s", prio,
3595 rte_i40e_rxq_prio_strings[i].name);
3600 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3601 for (prio = 0; prio < 8; prio++) {
3602 snprintf(xstats_names[count].name,
3603 sizeof(xstats_names[count].name),
3604 "tx_priority%u_%s", prio,
3605 rte_i40e_txq_prio_strings[i].name);
3613 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3616 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3617 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3618 unsigned i, count, prio;
3619 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3621 count = i40e_xstats_calc_num();
3625 i40e_read_stats_registers(pf, hw);
3632 /* Get stats from i40e_eth_stats struct */
3633 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3634 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3635 rte_i40e_stats_strings[i].offset);
3636 xstats[count].id = count;
3640 /* Get individiual stats from i40e_hw_port struct */
3641 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3642 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3643 rte_i40e_hw_port_strings[i].offset);
3644 xstats[count].id = count;
3648 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3649 for (prio = 0; prio < 8; prio++) {
3650 xstats[count].value =
3651 *(uint64_t *)(((char *)hw_stats) +
3652 rte_i40e_rxq_prio_strings[i].offset +
3653 (sizeof(uint64_t) * prio));
3654 xstats[count].id = count;
3659 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3660 for (prio = 0; prio < 8; prio++) {
3661 xstats[count].value =
3662 *(uint64_t *)(((char *)hw_stats) +
3663 rte_i40e_txq_prio_strings[i].offset +
3664 (sizeof(uint64_t) * prio));
3665 xstats[count].id = count;
3674 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3676 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3682 full_ver = hw->nvm.oem_ver;
3683 ver = (u8)(full_ver >> 24);
3684 build = (u16)((full_ver >> 8) & 0xffff);
3685 patch = (u8)(full_ver & 0xff);
3687 ret = snprintf(fw_version, fw_size,
3688 "%d.%d%d 0x%08x %d.%d.%d",
3689 ((hw->nvm.version >> 12) & 0xf),
3690 ((hw->nvm.version >> 4) & 0xff),
3691 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3694 ret += 1; /* add the size of '\0' */
3695 if (fw_size < (u32)ret)
3702 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3703 * the Rx data path does not hang if the FW LLDP is stopped.
3704 * return true if lldp need to stop
3705 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3708 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3711 char ver_str[64] = {0};
3712 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3714 i40e_fw_version_get(dev, ver_str, 64);
3715 nvm_ver = atof(ver_str);
3716 if ((hw->mac.type == I40E_MAC_X722 ||
3717 hw->mac.type == I40E_MAC_X722_VF) &&
3718 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3720 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3727 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3729 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3730 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3731 struct i40e_vsi *vsi = pf->main_vsi;
3732 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3734 dev_info->max_rx_queues = vsi->nb_qps;
3735 dev_info->max_tx_queues = vsi->nb_qps;
3736 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3737 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3738 dev_info->max_mac_addrs = vsi->max_macaddrs;
3739 dev_info->max_vfs = pci_dev->max_vfs;
3740 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3741 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3742 dev_info->rx_queue_offload_capa = 0;
3743 dev_info->rx_offload_capa =
3744 DEV_RX_OFFLOAD_VLAN_STRIP |
3745 DEV_RX_OFFLOAD_QINQ_STRIP |
3746 DEV_RX_OFFLOAD_IPV4_CKSUM |
3747 DEV_RX_OFFLOAD_UDP_CKSUM |
3748 DEV_RX_OFFLOAD_TCP_CKSUM |
3749 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3750 DEV_RX_OFFLOAD_KEEP_CRC |
3751 DEV_RX_OFFLOAD_SCATTER |
3752 DEV_RX_OFFLOAD_VLAN_EXTEND |
3753 DEV_RX_OFFLOAD_VLAN_FILTER |
3754 DEV_RX_OFFLOAD_JUMBO_FRAME |
3755 DEV_RX_OFFLOAD_RSS_HASH;
3757 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3758 dev_info->tx_offload_capa =
3759 DEV_TX_OFFLOAD_VLAN_INSERT |
3760 DEV_TX_OFFLOAD_QINQ_INSERT |
3761 DEV_TX_OFFLOAD_IPV4_CKSUM |
3762 DEV_TX_OFFLOAD_UDP_CKSUM |
3763 DEV_TX_OFFLOAD_TCP_CKSUM |
3764 DEV_TX_OFFLOAD_SCTP_CKSUM |
3765 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3766 DEV_TX_OFFLOAD_TCP_TSO |
3767 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3768 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3769 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3770 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3771 DEV_TX_OFFLOAD_MULTI_SEGS |
3772 dev_info->tx_queue_offload_capa;
3773 dev_info->dev_capa =
3774 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3775 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3777 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3779 dev_info->reta_size = pf->hash_lut_size;
3780 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3782 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3784 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3785 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3786 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3788 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3793 dev_info->default_txconf = (struct rte_eth_txconf) {
3795 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3796 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3797 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3799 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3800 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3804 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3805 .nb_max = I40E_MAX_RING_DESC,
3806 .nb_min = I40E_MIN_RING_DESC,
3807 .nb_align = I40E_ALIGN_RING_DESC,
3810 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3811 .nb_max = I40E_MAX_RING_DESC,
3812 .nb_min = I40E_MIN_RING_DESC,
3813 .nb_align = I40E_ALIGN_RING_DESC,
3814 .nb_seg_max = I40E_TX_MAX_SEG,
3815 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3818 if (pf->flags & I40E_FLAG_VMDQ) {
3819 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3820 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3821 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3822 pf->max_nb_vmdq_vsi;
3823 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3824 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3825 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3828 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3830 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3831 dev_info->default_rxportconf.nb_queues = 2;
3832 dev_info->default_txportconf.nb_queues = 2;
3833 if (dev->data->nb_rx_queues == 1)
3834 dev_info->default_rxportconf.ring_size = 2048;
3836 dev_info->default_rxportconf.ring_size = 1024;
3837 if (dev->data->nb_tx_queues == 1)
3838 dev_info->default_txportconf.ring_size = 1024;
3840 dev_info->default_txportconf.ring_size = 512;
3842 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3844 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3845 dev_info->default_rxportconf.nb_queues = 1;
3846 dev_info->default_txportconf.nb_queues = 1;
3847 dev_info->default_rxportconf.ring_size = 256;
3848 dev_info->default_txportconf.ring_size = 256;
3851 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3852 dev_info->default_rxportconf.nb_queues = 1;
3853 dev_info->default_txportconf.nb_queues = 1;
3854 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3855 dev_info->default_rxportconf.ring_size = 512;
3856 dev_info->default_txportconf.ring_size = 256;
3858 dev_info->default_rxportconf.ring_size = 256;
3859 dev_info->default_txportconf.ring_size = 256;
3862 dev_info->default_rxportconf.burst_size = 32;
3863 dev_info->default_txportconf.burst_size = 32;
3869 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3871 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3872 struct i40e_vsi *vsi = pf->main_vsi;
3873 PMD_INIT_FUNC_TRACE();
3876 return i40e_vsi_add_vlan(vsi, vlan_id);
3878 return i40e_vsi_delete_vlan(vsi, vlan_id);
3882 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3883 enum rte_vlan_type vlan_type,
3884 uint16_t tpid, int qinq)
3886 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3889 uint16_t reg_id = 3;
3893 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3897 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3899 if (ret != I40E_SUCCESS) {
3901 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3906 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3909 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3910 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3911 if (reg_r == reg_w) {
3912 PMD_DRV_LOG(DEBUG, "No need to write");
3916 ret = i40e_aq_debug_write_global_register(hw,
3917 I40E_GL_SWT_L2TAGCTRL(reg_id),
3919 if (ret != I40E_SUCCESS) {
3921 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3926 "Global register 0x%08x is changed with value 0x%08x",
3927 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3933 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3934 enum rte_vlan_type vlan_type,
3937 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3938 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3939 int qinq = dev->data->dev_conf.rxmode.offloads &
3940 DEV_RX_OFFLOAD_VLAN_EXTEND;
3943 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3944 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3945 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3947 "Unsupported vlan type.");
3951 if (pf->support_multi_driver) {
3952 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3956 /* 802.1ad frames ability is added in NVM API 1.7*/
3957 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3959 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3960 hw->first_tag = rte_cpu_to_le_16(tpid);
3961 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3962 hw->second_tag = rte_cpu_to_le_16(tpid);
3964 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3965 hw->second_tag = rte_cpu_to_le_16(tpid);
3967 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3968 if (ret != I40E_SUCCESS) {
3970 "Set switch config failed aq_err: %d",
3971 hw->aq.asq_last_status);
3975 /* If NVM API < 1.7, keep the register setting */
3976 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3983 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3985 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3986 struct i40e_vsi *vsi = pf->main_vsi;
3987 struct rte_eth_rxmode *rxmode;
3989 rxmode = &dev->data->dev_conf.rxmode;
3990 if (mask & ETH_VLAN_FILTER_MASK) {
3991 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3992 i40e_vsi_config_vlan_filter(vsi, TRUE);
3994 i40e_vsi_config_vlan_filter(vsi, FALSE);
3997 if (mask & ETH_VLAN_STRIP_MASK) {
3998 /* Enable or disable VLAN stripping */
3999 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4000 i40e_vsi_config_vlan_stripping(vsi, TRUE);
4002 i40e_vsi_config_vlan_stripping(vsi, FALSE);
4005 if (mask & ETH_VLAN_EXTEND_MASK) {
4006 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4007 i40e_vsi_config_double_vlan(vsi, TRUE);
4008 /* Set global registers with default ethertype. */
4009 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4010 RTE_ETHER_TYPE_VLAN);
4011 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4012 RTE_ETHER_TYPE_VLAN);
4015 i40e_vsi_config_double_vlan(vsi, FALSE);
4022 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4023 __rte_unused uint16_t queue,
4024 __rte_unused int on)
4026 PMD_INIT_FUNC_TRACE();
4030 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4032 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4033 struct i40e_vsi *vsi = pf->main_vsi;
4034 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4035 struct i40e_vsi_vlan_pvid_info info;
4037 memset(&info, 0, sizeof(info));
4040 info.config.pvid = pvid;
4042 info.config.reject.tagged =
4043 data->dev_conf.txmode.hw_vlan_reject_tagged;
4044 info.config.reject.untagged =
4045 data->dev_conf.txmode.hw_vlan_reject_untagged;
4048 return i40e_vsi_vlan_pvid_set(vsi, &info);
4052 i40e_dev_led_on(struct rte_eth_dev *dev)
4054 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4055 uint32_t mode = i40e_led_get(hw);
4058 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4064 i40e_dev_led_off(struct rte_eth_dev *dev)
4066 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4067 uint32_t mode = i40e_led_get(hw);
4070 i40e_led_set(hw, 0, false);
4076 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4078 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4079 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4081 fc_conf->pause_time = pf->fc_conf.pause_time;
4083 /* read out from register, in case they are modified by other port */
4084 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4085 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4086 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4087 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4089 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4090 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4092 /* Return current mode according to actual setting*/
4093 switch (hw->fc.current_mode) {
4095 fc_conf->mode = RTE_FC_FULL;
4097 case I40E_FC_TX_PAUSE:
4098 fc_conf->mode = RTE_FC_TX_PAUSE;
4100 case I40E_FC_RX_PAUSE:
4101 fc_conf->mode = RTE_FC_RX_PAUSE;
4105 fc_conf->mode = RTE_FC_NONE;
4112 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4114 uint32_t mflcn_reg, fctrl_reg, reg;
4115 uint32_t max_high_water;
4116 uint8_t i, aq_failure;
4120 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4121 [RTE_FC_NONE] = I40E_FC_NONE,
4122 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4123 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4124 [RTE_FC_FULL] = I40E_FC_FULL
4127 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4129 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4130 if ((fc_conf->high_water > max_high_water) ||
4131 (fc_conf->high_water < fc_conf->low_water)) {
4133 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4138 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4139 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4140 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4142 pf->fc_conf.pause_time = fc_conf->pause_time;
4143 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4144 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4146 PMD_INIT_FUNC_TRACE();
4148 /* All the link flow control related enable/disable register
4149 * configuration is handle by the F/W
4151 err = i40e_set_fc(hw, &aq_failure, true);
4155 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4156 /* Configure flow control refresh threshold,
4157 * the value for stat_tx_pause_refresh_timer[8]
4158 * is used for global pause operation.
4162 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4163 pf->fc_conf.pause_time);
4165 /* configure the timer value included in transmitted pause
4167 * the value for stat_tx_pause_quanta[8] is used for global
4170 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4171 pf->fc_conf.pause_time);
4173 fctrl_reg = I40E_READ_REG(hw,
4174 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4176 if (fc_conf->mac_ctrl_frame_fwd != 0)
4177 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4179 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4181 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4184 /* Configure pause time (2 TCs per register) */
4185 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4186 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4187 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4189 /* Configure flow control refresh threshold value */
4190 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4191 pf->fc_conf.pause_time / 2);
4193 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4195 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4196 *depending on configuration
4198 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4199 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4200 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4202 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4203 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4206 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4209 if (!pf->support_multi_driver) {
4210 /* config water marker both based on the packets and bytes */
4211 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4212 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4213 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4214 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4215 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4216 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4217 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4218 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4220 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4221 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4225 "Water marker configuration is not supported.");
4228 I40E_WRITE_FLUSH(hw);
4234 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4235 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4237 PMD_INIT_FUNC_TRACE();
4242 /* Add a MAC address, and update filters */
4244 i40e_macaddr_add(struct rte_eth_dev *dev,
4245 struct rte_ether_addr *mac_addr,
4246 __rte_unused uint32_t index,
4249 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4250 struct i40e_mac_filter_info mac_filter;
4251 struct i40e_vsi *vsi;
4252 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4255 /* If VMDQ not enabled or configured, return */
4256 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4257 !pf->nb_cfg_vmdq_vsi)) {
4258 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4259 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4264 if (pool > pf->nb_cfg_vmdq_vsi) {
4265 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4266 pool, pf->nb_cfg_vmdq_vsi);
4270 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4271 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4272 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4274 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4279 vsi = pf->vmdq[pool - 1].vsi;
4281 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4282 if (ret != I40E_SUCCESS) {
4283 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4289 /* Remove a MAC address, and update filters */
4291 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4293 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4294 struct i40e_vsi *vsi;
4295 struct rte_eth_dev_data *data = dev->data;
4296 struct rte_ether_addr *macaddr;
4301 macaddr = &(data->mac_addrs[index]);
4303 pool_sel = dev->data->mac_pool_sel[index];
4305 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4306 if (pool_sel & (1ULL << i)) {
4310 /* No VMDQ pool enabled or configured */
4311 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4312 (i > pf->nb_cfg_vmdq_vsi)) {
4314 "No VMDQ pool enabled/configured");
4317 vsi = pf->vmdq[i - 1].vsi;
4319 ret = i40e_vsi_delete_mac(vsi, macaddr);
4322 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4329 /* Set perfect match or hash match of MAC and VLAN for a VF */
4331 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4332 struct rte_eth_mac_filter *filter,
4336 struct i40e_mac_filter_info mac_filter;
4337 struct rte_ether_addr old_mac;
4338 struct rte_ether_addr *new_mac;
4339 struct i40e_pf_vf *vf = NULL;
4344 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4347 hw = I40E_PF_TO_HW(pf);
4349 if (filter == NULL) {
4350 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4354 new_mac = &filter->mac_addr;
4356 if (rte_is_zero_ether_addr(new_mac)) {
4357 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4361 vf_id = filter->dst_id;
4363 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4364 PMD_DRV_LOG(ERR, "Invalid argument.");
4367 vf = &pf->vfs[vf_id];
4369 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4370 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4375 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4376 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4377 RTE_ETHER_ADDR_LEN);
4378 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4379 RTE_ETHER_ADDR_LEN);
4381 mac_filter.filter_type = filter->filter_type;
4382 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4383 if (ret != I40E_SUCCESS) {
4384 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4387 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4389 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4390 RTE_ETHER_ADDR_LEN);
4391 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4392 if (ret != I40E_SUCCESS) {
4393 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4397 /* Clear device address as it has been removed */
4398 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4399 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4405 /* MAC filter handle */
4407 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4410 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4411 struct rte_eth_mac_filter *filter;
4412 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4413 int ret = I40E_NOT_SUPPORTED;
4415 filter = (struct rte_eth_mac_filter *)(arg);
4417 switch (filter_op) {
4418 case RTE_ETH_FILTER_NOP:
4421 case RTE_ETH_FILTER_ADD:
4422 i40e_pf_disable_irq0(hw);
4424 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4425 i40e_pf_enable_irq0(hw);
4427 case RTE_ETH_FILTER_DELETE:
4428 i40e_pf_disable_irq0(hw);
4430 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4431 i40e_pf_enable_irq0(hw);
4434 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4435 ret = I40E_ERR_PARAM;
4443 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4445 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4446 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4453 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4454 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4455 vsi->type != I40E_VSI_SRIOV,
4458 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4462 uint32_t *lut_dw = (uint32_t *)lut;
4463 uint16_t i, lut_size_dw = lut_size / 4;
4465 if (vsi->type == I40E_VSI_SRIOV) {
4466 for (i = 0; i <= lut_size_dw; i++) {
4467 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4468 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4471 for (i = 0; i < lut_size_dw; i++)
4472 lut_dw[i] = I40E_READ_REG(hw,
4481 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4490 pf = I40E_VSI_TO_PF(vsi);
4491 hw = I40E_VSI_TO_HW(vsi);
4493 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4494 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4495 vsi->type != I40E_VSI_SRIOV,
4498 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4502 uint32_t *lut_dw = (uint32_t *)lut;
4503 uint16_t i, lut_size_dw = lut_size / 4;
4505 if (vsi->type == I40E_VSI_SRIOV) {
4506 for (i = 0; i < lut_size_dw; i++)
4509 I40E_VFQF_HLUT1(i, vsi->user_param),
4512 for (i = 0; i < lut_size_dw; i++)
4513 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4516 I40E_WRITE_FLUSH(hw);
4523 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4524 struct rte_eth_rss_reta_entry64 *reta_conf,
4527 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4528 uint16_t i, lut_size = pf->hash_lut_size;
4529 uint16_t idx, shift;
4533 if (reta_size != lut_size ||
4534 reta_size > ETH_RSS_RETA_SIZE_512) {
4536 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4537 reta_size, lut_size);
4541 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4543 PMD_DRV_LOG(ERR, "No memory can be allocated");
4546 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4549 for (i = 0; i < reta_size; i++) {
4550 idx = i / RTE_RETA_GROUP_SIZE;
4551 shift = i % RTE_RETA_GROUP_SIZE;
4552 if (reta_conf[idx].mask & (1ULL << shift))
4553 lut[i] = reta_conf[idx].reta[shift];
4555 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4557 pf->adapter->rss_reta_updated = 1;
4566 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4567 struct rte_eth_rss_reta_entry64 *reta_conf,
4570 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4571 uint16_t i, lut_size = pf->hash_lut_size;
4572 uint16_t idx, shift;
4576 if (reta_size != lut_size ||
4577 reta_size > ETH_RSS_RETA_SIZE_512) {
4579 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4580 reta_size, lut_size);
4584 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4586 PMD_DRV_LOG(ERR, "No memory can be allocated");
4590 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4593 for (i = 0; i < reta_size; i++) {
4594 idx = i / RTE_RETA_GROUP_SIZE;
4595 shift = i % RTE_RETA_GROUP_SIZE;
4596 if (reta_conf[idx].mask & (1ULL << shift))
4597 reta_conf[idx].reta[shift] = lut[i];
4607 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4608 * @hw: pointer to the HW structure
4609 * @mem: pointer to mem struct to fill out
4610 * @size: size of memory requested
4611 * @alignment: what to align the allocation to
4613 enum i40e_status_code
4614 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4615 struct i40e_dma_mem *mem,
4619 const struct rte_memzone *mz = NULL;
4620 char z_name[RTE_MEMZONE_NAMESIZE];
4623 return I40E_ERR_PARAM;
4625 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4626 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4627 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4629 return I40E_ERR_NO_MEMORY;
4634 mem->zone = (const void *)mz;
4636 "memzone %s allocated with physical address: %"PRIu64,
4639 return I40E_SUCCESS;
4643 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4644 * @hw: pointer to the HW structure
4645 * @mem: ptr to mem struct to free
4647 enum i40e_status_code
4648 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4649 struct i40e_dma_mem *mem)
4652 return I40E_ERR_PARAM;
4655 "memzone %s to be freed with physical address: %"PRIu64,
4656 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4657 rte_memzone_free((const struct rte_memzone *)mem->zone);
4662 return I40E_SUCCESS;
4666 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4667 * @hw: pointer to the HW structure
4668 * @mem: pointer to mem struct to fill out
4669 * @size: size of memory requested
4671 enum i40e_status_code
4672 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4673 struct i40e_virt_mem *mem,
4677 return I40E_ERR_PARAM;
4680 mem->va = rte_zmalloc("i40e", size, 0);
4683 return I40E_SUCCESS;
4685 return I40E_ERR_NO_MEMORY;
4689 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4690 * @hw: pointer to the HW structure
4691 * @mem: pointer to mem struct to free
4693 enum i40e_status_code
4694 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4695 struct i40e_virt_mem *mem)
4698 return I40E_ERR_PARAM;
4703 return I40E_SUCCESS;
4707 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4709 rte_spinlock_init(&sp->spinlock);
4713 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4715 rte_spinlock_lock(&sp->spinlock);
4719 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4721 rte_spinlock_unlock(&sp->spinlock);
4725 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4731 * Get the hardware capabilities, which will be parsed
4732 * and saved into struct i40e_hw.
4735 i40e_get_cap(struct i40e_hw *hw)
4737 struct i40e_aqc_list_capabilities_element_resp *buf;
4738 uint16_t len, size = 0;
4741 /* Calculate a huge enough buff for saving response data temporarily */
4742 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4743 I40E_MAX_CAP_ELE_NUM;
4744 buf = rte_zmalloc("i40e", len, 0);
4746 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4747 return I40E_ERR_NO_MEMORY;
4750 /* Get, parse the capabilities and save it to hw */
4751 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4752 i40e_aqc_opc_list_func_capabilities, NULL);
4753 if (ret != I40E_SUCCESS)
4754 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4756 /* Free the temporary buffer after being used */
4762 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4764 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4772 pf = (struct i40e_pf *)opaque;
4776 num = strtoul(value, &end, 0);
4777 if (errno != 0 || end == value || *end != 0) {
4778 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4779 "kept the value = %hu", value, pf->vf_nb_qp_max);
4783 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4784 pf->vf_nb_qp_max = (uint16_t)num;
4786 /* here return 0 to make next valid same argument work */
4787 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4788 "power of 2 and equal or less than 16 !, Now it is "
4789 "kept the value = %hu", num, pf->vf_nb_qp_max);
4794 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4796 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4797 struct rte_kvargs *kvlist;
4800 /* set default queue number per VF as 4 */
4801 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4803 if (dev->device->devargs == NULL)
4806 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4810 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4811 if (!kvargs_count) {
4812 rte_kvargs_free(kvlist);
4816 if (kvargs_count > 1)
4817 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4818 "the first invalid or last valid one is used !",
4819 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4821 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4822 i40e_pf_parse_vf_queue_number_handler, pf);
4824 rte_kvargs_free(kvlist);
4830 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4832 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4833 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4834 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4835 uint16_t qp_count = 0, vsi_count = 0;
4837 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4838 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4842 i40e_pf_config_vf_rxq_number(dev);
4844 /* Add the parameter init for LFC */
4845 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4846 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4847 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4849 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4850 pf->max_num_vsi = hw->func_caps.num_vsis;
4851 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4852 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4854 /* FDir queue/VSI allocation */
4855 pf->fdir_qp_offset = 0;
4856 if (hw->func_caps.fd) {
4857 pf->flags |= I40E_FLAG_FDIR;
4858 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4860 pf->fdir_nb_qps = 0;
4862 qp_count += pf->fdir_nb_qps;
4865 /* LAN queue/VSI allocation */
4866 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4867 if (!hw->func_caps.rss) {
4870 pf->flags |= I40E_FLAG_RSS;
4871 if (hw->mac.type == I40E_MAC_X722)
4872 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4873 pf->lan_nb_qps = pf->lan_nb_qp_max;
4875 qp_count += pf->lan_nb_qps;
4878 /* VF queue/VSI allocation */
4879 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4880 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4881 pf->flags |= I40E_FLAG_SRIOV;
4882 pf->vf_nb_qps = pf->vf_nb_qp_max;
4883 pf->vf_num = pci_dev->max_vfs;
4885 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4886 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4891 qp_count += pf->vf_nb_qps * pf->vf_num;
4892 vsi_count += pf->vf_num;
4894 /* VMDq queue/VSI allocation */
4895 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4896 pf->vmdq_nb_qps = 0;
4897 pf->max_nb_vmdq_vsi = 0;
4898 if (hw->func_caps.vmdq) {
4899 if (qp_count < hw->func_caps.num_tx_qp &&
4900 vsi_count < hw->func_caps.num_vsis) {
4901 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4902 qp_count) / pf->vmdq_nb_qp_max;
4904 /* Limit the maximum number of VMDq vsi to the maximum
4905 * ethdev can support
4907 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4908 hw->func_caps.num_vsis - vsi_count);
4909 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4911 if (pf->max_nb_vmdq_vsi) {
4912 pf->flags |= I40E_FLAG_VMDQ;
4913 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4915 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4916 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4917 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4920 "No enough queues left for VMDq");
4923 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4926 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4927 vsi_count += pf->max_nb_vmdq_vsi;
4929 if (hw->func_caps.dcb)
4930 pf->flags |= I40E_FLAG_DCB;
4932 if (qp_count > hw->func_caps.num_tx_qp) {
4934 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4935 qp_count, hw->func_caps.num_tx_qp);
4938 if (vsi_count > hw->func_caps.num_vsis) {
4940 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4941 vsi_count, hw->func_caps.num_vsis);
4949 i40e_pf_get_switch_config(struct i40e_pf *pf)
4951 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4952 struct i40e_aqc_get_switch_config_resp *switch_config;
4953 struct i40e_aqc_switch_config_element_resp *element;
4954 uint16_t start_seid = 0, num_reported;
4957 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4958 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4959 if (!switch_config) {
4960 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4964 /* Get the switch configurations */
4965 ret = i40e_aq_get_switch_config(hw, switch_config,
4966 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4967 if (ret != I40E_SUCCESS) {
4968 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4971 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4972 if (num_reported != 1) { /* The number should be 1 */
4973 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4977 /* Parse the switch configuration elements */
4978 element = &(switch_config->element[0]);
4979 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4980 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4981 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4983 PMD_DRV_LOG(INFO, "Unknown element type");
4986 rte_free(switch_config);
4992 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4995 struct pool_entry *entry;
4997 if (pool == NULL || num == 0)
5000 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
5001 if (entry == NULL) {
5002 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
5006 /* queue heap initialize */
5007 pool->num_free = num;
5008 pool->num_alloc = 0;
5010 LIST_INIT(&pool->alloc_list);
5011 LIST_INIT(&pool->free_list);
5013 /* Initialize element */
5017 LIST_INSERT_HEAD(&pool->free_list, entry, next);
5022 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
5024 struct pool_entry *entry, *next_entry;
5029 for (entry = LIST_FIRST(&pool->alloc_list);
5030 entry && (next_entry = LIST_NEXT(entry, next), 1);
5031 entry = next_entry) {
5032 LIST_REMOVE(entry, next);
5036 for (entry = LIST_FIRST(&pool->free_list);
5037 entry && (next_entry = LIST_NEXT(entry, next), 1);
5038 entry = next_entry) {
5039 LIST_REMOVE(entry, next);
5044 pool->num_alloc = 0;
5046 LIST_INIT(&pool->alloc_list);
5047 LIST_INIT(&pool->free_list);
5051 i40e_res_pool_free(struct i40e_res_pool_info *pool,
5054 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
5055 uint32_t pool_offset;
5060 PMD_DRV_LOG(ERR, "Invalid parameter");
5064 pool_offset = base - pool->base;
5065 /* Lookup in alloc list */
5066 LIST_FOREACH(entry, &pool->alloc_list, next) {
5067 if (entry->base == pool_offset) {
5068 valid_entry = entry;
5069 LIST_REMOVE(entry, next);
5074 /* Not find, return */
5075 if (valid_entry == NULL) {
5076 PMD_DRV_LOG(ERR, "Failed to find entry");
5081 * Found it, move it to free list and try to merge.
5082 * In order to make merge easier, always sort it by qbase.
5083 * Find adjacent prev and last entries.
5086 LIST_FOREACH(entry, &pool->free_list, next) {
5087 if (entry->base > valid_entry->base) {
5095 len = valid_entry->len;
5096 /* Try to merge with next one*/
5098 /* Merge with next one */
5099 if (valid_entry->base + len == next->base) {
5100 next->base = valid_entry->base;
5102 rte_free(valid_entry);
5109 /* Merge with previous one */
5110 if (prev->base + prev->len == valid_entry->base) {
5112 /* If it merge with next one, remove next node */
5114 LIST_REMOVE(valid_entry, next);
5115 rte_free(valid_entry);
5118 rte_free(valid_entry);
5125 /* Not find any entry to merge, insert */
5128 LIST_INSERT_AFTER(prev, valid_entry, next);
5129 else if (next != NULL)
5130 LIST_INSERT_BEFORE(next, valid_entry, next);
5131 else /* It's empty list, insert to head */
5132 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5135 pool->num_free += len;
5136 pool->num_alloc -= len;
5142 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5145 struct pool_entry *entry, *valid_entry;
5147 if (pool == NULL || num == 0) {
5148 PMD_DRV_LOG(ERR, "Invalid parameter");
5152 if (pool->num_free < num) {
5153 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5154 num, pool->num_free);
5159 /* Lookup in free list and find most fit one */
5160 LIST_FOREACH(entry, &pool->free_list, next) {
5161 if (entry->len >= num) {
5163 if (entry->len == num) {
5164 valid_entry = entry;
5167 if (valid_entry == NULL || valid_entry->len > entry->len)
5168 valid_entry = entry;
5172 /* Not find one to satisfy the request, return */
5173 if (valid_entry == NULL) {
5174 PMD_DRV_LOG(ERR, "No valid entry found");
5178 * The entry have equal queue number as requested,
5179 * remove it from alloc_list.
5181 if (valid_entry->len == num) {
5182 LIST_REMOVE(valid_entry, next);
5185 * The entry have more numbers than requested,
5186 * create a new entry for alloc_list and minus its
5187 * queue base and number in free_list.
5189 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5190 if (entry == NULL) {
5192 "Failed to allocate memory for resource pool");
5195 entry->base = valid_entry->base;
5197 valid_entry->base += num;
5198 valid_entry->len -= num;
5199 valid_entry = entry;
5202 /* Insert it into alloc list, not sorted */
5203 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5205 pool->num_free -= valid_entry->len;
5206 pool->num_alloc += valid_entry->len;
5208 return valid_entry->base + pool->base;
5212 * bitmap_is_subset - Check whether src2 is subset of src1
5215 bitmap_is_subset(uint8_t src1, uint8_t src2)
5217 return !((src1 ^ src2) & src2);
5220 static enum i40e_status_code
5221 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5223 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5225 /* If DCB is not supported, only default TC is supported */
5226 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5227 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5228 return I40E_NOT_SUPPORTED;
5231 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5233 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5234 hw->func_caps.enabled_tcmap, enabled_tcmap);
5235 return I40E_NOT_SUPPORTED;
5237 return I40E_SUCCESS;
5241 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5242 struct i40e_vsi_vlan_pvid_info *info)
5245 struct i40e_vsi_context ctxt;
5246 uint8_t vlan_flags = 0;
5249 if (vsi == NULL || info == NULL) {
5250 PMD_DRV_LOG(ERR, "invalid parameters");
5251 return I40E_ERR_PARAM;
5255 vsi->info.pvid = info->config.pvid;
5257 * If insert pvid is enabled, only tagged pkts are
5258 * allowed to be sent out.
5260 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5261 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5264 if (info->config.reject.tagged == 0)
5265 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5267 if (info->config.reject.untagged == 0)
5268 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5270 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5271 I40E_AQ_VSI_PVLAN_MODE_MASK);
5272 vsi->info.port_vlan_flags |= vlan_flags;
5273 vsi->info.valid_sections =
5274 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5275 memset(&ctxt, 0, sizeof(ctxt));
5276 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5277 ctxt.seid = vsi->seid;
5279 hw = I40E_VSI_TO_HW(vsi);
5280 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5281 if (ret != I40E_SUCCESS)
5282 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5288 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5290 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5292 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5294 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5295 if (ret != I40E_SUCCESS)
5299 PMD_DRV_LOG(ERR, "seid not valid");
5303 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5304 tc_bw_data.tc_valid_bits = enabled_tcmap;
5305 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5306 tc_bw_data.tc_bw_credits[i] =
5307 (enabled_tcmap & (1 << i)) ? 1 : 0;
5309 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5310 if (ret != I40E_SUCCESS) {
5311 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5315 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5316 sizeof(vsi->info.qs_handle));
5317 return I40E_SUCCESS;
5320 static enum i40e_status_code
5321 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5322 struct i40e_aqc_vsi_properties_data *info,
5323 uint8_t enabled_tcmap)
5325 enum i40e_status_code ret;
5326 int i, total_tc = 0;
5327 uint16_t qpnum_per_tc, bsf, qp_idx;
5329 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5330 if (ret != I40E_SUCCESS)
5333 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5334 if (enabled_tcmap & (1 << i))
5338 vsi->enabled_tc = enabled_tcmap;
5340 /* Number of queues per enabled TC */
5341 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5342 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5343 bsf = rte_bsf32(qpnum_per_tc);
5345 /* Adjust the queue number to actual queues that can be applied */
5346 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5347 vsi->nb_qps = qpnum_per_tc * total_tc;
5350 * Configure TC and queue mapping parameters, for enabled TC,
5351 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5352 * default queue will serve it.
5355 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5356 if (vsi->enabled_tc & (1 << i)) {
5357 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5358 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5359 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5360 qp_idx += qpnum_per_tc;
5362 info->tc_mapping[i] = 0;
5365 /* Associate queue number with VSI */
5366 if (vsi->type == I40E_VSI_SRIOV) {
5367 info->mapping_flags |=
5368 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5369 for (i = 0; i < vsi->nb_qps; i++)
5370 info->queue_mapping[i] =
5371 rte_cpu_to_le_16(vsi->base_queue + i);
5373 info->mapping_flags |=
5374 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5375 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5377 info->valid_sections |=
5378 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5380 return I40E_SUCCESS;
5384 i40e_veb_release(struct i40e_veb *veb)
5386 struct i40e_vsi *vsi;
5392 if (!TAILQ_EMPTY(&veb->head)) {
5393 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5396 /* associate_vsi field is NULL for floating VEB */
5397 if (veb->associate_vsi != NULL) {
5398 vsi = veb->associate_vsi;
5399 hw = I40E_VSI_TO_HW(vsi);
5401 vsi->uplink_seid = veb->uplink_seid;
5404 veb->associate_pf->main_vsi->floating_veb = NULL;
5405 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5408 i40e_aq_delete_element(hw, veb->seid, NULL);
5410 return I40E_SUCCESS;
5414 static struct i40e_veb *
5415 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5417 struct i40e_veb *veb;
5423 "veb setup failed, associated PF shouldn't null");
5426 hw = I40E_PF_TO_HW(pf);
5428 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5430 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5434 veb->associate_vsi = vsi;
5435 veb->associate_pf = pf;
5436 TAILQ_INIT(&veb->head);
5437 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5439 /* create floating veb if vsi is NULL */
5441 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5442 I40E_DEFAULT_TCMAP, false,
5443 &veb->seid, false, NULL);
5445 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5446 true, &veb->seid, false, NULL);
5449 if (ret != I40E_SUCCESS) {
5450 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5451 hw->aq.asq_last_status);
5454 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5456 /* get statistics index */
5457 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5458 &veb->stats_idx, NULL, NULL, NULL);
5459 if (ret != I40E_SUCCESS) {
5460 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5461 hw->aq.asq_last_status);
5464 /* Get VEB bandwidth, to be implemented */
5465 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5467 vsi->uplink_seid = veb->seid;
5476 i40e_vsi_release(struct i40e_vsi *vsi)
5480 struct i40e_vsi_list *vsi_list;
5483 struct i40e_mac_filter *f;
5484 uint16_t user_param;
5487 return I40E_SUCCESS;
5492 user_param = vsi->user_param;
5494 pf = I40E_VSI_TO_PF(vsi);
5495 hw = I40E_VSI_TO_HW(vsi);
5497 /* VSI has child to attach, release child first */
5499 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5500 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5503 i40e_veb_release(vsi->veb);
5506 if (vsi->floating_veb) {
5507 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5508 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5513 /* Remove all macvlan filters of the VSI */
5514 i40e_vsi_remove_all_macvlan_filter(vsi);
5515 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5518 if (vsi->type != I40E_VSI_MAIN &&
5519 ((vsi->type != I40E_VSI_SRIOV) ||
5520 !pf->floating_veb_list[user_param])) {
5521 /* Remove vsi from parent's sibling list */
5522 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5523 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5524 return I40E_ERR_PARAM;
5526 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5527 &vsi->sib_vsi_list, list);
5529 /* Remove all switch element of the VSI */
5530 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5531 if (ret != I40E_SUCCESS)
5532 PMD_DRV_LOG(ERR, "Failed to delete element");
5535 if ((vsi->type == I40E_VSI_SRIOV) &&
5536 pf->floating_veb_list[user_param]) {
5537 /* Remove vsi from parent's sibling list */
5538 if (vsi->parent_vsi == NULL ||
5539 vsi->parent_vsi->floating_veb == NULL) {
5540 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5541 return I40E_ERR_PARAM;
5543 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5544 &vsi->sib_vsi_list, list);
5546 /* Remove all switch element of the VSI */
5547 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5548 if (ret != I40E_SUCCESS)
5549 PMD_DRV_LOG(ERR, "Failed to delete element");
5552 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5554 if (vsi->type != I40E_VSI_SRIOV)
5555 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5558 return I40E_SUCCESS;
5562 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5564 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5565 struct i40e_aqc_remove_macvlan_element_data def_filter;
5566 struct i40e_mac_filter_info filter;
5569 if (vsi->type != I40E_VSI_MAIN)
5570 return I40E_ERR_CONFIG;
5571 memset(&def_filter, 0, sizeof(def_filter));
5572 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5574 def_filter.vlan_tag = 0;
5575 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5576 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5577 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5578 if (ret != I40E_SUCCESS) {
5579 struct i40e_mac_filter *f;
5580 struct rte_ether_addr *mac;
5583 "Cannot remove the default macvlan filter");
5584 /* It needs to add the permanent mac into mac list */
5585 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5587 PMD_DRV_LOG(ERR, "failed to allocate memory");
5588 return I40E_ERR_NO_MEMORY;
5590 mac = &f->mac_info.mac_addr;
5591 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5593 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5594 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5599 rte_memcpy(&filter.mac_addr,
5600 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5601 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5602 return i40e_vsi_add_mac(vsi, &filter);
5606 * i40e_vsi_get_bw_config - Query VSI BW Information
5607 * @vsi: the VSI to be queried
5609 * Returns 0 on success, negative value on failure
5611 static enum i40e_status_code
5612 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5614 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5615 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5616 struct i40e_hw *hw = &vsi->adapter->hw;
5621 memset(&bw_config, 0, sizeof(bw_config));
5622 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5623 if (ret != I40E_SUCCESS) {
5624 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5625 hw->aq.asq_last_status);
5629 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5630 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5631 &ets_sla_config, NULL);
5632 if (ret != I40E_SUCCESS) {
5634 "VSI failed to get TC bandwdith configuration %u",
5635 hw->aq.asq_last_status);
5639 /* store and print out BW info */
5640 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5641 vsi->bw_info.bw_max = bw_config.max_bw;
5642 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5643 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5644 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5645 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5647 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5648 vsi->bw_info.bw_ets_share_credits[i] =
5649 ets_sla_config.share_credits[i];
5650 vsi->bw_info.bw_ets_credits[i] =
5651 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5652 /* 4 bits per TC, 4th bit is reserved */
5653 vsi->bw_info.bw_ets_max[i] =
5654 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5655 RTE_LEN2MASK(3, uint8_t));
5656 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5657 vsi->bw_info.bw_ets_share_credits[i]);
5658 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5659 vsi->bw_info.bw_ets_credits[i]);
5660 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5661 vsi->bw_info.bw_ets_max[i]);
5664 return I40E_SUCCESS;
5667 /* i40e_enable_pf_lb
5668 * @pf: pointer to the pf structure
5670 * allow loopback on pf
5673 i40e_enable_pf_lb(struct i40e_pf *pf)
5675 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5676 struct i40e_vsi_context ctxt;
5679 /* Use the FW API if FW >= v5.0 */
5680 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5681 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5685 memset(&ctxt, 0, sizeof(ctxt));
5686 ctxt.seid = pf->main_vsi_seid;
5687 ctxt.pf_num = hw->pf_id;
5688 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5690 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5691 ret, hw->aq.asq_last_status);
5694 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5695 ctxt.info.valid_sections =
5696 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5697 ctxt.info.switch_id |=
5698 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5700 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5702 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5703 hw->aq.asq_last_status);
5708 i40e_vsi_setup(struct i40e_pf *pf,
5709 enum i40e_vsi_type type,
5710 struct i40e_vsi *uplink_vsi,
5711 uint16_t user_param)
5713 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5714 struct i40e_vsi *vsi;
5715 struct i40e_mac_filter_info filter;
5717 struct i40e_vsi_context ctxt;
5718 struct rte_ether_addr broadcast =
5719 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5721 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5722 uplink_vsi == NULL) {
5724 "VSI setup failed, VSI link shouldn't be NULL");
5728 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5730 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5735 * 1.type is not MAIN and uplink vsi is not NULL
5736 * If uplink vsi didn't setup VEB, create one first under veb field
5737 * 2.type is SRIOV and the uplink is NULL
5738 * If floating VEB is NULL, create one veb under floating veb field
5741 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5742 uplink_vsi->veb == NULL) {
5743 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5745 if (uplink_vsi->veb == NULL) {
5746 PMD_DRV_LOG(ERR, "VEB setup failed");
5749 /* set ALLOWLOOPBACk on pf, when veb is created */
5750 i40e_enable_pf_lb(pf);
5753 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5754 pf->main_vsi->floating_veb == NULL) {
5755 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5757 if (pf->main_vsi->floating_veb == NULL) {
5758 PMD_DRV_LOG(ERR, "VEB setup failed");
5763 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5765 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5768 TAILQ_INIT(&vsi->mac_list);
5770 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5771 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5772 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5773 vsi->user_param = user_param;
5774 vsi->vlan_anti_spoof_on = 0;
5775 vsi->vlan_filter_on = 0;
5776 /* Allocate queues */
5777 switch (vsi->type) {
5778 case I40E_VSI_MAIN :
5779 vsi->nb_qps = pf->lan_nb_qps;
5781 case I40E_VSI_SRIOV :
5782 vsi->nb_qps = pf->vf_nb_qps;
5784 case I40E_VSI_VMDQ2:
5785 vsi->nb_qps = pf->vmdq_nb_qps;
5788 vsi->nb_qps = pf->fdir_nb_qps;
5794 * The filter status descriptor is reported in rx queue 0,
5795 * while the tx queue for fdir filter programming has no
5796 * such constraints, can be non-zero queues.
5797 * To simplify it, choose FDIR vsi use queue 0 pair.
5798 * To make sure it will use queue 0 pair, queue allocation
5799 * need be done before this function is called
5801 if (type != I40E_VSI_FDIR) {
5802 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5804 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5808 vsi->base_queue = ret;
5810 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5812 /* VF has MSIX interrupt in VF range, don't allocate here */
5813 if (type == I40E_VSI_MAIN) {
5814 if (pf->support_multi_driver) {
5815 /* If support multi-driver, need to use INT0 instead of
5816 * allocating from msix pool. The Msix pool is init from
5817 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5818 * to 1 without calling i40e_res_pool_alloc.
5823 ret = i40e_res_pool_alloc(&pf->msix_pool,
5824 RTE_MIN(vsi->nb_qps,
5825 RTE_MAX_RXTX_INTR_VEC_ID));
5828 "VSI MAIN %d get heap failed %d",
5830 goto fail_queue_alloc;
5832 vsi->msix_intr = ret;
5833 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5834 RTE_MAX_RXTX_INTR_VEC_ID);
5836 } else if (type != I40E_VSI_SRIOV) {
5837 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5839 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5840 goto fail_queue_alloc;
5842 vsi->msix_intr = ret;
5850 if (type == I40E_VSI_MAIN) {
5851 /* For main VSI, no need to add since it's default one */
5852 vsi->uplink_seid = pf->mac_seid;
5853 vsi->seid = pf->main_vsi_seid;
5854 /* Bind queues with specific MSIX interrupt */
5856 * Needs 2 interrupt at least, one for misc cause which will
5857 * enabled from OS side, Another for queues binding the
5858 * interrupt from device side only.
5861 /* Get default VSI parameters from hardware */
5862 memset(&ctxt, 0, sizeof(ctxt));
5863 ctxt.seid = vsi->seid;
5864 ctxt.pf_num = hw->pf_id;
5865 ctxt.uplink_seid = vsi->uplink_seid;
5867 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5868 if (ret != I40E_SUCCESS) {
5869 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5870 goto fail_msix_alloc;
5872 rte_memcpy(&vsi->info, &ctxt.info,
5873 sizeof(struct i40e_aqc_vsi_properties_data));
5874 vsi->vsi_id = ctxt.vsi_number;
5875 vsi->info.valid_sections = 0;
5877 /* Configure tc, enabled TC0 only */
5878 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5880 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5881 goto fail_msix_alloc;
5884 /* TC, queue mapping */
5885 memset(&ctxt, 0, sizeof(ctxt));
5886 vsi->info.valid_sections |=
5887 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5888 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5889 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5890 rte_memcpy(&ctxt.info, &vsi->info,
5891 sizeof(struct i40e_aqc_vsi_properties_data));
5892 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5893 I40E_DEFAULT_TCMAP);
5894 if (ret != I40E_SUCCESS) {
5896 "Failed to configure TC queue mapping");
5897 goto fail_msix_alloc;
5899 ctxt.seid = vsi->seid;
5900 ctxt.pf_num = hw->pf_id;
5901 ctxt.uplink_seid = vsi->uplink_seid;
5904 /* Update VSI parameters */
5905 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5906 if (ret != I40E_SUCCESS) {
5907 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5908 goto fail_msix_alloc;
5911 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5912 sizeof(vsi->info.tc_mapping));
5913 rte_memcpy(&vsi->info.queue_mapping,
5914 &ctxt.info.queue_mapping,
5915 sizeof(vsi->info.queue_mapping));
5916 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5917 vsi->info.valid_sections = 0;
5919 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5923 * Updating default filter settings are necessary to prevent
5924 * reception of tagged packets.
5925 * Some old firmware configurations load a default macvlan
5926 * filter which accepts both tagged and untagged packets.
5927 * The updating is to use a normal filter instead if needed.
5928 * For NVM 4.2.2 or after, the updating is not needed anymore.
5929 * The firmware with correct configurations load the default
5930 * macvlan filter which is expected and cannot be removed.
5932 i40e_update_default_filter_setting(vsi);
5933 i40e_config_qinq(hw, vsi);
5934 } else if (type == I40E_VSI_SRIOV) {
5935 memset(&ctxt, 0, sizeof(ctxt));
5937 * For other VSI, the uplink_seid equals to uplink VSI's
5938 * uplink_seid since they share same VEB
5940 if (uplink_vsi == NULL)
5941 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5943 vsi->uplink_seid = uplink_vsi->uplink_seid;
5944 ctxt.pf_num = hw->pf_id;
5945 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5946 ctxt.uplink_seid = vsi->uplink_seid;
5947 ctxt.connection_type = 0x1;
5948 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5950 /* Use the VEB configuration if FW >= v5.0 */
5951 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5952 /* Configure switch ID */
5953 ctxt.info.valid_sections |=
5954 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5955 ctxt.info.switch_id =
5956 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5959 /* Configure port/vlan */
5960 ctxt.info.valid_sections |=
5961 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5962 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5963 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5964 hw->func_caps.enabled_tcmap);
5965 if (ret != I40E_SUCCESS) {
5967 "Failed to configure TC queue mapping");
5968 goto fail_msix_alloc;
5971 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5972 ctxt.info.valid_sections |=
5973 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5975 * Since VSI is not created yet, only configure parameter,
5976 * will add vsi below.
5979 i40e_config_qinq(hw, vsi);
5980 } else if (type == I40E_VSI_VMDQ2) {
5981 memset(&ctxt, 0, sizeof(ctxt));
5983 * For other VSI, the uplink_seid equals to uplink VSI's
5984 * uplink_seid since they share same VEB
5986 vsi->uplink_seid = uplink_vsi->uplink_seid;
5987 ctxt.pf_num = hw->pf_id;
5989 ctxt.uplink_seid = vsi->uplink_seid;
5990 ctxt.connection_type = 0x1;
5991 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5993 ctxt.info.valid_sections |=
5994 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5995 /* user_param carries flag to enable loop back */
5997 ctxt.info.switch_id =
5998 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5999 ctxt.info.switch_id |=
6000 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6003 /* Configure port/vlan */
6004 ctxt.info.valid_sections |=
6005 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6006 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6007 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6008 I40E_DEFAULT_TCMAP);
6009 if (ret != I40E_SUCCESS) {
6011 "Failed to configure TC queue mapping");
6012 goto fail_msix_alloc;
6014 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6015 ctxt.info.valid_sections |=
6016 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6017 } else if (type == I40E_VSI_FDIR) {
6018 memset(&ctxt, 0, sizeof(ctxt));
6019 vsi->uplink_seid = uplink_vsi->uplink_seid;
6020 ctxt.pf_num = hw->pf_id;
6022 ctxt.uplink_seid = vsi->uplink_seid;
6023 ctxt.connection_type = 0x1; /* regular data port */
6024 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6025 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6026 I40E_DEFAULT_TCMAP);
6027 if (ret != I40E_SUCCESS) {
6029 "Failed to configure TC queue mapping.");
6030 goto fail_msix_alloc;
6032 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6033 ctxt.info.valid_sections |=
6034 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6036 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
6037 goto fail_msix_alloc;
6040 if (vsi->type != I40E_VSI_MAIN) {
6041 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6042 if (ret != I40E_SUCCESS) {
6043 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
6044 hw->aq.asq_last_status);
6045 goto fail_msix_alloc;
6047 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6048 vsi->info.valid_sections = 0;
6049 vsi->seid = ctxt.seid;
6050 vsi->vsi_id = ctxt.vsi_number;
6051 vsi->sib_vsi_list.vsi = vsi;
6052 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
6053 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
6054 &vsi->sib_vsi_list, list);
6056 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
6057 &vsi->sib_vsi_list, list);
6061 /* MAC/VLAN configuration */
6062 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6063 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
6065 ret = i40e_vsi_add_mac(vsi, &filter);
6066 if (ret != I40E_SUCCESS) {
6067 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6068 goto fail_msix_alloc;
6071 /* Get VSI BW information */
6072 i40e_vsi_get_bw_config(vsi);
6075 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6077 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6083 /* Configure vlan filter on or off */
6085 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6088 struct i40e_mac_filter *f;
6090 struct i40e_mac_filter_info *mac_filter;
6091 enum rte_mac_filter_type desired_filter;
6092 int ret = I40E_SUCCESS;
6095 /* Filter to match MAC and VLAN */
6096 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
6098 /* Filter to match only MAC */
6099 desired_filter = RTE_MAC_PERFECT_MATCH;
6104 mac_filter = rte_zmalloc("mac_filter_info_data",
6105 num * sizeof(*mac_filter), 0);
6106 if (mac_filter == NULL) {
6107 PMD_DRV_LOG(ERR, "failed to allocate memory");
6108 return I40E_ERR_NO_MEMORY;
6113 /* Remove all existing mac */
6114 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6115 mac_filter[i] = f->mac_info;
6116 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6118 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6119 on ? "enable" : "disable");
6125 /* Override with new filter */
6126 for (i = 0; i < num; i++) {
6127 mac_filter[i].filter_type = desired_filter;
6128 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6130 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6131 on ? "enable" : "disable");
6137 rte_free(mac_filter);
6141 /* Configure vlan stripping on or off */
6143 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6145 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6146 struct i40e_vsi_context ctxt;
6148 int ret = I40E_SUCCESS;
6150 /* Check if it has been already on or off */
6151 if (vsi->info.valid_sections &
6152 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6154 if ((vsi->info.port_vlan_flags &
6155 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6156 return 0; /* already on */
6158 if ((vsi->info.port_vlan_flags &
6159 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6160 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6161 return 0; /* already off */
6166 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6168 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6169 vsi->info.valid_sections =
6170 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6171 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6172 vsi->info.port_vlan_flags |= vlan_flags;
6173 ctxt.seid = vsi->seid;
6174 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6175 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6177 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6178 on ? "enable" : "disable");
6184 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6186 struct rte_eth_dev_data *data = dev->data;
6190 /* Apply vlan offload setting */
6191 mask = ETH_VLAN_STRIP_MASK |
6192 ETH_VLAN_FILTER_MASK |
6193 ETH_VLAN_EXTEND_MASK;
6194 ret = i40e_vlan_offload_set(dev, mask);
6196 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6200 /* Apply pvid setting */
6201 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6202 data->dev_conf.txmode.hw_vlan_insert_pvid);
6204 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6210 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6212 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6214 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6218 i40e_update_flow_control(struct i40e_hw *hw)
6220 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6221 struct i40e_link_status link_status;
6222 uint32_t rxfc = 0, txfc = 0, reg;
6226 memset(&link_status, 0, sizeof(link_status));
6227 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6228 if (ret != I40E_SUCCESS) {
6229 PMD_DRV_LOG(ERR, "Failed to get link status information");
6230 goto write_reg; /* Disable flow control */
6233 an_info = hw->phy.link_info.an_info;
6234 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6235 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6236 ret = I40E_ERR_NOT_READY;
6237 goto write_reg; /* Disable flow control */
6240 * If link auto negotiation is enabled, flow control needs to
6241 * be configured according to it
6243 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6244 case I40E_LINK_PAUSE_RXTX:
6247 hw->fc.current_mode = I40E_FC_FULL;
6249 case I40E_AQ_LINK_PAUSE_RX:
6251 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6253 case I40E_AQ_LINK_PAUSE_TX:
6255 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6258 hw->fc.current_mode = I40E_FC_NONE;
6263 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6264 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6265 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6266 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6267 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6268 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6275 i40e_pf_setup(struct i40e_pf *pf)
6277 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6278 struct i40e_filter_control_settings settings;
6279 struct i40e_vsi *vsi;
6282 /* Clear all stats counters */
6283 pf->offset_loaded = FALSE;
6284 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6285 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6286 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6287 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6289 ret = i40e_pf_get_switch_config(pf);
6290 if (ret != I40E_SUCCESS) {
6291 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6295 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6297 PMD_INIT_LOG(WARNING,
6298 "failed to allocate switch domain for device %d", ret);
6300 if (pf->flags & I40E_FLAG_FDIR) {
6301 /* make queue allocated first, let FDIR use queue pair 0*/
6302 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6303 if (ret != I40E_FDIR_QUEUE_ID) {
6305 "queue allocation fails for FDIR: ret =%d",
6307 pf->flags &= ~I40E_FLAG_FDIR;
6310 /* main VSI setup */
6311 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6313 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6314 return I40E_ERR_NOT_READY;
6318 /* Configure filter control */
6319 memset(&settings, 0, sizeof(settings));
6320 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6321 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6322 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6323 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6325 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6326 hw->func_caps.rss_table_size);
6327 return I40E_ERR_PARAM;
6329 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6330 hw->func_caps.rss_table_size);
6331 pf->hash_lut_size = hw->func_caps.rss_table_size;
6333 /* Enable ethtype and macvlan filters */
6334 settings.enable_ethtype = TRUE;
6335 settings.enable_macvlan = TRUE;
6336 ret = i40e_set_filter_control(hw, &settings);
6338 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6341 /* Update flow control according to the auto negotiation */
6342 i40e_update_flow_control(hw);
6344 return I40E_SUCCESS;
6348 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6354 * Set or clear TX Queue Disable flags,
6355 * which is required by hardware.
6357 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6358 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6360 /* Wait until the request is finished */
6361 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6362 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6363 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6364 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6365 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6371 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6372 return I40E_SUCCESS; /* already on, skip next steps */
6374 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6375 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6377 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6378 return I40E_SUCCESS; /* already off, skip next steps */
6379 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6381 /* Write the register */
6382 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6383 /* Check the result */
6384 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6385 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6386 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6388 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6389 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6392 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6393 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6397 /* Check if it is timeout */
6398 if (j >= I40E_CHK_Q_ENA_COUNT) {
6399 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6400 (on ? "enable" : "disable"), q_idx);
6401 return I40E_ERR_TIMEOUT;
6404 return I40E_SUCCESS;
6408 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6413 /* Wait until the request is finished */
6414 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6415 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6416 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6417 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6418 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6423 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6424 return I40E_SUCCESS; /* Already on, skip next steps */
6425 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6427 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6428 return I40E_SUCCESS; /* Already off, skip next steps */
6429 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6432 /* Write the register */
6433 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6434 /* Check the result */
6435 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6436 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6437 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6439 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6440 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6443 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6444 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6449 /* Check if it is timeout */
6450 if (j >= I40E_CHK_Q_ENA_COUNT) {
6451 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6452 (on ? "enable" : "disable"), q_idx);
6453 return I40E_ERR_TIMEOUT;
6456 return I40E_SUCCESS;
6459 /* Initialize VSI for TX */
6461 i40e_dev_tx_init(struct i40e_pf *pf)
6463 struct rte_eth_dev_data *data = pf->dev_data;
6465 uint32_t ret = I40E_SUCCESS;
6466 struct i40e_tx_queue *txq;
6468 for (i = 0; i < data->nb_tx_queues; i++) {
6469 txq = data->tx_queues[i];
6470 if (!txq || !txq->q_set)
6472 ret = i40e_tx_queue_init(txq);
6473 if (ret != I40E_SUCCESS)
6476 if (ret == I40E_SUCCESS)
6477 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6483 /* Initialize VSI for RX */
6485 i40e_dev_rx_init(struct i40e_pf *pf)
6487 struct rte_eth_dev_data *data = pf->dev_data;
6488 int ret = I40E_SUCCESS;
6490 struct i40e_rx_queue *rxq;
6492 i40e_pf_config_mq_rx(pf);
6493 for (i = 0; i < data->nb_rx_queues; i++) {
6494 rxq = data->rx_queues[i];
6495 if (!rxq || !rxq->q_set)
6498 ret = i40e_rx_queue_init(rxq);
6499 if (ret != I40E_SUCCESS) {
6501 "Failed to do RX queue initialization");
6505 if (ret == I40E_SUCCESS)
6506 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6513 i40e_dev_rxtx_init(struct i40e_pf *pf)
6517 err = i40e_dev_tx_init(pf);
6519 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6522 err = i40e_dev_rx_init(pf);
6524 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6532 i40e_vmdq_setup(struct rte_eth_dev *dev)
6534 struct rte_eth_conf *conf = &dev->data->dev_conf;
6535 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6536 int i, err, conf_vsis, j, loop;
6537 struct i40e_vsi *vsi;
6538 struct i40e_vmdq_info *vmdq_info;
6539 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6540 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6543 * Disable interrupt to avoid message from VF. Furthermore, it will
6544 * avoid race condition in VSI creation/destroy.
6546 i40e_pf_disable_irq0(hw);
6548 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6549 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6553 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6554 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6555 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6556 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6557 pf->max_nb_vmdq_vsi);
6561 if (pf->vmdq != NULL) {
6562 PMD_INIT_LOG(INFO, "VMDQ already configured");
6566 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6567 sizeof(*vmdq_info) * conf_vsis, 0);
6569 if (pf->vmdq == NULL) {
6570 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6574 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6576 /* Create VMDQ VSI */
6577 for (i = 0; i < conf_vsis; i++) {
6578 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6579 vmdq_conf->enable_loop_back);
6581 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6585 vmdq_info = &pf->vmdq[i];
6587 vmdq_info->vsi = vsi;
6589 pf->nb_cfg_vmdq_vsi = conf_vsis;
6591 /* Configure Vlan */
6592 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6593 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6594 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6595 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6596 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6597 vmdq_conf->pool_map[i].vlan_id, j);
6599 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6600 vmdq_conf->pool_map[i].vlan_id);
6602 PMD_INIT_LOG(ERR, "Failed to add vlan");
6610 i40e_pf_enable_irq0(hw);
6615 for (i = 0; i < conf_vsis; i++)
6616 if (pf->vmdq[i].vsi == NULL)
6619 i40e_vsi_release(pf->vmdq[i].vsi);
6623 i40e_pf_enable_irq0(hw);
6628 i40e_stat_update_32(struct i40e_hw *hw,
6636 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6640 if (new_data >= *offset)
6641 *stat = (uint64_t)(new_data - *offset);
6643 *stat = (uint64_t)((new_data +
6644 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6648 i40e_stat_update_48(struct i40e_hw *hw,
6657 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6658 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6659 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6664 if (new_data >= *offset)
6665 *stat = new_data - *offset;
6667 *stat = (uint64_t)((new_data +
6668 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6670 *stat &= I40E_48_BIT_MASK;
6675 i40e_pf_disable_irq0(struct i40e_hw *hw)
6677 /* Disable all interrupt types */
6678 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6679 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6680 I40E_WRITE_FLUSH(hw);
6685 i40e_pf_enable_irq0(struct i40e_hw *hw)
6687 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6688 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6689 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6690 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6691 I40E_WRITE_FLUSH(hw);
6695 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6697 /* read pending request and disable first */
6698 i40e_pf_disable_irq0(hw);
6699 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6700 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6701 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6704 /* Link no queues with irq0 */
6705 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6706 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6710 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6712 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6713 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6716 uint32_t index, offset, val;
6721 * Try to find which VF trigger a reset, use absolute VF id to access
6722 * since the reg is global register.
6724 for (i = 0; i < pf->vf_num; i++) {
6725 abs_vf_id = hw->func_caps.vf_base_id + i;
6726 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6727 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6728 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6729 /* VFR event occurred */
6730 if (val & (0x1 << offset)) {
6733 /* Clear the event first */
6734 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6736 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6738 * Only notify a VF reset event occurred,
6739 * don't trigger another SW reset
6741 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6742 if (ret != I40E_SUCCESS)
6743 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6749 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6751 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6754 for (i = 0; i < pf->vf_num; i++)
6755 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6759 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6761 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6762 struct i40e_arq_event_info info;
6763 uint16_t pending, opcode;
6766 info.buf_len = I40E_AQ_BUF_SZ;
6767 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6768 if (!info.msg_buf) {
6769 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6775 ret = i40e_clean_arq_element(hw, &info, &pending);
6777 if (ret != I40E_SUCCESS) {
6779 "Failed to read msg from AdminQ, aq_err: %u",
6780 hw->aq.asq_last_status);
6783 opcode = rte_le_to_cpu_16(info.desc.opcode);
6786 case i40e_aqc_opc_send_msg_to_pf:
6787 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6788 i40e_pf_host_handle_vf_msg(dev,
6789 rte_le_to_cpu_16(info.desc.retval),
6790 rte_le_to_cpu_32(info.desc.cookie_high),
6791 rte_le_to_cpu_32(info.desc.cookie_low),
6795 case i40e_aqc_opc_get_link_status:
6796 ret = i40e_dev_link_update(dev, 0);
6798 _rte_eth_dev_callback_process(dev,
6799 RTE_ETH_EVENT_INTR_LSC, NULL);
6802 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6807 rte_free(info.msg_buf);
6811 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6813 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6814 #define I40E_MDD_CLEAR16 0xFFFF
6815 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6816 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6817 bool mdd_detected = false;
6818 struct i40e_pf_vf *vf;
6822 /* find what triggered the MDD event */
6823 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6824 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6825 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6826 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6827 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6828 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6829 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6830 I40E_GL_MDET_TX_EVENT_SHIFT;
6831 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6832 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6833 hw->func_caps.base_queue;
6834 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6835 "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6836 event, queue, pf_num, vf_num, dev->data->name);
6837 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6838 mdd_detected = true;
6840 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6841 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6842 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6843 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6844 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6845 I40E_GL_MDET_RX_EVENT_SHIFT;
6846 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6847 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6848 hw->func_caps.base_queue;
6850 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6851 "queue %d of function 0x%02x device %s\n",
6852 event, queue, func, dev->data->name);
6853 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6854 mdd_detected = true;
6858 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6859 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6860 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6861 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6863 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6864 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6865 I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6867 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6871 /* see if one of the VFs needs its hand slapped */
6872 for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6874 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6875 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6876 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6878 vf->num_mdd_events++;
6879 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6881 i, vf->num_mdd_events);
6884 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6885 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6886 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6888 vf->num_mdd_events++;
6889 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6891 i, vf->num_mdd_events);
6897 * Interrupt handler triggered by NIC for handling
6898 * specific interrupt.
6901 * Pointer to interrupt handle.
6903 * The address of parameter (struct rte_eth_dev *) regsitered before.
6909 i40e_dev_interrupt_handler(void *param)
6911 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6912 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6915 /* Disable interrupt */
6916 i40e_pf_disable_irq0(hw);
6918 /* read out interrupt causes */
6919 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6921 /* No interrupt event indicated */
6922 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6923 PMD_DRV_LOG(INFO, "No interrupt event");
6926 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6927 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6928 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6929 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6930 i40e_handle_mdd_event(dev);
6932 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6933 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6934 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6935 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6936 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6937 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6938 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6939 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6940 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6941 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6943 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6944 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6945 i40e_dev_handle_vfr_event(dev);
6947 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6948 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6949 i40e_dev_handle_aq_msg(dev);
6953 /* Enable interrupt */
6954 i40e_pf_enable_irq0(hw);
6958 i40e_dev_alarm_handler(void *param)
6960 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6961 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6964 /* Disable interrupt */
6965 i40e_pf_disable_irq0(hw);
6967 /* read out interrupt causes */
6968 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6970 /* No interrupt event indicated */
6971 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6973 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6974 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6975 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6976 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6977 i40e_handle_mdd_event(dev);
6979 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6980 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6981 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6982 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6983 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6984 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6985 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6986 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6987 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6988 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6990 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6991 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6992 i40e_dev_handle_vfr_event(dev);
6994 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6995 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6996 i40e_dev_handle_aq_msg(dev);
7000 /* Enable interrupt */
7001 i40e_pf_enable_irq0(hw);
7002 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
7003 i40e_dev_alarm_handler, dev);
7007 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
7008 struct i40e_macvlan_filter *filter,
7011 int ele_num, ele_buff_size;
7012 int num, actual_num, i;
7014 int ret = I40E_SUCCESS;
7015 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7016 struct i40e_aqc_add_macvlan_element_data *req_list;
7018 if (filter == NULL || total == 0)
7019 return I40E_ERR_PARAM;
7020 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7021 ele_buff_size = hw->aq.asq_buf_size;
7023 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
7024 if (req_list == NULL) {
7025 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7026 return I40E_ERR_NO_MEMORY;
7031 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7032 memset(req_list, 0, ele_buff_size);
7034 for (i = 0; i < actual_num; i++) {
7035 rte_memcpy(req_list[i].mac_addr,
7036 &filter[num + i].macaddr, ETH_ADDR_LEN);
7037 req_list[i].vlan_tag =
7038 rte_cpu_to_le_16(filter[num + i].vlan_id);
7040 switch (filter[num + i].filter_type) {
7041 case RTE_MAC_PERFECT_MATCH:
7042 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
7043 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7045 case RTE_MACVLAN_PERFECT_MATCH:
7046 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7048 case RTE_MAC_HASH_MATCH:
7049 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7050 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7052 case RTE_MACVLAN_HASH_MATCH:
7053 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7056 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7057 ret = I40E_ERR_PARAM;
7061 req_list[i].queue_number = 0;
7063 req_list[i].flags = rte_cpu_to_le_16(flags);
7066 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7068 if (ret != I40E_SUCCESS) {
7069 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7073 } while (num < total);
7081 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7082 struct i40e_macvlan_filter *filter,
7085 int ele_num, ele_buff_size;
7086 int num, actual_num, i;
7088 int ret = I40E_SUCCESS;
7089 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7090 struct i40e_aqc_remove_macvlan_element_data *req_list;
7092 if (filter == NULL || total == 0)
7093 return I40E_ERR_PARAM;
7095 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7096 ele_buff_size = hw->aq.asq_buf_size;
7098 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7099 if (req_list == NULL) {
7100 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7101 return I40E_ERR_NO_MEMORY;
7106 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7107 memset(req_list, 0, ele_buff_size);
7109 for (i = 0; i < actual_num; i++) {
7110 rte_memcpy(req_list[i].mac_addr,
7111 &filter[num + i].macaddr, ETH_ADDR_LEN);
7112 req_list[i].vlan_tag =
7113 rte_cpu_to_le_16(filter[num + i].vlan_id);
7115 switch (filter[num + i].filter_type) {
7116 case RTE_MAC_PERFECT_MATCH:
7117 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7118 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7120 case RTE_MACVLAN_PERFECT_MATCH:
7121 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7123 case RTE_MAC_HASH_MATCH:
7124 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7125 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7127 case RTE_MACVLAN_HASH_MATCH:
7128 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7131 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7132 ret = I40E_ERR_PARAM;
7135 req_list[i].flags = rte_cpu_to_le_16(flags);
7138 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7140 if (ret != I40E_SUCCESS) {
7141 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7145 } while (num < total);
7152 /* Find out specific MAC filter */
7153 static struct i40e_mac_filter *
7154 i40e_find_mac_filter(struct i40e_vsi *vsi,
7155 struct rte_ether_addr *macaddr)
7157 struct i40e_mac_filter *f;
7159 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7160 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7168 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7171 uint32_t vid_idx, vid_bit;
7173 if (vlan_id > ETH_VLAN_ID_MAX)
7176 vid_idx = I40E_VFTA_IDX(vlan_id);
7177 vid_bit = I40E_VFTA_BIT(vlan_id);
7179 if (vsi->vfta[vid_idx] & vid_bit)
7186 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7187 uint16_t vlan_id, bool on)
7189 uint32_t vid_idx, vid_bit;
7191 vid_idx = I40E_VFTA_IDX(vlan_id);
7192 vid_bit = I40E_VFTA_BIT(vlan_id);
7195 vsi->vfta[vid_idx] |= vid_bit;
7197 vsi->vfta[vid_idx] &= ~vid_bit;
7201 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7202 uint16_t vlan_id, bool on)
7204 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7205 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7208 if (vlan_id > ETH_VLAN_ID_MAX)
7211 i40e_store_vlan_filter(vsi, vlan_id, on);
7213 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7216 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7219 ret = i40e_aq_add_vlan(hw, vsi->seid,
7220 &vlan_data, 1, NULL);
7221 if (ret != I40E_SUCCESS)
7222 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7224 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7225 &vlan_data, 1, NULL);
7226 if (ret != I40E_SUCCESS)
7228 "Failed to remove vlan filter");
7233 * Find all vlan options for specific mac addr,
7234 * return with actual vlan found.
7237 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7238 struct i40e_macvlan_filter *mv_f,
7239 int num, struct rte_ether_addr *addr)
7245 * Not to use i40e_find_vlan_filter to decrease the loop time,
7246 * although the code looks complex.
7248 if (num < vsi->vlan_num)
7249 return I40E_ERR_PARAM;
7252 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7254 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7255 if (vsi->vfta[j] & (1 << k)) {
7258 "vlan number doesn't match");
7259 return I40E_ERR_PARAM;
7261 rte_memcpy(&mv_f[i].macaddr,
7262 addr, ETH_ADDR_LEN);
7264 j * I40E_UINT32_BIT_SIZE + k;
7270 return I40E_SUCCESS;
7274 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7275 struct i40e_macvlan_filter *mv_f,
7280 struct i40e_mac_filter *f;
7282 if (num < vsi->mac_num)
7283 return I40E_ERR_PARAM;
7285 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7287 PMD_DRV_LOG(ERR, "buffer number not match");
7288 return I40E_ERR_PARAM;
7290 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7292 mv_f[i].vlan_id = vlan;
7293 mv_f[i].filter_type = f->mac_info.filter_type;
7297 return I40E_SUCCESS;
7301 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7304 struct i40e_mac_filter *f;
7305 struct i40e_macvlan_filter *mv_f;
7306 int ret = I40E_SUCCESS;
7308 if (vsi == NULL || vsi->mac_num == 0)
7309 return I40E_ERR_PARAM;
7311 /* Case that no vlan is set */
7312 if (vsi->vlan_num == 0)
7315 num = vsi->mac_num * vsi->vlan_num;
7317 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7319 PMD_DRV_LOG(ERR, "failed to allocate memory");
7320 return I40E_ERR_NO_MEMORY;
7324 if (vsi->vlan_num == 0) {
7325 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7326 rte_memcpy(&mv_f[i].macaddr,
7327 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7328 mv_f[i].filter_type = f->mac_info.filter_type;
7329 mv_f[i].vlan_id = 0;
7333 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7334 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7335 vsi->vlan_num, &f->mac_info.mac_addr);
7336 if (ret != I40E_SUCCESS)
7338 for (j = i; j < i + vsi->vlan_num; j++)
7339 mv_f[j].filter_type = f->mac_info.filter_type;
7344 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7352 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7354 struct i40e_macvlan_filter *mv_f;
7356 int ret = I40E_SUCCESS;
7358 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7359 return I40E_ERR_PARAM;
7361 /* If it's already set, just return */
7362 if (i40e_find_vlan_filter(vsi,vlan))
7363 return I40E_SUCCESS;
7365 mac_num = vsi->mac_num;
7368 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7369 return I40E_ERR_PARAM;
7372 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7375 PMD_DRV_LOG(ERR, "failed to allocate memory");
7376 return I40E_ERR_NO_MEMORY;
7379 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7381 if (ret != I40E_SUCCESS)
7384 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7386 if (ret != I40E_SUCCESS)
7389 i40e_set_vlan_filter(vsi, vlan, 1);
7399 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7401 struct i40e_macvlan_filter *mv_f;
7403 int ret = I40E_SUCCESS;
7406 * Vlan 0 is the generic filter for untagged packets
7407 * and can't be removed.
7409 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7410 return I40E_ERR_PARAM;
7412 /* If can't find it, just return */
7413 if (!i40e_find_vlan_filter(vsi, vlan))
7414 return I40E_ERR_PARAM;
7416 mac_num = vsi->mac_num;
7419 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7420 return I40E_ERR_PARAM;
7423 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7426 PMD_DRV_LOG(ERR, "failed to allocate memory");
7427 return I40E_ERR_NO_MEMORY;
7430 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7432 if (ret != I40E_SUCCESS)
7435 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7437 if (ret != I40E_SUCCESS)
7440 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7441 if (vsi->vlan_num == 1) {
7442 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7443 if (ret != I40E_SUCCESS)
7446 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7447 if (ret != I40E_SUCCESS)
7451 i40e_set_vlan_filter(vsi, vlan, 0);
7461 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7463 struct i40e_mac_filter *f;
7464 struct i40e_macvlan_filter *mv_f;
7465 int i, vlan_num = 0;
7466 int ret = I40E_SUCCESS;
7468 /* If it's add and we've config it, return */
7469 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7471 return I40E_SUCCESS;
7472 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7473 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7476 * If vlan_num is 0, that's the first time to add mac,
7477 * set mask for vlan_id 0.
7479 if (vsi->vlan_num == 0) {
7480 i40e_set_vlan_filter(vsi, 0, 1);
7483 vlan_num = vsi->vlan_num;
7484 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7485 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7488 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7490 PMD_DRV_LOG(ERR, "failed to allocate memory");
7491 return I40E_ERR_NO_MEMORY;
7494 for (i = 0; i < vlan_num; i++) {
7495 mv_f[i].filter_type = mac_filter->filter_type;
7496 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7500 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7501 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7502 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7503 &mac_filter->mac_addr);
7504 if (ret != I40E_SUCCESS)
7508 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7509 if (ret != I40E_SUCCESS)
7512 /* Add the mac addr into mac list */
7513 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7515 PMD_DRV_LOG(ERR, "failed to allocate memory");
7516 ret = I40E_ERR_NO_MEMORY;
7519 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7521 f->mac_info.filter_type = mac_filter->filter_type;
7522 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7533 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7535 struct i40e_mac_filter *f;
7536 struct i40e_macvlan_filter *mv_f;
7538 enum rte_mac_filter_type filter_type;
7539 int ret = I40E_SUCCESS;
7541 /* Can't find it, return an error */
7542 f = i40e_find_mac_filter(vsi, addr);
7544 return I40E_ERR_PARAM;
7546 vlan_num = vsi->vlan_num;
7547 filter_type = f->mac_info.filter_type;
7548 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7549 filter_type == RTE_MACVLAN_HASH_MATCH) {
7550 if (vlan_num == 0) {
7551 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7552 return I40E_ERR_PARAM;
7554 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7555 filter_type == RTE_MAC_HASH_MATCH)
7558 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7560 PMD_DRV_LOG(ERR, "failed to allocate memory");
7561 return I40E_ERR_NO_MEMORY;
7564 for (i = 0; i < vlan_num; i++) {
7565 mv_f[i].filter_type = filter_type;
7566 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7569 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7570 filter_type == RTE_MACVLAN_HASH_MATCH) {
7571 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7572 if (ret != I40E_SUCCESS)
7576 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7577 if (ret != I40E_SUCCESS)
7580 /* Remove the mac addr into mac list */
7581 TAILQ_REMOVE(&vsi->mac_list, f, next);
7591 /* Configure hash enable flags for RSS */
7593 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7601 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7602 if (flags & (1ULL << i))
7603 hena |= adapter->pctypes_tbl[i];
7609 /* Parse the hash enable flags */
7611 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7613 uint64_t rss_hf = 0;
7619 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7620 if (flags & adapter->pctypes_tbl[i])
7621 rss_hf |= (1ULL << i);
7628 i40e_pf_disable_rss(struct i40e_pf *pf)
7630 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7632 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7633 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7634 I40E_WRITE_FLUSH(hw);
7638 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7640 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7641 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7642 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7643 I40E_VFQF_HKEY_MAX_INDEX :
7644 I40E_PFQF_HKEY_MAX_INDEX;
7647 if (!key || key_len == 0) {
7648 PMD_DRV_LOG(DEBUG, "No key to be configured");
7650 } else if (key_len != (key_idx + 1) *
7652 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7656 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7657 struct i40e_aqc_get_set_rss_key_data *key_dw =
7658 (struct i40e_aqc_get_set_rss_key_data *)key;
7660 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7662 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7664 uint32_t *hash_key = (uint32_t *)key;
7667 if (vsi->type == I40E_VSI_SRIOV) {
7668 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7671 I40E_VFQF_HKEY1(i, vsi->user_param),
7675 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7676 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7679 I40E_WRITE_FLUSH(hw);
7686 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7688 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7689 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7693 if (!key || !key_len)
7696 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7697 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7698 (struct i40e_aqc_get_set_rss_key_data *)key);
7700 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7704 uint32_t *key_dw = (uint32_t *)key;
7707 if (vsi->type == I40E_VSI_SRIOV) {
7708 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7709 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7710 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7712 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7715 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7716 reg = I40E_PFQF_HKEY(i);
7717 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7719 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7727 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7729 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7733 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7734 rss_conf->rss_key_len);
7738 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7739 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7740 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7741 I40E_WRITE_FLUSH(hw);
7747 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7748 struct rte_eth_rss_conf *rss_conf)
7750 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7751 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7752 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7755 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7756 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7758 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7759 if (rss_hf != 0) /* Enable RSS */
7761 return 0; /* Nothing to do */
7764 if (rss_hf == 0) /* Disable RSS */
7767 return i40e_hw_rss_hash_set(pf, rss_conf);
7771 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7772 struct rte_eth_rss_conf *rss_conf)
7774 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7775 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7782 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7783 &rss_conf->rss_key_len);
7787 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7788 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7789 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7795 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7797 switch (filter_type) {
7798 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7799 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7801 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7802 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7804 case RTE_TUNNEL_FILTER_IMAC_TENID:
7805 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7807 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7808 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7810 case ETH_TUNNEL_FILTER_IMAC:
7811 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7813 case ETH_TUNNEL_FILTER_OIP:
7814 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7816 case ETH_TUNNEL_FILTER_IIP:
7817 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7820 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7827 /* Convert tunnel filter structure */
7829 i40e_tunnel_filter_convert(
7830 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7831 struct i40e_tunnel_filter *tunnel_filter)
7833 rte_ether_addr_copy((struct rte_ether_addr *)
7834 &cld_filter->element.outer_mac,
7835 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7836 rte_ether_addr_copy((struct rte_ether_addr *)
7837 &cld_filter->element.inner_mac,
7838 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7839 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7840 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7841 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7842 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7843 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7845 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7846 tunnel_filter->input.flags = cld_filter->element.flags;
7847 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7848 tunnel_filter->queue = cld_filter->element.queue_number;
7849 rte_memcpy(tunnel_filter->input.general_fields,
7850 cld_filter->general_fields,
7851 sizeof(cld_filter->general_fields));
7856 /* Check if there exists the tunnel filter */
7857 struct i40e_tunnel_filter *
7858 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7859 const struct i40e_tunnel_filter_input *input)
7863 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7867 return tunnel_rule->hash_map[ret];
7870 /* Add a tunnel filter into the SW list */
7872 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7873 struct i40e_tunnel_filter *tunnel_filter)
7875 struct i40e_tunnel_rule *rule = &pf->tunnel;
7878 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7881 "Failed to insert tunnel filter to hash table %d!",
7885 rule->hash_map[ret] = tunnel_filter;
7887 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7892 /* Delete a tunnel filter from the SW list */
7894 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7895 struct i40e_tunnel_filter_input *input)
7897 struct i40e_tunnel_rule *rule = &pf->tunnel;
7898 struct i40e_tunnel_filter *tunnel_filter;
7901 ret = rte_hash_del_key(rule->hash_table, input);
7904 "Failed to delete tunnel filter to hash table %d!",
7908 tunnel_filter = rule->hash_map[ret];
7909 rule->hash_map[ret] = NULL;
7911 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7912 rte_free(tunnel_filter);
7918 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7919 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7923 uint32_t ipv4_addr, ipv4_addr_le;
7924 uint8_t i, tun_type = 0;
7925 /* internal varialbe to convert ipv6 byte order */
7926 uint32_t convert_ipv6[4];
7928 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7929 struct i40e_vsi *vsi = pf->main_vsi;
7930 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7931 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7932 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7933 struct i40e_tunnel_filter *tunnel, *node;
7934 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7936 cld_filter = rte_zmalloc("tunnel_filter",
7937 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7940 if (NULL == cld_filter) {
7941 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7944 pfilter = cld_filter;
7946 rte_ether_addr_copy(&tunnel_filter->outer_mac,
7947 (struct rte_ether_addr *)&pfilter->element.outer_mac);
7948 rte_ether_addr_copy(&tunnel_filter->inner_mac,
7949 (struct rte_ether_addr *)&pfilter->element.inner_mac);
7951 pfilter->element.inner_vlan =
7952 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7953 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7954 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7955 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7956 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7957 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7959 sizeof(pfilter->element.ipaddr.v4.data));
7961 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7962 for (i = 0; i < 4; i++) {
7964 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7966 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7968 sizeof(pfilter->element.ipaddr.v6.data));
7971 /* check tunneled type */
7972 switch (tunnel_filter->tunnel_type) {
7973 case RTE_TUNNEL_TYPE_VXLAN:
7974 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7976 case RTE_TUNNEL_TYPE_NVGRE:
7977 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7979 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7980 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7982 case RTE_TUNNEL_TYPE_VXLAN_GPE:
7983 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7986 /* Other tunnel types is not supported. */
7987 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7988 rte_free(cld_filter);
7992 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7993 &pfilter->element.flags);
7995 rte_free(cld_filter);
7999 pfilter->element.flags |= rte_cpu_to_le_16(
8000 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8001 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8002 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8003 pfilter->element.queue_number =
8004 rte_cpu_to_le_16(tunnel_filter->queue_id);
8006 /* Check if there is the filter in SW list */
8007 memset(&check_filter, 0, sizeof(check_filter));
8008 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8009 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8011 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8012 rte_free(cld_filter);
8016 if (!add && !node) {
8017 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8018 rte_free(cld_filter);
8023 ret = i40e_aq_add_cloud_filters(hw,
8024 vsi->seid, &cld_filter->element, 1);
8026 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8027 rte_free(cld_filter);
8030 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8031 if (tunnel == NULL) {
8032 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8033 rte_free(cld_filter);
8037 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8038 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8042 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8043 &cld_filter->element, 1);
8045 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8046 rte_free(cld_filter);
8049 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8052 rte_free(cld_filter);
8056 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8057 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
8058 #define I40E_TR_GENEVE_KEY_MASK 0x8
8059 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
8060 #define I40E_TR_GRE_KEY_MASK 0x400
8061 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
8062 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
8063 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
8064 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
8065 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
8066 #define I40E_DIRECTION_INGRESS_KEY 0x8000
8067 #define I40E_TR_L4_TYPE_TCP 0x2
8068 #define I40E_TR_L4_TYPE_UDP 0x4
8069 #define I40E_TR_L4_TYPE_SCTP 0x8
8072 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8074 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8075 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8076 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8077 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8078 enum i40e_status_code status = I40E_SUCCESS;
8080 if (pf->support_multi_driver) {
8081 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8082 return I40E_NOT_SUPPORTED;
8085 memset(&filter_replace, 0,
8086 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8087 memset(&filter_replace_buf, 0,
8088 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8090 /* create L1 filter */
8091 filter_replace.old_filter_type =
8092 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8093 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8094 filter_replace.tr_bit = 0;
8096 /* Prepare the buffer, 3 entries */
8097 filter_replace_buf.data[0] =
8098 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8099 filter_replace_buf.data[0] |=
8100 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8101 filter_replace_buf.data[2] = 0xFF;
8102 filter_replace_buf.data[3] = 0xFF;
8103 filter_replace_buf.data[4] =
8104 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8105 filter_replace_buf.data[4] |=
8106 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8107 filter_replace_buf.data[7] = 0xF0;
8108 filter_replace_buf.data[8]
8109 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8110 filter_replace_buf.data[8] |=
8111 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8112 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8113 I40E_TR_GENEVE_KEY_MASK |
8114 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8115 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8116 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8117 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8119 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8120 &filter_replace_buf);
8121 if (!status && (filter_replace.old_filter_type !=
8122 filter_replace.new_filter_type))
8123 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8124 " original: 0x%x, new: 0x%x",
8126 filter_replace.old_filter_type,
8127 filter_replace.new_filter_type);
8133 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8135 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8136 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8137 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8138 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8139 enum i40e_status_code status = I40E_SUCCESS;
8141 if (pf->support_multi_driver) {
8142 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8143 return I40E_NOT_SUPPORTED;
8147 memset(&filter_replace, 0,
8148 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8149 memset(&filter_replace_buf, 0,
8150 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8151 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8152 I40E_AQC_MIRROR_CLOUD_FILTER;
8153 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8154 filter_replace.new_filter_type =
8155 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8156 /* Prepare the buffer, 2 entries */
8157 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8158 filter_replace_buf.data[0] |=
8159 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8160 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8161 filter_replace_buf.data[4] |=
8162 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8163 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8164 &filter_replace_buf);
8167 if (filter_replace.old_filter_type !=
8168 filter_replace.new_filter_type)
8169 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8170 " original: 0x%x, new: 0x%x",
8172 filter_replace.old_filter_type,
8173 filter_replace.new_filter_type);
8176 memset(&filter_replace, 0,
8177 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8178 memset(&filter_replace_buf, 0,
8179 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8181 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8182 I40E_AQC_MIRROR_CLOUD_FILTER;
8183 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8184 filter_replace.new_filter_type =
8185 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8186 /* Prepare the buffer, 2 entries */
8187 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8188 filter_replace_buf.data[0] |=
8189 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8190 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8191 filter_replace_buf.data[4] |=
8192 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8194 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8195 &filter_replace_buf);
8196 if (!status && (filter_replace.old_filter_type !=
8197 filter_replace.new_filter_type))
8198 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8199 " original: 0x%x, new: 0x%x",
8201 filter_replace.old_filter_type,
8202 filter_replace.new_filter_type);
8207 static enum i40e_status_code
8208 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8210 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8211 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8212 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8213 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8214 enum i40e_status_code status = I40E_SUCCESS;
8216 if (pf->support_multi_driver) {
8217 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8218 return I40E_NOT_SUPPORTED;
8222 memset(&filter_replace, 0,
8223 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8224 memset(&filter_replace_buf, 0,
8225 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8226 /* create L1 filter */
8227 filter_replace.old_filter_type =
8228 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8229 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8230 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8231 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8232 /* Prepare the buffer, 2 entries */
8233 filter_replace_buf.data[0] =
8234 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8235 filter_replace_buf.data[0] |=
8236 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8237 filter_replace_buf.data[2] = 0xFF;
8238 filter_replace_buf.data[3] = 0xFF;
8239 filter_replace_buf.data[4] =
8240 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8241 filter_replace_buf.data[4] |=
8242 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8243 filter_replace_buf.data[6] = 0xFF;
8244 filter_replace_buf.data[7] = 0xFF;
8245 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8246 &filter_replace_buf);
8249 if (filter_replace.old_filter_type !=
8250 filter_replace.new_filter_type)
8251 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8252 " original: 0x%x, new: 0x%x",
8254 filter_replace.old_filter_type,
8255 filter_replace.new_filter_type);
8258 memset(&filter_replace, 0,
8259 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8260 memset(&filter_replace_buf, 0,
8261 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8262 /* create L1 filter */
8263 filter_replace.old_filter_type =
8264 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8265 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8266 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8267 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8268 /* Prepare the buffer, 2 entries */
8269 filter_replace_buf.data[0] =
8270 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8271 filter_replace_buf.data[0] |=
8272 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8273 filter_replace_buf.data[2] = 0xFF;
8274 filter_replace_buf.data[3] = 0xFF;
8275 filter_replace_buf.data[4] =
8276 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8277 filter_replace_buf.data[4] |=
8278 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8279 filter_replace_buf.data[6] = 0xFF;
8280 filter_replace_buf.data[7] = 0xFF;
8282 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8283 &filter_replace_buf);
8284 if (!status && (filter_replace.old_filter_type !=
8285 filter_replace.new_filter_type))
8286 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8287 " original: 0x%x, new: 0x%x",
8289 filter_replace.old_filter_type,
8290 filter_replace.new_filter_type);
8296 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8298 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8299 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8300 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8301 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8302 enum i40e_status_code status = I40E_SUCCESS;
8304 if (pf->support_multi_driver) {
8305 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8306 return I40E_NOT_SUPPORTED;
8310 memset(&filter_replace, 0,
8311 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8312 memset(&filter_replace_buf, 0,
8313 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8314 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8315 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8316 filter_replace.new_filter_type =
8317 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8318 /* Prepare the buffer, 2 entries */
8319 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8320 filter_replace_buf.data[0] |=
8321 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8322 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8323 filter_replace_buf.data[4] |=
8324 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8325 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8326 &filter_replace_buf);
8329 if (filter_replace.old_filter_type !=
8330 filter_replace.new_filter_type)
8331 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8332 " original: 0x%x, new: 0x%x",
8334 filter_replace.old_filter_type,
8335 filter_replace.new_filter_type);
8338 memset(&filter_replace, 0,
8339 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8340 memset(&filter_replace_buf, 0,
8341 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8342 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8343 filter_replace.old_filter_type =
8344 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8345 filter_replace.new_filter_type =
8346 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8347 /* Prepare the buffer, 2 entries */
8348 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8349 filter_replace_buf.data[0] |=
8350 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8351 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8352 filter_replace_buf.data[4] |=
8353 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8355 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8356 &filter_replace_buf);
8357 if (!status && (filter_replace.old_filter_type !=
8358 filter_replace.new_filter_type))
8359 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8360 " original: 0x%x, new: 0x%x",
8362 filter_replace.old_filter_type,
8363 filter_replace.new_filter_type);
8368 static enum i40e_status_code
8369 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8370 enum i40e_l4_port_type l4_port_type)
8372 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8373 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8374 enum i40e_status_code status = I40E_SUCCESS;
8375 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8376 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8378 if (pf->support_multi_driver) {
8379 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8380 return I40E_NOT_SUPPORTED;
8383 memset(&filter_replace, 0,
8384 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8385 memset(&filter_replace_buf, 0,
8386 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8388 /* create L1 filter */
8389 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8390 filter_replace.old_filter_type =
8391 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8392 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8393 filter_replace_buf.data[8] =
8394 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8396 filter_replace.old_filter_type =
8397 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8398 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8399 filter_replace_buf.data[8] =
8400 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8403 filter_replace.tr_bit = 0;
8404 /* Prepare the buffer, 3 entries */
8405 filter_replace_buf.data[0] =
8406 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8407 filter_replace_buf.data[0] |=
8408 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8409 filter_replace_buf.data[2] = 0x00;
8410 filter_replace_buf.data[3] =
8411 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8412 filter_replace_buf.data[4] =
8413 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8414 filter_replace_buf.data[4] |=
8415 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8416 filter_replace_buf.data[5] = 0x00;
8417 filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8418 I40E_TR_L4_TYPE_TCP |
8419 I40E_TR_L4_TYPE_SCTP;
8420 filter_replace_buf.data[7] = 0x00;
8421 filter_replace_buf.data[8] |=
8422 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8423 filter_replace_buf.data[9] = 0x00;
8424 filter_replace_buf.data[10] = 0xFF;
8425 filter_replace_buf.data[11] = 0xFF;
8427 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8428 &filter_replace_buf);
8429 if (!status && filter_replace.old_filter_type !=
8430 filter_replace.new_filter_type)
8431 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8432 " original: 0x%x, new: 0x%x",
8434 filter_replace.old_filter_type,
8435 filter_replace.new_filter_type);
8440 static enum i40e_status_code
8441 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8442 enum i40e_l4_port_type l4_port_type)
8444 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8445 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8446 enum i40e_status_code status = I40E_SUCCESS;
8447 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8448 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8450 if (pf->support_multi_driver) {
8451 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8452 return I40E_NOT_SUPPORTED;
8455 memset(&filter_replace, 0,
8456 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8457 memset(&filter_replace_buf, 0,
8458 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8460 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8461 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8462 filter_replace.new_filter_type =
8463 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8464 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8466 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8467 filter_replace.new_filter_type =
8468 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8469 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8472 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8473 filter_replace.tr_bit = 0;
8474 /* Prepare the buffer, 2 entries */
8475 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8476 filter_replace_buf.data[0] |=
8477 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8478 filter_replace_buf.data[4] |=
8479 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8480 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8481 &filter_replace_buf);
8483 if (!status && filter_replace.old_filter_type !=
8484 filter_replace.new_filter_type)
8485 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8486 " original: 0x%x, new: 0x%x",
8488 filter_replace.old_filter_type,
8489 filter_replace.new_filter_type);
8495 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8496 struct i40e_tunnel_filter_conf *tunnel_filter,
8500 uint32_t ipv4_addr, ipv4_addr_le;
8501 uint8_t i, tun_type = 0;
8502 /* internal variable to convert ipv6 byte order */
8503 uint32_t convert_ipv6[4];
8505 struct i40e_pf_vf *vf = NULL;
8506 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8507 struct i40e_vsi *vsi;
8508 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8509 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8510 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8511 struct i40e_tunnel_filter *tunnel, *node;
8512 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8514 bool big_buffer = 0;
8516 cld_filter = rte_zmalloc("tunnel_filter",
8517 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8520 if (cld_filter == NULL) {
8521 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8524 pfilter = cld_filter;
8526 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8527 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8528 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8529 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8531 pfilter->element.inner_vlan =
8532 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8533 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8534 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8535 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8536 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8537 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8539 sizeof(pfilter->element.ipaddr.v4.data));
8541 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8542 for (i = 0; i < 4; i++) {
8544 rte_cpu_to_le_32(rte_be_to_cpu_32(
8545 tunnel_filter->ip_addr.ipv6_addr[i]));
8547 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8549 sizeof(pfilter->element.ipaddr.v6.data));
8552 /* check tunneled type */
8553 switch (tunnel_filter->tunnel_type) {
8554 case I40E_TUNNEL_TYPE_VXLAN:
8555 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8557 case I40E_TUNNEL_TYPE_NVGRE:
8558 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8560 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8561 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8563 case I40E_TUNNEL_TYPE_MPLSoUDP:
8564 if (!pf->mpls_replace_flag) {
8565 i40e_replace_mpls_l1_filter(pf);
8566 i40e_replace_mpls_cloud_filter(pf);
8567 pf->mpls_replace_flag = 1;
8569 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8570 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8572 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8573 (teid_le & 0xF) << 12;
8574 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8577 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8579 case I40E_TUNNEL_TYPE_MPLSoGRE:
8580 if (!pf->mpls_replace_flag) {
8581 i40e_replace_mpls_l1_filter(pf);
8582 i40e_replace_mpls_cloud_filter(pf);
8583 pf->mpls_replace_flag = 1;
8585 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8586 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8588 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8589 (teid_le & 0xF) << 12;
8590 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8593 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8595 case I40E_TUNNEL_TYPE_GTPC:
8596 if (!pf->gtp_replace_flag) {
8597 i40e_replace_gtp_l1_filter(pf);
8598 i40e_replace_gtp_cloud_filter(pf);
8599 pf->gtp_replace_flag = 1;
8601 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8602 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8603 (teid_le >> 16) & 0xFFFF;
8604 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8606 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8610 case I40E_TUNNEL_TYPE_GTPU:
8611 if (!pf->gtp_replace_flag) {
8612 i40e_replace_gtp_l1_filter(pf);
8613 i40e_replace_gtp_cloud_filter(pf);
8614 pf->gtp_replace_flag = 1;
8616 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8617 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8618 (teid_le >> 16) & 0xFFFF;
8619 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8621 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8625 case I40E_TUNNEL_TYPE_QINQ:
8626 if (!pf->qinq_replace_flag) {
8627 ret = i40e_cloud_filter_qinq_create(pf);
8630 "QinQ tunnel filter already created.");
8631 pf->qinq_replace_flag = 1;
8633 /* Add in the General fields the values of
8634 * the Outer and Inner VLAN
8635 * Big Buffer should be set, see changes in
8636 * i40e_aq_add_cloud_filters
8638 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8639 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8642 case I40E_CLOUD_TYPE_UDP:
8643 case I40E_CLOUD_TYPE_TCP:
8644 case I40E_CLOUD_TYPE_SCTP:
8645 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8646 if (!pf->sport_replace_flag) {
8647 i40e_replace_port_l1_filter(pf,
8648 tunnel_filter->l4_port_type);
8649 i40e_replace_port_cloud_filter(pf,
8650 tunnel_filter->l4_port_type);
8651 pf->sport_replace_flag = 1;
8653 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8654 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8655 I40E_DIRECTION_INGRESS_KEY;
8657 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8658 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8659 I40E_TR_L4_TYPE_UDP;
8660 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8661 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8662 I40E_TR_L4_TYPE_TCP;
8664 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8665 I40E_TR_L4_TYPE_SCTP;
8667 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8668 (teid_le >> 16) & 0xFFFF;
8671 if (!pf->dport_replace_flag) {
8672 i40e_replace_port_l1_filter(pf,
8673 tunnel_filter->l4_port_type);
8674 i40e_replace_port_cloud_filter(pf,
8675 tunnel_filter->l4_port_type);
8676 pf->dport_replace_flag = 1;
8678 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8679 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8680 I40E_DIRECTION_INGRESS_KEY;
8682 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8683 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8684 I40E_TR_L4_TYPE_UDP;
8685 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8686 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8687 I40E_TR_L4_TYPE_TCP;
8689 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8690 I40E_TR_L4_TYPE_SCTP;
8692 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8693 (teid_le >> 16) & 0xFFFF;
8699 /* Other tunnel types is not supported. */
8700 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8701 rte_free(cld_filter);
8705 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8706 pfilter->element.flags =
8707 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8708 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8709 pfilter->element.flags =
8710 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8711 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8712 pfilter->element.flags =
8713 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8714 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8715 pfilter->element.flags =
8716 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8717 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8718 pfilter->element.flags |=
8719 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8720 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8721 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8722 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8723 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8724 pfilter->element.flags |=
8725 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8727 pfilter->element.flags |=
8728 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8730 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8731 &pfilter->element.flags);
8733 rte_free(cld_filter);
8738 pfilter->element.flags |= rte_cpu_to_le_16(
8739 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8740 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8741 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8742 pfilter->element.queue_number =
8743 rte_cpu_to_le_16(tunnel_filter->queue_id);
8745 if (!tunnel_filter->is_to_vf)
8748 if (tunnel_filter->vf_id >= pf->vf_num) {
8749 PMD_DRV_LOG(ERR, "Invalid argument.");
8750 rte_free(cld_filter);
8753 vf = &pf->vfs[tunnel_filter->vf_id];
8757 /* Check if there is the filter in SW list */
8758 memset(&check_filter, 0, sizeof(check_filter));
8759 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8760 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8761 check_filter.vf_id = tunnel_filter->vf_id;
8762 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8764 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8765 rte_free(cld_filter);
8769 if (!add && !node) {
8770 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8771 rte_free(cld_filter);
8777 ret = i40e_aq_add_cloud_filters_bb(hw,
8778 vsi->seid, cld_filter, 1);
8780 ret = i40e_aq_add_cloud_filters(hw,
8781 vsi->seid, &cld_filter->element, 1);
8783 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8784 rte_free(cld_filter);
8787 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8788 if (tunnel == NULL) {
8789 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8790 rte_free(cld_filter);
8794 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8795 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8800 ret = i40e_aq_rem_cloud_filters_bb(
8801 hw, vsi->seid, cld_filter, 1);
8803 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8804 &cld_filter->element, 1);
8806 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8807 rte_free(cld_filter);
8810 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8813 rte_free(cld_filter);
8818 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8822 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8823 if (pf->vxlan_ports[i] == port)
8831 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8834 uint8_t filter_idx = 0;
8835 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8837 idx = i40e_get_vxlan_port_idx(pf, port);
8839 /* Check if port already exists */
8841 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8845 /* Now check if there is space to add the new port */
8846 idx = i40e_get_vxlan_port_idx(pf, 0);
8849 "Maximum number of UDP ports reached, not adding port %d",
8854 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8857 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8861 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8864 /* New port: add it and mark its index in the bitmap */
8865 pf->vxlan_ports[idx] = port;
8866 pf->vxlan_bitmap |= (1 << idx);
8868 if (!(pf->flags & I40E_FLAG_VXLAN))
8869 pf->flags |= I40E_FLAG_VXLAN;
8875 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8878 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8880 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8881 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8885 idx = i40e_get_vxlan_port_idx(pf, port);
8888 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8892 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8893 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8897 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8900 pf->vxlan_ports[idx] = 0;
8901 pf->vxlan_bitmap &= ~(1 << idx);
8903 if (!pf->vxlan_bitmap)
8904 pf->flags &= ~I40E_FLAG_VXLAN;
8909 /* Add UDP tunneling port */
8911 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8912 struct rte_eth_udp_tunnel *udp_tunnel)
8915 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8917 if (udp_tunnel == NULL)
8920 switch (udp_tunnel->prot_type) {
8921 case RTE_TUNNEL_TYPE_VXLAN:
8922 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8923 I40E_AQC_TUNNEL_TYPE_VXLAN);
8925 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8926 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8927 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8929 case RTE_TUNNEL_TYPE_GENEVE:
8930 case RTE_TUNNEL_TYPE_TEREDO:
8931 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8936 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8944 /* Remove UDP tunneling port */
8946 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8947 struct rte_eth_udp_tunnel *udp_tunnel)
8950 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8952 if (udp_tunnel == NULL)
8955 switch (udp_tunnel->prot_type) {
8956 case RTE_TUNNEL_TYPE_VXLAN:
8957 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8958 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8960 case RTE_TUNNEL_TYPE_GENEVE:
8961 case RTE_TUNNEL_TYPE_TEREDO:
8962 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8966 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8974 /* Calculate the maximum number of contiguous PF queues that are configured */
8976 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8978 struct rte_eth_dev_data *data = pf->dev_data;
8980 struct i40e_rx_queue *rxq;
8983 for (i = 0; i < pf->lan_nb_qps; i++) {
8984 rxq = data->rx_queues[i];
8985 if (rxq && rxq->q_set)
8996 i40e_pf_config_rss(struct i40e_pf *pf)
8998 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8999 struct rte_eth_rss_conf rss_conf;
9000 uint32_t i, lut = 0;
9004 * If both VMDQ and RSS enabled, not all of PF queues are configured.
9005 * It's necessary to calculate the actual PF queues that are configured.
9007 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
9008 num = i40e_pf_calc_configured_queues_num(pf);
9010 num = pf->dev_data->nb_rx_queues;
9012 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
9013 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
9018 "No PF queues are configured to enable RSS for port %u",
9019 pf->dev_data->port_id);
9023 if (pf->adapter->rss_reta_updated == 0) {
9024 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
9027 lut = (lut << 8) | (j & ((0x1 <<
9028 hw->func_caps.rss_table_entry_width) - 1));
9030 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
9035 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
9036 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
9037 i40e_pf_disable_rss(pf);
9040 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
9041 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
9042 /* Random default keys */
9043 static uint32_t rss_key_default[] = {0x6b793944,
9044 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
9045 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
9046 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
9048 rss_conf.rss_key = (uint8_t *)rss_key_default;
9049 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
9053 return i40e_hw_rss_hash_set(pf, &rss_conf);
9057 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
9058 struct rte_eth_tunnel_filter_conf *filter)
9060 if (pf == NULL || filter == NULL) {
9061 PMD_DRV_LOG(ERR, "Invalid parameter");
9065 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
9066 PMD_DRV_LOG(ERR, "Invalid queue ID");
9070 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
9071 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
9075 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
9076 (rte_is_zero_ether_addr(&filter->outer_mac))) {
9077 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
9081 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
9082 (rte_is_zero_ether_addr(&filter->inner_mac))) {
9083 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
9090 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
9091 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
9093 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
9095 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9099 if (pf->support_multi_driver) {
9100 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
9104 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
9105 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
9108 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
9109 } else if (len == 4) {
9110 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
9112 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
9117 ret = i40e_aq_debug_write_global_register(hw,
9118 I40E_GL_PRS_FVBM(2),
9122 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9123 "with value 0x%08x",
9124 I40E_GL_PRS_FVBM(2), reg);
9128 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9129 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9135 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
9142 switch (cfg->cfg_type) {
9143 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
9144 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
9147 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
9155 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
9156 enum rte_filter_op filter_op,
9159 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9160 int ret = I40E_ERR_PARAM;
9162 switch (filter_op) {
9163 case RTE_ETH_FILTER_SET:
9164 ret = i40e_dev_global_config_set(hw,
9165 (struct rte_eth_global_cfg *)arg);
9168 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9176 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
9177 enum rte_filter_op filter_op,
9180 struct rte_eth_tunnel_filter_conf *filter;
9181 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9182 int ret = I40E_SUCCESS;
9184 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
9186 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
9187 return I40E_ERR_PARAM;
9189 switch (filter_op) {
9190 case RTE_ETH_FILTER_NOP:
9191 if (!(pf->flags & I40E_FLAG_VXLAN))
9192 ret = I40E_NOT_SUPPORTED;
9194 case RTE_ETH_FILTER_ADD:
9195 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
9197 case RTE_ETH_FILTER_DELETE:
9198 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
9201 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9202 ret = I40E_ERR_PARAM;
9210 i40e_pf_config_mq_rx(struct i40e_pf *pf)
9213 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
9216 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
9217 ret = i40e_pf_config_rss(pf);
9219 i40e_pf_disable_rss(pf);
9224 /* Get the symmetric hash enable configurations per port */
9226 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
9228 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9230 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
9233 /* Set the symmetric hash enable configurations per port */
9235 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9237 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9240 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9242 "Symmetric hash has already been enabled");
9245 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9247 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9249 "Symmetric hash has already been disabled");
9252 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9254 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9255 I40E_WRITE_FLUSH(hw);
9259 * Get global configurations of hash function type and symmetric hash enable
9260 * per flow type (pctype). Note that global configuration means it affects all
9261 * the ports on the same NIC.
9264 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9265 struct rte_eth_hash_global_conf *g_cfg)
9267 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9271 memset(g_cfg, 0, sizeof(*g_cfg));
9272 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9273 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9274 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9276 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9277 PMD_DRV_LOG(DEBUG, "Hash function is %s",
9278 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9281 * As i40e supports less than 64 flow types, only first 64 bits need to
9284 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9285 g_cfg->valid_bit_mask[i] = 0ULL;
9286 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9289 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9291 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9292 if (!adapter->pctypes_tbl[i])
9294 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9295 j < I40E_FILTER_PCTYPE_MAX; j++) {
9296 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9297 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9298 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9299 g_cfg->sym_hash_enable_mask[0] |=
9310 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9311 const struct rte_eth_hash_global_conf *g_cfg)
9314 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9316 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9317 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9318 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9319 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9325 * As i40e supports less than 64 flow types, only first 64 bits need to
9328 mask0 = g_cfg->valid_bit_mask[0];
9329 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9331 /* Check if any unsupported flow type configured */
9332 if ((mask0 | i40e_mask) ^ i40e_mask)
9335 if (g_cfg->valid_bit_mask[i])
9343 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9349 * Set global configurations of hash function type and symmetric hash enable
9350 * per flow type (pctype). Note any modifying global configuration will affect
9351 * all the ports on the same NIC.
9354 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9355 struct rte_eth_hash_global_conf *g_cfg)
9357 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9358 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9362 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9364 if (pf->support_multi_driver) {
9365 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9369 /* Check the input parameters */
9370 ret = i40e_hash_global_config_check(adapter, g_cfg);
9375 * As i40e supports less than 64 flow types, only first 64 bits need to
9378 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9379 if (mask0 & (1UL << i)) {
9380 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9381 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9383 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9384 j < I40E_FILTER_PCTYPE_MAX; j++) {
9385 if (adapter->pctypes_tbl[i] & (1ULL << j))
9386 i40e_write_global_rx_ctl(hw,
9393 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9394 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9396 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9398 "Hash function already set to Toeplitz");
9401 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9402 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9404 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9406 "Hash function already set to Simple XOR");
9409 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9411 /* Use the default, and keep it as it is */
9414 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9417 I40E_WRITE_FLUSH(hw);
9423 * Valid input sets for hash and flow director filters per PCTYPE
9426 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9427 enum rte_filter_type filter)
9431 static const uint64_t valid_hash_inset_table[] = {
9432 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9433 I40E_INSET_DMAC | I40E_INSET_SMAC |
9434 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9435 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9436 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9437 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9438 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9439 I40E_INSET_FLEX_PAYLOAD,
9440 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9441 I40E_INSET_DMAC | I40E_INSET_SMAC |
9442 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9443 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9444 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9445 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9446 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9447 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9448 I40E_INSET_FLEX_PAYLOAD,
9449 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9450 I40E_INSET_DMAC | I40E_INSET_SMAC |
9451 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9452 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9453 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9454 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9455 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9456 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9457 I40E_INSET_FLEX_PAYLOAD,
9458 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9459 I40E_INSET_DMAC | I40E_INSET_SMAC |
9460 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9461 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9462 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9463 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9464 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9465 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9466 I40E_INSET_FLEX_PAYLOAD,
9467 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9468 I40E_INSET_DMAC | I40E_INSET_SMAC |
9469 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9470 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9471 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9472 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9473 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9474 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9475 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9476 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9477 I40E_INSET_DMAC | I40E_INSET_SMAC |
9478 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9479 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9480 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9481 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9482 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9483 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9484 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9485 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9486 I40E_INSET_DMAC | I40E_INSET_SMAC |
9487 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9488 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9489 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9490 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9491 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9492 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9493 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9494 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9495 I40E_INSET_DMAC | I40E_INSET_SMAC |
9496 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9497 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9498 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9499 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9500 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9501 I40E_INSET_FLEX_PAYLOAD,
9502 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9503 I40E_INSET_DMAC | I40E_INSET_SMAC |
9504 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9505 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9506 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9507 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9508 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9509 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9510 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9511 I40E_INSET_DMAC | I40E_INSET_SMAC |
9512 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9513 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9514 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9515 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9516 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9517 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9518 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9519 I40E_INSET_DMAC | I40E_INSET_SMAC |
9520 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9521 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9522 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9523 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9524 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9525 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9526 I40E_INSET_FLEX_PAYLOAD,
9527 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9528 I40E_INSET_DMAC | I40E_INSET_SMAC |
9529 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9530 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9531 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9532 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9533 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9534 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9535 I40E_INSET_FLEX_PAYLOAD,
9536 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9537 I40E_INSET_DMAC | I40E_INSET_SMAC |
9538 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9539 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9540 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9541 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9542 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9543 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9544 I40E_INSET_FLEX_PAYLOAD,
9545 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9546 I40E_INSET_DMAC | I40E_INSET_SMAC |
9547 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9548 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9549 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9550 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9551 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9552 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9553 I40E_INSET_FLEX_PAYLOAD,
9554 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9555 I40E_INSET_DMAC | I40E_INSET_SMAC |
9556 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9557 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9558 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9559 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9560 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9561 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9562 I40E_INSET_FLEX_PAYLOAD,
9563 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9564 I40E_INSET_DMAC | I40E_INSET_SMAC |
9565 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9566 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9567 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9568 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9569 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9570 I40E_INSET_FLEX_PAYLOAD,
9571 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9572 I40E_INSET_DMAC | I40E_INSET_SMAC |
9573 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9574 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9575 I40E_INSET_FLEX_PAYLOAD,
9579 * Flow director supports only fields defined in
9580 * union rte_eth_fdir_flow.
9582 static const uint64_t valid_fdir_inset_table[] = {
9583 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9584 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9585 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9586 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9587 I40E_INSET_IPV4_TTL,
9588 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9589 I40E_INSET_DMAC | I40E_INSET_SMAC |
9590 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9591 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9592 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9593 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9594 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9595 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9596 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9597 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9598 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9599 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9600 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9601 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9602 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9603 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9604 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9605 I40E_INSET_DMAC | I40E_INSET_SMAC |
9606 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9607 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9608 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9609 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9610 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9611 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9612 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9613 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9614 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9615 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9616 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9617 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9618 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9619 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9621 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9622 I40E_INSET_DMAC | I40E_INSET_SMAC |
9623 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9624 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9625 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9626 I40E_INSET_IPV4_TTL,
9627 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9628 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9629 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9630 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9631 I40E_INSET_IPV6_HOP_LIMIT,
9632 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9633 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9634 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9635 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9636 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9637 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9638 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9639 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9640 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9641 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9642 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9643 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9644 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9645 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9646 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9647 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9648 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9649 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9650 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9651 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9652 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9653 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9654 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9655 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9656 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9657 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9658 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9659 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9660 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9661 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9663 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9664 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9665 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9666 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9667 I40E_INSET_IPV6_HOP_LIMIT,
9668 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9669 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9670 I40E_INSET_LAST_ETHER_TYPE,
9673 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9675 if (filter == RTE_ETH_FILTER_HASH)
9676 valid = valid_hash_inset_table[pctype];
9678 valid = valid_fdir_inset_table[pctype];
9684 * Validate if the input set is allowed for a specific PCTYPE
9687 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9688 enum rte_filter_type filter, uint64_t inset)
9692 valid = i40e_get_valid_input_set(pctype, filter);
9693 if (inset & (~valid))
9699 /* default input set fields combination per pctype */
9701 i40e_get_default_input_set(uint16_t pctype)
9703 static const uint64_t default_inset_table[] = {
9704 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9705 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9706 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9707 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9708 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9709 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9710 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9711 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9712 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9713 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9714 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9715 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9716 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9717 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9718 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9719 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9720 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9721 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9722 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9723 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9725 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9726 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9727 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9728 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9729 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9730 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9731 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9732 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9733 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9734 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9735 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9736 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9737 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9738 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9739 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9740 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9741 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9742 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9743 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9744 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9745 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9746 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9748 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9749 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9750 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9751 I40E_INSET_LAST_ETHER_TYPE,
9754 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9757 return default_inset_table[pctype];
9761 * Parse the input set from index to logical bit masks
9764 i40e_parse_input_set(uint64_t *inset,
9765 enum i40e_filter_pctype pctype,
9766 enum rte_eth_input_set_field *field,
9772 static const struct {
9773 enum rte_eth_input_set_field field;
9775 } inset_convert_table[] = {
9776 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9777 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9778 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9779 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9780 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9781 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9782 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9783 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9784 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9785 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9786 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9787 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9788 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9789 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9790 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9791 I40E_INSET_IPV6_NEXT_HDR},
9792 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9793 I40E_INSET_IPV6_HOP_LIMIT},
9794 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9795 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9796 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9797 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9798 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9799 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9800 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9801 I40E_INSET_SCTP_VT},
9802 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9803 I40E_INSET_TUNNEL_DMAC},
9804 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9805 I40E_INSET_VLAN_TUNNEL},
9806 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9807 I40E_INSET_TUNNEL_ID},
9808 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9809 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9810 I40E_INSET_FLEX_PAYLOAD_W1},
9811 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9812 I40E_INSET_FLEX_PAYLOAD_W2},
9813 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9814 I40E_INSET_FLEX_PAYLOAD_W3},
9815 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9816 I40E_INSET_FLEX_PAYLOAD_W4},
9817 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9818 I40E_INSET_FLEX_PAYLOAD_W5},
9819 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9820 I40E_INSET_FLEX_PAYLOAD_W6},
9821 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9822 I40E_INSET_FLEX_PAYLOAD_W7},
9823 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9824 I40E_INSET_FLEX_PAYLOAD_W8},
9827 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9830 /* Only one item allowed for default or all */
9832 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9833 *inset = i40e_get_default_input_set(pctype);
9835 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9836 *inset = I40E_INSET_NONE;
9841 for (i = 0, *inset = 0; i < size; i++) {
9842 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9843 if (field[i] == inset_convert_table[j].field) {
9844 *inset |= inset_convert_table[j].inset;
9849 /* It contains unsupported input set, return immediately */
9850 if (j == RTE_DIM(inset_convert_table))
9858 * Translate the input set from bit masks to register aware bit masks
9862 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9872 static const struct inset_map inset_map_common[] = {
9873 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9874 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9875 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9876 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9877 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9878 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9879 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9880 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9881 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9882 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9883 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9884 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9885 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9886 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9887 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9888 {I40E_INSET_TUNNEL_DMAC,
9889 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9890 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9891 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9892 {I40E_INSET_TUNNEL_SRC_PORT,
9893 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9894 {I40E_INSET_TUNNEL_DST_PORT,
9895 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9896 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9897 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9898 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9899 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9900 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9901 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9902 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9903 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9904 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9907 /* some different registers map in x722*/
9908 static const struct inset_map inset_map_diff_x722[] = {
9909 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9910 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9911 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9912 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9915 static const struct inset_map inset_map_diff_not_x722[] = {
9916 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9917 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9918 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9919 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9925 /* Translate input set to register aware inset */
9926 if (type == I40E_MAC_X722) {
9927 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9928 if (input & inset_map_diff_x722[i].inset)
9929 val |= inset_map_diff_x722[i].inset_reg;
9932 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9933 if (input & inset_map_diff_not_x722[i].inset)
9934 val |= inset_map_diff_not_x722[i].inset_reg;
9938 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9939 if (input & inset_map_common[i].inset)
9940 val |= inset_map_common[i].inset_reg;
9947 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9950 uint64_t inset_need_mask = inset;
9952 static const struct {
9955 } inset_mask_map[] = {
9956 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9957 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9958 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9959 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9960 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9961 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9962 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9963 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9966 if (!inset || !mask || !nb_elem)
9969 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9970 /* Clear the inset bit, if no MASK is required,
9971 * for example proto + ttl
9973 if ((inset & inset_mask_map[i].inset) ==
9974 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9975 inset_need_mask &= ~inset_mask_map[i].inset;
9976 if (!inset_need_mask)
9979 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9980 if ((inset_need_mask & inset_mask_map[i].inset) ==
9981 inset_mask_map[i].inset) {
9982 if (idx >= nb_elem) {
9983 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9986 mask[idx] = inset_mask_map[i].mask;
9995 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9997 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9999 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
10001 i40e_write_rx_ctl(hw, addr, val);
10002 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
10003 (uint32_t)i40e_read_rx_ctl(hw, addr));
10007 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
10009 uint32_t reg = i40e_read_rx_ctl(hw, addr);
10010 struct rte_eth_dev *dev;
10012 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
10014 i40e_write_rx_ctl(hw, addr, val);
10015 PMD_DRV_LOG(WARNING,
10016 "i40e device %s changed global register [0x%08x]."
10017 " original: 0x%08x, new: 0x%08x",
10018 dev->device->name, addr, reg,
10019 (uint32_t)i40e_read_rx_ctl(hw, addr));
10024 i40e_filter_input_set_init(struct i40e_pf *pf)
10026 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10027 enum i40e_filter_pctype pctype;
10028 uint64_t input_set, inset_reg;
10029 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10031 uint16_t flow_type;
10033 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
10034 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
10035 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
10037 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
10040 input_set = i40e_get_default_input_set(pctype);
10042 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10043 I40E_INSET_MASK_NUM_REG);
10046 if (pf->support_multi_driver && num > 0) {
10047 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10050 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
10053 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10054 (uint32_t)(inset_reg & UINT32_MAX));
10055 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10056 (uint32_t)((inset_reg >>
10057 I40E_32_BIT_WIDTH) & UINT32_MAX));
10058 if (!pf->support_multi_driver) {
10059 i40e_check_write_global_reg(hw,
10060 I40E_GLQF_HASH_INSET(0, pctype),
10061 (uint32_t)(inset_reg & UINT32_MAX));
10062 i40e_check_write_global_reg(hw,
10063 I40E_GLQF_HASH_INSET(1, pctype),
10064 (uint32_t)((inset_reg >>
10065 I40E_32_BIT_WIDTH) & UINT32_MAX));
10067 for (i = 0; i < num; i++) {
10068 i40e_check_write_global_reg(hw,
10069 I40E_GLQF_FD_MSK(i, pctype),
10071 i40e_check_write_global_reg(hw,
10072 I40E_GLQF_HASH_MSK(i, pctype),
10075 /*clear unused mask registers of the pctype */
10076 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
10077 i40e_check_write_global_reg(hw,
10078 I40E_GLQF_FD_MSK(i, pctype),
10080 i40e_check_write_global_reg(hw,
10081 I40E_GLQF_HASH_MSK(i, pctype),
10085 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10087 I40E_WRITE_FLUSH(hw);
10089 /* store the default input set */
10090 if (!pf->support_multi_driver)
10091 pf->hash_input_set[pctype] = input_set;
10092 pf->fdir.input_set[pctype] = input_set;
10097 i40e_hash_filter_inset_select(struct i40e_hw *hw,
10098 struct rte_eth_input_set_conf *conf)
10100 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
10101 enum i40e_filter_pctype pctype;
10102 uint64_t input_set, inset_reg = 0;
10103 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10107 PMD_DRV_LOG(ERR, "Invalid pointer");
10110 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10111 conf->op != RTE_ETH_INPUT_SET_ADD) {
10112 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10116 if (pf->support_multi_driver) {
10117 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
10121 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10122 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10123 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10127 if (hw->mac.type == I40E_MAC_X722) {
10128 /* get translated pctype value in fd pctype register */
10129 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
10130 I40E_GLQF_FD_PCTYPES((int)pctype));
10133 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10136 PMD_DRV_LOG(ERR, "Failed to parse input set");
10140 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
10141 /* get inset value in register */
10142 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
10143 inset_reg <<= I40E_32_BIT_WIDTH;
10144 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
10145 input_set |= pf->hash_input_set[pctype];
10147 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10148 I40E_INSET_MASK_NUM_REG);
10152 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10154 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
10155 (uint32_t)(inset_reg & UINT32_MAX));
10156 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
10157 (uint32_t)((inset_reg >>
10158 I40E_32_BIT_WIDTH) & UINT32_MAX));
10160 for (i = 0; i < num; i++)
10161 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10163 /*clear unused mask registers of the pctype */
10164 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10165 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10167 I40E_WRITE_FLUSH(hw);
10169 pf->hash_input_set[pctype] = input_set;
10174 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
10175 struct rte_eth_input_set_conf *conf)
10177 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10178 enum i40e_filter_pctype pctype;
10179 uint64_t input_set, inset_reg = 0;
10180 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10183 if (!hw || !conf) {
10184 PMD_DRV_LOG(ERR, "Invalid pointer");
10187 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10188 conf->op != RTE_ETH_INPUT_SET_ADD) {
10189 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10193 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10195 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10196 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10200 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10203 PMD_DRV_LOG(ERR, "Failed to parse input set");
10207 /* get inset value in register */
10208 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
10209 inset_reg <<= I40E_32_BIT_WIDTH;
10210 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
10212 /* Can not change the inset reg for flex payload for fdir,
10213 * it is done by writing I40E_PRTQF_FD_FLXINSET
10214 * in i40e_set_flex_mask_on_pctype.
10216 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
10217 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
10219 input_set |= pf->fdir.input_set[pctype];
10220 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10221 I40E_INSET_MASK_NUM_REG);
10224 if (pf->support_multi_driver && num > 0) {
10225 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10229 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10231 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10232 (uint32_t)(inset_reg & UINT32_MAX));
10233 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10234 (uint32_t)((inset_reg >>
10235 I40E_32_BIT_WIDTH) & UINT32_MAX));
10237 if (!pf->support_multi_driver) {
10238 for (i = 0; i < num; i++)
10239 i40e_check_write_global_reg(hw,
10240 I40E_GLQF_FD_MSK(i, pctype),
10242 /*clear unused mask registers of the pctype */
10243 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10244 i40e_check_write_global_reg(hw,
10245 I40E_GLQF_FD_MSK(i, pctype),
10248 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10250 I40E_WRITE_FLUSH(hw);
10252 pf->fdir.input_set[pctype] = input_set;
10257 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10261 if (!hw || !info) {
10262 PMD_DRV_LOG(ERR, "Invalid pointer");
10266 switch (info->info_type) {
10267 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10268 i40e_get_symmetric_hash_enable_per_port(hw,
10269 &(info->info.enable));
10271 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10272 ret = i40e_get_hash_filter_global_config(hw,
10273 &(info->info.global_conf));
10276 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10286 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10290 if (!hw || !info) {
10291 PMD_DRV_LOG(ERR, "Invalid pointer");
10295 switch (info->info_type) {
10296 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10297 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10299 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10300 ret = i40e_set_hash_filter_global_config(hw,
10301 &(info->info.global_conf));
10303 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10304 ret = i40e_hash_filter_inset_select(hw,
10305 &(info->info.input_set_conf));
10309 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10318 /* Operations for hash function */
10320 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10321 enum rte_filter_op filter_op,
10324 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10327 switch (filter_op) {
10328 case RTE_ETH_FILTER_NOP:
10330 case RTE_ETH_FILTER_GET:
10331 ret = i40e_hash_filter_get(hw,
10332 (struct rte_eth_hash_filter_info *)arg);
10334 case RTE_ETH_FILTER_SET:
10335 ret = i40e_hash_filter_set(hw,
10336 (struct rte_eth_hash_filter_info *)arg);
10339 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10348 /* Convert ethertype filter structure */
10350 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10351 struct i40e_ethertype_filter *filter)
10353 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10354 RTE_ETHER_ADDR_LEN);
10355 filter->input.ether_type = input->ether_type;
10356 filter->flags = input->flags;
10357 filter->queue = input->queue;
10362 /* Check if there exists the ehtertype filter */
10363 struct i40e_ethertype_filter *
10364 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10365 const struct i40e_ethertype_filter_input *input)
10369 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10373 return ethertype_rule->hash_map[ret];
10376 /* Add ethertype filter in SW list */
10378 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10379 struct i40e_ethertype_filter *filter)
10381 struct i40e_ethertype_rule *rule = &pf->ethertype;
10384 ret = rte_hash_add_key(rule->hash_table, &filter->input);
10387 "Failed to insert ethertype filter"
10388 " to hash table %d!",
10392 rule->hash_map[ret] = filter;
10394 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10399 /* Delete ethertype filter in SW list */
10401 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10402 struct i40e_ethertype_filter_input *input)
10404 struct i40e_ethertype_rule *rule = &pf->ethertype;
10405 struct i40e_ethertype_filter *filter;
10408 ret = rte_hash_del_key(rule->hash_table, input);
10411 "Failed to delete ethertype filter"
10412 " to hash table %d!",
10416 filter = rule->hash_map[ret];
10417 rule->hash_map[ret] = NULL;
10419 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10426 * Configure ethertype filter, which can director packet by filtering
10427 * with mac address and ether_type or only ether_type
10430 i40e_ethertype_filter_set(struct i40e_pf *pf,
10431 struct rte_eth_ethertype_filter *filter,
10434 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10435 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10436 struct i40e_ethertype_filter *ethertype_filter, *node;
10437 struct i40e_ethertype_filter check_filter;
10438 struct i40e_control_filter_stats stats;
10439 uint16_t flags = 0;
10442 if (filter->queue >= pf->dev_data->nb_rx_queues) {
10443 PMD_DRV_LOG(ERR, "Invalid queue ID");
10446 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10447 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10449 "unsupported ether_type(0x%04x) in control packet filter.",
10450 filter->ether_type);
10453 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10454 PMD_DRV_LOG(WARNING,
10455 "filter vlan ether_type in first tag is not supported.");
10457 /* Check if there is the filter in SW list */
10458 memset(&check_filter, 0, sizeof(check_filter));
10459 i40e_ethertype_filter_convert(filter, &check_filter);
10460 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10461 &check_filter.input);
10463 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10467 if (!add && !node) {
10468 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10472 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10473 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10474 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10475 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10476 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10478 memset(&stats, 0, sizeof(stats));
10479 ret = i40e_aq_add_rem_control_packet_filter(hw,
10480 filter->mac_addr.addr_bytes,
10481 filter->ether_type, flags,
10482 pf->main_vsi->seid,
10483 filter->queue, add, &stats, NULL);
10486 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10487 ret, stats.mac_etype_used, stats.etype_used,
10488 stats.mac_etype_free, stats.etype_free);
10492 /* Add or delete a filter in SW list */
10494 ethertype_filter = rte_zmalloc("ethertype_filter",
10495 sizeof(*ethertype_filter), 0);
10496 if (ethertype_filter == NULL) {
10497 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10501 rte_memcpy(ethertype_filter, &check_filter,
10502 sizeof(check_filter));
10503 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10505 rte_free(ethertype_filter);
10507 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10514 * Handle operations for ethertype filter.
10517 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10518 enum rte_filter_op filter_op,
10521 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10524 if (filter_op == RTE_ETH_FILTER_NOP)
10528 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10533 switch (filter_op) {
10534 case RTE_ETH_FILTER_ADD:
10535 ret = i40e_ethertype_filter_set(pf,
10536 (struct rte_eth_ethertype_filter *)arg,
10539 case RTE_ETH_FILTER_DELETE:
10540 ret = i40e_ethertype_filter_set(pf,
10541 (struct rte_eth_ethertype_filter *)arg,
10545 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10553 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10554 enum rte_filter_type filter_type,
10555 enum rte_filter_op filter_op,
10563 switch (filter_type) {
10564 case RTE_ETH_FILTER_NONE:
10565 /* For global configuration */
10566 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10568 case RTE_ETH_FILTER_HASH:
10569 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10571 case RTE_ETH_FILTER_MACVLAN:
10572 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10574 case RTE_ETH_FILTER_ETHERTYPE:
10575 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10577 case RTE_ETH_FILTER_TUNNEL:
10578 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10580 case RTE_ETH_FILTER_FDIR:
10581 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10583 case RTE_ETH_FILTER_GENERIC:
10584 if (filter_op != RTE_ETH_FILTER_GET)
10586 *(const void **)arg = &i40e_flow_ops;
10589 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10599 * Check and enable Extended Tag.
10600 * Enabling Extended Tag is important for 40G performance.
10603 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10605 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10609 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10612 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10616 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10617 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10622 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10625 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10629 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10630 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10633 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10634 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10637 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10644 * As some registers wouldn't be reset unless a global hardware reset,
10645 * hardware initialization is needed to put those registers into an
10646 * expected initial state.
10649 i40e_hw_init(struct rte_eth_dev *dev)
10651 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10653 i40e_enable_extended_tag(dev);
10655 /* clear the PF Queue Filter control register */
10656 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10658 /* Disable symmetric hash per port */
10659 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10663 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10664 * however this function will return only one highest pctype index,
10665 * which is not quite correct. This is known problem of i40e driver
10666 * and needs to be fixed later.
10668 enum i40e_filter_pctype
10669 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10672 uint64_t pctype_mask;
10674 if (flow_type < I40E_FLOW_TYPE_MAX) {
10675 pctype_mask = adapter->pctypes_tbl[flow_type];
10676 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10677 if (pctype_mask & (1ULL << i))
10678 return (enum i40e_filter_pctype)i;
10681 return I40E_FILTER_PCTYPE_INVALID;
10685 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10686 enum i40e_filter_pctype pctype)
10689 uint64_t pctype_mask = 1ULL << pctype;
10691 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10693 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10697 return RTE_ETH_FLOW_UNKNOWN;
10701 * On X710, performance number is far from the expectation on recent firmware
10702 * versions; on XL710, performance number is also far from the expectation on
10703 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10704 * mode is enabled and port MAC address is equal to the packet destination MAC
10705 * address. The fix for this issue may not be integrated in the following
10706 * firmware version. So the workaround in software driver is needed. It needs
10707 * to modify the initial values of 3 internal only registers for both X710 and
10708 * XL710. Note that the values for X710 or XL710 could be different, and the
10709 * workaround can be removed when it is fixed in firmware in the future.
10712 /* For both X710 and XL710 */
10713 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10714 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10715 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10717 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10718 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10721 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10722 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10725 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10727 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10728 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10731 * GL_SWR_PM_UP_THR:
10732 * The value is not impacted from the link speed, its value is set according
10733 * to the total number of ports for a better pipe-monitor configuration.
10736 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10738 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10739 .device_id = (dev), \
10740 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10742 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10743 .device_id = (dev), \
10744 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10746 static const struct {
10747 uint16_t device_id;
10749 } swr_pm_table[] = {
10750 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10751 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10752 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10753 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10754 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10756 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10757 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10758 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10759 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10760 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10761 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10762 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10766 if (value == NULL) {
10767 PMD_DRV_LOG(ERR, "value is NULL");
10771 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10772 if (hw->device_id == swr_pm_table[i].device_id) {
10773 *value = swr_pm_table[i].val;
10775 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10777 hw->device_id, *value);
10786 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10788 enum i40e_status_code status;
10789 struct i40e_aq_get_phy_abilities_resp phy_ab;
10790 int ret = -ENOTSUP;
10793 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10797 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10800 rte_delay_us(100000);
10802 status = i40e_aq_get_phy_capabilities(hw, false,
10803 true, &phy_ab, NULL);
10811 i40e_configure_registers(struct i40e_hw *hw)
10817 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10818 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10819 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10825 for (i = 0; i < RTE_DIM(reg_table); i++) {
10826 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10827 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10829 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10830 else /* For X710/XL710/XXV710 */
10831 if (hw->aq.fw_maj_ver < 6)
10833 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10836 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10839 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10840 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10842 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10843 else /* For X710/XL710/XXV710 */
10845 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10848 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10851 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10852 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10853 "GL_SWR_PM_UP_THR value fixup",
10858 reg_table[i].val = cfg_val;
10861 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10864 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10865 reg_table[i].addr);
10868 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10869 reg_table[i].addr, reg);
10870 if (reg == reg_table[i].val)
10873 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10874 reg_table[i].val, NULL);
10877 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10878 reg_table[i].val, reg_table[i].addr);
10881 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10882 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10886 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10887 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10888 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10889 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10891 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10896 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10897 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10901 /* Configure for double VLAN RX stripping */
10902 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10903 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10904 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10905 ret = i40e_aq_debug_write_register(hw,
10906 I40E_VSI_TSR(vsi->vsi_id),
10909 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10911 return I40E_ERR_CONFIG;
10915 /* Configure for double VLAN TX insertion */
10916 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10917 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10918 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10919 ret = i40e_aq_debug_write_register(hw,
10920 I40E_VSI_L2TAGSTXVALID(
10921 vsi->vsi_id), reg, NULL);
10924 "Failed to update VSI_L2TAGSTXVALID[%d]",
10926 return I40E_ERR_CONFIG;
10934 * i40e_aq_add_mirror_rule
10935 * @hw: pointer to the hardware structure
10936 * @seid: VEB seid to add mirror rule to
10937 * @dst_id: destination vsi seid
10938 * @entries: Buffer which contains the entities to be mirrored
10939 * @count: number of entities contained in the buffer
10940 * @rule_id:the rule_id of the rule to be added
10942 * Add a mirror rule for a given veb.
10945 static enum i40e_status_code
10946 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10947 uint16_t seid, uint16_t dst_id,
10948 uint16_t rule_type, uint16_t *entries,
10949 uint16_t count, uint16_t *rule_id)
10951 struct i40e_aq_desc desc;
10952 struct i40e_aqc_add_delete_mirror_rule cmd;
10953 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10954 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10957 enum i40e_status_code status;
10959 i40e_fill_default_direct_cmd_desc(&desc,
10960 i40e_aqc_opc_add_mirror_rule);
10961 memset(&cmd, 0, sizeof(cmd));
10963 buff_len = sizeof(uint16_t) * count;
10964 desc.datalen = rte_cpu_to_le_16(buff_len);
10966 desc.flags |= rte_cpu_to_le_16(
10967 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10968 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10969 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10970 cmd.num_entries = rte_cpu_to_le_16(count);
10971 cmd.seid = rte_cpu_to_le_16(seid);
10972 cmd.destination = rte_cpu_to_le_16(dst_id);
10974 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10975 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10977 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10978 hw->aq.asq_last_status, resp->rule_id,
10979 resp->mirror_rules_used, resp->mirror_rules_free);
10980 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10986 * i40e_aq_del_mirror_rule
10987 * @hw: pointer to the hardware structure
10988 * @seid: VEB seid to add mirror rule to
10989 * @entries: Buffer which contains the entities to be mirrored
10990 * @count: number of entities contained in the buffer
10991 * @rule_id:the rule_id of the rule to be delete
10993 * Delete a mirror rule for a given veb.
10996 static enum i40e_status_code
10997 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10998 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10999 uint16_t count, uint16_t rule_id)
11001 struct i40e_aq_desc desc;
11002 struct i40e_aqc_add_delete_mirror_rule cmd;
11003 uint16_t buff_len = 0;
11004 enum i40e_status_code status;
11007 i40e_fill_default_direct_cmd_desc(&desc,
11008 i40e_aqc_opc_delete_mirror_rule);
11009 memset(&cmd, 0, sizeof(cmd));
11010 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
11011 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
11013 cmd.num_entries = count;
11014 buff_len = sizeof(uint16_t) * count;
11015 desc.datalen = rte_cpu_to_le_16(buff_len);
11016 buff = (void *)entries;
11018 /* rule id is filled in destination field for deleting mirror rule */
11019 cmd.destination = rte_cpu_to_le_16(rule_id);
11021 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11022 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11023 cmd.seid = rte_cpu_to_le_16(seid);
11025 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11026 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
11032 * i40e_mirror_rule_set
11033 * @dev: pointer to the hardware structure
11034 * @mirror_conf: mirror rule info
11035 * @sw_id: mirror rule's sw_id
11036 * @on: enable/disable
11038 * set a mirror rule.
11042 i40e_mirror_rule_set(struct rte_eth_dev *dev,
11043 struct rte_eth_mirror_conf *mirror_conf,
11044 uint8_t sw_id, uint8_t on)
11046 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11047 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11048 struct i40e_mirror_rule *it, *mirr_rule = NULL;
11049 struct i40e_mirror_rule *parent = NULL;
11050 uint16_t seid, dst_seid, rule_id;
11054 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
11056 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
11058 "mirror rule can not be configured without veb or vfs.");
11061 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
11062 PMD_DRV_LOG(ERR, "mirror table is full.");
11065 if (mirror_conf->dst_pool > pf->vf_num) {
11066 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
11067 mirror_conf->dst_pool);
11071 seid = pf->main_vsi->veb->seid;
11073 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11074 if (sw_id <= it->index) {
11080 if (mirr_rule && sw_id == mirr_rule->index) {
11082 PMD_DRV_LOG(ERR, "mirror rule exists.");
11085 ret = i40e_aq_del_mirror_rule(hw, seid,
11086 mirr_rule->rule_type,
11087 mirr_rule->entries,
11088 mirr_rule->num_entries, mirr_rule->id);
11091 "failed to remove mirror rule: ret = %d, aq_err = %d.",
11092 ret, hw->aq.asq_last_status);
11095 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11096 rte_free(mirr_rule);
11097 pf->nb_mirror_rule--;
11101 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11105 mirr_rule = rte_zmalloc("i40e_mirror_rule",
11106 sizeof(struct i40e_mirror_rule) , 0);
11108 PMD_DRV_LOG(ERR, "failed to allocate memory");
11109 return I40E_ERR_NO_MEMORY;
11111 switch (mirror_conf->rule_type) {
11112 case ETH_MIRROR_VLAN:
11113 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
11114 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
11115 mirr_rule->entries[j] =
11116 mirror_conf->vlan.vlan_id[i];
11121 PMD_DRV_LOG(ERR, "vlan is not specified.");
11122 rte_free(mirr_rule);
11125 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
11127 case ETH_MIRROR_VIRTUAL_POOL_UP:
11128 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
11129 /* check if the specified pool bit is out of range */
11130 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
11131 PMD_DRV_LOG(ERR, "pool mask is out of range.");
11132 rte_free(mirr_rule);
11135 for (i = 0, j = 0; i < pf->vf_num; i++) {
11136 if (mirror_conf->pool_mask & (1ULL << i)) {
11137 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
11141 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
11142 /* add pf vsi to entries */
11143 mirr_rule->entries[j] = pf->main_vsi_seid;
11147 PMD_DRV_LOG(ERR, "pool is not specified.");
11148 rte_free(mirr_rule);
11151 /* egress and ingress in aq commands means from switch but not port */
11152 mirr_rule->rule_type =
11153 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
11154 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
11155 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
11157 case ETH_MIRROR_UPLINK_PORT:
11158 /* egress and ingress in aq commands means from switch but not port*/
11159 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
11161 case ETH_MIRROR_DOWNLINK_PORT:
11162 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
11165 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
11166 mirror_conf->rule_type);
11167 rte_free(mirr_rule);
11171 /* If the dst_pool is equal to vf_num, consider it as PF */
11172 if (mirror_conf->dst_pool == pf->vf_num)
11173 dst_seid = pf->main_vsi_seid;
11175 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
11177 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
11178 mirr_rule->rule_type, mirr_rule->entries,
11182 "failed to add mirror rule: ret = %d, aq_err = %d.",
11183 ret, hw->aq.asq_last_status);
11184 rte_free(mirr_rule);
11188 mirr_rule->index = sw_id;
11189 mirr_rule->num_entries = j;
11190 mirr_rule->id = rule_id;
11191 mirr_rule->dst_vsi_seid = dst_seid;
11194 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
11196 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
11198 pf->nb_mirror_rule++;
11203 * i40e_mirror_rule_reset
11204 * @dev: pointer to the device
11205 * @sw_id: mirror rule's sw_id
11207 * reset a mirror rule.
11211 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
11213 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11214 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11215 struct i40e_mirror_rule *it, *mirr_rule = NULL;
11219 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
11221 seid = pf->main_vsi->veb->seid;
11223 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11224 if (sw_id == it->index) {
11230 ret = i40e_aq_del_mirror_rule(hw, seid,
11231 mirr_rule->rule_type,
11232 mirr_rule->entries,
11233 mirr_rule->num_entries, mirr_rule->id);
11236 "failed to remove mirror rule: status = %d, aq_err = %d.",
11237 ret, hw->aq.asq_last_status);
11240 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11241 rte_free(mirr_rule);
11242 pf->nb_mirror_rule--;
11244 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11251 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11253 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11254 uint64_t systim_cycles;
11256 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11257 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11260 return systim_cycles;
11264 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11266 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11267 uint64_t rx_tstamp;
11269 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11270 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11277 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11279 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11280 uint64_t tx_tstamp;
11282 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11283 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11290 i40e_start_timecounters(struct rte_eth_dev *dev)
11292 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11293 struct i40e_adapter *adapter = dev->data->dev_private;
11294 struct rte_eth_link link;
11295 uint32_t tsync_inc_l;
11296 uint32_t tsync_inc_h;
11298 /* Get current link speed. */
11299 i40e_dev_link_update(dev, 1);
11300 rte_eth_linkstatus_get(dev, &link);
11302 switch (link.link_speed) {
11303 case ETH_SPEED_NUM_40G:
11304 case ETH_SPEED_NUM_25G:
11305 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11306 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11308 case ETH_SPEED_NUM_10G:
11309 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11310 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11312 case ETH_SPEED_NUM_1G:
11313 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11314 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11321 /* Set the timesync increment value. */
11322 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11323 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11325 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11326 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11327 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11329 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11330 adapter->systime_tc.cc_shift = 0;
11331 adapter->systime_tc.nsec_mask = 0;
11333 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11334 adapter->rx_tstamp_tc.cc_shift = 0;
11335 adapter->rx_tstamp_tc.nsec_mask = 0;
11337 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11338 adapter->tx_tstamp_tc.cc_shift = 0;
11339 adapter->tx_tstamp_tc.nsec_mask = 0;
11343 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11345 struct i40e_adapter *adapter = dev->data->dev_private;
11347 adapter->systime_tc.nsec += delta;
11348 adapter->rx_tstamp_tc.nsec += delta;
11349 adapter->tx_tstamp_tc.nsec += delta;
11355 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11358 struct i40e_adapter *adapter = dev->data->dev_private;
11360 ns = rte_timespec_to_ns(ts);
11362 /* Set the timecounters to a new value. */
11363 adapter->systime_tc.nsec = ns;
11364 adapter->rx_tstamp_tc.nsec = ns;
11365 adapter->tx_tstamp_tc.nsec = ns;
11371 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11373 uint64_t ns, systime_cycles;
11374 struct i40e_adapter *adapter = dev->data->dev_private;
11376 systime_cycles = i40e_read_systime_cyclecounter(dev);
11377 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11378 *ts = rte_ns_to_timespec(ns);
11384 i40e_timesync_enable(struct rte_eth_dev *dev)
11386 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11387 uint32_t tsync_ctl_l;
11388 uint32_t tsync_ctl_h;
11390 /* Stop the timesync system time. */
11391 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11392 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11393 /* Reset the timesync system time value. */
11394 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11395 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11397 i40e_start_timecounters(dev);
11399 /* Clear timesync registers. */
11400 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11401 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11402 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11403 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11404 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11405 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11407 /* Enable timestamping of PTP packets. */
11408 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11409 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11411 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11412 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11413 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11415 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11416 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11422 i40e_timesync_disable(struct rte_eth_dev *dev)
11424 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11425 uint32_t tsync_ctl_l;
11426 uint32_t tsync_ctl_h;
11428 /* Disable timestamping of transmitted PTP packets. */
11429 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11430 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11432 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11433 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11435 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11436 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11438 /* Reset the timesync increment value. */
11439 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11440 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11446 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11447 struct timespec *timestamp, uint32_t flags)
11449 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11450 struct i40e_adapter *adapter = dev->data->dev_private;
11451 uint32_t sync_status;
11452 uint32_t index = flags & 0x03;
11453 uint64_t rx_tstamp_cycles;
11456 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11457 if ((sync_status & (1 << index)) == 0)
11460 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11461 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11462 *timestamp = rte_ns_to_timespec(ns);
11468 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11469 struct timespec *timestamp)
11471 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11472 struct i40e_adapter *adapter = dev->data->dev_private;
11473 uint32_t sync_status;
11474 uint64_t tx_tstamp_cycles;
11477 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11478 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11481 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11482 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11483 *timestamp = rte_ns_to_timespec(ns);
11489 * i40e_parse_dcb_configure - parse dcb configure from user
11490 * @dev: the device being configured
11491 * @dcb_cfg: pointer of the result of parse
11492 * @*tc_map: bit map of enabled traffic classes
11494 * Returns 0 on success, negative value on failure
11497 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11498 struct i40e_dcbx_config *dcb_cfg,
11501 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11502 uint8_t i, tc_bw, bw_lf;
11504 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11506 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11507 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11508 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11512 /* assume each tc has the same bw */
11513 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11514 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11515 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11516 /* to ensure the sum of tcbw is equal to 100 */
11517 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11518 for (i = 0; i < bw_lf; i++)
11519 dcb_cfg->etscfg.tcbwtable[i]++;
11521 /* assume each tc has the same Transmission Selection Algorithm */
11522 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11523 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11525 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11526 dcb_cfg->etscfg.prioritytable[i] =
11527 dcb_rx_conf->dcb_tc[i];
11529 /* FW needs one App to configure HW */
11530 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11531 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11532 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11533 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11535 if (dcb_rx_conf->nb_tcs == 0)
11536 *tc_map = 1; /* tc0 only */
11538 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11540 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11541 dcb_cfg->pfc.willing = 0;
11542 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11543 dcb_cfg->pfc.pfcenable = *tc_map;
11549 static enum i40e_status_code
11550 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11551 struct i40e_aqc_vsi_properties_data *info,
11552 uint8_t enabled_tcmap)
11554 enum i40e_status_code ret;
11555 int i, total_tc = 0;
11556 uint16_t qpnum_per_tc, bsf, qp_idx;
11557 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11558 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11559 uint16_t used_queues;
11561 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11562 if (ret != I40E_SUCCESS)
11565 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11566 if (enabled_tcmap & (1 << i))
11571 vsi->enabled_tc = enabled_tcmap;
11573 /* different VSI has different queues assigned */
11574 if (vsi->type == I40E_VSI_MAIN)
11575 used_queues = dev_data->nb_rx_queues -
11576 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11577 else if (vsi->type == I40E_VSI_VMDQ2)
11578 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11580 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11581 return I40E_ERR_NO_AVAILABLE_VSI;
11584 qpnum_per_tc = used_queues / total_tc;
11585 /* Number of queues per enabled TC */
11586 if (qpnum_per_tc == 0) {
11587 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11588 return I40E_ERR_INVALID_QP_ID;
11590 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11591 I40E_MAX_Q_PER_TC);
11592 bsf = rte_bsf32(qpnum_per_tc);
11595 * Configure TC and queue mapping parameters, for enabled TC,
11596 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11597 * default queue will serve it.
11600 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11601 if (vsi->enabled_tc & (1 << i)) {
11602 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11603 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11604 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11605 qp_idx += qpnum_per_tc;
11607 info->tc_mapping[i] = 0;
11610 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11611 if (vsi->type == I40E_VSI_SRIOV) {
11612 info->mapping_flags |=
11613 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11614 for (i = 0; i < vsi->nb_qps; i++)
11615 info->queue_mapping[i] =
11616 rte_cpu_to_le_16(vsi->base_queue + i);
11618 info->mapping_flags |=
11619 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11620 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11622 info->valid_sections |=
11623 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11625 return I40E_SUCCESS;
11629 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11630 * @veb: VEB to be configured
11631 * @tc_map: enabled TC bitmap
11633 * Returns 0 on success, negative value on failure
11635 static enum i40e_status_code
11636 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11638 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11639 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11640 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11641 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11642 enum i40e_status_code ret = I40E_SUCCESS;
11646 /* Check if enabled_tc is same as existing or new TCs */
11647 if (veb->enabled_tc == tc_map)
11650 /* configure tc bandwidth */
11651 memset(&veb_bw, 0, sizeof(veb_bw));
11652 veb_bw.tc_valid_bits = tc_map;
11653 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11654 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11655 if (tc_map & BIT_ULL(i))
11656 veb_bw.tc_bw_share_credits[i] = 1;
11658 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11662 "AQ command Config switch_comp BW allocation per TC failed = %d",
11663 hw->aq.asq_last_status);
11667 memset(&ets_query, 0, sizeof(ets_query));
11668 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11670 if (ret != I40E_SUCCESS) {
11672 "Failed to get switch_comp ETS configuration %u",
11673 hw->aq.asq_last_status);
11676 memset(&bw_query, 0, sizeof(bw_query));
11677 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11679 if (ret != I40E_SUCCESS) {
11681 "Failed to get switch_comp bandwidth configuration %u",
11682 hw->aq.asq_last_status);
11686 /* store and print out BW info */
11687 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11688 veb->bw_info.bw_max = ets_query.tc_bw_max;
11689 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11690 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11691 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11692 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11693 I40E_16_BIT_WIDTH);
11694 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11695 veb->bw_info.bw_ets_share_credits[i] =
11696 bw_query.tc_bw_share_credits[i];
11697 veb->bw_info.bw_ets_credits[i] =
11698 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11699 /* 4 bits per TC, 4th bit is reserved */
11700 veb->bw_info.bw_ets_max[i] =
11701 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11702 RTE_LEN2MASK(3, uint8_t));
11703 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11704 veb->bw_info.bw_ets_share_credits[i]);
11705 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11706 veb->bw_info.bw_ets_credits[i]);
11707 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11708 veb->bw_info.bw_ets_max[i]);
11711 veb->enabled_tc = tc_map;
11718 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11719 * @vsi: VSI to be configured
11720 * @tc_map: enabled TC bitmap
11722 * Returns 0 on success, negative value on failure
11724 static enum i40e_status_code
11725 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11727 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11728 struct i40e_vsi_context ctxt;
11729 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11730 enum i40e_status_code ret = I40E_SUCCESS;
11733 /* Check if enabled_tc is same as existing or new TCs */
11734 if (vsi->enabled_tc == tc_map)
11737 /* configure tc bandwidth */
11738 memset(&bw_data, 0, sizeof(bw_data));
11739 bw_data.tc_valid_bits = tc_map;
11740 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11741 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11742 if (tc_map & BIT_ULL(i))
11743 bw_data.tc_bw_credits[i] = 1;
11745 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11748 "AQ command Config VSI BW allocation per TC failed = %d",
11749 hw->aq.asq_last_status);
11752 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11753 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11755 /* Update Queue Pairs Mapping for currently enabled UPs */
11756 ctxt.seid = vsi->seid;
11757 ctxt.pf_num = hw->pf_id;
11759 ctxt.uplink_seid = vsi->uplink_seid;
11760 ctxt.info = vsi->info;
11762 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11766 /* Update the VSI after updating the VSI queue-mapping information */
11767 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11769 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11770 hw->aq.asq_last_status);
11773 /* update the local VSI info with updated queue map */
11774 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11775 sizeof(vsi->info.tc_mapping));
11776 rte_memcpy(&vsi->info.queue_mapping,
11777 &ctxt.info.queue_mapping,
11778 sizeof(vsi->info.queue_mapping));
11779 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11780 vsi->info.valid_sections = 0;
11782 /* query and update current VSI BW information */
11783 ret = i40e_vsi_get_bw_config(vsi);
11786 "Failed updating vsi bw info, err %s aq_err %s",
11787 i40e_stat_str(hw, ret),
11788 i40e_aq_str(hw, hw->aq.asq_last_status));
11792 vsi->enabled_tc = tc_map;
11799 * i40e_dcb_hw_configure - program the dcb setting to hw
11800 * @pf: pf the configuration is taken on
11801 * @new_cfg: new configuration
11802 * @tc_map: enabled TC bitmap
11804 * Returns 0 on success, negative value on failure
11806 static enum i40e_status_code
11807 i40e_dcb_hw_configure(struct i40e_pf *pf,
11808 struct i40e_dcbx_config *new_cfg,
11811 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11812 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11813 struct i40e_vsi *main_vsi = pf->main_vsi;
11814 struct i40e_vsi_list *vsi_list;
11815 enum i40e_status_code ret;
11819 /* Use the FW API if FW > v4.4*/
11820 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11821 (hw->aq.fw_maj_ver >= 5))) {
11823 "FW < v4.4, can not use FW LLDP API to configure DCB");
11824 return I40E_ERR_FIRMWARE_API_VERSION;
11827 /* Check if need reconfiguration */
11828 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11829 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11830 return I40E_SUCCESS;
11833 /* Copy the new config to the current config */
11834 *old_cfg = *new_cfg;
11835 old_cfg->etsrec = old_cfg->etscfg;
11836 ret = i40e_set_dcb_config(hw);
11838 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11839 i40e_stat_str(hw, ret),
11840 i40e_aq_str(hw, hw->aq.asq_last_status));
11843 /* set receive Arbiter to RR mode and ETS scheme by default */
11844 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11845 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11846 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11847 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11848 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11849 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11850 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11851 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11852 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11853 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11854 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11855 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11856 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11858 /* get local mib to check whether it is configured correctly */
11860 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11861 /* Get Local DCB Config */
11862 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11863 &hw->local_dcbx_config);
11865 /* if Veb is created, need to update TC of it at first */
11866 if (main_vsi->veb) {
11867 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11869 PMD_INIT_LOG(WARNING,
11870 "Failed configuring TC for VEB seid=%d",
11871 main_vsi->veb->seid);
11873 /* Update each VSI */
11874 i40e_vsi_config_tc(main_vsi, tc_map);
11875 if (main_vsi->veb) {
11876 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11877 /* Beside main VSI and VMDQ VSIs, only enable default
11878 * TC for other VSIs
11880 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11881 ret = i40e_vsi_config_tc(vsi_list->vsi,
11884 ret = i40e_vsi_config_tc(vsi_list->vsi,
11885 I40E_DEFAULT_TCMAP);
11887 PMD_INIT_LOG(WARNING,
11888 "Failed configuring TC for VSI seid=%d",
11889 vsi_list->vsi->seid);
11893 return I40E_SUCCESS;
11897 * i40e_dcb_init_configure - initial dcb config
11898 * @dev: device being configured
11899 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11901 * Returns 0 on success, negative value on failure
11904 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11906 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11907 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11910 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11911 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11915 /* DCB initialization:
11916 * Update DCB configuration from the Firmware and configure
11917 * LLDP MIB change event.
11919 if (sw_dcb == TRUE) {
11920 /* Stopping lldp is necessary for DPDK, but it will cause
11921 * DCB init failed. For i40e_init_dcb(), the prerequisite
11922 * for successful initialization of DCB is that LLDP is
11923 * enabled. So it is needed to start lldp before DCB init
11924 * and stop it after initialization.
11926 ret = i40e_aq_start_lldp(hw, true, NULL);
11927 if (ret != I40E_SUCCESS)
11928 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11930 ret = i40e_init_dcb(hw, true);
11931 /* If lldp agent is stopped, the return value from
11932 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11933 * adminq status. Otherwise, it should return success.
11935 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11936 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11937 memset(&hw->local_dcbx_config, 0,
11938 sizeof(struct i40e_dcbx_config));
11939 /* set dcb default configuration */
11940 hw->local_dcbx_config.etscfg.willing = 0;
11941 hw->local_dcbx_config.etscfg.maxtcs = 0;
11942 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11943 hw->local_dcbx_config.etscfg.tsatable[0] =
11945 /* all UPs mapping to TC0 */
11946 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11947 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11948 hw->local_dcbx_config.etsrec =
11949 hw->local_dcbx_config.etscfg;
11950 hw->local_dcbx_config.pfc.willing = 0;
11951 hw->local_dcbx_config.pfc.pfccap =
11952 I40E_MAX_TRAFFIC_CLASS;
11953 /* FW needs one App to configure HW */
11954 hw->local_dcbx_config.numapps = 1;
11955 hw->local_dcbx_config.app[0].selector =
11956 I40E_APP_SEL_ETHTYPE;
11957 hw->local_dcbx_config.app[0].priority = 3;
11958 hw->local_dcbx_config.app[0].protocolid =
11959 I40E_APP_PROTOID_FCOE;
11960 ret = i40e_set_dcb_config(hw);
11963 "default dcb config fails. err = %d, aq_err = %d.",
11964 ret, hw->aq.asq_last_status);
11969 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11970 ret, hw->aq.asq_last_status);
11974 if (i40e_need_stop_lldp(dev)) {
11975 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11976 if (ret != I40E_SUCCESS)
11977 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11980 ret = i40e_aq_start_lldp(hw, true, NULL);
11981 if (ret != I40E_SUCCESS)
11982 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11984 ret = i40e_init_dcb(hw, true);
11986 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11988 "HW doesn't support DCBX offload.");
11993 "DCBX configuration failed, err = %d, aq_err = %d.",
11994 ret, hw->aq.asq_last_status);
12002 * i40e_dcb_setup - setup dcb related config
12003 * @dev: device being configured
12005 * Returns 0 on success, negative value on failure
12008 i40e_dcb_setup(struct rte_eth_dev *dev)
12010 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12011 struct i40e_dcbx_config dcb_cfg;
12012 uint8_t tc_map = 0;
12015 if ((pf->flags & I40E_FLAG_DCB) == 0) {
12016 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
12020 if (pf->vf_num != 0)
12021 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
12023 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
12025 PMD_INIT_LOG(ERR, "invalid dcb config");
12028 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
12030 PMD_INIT_LOG(ERR, "dcb sw configure fails");
12038 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
12039 struct rte_eth_dcb_info *dcb_info)
12041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12042 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12043 struct i40e_vsi *vsi = pf->main_vsi;
12044 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
12045 uint16_t bsf, tc_mapping;
12048 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
12049 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
12051 dcb_info->nb_tcs = 1;
12052 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
12053 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
12054 for (i = 0; i < dcb_info->nb_tcs; i++)
12055 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
12057 /* get queue mapping if vmdq is disabled */
12058 if (!pf->nb_cfg_vmdq_vsi) {
12059 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12060 if (!(vsi->enabled_tc & (1 << i)))
12062 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12063 dcb_info->tc_queue.tc_rxq[j][i].base =
12064 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12065 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12066 dcb_info->tc_queue.tc_txq[j][i].base =
12067 dcb_info->tc_queue.tc_rxq[j][i].base;
12068 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12069 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12070 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12071 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12072 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12077 /* get queue mapping if vmdq is enabled */
12079 vsi = pf->vmdq[j].vsi;
12080 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12081 if (!(vsi->enabled_tc & (1 << i)))
12083 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12084 dcb_info->tc_queue.tc_rxq[j][i].base =
12085 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12086 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12087 dcb_info->tc_queue.tc_txq[j][i].base =
12088 dcb_info->tc_queue.tc_rxq[j][i].base;
12089 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12090 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12091 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12092 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12093 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12096 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
12101 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
12103 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12104 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12105 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12106 uint16_t msix_intr;
12108 msix_intr = intr_handle->intr_vec[queue_id];
12109 if (msix_intr == I40E_MISC_VEC_ID)
12110 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12111 I40E_PFINT_DYN_CTL0_INTENA_MASK |
12112 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
12113 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12116 I40E_PFINT_DYN_CTLN(msix_intr -
12117 I40E_RX_VEC_START),
12118 I40E_PFINT_DYN_CTLN_INTENA_MASK |
12119 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
12120 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12122 I40E_WRITE_FLUSH(hw);
12123 rte_intr_ack(&pci_dev->intr_handle);
12129 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
12131 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12132 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12133 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12134 uint16_t msix_intr;
12136 msix_intr = intr_handle->intr_vec[queue_id];
12137 if (msix_intr == I40E_MISC_VEC_ID)
12138 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12139 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12142 I40E_PFINT_DYN_CTLN(msix_intr -
12143 I40E_RX_VEC_START),
12144 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12145 I40E_WRITE_FLUSH(hw);
12151 * This function is used to check if the register is valid.
12152 * Below is the valid registers list for X722 only:
12156 * 0x208e00--0x209000
12157 * 0x20be00--0x20c000
12158 * 0x263c00--0x264000
12159 * 0x265c00--0x266000
12161 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
12163 if ((type != I40E_MAC_X722) &&
12164 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
12165 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
12166 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
12167 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
12168 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
12169 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
12170 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
12176 static int i40e_get_regs(struct rte_eth_dev *dev,
12177 struct rte_dev_reg_info *regs)
12179 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12180 uint32_t *ptr_data = regs->data;
12181 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
12182 const struct i40e_reg_info *reg_info;
12184 if (ptr_data == NULL) {
12185 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
12186 regs->width = sizeof(uint32_t);
12190 /* The first few registers have to be read using AQ operations */
12192 while (i40e_regs_adminq[reg_idx].name) {
12193 reg_info = &i40e_regs_adminq[reg_idx++];
12194 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12196 arr_idx2 <= reg_info->count2;
12198 reg_offset = arr_idx * reg_info->stride1 +
12199 arr_idx2 * reg_info->stride2;
12200 reg_offset += reg_info->base_addr;
12201 ptr_data[reg_offset >> 2] =
12202 i40e_read_rx_ctl(hw, reg_offset);
12206 /* The remaining registers can be read using primitives */
12208 while (i40e_regs_others[reg_idx].name) {
12209 reg_info = &i40e_regs_others[reg_idx++];
12210 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12212 arr_idx2 <= reg_info->count2;
12214 reg_offset = arr_idx * reg_info->stride1 +
12215 arr_idx2 * reg_info->stride2;
12216 reg_offset += reg_info->base_addr;
12217 if (!i40e_valid_regs(hw->mac.type, reg_offset))
12218 ptr_data[reg_offset >> 2] = 0;
12220 ptr_data[reg_offset >> 2] =
12221 I40E_READ_REG(hw, reg_offset);
12228 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
12230 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12232 /* Convert word count to byte count */
12233 return hw->nvm.sr_size << 1;
12236 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12237 struct rte_dev_eeprom_info *eeprom)
12239 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12240 uint16_t *data = eeprom->data;
12241 uint16_t offset, length, cnt_words;
12244 offset = eeprom->offset >> 1;
12245 length = eeprom->length >> 1;
12246 cnt_words = length;
12248 if (offset > hw->nvm.sr_size ||
12249 offset + length > hw->nvm.sr_size) {
12250 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12254 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12256 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12257 if (ret_code != I40E_SUCCESS || cnt_words != length) {
12258 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12265 static int i40e_get_module_info(struct rte_eth_dev *dev,
12266 struct rte_eth_dev_module_info *modinfo)
12268 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12269 uint32_t sff8472_comp = 0;
12270 uint32_t sff8472_swap = 0;
12271 uint32_t sff8636_rev = 0;
12272 i40e_status status;
12275 /* Check if firmware supports reading module EEPROM. */
12276 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12278 "Module EEPROM memory read not supported. "
12279 "Please update the NVM image.\n");
12283 status = i40e_update_link_info(hw);
12287 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12289 "Cannot read module EEPROM memory. "
12290 "No module connected.\n");
12294 type = hw->phy.link_info.module_type[0];
12297 case I40E_MODULE_TYPE_SFP:
12298 status = i40e_aq_get_phy_register(hw,
12299 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12300 I40E_I2C_EEPROM_DEV_ADDR, 1,
12301 I40E_MODULE_SFF_8472_COMP,
12302 &sff8472_comp, NULL);
12306 status = i40e_aq_get_phy_register(hw,
12307 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12308 I40E_I2C_EEPROM_DEV_ADDR, 1,
12309 I40E_MODULE_SFF_8472_SWAP,
12310 &sff8472_swap, NULL);
12314 /* Check if the module requires address swap to access
12315 * the other EEPROM memory page.
12317 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12318 PMD_DRV_LOG(WARNING,
12319 "Module address swap to access "
12320 "page 0xA2 is not supported.\n");
12321 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12322 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12323 } else if (sff8472_comp == 0x00) {
12324 /* Module is not SFF-8472 compliant */
12325 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12326 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12328 modinfo->type = RTE_ETH_MODULE_SFF_8472;
12329 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12332 case I40E_MODULE_TYPE_QSFP_PLUS:
12333 /* Read from memory page 0. */
12334 status = i40e_aq_get_phy_register(hw,
12335 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12337 I40E_MODULE_REVISION_ADDR,
12338 &sff8636_rev, NULL);
12341 /* Determine revision compliance byte */
12342 if (sff8636_rev > 0x02) {
12343 /* Module is SFF-8636 compliant */
12344 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12345 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12347 modinfo->type = RTE_ETH_MODULE_SFF_8436;
12348 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12351 case I40E_MODULE_TYPE_QSFP28:
12352 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12353 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12356 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12362 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12363 struct rte_dev_eeprom_info *info)
12365 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12366 bool is_sfp = false;
12367 i40e_status status;
12369 uint32_t value = 0;
12372 if (!info || !info->length || !info->data)
12375 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12379 for (i = 0; i < info->length; i++) {
12380 u32 offset = i + info->offset;
12381 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12383 /* Check if we need to access the other memory page */
12385 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12386 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12387 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12390 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12391 /* Compute memory page number and offset. */
12392 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12396 status = i40e_aq_get_phy_register(hw,
12397 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12398 addr, 1, offset, &value, NULL);
12401 data[i] = (uint8_t)value;
12406 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12407 struct rte_ether_addr *mac_addr)
12409 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12410 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12411 struct i40e_vsi *vsi = pf->main_vsi;
12412 struct i40e_mac_filter_info mac_filter;
12413 struct i40e_mac_filter *f;
12416 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12417 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12421 TAILQ_FOREACH(f, &vsi->mac_list, next) {
12422 if (rte_is_same_ether_addr(&pf->dev_addr,
12423 &f->mac_info.mac_addr))
12428 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12432 mac_filter = f->mac_info;
12433 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12434 if (ret != I40E_SUCCESS) {
12435 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12438 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12439 ret = i40e_vsi_add_mac(vsi, &mac_filter);
12440 if (ret != I40E_SUCCESS) {
12441 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12444 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12446 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12447 mac_addr->addr_bytes, NULL);
12448 if (ret != I40E_SUCCESS) {
12449 PMD_DRV_LOG(ERR, "Failed to change mac");
12457 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12459 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12460 struct rte_eth_dev_data *dev_data = pf->dev_data;
12461 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12464 /* check if mtu is within the allowed range */
12465 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12468 /* mtu setting is forbidden if port is start */
12469 if (dev_data->dev_started) {
12470 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12471 dev_data->port_id);
12475 if (frame_size > RTE_ETHER_MAX_LEN)
12476 dev_data->dev_conf.rxmode.offloads |=
12477 DEV_RX_OFFLOAD_JUMBO_FRAME;
12479 dev_data->dev_conf.rxmode.offloads &=
12480 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12482 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12487 /* Restore ethertype filter */
12489 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12491 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12492 struct i40e_ethertype_filter_list
12493 *ethertype_list = &pf->ethertype.ethertype_list;
12494 struct i40e_ethertype_filter *f;
12495 struct i40e_control_filter_stats stats;
12498 TAILQ_FOREACH(f, ethertype_list, rules) {
12500 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12501 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12502 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12503 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12504 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12506 memset(&stats, 0, sizeof(stats));
12507 i40e_aq_add_rem_control_packet_filter(hw,
12508 f->input.mac_addr.addr_bytes,
12509 f->input.ether_type,
12510 flags, pf->main_vsi->seid,
12511 f->queue, 1, &stats, NULL);
12513 PMD_DRV_LOG(INFO, "Ethertype filter:"
12514 " mac_etype_used = %u, etype_used = %u,"
12515 " mac_etype_free = %u, etype_free = %u",
12516 stats.mac_etype_used, stats.etype_used,
12517 stats.mac_etype_free, stats.etype_free);
12520 /* Restore tunnel filter */
12522 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12524 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12525 struct i40e_vsi *vsi;
12526 struct i40e_pf_vf *vf;
12527 struct i40e_tunnel_filter_list
12528 *tunnel_list = &pf->tunnel.tunnel_list;
12529 struct i40e_tunnel_filter *f;
12530 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12531 bool big_buffer = 0;
12533 TAILQ_FOREACH(f, tunnel_list, rules) {
12535 vsi = pf->main_vsi;
12537 vf = &pf->vfs[f->vf_id];
12540 memset(&cld_filter, 0, sizeof(cld_filter));
12541 rte_ether_addr_copy((struct rte_ether_addr *)
12542 &f->input.outer_mac,
12543 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12544 rte_ether_addr_copy((struct rte_ether_addr *)
12545 &f->input.inner_mac,
12546 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12547 cld_filter.element.inner_vlan = f->input.inner_vlan;
12548 cld_filter.element.flags = f->input.flags;
12549 cld_filter.element.tenant_id = f->input.tenant_id;
12550 cld_filter.element.queue_number = f->queue;
12551 rte_memcpy(cld_filter.general_fields,
12552 f->input.general_fields,
12553 sizeof(f->input.general_fields));
12555 if (((f->input.flags &
12556 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12557 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12559 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12560 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12562 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12563 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12567 i40e_aq_add_cloud_filters_bb(hw,
12568 vsi->seid, &cld_filter, 1);
12570 i40e_aq_add_cloud_filters(hw, vsi->seid,
12571 &cld_filter.element, 1);
12575 /* Restore RSS filter */
12577 i40e_rss_filter_restore(struct i40e_pf *pf)
12579 struct i40e_rss_conf_list *list = &pf->rss_config_list;
12580 struct i40e_rss_filter *filter;
12582 TAILQ_FOREACH(filter, list, next) {
12583 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12588 i40e_filter_restore(struct i40e_pf *pf)
12590 i40e_ethertype_filter_restore(pf);
12591 i40e_tunnel_filter_restore(pf);
12592 i40e_fdir_filter_restore(pf);
12593 i40e_rss_filter_restore(pf);
12597 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12599 if (strcmp(dev->device->driver->name, drv->driver.name))
12606 is_i40e_supported(struct rte_eth_dev *dev)
12608 return is_device_supported(dev, &rte_i40e_pmd);
12611 struct i40e_customized_pctype*
12612 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12616 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12617 if (pf->customized_pctype[i].index == index)
12618 return &pf->customized_pctype[i];
12624 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12625 uint32_t pkg_size, uint32_t proto_num,
12626 struct rte_pmd_i40e_proto_info *proto,
12627 enum rte_pmd_i40e_package_op op)
12629 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12630 uint32_t pctype_num;
12631 struct rte_pmd_i40e_ptype_info *pctype;
12632 uint32_t buff_size;
12633 struct i40e_customized_pctype *new_pctype = NULL;
12635 uint8_t pctype_value;
12640 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12641 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12642 PMD_DRV_LOG(ERR, "Unsupported operation.");
12646 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12647 (uint8_t *)&pctype_num, sizeof(pctype_num),
12648 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12650 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12654 PMD_DRV_LOG(INFO, "No new pctype added");
12658 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12659 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12661 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12664 /* get information about new pctype list */
12665 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12666 (uint8_t *)pctype, buff_size,
12667 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12669 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12674 /* Update customized pctype. */
12675 for (i = 0; i < pctype_num; i++) {
12676 pctype_value = pctype[i].ptype_id;
12677 memset(name, 0, sizeof(name));
12678 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12679 proto_id = pctype[i].protocols[j];
12680 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12682 for (n = 0; n < proto_num; n++) {
12683 if (proto[n].proto_id != proto_id)
12685 strlcat(name, proto[n].name, sizeof(name));
12686 strlcat(name, "_", sizeof(name));
12690 name[strlen(name) - 1] = '\0';
12691 PMD_DRV_LOG(INFO, "name = %s\n", name);
12692 if (!strcmp(name, "GTPC"))
12694 i40e_find_customized_pctype(pf,
12695 I40E_CUSTOMIZED_GTPC);
12696 else if (!strcmp(name, "GTPU_IPV4"))
12698 i40e_find_customized_pctype(pf,
12699 I40E_CUSTOMIZED_GTPU_IPV4);
12700 else if (!strcmp(name, "GTPU_IPV6"))
12702 i40e_find_customized_pctype(pf,
12703 I40E_CUSTOMIZED_GTPU_IPV6);
12704 else if (!strcmp(name, "GTPU"))
12706 i40e_find_customized_pctype(pf,
12707 I40E_CUSTOMIZED_GTPU);
12708 else if (!strcmp(name, "IPV4_L2TPV3"))
12710 i40e_find_customized_pctype(pf,
12711 I40E_CUSTOMIZED_IPV4_L2TPV3);
12712 else if (!strcmp(name, "IPV6_L2TPV3"))
12714 i40e_find_customized_pctype(pf,
12715 I40E_CUSTOMIZED_IPV6_L2TPV3);
12716 else if (!strcmp(name, "IPV4_ESP"))
12718 i40e_find_customized_pctype(pf,
12719 I40E_CUSTOMIZED_ESP_IPV4);
12720 else if (!strcmp(name, "IPV6_ESP"))
12722 i40e_find_customized_pctype(pf,
12723 I40E_CUSTOMIZED_ESP_IPV6);
12724 else if (!strcmp(name, "IPV4_UDP_ESP"))
12726 i40e_find_customized_pctype(pf,
12727 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12728 else if (!strcmp(name, "IPV6_UDP_ESP"))
12730 i40e_find_customized_pctype(pf,
12731 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12732 else if (!strcmp(name, "IPV4_AH"))
12734 i40e_find_customized_pctype(pf,
12735 I40E_CUSTOMIZED_AH_IPV4);
12736 else if (!strcmp(name, "IPV6_AH"))
12738 i40e_find_customized_pctype(pf,
12739 I40E_CUSTOMIZED_AH_IPV6);
12741 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12742 new_pctype->pctype = pctype_value;
12743 new_pctype->valid = true;
12745 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12746 new_pctype->valid = false;
12756 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12757 uint32_t pkg_size, uint32_t proto_num,
12758 struct rte_pmd_i40e_proto_info *proto,
12759 enum rte_pmd_i40e_package_op op)
12761 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12762 uint16_t port_id = dev->data->port_id;
12763 uint32_t ptype_num;
12764 struct rte_pmd_i40e_ptype_info *ptype;
12765 uint32_t buff_size;
12767 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12772 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12773 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12774 PMD_DRV_LOG(ERR, "Unsupported operation.");
12778 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12779 rte_pmd_i40e_ptype_mapping_reset(port_id);
12783 /* get information about new ptype num */
12784 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12785 (uint8_t *)&ptype_num, sizeof(ptype_num),
12786 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12788 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12792 PMD_DRV_LOG(INFO, "No new ptype added");
12796 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12797 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12799 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12803 /* get information about new ptype list */
12804 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12805 (uint8_t *)ptype, buff_size,
12806 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12808 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12813 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12814 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12815 if (!ptype_mapping) {
12816 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12821 /* Update ptype mapping table. */
12822 for (i = 0; i < ptype_num; i++) {
12823 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12824 ptype_mapping[i].sw_ptype = 0;
12826 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12827 proto_id = ptype[i].protocols[j];
12828 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12830 for (n = 0; n < proto_num; n++) {
12831 if (proto[n].proto_id != proto_id)
12833 memset(name, 0, sizeof(name));
12834 strcpy(name, proto[n].name);
12835 PMD_DRV_LOG(INFO, "name = %s\n", name);
12836 if (!strncasecmp(name, "PPPOE", 5))
12837 ptype_mapping[i].sw_ptype |=
12838 RTE_PTYPE_L2_ETHER_PPPOE;
12839 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12841 ptype_mapping[i].sw_ptype |=
12842 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12843 ptype_mapping[i].sw_ptype |=
12845 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12847 ptype_mapping[i].sw_ptype |=
12848 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12849 ptype_mapping[i].sw_ptype |=
12850 RTE_PTYPE_INNER_L4_FRAG;
12851 } else if (!strncasecmp(name, "OIPV4", 5)) {
12852 ptype_mapping[i].sw_ptype |=
12853 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12855 } else if (!strncasecmp(name, "IPV4", 4) &&
12857 ptype_mapping[i].sw_ptype |=
12858 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12859 else if (!strncasecmp(name, "IPV4", 4) &&
12861 ptype_mapping[i].sw_ptype |=
12862 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12863 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12865 ptype_mapping[i].sw_ptype |=
12866 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12867 ptype_mapping[i].sw_ptype |=
12869 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12871 ptype_mapping[i].sw_ptype |=
12872 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12873 ptype_mapping[i].sw_ptype |=
12874 RTE_PTYPE_INNER_L4_FRAG;
12875 } else if (!strncasecmp(name, "OIPV6", 5)) {
12876 ptype_mapping[i].sw_ptype |=
12877 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12879 } else if (!strncasecmp(name, "IPV6", 4) &&
12881 ptype_mapping[i].sw_ptype |=
12882 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12883 else if (!strncasecmp(name, "IPV6", 4) &&
12885 ptype_mapping[i].sw_ptype |=
12886 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12887 else if (!strncasecmp(name, "UDP", 3) &&
12889 ptype_mapping[i].sw_ptype |=
12891 else if (!strncasecmp(name, "UDP", 3) &&
12893 ptype_mapping[i].sw_ptype |=
12894 RTE_PTYPE_INNER_L4_UDP;
12895 else if (!strncasecmp(name, "TCP", 3) &&
12897 ptype_mapping[i].sw_ptype |=
12899 else if (!strncasecmp(name, "TCP", 3) &&
12901 ptype_mapping[i].sw_ptype |=
12902 RTE_PTYPE_INNER_L4_TCP;
12903 else if (!strncasecmp(name, "SCTP", 4) &&
12905 ptype_mapping[i].sw_ptype |=
12907 else if (!strncasecmp(name, "SCTP", 4) &&
12909 ptype_mapping[i].sw_ptype |=
12910 RTE_PTYPE_INNER_L4_SCTP;
12911 else if ((!strncasecmp(name, "ICMP", 4) ||
12912 !strncasecmp(name, "ICMPV6", 6)) &&
12914 ptype_mapping[i].sw_ptype |=
12916 else if ((!strncasecmp(name, "ICMP", 4) ||
12917 !strncasecmp(name, "ICMPV6", 6)) &&
12919 ptype_mapping[i].sw_ptype |=
12920 RTE_PTYPE_INNER_L4_ICMP;
12921 else if (!strncasecmp(name, "GTPC", 4)) {
12922 ptype_mapping[i].sw_ptype |=
12923 RTE_PTYPE_TUNNEL_GTPC;
12925 } else if (!strncasecmp(name, "GTPU", 4)) {
12926 ptype_mapping[i].sw_ptype |=
12927 RTE_PTYPE_TUNNEL_GTPU;
12929 } else if (!strncasecmp(name, "ESP", 3)) {
12930 ptype_mapping[i].sw_ptype |=
12931 RTE_PTYPE_TUNNEL_ESP;
12933 } else if (!strncasecmp(name, "GRENAT", 6)) {
12934 ptype_mapping[i].sw_ptype |=
12935 RTE_PTYPE_TUNNEL_GRENAT;
12937 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12938 !strncasecmp(name, "L2TPV2", 6) ||
12939 !strncasecmp(name, "L2TPV3", 6)) {
12940 ptype_mapping[i].sw_ptype |=
12941 RTE_PTYPE_TUNNEL_L2TP;
12950 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12953 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12955 rte_free(ptype_mapping);
12961 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12962 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12964 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12965 uint32_t proto_num;
12966 struct rte_pmd_i40e_proto_info *proto;
12967 uint32_t buff_size;
12971 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12972 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12973 PMD_DRV_LOG(ERR, "Unsupported operation.");
12977 /* get information about protocol number */
12978 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12979 (uint8_t *)&proto_num, sizeof(proto_num),
12980 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12982 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12986 PMD_DRV_LOG(INFO, "No new protocol added");
12990 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12991 proto = rte_zmalloc("new_proto", buff_size, 0);
12993 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12997 /* get information about protocol list */
12998 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12999 (uint8_t *)proto, buff_size,
13000 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
13002 PMD_DRV_LOG(ERR, "Failed to get protocol list");
13007 /* Check if GTP is supported. */
13008 for (i = 0; i < proto_num; i++) {
13009 if (!strncmp(proto[i].name, "GTP", 3)) {
13010 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13011 pf->gtp_support = true;
13013 pf->gtp_support = false;
13018 /* Check if ESP is supported. */
13019 for (i = 0; i < proto_num; i++) {
13020 if (!strncmp(proto[i].name, "ESP", 3)) {
13021 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13022 pf->esp_support = true;
13024 pf->esp_support = false;
13029 /* Update customized pctype info */
13030 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
13031 proto_num, proto, op);
13033 PMD_DRV_LOG(INFO, "No pctype is updated.");
13035 /* Update customized ptype info */
13036 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
13037 proto_num, proto, op);
13039 PMD_DRV_LOG(INFO, "No ptype is updated.");
13044 /* Create a QinQ cloud filter
13046 * The Fortville NIC has limited resources for tunnel filters,
13047 * so we can only reuse existing filters.
13049 * In step 1 we define which Field Vector fields can be used for
13051 * As we do not have the inner tag defined as a field,
13052 * we have to define it first, by reusing one of L1 entries.
13054 * In step 2 we are replacing one of existing filter types with
13055 * a new one for QinQ.
13056 * As we reusing L1 and replacing L2, some of the default filter
13057 * types will disappear,which depends on L1 and L2 entries we reuse.
13059 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
13061 * 1. Create L1 filter of outer vlan (12b) which will be in use
13062 * later when we define the cloud filter.
13063 * a. Valid_flags.replace_cloud = 0
13064 * b. Old_filter = 10 (Stag_Inner_Vlan)
13065 * c. New_filter = 0x10
13066 * d. TR bit = 0xff (optional, not used here)
13067 * e. Buffer – 2 entries:
13068 * i. Byte 0 = 8 (outer vlan FV index).
13070 * Byte 2-3 = 0x0fff
13071 * ii. Byte 0 = 37 (inner vlan FV index).
13073 * Byte 2-3 = 0x0fff
13076 * 2. Create cloud filter using two L1 filters entries: stag and
13077 * new filter(outer vlan+ inner vlan)
13078 * a. Valid_flags.replace_cloud = 1
13079 * b. Old_filter = 1 (instead of outer IP)
13080 * c. New_filter = 0x10
13081 * d. Buffer – 2 entries:
13082 * i. Byte 0 = 0x80 | 7 (valid | Stag).
13083 * Byte 1-3 = 0 (rsv)
13084 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
13085 * Byte 9-11 = 0 (rsv)
13088 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
13090 int ret = -ENOTSUP;
13091 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
13092 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
13093 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13094 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
13096 if (pf->support_multi_driver) {
13097 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
13102 memset(&filter_replace, 0,
13103 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13104 memset(&filter_replace_buf, 0,
13105 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13107 /* create L1 filter */
13108 filter_replace.old_filter_type =
13109 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
13110 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13111 filter_replace.tr_bit = 0;
13113 /* Prepare the buffer, 2 entries */
13114 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
13115 filter_replace_buf.data[0] |=
13116 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13117 /* Field Vector 12b mask */
13118 filter_replace_buf.data[2] = 0xff;
13119 filter_replace_buf.data[3] = 0x0f;
13120 filter_replace_buf.data[4] =
13121 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
13122 filter_replace_buf.data[4] |=
13123 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13124 /* Field Vector 12b mask */
13125 filter_replace_buf.data[6] = 0xff;
13126 filter_replace_buf.data[7] = 0x0f;
13127 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13128 &filter_replace_buf);
13129 if (ret != I40E_SUCCESS)
13132 if (filter_replace.old_filter_type !=
13133 filter_replace.new_filter_type)
13134 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
13135 " original: 0x%x, new: 0x%x",
13137 filter_replace.old_filter_type,
13138 filter_replace.new_filter_type);
13140 /* Apply the second L2 cloud filter */
13141 memset(&filter_replace, 0,
13142 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13143 memset(&filter_replace_buf, 0,
13144 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13146 /* create L2 filter, input for L2 filter will be L1 filter */
13147 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
13148 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
13149 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13151 /* Prepare the buffer, 2 entries */
13152 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
13153 filter_replace_buf.data[0] |=
13154 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13155 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13156 filter_replace_buf.data[4] |=
13157 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13158 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13159 &filter_replace_buf);
13160 if (!ret && (filter_replace.old_filter_type !=
13161 filter_replace.new_filter_type))
13162 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
13163 " original: 0x%x, new: 0x%x",
13165 filter_replace.old_filter_type,
13166 filter_replace.new_filter_type);
13172 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
13173 const struct rte_flow_action_rss *in)
13175 if (in->key_len > RTE_DIM(out->key) ||
13176 in->queue_num > RTE_DIM(out->queue))
13178 if (!in->key && in->key_len)
13180 out->conf = (struct rte_flow_action_rss){
13182 .level = in->level,
13183 .types = in->types,
13184 .key_len = in->key_len,
13185 .queue_num = in->queue_num,
13186 .queue = memcpy(out->queue, in->queue,
13187 sizeof(*in->queue) * in->queue_num),
13190 out->conf.key = memcpy(out->key, in->key, in->key_len);
13194 /* Write HENA register to enable hash */
13196 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
13198 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13199 uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
13203 ret = i40e_set_rss_key(pf->main_vsi, key,
13204 rss_conf->conf.key_len);
13208 hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
13209 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
13210 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
13211 I40E_WRITE_FLUSH(hw);
13216 /* Configure hash input set */
13218 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
13220 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13221 struct rte_eth_input_set_conf conf;
13226 static const struct {
13228 enum rte_eth_input_set_field field;
13229 } inset_match_table[] = {
13230 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
13231 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13232 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
13233 RTE_ETH_INPUT_SET_L3_DST_IP4},
13234 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
13235 RTE_ETH_INPUT_SET_UNKNOWN},
13236 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13237 RTE_ETH_INPUT_SET_UNKNOWN},
13239 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13240 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13241 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13242 RTE_ETH_INPUT_SET_L3_DST_IP4},
13243 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13244 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13245 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13246 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13248 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13249 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13250 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13251 RTE_ETH_INPUT_SET_L3_DST_IP4},
13252 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13253 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13254 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13255 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13257 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13258 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13259 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13260 RTE_ETH_INPUT_SET_L3_DST_IP4},
13261 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13262 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13263 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13264 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13266 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13267 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13268 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13269 RTE_ETH_INPUT_SET_L3_DST_IP4},
13270 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13271 RTE_ETH_INPUT_SET_UNKNOWN},
13272 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13273 RTE_ETH_INPUT_SET_UNKNOWN},
13275 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13276 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13277 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13278 RTE_ETH_INPUT_SET_L3_DST_IP6},
13279 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13280 RTE_ETH_INPUT_SET_UNKNOWN},
13281 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13282 RTE_ETH_INPUT_SET_UNKNOWN},
13284 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13285 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13286 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13287 RTE_ETH_INPUT_SET_L3_DST_IP6},
13288 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13289 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13290 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13291 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13293 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13294 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13295 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13296 RTE_ETH_INPUT_SET_L3_DST_IP6},
13297 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13298 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13299 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13300 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13302 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13303 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13304 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13305 RTE_ETH_INPUT_SET_L3_DST_IP6},
13306 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13307 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13308 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13309 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13311 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13312 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13313 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13314 RTE_ETH_INPUT_SET_L3_DST_IP6},
13315 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13316 RTE_ETH_INPUT_SET_UNKNOWN},
13317 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13318 RTE_ETH_INPUT_SET_UNKNOWN},
13321 mask0 = types & pf->adapter->flow_types_mask;
13322 conf.op = RTE_ETH_INPUT_SET_SELECT;
13323 conf.inset_size = 0;
13324 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13325 if (mask0 & (1ULL << i)) {
13326 conf.flow_type = i;
13331 for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13332 if ((types & inset_match_table[j].type) ==
13333 inset_match_table[j].type) {
13334 if (inset_match_table[j].field ==
13335 RTE_ETH_INPUT_SET_UNKNOWN)
13338 conf.field[conf.inset_size] =
13339 inset_match_table[j].field;
13344 if (conf.inset_size) {
13345 ret = i40e_hash_filter_inset_select(hw, &conf);
13353 /* Look up the conflicted rule then mark it as invalid */
13355 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13356 struct i40e_rte_flow_rss_conf *conf)
13358 struct i40e_rss_filter *rss_item;
13359 uint64_t rss_inset;
13361 /* Clear input set bits before comparing the pctype */
13362 rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13363 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13365 /* Look up the conflicted rule then mark it as invalid */
13366 TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13367 if (!rss_item->rss_filter_info.valid)
13370 if (conf->conf.queue_num &&
13371 rss_item->rss_filter_info.conf.queue_num)
13372 rss_item->rss_filter_info.valid = false;
13374 if (conf->conf.types &&
13375 (rss_item->rss_filter_info.conf.types &
13377 (conf->conf.types & rss_inset))
13378 rss_item->rss_filter_info.valid = false;
13380 if (conf->conf.func ==
13381 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13382 rss_item->rss_filter_info.conf.func ==
13383 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13384 rss_item->rss_filter_info.valid = false;
13388 /* Configure RSS hash function */
13390 i40e_rss_config_hash_function(struct i40e_pf *pf,
13391 struct i40e_rte_flow_rss_conf *conf)
13393 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13398 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13399 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13400 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13401 PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13402 I40E_WRITE_FLUSH(hw);
13403 i40e_rss_mark_invalid_rule(pf, conf);
13407 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13409 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13410 I40E_WRITE_FLUSH(hw);
13411 i40e_rss_mark_invalid_rule(pf, conf);
13412 } else if (conf->conf.func ==
13413 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13414 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13416 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13417 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13418 if (mask0 & (1UL << i))
13422 if (i == UINT64_BIT)
13425 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13426 j < I40E_FILTER_PCTYPE_MAX; j++) {
13427 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13428 i40e_write_global_rx_ctl(hw,
13430 I40E_GLQF_HSYM_SYMH_ENA_MASK);
13437 /* Enable RSS according to the configuration */
13439 i40e_rss_enable_hash(struct i40e_pf *pf,
13440 struct i40e_rte_flow_rss_conf *conf)
13442 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13443 struct i40e_rte_flow_rss_conf rss_conf;
13445 if (!(conf->conf.types & pf->adapter->flow_types_mask))
13448 memset(&rss_conf, 0, sizeof(rss_conf));
13449 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13451 /* Configure hash input set */
13452 if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13455 if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13456 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13457 /* Random default keys */
13458 static uint32_t rss_key_default[] = {0x6b793944,
13459 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13460 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13461 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13463 rss_conf.conf.key = (uint8_t *)rss_key_default;
13464 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13467 "No valid RSS key config for i40e, using default\n");
13470 rss_conf.conf.types |= rss_info->conf.types;
13471 i40e_rss_hash_set(pf, &rss_conf);
13473 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13474 i40e_rss_config_hash_function(pf, conf);
13476 i40e_rss_mark_invalid_rule(pf, conf);
13481 /* Configure RSS queue region */
13483 i40e_rss_config_queue_region(struct i40e_pf *pf,
13484 struct i40e_rte_flow_rss_conf *conf)
13486 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13491 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13492 * It's necessary to calculate the actual PF queues that are configured.
13494 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13495 num = i40e_pf_calc_configured_queues_num(pf);
13497 num = pf->dev_data->nb_rx_queues;
13499 num = RTE_MIN(num, conf->conf.queue_num);
13500 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13505 "No PF queues are configured to enable RSS for port %u",
13506 pf->dev_data->port_id);
13510 /* Fill in redirection table */
13511 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13514 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13515 hw->func_caps.rss_table_entry_width) - 1));
13517 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13520 i40e_rss_mark_invalid_rule(pf, conf);
13525 /* Configure RSS hash function to default */
13527 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13528 struct i40e_rte_flow_rss_conf *conf)
13530 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13535 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13536 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13537 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13539 "Hash function already set to Toeplitz");
13540 I40E_WRITE_FLUSH(hw);
13544 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13546 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13547 I40E_WRITE_FLUSH(hw);
13548 } else if (conf->conf.func ==
13549 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13550 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13552 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13553 if (mask0 & (1UL << i))
13557 if (i == UINT64_BIT)
13560 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13561 j < I40E_FILTER_PCTYPE_MAX; j++) {
13562 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13563 i40e_write_global_rx_ctl(hw,
13572 /* Disable RSS hash and configure default input set */
13574 i40e_rss_disable_hash(struct i40e_pf *pf,
13575 struct i40e_rte_flow_rss_conf *conf)
13577 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13578 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13579 struct i40e_rte_flow_rss_conf rss_conf;
13582 memset(&rss_conf, 0, sizeof(rss_conf));
13583 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13585 /* Disable RSS hash */
13586 rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13587 i40e_rss_hash_set(pf, &rss_conf);
13589 for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13590 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13591 !(conf->conf.types & (1ULL << i)))
13594 /* Configure default input set */
13595 struct rte_eth_input_set_conf input_conf = {
13596 .op = RTE_ETH_INPUT_SET_SELECT,
13600 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13601 i40e_hash_filter_inset_select(hw, &input_conf);
13604 rss_info->conf.types = rss_conf.conf.types;
13606 i40e_rss_clear_hash_function(pf, conf);
13611 /* Configure RSS queue region to default */
13613 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13615 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13616 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13617 uint16_t queue[I40E_MAX_Q_PER_TC];
13618 uint32_t num_rxq, i;
13622 num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13624 for (j = 0; j < num_rxq; j++)
13627 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13628 * It's necessary to calculate the actual PF queues that are configured.
13630 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13631 num = i40e_pf_calc_configured_queues_num(pf);
13633 num = pf->dev_data->nb_rx_queues;
13635 num = RTE_MIN(num, num_rxq);
13636 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13641 "No PF queues are configured to enable RSS for port %u",
13642 pf->dev_data->port_id);
13646 /* Fill in redirection table */
13647 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13650 lut = (lut << 8) | (queue[j] & ((0x1 <<
13651 hw->func_caps.rss_table_entry_width) - 1));
13653 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13656 rss_info->conf.queue_num = 0;
13657 memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13663 i40e_config_rss_filter(struct i40e_pf *pf,
13664 struct i40e_rte_flow_rss_conf *conf, bool add)
13666 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13667 struct rte_flow_action_rss update_conf = rss_info->conf;
13671 if (conf->conf.queue_num) {
13672 /* Configure RSS queue region */
13673 ret = i40e_rss_config_queue_region(pf, conf);
13677 update_conf.queue_num = conf->conf.queue_num;
13678 update_conf.queue = conf->conf.queue;
13679 } else if (conf->conf.func ==
13680 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13681 /* Configure hash function */
13682 ret = i40e_rss_config_hash_function(pf, conf);
13686 update_conf.func = conf->conf.func;
13688 /* Configure hash enable and input set */
13689 ret = i40e_rss_enable_hash(pf, conf);
13693 update_conf.types |= conf->conf.types;
13694 update_conf.key = conf->conf.key;
13695 update_conf.key_len = conf->conf.key_len;
13698 /* Update RSS info in pf */
13699 if (i40e_rss_conf_init(rss_info, &update_conf))
13705 if (conf->conf.queue_num)
13706 i40e_rss_clear_queue_region(pf);
13707 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13708 i40e_rss_clear_hash_function(pf, conf);
13710 i40e_rss_disable_hash(pf, conf);
13716 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13717 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13718 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13719 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13721 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13722 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13724 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13725 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13728 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13729 ETH_I40E_FLOATING_VEB_ARG "=1"
13730 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13731 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13732 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13733 ETH_I40E_USE_LATEST_VEC "=0|1");