4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memzone.h>
49 #include <rte_malloc.h>
50 #include <rte_memcpy.h>
51 #include <rte_alarm.h>
53 #include <rte_eth_ctrl.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define I40E_CLEAR_PXE_WAIT_MS 200
68 /* Maximun number of capability elements */
69 #define I40E_MAX_CAP_ELE_NUM 128
71 /* Wait count and inteval */
72 #define I40E_CHK_Q_ENA_COUNT 1000
73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
75 /* Maximun number of VSI */
76 #define I40E_MAX_NUM_VSIS (384UL)
78 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
80 /* Flow control default timer */
81 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
83 /* Flow control default high water */
84 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
86 /* Flow control default low water */
87 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
89 /* Flow control enable fwd bit */
90 #define I40E_PRTMAC_FWD_CTRL 0x00000001
92 /* Receive Packet Buffer size */
93 #define I40E_RXPBSIZE (968 * 1024)
96 #define I40E_KILOSHIFT 10
98 /* Receive Average Packet Size in Byte*/
99 #define I40E_PACKET_AVERAGE_SIZE 128
101 /* Mask of PF interrupt causes */
102 #define I40E_PFINT_ICR0_ENA_MASK ( \
103 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
104 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
105 I40E_PFINT_ICR0_ENA_GRST_MASK | \
106 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
107 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
109 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
111 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
112 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
114 #define I40E_FLOW_TYPES ( \
115 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
116 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
117 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
118 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
125 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
127 /* Additional timesync values. */
128 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
129 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
130 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
131 #define I40E_PRTTSYN_TSYNENA 0x80000000
132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
133 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
135 #define I40E_MAX_PERCENT 100
136 #define I40E_DEFAULT_DCB_APP_NUM 1
137 #define I40E_DEFAULT_DCB_APP_PRIO 3
139 #define I40E_INSET_NONE 0x00000000000000000ULL
142 #define I40E_INSET_DMAC 0x0000000000000001ULL
143 #define I40E_INSET_SMAC 0x0000000000000002ULL
144 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
145 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
146 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
149 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
150 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
151 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
152 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
153 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
154 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
155 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
157 /* bit 16 ~ bit 31 */
158 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
159 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
160 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
161 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
162 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
163 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
164 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
165 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
167 /* bit 32 ~ bit 47, tunnel fields */
168 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
169 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
170 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
171 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
172 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
173 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
175 /* bit 48 ~ bit 55 */
176 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
178 /* bit 56 ~ bit 63, Flex Payload */
179 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
180 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
181 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
182 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD \
188 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
189 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
190 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
191 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
194 * Below are values for writing un-exposed registers suggested
197 /* Destination MAC address */
198 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
199 /* Source MAC address */
200 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
201 /* VLAN tag in the outer L2 header */
202 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0080000000000000ULL
203 /* VLAN tag in the inner L2 header */
204 #define I40E_REG_INSET_L2_INNER_VLAN 0x0100000000000000ULL
205 /* Source IPv4 address */
206 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
207 /* Destination IPv4 address */
208 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
209 /* IPv4 Type of Service (TOS) */
210 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
212 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
213 /* Source IPv6 address */
214 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
215 /* Destination IPv6 address */
216 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
217 /* IPv6 Traffic Class (TC) */
218 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
219 /* IPv6 Next Header */
220 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
222 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
223 /* Destination L4 port */
224 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
225 /* SCTP verification tag */
226 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
227 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
228 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
229 /* Source port of tunneling UDP */
230 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
231 /* Destination port of tunneling UDP */
232 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
233 /* UDP Tunneling ID, NVGRE/GRE key */
234 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
235 /* Last ether type */
236 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
237 /* Tunneling outer destination IPv4 address */
238 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
239 /* Tunneling outer destination IPv6 address */
240 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
241 /* 1st word of flex payload */
242 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
243 /* 2nd word of flex payload */
244 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
245 /* 3rd word of flex payload */
246 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
247 /* 4th word of flex payload */
248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
249 /* 5th word of flex payload */
250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
251 /* 6th word of flex payload */
252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
253 /* 7th word of flex payload */
254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
255 /* 8th word of flex payload */
256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
258 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
260 #define I40E_TRANSLATE_INSET 0
261 #define I40E_TRANSLATE_REG 1
263 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
264 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
265 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
266 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
268 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
269 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
270 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
271 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
273 /* PCI offset for querying capability */
274 #define PCI_DEV_CAP_REG 0xA4
275 /* PCI offset for enabling/disabling Extended Tag */
276 #define PCI_DEV_CTRL_REG 0xA8
277 /* Bit mask of Extended Tag capability */
278 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
279 /* Bit shift of Extended Tag enable/disable */
280 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
281 /* Bit mask of Extended Tag enable/disable */
282 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
284 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
285 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
286 static int i40e_dev_configure(struct rte_eth_dev *dev);
287 static int i40e_dev_start(struct rte_eth_dev *dev);
288 static void i40e_dev_stop(struct rte_eth_dev *dev);
289 static void i40e_dev_close(struct rte_eth_dev *dev);
290 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
291 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
292 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
293 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
294 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
295 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
296 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
297 struct rte_eth_stats *stats);
298 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
299 struct rte_eth_xstats *xstats, unsigned n);
300 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
301 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
305 static void i40e_dev_info_get(struct rte_eth_dev *dev,
306 struct rte_eth_dev_info *dev_info);
307 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
310 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
311 enum rte_vlan_type vlan_type,
313 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
314 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
317 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
318 static int i40e_dev_led_on(struct rte_eth_dev *dev);
319 static int i40e_dev_led_off(struct rte_eth_dev *dev);
320 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
321 struct rte_eth_fc_conf *fc_conf);
322 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
323 struct rte_eth_fc_conf *fc_conf);
324 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
325 struct rte_eth_pfc_conf *pfc_conf);
326 static void i40e_macaddr_add(struct rte_eth_dev *dev,
327 struct ether_addr *mac_addr,
330 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
331 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
332 struct rte_eth_rss_reta_entry64 *reta_conf,
334 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
335 struct rte_eth_rss_reta_entry64 *reta_conf,
338 static int i40e_get_cap(struct i40e_hw *hw);
339 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
340 static int i40e_pf_setup(struct i40e_pf *pf);
341 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
342 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
343 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
344 static int i40e_dcb_setup(struct rte_eth_dev *dev);
345 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
346 bool offset_loaded, uint64_t *offset, uint64_t *stat);
347 static void i40e_stat_update_48(struct i40e_hw *hw,
353 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
354 static void i40e_dev_interrupt_handler(
355 __rte_unused struct rte_intr_handle *handle, void *param);
356 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
357 uint32_t base, uint32_t num);
358 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
359 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
361 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
363 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
364 static int i40e_veb_release(struct i40e_veb *veb);
365 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
366 struct i40e_vsi *vsi);
367 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
368 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
369 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
370 struct i40e_macvlan_filter *mv_f,
372 struct ether_addr *addr);
373 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
374 struct i40e_macvlan_filter *mv_f,
377 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
378 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
379 struct rte_eth_rss_conf *rss_conf);
380 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
381 struct rte_eth_rss_conf *rss_conf);
382 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
383 struct rte_eth_udp_tunnel *udp_tunnel);
384 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
385 struct rte_eth_udp_tunnel *udp_tunnel);
386 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
387 struct rte_eth_ethertype_filter *filter,
389 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
390 enum rte_filter_op filter_op,
392 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
393 enum rte_filter_type filter_type,
394 enum rte_filter_op filter_op,
396 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
397 struct rte_eth_dcb_info *dcb_info);
398 static void i40e_configure_registers(struct i40e_hw *hw);
399 static void i40e_hw_init(struct rte_eth_dev *dev);
400 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
401 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
402 struct rte_eth_mirror_conf *mirror_conf,
403 uint8_t sw_id, uint8_t on);
404 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
406 static int i40e_timesync_enable(struct rte_eth_dev *dev);
407 static int i40e_timesync_disable(struct rte_eth_dev *dev);
408 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
409 struct timespec *timestamp,
411 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
412 struct timespec *timestamp);
413 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
415 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
417 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
418 struct timespec *timestamp);
419 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
420 const struct timespec *timestamp);
422 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
424 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
427 static int i40e_get_reg_length(struct rte_eth_dev *dev);
429 static int i40e_get_regs(struct rte_eth_dev *dev,
430 struct rte_dev_reg_info *regs);
432 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
434 static int i40e_get_eeprom(struct rte_eth_dev *dev,
435 struct rte_dev_eeprom_info *eeprom);
437 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
438 struct ether_addr *mac_addr);
440 static const struct rte_pci_id pci_id_i40e_map[] = {
441 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
442 #include "rte_pci_dev_ids.h"
443 { .vendor_id = 0, /* sentinel */ },
446 static const struct eth_dev_ops i40e_eth_dev_ops = {
447 .dev_configure = i40e_dev_configure,
448 .dev_start = i40e_dev_start,
449 .dev_stop = i40e_dev_stop,
450 .dev_close = i40e_dev_close,
451 .promiscuous_enable = i40e_dev_promiscuous_enable,
452 .promiscuous_disable = i40e_dev_promiscuous_disable,
453 .allmulticast_enable = i40e_dev_allmulticast_enable,
454 .allmulticast_disable = i40e_dev_allmulticast_disable,
455 .dev_set_link_up = i40e_dev_set_link_up,
456 .dev_set_link_down = i40e_dev_set_link_down,
457 .link_update = i40e_dev_link_update,
458 .stats_get = i40e_dev_stats_get,
459 .xstats_get = i40e_dev_xstats_get,
460 .stats_reset = i40e_dev_stats_reset,
461 .xstats_reset = i40e_dev_stats_reset,
462 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
463 .dev_infos_get = i40e_dev_info_get,
464 .vlan_filter_set = i40e_vlan_filter_set,
465 .vlan_tpid_set = i40e_vlan_tpid_set,
466 .vlan_offload_set = i40e_vlan_offload_set,
467 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
468 .vlan_pvid_set = i40e_vlan_pvid_set,
469 .rx_queue_start = i40e_dev_rx_queue_start,
470 .rx_queue_stop = i40e_dev_rx_queue_stop,
471 .tx_queue_start = i40e_dev_tx_queue_start,
472 .tx_queue_stop = i40e_dev_tx_queue_stop,
473 .rx_queue_setup = i40e_dev_rx_queue_setup,
474 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
475 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
476 .rx_queue_release = i40e_dev_rx_queue_release,
477 .rx_queue_count = i40e_dev_rx_queue_count,
478 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
479 .tx_queue_setup = i40e_dev_tx_queue_setup,
480 .tx_queue_release = i40e_dev_tx_queue_release,
481 .dev_led_on = i40e_dev_led_on,
482 .dev_led_off = i40e_dev_led_off,
483 .flow_ctrl_get = i40e_flow_ctrl_get,
484 .flow_ctrl_set = i40e_flow_ctrl_set,
485 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
486 .mac_addr_add = i40e_macaddr_add,
487 .mac_addr_remove = i40e_macaddr_remove,
488 .reta_update = i40e_dev_rss_reta_update,
489 .reta_query = i40e_dev_rss_reta_query,
490 .rss_hash_update = i40e_dev_rss_hash_update,
491 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
492 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
493 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
494 .filter_ctrl = i40e_dev_filter_ctrl,
495 .rxq_info_get = i40e_rxq_info_get,
496 .txq_info_get = i40e_txq_info_get,
497 .mirror_rule_set = i40e_mirror_rule_set,
498 .mirror_rule_reset = i40e_mirror_rule_reset,
499 .timesync_enable = i40e_timesync_enable,
500 .timesync_disable = i40e_timesync_disable,
501 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
502 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
503 .get_dcb_info = i40e_dev_get_dcb_info,
504 .timesync_adjust_time = i40e_timesync_adjust_time,
505 .timesync_read_time = i40e_timesync_read_time,
506 .timesync_write_time = i40e_timesync_write_time,
507 .get_reg_length = i40e_get_reg_length,
508 .get_reg = i40e_get_regs,
509 .get_eeprom_length = i40e_get_eeprom_length,
510 .get_eeprom = i40e_get_eeprom,
511 .mac_addr_set = i40e_set_default_mac_addr,
514 /* store statistics names and its offset in stats structure */
515 struct rte_i40e_xstats_name_off {
516 char name[RTE_ETH_XSTATS_NAME_SIZE];
520 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
521 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
522 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
523 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
524 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
525 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
526 rx_unknown_protocol)},
527 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
528 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
529 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
530 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
533 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
534 sizeof(rte_i40e_stats_strings[0]))
536 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
537 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
538 tx_dropped_link_down)},
539 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
540 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
542 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
543 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
545 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
547 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
549 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
550 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
551 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
552 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
553 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
554 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
556 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
558 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
560 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
568 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
570 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
571 mac_short_packet_dropped)},
572 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
574 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
575 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
576 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
578 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
580 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
582 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
588 {"rx_flow_director_atr_match_packets",
589 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
590 {"rx_flow_director_sb_match_packets",
591 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
592 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
594 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
596 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
598 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
602 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
603 sizeof(rte_i40e_hw_port_strings[0]))
605 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
606 {"xon_packets", offsetof(struct i40e_hw_port_stats,
608 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
612 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
613 sizeof(rte_i40e_rxq_prio_strings[0]))
615 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
616 {"xon_packets", offsetof(struct i40e_hw_port_stats,
618 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
620 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
621 priority_xon_2_xoff)},
624 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
625 sizeof(rte_i40e_txq_prio_strings[0]))
627 static struct eth_driver rte_i40e_pmd = {
629 .name = "rte_i40e_pmd",
630 .id_table = pci_id_i40e_map,
631 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
632 RTE_PCI_DRV_DETACHABLE,
634 .eth_dev_init = eth_i40e_dev_init,
635 .eth_dev_uninit = eth_i40e_dev_uninit,
636 .dev_private_size = sizeof(struct i40e_adapter),
640 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
641 struct rte_eth_link *link)
643 struct rte_eth_link *dst = link;
644 struct rte_eth_link *src = &(dev->data->dev_link);
646 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
647 *(uint64_t *)src) == 0)
654 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
655 struct rte_eth_link *link)
657 struct rte_eth_link *dst = &(dev->data->dev_link);
658 struct rte_eth_link *src = link;
660 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
661 *(uint64_t *)src) == 0)
668 * Driver initialization routine.
669 * Invoked once at EAL init time.
670 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
673 rte_i40e_pmd_init(const char *name __rte_unused,
674 const char *params __rte_unused)
676 PMD_INIT_FUNC_TRACE();
677 rte_eth_driver_register(&rte_i40e_pmd);
682 static struct rte_driver rte_i40e_driver = {
684 .init = rte_i40e_pmd_init,
687 PMD_REGISTER_DRIVER(rte_i40e_driver);
690 * Initialize registers for flexible payload, which should be set by NVM.
691 * This should be removed from code once it is fixed in NVM.
693 #ifndef I40E_GLQF_ORT
694 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
696 #ifndef I40E_GLQF_PIT
697 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
700 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
702 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
703 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
704 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
705 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
706 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
707 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
708 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
710 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
711 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
713 /* GLQF_PIT Registers */
714 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
715 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
718 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
721 * Add a ethertype filter to drop all flow control frames transmitted
725 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
727 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
728 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
729 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
730 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
733 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
734 I40E_FLOW_CONTROL_ETHERTYPE, flags,
735 pf->main_vsi_seid, 0,
738 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
739 " frames from VSIs.");
743 eth_i40e_dev_init(struct rte_eth_dev *dev)
745 struct rte_pci_device *pci_dev;
746 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
747 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
748 struct i40e_vsi *vsi;
753 PMD_INIT_FUNC_TRACE();
755 dev->dev_ops = &i40e_eth_dev_ops;
756 dev->rx_pkt_burst = i40e_recv_pkts;
757 dev->tx_pkt_burst = i40e_xmit_pkts;
759 /* for secondary processes, we don't initialise any further as primary
760 * has already done this work. Only check we don't need a different
762 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
763 i40e_set_rx_function(dev);
764 i40e_set_tx_function(dev);
767 pci_dev = dev->pci_dev;
769 rte_eth_copy_pci_info(dev, pci_dev);
771 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
772 pf->adapter->eth_dev = dev;
773 pf->dev_data = dev->data;
775 hw->back = I40E_PF_TO_ADAPTER(pf);
776 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
778 PMD_INIT_LOG(ERR, "Hardware is not available, "
779 "as address is NULL");
783 hw->vendor_id = pci_dev->id.vendor_id;
784 hw->device_id = pci_dev->id.device_id;
785 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
786 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
787 hw->bus.device = pci_dev->addr.devid;
788 hw->bus.func = pci_dev->addr.function;
789 hw->adapter_stopped = 0;
791 /* Make sure all is clean before doing PF reset */
794 /* Initialize the hardware */
797 /* Reset here to make sure all is clean for each PF */
798 ret = i40e_pf_reset(hw);
800 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
804 /* Initialize the shared code (base driver) */
805 ret = i40e_init_shared_code(hw);
807 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
812 * To work around the NVM issue,initialize registers
813 * for flexible payload by software.
814 * It should be removed once issues are fixed in NVM.
816 i40e_flex_payload_reg_init(hw);
818 /* Initialize the parameters for adminq */
819 i40e_init_adminq_parameter(hw);
820 ret = i40e_init_adminq(hw);
821 if (ret != I40E_SUCCESS) {
822 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
825 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
826 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
827 hw->aq.api_maj_ver, hw->aq.api_min_ver,
828 ((hw->nvm.version >> 12) & 0xf),
829 ((hw->nvm.version >> 4) & 0xff),
830 (hw->nvm.version & 0xf), hw->nvm.eetrack);
833 i40e_clear_pxe_mode(hw);
836 * On X710, performance number is far from the expectation on recent
837 * firmware versions. The fix for this issue may not be integrated in
838 * the following firmware version. So the workaround in software driver
839 * is needed. It needs to modify the initial values of 3 internal only
840 * registers. Note that the workaround can be removed when it is fixed
841 * in firmware in the future.
843 i40e_configure_registers(hw);
845 /* Get hw capabilities */
846 ret = i40e_get_cap(hw);
847 if (ret != I40E_SUCCESS) {
848 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
849 goto err_get_capabilities;
852 /* Initialize parameters for PF */
853 ret = i40e_pf_parameter_init(dev);
855 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
856 goto err_parameter_init;
859 /* Initialize the queue management */
860 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
862 PMD_INIT_LOG(ERR, "Failed to init queue pool");
863 goto err_qp_pool_init;
865 ret = i40e_res_pool_init(&pf->msix_pool, 1,
866 hw->func_caps.num_msix_vectors - 1);
868 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
869 goto err_msix_pool_init;
872 /* Initialize lan hmc */
873 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
874 hw->func_caps.num_rx_qp, 0, 0);
875 if (ret != I40E_SUCCESS) {
876 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
877 goto err_init_lan_hmc;
880 /* Configure lan hmc */
881 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
882 if (ret != I40E_SUCCESS) {
883 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
884 goto err_configure_lan_hmc;
887 /* Get and check the mac address */
888 i40e_get_mac_addr(hw, hw->mac.addr);
889 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
890 PMD_INIT_LOG(ERR, "mac address is not valid");
892 goto err_get_mac_addr;
894 /* Copy the permanent MAC address */
895 ether_addr_copy((struct ether_addr *) hw->mac.addr,
896 (struct ether_addr *) hw->mac.perm_addr);
898 /* Disable flow control */
899 hw->fc.requested_mode = I40E_FC_NONE;
900 i40e_set_fc(hw, &aq_fail, TRUE);
902 /* Set the global registers with default ether type value */
903 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
904 if (ret != I40E_SUCCESS) {
905 PMD_INIT_LOG(ERR, "Failed to set the default outer "
907 goto err_setup_pf_switch;
909 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
910 if (ret != I40E_SUCCESS) {
911 PMD_INIT_LOG(ERR, "Failed to set the default outer "
913 goto err_setup_pf_switch;
916 /* PF setup, which includes VSI setup */
917 ret = i40e_pf_setup(pf);
919 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
920 goto err_setup_pf_switch;
925 /* Disable double vlan by default */
926 i40e_vsi_config_double_vlan(vsi, FALSE);
928 if (!vsi->max_macaddrs)
929 len = ETHER_ADDR_LEN;
931 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
933 /* Should be after VSI initialized */
934 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
935 if (!dev->data->mac_addrs) {
936 PMD_INIT_LOG(ERR, "Failed to allocated memory "
937 "for storing mac address");
940 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
941 &dev->data->mac_addrs[0]);
943 /* initialize pf host driver to setup SRIOV resource if applicable */
944 i40e_pf_host_init(dev);
946 /* register callback func to eal lib */
947 rte_intr_callback_register(&(pci_dev->intr_handle),
948 i40e_dev_interrupt_handler, (void *)dev);
950 /* configure and enable device interrupt */
951 i40e_pf_config_irq0(hw, TRUE);
952 i40e_pf_enable_irq0(hw);
954 /* enable uio intr after callback register */
955 rte_intr_enable(&(pci_dev->intr_handle));
957 * Add an ethertype filter to drop all flow control frames transmitted
958 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
961 i40e_add_tx_flow_control_drop_filter(pf);
963 /* Set the max frame size to 0x2600 by default,
964 * in case other drivers changed the default value.
966 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
968 /* initialize mirror rule list */
969 TAILQ_INIT(&pf->mirror_list);
971 /* Init dcb to sw mode by default */
972 ret = i40e_dcb_init_configure(dev, TRUE);
973 if (ret != I40E_SUCCESS) {
974 PMD_INIT_LOG(INFO, "Failed to init dcb.");
975 pf->flags &= ~I40E_FLAG_DCB;
981 i40e_vsi_release(pf->main_vsi);
984 err_configure_lan_hmc:
985 (void)i40e_shutdown_lan_hmc(hw);
987 i40e_res_pool_destroy(&pf->msix_pool);
989 i40e_res_pool_destroy(&pf->qp_pool);
992 err_get_capabilities:
993 (void)i40e_shutdown_adminq(hw);
999 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1001 struct rte_pci_device *pci_dev;
1003 struct i40e_filter_control_settings settings;
1005 uint8_t aq_fail = 0;
1007 PMD_INIT_FUNC_TRACE();
1009 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1012 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1013 pci_dev = dev->pci_dev;
1015 if (hw->adapter_stopped == 0)
1016 i40e_dev_close(dev);
1018 dev->dev_ops = NULL;
1019 dev->rx_pkt_burst = NULL;
1020 dev->tx_pkt_burst = NULL;
1023 ret = i40e_aq_stop_lldp(hw, true, NULL);
1024 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1025 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1027 /* Clear PXE mode */
1028 i40e_clear_pxe_mode(hw);
1030 /* Unconfigure filter control */
1031 memset(&settings, 0, sizeof(settings));
1032 ret = i40e_set_filter_control(hw, &settings);
1034 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1037 /* Disable flow control */
1038 hw->fc.requested_mode = I40E_FC_NONE;
1039 i40e_set_fc(hw, &aq_fail, TRUE);
1041 /* uninitialize pf host driver */
1042 i40e_pf_host_uninit(dev);
1044 rte_free(dev->data->mac_addrs);
1045 dev->data->mac_addrs = NULL;
1047 /* disable uio intr before callback unregister */
1048 rte_intr_disable(&(pci_dev->intr_handle));
1050 /* register callback func to eal lib */
1051 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1052 i40e_dev_interrupt_handler, (void *)dev);
1058 i40e_dev_configure(struct rte_eth_dev *dev)
1060 struct i40e_adapter *ad =
1061 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1062 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1063 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1066 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1067 * bulk allocation or vector Rx preconditions we will reset it.
1069 ad->rx_bulk_alloc_allowed = true;
1070 ad->rx_vec_allowed = true;
1071 ad->tx_simple_allowed = true;
1072 ad->tx_vec_allowed = true;
1074 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1075 ret = i40e_fdir_setup(pf);
1076 if (ret != I40E_SUCCESS) {
1077 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1080 ret = i40e_fdir_configure(dev);
1082 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1086 i40e_fdir_teardown(pf);
1088 ret = i40e_dev_init_vlan(dev);
1093 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1094 * RSS setting have different requirements.
1095 * General PMD driver call sequence are NIC init, configure,
1096 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1097 * will try to lookup the VSI that specific queue belongs to if VMDQ
1098 * applicable. So, VMDQ setting has to be done before
1099 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1100 * For RSS setting, it will try to calculate actual configured RX queue
1101 * number, which will be available after rx_queue_setup(). dev_start()
1102 * function is good to place RSS setup.
1104 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1105 ret = i40e_vmdq_setup(dev);
1110 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1111 ret = i40e_dcb_setup(dev);
1113 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1121 /* need to release vmdq resource if exists */
1122 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1123 i40e_vsi_release(pf->vmdq[i].vsi);
1124 pf->vmdq[i].vsi = NULL;
1129 /* need to release fdir resource if exists */
1130 i40e_fdir_teardown(pf);
1135 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1137 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1138 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1139 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1140 uint16_t msix_vect = vsi->msix_intr;
1143 for (i = 0; i < vsi->nb_qps; i++) {
1144 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1145 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1149 if (vsi->type != I40E_VSI_SRIOV) {
1150 if (!rte_intr_allow_others(intr_handle)) {
1151 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1152 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1154 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1157 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1158 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1160 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1165 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1166 vsi->user_param + (msix_vect - 1);
1168 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1169 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1171 I40E_WRITE_FLUSH(hw);
1175 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1176 int base_queue, int nb_queue)
1180 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1182 /* Bind all RX queues to allocated MSIX interrupt */
1183 for (i = 0; i < nb_queue; i++) {
1184 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1185 I40E_QINT_RQCTL_ITR_INDX_MASK |
1186 ((base_queue + i + 1) <<
1187 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1188 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1189 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1191 if (i == nb_queue - 1)
1192 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1193 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1196 /* Write first RX queue to Link list register as the head element */
1197 if (vsi->type != I40E_VSI_SRIOV) {
1199 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1201 if (msix_vect == I40E_MISC_VEC_ID) {
1202 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1204 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1206 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1208 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1211 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1213 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1215 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1217 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1224 if (msix_vect == I40E_MISC_VEC_ID) {
1226 I40E_VPINT_LNKLST0(vsi->user_param),
1228 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1230 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1232 /* num_msix_vectors_vf needs to minus irq0 */
1233 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1234 vsi->user_param + (msix_vect - 1);
1236 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1238 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1240 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1244 I40E_WRITE_FLUSH(hw);
1248 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1250 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1251 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1252 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1253 uint16_t msix_vect = vsi->msix_intr;
1254 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1255 uint16_t queue_idx = 0;
1260 for (i = 0; i < vsi->nb_qps; i++) {
1261 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1262 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1265 /* INTENA flag is not auto-cleared for interrupt */
1266 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1267 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1268 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1269 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1270 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1272 /* VF bind interrupt */
1273 if (vsi->type == I40E_VSI_SRIOV) {
1274 __vsi_queues_bind_intr(vsi, msix_vect,
1275 vsi->base_queue, vsi->nb_qps);
1279 /* PF & VMDq bind interrupt */
1280 if (rte_intr_dp_is_en(intr_handle)) {
1281 if (vsi->type == I40E_VSI_MAIN) {
1284 } else if (vsi->type == I40E_VSI_VMDQ2) {
1285 struct i40e_vsi *main_vsi =
1286 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1287 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1292 for (i = 0; i < vsi->nb_used_qps; i++) {
1294 if (!rte_intr_allow_others(intr_handle))
1295 /* allow to share MISC_VEC_ID */
1296 msix_vect = I40E_MISC_VEC_ID;
1298 /* no enough msix_vect, map all to one */
1299 __vsi_queues_bind_intr(vsi, msix_vect,
1300 vsi->base_queue + i,
1301 vsi->nb_used_qps - i);
1302 for (; !!record && i < vsi->nb_used_qps; i++)
1303 intr_handle->intr_vec[queue_idx + i] =
1307 /* 1:1 queue/msix_vect mapping */
1308 __vsi_queues_bind_intr(vsi, msix_vect,
1309 vsi->base_queue + i, 1);
1311 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1319 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1321 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1322 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1323 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1324 uint16_t interval = i40e_calc_itr_interval(\
1325 RTE_LIBRTE_I40E_ITR_INTERVAL);
1326 uint16_t msix_intr, i;
1328 if (rte_intr_allow_others(intr_handle))
1329 for (i = 0; i < vsi->nb_msix; i++) {
1330 msix_intr = vsi->msix_intr + i;
1331 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1332 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1333 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1334 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1336 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1339 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1340 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1341 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1342 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1344 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1346 I40E_WRITE_FLUSH(hw);
1350 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1352 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1353 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1354 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1355 uint16_t msix_intr, i;
1357 if (rte_intr_allow_others(intr_handle))
1358 for (i = 0; i < vsi->nb_msix; i++) {
1359 msix_intr = vsi->msix_intr + i;
1360 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1364 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1366 I40E_WRITE_FLUSH(hw);
1369 static inline uint8_t
1370 i40e_parse_link_speed(uint16_t eth_link_speed)
1372 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1374 switch (eth_link_speed) {
1375 case ETH_LINK_SPEED_40G:
1376 link_speed = I40E_LINK_SPEED_40GB;
1378 case ETH_LINK_SPEED_20G:
1379 link_speed = I40E_LINK_SPEED_20GB;
1381 case ETH_LINK_SPEED_10G:
1382 link_speed = I40E_LINK_SPEED_10GB;
1384 case ETH_LINK_SPEED_1000:
1385 link_speed = I40E_LINK_SPEED_1GB;
1387 case ETH_LINK_SPEED_100:
1388 link_speed = I40E_LINK_SPEED_100MB;
1396 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1397 __rte_unused uint8_t abilities,
1398 __rte_unused uint8_t force_speed)
1400 /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1401 * for the link control limitation of that all link control should be
1402 * handled by firmware. It should follow up if link control will be
1403 * opened to software driver in future firmware versions.
1405 return I40E_SUCCESS;
1409 i40e_apply_link_speed(struct rte_eth_dev *dev)
1412 uint8_t abilities = 0;
1413 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414 struct rte_eth_conf *conf = &dev->data->dev_conf;
1416 speed = i40e_parse_link_speed(conf->link_speed);
1417 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1418 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1419 abilities |= I40E_AQ_PHY_AN_ENABLED;
1421 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1423 return i40e_phy_conf_link(hw, abilities, speed);
1427 i40e_dev_start(struct rte_eth_dev *dev)
1429 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1430 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1431 struct i40e_vsi *main_vsi = pf->main_vsi;
1433 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1434 uint32_t intr_vector = 0;
1436 hw->adapter_stopped = 0;
1438 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1439 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1440 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1441 dev->data->dev_conf.link_duplex,
1442 dev->data->port_id);
1446 rte_intr_disable(intr_handle);
1448 if ((rte_intr_cap_multiple(intr_handle) ||
1449 !RTE_ETH_DEV_SRIOV(dev).active) &&
1450 dev->data->dev_conf.intr_conf.rxq != 0) {
1451 intr_vector = dev->data->nb_rx_queues;
1452 if (rte_intr_efd_enable(intr_handle, intr_vector))
1456 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1457 intr_handle->intr_vec =
1458 rte_zmalloc("intr_vec",
1459 dev->data->nb_rx_queues * sizeof(int),
1461 if (!intr_handle->intr_vec) {
1462 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1463 " intr_vec\n", dev->data->nb_rx_queues);
1468 /* Initialize VSI */
1469 ret = i40e_dev_rxtx_init(pf);
1470 if (ret != I40E_SUCCESS) {
1471 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1475 /* Map queues with MSIX interrupt */
1476 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1477 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1478 i40e_vsi_queues_bind_intr(main_vsi);
1479 i40e_vsi_enable_queues_intr(main_vsi);
1481 /* Map VMDQ VSI queues with MSIX interrupt */
1482 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1483 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1484 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1485 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1488 /* enable FDIR MSIX interrupt */
1489 if (pf->fdir.fdir_vsi) {
1490 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1491 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1494 /* Enable all queues which have been configured */
1495 ret = i40e_dev_switch_queues(pf, TRUE);
1496 if (ret != I40E_SUCCESS) {
1497 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1501 /* Enable receiving broadcast packets */
1502 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1503 if (ret != I40E_SUCCESS)
1504 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1506 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1507 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1509 if (ret != I40E_SUCCESS)
1510 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1513 /* Apply link configure */
1514 ret = i40e_apply_link_speed(dev);
1515 if (I40E_SUCCESS != ret) {
1516 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1520 if (!rte_intr_allow_others(intr_handle)) {
1521 rte_intr_callback_unregister(intr_handle,
1522 i40e_dev_interrupt_handler,
1524 /* configure and enable device interrupt */
1525 i40e_pf_config_irq0(hw, FALSE);
1526 i40e_pf_enable_irq0(hw);
1528 if (dev->data->dev_conf.intr_conf.lsc != 0)
1529 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1530 " no intr multiplex\n");
1533 /* enable uio intr after callback register */
1534 rte_intr_enable(intr_handle);
1536 return I40E_SUCCESS;
1539 i40e_dev_switch_queues(pf, FALSE);
1540 i40e_dev_clear_queues(dev);
1546 i40e_dev_stop(struct rte_eth_dev *dev)
1548 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1549 struct i40e_vsi *main_vsi = pf->main_vsi;
1550 struct i40e_mirror_rule *p_mirror;
1551 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1554 /* Disable all queues */
1555 i40e_dev_switch_queues(pf, FALSE);
1557 /* un-map queues with interrupt registers */
1558 i40e_vsi_disable_queues_intr(main_vsi);
1559 i40e_vsi_queues_unbind_intr(main_vsi);
1561 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1562 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1563 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1566 if (pf->fdir.fdir_vsi) {
1567 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1568 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1570 /* Clear all queues and release memory */
1571 i40e_dev_clear_queues(dev);
1574 i40e_dev_set_link_down(dev);
1576 /* Remove all mirror rules */
1577 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1578 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1581 pf->nb_mirror_rule = 0;
1583 if (!rte_intr_allow_others(intr_handle))
1584 /* resume to the default handler */
1585 rte_intr_callback_register(intr_handle,
1586 i40e_dev_interrupt_handler,
1589 /* Clean datapath event and queue/vec mapping */
1590 rte_intr_efd_disable(intr_handle);
1591 if (intr_handle->intr_vec) {
1592 rte_free(intr_handle->intr_vec);
1593 intr_handle->intr_vec = NULL;
1598 i40e_dev_close(struct rte_eth_dev *dev)
1600 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1601 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1605 PMD_INIT_FUNC_TRACE();
1608 hw->adapter_stopped = 1;
1609 i40e_dev_free_queues(dev);
1611 /* Disable interrupt */
1612 i40e_pf_disable_irq0(hw);
1613 rte_intr_disable(&(dev->pci_dev->intr_handle));
1615 /* shutdown and destroy the HMC */
1616 i40e_shutdown_lan_hmc(hw);
1618 /* release all the existing VSIs and VEBs */
1619 i40e_fdir_teardown(pf);
1620 i40e_vsi_release(pf->main_vsi);
1622 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1623 i40e_vsi_release(pf->vmdq[i].vsi);
1624 pf->vmdq[i].vsi = NULL;
1630 /* shutdown the adminq */
1631 i40e_aq_queue_shutdown(hw, true);
1632 i40e_shutdown_adminq(hw);
1634 i40e_res_pool_destroy(&pf->qp_pool);
1635 i40e_res_pool_destroy(&pf->msix_pool);
1637 /* force a PF reset to clean anything leftover */
1638 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1639 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1640 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1641 I40E_WRITE_FLUSH(hw);
1645 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1647 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1648 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1649 struct i40e_vsi *vsi = pf->main_vsi;
1652 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1654 if (status != I40E_SUCCESS)
1655 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1657 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1659 if (status != I40E_SUCCESS)
1660 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1665 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1667 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1668 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1669 struct i40e_vsi *vsi = pf->main_vsi;
1672 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1674 if (status != I40E_SUCCESS)
1675 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1677 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1679 if (status != I40E_SUCCESS)
1680 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1684 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1686 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1687 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1688 struct i40e_vsi *vsi = pf->main_vsi;
1691 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1692 if (ret != I40E_SUCCESS)
1693 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1697 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1699 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1700 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701 struct i40e_vsi *vsi = pf->main_vsi;
1704 if (dev->data->promiscuous == 1)
1705 return; /* must remain in all_multicast mode */
1707 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1708 vsi->seid, FALSE, NULL);
1709 if (ret != I40E_SUCCESS)
1710 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1714 * Set device link up.
1717 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1719 /* re-apply link speed setting */
1720 return i40e_apply_link_speed(dev);
1724 * Set device link down.
1727 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1729 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1730 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1731 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1733 return i40e_phy_conf_link(hw, abilities, speed);
1737 i40e_dev_link_update(struct rte_eth_dev *dev,
1738 int wait_to_complete)
1740 #define CHECK_INTERVAL 100 /* 100ms */
1741 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1742 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1743 struct i40e_link_status link_status;
1744 struct rte_eth_link link, old;
1746 unsigned rep_cnt = MAX_REPEAT_TIME;
1748 memset(&link, 0, sizeof(link));
1749 memset(&old, 0, sizeof(old));
1750 memset(&link_status, 0, sizeof(link_status));
1751 rte_i40e_dev_atomic_read_link_status(dev, &old);
1754 /* Get link status information from hardware */
1755 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1756 if (status != I40E_SUCCESS) {
1757 link.link_speed = ETH_LINK_SPEED_100;
1758 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1759 PMD_DRV_LOG(ERR, "Failed to get link info");
1763 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1764 if (!wait_to_complete)
1767 rte_delay_ms(CHECK_INTERVAL);
1768 } while (!link.link_status && rep_cnt--);
1770 if (!link.link_status)
1773 /* i40e uses full duplex only */
1774 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1776 /* Parse the link status */
1777 switch (link_status.link_speed) {
1778 case I40E_LINK_SPEED_100MB:
1779 link.link_speed = ETH_LINK_SPEED_100;
1781 case I40E_LINK_SPEED_1GB:
1782 link.link_speed = ETH_LINK_SPEED_1000;
1784 case I40E_LINK_SPEED_10GB:
1785 link.link_speed = ETH_LINK_SPEED_10G;
1787 case I40E_LINK_SPEED_20GB:
1788 link.link_speed = ETH_LINK_SPEED_20G;
1790 case I40E_LINK_SPEED_40GB:
1791 link.link_speed = ETH_LINK_SPEED_40G;
1794 link.link_speed = ETH_LINK_SPEED_100;
1799 rte_i40e_dev_atomic_write_link_status(dev, &link);
1800 if (link.link_status == old.link_status)
1806 /* Get all the statistics of a VSI */
1808 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1810 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1811 struct i40e_eth_stats *nes = &vsi->eth_stats;
1812 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1813 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1815 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1816 vsi->offset_loaded, &oes->rx_bytes,
1818 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1819 vsi->offset_loaded, &oes->rx_unicast,
1821 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1822 vsi->offset_loaded, &oes->rx_multicast,
1823 &nes->rx_multicast);
1824 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1825 vsi->offset_loaded, &oes->rx_broadcast,
1826 &nes->rx_broadcast);
1827 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1828 &oes->rx_discards, &nes->rx_discards);
1829 /* GLV_REPC not supported */
1830 /* GLV_RMPC not supported */
1831 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1832 &oes->rx_unknown_protocol,
1833 &nes->rx_unknown_protocol);
1834 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1835 vsi->offset_loaded, &oes->tx_bytes,
1837 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1838 vsi->offset_loaded, &oes->tx_unicast,
1840 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1841 vsi->offset_loaded, &oes->tx_multicast,
1842 &nes->tx_multicast);
1843 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1844 vsi->offset_loaded, &oes->tx_broadcast,
1845 &nes->tx_broadcast);
1846 /* GLV_TDPC not supported */
1847 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1848 &oes->tx_errors, &nes->tx_errors);
1849 vsi->offset_loaded = true;
1851 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1853 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1854 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1855 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1856 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1857 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1858 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1859 nes->rx_unknown_protocol);
1860 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1861 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1862 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1863 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1864 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1865 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1866 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1871 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1874 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1875 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1877 /* Get statistics of struct i40e_eth_stats */
1878 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1879 I40E_GLPRT_GORCL(hw->port),
1880 pf->offset_loaded, &os->eth.rx_bytes,
1882 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1883 I40E_GLPRT_UPRCL(hw->port),
1884 pf->offset_loaded, &os->eth.rx_unicast,
1885 &ns->eth.rx_unicast);
1886 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1887 I40E_GLPRT_MPRCL(hw->port),
1888 pf->offset_loaded, &os->eth.rx_multicast,
1889 &ns->eth.rx_multicast);
1890 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1891 I40E_GLPRT_BPRCL(hw->port),
1892 pf->offset_loaded, &os->eth.rx_broadcast,
1893 &ns->eth.rx_broadcast);
1894 /* Workaround: CRC size should not be included in byte statistics,
1895 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1897 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1898 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1900 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1901 pf->offset_loaded, &os->eth.rx_discards,
1902 &ns->eth.rx_discards);
1903 /* GLPRT_REPC not supported */
1904 /* GLPRT_RMPC not supported */
1905 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1907 &os->eth.rx_unknown_protocol,
1908 &ns->eth.rx_unknown_protocol);
1909 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1910 I40E_GLPRT_GOTCL(hw->port),
1911 pf->offset_loaded, &os->eth.tx_bytes,
1913 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1914 I40E_GLPRT_UPTCL(hw->port),
1915 pf->offset_loaded, &os->eth.tx_unicast,
1916 &ns->eth.tx_unicast);
1917 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1918 I40E_GLPRT_MPTCL(hw->port),
1919 pf->offset_loaded, &os->eth.tx_multicast,
1920 &ns->eth.tx_multicast);
1921 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1922 I40E_GLPRT_BPTCL(hw->port),
1923 pf->offset_loaded, &os->eth.tx_broadcast,
1924 &ns->eth.tx_broadcast);
1925 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1926 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1927 /* GLPRT_TEPC not supported */
1929 /* additional port specific stats */
1930 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1931 pf->offset_loaded, &os->tx_dropped_link_down,
1932 &ns->tx_dropped_link_down);
1933 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1934 pf->offset_loaded, &os->crc_errors,
1936 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1937 pf->offset_loaded, &os->illegal_bytes,
1938 &ns->illegal_bytes);
1939 /* GLPRT_ERRBC not supported */
1940 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1941 pf->offset_loaded, &os->mac_local_faults,
1942 &ns->mac_local_faults);
1943 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1944 pf->offset_loaded, &os->mac_remote_faults,
1945 &ns->mac_remote_faults);
1946 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1947 pf->offset_loaded, &os->rx_length_errors,
1948 &ns->rx_length_errors);
1949 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1950 pf->offset_loaded, &os->link_xon_rx,
1952 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1953 pf->offset_loaded, &os->link_xoff_rx,
1955 for (i = 0; i < 8; i++) {
1956 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1958 &os->priority_xon_rx[i],
1959 &ns->priority_xon_rx[i]);
1960 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1962 &os->priority_xoff_rx[i],
1963 &ns->priority_xoff_rx[i]);
1965 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1966 pf->offset_loaded, &os->link_xon_tx,
1968 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1969 pf->offset_loaded, &os->link_xoff_tx,
1971 for (i = 0; i < 8; i++) {
1972 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1974 &os->priority_xon_tx[i],
1975 &ns->priority_xon_tx[i]);
1976 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1978 &os->priority_xoff_tx[i],
1979 &ns->priority_xoff_tx[i]);
1980 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1982 &os->priority_xon_2_xoff[i],
1983 &ns->priority_xon_2_xoff[i]);
1985 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1986 I40E_GLPRT_PRC64L(hw->port),
1987 pf->offset_loaded, &os->rx_size_64,
1989 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1990 I40E_GLPRT_PRC127L(hw->port),
1991 pf->offset_loaded, &os->rx_size_127,
1993 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1994 I40E_GLPRT_PRC255L(hw->port),
1995 pf->offset_loaded, &os->rx_size_255,
1997 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1998 I40E_GLPRT_PRC511L(hw->port),
1999 pf->offset_loaded, &os->rx_size_511,
2001 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2002 I40E_GLPRT_PRC1023L(hw->port),
2003 pf->offset_loaded, &os->rx_size_1023,
2005 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2006 I40E_GLPRT_PRC1522L(hw->port),
2007 pf->offset_loaded, &os->rx_size_1522,
2009 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2010 I40E_GLPRT_PRC9522L(hw->port),
2011 pf->offset_loaded, &os->rx_size_big,
2013 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2014 pf->offset_loaded, &os->rx_undersize,
2016 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2017 pf->offset_loaded, &os->rx_fragments,
2019 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2020 pf->offset_loaded, &os->rx_oversize,
2022 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2023 pf->offset_loaded, &os->rx_jabber,
2025 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2026 I40E_GLPRT_PTC64L(hw->port),
2027 pf->offset_loaded, &os->tx_size_64,
2029 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2030 I40E_GLPRT_PTC127L(hw->port),
2031 pf->offset_loaded, &os->tx_size_127,
2033 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2034 I40E_GLPRT_PTC255L(hw->port),
2035 pf->offset_loaded, &os->tx_size_255,
2037 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2038 I40E_GLPRT_PTC511L(hw->port),
2039 pf->offset_loaded, &os->tx_size_511,
2041 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2042 I40E_GLPRT_PTC1023L(hw->port),
2043 pf->offset_loaded, &os->tx_size_1023,
2045 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2046 I40E_GLPRT_PTC1522L(hw->port),
2047 pf->offset_loaded, &os->tx_size_1522,
2049 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2050 I40E_GLPRT_PTC9522L(hw->port),
2051 pf->offset_loaded, &os->tx_size_big,
2053 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2055 &os->fd_sb_match, &ns->fd_sb_match);
2056 /* GLPRT_MSPDC not supported */
2057 /* GLPRT_XEC not supported */
2059 pf->offset_loaded = true;
2062 i40e_update_vsi_stats(pf->main_vsi);
2065 /* Get all statistics of a port */
2067 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2069 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2070 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2071 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2074 /* call read registers - updates values, now write them to struct */
2075 i40e_read_stats_registers(pf, hw);
2077 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2078 pf->main_vsi->eth_stats.rx_multicast +
2079 pf->main_vsi->eth_stats.rx_broadcast -
2080 pf->main_vsi->eth_stats.rx_discards;
2081 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2082 pf->main_vsi->eth_stats.tx_multicast +
2083 pf->main_vsi->eth_stats.tx_broadcast;
2084 stats->ibytes = ns->eth.rx_bytes;
2085 stats->obytes = ns->eth.tx_bytes;
2086 stats->oerrors = ns->eth.tx_errors +
2087 pf->main_vsi->eth_stats.tx_errors;
2088 stats->imcasts = pf->main_vsi->eth_stats.rx_multicast;
2091 stats->imissed = ns->eth.rx_discards +
2092 pf->main_vsi->eth_stats.rx_discards;
2093 stats->ierrors = ns->crc_errors +
2094 ns->rx_length_errors + ns->rx_undersize +
2095 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2097 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2098 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2099 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2100 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2101 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2102 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2103 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2104 ns->eth.rx_unknown_protocol);
2105 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2106 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2107 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2108 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2109 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2110 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2112 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2113 ns->tx_dropped_link_down);
2114 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2115 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2117 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2118 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2119 ns->mac_local_faults);
2120 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2121 ns->mac_remote_faults);
2122 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2123 ns->rx_length_errors);
2124 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2125 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2126 for (i = 0; i < 8; i++) {
2127 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2128 i, ns->priority_xon_rx[i]);
2129 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2130 i, ns->priority_xoff_rx[i]);
2132 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2133 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2134 for (i = 0; i < 8; i++) {
2135 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2136 i, ns->priority_xon_tx[i]);
2137 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2138 i, ns->priority_xoff_tx[i]);
2139 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2140 i, ns->priority_xon_2_xoff[i]);
2142 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2143 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2144 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2145 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2146 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2147 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2148 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2149 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2150 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2151 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2152 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2153 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2154 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2155 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2156 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2157 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2158 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2159 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2160 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2161 ns->mac_short_packet_dropped);
2162 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2163 ns->checksum_error);
2164 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2165 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2168 /* Reset the statistics */
2170 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2172 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2173 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2175 /* Mark PF and VSI stats to update the offset, aka "reset" */
2176 pf->offset_loaded = false;
2178 pf->main_vsi->offset_loaded = false;
2180 /* read the stats, reading current register values into offset */
2181 i40e_read_stats_registers(pf, hw);
2185 i40e_xstats_calc_num(void)
2187 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2188 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2189 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2193 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2196 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2197 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198 unsigned i, count, prio;
2199 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2201 count = i40e_xstats_calc_num();
2205 i40e_read_stats_registers(pf, hw);
2212 /* Get stats from i40e_eth_stats struct */
2213 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2214 snprintf(xstats[count].name, sizeof(xstats[count].name),
2215 "%s", rte_i40e_stats_strings[i].name);
2216 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2217 rte_i40e_stats_strings[i].offset);
2221 /* Get individiual stats from i40e_hw_port struct */
2222 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2223 snprintf(xstats[count].name, sizeof(xstats[count].name),
2224 "%s", rte_i40e_hw_port_strings[i].name);
2225 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2226 rte_i40e_hw_port_strings[i].offset);
2230 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2231 for (prio = 0; prio < 8; prio++) {
2232 snprintf(xstats[count].name,
2233 sizeof(xstats[count].name),
2234 "rx_priority%u_%s", prio,
2235 rte_i40e_rxq_prio_strings[i].name);
2236 xstats[count].value =
2237 *(uint64_t *)(((char *)hw_stats) +
2238 rte_i40e_rxq_prio_strings[i].offset +
2239 (sizeof(uint64_t) * prio));
2244 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2245 for (prio = 0; prio < 8; prio++) {
2246 snprintf(xstats[count].name,
2247 sizeof(xstats[count].name),
2248 "tx_priority%u_%s", prio,
2249 rte_i40e_txq_prio_strings[i].name);
2250 xstats[count].value =
2251 *(uint64_t *)(((char *)hw_stats) +
2252 rte_i40e_txq_prio_strings[i].offset +
2253 (sizeof(uint64_t) * prio));
2262 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2263 __rte_unused uint16_t queue_id,
2264 __rte_unused uint8_t stat_idx,
2265 __rte_unused uint8_t is_rx)
2267 PMD_INIT_FUNC_TRACE();
2273 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2275 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2276 struct i40e_vsi *vsi = pf->main_vsi;
2278 dev_info->max_rx_queues = vsi->nb_qps;
2279 dev_info->max_tx_queues = vsi->nb_qps;
2280 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2281 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2282 dev_info->max_mac_addrs = vsi->max_macaddrs;
2283 dev_info->max_vfs = dev->pci_dev->max_vfs;
2284 dev_info->rx_offload_capa =
2285 DEV_RX_OFFLOAD_VLAN_STRIP |
2286 DEV_RX_OFFLOAD_QINQ_STRIP |
2287 DEV_RX_OFFLOAD_IPV4_CKSUM |
2288 DEV_RX_OFFLOAD_UDP_CKSUM |
2289 DEV_RX_OFFLOAD_TCP_CKSUM;
2290 dev_info->tx_offload_capa =
2291 DEV_TX_OFFLOAD_VLAN_INSERT |
2292 DEV_TX_OFFLOAD_QINQ_INSERT |
2293 DEV_TX_OFFLOAD_IPV4_CKSUM |
2294 DEV_TX_OFFLOAD_UDP_CKSUM |
2295 DEV_TX_OFFLOAD_TCP_CKSUM |
2296 DEV_TX_OFFLOAD_SCTP_CKSUM |
2297 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2298 DEV_TX_OFFLOAD_TCP_TSO;
2299 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2301 dev_info->reta_size = pf->hash_lut_size;
2302 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2304 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2306 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2307 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2308 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2310 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2314 dev_info->default_txconf = (struct rte_eth_txconf) {
2316 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2317 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2318 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2320 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2321 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2322 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2323 ETH_TXQ_FLAGS_NOOFFLOADS,
2326 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2327 .nb_max = I40E_MAX_RING_DESC,
2328 .nb_min = I40E_MIN_RING_DESC,
2329 .nb_align = I40E_ALIGN_RING_DESC,
2332 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2333 .nb_max = I40E_MAX_RING_DESC,
2334 .nb_min = I40E_MIN_RING_DESC,
2335 .nb_align = I40E_ALIGN_RING_DESC,
2338 if (pf->flags & I40E_FLAG_VMDQ) {
2339 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2340 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2341 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2342 pf->max_nb_vmdq_vsi;
2343 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2344 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2345 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2350 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2352 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2353 struct i40e_vsi *vsi = pf->main_vsi;
2354 PMD_INIT_FUNC_TRACE();
2357 return i40e_vsi_add_vlan(vsi, vlan_id);
2359 return i40e_vsi_delete_vlan(vsi, vlan_id);
2363 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2364 enum rte_vlan_type vlan_type,
2367 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2368 uint64_t reg_r = 0, reg_w = 0;
2369 uint16_t reg_id = 0;
2372 switch (vlan_type) {
2373 case ETH_VLAN_TYPE_OUTER:
2376 case ETH_VLAN_TYPE_INNER:
2381 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2384 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2386 if (ret != I40E_SUCCESS) {
2387 PMD_DRV_LOG(ERR, "Fail to debug read from "
2388 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2392 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2393 "0x%08"PRIx64"", reg_id, reg_r);
2395 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2396 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2397 if (reg_r == reg_w) {
2399 PMD_DRV_LOG(DEBUG, "No need to write");
2403 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2405 if (ret != I40E_SUCCESS) {
2407 PMD_DRV_LOG(ERR, "Fail to debug write to "
2408 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2411 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2412 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2418 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2420 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2421 struct i40e_vsi *vsi = pf->main_vsi;
2423 if (mask & ETH_VLAN_FILTER_MASK) {
2424 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2425 i40e_vsi_config_vlan_filter(vsi, TRUE);
2427 i40e_vsi_config_vlan_filter(vsi, FALSE);
2430 if (mask & ETH_VLAN_STRIP_MASK) {
2431 /* Enable or disable VLAN stripping */
2432 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2433 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2435 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2438 if (mask & ETH_VLAN_EXTEND_MASK) {
2439 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2440 i40e_vsi_config_double_vlan(vsi, TRUE);
2442 i40e_vsi_config_double_vlan(vsi, FALSE);
2447 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2448 __rte_unused uint16_t queue,
2449 __rte_unused int on)
2451 PMD_INIT_FUNC_TRACE();
2455 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2457 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2458 struct i40e_vsi *vsi = pf->main_vsi;
2459 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2460 struct i40e_vsi_vlan_pvid_info info;
2462 memset(&info, 0, sizeof(info));
2465 info.config.pvid = pvid;
2467 info.config.reject.tagged =
2468 data->dev_conf.txmode.hw_vlan_reject_tagged;
2469 info.config.reject.untagged =
2470 data->dev_conf.txmode.hw_vlan_reject_untagged;
2473 return i40e_vsi_vlan_pvid_set(vsi, &info);
2477 i40e_dev_led_on(struct rte_eth_dev *dev)
2479 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2480 uint32_t mode = i40e_led_get(hw);
2483 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2489 i40e_dev_led_off(struct rte_eth_dev *dev)
2491 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2492 uint32_t mode = i40e_led_get(hw);
2495 i40e_led_set(hw, 0, false);
2501 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2503 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2504 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2506 fc_conf->pause_time = pf->fc_conf.pause_time;
2507 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2508 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2510 /* Return current mode according to actual setting*/
2511 switch (hw->fc.current_mode) {
2513 fc_conf->mode = RTE_FC_FULL;
2515 case I40E_FC_TX_PAUSE:
2516 fc_conf->mode = RTE_FC_TX_PAUSE;
2518 case I40E_FC_RX_PAUSE:
2519 fc_conf->mode = RTE_FC_RX_PAUSE;
2523 fc_conf->mode = RTE_FC_NONE;
2530 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2532 uint32_t mflcn_reg, fctrl_reg, reg;
2533 uint32_t max_high_water;
2534 uint8_t i, aq_failure;
2538 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2539 [RTE_FC_NONE] = I40E_FC_NONE,
2540 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2541 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2542 [RTE_FC_FULL] = I40E_FC_FULL
2545 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2547 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2548 if ((fc_conf->high_water > max_high_water) ||
2549 (fc_conf->high_water < fc_conf->low_water)) {
2550 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2551 "High_water must <= %d.", max_high_water);
2555 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2556 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2557 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2559 pf->fc_conf.pause_time = fc_conf->pause_time;
2560 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2561 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2563 PMD_INIT_FUNC_TRACE();
2565 /* All the link flow control related enable/disable register
2566 * configuration is handle by the F/W
2568 err = i40e_set_fc(hw, &aq_failure, true);
2572 if (i40e_is_40G_device(hw->device_id)) {
2573 /* Configure flow control refresh threshold,
2574 * the value for stat_tx_pause_refresh_timer[8]
2575 * is used for global pause operation.
2579 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2580 pf->fc_conf.pause_time);
2582 /* configure the timer value included in transmitted pause
2584 * the value for stat_tx_pause_quanta[8] is used for global
2587 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2588 pf->fc_conf.pause_time);
2590 fctrl_reg = I40E_READ_REG(hw,
2591 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2593 if (fc_conf->mac_ctrl_frame_fwd != 0)
2594 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2596 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2598 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2601 /* Configure pause time (2 TCs per register) */
2602 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2603 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2604 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2606 /* Configure flow control refresh threshold value */
2607 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2608 pf->fc_conf.pause_time / 2);
2610 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2612 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2613 *depending on configuration
2615 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2616 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2617 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2619 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2620 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2623 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2626 /* config the water marker both based on the packets and bytes */
2627 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2628 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2629 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2630 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2631 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2632 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2633 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2634 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2636 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2637 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2640 I40E_WRITE_FLUSH(hw);
2646 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2647 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2649 PMD_INIT_FUNC_TRACE();
2654 /* Add a MAC address, and update filters */
2656 i40e_macaddr_add(struct rte_eth_dev *dev,
2657 struct ether_addr *mac_addr,
2658 __rte_unused uint32_t index,
2661 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2662 struct i40e_mac_filter_info mac_filter;
2663 struct i40e_vsi *vsi;
2666 /* If VMDQ not enabled or configured, return */
2667 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2668 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2669 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2674 if (pool > pf->nb_cfg_vmdq_vsi) {
2675 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2676 pool, pf->nb_cfg_vmdq_vsi);
2680 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2681 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2682 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2684 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2689 vsi = pf->vmdq[pool - 1].vsi;
2691 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2692 if (ret != I40E_SUCCESS) {
2693 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2698 /* Remove a MAC address, and update filters */
2700 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2702 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2703 struct i40e_vsi *vsi;
2704 struct rte_eth_dev_data *data = dev->data;
2705 struct ether_addr *macaddr;
2710 macaddr = &(data->mac_addrs[index]);
2712 pool_sel = dev->data->mac_pool_sel[index];
2714 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2715 if (pool_sel & (1ULL << i)) {
2719 /* No VMDQ pool enabled or configured */
2720 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2721 (i > pf->nb_cfg_vmdq_vsi)) {
2722 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2726 vsi = pf->vmdq[i - 1].vsi;
2728 ret = i40e_vsi_delete_mac(vsi, macaddr);
2731 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2738 /* Set perfect match or hash match of MAC and VLAN for a VF */
2740 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2741 struct rte_eth_mac_filter *filter,
2745 struct i40e_mac_filter_info mac_filter;
2746 struct ether_addr old_mac;
2747 struct ether_addr *new_mac;
2748 struct i40e_pf_vf *vf = NULL;
2753 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2756 hw = I40E_PF_TO_HW(pf);
2758 if (filter == NULL) {
2759 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2763 new_mac = &filter->mac_addr;
2765 if (is_zero_ether_addr(new_mac)) {
2766 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2770 vf_id = filter->dst_id;
2772 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2773 PMD_DRV_LOG(ERR, "Invalid argument.");
2776 vf = &pf->vfs[vf_id];
2778 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2779 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2784 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2785 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2787 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2790 mac_filter.filter_type = filter->filter_type;
2791 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2792 if (ret != I40E_SUCCESS) {
2793 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2796 ether_addr_copy(new_mac, &pf->dev_addr);
2798 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2800 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2801 if (ret != I40E_SUCCESS) {
2802 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2806 /* Clear device address as it has been removed */
2807 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2808 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2814 /* MAC filter handle */
2816 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2819 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2820 struct rte_eth_mac_filter *filter;
2821 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2822 int ret = I40E_NOT_SUPPORTED;
2824 filter = (struct rte_eth_mac_filter *)(arg);
2826 switch (filter_op) {
2827 case RTE_ETH_FILTER_NOP:
2830 case RTE_ETH_FILTER_ADD:
2831 i40e_pf_disable_irq0(hw);
2833 ret = i40e_vf_mac_filter_set(pf, filter, 1);
2834 i40e_pf_enable_irq0(hw);
2836 case RTE_ETH_FILTER_DELETE:
2837 i40e_pf_disable_irq0(hw);
2839 ret = i40e_vf_mac_filter_set(pf, filter, 0);
2840 i40e_pf_enable_irq0(hw);
2843 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2844 ret = I40E_ERR_PARAM;
2852 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2854 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2855 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2861 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2862 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2865 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2869 uint32_t *lut_dw = (uint32_t *)lut;
2870 uint16_t i, lut_size_dw = lut_size / 4;
2872 for (i = 0; i < lut_size_dw; i++)
2873 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2880 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2882 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2883 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2889 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2890 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2893 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2897 uint32_t *lut_dw = (uint32_t *)lut;
2898 uint16_t i, lut_size_dw = lut_size / 4;
2900 for (i = 0; i < lut_size_dw; i++)
2901 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2902 I40E_WRITE_FLUSH(hw);
2909 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2910 struct rte_eth_rss_reta_entry64 *reta_conf,
2913 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2914 uint16_t i, lut_size = pf->hash_lut_size;
2915 uint16_t idx, shift;
2919 if (reta_size != lut_size ||
2920 reta_size > ETH_RSS_RETA_SIZE_512) {
2921 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2922 "(%d) doesn't match the number hardware can supported "
2923 "(%d)\n", reta_size, lut_size);
2927 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2929 PMD_DRV_LOG(ERR, "No memory can be allocated");
2932 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2935 for (i = 0; i < reta_size; i++) {
2936 idx = i / RTE_RETA_GROUP_SIZE;
2937 shift = i % RTE_RETA_GROUP_SIZE;
2938 if (reta_conf[idx].mask & (1ULL << shift))
2939 lut[i] = reta_conf[idx].reta[shift];
2941 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2950 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2951 struct rte_eth_rss_reta_entry64 *reta_conf,
2954 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2955 uint16_t i, lut_size = pf->hash_lut_size;
2956 uint16_t idx, shift;
2960 if (reta_size != lut_size ||
2961 reta_size > ETH_RSS_RETA_SIZE_512) {
2962 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2963 "(%d) doesn't match the number hardware can supported "
2964 "(%d)\n", reta_size, lut_size);
2968 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2970 PMD_DRV_LOG(ERR, "No memory can be allocated");
2974 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2977 for (i = 0; i < reta_size; i++) {
2978 idx = i / RTE_RETA_GROUP_SIZE;
2979 shift = i % RTE_RETA_GROUP_SIZE;
2980 if (reta_conf[idx].mask & (1ULL << shift))
2981 reta_conf[idx].reta[shift] = lut[i];
2991 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2992 * @hw: pointer to the HW structure
2993 * @mem: pointer to mem struct to fill out
2994 * @size: size of memory requested
2995 * @alignment: what to align the allocation to
2997 enum i40e_status_code
2998 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2999 struct i40e_dma_mem *mem,
3003 const struct rte_memzone *mz = NULL;
3004 char z_name[RTE_MEMZONE_NAMESIZE];
3007 return I40E_ERR_PARAM;
3009 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3010 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3011 alignment, RTE_PGSIZE_2M);
3013 return I40E_ERR_NO_MEMORY;
3017 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3018 mem->zone = (const void *)mz;
3019 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3020 "%"PRIu64, mz->name, mem->pa);
3022 return I40E_SUCCESS;
3026 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3027 * @hw: pointer to the HW structure
3028 * @mem: ptr to mem struct to free
3030 enum i40e_status_code
3031 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3032 struct i40e_dma_mem *mem)
3035 return I40E_ERR_PARAM;
3037 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3038 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3040 rte_memzone_free((const struct rte_memzone *)mem->zone);
3045 return I40E_SUCCESS;
3049 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3050 * @hw: pointer to the HW structure
3051 * @mem: pointer to mem struct to fill out
3052 * @size: size of memory requested
3054 enum i40e_status_code
3055 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3056 struct i40e_virt_mem *mem,
3060 return I40E_ERR_PARAM;
3063 mem->va = rte_zmalloc("i40e", size, 0);
3066 return I40E_SUCCESS;
3068 return I40E_ERR_NO_MEMORY;
3072 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3073 * @hw: pointer to the HW structure
3074 * @mem: pointer to mem struct to free
3076 enum i40e_status_code
3077 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3078 struct i40e_virt_mem *mem)
3081 return I40E_ERR_PARAM;
3086 return I40E_SUCCESS;
3090 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3092 rte_spinlock_init(&sp->spinlock);
3096 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3098 rte_spinlock_lock(&sp->spinlock);
3102 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3104 rte_spinlock_unlock(&sp->spinlock);
3108 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3114 * Get the hardware capabilities, which will be parsed
3115 * and saved into struct i40e_hw.
3118 i40e_get_cap(struct i40e_hw *hw)
3120 struct i40e_aqc_list_capabilities_element_resp *buf;
3121 uint16_t len, size = 0;
3124 /* Calculate a huge enough buff for saving response data temporarily */
3125 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3126 I40E_MAX_CAP_ELE_NUM;
3127 buf = rte_zmalloc("i40e", len, 0);
3129 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3130 return I40E_ERR_NO_MEMORY;
3133 /* Get, parse the capabilities and save it to hw */
3134 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3135 i40e_aqc_opc_list_func_capabilities, NULL);
3136 if (ret != I40E_SUCCESS)
3137 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3139 /* Free the temporary buffer after being used */
3146 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3148 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3149 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3150 uint16_t qp_count = 0, vsi_count = 0;
3152 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3153 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3156 /* Add the parameter init for LFC */
3157 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3158 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3159 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3161 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3162 pf->max_num_vsi = hw->func_caps.num_vsis;
3163 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3164 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3165 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3167 /* FDir queue/VSI allocation */
3168 pf->fdir_qp_offset = 0;
3169 if (hw->func_caps.fd) {
3170 pf->flags |= I40E_FLAG_FDIR;
3171 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3173 pf->fdir_nb_qps = 0;
3175 qp_count += pf->fdir_nb_qps;
3178 /* LAN queue/VSI allocation */
3179 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3180 if (!hw->func_caps.rss) {
3183 pf->flags |= I40E_FLAG_RSS;
3184 if (hw->mac.type == I40E_MAC_X722)
3185 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3186 pf->lan_nb_qps = pf->lan_nb_qp_max;
3188 qp_count += pf->lan_nb_qps;
3191 /* VF queue/VSI allocation */
3192 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3193 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3194 pf->flags |= I40E_FLAG_SRIOV;
3195 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3196 pf->vf_num = dev->pci_dev->max_vfs;
3197 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3198 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3199 pf->vf_nb_qps * pf->vf_num);
3204 qp_count += pf->vf_nb_qps * pf->vf_num;
3205 vsi_count += pf->vf_num;
3207 /* VMDq queue/VSI allocation */
3208 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3209 pf->vmdq_nb_qps = 0;
3210 pf->max_nb_vmdq_vsi = 0;
3211 if (hw->func_caps.vmdq) {
3212 if (qp_count < hw->func_caps.num_tx_qp &&
3213 vsi_count < hw->func_caps.num_vsis) {
3214 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3215 qp_count) / pf->vmdq_nb_qp_max;
3217 /* Limit the maximum number of VMDq vsi to the maximum
3218 * ethdev can support
3220 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3221 hw->func_caps.num_vsis - vsi_count);
3222 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3224 if (pf->max_nb_vmdq_vsi) {
3225 pf->flags |= I40E_FLAG_VMDQ;
3226 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3227 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3228 "per VMDQ VSI, in total %u queues",
3229 pf->max_nb_vmdq_vsi,
3230 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3231 pf->max_nb_vmdq_vsi);
3233 PMD_DRV_LOG(INFO, "No enough queues left for "
3237 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3240 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3241 vsi_count += pf->max_nb_vmdq_vsi;
3243 if (hw->func_caps.dcb)
3244 pf->flags |= I40E_FLAG_DCB;
3246 if (qp_count > hw->func_caps.num_tx_qp) {
3247 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3248 "the hardware maximum %u", qp_count,
3249 hw->func_caps.num_tx_qp);
3252 if (vsi_count > hw->func_caps.num_vsis) {
3253 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3254 "the hardware maximum %u", vsi_count,
3255 hw->func_caps.num_vsis);
3263 i40e_pf_get_switch_config(struct i40e_pf *pf)
3265 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3266 struct i40e_aqc_get_switch_config_resp *switch_config;
3267 struct i40e_aqc_switch_config_element_resp *element;
3268 uint16_t start_seid = 0, num_reported;
3271 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3272 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3273 if (!switch_config) {
3274 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3278 /* Get the switch configurations */
3279 ret = i40e_aq_get_switch_config(hw, switch_config,
3280 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3281 if (ret != I40E_SUCCESS) {
3282 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3285 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3286 if (num_reported != 1) { /* The number should be 1 */
3287 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3291 /* Parse the switch configuration elements */
3292 element = &(switch_config->element[0]);
3293 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3294 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3295 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3297 PMD_DRV_LOG(INFO, "Unknown element type");
3300 rte_free(switch_config);
3306 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3309 struct pool_entry *entry;
3311 if (pool == NULL || num == 0)
3314 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3315 if (entry == NULL) {
3316 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3320 /* queue heap initialize */
3321 pool->num_free = num;
3322 pool->num_alloc = 0;
3324 LIST_INIT(&pool->alloc_list);
3325 LIST_INIT(&pool->free_list);
3327 /* Initialize element */
3331 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3336 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3338 struct pool_entry *entry;
3343 LIST_FOREACH(entry, &pool->alloc_list, next) {
3344 LIST_REMOVE(entry, next);
3348 LIST_FOREACH(entry, &pool->free_list, next) {
3349 LIST_REMOVE(entry, next);
3354 pool->num_alloc = 0;
3356 LIST_INIT(&pool->alloc_list);
3357 LIST_INIT(&pool->free_list);
3361 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3364 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3365 uint32_t pool_offset;
3369 PMD_DRV_LOG(ERR, "Invalid parameter");
3373 pool_offset = base - pool->base;
3374 /* Lookup in alloc list */
3375 LIST_FOREACH(entry, &pool->alloc_list, next) {
3376 if (entry->base == pool_offset) {
3377 valid_entry = entry;
3378 LIST_REMOVE(entry, next);
3383 /* Not find, return */
3384 if (valid_entry == NULL) {
3385 PMD_DRV_LOG(ERR, "Failed to find entry");
3390 * Found it, move it to free list and try to merge.
3391 * In order to make merge easier, always sort it by qbase.
3392 * Find adjacent prev and last entries.
3395 LIST_FOREACH(entry, &pool->free_list, next) {
3396 if (entry->base > valid_entry->base) {
3404 /* Try to merge with next one*/
3406 /* Merge with next one */
3407 if (valid_entry->base + valid_entry->len == next->base) {
3408 next->base = valid_entry->base;
3409 next->len += valid_entry->len;
3410 rte_free(valid_entry);
3417 /* Merge with previous one */
3418 if (prev->base + prev->len == valid_entry->base) {
3419 prev->len += valid_entry->len;
3420 /* If it merge with next one, remove next node */
3422 LIST_REMOVE(valid_entry, next);
3423 rte_free(valid_entry);
3425 rte_free(valid_entry);
3431 /* Not find any entry to merge, insert */
3434 LIST_INSERT_AFTER(prev, valid_entry, next);
3435 else if (next != NULL)
3436 LIST_INSERT_BEFORE(next, valid_entry, next);
3437 else /* It's empty list, insert to head */
3438 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3441 pool->num_free += valid_entry->len;
3442 pool->num_alloc -= valid_entry->len;
3448 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3451 struct pool_entry *entry, *valid_entry;
3453 if (pool == NULL || num == 0) {
3454 PMD_DRV_LOG(ERR, "Invalid parameter");
3458 if (pool->num_free < num) {
3459 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3460 num, pool->num_free);
3465 /* Lookup in free list and find most fit one */
3466 LIST_FOREACH(entry, &pool->free_list, next) {
3467 if (entry->len >= num) {
3469 if (entry->len == num) {
3470 valid_entry = entry;
3473 if (valid_entry == NULL || valid_entry->len > entry->len)
3474 valid_entry = entry;
3478 /* Not find one to satisfy the request, return */
3479 if (valid_entry == NULL) {
3480 PMD_DRV_LOG(ERR, "No valid entry found");
3484 * The entry have equal queue number as requested,
3485 * remove it from alloc_list.
3487 if (valid_entry->len == num) {
3488 LIST_REMOVE(valid_entry, next);
3491 * The entry have more numbers than requested,
3492 * create a new entry for alloc_list and minus its
3493 * queue base and number in free_list.
3495 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3496 if (entry == NULL) {
3497 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3501 entry->base = valid_entry->base;
3503 valid_entry->base += num;
3504 valid_entry->len -= num;
3505 valid_entry = entry;
3508 /* Insert it into alloc list, not sorted */
3509 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3511 pool->num_free -= valid_entry->len;
3512 pool->num_alloc += valid_entry->len;
3514 return valid_entry->base + pool->base;
3518 * bitmap_is_subset - Check whether src2 is subset of src1
3521 bitmap_is_subset(uint8_t src1, uint8_t src2)
3523 return !((src1 ^ src2) & src2);
3526 static enum i40e_status_code
3527 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3529 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3531 /* If DCB is not supported, only default TC is supported */
3532 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3533 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3534 return I40E_NOT_SUPPORTED;
3537 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3538 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3539 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3541 return I40E_NOT_SUPPORTED;
3543 return I40E_SUCCESS;
3547 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3548 struct i40e_vsi_vlan_pvid_info *info)
3551 struct i40e_vsi_context ctxt;
3552 uint8_t vlan_flags = 0;
3555 if (vsi == NULL || info == NULL) {
3556 PMD_DRV_LOG(ERR, "invalid parameters");
3557 return I40E_ERR_PARAM;
3561 vsi->info.pvid = info->config.pvid;
3563 * If insert pvid is enabled, only tagged pkts are
3564 * allowed to be sent out.
3566 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3567 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3570 if (info->config.reject.tagged == 0)
3571 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3573 if (info->config.reject.untagged == 0)
3574 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3576 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3577 I40E_AQ_VSI_PVLAN_MODE_MASK);
3578 vsi->info.port_vlan_flags |= vlan_flags;
3579 vsi->info.valid_sections =
3580 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3581 memset(&ctxt, 0, sizeof(ctxt));
3582 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3583 ctxt.seid = vsi->seid;
3585 hw = I40E_VSI_TO_HW(vsi);
3586 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3587 if (ret != I40E_SUCCESS)
3588 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3594 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3596 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3598 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3600 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3601 if (ret != I40E_SUCCESS)
3605 PMD_DRV_LOG(ERR, "seid not valid");
3609 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3610 tc_bw_data.tc_valid_bits = enabled_tcmap;
3611 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3612 tc_bw_data.tc_bw_credits[i] =
3613 (enabled_tcmap & (1 << i)) ? 1 : 0;
3615 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3616 if (ret != I40E_SUCCESS) {
3617 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3621 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3622 sizeof(vsi->info.qs_handle));
3623 return I40E_SUCCESS;
3626 static enum i40e_status_code
3627 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3628 struct i40e_aqc_vsi_properties_data *info,
3629 uint8_t enabled_tcmap)
3631 enum i40e_status_code ret;
3632 int i, total_tc = 0;
3633 uint16_t qpnum_per_tc, bsf, qp_idx;
3635 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3636 if (ret != I40E_SUCCESS)
3639 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3640 if (enabled_tcmap & (1 << i))
3642 vsi->enabled_tc = enabled_tcmap;
3644 /* Number of queues per enabled TC */
3645 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3646 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3647 bsf = rte_bsf32(qpnum_per_tc);
3649 /* Adjust the queue number to actual queues that can be applied */
3650 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3651 vsi->nb_qps = qpnum_per_tc * total_tc;
3654 * Configure TC and queue mapping parameters, for enabled TC,
3655 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3656 * default queue will serve it.
3659 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3660 if (vsi->enabled_tc & (1 << i)) {
3661 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3662 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3663 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3664 qp_idx += qpnum_per_tc;
3666 info->tc_mapping[i] = 0;
3669 /* Associate queue number with VSI */
3670 if (vsi->type == I40E_VSI_SRIOV) {
3671 info->mapping_flags |=
3672 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3673 for (i = 0; i < vsi->nb_qps; i++)
3674 info->queue_mapping[i] =
3675 rte_cpu_to_le_16(vsi->base_queue + i);
3677 info->mapping_flags |=
3678 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3679 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3681 info->valid_sections |=
3682 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3684 return I40E_SUCCESS;
3688 i40e_veb_release(struct i40e_veb *veb)
3690 struct i40e_vsi *vsi;
3693 if (veb == NULL || veb->associate_vsi == NULL)
3696 if (!TAILQ_EMPTY(&veb->head)) {
3697 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3701 vsi = veb->associate_vsi;
3702 hw = I40E_VSI_TO_HW(vsi);
3704 vsi->uplink_seid = veb->uplink_seid;
3705 i40e_aq_delete_element(hw, veb->seid, NULL);
3708 return I40E_SUCCESS;
3712 static struct i40e_veb *
3713 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3715 struct i40e_veb *veb;
3719 if (NULL == pf || vsi == NULL) {
3720 PMD_DRV_LOG(ERR, "veb setup failed, "
3721 "associated VSI shouldn't null");
3724 hw = I40E_PF_TO_HW(pf);
3726 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3728 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3732 veb->associate_vsi = vsi;
3733 TAILQ_INIT(&veb->head);
3734 veb->uplink_seid = vsi->uplink_seid;
3736 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3737 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3739 if (ret != I40E_SUCCESS) {
3740 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3741 hw->aq.asq_last_status);
3745 /* get statistics index */
3746 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3747 &veb->stats_idx, NULL, NULL, NULL);
3748 if (ret != I40E_SUCCESS) {
3749 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3750 hw->aq.asq_last_status);
3754 /* Get VEB bandwidth, to be implemented */
3755 /* Now associated vsi binding to the VEB, set uplink to this VEB */
3756 vsi->uplink_seid = veb->seid;
3765 i40e_vsi_release(struct i40e_vsi *vsi)
3769 struct i40e_vsi_list *vsi_list;
3771 struct i40e_mac_filter *f;
3774 return I40E_SUCCESS;
3776 pf = I40E_VSI_TO_PF(vsi);
3777 hw = I40E_VSI_TO_HW(vsi);
3779 /* VSI has child to attach, release child first */
3781 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3782 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3784 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3786 i40e_veb_release(vsi->veb);
3789 /* Remove all macvlan filters of the VSI */
3790 i40e_vsi_remove_all_macvlan_filter(vsi);
3791 TAILQ_FOREACH(f, &vsi->mac_list, next)
3794 if (vsi->type != I40E_VSI_MAIN) {
3795 /* Remove vsi from parent's sibling list */
3796 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3797 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3798 return I40E_ERR_PARAM;
3800 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3801 &vsi->sib_vsi_list, list);
3803 /* Remove all switch element of the VSI */
3804 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3805 if (ret != I40E_SUCCESS)
3806 PMD_DRV_LOG(ERR, "Failed to delete element");
3808 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3810 if (vsi->type != I40E_VSI_SRIOV)
3811 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3814 return I40E_SUCCESS;
3818 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3820 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3821 struct i40e_aqc_remove_macvlan_element_data def_filter;
3822 struct i40e_mac_filter_info filter;
3825 if (vsi->type != I40E_VSI_MAIN)
3826 return I40E_ERR_CONFIG;
3827 memset(&def_filter, 0, sizeof(def_filter));
3828 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3830 def_filter.vlan_tag = 0;
3831 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3832 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3833 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3834 if (ret != I40E_SUCCESS) {
3835 struct i40e_mac_filter *f;
3836 struct ether_addr *mac;
3838 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3840 /* It needs to add the permanent mac into mac list */
3841 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3843 PMD_DRV_LOG(ERR, "failed to allocate memory");
3844 return I40E_ERR_NO_MEMORY;
3846 mac = &f->mac_info.mac_addr;
3847 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3849 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3850 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3855 (void)rte_memcpy(&filter.mac_addr,
3856 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3857 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3858 return i40e_vsi_add_mac(vsi, &filter);
3862 * i40e_vsi_get_bw_config - Query VSI BW Information
3863 * @vsi: the VSI to be queried
3865 * Returns 0 on success, negative value on failure
3867 static enum i40e_status_code
3868 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3870 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3871 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3872 struct i40e_hw *hw = &vsi->adapter->hw;
3877 memset(&bw_config, 0, sizeof(bw_config));
3878 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3879 if (ret != I40E_SUCCESS) {
3880 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3881 hw->aq.asq_last_status);
3885 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3886 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3887 &ets_sla_config, NULL);
3888 if (ret != I40E_SUCCESS) {
3889 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3890 "configuration %u", hw->aq.asq_last_status);
3894 /* store and print out BW info */
3895 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3896 vsi->bw_info.bw_max = bw_config.max_bw;
3897 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3898 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3899 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3900 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3902 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3903 vsi->bw_info.bw_ets_share_credits[i] =
3904 ets_sla_config.share_credits[i];
3905 vsi->bw_info.bw_ets_credits[i] =
3906 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3907 /* 4 bits per TC, 4th bit is reserved */
3908 vsi->bw_info.bw_ets_max[i] =
3909 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3910 RTE_LEN2MASK(3, uint8_t));
3911 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3912 vsi->bw_info.bw_ets_share_credits[i]);
3913 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3914 vsi->bw_info.bw_ets_credits[i]);
3915 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3916 vsi->bw_info.bw_ets_max[i]);
3919 return I40E_SUCCESS;
3922 /* i40e_enable_pf_lb
3923 * @pf: pointer to the pf structure
3925 * allow loopback on pf
3928 i40e_enable_pf_lb(struct i40e_pf *pf)
3930 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3931 struct i40e_vsi_context ctxt;
3934 /* Use the FW API if FW >= v5.0 */
3935 if (hw->aq.fw_maj_ver < 5) {
3936 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
3940 memset(&ctxt, 0, sizeof(ctxt));
3941 ctxt.seid = pf->main_vsi_seid;
3942 ctxt.pf_num = hw->pf_id;
3943 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3945 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
3946 ret, hw->aq.asq_last_status);
3949 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3950 ctxt.info.valid_sections =
3951 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3952 ctxt.info.switch_id |=
3953 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3955 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3957 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
3958 hw->aq.asq_last_status);
3963 i40e_vsi_setup(struct i40e_pf *pf,
3964 enum i40e_vsi_type type,
3965 struct i40e_vsi *uplink_vsi,
3966 uint16_t user_param)
3968 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3969 struct i40e_vsi *vsi;
3970 struct i40e_mac_filter_info filter;
3972 struct i40e_vsi_context ctxt;
3973 struct ether_addr broadcast =
3974 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3976 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3977 PMD_DRV_LOG(ERR, "VSI setup failed, "
3978 "VSI link shouldn't be NULL");
3982 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3983 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3984 "uplink VSI should be NULL");
3988 /* If uplink vsi didn't setup VEB, create one first */
3989 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3990 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3992 if (NULL == uplink_vsi->veb) {
3993 PMD_DRV_LOG(ERR, "VEB setup failed");
3996 /* set ALLOWLOOPBACk on pf, when veb is created */
3997 i40e_enable_pf_lb(pf);
4000 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4002 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4005 TAILQ_INIT(&vsi->mac_list);
4007 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4008 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4009 vsi->parent_vsi = uplink_vsi;
4010 vsi->user_param = user_param;
4011 /* Allocate queues */
4012 switch (vsi->type) {
4013 case I40E_VSI_MAIN :
4014 vsi->nb_qps = pf->lan_nb_qps;
4016 case I40E_VSI_SRIOV :
4017 vsi->nb_qps = pf->vf_nb_qps;
4019 case I40E_VSI_VMDQ2:
4020 vsi->nb_qps = pf->vmdq_nb_qps;
4023 vsi->nb_qps = pf->fdir_nb_qps;
4029 * The filter status descriptor is reported in rx queue 0,
4030 * while the tx queue for fdir filter programming has no
4031 * such constraints, can be non-zero queues.
4032 * To simplify it, choose FDIR vsi use queue 0 pair.
4033 * To make sure it will use queue 0 pair, queue allocation
4034 * need be done before this function is called
4036 if (type != I40E_VSI_FDIR) {
4037 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4039 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4043 vsi->base_queue = ret;
4045 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4047 /* VF has MSIX interrupt in VF range, don't allocate here */
4048 if (type == I40E_VSI_MAIN) {
4049 ret = i40e_res_pool_alloc(&pf->msix_pool,
4050 RTE_MIN(vsi->nb_qps,
4051 RTE_MAX_RXTX_INTR_VEC_ID));
4053 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4055 goto fail_queue_alloc;
4057 vsi->msix_intr = ret;
4058 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4059 } else if (type != I40E_VSI_SRIOV) {
4060 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4062 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4063 goto fail_queue_alloc;
4065 vsi->msix_intr = ret;
4073 if (type == I40E_VSI_MAIN) {
4074 /* For main VSI, no need to add since it's default one */
4075 vsi->uplink_seid = pf->mac_seid;
4076 vsi->seid = pf->main_vsi_seid;
4077 /* Bind queues with specific MSIX interrupt */
4079 * Needs 2 interrupt at least, one for misc cause which will
4080 * enabled from OS side, Another for queues binding the
4081 * interrupt from device side only.
4084 /* Get default VSI parameters from hardware */
4085 memset(&ctxt, 0, sizeof(ctxt));
4086 ctxt.seid = vsi->seid;
4087 ctxt.pf_num = hw->pf_id;
4088 ctxt.uplink_seid = vsi->uplink_seid;
4090 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4091 if (ret != I40E_SUCCESS) {
4092 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4093 goto fail_msix_alloc;
4095 (void)rte_memcpy(&vsi->info, &ctxt.info,
4096 sizeof(struct i40e_aqc_vsi_properties_data));
4097 vsi->vsi_id = ctxt.vsi_number;
4098 vsi->info.valid_sections = 0;
4100 /* Configure tc, enabled TC0 only */
4101 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4103 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4104 goto fail_msix_alloc;
4107 /* TC, queue mapping */
4108 memset(&ctxt, 0, sizeof(ctxt));
4109 vsi->info.valid_sections |=
4110 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4111 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4112 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4113 (void)rte_memcpy(&ctxt.info, &vsi->info,
4114 sizeof(struct i40e_aqc_vsi_properties_data));
4115 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4116 I40E_DEFAULT_TCMAP);
4117 if (ret != I40E_SUCCESS) {
4118 PMD_DRV_LOG(ERR, "Failed to configure "
4119 "TC queue mapping");
4120 goto fail_msix_alloc;
4122 ctxt.seid = vsi->seid;
4123 ctxt.pf_num = hw->pf_id;
4124 ctxt.uplink_seid = vsi->uplink_seid;
4127 /* Update VSI parameters */
4128 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4129 if (ret != I40E_SUCCESS) {
4130 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4131 goto fail_msix_alloc;
4134 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4135 sizeof(vsi->info.tc_mapping));
4136 (void)rte_memcpy(&vsi->info.queue_mapping,
4137 &ctxt.info.queue_mapping,
4138 sizeof(vsi->info.queue_mapping));
4139 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4140 vsi->info.valid_sections = 0;
4142 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4146 * Updating default filter settings are necessary to prevent
4147 * reception of tagged packets.
4148 * Some old firmware configurations load a default macvlan
4149 * filter which accepts both tagged and untagged packets.
4150 * The updating is to use a normal filter instead if needed.
4151 * For NVM 4.2.2 or after, the updating is not needed anymore.
4152 * The firmware with correct configurations load the default
4153 * macvlan filter which is expected and cannot be removed.
4155 i40e_update_default_filter_setting(vsi);
4156 i40e_config_qinq(hw, vsi);
4157 } else if (type == I40E_VSI_SRIOV) {
4158 memset(&ctxt, 0, sizeof(ctxt));
4160 * For other VSI, the uplink_seid equals to uplink VSI's
4161 * uplink_seid since they share same VEB
4163 vsi->uplink_seid = uplink_vsi->uplink_seid;
4164 ctxt.pf_num = hw->pf_id;
4165 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4166 ctxt.uplink_seid = vsi->uplink_seid;
4167 ctxt.connection_type = 0x1;
4168 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4170 /* Use the VEB configuration if FW >= v5.0 */
4171 if (hw->aq.fw_maj_ver >= 5) {
4172 /* Configure switch ID */
4173 ctxt.info.valid_sections |=
4174 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4175 ctxt.info.switch_id =
4176 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4179 /* Configure port/vlan */
4180 ctxt.info.valid_sections |=
4181 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4182 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4183 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4184 I40E_DEFAULT_TCMAP);
4185 if (ret != I40E_SUCCESS) {
4186 PMD_DRV_LOG(ERR, "Failed to configure "
4187 "TC queue mapping");
4188 goto fail_msix_alloc;
4190 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4191 ctxt.info.valid_sections |=
4192 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4194 * Since VSI is not created yet, only configure parameter,
4195 * will add vsi below.
4198 i40e_config_qinq(hw, vsi);
4199 } else if (type == I40E_VSI_VMDQ2) {
4200 memset(&ctxt, 0, sizeof(ctxt));
4202 * For other VSI, the uplink_seid equals to uplink VSI's
4203 * uplink_seid since they share same VEB
4205 vsi->uplink_seid = uplink_vsi->uplink_seid;
4206 ctxt.pf_num = hw->pf_id;
4208 ctxt.uplink_seid = vsi->uplink_seid;
4209 ctxt.connection_type = 0x1;
4210 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4212 ctxt.info.valid_sections |=
4213 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4214 /* user_param carries flag to enable loop back */
4216 ctxt.info.switch_id =
4217 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4218 ctxt.info.switch_id |=
4219 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4222 /* Configure port/vlan */
4223 ctxt.info.valid_sections |=
4224 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4225 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4226 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4227 I40E_DEFAULT_TCMAP);
4228 if (ret != I40E_SUCCESS) {
4229 PMD_DRV_LOG(ERR, "Failed to configure "
4230 "TC queue mapping");
4231 goto fail_msix_alloc;
4233 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4234 ctxt.info.valid_sections |=
4235 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4236 } else if (type == I40E_VSI_FDIR) {
4237 memset(&ctxt, 0, sizeof(ctxt));
4238 vsi->uplink_seid = uplink_vsi->uplink_seid;
4239 ctxt.pf_num = hw->pf_id;
4241 ctxt.uplink_seid = vsi->uplink_seid;
4242 ctxt.connection_type = 0x1; /* regular data port */
4243 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4244 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4245 I40E_DEFAULT_TCMAP);
4246 if (ret != I40E_SUCCESS) {
4247 PMD_DRV_LOG(ERR, "Failed to configure "
4248 "TC queue mapping.");
4249 goto fail_msix_alloc;
4251 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4252 ctxt.info.valid_sections |=
4253 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4255 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4256 goto fail_msix_alloc;
4259 if (vsi->type != I40E_VSI_MAIN) {
4260 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4261 if (ret != I40E_SUCCESS) {
4262 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4263 hw->aq.asq_last_status);
4264 goto fail_msix_alloc;
4266 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4267 vsi->info.valid_sections = 0;
4268 vsi->seid = ctxt.seid;
4269 vsi->vsi_id = ctxt.vsi_number;
4270 vsi->sib_vsi_list.vsi = vsi;
4271 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4272 &vsi->sib_vsi_list, list);
4275 /* MAC/VLAN configuration */
4276 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4277 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4279 ret = i40e_vsi_add_mac(vsi, &filter);
4280 if (ret != I40E_SUCCESS) {
4281 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4282 goto fail_msix_alloc;
4285 /* Get VSI BW information */
4286 i40e_vsi_get_bw_config(vsi);
4289 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4291 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4297 /* Configure vlan filter on or off */
4299 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4302 struct i40e_mac_filter *f;
4303 struct i40e_mac_filter_info *mac_filter;
4304 enum rte_mac_filter_type desired_filter;
4305 int ret = I40E_SUCCESS;
4308 /* Filter to match MAC and VLAN */
4309 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4311 /* Filter to match only MAC */
4312 desired_filter = RTE_MAC_PERFECT_MATCH;
4317 mac_filter = rte_zmalloc("mac_filter_info_data",
4318 num * sizeof(*mac_filter), 0);
4319 if (mac_filter == NULL) {
4320 PMD_DRV_LOG(ERR, "failed to allocate memory");
4321 return I40E_ERR_NO_MEMORY;
4326 /* Remove all existing mac */
4327 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4328 mac_filter[i] = f->mac_info;
4329 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4331 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4332 on ? "enable" : "disable");
4338 /* Override with new filter */
4339 for (i = 0; i < num; i++) {
4340 mac_filter[i].filter_type = desired_filter;
4341 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4343 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4344 on ? "enable" : "disable");
4350 rte_free(mac_filter);
4354 /* Configure vlan stripping on or off */
4356 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4358 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4359 struct i40e_vsi_context ctxt;
4361 int ret = I40E_SUCCESS;
4363 /* Check if it has been already on or off */
4364 if (vsi->info.valid_sections &
4365 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4367 if ((vsi->info.port_vlan_flags &
4368 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4369 return 0; /* already on */
4371 if ((vsi->info.port_vlan_flags &
4372 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4373 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4374 return 0; /* already off */
4379 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4381 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4382 vsi->info.valid_sections =
4383 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4384 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4385 vsi->info.port_vlan_flags |= vlan_flags;
4386 ctxt.seid = vsi->seid;
4387 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4388 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4390 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4391 on ? "enable" : "disable");
4397 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4399 struct rte_eth_dev_data *data = dev->data;
4403 /* Apply vlan offload setting */
4404 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4405 i40e_vlan_offload_set(dev, mask);
4407 /* Apply double-vlan setting, not implemented yet */
4409 /* Apply pvid setting */
4410 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4411 data->dev_conf.txmode.hw_vlan_insert_pvid);
4413 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4419 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4421 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4423 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4427 i40e_update_flow_control(struct i40e_hw *hw)
4429 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4430 struct i40e_link_status link_status;
4431 uint32_t rxfc = 0, txfc = 0, reg;
4435 memset(&link_status, 0, sizeof(link_status));
4436 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4437 if (ret != I40E_SUCCESS) {
4438 PMD_DRV_LOG(ERR, "Failed to get link status information");
4439 goto write_reg; /* Disable flow control */
4442 an_info = hw->phy.link_info.an_info;
4443 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4444 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4445 ret = I40E_ERR_NOT_READY;
4446 goto write_reg; /* Disable flow control */
4449 * If link auto negotiation is enabled, flow control needs to
4450 * be configured according to it
4452 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4453 case I40E_LINK_PAUSE_RXTX:
4456 hw->fc.current_mode = I40E_FC_FULL;
4458 case I40E_AQ_LINK_PAUSE_RX:
4460 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4462 case I40E_AQ_LINK_PAUSE_TX:
4464 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4467 hw->fc.current_mode = I40E_FC_NONE;
4472 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4473 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4474 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4475 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4476 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4477 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4484 i40e_pf_setup(struct i40e_pf *pf)
4486 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4487 struct i40e_filter_control_settings settings;
4488 struct i40e_vsi *vsi;
4491 /* Clear all stats counters */
4492 pf->offset_loaded = FALSE;
4493 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4494 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4496 ret = i40e_pf_get_switch_config(pf);
4497 if (ret != I40E_SUCCESS) {
4498 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4501 if (pf->flags & I40E_FLAG_FDIR) {
4502 /* make queue allocated first, let FDIR use queue pair 0*/
4503 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4504 if (ret != I40E_FDIR_QUEUE_ID) {
4505 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4507 pf->flags &= ~I40E_FLAG_FDIR;
4510 /* main VSI setup */
4511 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4513 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4514 return I40E_ERR_NOT_READY;
4518 /* Configure filter control */
4519 memset(&settings, 0, sizeof(settings));
4520 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4521 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4522 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4523 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4525 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4526 hw->func_caps.rss_table_size);
4527 return I40E_ERR_PARAM;
4529 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4530 "size: %u\n", hw->func_caps.rss_table_size);
4531 pf->hash_lut_size = hw->func_caps.rss_table_size;
4533 /* Enable ethtype and macvlan filters */
4534 settings.enable_ethtype = TRUE;
4535 settings.enable_macvlan = TRUE;
4536 ret = i40e_set_filter_control(hw, &settings);
4538 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4541 /* Update flow control according to the auto negotiation */
4542 i40e_update_flow_control(hw);
4544 return I40E_SUCCESS;
4548 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4554 * Set or clear TX Queue Disable flags,
4555 * which is required by hardware.
4557 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4558 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4560 /* Wait until the request is finished */
4561 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4562 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4563 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4564 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4565 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4571 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4572 return I40E_SUCCESS; /* already on, skip next steps */
4574 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4575 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4577 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4578 return I40E_SUCCESS; /* already off, skip next steps */
4579 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4581 /* Write the register */
4582 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4583 /* Check the result */
4584 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4585 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4586 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4588 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4589 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4592 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4593 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4597 /* Check if it is timeout */
4598 if (j >= I40E_CHK_Q_ENA_COUNT) {
4599 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4600 (on ? "enable" : "disable"), q_idx);
4601 return I40E_ERR_TIMEOUT;
4604 return I40E_SUCCESS;
4607 /* Swith on or off the tx queues */
4609 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4611 struct rte_eth_dev_data *dev_data = pf->dev_data;
4612 struct i40e_tx_queue *txq;
4613 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4617 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4618 txq = dev_data->tx_queues[i];
4619 /* Don't operate the queue if not configured or
4620 * if starting only per queue */
4621 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4624 ret = i40e_dev_tx_queue_start(dev, i);
4626 ret = i40e_dev_tx_queue_stop(dev, i);
4627 if ( ret != I40E_SUCCESS)
4631 return I40E_SUCCESS;
4635 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4640 /* Wait until the request is finished */
4641 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4642 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4643 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4644 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4645 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4650 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4651 return I40E_SUCCESS; /* Already on, skip next steps */
4652 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4654 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4655 return I40E_SUCCESS; /* Already off, skip next steps */
4656 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4659 /* Write the register */
4660 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4661 /* Check the result */
4662 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4663 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4664 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4666 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4667 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4670 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4671 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4676 /* Check if it is timeout */
4677 if (j >= I40E_CHK_Q_ENA_COUNT) {
4678 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4679 (on ? "enable" : "disable"), q_idx);
4680 return I40E_ERR_TIMEOUT;
4683 return I40E_SUCCESS;
4685 /* Switch on or off the rx queues */
4687 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4689 struct rte_eth_dev_data *dev_data = pf->dev_data;
4690 struct i40e_rx_queue *rxq;
4691 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4695 for (i = 0; i < dev_data->nb_rx_queues; i++) {
4696 rxq = dev_data->rx_queues[i];
4697 /* Don't operate the queue if not configured or
4698 * if starting only per queue */
4699 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4702 ret = i40e_dev_rx_queue_start(dev, i);
4704 ret = i40e_dev_rx_queue_stop(dev, i);
4705 if (ret != I40E_SUCCESS)
4709 return I40E_SUCCESS;
4712 /* Switch on or off all the rx/tx queues */
4714 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4719 /* enable rx queues before enabling tx queues */
4720 ret = i40e_dev_switch_rx_queues(pf, on);
4722 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4725 ret = i40e_dev_switch_tx_queues(pf, on);
4727 /* Stop tx queues before stopping rx queues */
4728 ret = i40e_dev_switch_tx_queues(pf, on);
4730 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4733 ret = i40e_dev_switch_rx_queues(pf, on);
4739 /* Initialize VSI for TX */
4741 i40e_dev_tx_init(struct i40e_pf *pf)
4743 struct rte_eth_dev_data *data = pf->dev_data;
4745 uint32_t ret = I40E_SUCCESS;
4746 struct i40e_tx_queue *txq;
4748 for (i = 0; i < data->nb_tx_queues; i++) {
4749 txq = data->tx_queues[i];
4750 if (!txq || !txq->q_set)
4752 ret = i40e_tx_queue_init(txq);
4753 if (ret != I40E_SUCCESS)
4756 if (ret == I40E_SUCCESS)
4757 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4763 /* Initialize VSI for RX */
4765 i40e_dev_rx_init(struct i40e_pf *pf)
4767 struct rte_eth_dev_data *data = pf->dev_data;
4768 int ret = I40E_SUCCESS;
4770 struct i40e_rx_queue *rxq;
4772 i40e_pf_config_mq_rx(pf);
4773 for (i = 0; i < data->nb_rx_queues; i++) {
4774 rxq = data->rx_queues[i];
4775 if (!rxq || !rxq->q_set)
4778 ret = i40e_rx_queue_init(rxq);
4779 if (ret != I40E_SUCCESS) {
4780 PMD_DRV_LOG(ERR, "Failed to do RX queue "
4785 if (ret == I40E_SUCCESS)
4786 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4793 i40e_dev_rxtx_init(struct i40e_pf *pf)
4797 err = i40e_dev_tx_init(pf);
4799 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4802 err = i40e_dev_rx_init(pf);
4804 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4812 i40e_vmdq_setup(struct rte_eth_dev *dev)
4814 struct rte_eth_conf *conf = &dev->data->dev_conf;
4815 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4816 int i, err, conf_vsis, j, loop;
4817 struct i40e_vsi *vsi;
4818 struct i40e_vmdq_info *vmdq_info;
4819 struct rte_eth_vmdq_rx_conf *vmdq_conf;
4820 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4823 * Disable interrupt to avoid message from VF. Furthermore, it will
4824 * avoid race condition in VSI creation/destroy.
4826 i40e_pf_disable_irq0(hw);
4828 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4829 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4833 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4834 if (conf_vsis > pf->max_nb_vmdq_vsi) {
4835 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4836 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4837 pf->max_nb_vmdq_vsi);
4841 if (pf->vmdq != NULL) {
4842 PMD_INIT_LOG(INFO, "VMDQ already configured");
4846 pf->vmdq = rte_zmalloc("vmdq_info_struct",
4847 sizeof(*vmdq_info) * conf_vsis, 0);
4849 if (pf->vmdq == NULL) {
4850 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4854 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4856 /* Create VMDQ VSI */
4857 for (i = 0; i < conf_vsis; i++) {
4858 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4859 vmdq_conf->enable_loop_back);
4861 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4865 vmdq_info = &pf->vmdq[i];
4867 vmdq_info->vsi = vsi;
4869 pf->nb_cfg_vmdq_vsi = conf_vsis;
4871 /* Configure Vlan */
4872 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4873 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4874 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4875 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4876 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4877 vmdq_conf->pool_map[i].vlan_id, j);
4879 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4880 vmdq_conf->pool_map[i].vlan_id);
4882 PMD_INIT_LOG(ERR, "Failed to add vlan");
4890 i40e_pf_enable_irq0(hw);
4895 for (i = 0; i < conf_vsis; i++)
4896 if (pf->vmdq[i].vsi == NULL)
4899 i40e_vsi_release(pf->vmdq[i].vsi);
4903 i40e_pf_enable_irq0(hw);
4908 i40e_stat_update_32(struct i40e_hw *hw,
4916 new_data = (uint64_t)I40E_READ_REG(hw, reg);
4920 if (new_data >= *offset)
4921 *stat = (uint64_t)(new_data - *offset);
4923 *stat = (uint64_t)((new_data +
4924 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4928 i40e_stat_update_48(struct i40e_hw *hw,
4937 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4938 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4939 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4944 if (new_data >= *offset)
4945 *stat = new_data - *offset;
4947 *stat = (uint64_t)((new_data +
4948 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4950 *stat &= I40E_48_BIT_MASK;
4955 i40e_pf_disable_irq0(struct i40e_hw *hw)
4957 /* Disable all interrupt types */
4958 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4959 I40E_WRITE_FLUSH(hw);
4964 i40e_pf_enable_irq0(struct i40e_hw *hw)
4966 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4967 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4968 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4969 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4970 I40E_WRITE_FLUSH(hw);
4974 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4976 /* read pending request and disable first */
4977 i40e_pf_disable_irq0(hw);
4978 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4979 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4980 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4983 /* Link no queues with irq0 */
4984 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4985 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4989 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4991 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4992 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4995 uint32_t index, offset, val;
5000 * Try to find which VF trigger a reset, use absolute VF id to access
5001 * since the reg is global register.
5003 for (i = 0; i < pf->vf_num; i++) {
5004 abs_vf_id = hw->func_caps.vf_base_id + i;
5005 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5006 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5007 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5008 /* VFR event occured */
5009 if (val & (0x1 << offset)) {
5012 /* Clear the event first */
5013 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5015 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5017 * Only notify a VF reset event occured,
5018 * don't trigger another SW reset
5020 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5021 if (ret != I40E_SUCCESS)
5022 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5028 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5030 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5031 struct i40e_arq_event_info info;
5032 uint16_t pending, opcode;
5035 info.buf_len = I40E_AQ_BUF_SZ;
5036 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5037 if (!info.msg_buf) {
5038 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5044 ret = i40e_clean_arq_element(hw, &info, &pending);
5046 if (ret != I40E_SUCCESS) {
5047 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5048 "aq_err: %u", hw->aq.asq_last_status);
5051 opcode = rte_le_to_cpu_16(info.desc.opcode);
5054 case i40e_aqc_opc_send_msg_to_pf:
5055 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5056 i40e_pf_host_handle_vf_msg(dev,
5057 rte_le_to_cpu_16(info.desc.retval),
5058 rte_le_to_cpu_32(info.desc.cookie_high),
5059 rte_le_to_cpu_32(info.desc.cookie_low),
5064 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5069 rte_free(info.msg_buf);
5073 * Interrupt handler is registered as the alarm callback for handling LSC
5074 * interrupt in a definite of time, in order to wait the NIC into a stable
5075 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5076 * no need for link down interrupt.
5079 i40e_dev_interrupt_delayed_handler(void *param)
5081 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5082 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5085 /* read interrupt causes again */
5086 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5088 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5089 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5090 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5091 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5092 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5093 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5094 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5095 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5096 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5097 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5098 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5100 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5101 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5102 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5103 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5104 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5106 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5107 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5108 i40e_dev_handle_vfr_event(dev);
5110 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5111 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5112 i40e_dev_handle_aq_msg(dev);
5115 /* handle the link up interrupt in an alarm callback */
5116 i40e_dev_link_update(dev, 0);
5117 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5119 i40e_pf_enable_irq0(hw);
5120 rte_intr_enable(&(dev->pci_dev->intr_handle));
5124 * Interrupt handler triggered by NIC for handling
5125 * specific interrupt.
5128 * Pointer to interrupt handle.
5130 * The address of parameter (struct rte_eth_dev *) regsitered before.
5136 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5139 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5140 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5143 /* Disable interrupt */
5144 i40e_pf_disable_irq0(hw);
5146 /* read out interrupt causes */
5147 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5149 /* No interrupt event indicated */
5150 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5151 PMD_DRV_LOG(INFO, "No interrupt event");
5154 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5155 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5156 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5157 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5158 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5159 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5160 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5161 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5162 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5163 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5164 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5165 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5166 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5167 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5168 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5169 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5171 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5172 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5173 i40e_dev_handle_vfr_event(dev);
5175 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5176 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5177 i40e_dev_handle_aq_msg(dev);
5180 /* Link Status Change interrupt */
5181 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5182 #define I40E_US_PER_SECOND 1000000
5183 struct rte_eth_link link;
5185 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5186 memset(&link, 0, sizeof(link));
5187 rte_i40e_dev_atomic_read_link_status(dev, &link);
5188 i40e_dev_link_update(dev, 0);
5191 * For link up interrupt, it needs to wait 1 second to let the
5192 * hardware be a stable state. Otherwise several consecutive
5193 * interrupts can be observed.
5194 * For link down interrupt, no need to wait.
5196 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5197 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5200 _rte_eth_dev_callback_process(dev,
5201 RTE_ETH_EVENT_INTR_LSC);
5205 /* Enable interrupt */
5206 i40e_pf_enable_irq0(hw);
5207 rte_intr_enable(&(dev->pci_dev->intr_handle));
5211 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5212 struct i40e_macvlan_filter *filter,
5215 int ele_num, ele_buff_size;
5216 int num, actual_num, i;
5218 int ret = I40E_SUCCESS;
5219 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5220 struct i40e_aqc_add_macvlan_element_data *req_list;
5222 if (filter == NULL || total == 0)
5223 return I40E_ERR_PARAM;
5224 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5225 ele_buff_size = hw->aq.asq_buf_size;
5227 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5228 if (req_list == NULL) {
5229 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5230 return I40E_ERR_NO_MEMORY;
5235 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5236 memset(req_list, 0, ele_buff_size);
5238 for (i = 0; i < actual_num; i++) {
5239 (void)rte_memcpy(req_list[i].mac_addr,
5240 &filter[num + i].macaddr, ETH_ADDR_LEN);
5241 req_list[i].vlan_tag =
5242 rte_cpu_to_le_16(filter[num + i].vlan_id);
5244 switch (filter[num + i].filter_type) {
5245 case RTE_MAC_PERFECT_MATCH:
5246 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5247 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5249 case RTE_MACVLAN_PERFECT_MATCH:
5250 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5252 case RTE_MAC_HASH_MATCH:
5253 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5254 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5256 case RTE_MACVLAN_HASH_MATCH:
5257 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5260 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5261 ret = I40E_ERR_PARAM;
5265 req_list[i].queue_number = 0;
5267 req_list[i].flags = rte_cpu_to_le_16(flags);
5270 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5272 if (ret != I40E_SUCCESS) {
5273 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5277 } while (num < total);
5285 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5286 struct i40e_macvlan_filter *filter,
5289 int ele_num, ele_buff_size;
5290 int num, actual_num, i;
5292 int ret = I40E_SUCCESS;
5293 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5294 struct i40e_aqc_remove_macvlan_element_data *req_list;
5296 if (filter == NULL || total == 0)
5297 return I40E_ERR_PARAM;
5299 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5300 ele_buff_size = hw->aq.asq_buf_size;
5302 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5303 if (req_list == NULL) {
5304 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5305 return I40E_ERR_NO_MEMORY;
5310 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5311 memset(req_list, 0, ele_buff_size);
5313 for (i = 0; i < actual_num; i++) {
5314 (void)rte_memcpy(req_list[i].mac_addr,
5315 &filter[num + i].macaddr, ETH_ADDR_LEN);
5316 req_list[i].vlan_tag =
5317 rte_cpu_to_le_16(filter[num + i].vlan_id);
5319 switch (filter[num + i].filter_type) {
5320 case RTE_MAC_PERFECT_MATCH:
5321 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5322 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5324 case RTE_MACVLAN_PERFECT_MATCH:
5325 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5327 case RTE_MAC_HASH_MATCH:
5328 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5329 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5331 case RTE_MACVLAN_HASH_MATCH:
5332 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5335 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5336 ret = I40E_ERR_PARAM;
5339 req_list[i].flags = rte_cpu_to_le_16(flags);
5342 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5344 if (ret != I40E_SUCCESS) {
5345 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5349 } while (num < total);
5356 /* Find out specific MAC filter */
5357 static struct i40e_mac_filter *
5358 i40e_find_mac_filter(struct i40e_vsi *vsi,
5359 struct ether_addr *macaddr)
5361 struct i40e_mac_filter *f;
5363 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5364 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5372 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5375 uint32_t vid_idx, vid_bit;
5377 if (vlan_id > ETH_VLAN_ID_MAX)
5380 vid_idx = I40E_VFTA_IDX(vlan_id);
5381 vid_bit = I40E_VFTA_BIT(vlan_id);
5383 if (vsi->vfta[vid_idx] & vid_bit)
5390 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5391 uint16_t vlan_id, bool on)
5393 uint32_t vid_idx, vid_bit;
5395 if (vlan_id > ETH_VLAN_ID_MAX)
5398 vid_idx = I40E_VFTA_IDX(vlan_id);
5399 vid_bit = I40E_VFTA_BIT(vlan_id);
5402 vsi->vfta[vid_idx] |= vid_bit;
5404 vsi->vfta[vid_idx] &= ~vid_bit;
5408 * Find all vlan options for specific mac addr,
5409 * return with actual vlan found.
5412 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5413 struct i40e_macvlan_filter *mv_f,
5414 int num, struct ether_addr *addr)
5420 * Not to use i40e_find_vlan_filter to decrease the loop time,
5421 * although the code looks complex.
5423 if (num < vsi->vlan_num)
5424 return I40E_ERR_PARAM;
5427 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5429 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5430 if (vsi->vfta[j] & (1 << k)) {
5432 PMD_DRV_LOG(ERR, "vlan number "
5434 return I40E_ERR_PARAM;
5436 (void)rte_memcpy(&mv_f[i].macaddr,
5437 addr, ETH_ADDR_LEN);
5439 j * I40E_UINT32_BIT_SIZE + k;
5445 return I40E_SUCCESS;
5449 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5450 struct i40e_macvlan_filter *mv_f,
5455 struct i40e_mac_filter *f;
5457 if (num < vsi->mac_num)
5458 return I40E_ERR_PARAM;
5460 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5462 PMD_DRV_LOG(ERR, "buffer number not match");
5463 return I40E_ERR_PARAM;
5465 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5467 mv_f[i].vlan_id = vlan;
5468 mv_f[i].filter_type = f->mac_info.filter_type;
5472 return I40E_SUCCESS;
5476 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5479 struct i40e_mac_filter *f;
5480 struct i40e_macvlan_filter *mv_f;
5481 int ret = I40E_SUCCESS;
5483 if (vsi == NULL || vsi->mac_num == 0)
5484 return I40E_ERR_PARAM;
5486 /* Case that no vlan is set */
5487 if (vsi->vlan_num == 0)
5490 num = vsi->mac_num * vsi->vlan_num;
5492 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5494 PMD_DRV_LOG(ERR, "failed to allocate memory");
5495 return I40E_ERR_NO_MEMORY;
5499 if (vsi->vlan_num == 0) {
5500 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5501 (void)rte_memcpy(&mv_f[i].macaddr,
5502 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5503 mv_f[i].vlan_id = 0;
5507 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5508 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5509 vsi->vlan_num, &f->mac_info.mac_addr);
5510 if (ret != I40E_SUCCESS)
5516 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5524 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5526 struct i40e_macvlan_filter *mv_f;
5528 int ret = I40E_SUCCESS;
5530 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5531 return I40E_ERR_PARAM;
5533 /* If it's already set, just return */
5534 if (i40e_find_vlan_filter(vsi,vlan))
5535 return I40E_SUCCESS;
5537 mac_num = vsi->mac_num;
5540 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5541 return I40E_ERR_PARAM;
5544 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5547 PMD_DRV_LOG(ERR, "failed to allocate memory");
5548 return I40E_ERR_NO_MEMORY;
5551 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5553 if (ret != I40E_SUCCESS)
5556 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5558 if (ret != I40E_SUCCESS)
5561 i40e_set_vlan_filter(vsi, vlan, 1);
5571 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5573 struct i40e_macvlan_filter *mv_f;
5575 int ret = I40E_SUCCESS;
5578 * Vlan 0 is the generic filter for untagged packets
5579 * and can't be removed.
5581 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5582 return I40E_ERR_PARAM;
5584 /* If can't find it, just return */
5585 if (!i40e_find_vlan_filter(vsi, vlan))
5586 return I40E_ERR_PARAM;
5588 mac_num = vsi->mac_num;
5591 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5592 return I40E_ERR_PARAM;
5595 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5598 PMD_DRV_LOG(ERR, "failed to allocate memory");
5599 return I40E_ERR_NO_MEMORY;
5602 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5604 if (ret != I40E_SUCCESS)
5607 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5609 if (ret != I40E_SUCCESS)
5612 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5613 if (vsi->vlan_num == 1) {
5614 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5615 if (ret != I40E_SUCCESS)
5618 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5619 if (ret != I40E_SUCCESS)
5623 i40e_set_vlan_filter(vsi, vlan, 0);
5633 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5635 struct i40e_mac_filter *f;
5636 struct i40e_macvlan_filter *mv_f;
5637 int i, vlan_num = 0;
5638 int ret = I40E_SUCCESS;
5640 /* If it's add and we've config it, return */
5641 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5643 return I40E_SUCCESS;
5644 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5645 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5648 * If vlan_num is 0, that's the first time to add mac,
5649 * set mask for vlan_id 0.
5651 if (vsi->vlan_num == 0) {
5652 i40e_set_vlan_filter(vsi, 0, 1);
5655 vlan_num = vsi->vlan_num;
5656 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5657 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5660 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5662 PMD_DRV_LOG(ERR, "failed to allocate memory");
5663 return I40E_ERR_NO_MEMORY;
5666 for (i = 0; i < vlan_num; i++) {
5667 mv_f[i].filter_type = mac_filter->filter_type;
5668 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5672 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5673 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5674 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5675 &mac_filter->mac_addr);
5676 if (ret != I40E_SUCCESS)
5680 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5681 if (ret != I40E_SUCCESS)
5684 /* Add the mac addr into mac list */
5685 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5687 PMD_DRV_LOG(ERR, "failed to allocate memory");
5688 ret = I40E_ERR_NO_MEMORY;
5691 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5693 f->mac_info.filter_type = mac_filter->filter_type;
5694 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5705 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5707 struct i40e_mac_filter *f;
5708 struct i40e_macvlan_filter *mv_f;
5710 enum rte_mac_filter_type filter_type;
5711 int ret = I40E_SUCCESS;
5713 /* Can't find it, return an error */
5714 f = i40e_find_mac_filter(vsi, addr);
5716 return I40E_ERR_PARAM;
5718 vlan_num = vsi->vlan_num;
5719 filter_type = f->mac_info.filter_type;
5720 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5721 filter_type == RTE_MACVLAN_HASH_MATCH) {
5722 if (vlan_num == 0) {
5723 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5724 return I40E_ERR_PARAM;
5726 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5727 filter_type == RTE_MAC_HASH_MATCH)
5730 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5732 PMD_DRV_LOG(ERR, "failed to allocate memory");
5733 return I40E_ERR_NO_MEMORY;
5736 for (i = 0; i < vlan_num; i++) {
5737 mv_f[i].filter_type = filter_type;
5738 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5741 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5742 filter_type == RTE_MACVLAN_HASH_MATCH) {
5743 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5744 if (ret != I40E_SUCCESS)
5748 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5749 if (ret != I40E_SUCCESS)
5752 /* Remove the mac addr into mac list */
5753 TAILQ_REMOVE(&vsi->mac_list, f, next);
5763 /* Configure hash enable flags for RSS */
5765 i40e_config_hena(uint64_t flags)
5772 if (flags & ETH_RSS_FRAG_IPV4)
5773 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5774 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5775 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5776 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5777 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5778 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5779 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5780 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5781 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5782 if (flags & ETH_RSS_FRAG_IPV6)
5783 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5784 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5785 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5786 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5787 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5788 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5789 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5790 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5791 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5792 if (flags & ETH_RSS_L2_PAYLOAD)
5793 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5798 /* Parse the hash enable flags */
5800 i40e_parse_hena(uint64_t flags)
5802 uint64_t rss_hf = 0;
5806 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5807 rss_hf |= ETH_RSS_FRAG_IPV4;
5808 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5809 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5810 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5811 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5812 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5813 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5814 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5815 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5816 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5817 rss_hf |= ETH_RSS_FRAG_IPV6;
5818 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5819 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5820 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5821 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5822 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5823 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5824 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5825 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5826 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5827 rss_hf |= ETH_RSS_L2_PAYLOAD;
5834 i40e_pf_disable_rss(struct i40e_pf *pf)
5836 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5839 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5840 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5841 hena &= ~I40E_RSS_HENA_ALL;
5842 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5843 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5844 I40E_WRITE_FLUSH(hw);
5848 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5850 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5851 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5854 if (!key || key_len == 0) {
5855 PMD_DRV_LOG(DEBUG, "No key to be configured");
5857 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5859 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5863 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5864 struct i40e_aqc_get_set_rss_key_data *key_dw =
5865 (struct i40e_aqc_get_set_rss_key_data *)key;
5867 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5869 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5872 uint32_t *hash_key = (uint32_t *)key;
5875 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5876 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5877 I40E_WRITE_FLUSH(hw);
5884 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5886 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5887 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5890 if (!key || !key_len)
5893 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5894 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5895 (struct i40e_aqc_get_set_rss_key_data *)key);
5897 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5901 uint32_t *key_dw = (uint32_t *)key;
5904 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5905 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
5907 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5913 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5915 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5920 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5921 rss_conf->rss_key_len);
5925 rss_hf = rss_conf->rss_hf;
5926 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5927 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5928 hena &= ~I40E_RSS_HENA_ALL;
5929 hena |= i40e_config_hena(rss_hf);
5930 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5931 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5932 I40E_WRITE_FLUSH(hw);
5938 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5939 struct rte_eth_rss_conf *rss_conf)
5941 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5942 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5943 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5946 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5947 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5948 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5949 if (rss_hf != 0) /* Enable RSS */
5951 return 0; /* Nothing to do */
5954 if (rss_hf == 0) /* Disable RSS */
5957 return i40e_hw_rss_hash_set(pf, rss_conf);
5961 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5962 struct rte_eth_rss_conf *rss_conf)
5964 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5965 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5968 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5969 &rss_conf->rss_key_len);
5971 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5972 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5973 rss_conf->rss_hf = i40e_parse_hena(hena);
5979 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5981 switch (filter_type) {
5982 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5983 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5985 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5986 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5988 case RTE_TUNNEL_FILTER_IMAC_TENID:
5989 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5991 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5992 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5994 case ETH_TUNNEL_FILTER_IMAC:
5995 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5997 case ETH_TUNNEL_FILTER_OIP:
5998 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6000 case ETH_TUNNEL_FILTER_IIP:
6001 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6004 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6012 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6013 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6017 uint8_t i, tun_type = 0;
6018 /* internal varialbe to convert ipv6 byte order */
6019 uint32_t convert_ipv6[4];
6021 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6022 struct i40e_vsi *vsi = pf->main_vsi;
6023 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6024 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6026 cld_filter = rte_zmalloc("tunnel_filter",
6027 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6030 if (NULL == cld_filter) {
6031 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6034 pfilter = cld_filter;
6036 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6037 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6039 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6040 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6041 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6042 rte_memcpy(&pfilter->ipaddr.v4.data,
6043 &rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv4_addr),
6044 sizeof(pfilter->ipaddr.v4.data));
6046 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6047 for (i = 0; i < 4; i++) {
6049 rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv6_addr[i]);
6051 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6052 sizeof(pfilter->ipaddr.v6.data));
6055 /* check tunneled type */
6056 switch (tunnel_filter->tunnel_type) {
6057 case RTE_TUNNEL_TYPE_VXLAN:
6058 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6060 case RTE_TUNNEL_TYPE_NVGRE:
6061 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6063 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6064 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6067 /* Other tunnel types is not supported. */
6068 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6069 rte_free(cld_filter);
6073 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6076 rte_free(cld_filter);
6080 pfilter->flags |= rte_cpu_to_le_16(
6081 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6082 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6083 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6084 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6087 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6089 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6092 rte_free(cld_filter);
6097 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6101 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6102 if (pf->vxlan_ports[i] == port)
6110 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6114 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6116 idx = i40e_get_vxlan_port_idx(pf, port);
6118 /* Check if port already exists */
6120 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6124 /* Now check if there is space to add the new port */
6125 idx = i40e_get_vxlan_port_idx(pf, 0);
6127 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6128 "not adding port %d", port);
6132 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6135 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6139 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6142 /* New port: add it and mark its index in the bitmap */
6143 pf->vxlan_ports[idx] = port;
6144 pf->vxlan_bitmap |= (1 << idx);
6146 if (!(pf->flags & I40E_FLAG_VXLAN))
6147 pf->flags |= I40E_FLAG_VXLAN;
6153 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6156 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6158 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6159 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6163 idx = i40e_get_vxlan_port_idx(pf, port);
6166 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6170 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6171 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6175 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6178 pf->vxlan_ports[idx] = 0;
6179 pf->vxlan_bitmap &= ~(1 << idx);
6181 if (!pf->vxlan_bitmap)
6182 pf->flags &= ~I40E_FLAG_VXLAN;
6187 /* Add UDP tunneling port */
6189 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6190 struct rte_eth_udp_tunnel *udp_tunnel)
6193 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6195 if (udp_tunnel == NULL)
6198 switch (udp_tunnel->prot_type) {
6199 case RTE_TUNNEL_TYPE_VXLAN:
6200 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6203 case RTE_TUNNEL_TYPE_GENEVE:
6204 case RTE_TUNNEL_TYPE_TEREDO:
6205 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6210 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6218 /* Remove UDP tunneling port */
6220 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6221 struct rte_eth_udp_tunnel *udp_tunnel)
6224 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6226 if (udp_tunnel == NULL)
6229 switch (udp_tunnel->prot_type) {
6230 case RTE_TUNNEL_TYPE_VXLAN:
6231 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6233 case RTE_TUNNEL_TYPE_GENEVE:
6234 case RTE_TUNNEL_TYPE_TEREDO:
6235 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6239 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6247 /* Calculate the maximum number of contiguous PF queues that are configured */
6249 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6251 struct rte_eth_dev_data *data = pf->dev_data;
6253 struct i40e_rx_queue *rxq;
6256 for (i = 0; i < pf->lan_nb_qps; i++) {
6257 rxq = data->rx_queues[i];
6258 if (rxq && rxq->q_set)
6269 i40e_pf_config_rss(struct i40e_pf *pf)
6271 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6272 struct rte_eth_rss_conf rss_conf;
6273 uint32_t i, lut = 0;
6277 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6278 * It's necessary to calulate the actual PF queues that are configured.
6280 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6281 num = i40e_pf_calc_configured_queues_num(pf);
6283 num = pf->dev_data->nb_rx_queues;
6285 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6286 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6290 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6294 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6297 lut = (lut << 8) | (j & ((0x1 <<
6298 hw->func_caps.rss_table_entry_width) - 1));
6300 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6303 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6304 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6305 i40e_pf_disable_rss(pf);
6308 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6309 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6310 /* Random default keys */
6311 static uint32_t rss_key_default[] = {0x6b793944,
6312 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6313 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6314 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6316 rss_conf.rss_key = (uint8_t *)rss_key_default;
6317 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6321 return i40e_hw_rss_hash_set(pf, &rss_conf);
6325 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6326 struct rte_eth_tunnel_filter_conf *filter)
6328 if (pf == NULL || filter == NULL) {
6329 PMD_DRV_LOG(ERR, "Invalid parameter");
6333 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6334 PMD_DRV_LOG(ERR, "Invalid queue ID");
6338 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6339 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6343 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6344 (is_zero_ether_addr(&filter->outer_mac))) {
6345 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6349 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6350 (is_zero_ether_addr(&filter->inner_mac))) {
6351 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6358 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6359 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6361 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6366 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6367 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6370 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6371 } else if (len == 4) {
6372 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6374 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6379 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6386 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6387 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6393 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6400 switch (cfg->cfg_type) {
6401 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6402 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6405 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6413 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6414 enum rte_filter_op filter_op,
6417 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6418 int ret = I40E_ERR_PARAM;
6420 switch (filter_op) {
6421 case RTE_ETH_FILTER_SET:
6422 ret = i40e_dev_global_config_set(hw,
6423 (struct rte_eth_global_cfg *)arg);
6426 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6434 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6435 enum rte_filter_op filter_op,
6438 struct rte_eth_tunnel_filter_conf *filter;
6439 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6440 int ret = I40E_SUCCESS;
6442 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6444 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6445 return I40E_ERR_PARAM;
6447 switch (filter_op) {
6448 case RTE_ETH_FILTER_NOP:
6449 if (!(pf->flags & I40E_FLAG_VXLAN))
6450 ret = I40E_NOT_SUPPORTED;
6452 case RTE_ETH_FILTER_ADD:
6453 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6455 case RTE_ETH_FILTER_DELETE:
6456 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6459 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6460 ret = I40E_ERR_PARAM;
6468 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6471 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6474 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6475 ret = i40e_pf_config_rss(pf);
6477 i40e_pf_disable_rss(pf);
6482 /* Get the symmetric hash enable configurations per port */
6484 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6486 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6488 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6491 /* Set the symmetric hash enable configurations per port */
6493 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6495 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6498 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6499 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6503 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6505 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6506 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6510 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6512 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6513 I40E_WRITE_FLUSH(hw);
6517 * Get global configurations of hash function type and symmetric hash enable
6518 * per flow type (pctype). Note that global configuration means it affects all
6519 * the ports on the same NIC.
6522 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6523 struct rte_eth_hash_global_conf *g_cfg)
6525 uint32_t reg, mask = I40E_FLOW_TYPES;
6527 enum i40e_filter_pctype pctype;
6529 memset(g_cfg, 0, sizeof(*g_cfg));
6530 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6531 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6532 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6534 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6535 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6536 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6538 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6539 if (!(mask & (1UL << i)))
6541 mask &= ~(1UL << i);
6542 /* Bit set indicats the coresponding flow type is supported */
6543 g_cfg->valid_bit_mask[0] |= (1UL << i);
6544 pctype = i40e_flowtype_to_pctype(i);
6545 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6546 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6547 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6554 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6557 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6559 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6560 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6561 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6562 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6568 * As i40e supports less than 32 flow types, only first 32 bits need to
6571 mask0 = g_cfg->valid_bit_mask[0];
6572 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6574 /* Check if any unsupported flow type configured */
6575 if ((mask0 | i40e_mask) ^ i40e_mask)
6578 if (g_cfg->valid_bit_mask[i])
6586 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6592 * Set global configurations of hash function type and symmetric hash enable
6593 * per flow type (pctype). Note any modifying global configuration will affect
6594 * all the ports on the same NIC.
6597 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6598 struct rte_eth_hash_global_conf *g_cfg)
6603 uint32_t mask0 = g_cfg->valid_bit_mask[0];
6604 enum i40e_filter_pctype pctype;
6606 /* Check the input parameters */
6607 ret = i40e_hash_global_config_check(g_cfg);
6611 for (i = 0; mask0 && i < UINT32_BIT; i++) {
6612 if (!(mask0 & (1UL << i)))
6614 mask0 &= ~(1UL << i);
6615 pctype = i40e_flowtype_to_pctype(i);
6616 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6617 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6618 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6621 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6622 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6624 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6625 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6629 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6630 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6632 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6633 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6637 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6639 /* Use the default, and keep it as it is */
6642 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6645 I40E_WRITE_FLUSH(hw);
6651 * Valid input sets for hash and flow director filters per PCTYPE
6654 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6655 enum rte_filter_type filter)
6659 static const uint64_t valid_hash_inset_table[] = {
6660 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6661 I40E_INSET_DMAC | I40E_INSET_SMAC |
6662 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6663 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6664 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6665 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6666 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6667 I40E_INSET_FLEX_PAYLOAD,
6668 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6669 I40E_INSET_DMAC | I40E_INSET_SMAC |
6670 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6671 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6672 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6673 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6674 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6675 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6676 I40E_INSET_FLEX_PAYLOAD,
6677 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6678 I40E_INSET_DMAC | I40E_INSET_SMAC |
6679 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6680 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6681 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6682 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6683 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6684 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6685 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6686 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6687 I40E_INSET_DMAC | I40E_INSET_SMAC |
6688 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6689 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6690 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6691 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6692 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6693 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6694 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6695 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6696 I40E_INSET_DMAC | I40E_INSET_SMAC |
6697 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6698 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6699 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6700 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6701 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6702 I40E_INSET_FLEX_PAYLOAD,
6703 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6704 I40E_INSET_DMAC | I40E_INSET_SMAC |
6705 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6706 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6707 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6708 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6709 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6710 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6711 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6712 I40E_INSET_DMAC | I40E_INSET_SMAC |
6713 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6714 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6715 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6716 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6717 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6718 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6719 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6720 I40E_INSET_DMAC | I40E_INSET_SMAC |
6721 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6722 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6723 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6724 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6725 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6726 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6727 I40E_INSET_FLEX_PAYLOAD,
6728 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6729 I40E_INSET_DMAC | I40E_INSET_SMAC |
6730 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6731 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6732 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6733 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6734 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6735 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6736 I40E_INSET_FLEX_PAYLOAD,
6737 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6738 I40E_INSET_DMAC | I40E_INSET_SMAC |
6739 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6740 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6741 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6742 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6743 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6744 I40E_INSET_FLEX_PAYLOAD,
6745 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6746 I40E_INSET_DMAC | I40E_INSET_SMAC |
6747 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6748 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6749 I40E_INSET_FLEX_PAYLOAD,
6753 * Flow director supports only fields defined in
6754 * union rte_eth_fdir_flow.
6756 static const uint64_t valid_fdir_inset_table[] = {
6757 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6758 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6759 I40E_INSET_FLEX_PAYLOAD,
6760 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6761 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6762 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6763 I40E_INSET_FLEX_PAYLOAD,
6764 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6765 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6766 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6767 I40E_INSET_FLEX_PAYLOAD,
6768 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6769 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6770 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6771 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6772 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6773 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6774 I40E_INSET_FLEX_PAYLOAD,
6775 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6776 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6777 I40E_INSET_FLEX_PAYLOAD,
6778 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6779 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6780 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6781 I40E_INSET_FLEX_PAYLOAD,
6782 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6783 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6784 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6785 I40E_INSET_FLEX_PAYLOAD,
6786 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6787 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6788 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6789 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6790 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6791 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6792 I40E_INSET_FLEX_PAYLOAD,
6793 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6794 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6797 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6799 if (filter == RTE_ETH_FILTER_HASH)
6800 valid = valid_hash_inset_table[pctype];
6802 valid = valid_fdir_inset_table[pctype];
6808 * Validate if the input set is allowed for a specific PCTYPE
6811 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6812 enum rte_filter_type filter, uint64_t inset)
6816 valid = i40e_get_valid_input_set(pctype, filter);
6817 if (inset & (~valid))
6823 /* default input set fields combination per pctype */
6825 i40e_get_default_input_set(uint16_t pctype)
6827 static const uint64_t default_inset_table[] = {
6828 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6829 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6830 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6831 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6832 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6833 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6834 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6835 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6836 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6837 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6838 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6840 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6841 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6842 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6843 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6844 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6845 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6846 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6847 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6848 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6849 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6850 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6851 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6852 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6854 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6855 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6856 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6857 I40E_INSET_LAST_ETHER_TYPE,
6860 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6863 return default_inset_table[pctype];
6867 * Parse the input set from index to logical bit masks
6870 i40e_parse_input_set(uint64_t *inset,
6871 enum i40e_filter_pctype pctype,
6872 enum rte_eth_input_set_field *field,
6878 static const struct {
6879 enum rte_eth_input_set_field field;
6881 } inset_convert_table[] = {
6882 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6883 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6884 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6885 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6886 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6887 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6888 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6889 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6890 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6891 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6892 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6893 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6894 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6895 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6896 I40E_INSET_IPV6_NEXT_HDR},
6897 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6898 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6899 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6900 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6901 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6902 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6903 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6904 I40E_INSET_SCTP_VT},
6905 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6906 I40E_INSET_TUNNEL_DMAC},
6907 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6908 I40E_INSET_VLAN_TUNNEL},
6909 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6910 I40E_INSET_TUNNEL_ID},
6911 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6912 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6913 I40E_INSET_FLEX_PAYLOAD_W1},
6914 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6915 I40E_INSET_FLEX_PAYLOAD_W2},
6916 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6917 I40E_INSET_FLEX_PAYLOAD_W3},
6918 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6919 I40E_INSET_FLEX_PAYLOAD_W4},
6920 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6921 I40E_INSET_FLEX_PAYLOAD_W5},
6922 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6923 I40E_INSET_FLEX_PAYLOAD_W6},
6924 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6925 I40E_INSET_FLEX_PAYLOAD_W7},
6926 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6927 I40E_INSET_FLEX_PAYLOAD_W8},
6930 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6933 /* Only one item allowed for default or all */
6935 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6936 *inset = i40e_get_default_input_set(pctype);
6938 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6939 *inset = I40E_INSET_NONE;
6944 for (i = 0, *inset = 0; i < size; i++) {
6945 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6946 if (field[i] == inset_convert_table[j].field) {
6947 *inset |= inset_convert_table[j].inset;
6952 /* It contains unsupported input set, return immediately */
6953 if (j == RTE_DIM(inset_convert_table))
6961 * Translate the input set from bit masks to register aware bit masks
6965 i40e_translate_input_set_reg(uint64_t input)
6970 static const struct {
6974 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6975 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6976 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6977 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6978 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6979 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6980 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6981 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6982 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6983 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6984 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6985 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6986 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6987 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6988 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6989 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6990 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6991 {I40E_INSET_TUNNEL_DMAC,
6992 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6993 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6994 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6995 {I40E_INSET_TUNNEL_SRC_PORT,
6996 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6997 {I40E_INSET_TUNNEL_DST_PORT,
6998 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6999 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7000 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7001 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7002 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7003 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7004 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7005 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7006 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7007 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7013 /* Translate input set to register aware inset */
7014 for (i = 0; i < RTE_DIM(inset_map); i++) {
7015 if (input & inset_map[i].inset)
7016 val |= inset_map[i].inset_reg;
7023 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7027 static const struct {
7030 } inset_mask_map[] = {
7031 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7032 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7033 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7034 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7037 if (!inset || !mask || !nb_elem)
7040 if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
7041 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
7043 return I40E_INSET_MASK_NUM_REG;
7046 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7049 if (inset & inset_mask_map[i].inset) {
7050 mask[idx] = inset_mask_map[i].mask;
7059 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
7060 enum i40e_filter_pctype pctype)
7064 if (filter == RTE_ETH_FILTER_HASH) {
7065 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7066 reg <<= I40E_32_BIT_WIDTH;
7067 reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7068 } else if (filter == RTE_ETH_FILTER_FDIR) {
7069 reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7070 reg <<= I40E_32_BIT_WIDTH;
7071 reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7078 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7080 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7082 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7084 i40e_write_rx_ctl(hw, addr, val);
7085 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7086 (uint32_t)i40e_read_rx_ctl(hw, addr));
7090 i40e_set_hash_inset_mask(struct i40e_hw *hw,
7091 enum i40e_filter_pctype pctype,
7092 enum rte_filter_input_set_op op,
7099 if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
7102 if (op == RTE_ETH_INPUT_SET_SELECT) {
7103 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7104 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7108 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7111 } else if (op == RTE_ETH_INPUT_SET_ADD) {
7112 uint8_t j, count = 0;
7114 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7115 reg = i40e_read_rx_ctl(hw,
7116 I40E_GLQF_HASH_MSK(i, pctype));
7117 if (reg & I40E_GLQF_HASH_MSK_MASK_MASK)
7120 if (count + num > I40E_INSET_MASK_NUM_REG)
7123 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
7124 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7132 i40e_set_fd_inset_mask(struct i40e_hw *hw,
7133 enum i40e_filter_pctype pctype,
7134 enum rte_filter_input_set_op op,
7141 if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
7144 if (op == RTE_ETH_INPUT_SET_SELECT) {
7145 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7146 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7150 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7153 } else if (op == RTE_ETH_INPUT_SET_ADD) {
7154 uint8_t j, count = 0;
7156 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7157 reg = i40e_read_rx_ctl(hw,
7158 I40E_GLQF_FD_MSK(i, pctype));
7159 if (reg & I40E_GLQF_FD_MSK_MASK_MASK)
7162 if (count + num > I40E_INSET_MASK_NUM_REG)
7165 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
7166 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7174 i40e_filter_inset_select(struct i40e_hw *hw,
7175 struct rte_eth_input_set_conf *conf,
7176 enum rte_filter_type filter)
7178 enum i40e_filter_pctype pctype;
7179 uint64_t inset_reg = 0, input_set;
7180 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
7185 PMD_DRV_LOG(ERR, "Invalid pointer");
7189 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7190 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7191 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7195 if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
7196 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7200 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7203 PMD_DRV_LOG(ERR, "Failed to parse input set");
7206 if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
7207 PMD_DRV_LOG(ERR, "Invalid input set");
7211 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7212 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
7213 } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
7214 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7217 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7218 I40E_INSET_MASK_NUM_REG);
7219 inset_reg |= i40e_translate_input_set_reg(input_set);
7221 if (filter == RTE_ETH_FILTER_HASH) {
7222 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
7227 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7228 (uint32_t)(inset_reg & UINT32_MAX));
7229 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7230 (uint32_t)((inset_reg >>
7231 I40E_32_BIT_WIDTH) & UINT32_MAX));
7232 } else if (filter == RTE_ETH_FILTER_FDIR) {
7233 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7238 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7239 (uint32_t)(inset_reg & UINT32_MAX));
7240 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7241 (uint32_t)((inset_reg >>
7242 I40E_32_BIT_WIDTH) & UINT32_MAX));
7244 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7247 I40E_WRITE_FLUSH(hw);
7253 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7258 PMD_DRV_LOG(ERR, "Invalid pointer");
7262 switch (info->info_type) {
7263 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7264 i40e_get_symmetric_hash_enable_per_port(hw,
7265 &(info->info.enable));
7267 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7268 ret = i40e_get_hash_filter_global_config(hw,
7269 &(info->info.global_conf));
7272 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7282 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7287 PMD_DRV_LOG(ERR, "Invalid pointer");
7291 switch (info->info_type) {
7292 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7293 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7295 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7296 ret = i40e_set_hash_filter_global_config(hw,
7297 &(info->info.global_conf));
7299 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7300 ret = i40e_filter_inset_select(hw,
7301 &(info->info.input_set_conf),
7302 RTE_ETH_FILTER_HASH);
7306 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7315 /* Operations for hash function */
7317 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7318 enum rte_filter_op filter_op,
7321 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7324 switch (filter_op) {
7325 case RTE_ETH_FILTER_NOP:
7327 case RTE_ETH_FILTER_GET:
7328 ret = i40e_hash_filter_get(hw,
7329 (struct rte_eth_hash_filter_info *)arg);
7331 case RTE_ETH_FILTER_SET:
7332 ret = i40e_hash_filter_set(hw,
7333 (struct rte_eth_hash_filter_info *)arg);
7336 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7346 * Configure ethertype filter, which can director packet by filtering
7347 * with mac address and ether_type or only ether_type
7350 i40e_ethertype_filter_set(struct i40e_pf *pf,
7351 struct rte_eth_ethertype_filter *filter,
7354 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7355 struct i40e_control_filter_stats stats;
7359 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7360 PMD_DRV_LOG(ERR, "Invalid queue ID");
7363 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7364 filter->ether_type == ETHER_TYPE_IPv6) {
7365 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7366 " control packet filter.", filter->ether_type);
7369 if (filter->ether_type == ETHER_TYPE_VLAN)
7370 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7373 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7374 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7375 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7376 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7377 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7379 memset(&stats, 0, sizeof(stats));
7380 ret = i40e_aq_add_rem_control_packet_filter(hw,
7381 filter->mac_addr.addr_bytes,
7382 filter->ether_type, flags,
7384 filter->queue, add, &stats, NULL);
7386 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7387 " mac_etype_used = %u, etype_used = %u,"
7388 " mac_etype_free = %u, etype_free = %u\n",
7389 ret, stats.mac_etype_used, stats.etype_used,
7390 stats.mac_etype_free, stats.etype_free);
7397 * Handle operations for ethertype filter.
7400 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7401 enum rte_filter_op filter_op,
7404 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7407 if (filter_op == RTE_ETH_FILTER_NOP)
7411 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7416 switch (filter_op) {
7417 case RTE_ETH_FILTER_ADD:
7418 ret = i40e_ethertype_filter_set(pf,
7419 (struct rte_eth_ethertype_filter *)arg,
7422 case RTE_ETH_FILTER_DELETE:
7423 ret = i40e_ethertype_filter_set(pf,
7424 (struct rte_eth_ethertype_filter *)arg,
7428 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7436 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7437 enum rte_filter_type filter_type,
7438 enum rte_filter_op filter_op,
7446 switch (filter_type) {
7447 case RTE_ETH_FILTER_NONE:
7448 /* For global configuration */
7449 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7451 case RTE_ETH_FILTER_HASH:
7452 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7454 case RTE_ETH_FILTER_MACVLAN:
7455 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7457 case RTE_ETH_FILTER_ETHERTYPE:
7458 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7460 case RTE_ETH_FILTER_TUNNEL:
7461 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7463 case RTE_ETH_FILTER_FDIR:
7464 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7467 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7477 * Check and enable Extended Tag.
7478 * Enabling Extended Tag is important for 40G performance.
7481 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7486 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7489 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7493 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7494 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7499 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7502 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7506 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7507 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7510 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7511 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7514 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7521 * As some registers wouldn't be reset unless a global hardware reset,
7522 * hardware initialization is needed to put those registers into an
7523 * expected initial state.
7526 i40e_hw_init(struct rte_eth_dev *dev)
7528 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7530 i40e_enable_extended_tag(dev);
7532 /* clear the PF Queue Filter control register */
7533 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7535 /* Disable symmetric hash per port */
7536 i40e_set_symmetric_hash_enable_per_port(hw, 0);
7539 enum i40e_filter_pctype
7540 i40e_flowtype_to_pctype(uint16_t flow_type)
7542 static const enum i40e_filter_pctype pctype_table[] = {
7543 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7544 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7545 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7546 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7547 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7548 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7549 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7550 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7551 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7552 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7553 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7554 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7555 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7556 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7557 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7558 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7559 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7560 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7561 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7564 return pctype_table[flow_type];
7568 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7570 static const uint16_t flowtype_table[] = {
7571 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7572 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7573 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7574 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7575 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7576 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7577 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7578 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7579 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7580 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7581 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7582 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7583 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7584 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7585 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7586 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7587 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7588 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7589 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7592 return flowtype_table[pctype];
7596 * On X710, performance number is far from the expectation on recent firmware
7597 * versions; on XL710, performance number is also far from the expectation on
7598 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7599 * mode is enabled and port MAC address is equal to the packet destination MAC
7600 * address. The fix for this issue may not be integrated in the following
7601 * firmware version. So the workaround in software driver is needed. It needs
7602 * to modify the initial values of 3 internal only registers for both X710 and
7603 * XL710. Note that the values for X710 or XL710 could be different, and the
7604 * workaround can be removed when it is fixed in firmware in the future.
7607 /* For both X710 and XL710 */
7608 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7609 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
7611 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7612 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
7615 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
7617 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
7618 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
7621 i40e_configure_registers(struct i40e_hw *hw)
7627 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7628 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7629 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7635 for (i = 0; i < RTE_DIM(reg_table); i++) {
7636 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7637 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7639 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7642 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7645 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7648 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7652 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7653 reg_table[i].addr, reg);
7654 if (reg == reg_table[i].val)
7657 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7658 reg_table[i].val, NULL);
7660 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7661 "address of 0x%"PRIx32, reg_table[i].val,
7665 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7666 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7670 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
7671 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
7672 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
7673 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7675 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7680 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7681 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7685 /* Configure for double VLAN RX stripping */
7686 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7687 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7688 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7689 ret = i40e_aq_debug_write_register(hw,
7690 I40E_VSI_TSR(vsi->vsi_id),
7693 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7695 return I40E_ERR_CONFIG;
7699 /* Configure for double VLAN TX insertion */
7700 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7701 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7702 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7703 ret = i40e_aq_debug_write_register(hw,
7704 I40E_VSI_L2TAGSTXVALID(
7705 vsi->vsi_id), reg, NULL);
7707 PMD_DRV_LOG(ERR, "Failed to update "
7708 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7709 return I40E_ERR_CONFIG;
7717 * i40e_aq_add_mirror_rule
7718 * @hw: pointer to the hardware structure
7719 * @seid: VEB seid to add mirror rule to
7720 * @dst_id: destination vsi seid
7721 * @entries: Buffer which contains the entities to be mirrored
7722 * @count: number of entities contained in the buffer
7723 * @rule_id:the rule_id of the rule to be added
7725 * Add a mirror rule for a given veb.
7728 static enum i40e_status_code
7729 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7730 uint16_t seid, uint16_t dst_id,
7731 uint16_t rule_type, uint16_t *entries,
7732 uint16_t count, uint16_t *rule_id)
7734 struct i40e_aq_desc desc;
7735 struct i40e_aqc_add_delete_mirror_rule cmd;
7736 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7737 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7740 enum i40e_status_code status;
7742 i40e_fill_default_direct_cmd_desc(&desc,
7743 i40e_aqc_opc_add_mirror_rule);
7744 memset(&cmd, 0, sizeof(cmd));
7746 buff_len = sizeof(uint16_t) * count;
7747 desc.datalen = rte_cpu_to_le_16(buff_len);
7749 desc.flags |= rte_cpu_to_le_16(
7750 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7751 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7752 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7753 cmd.num_entries = rte_cpu_to_le_16(count);
7754 cmd.seid = rte_cpu_to_le_16(seid);
7755 cmd.destination = rte_cpu_to_le_16(dst_id);
7757 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7758 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7759 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7761 " mirror_rules_used = %u, mirror_rules_free = %u,",
7762 hw->aq.asq_last_status, resp->rule_id,
7763 resp->mirror_rules_used, resp->mirror_rules_free);
7764 *rule_id = rte_le_to_cpu_16(resp->rule_id);
7770 * i40e_aq_del_mirror_rule
7771 * @hw: pointer to the hardware structure
7772 * @seid: VEB seid to add mirror rule to
7773 * @entries: Buffer which contains the entities to be mirrored
7774 * @count: number of entities contained in the buffer
7775 * @rule_id:the rule_id of the rule to be delete
7777 * Delete a mirror rule for a given veb.
7780 static enum i40e_status_code
7781 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7782 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7783 uint16_t count, uint16_t rule_id)
7785 struct i40e_aq_desc desc;
7786 struct i40e_aqc_add_delete_mirror_rule cmd;
7787 uint16_t buff_len = 0;
7788 enum i40e_status_code status;
7791 i40e_fill_default_direct_cmd_desc(&desc,
7792 i40e_aqc_opc_delete_mirror_rule);
7793 memset(&cmd, 0, sizeof(cmd));
7794 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7795 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7797 cmd.num_entries = count;
7798 buff_len = sizeof(uint16_t) * count;
7799 desc.datalen = rte_cpu_to_le_16(buff_len);
7800 buff = (void *)entries;
7802 /* rule id is filled in destination field for deleting mirror rule */
7803 cmd.destination = rte_cpu_to_le_16(rule_id);
7805 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7806 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7807 cmd.seid = rte_cpu_to_le_16(seid);
7809 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7810 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7816 * i40e_mirror_rule_set
7817 * @dev: pointer to the hardware structure
7818 * @mirror_conf: mirror rule info
7819 * @sw_id: mirror rule's sw_id
7820 * @on: enable/disable
7822 * set a mirror rule.
7826 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7827 struct rte_eth_mirror_conf *mirror_conf,
7828 uint8_t sw_id, uint8_t on)
7830 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7831 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7832 struct i40e_mirror_rule *it, *mirr_rule = NULL;
7833 struct i40e_mirror_rule *parent = NULL;
7834 uint16_t seid, dst_seid, rule_id;
7838 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7840 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7841 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7842 " without veb or vfs.");
7845 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7846 PMD_DRV_LOG(ERR, "mirror table is full.");
7849 if (mirror_conf->dst_pool > pf->vf_num) {
7850 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7851 mirror_conf->dst_pool);
7855 seid = pf->main_vsi->veb->seid;
7857 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7858 if (sw_id <= it->index) {
7864 if (mirr_rule && sw_id == mirr_rule->index) {
7866 PMD_DRV_LOG(ERR, "mirror rule exists.");
7869 ret = i40e_aq_del_mirror_rule(hw, seid,
7870 mirr_rule->rule_type,
7872 mirr_rule->num_entries, mirr_rule->id);
7874 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7875 " ret = %d, aq_err = %d.",
7876 ret, hw->aq.asq_last_status);
7879 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7880 rte_free(mirr_rule);
7881 pf->nb_mirror_rule--;
7885 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7889 mirr_rule = rte_zmalloc("i40e_mirror_rule",
7890 sizeof(struct i40e_mirror_rule) , 0);
7892 PMD_DRV_LOG(ERR, "failed to allocate memory");
7893 return I40E_ERR_NO_MEMORY;
7895 switch (mirror_conf->rule_type) {
7896 case ETH_MIRROR_VLAN:
7897 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7898 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7899 mirr_rule->entries[j] =
7900 mirror_conf->vlan.vlan_id[i];
7905 PMD_DRV_LOG(ERR, "vlan is not specified.");
7906 rte_free(mirr_rule);
7909 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7911 case ETH_MIRROR_VIRTUAL_POOL_UP:
7912 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7913 /* check if the specified pool bit is out of range */
7914 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7915 PMD_DRV_LOG(ERR, "pool mask is out of range.");
7916 rte_free(mirr_rule);
7919 for (i = 0, j = 0; i < pf->vf_num; i++) {
7920 if (mirror_conf->pool_mask & (1ULL << i)) {
7921 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7925 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7926 /* add pf vsi to entries */
7927 mirr_rule->entries[j] = pf->main_vsi_seid;
7931 PMD_DRV_LOG(ERR, "pool is not specified.");
7932 rte_free(mirr_rule);
7935 /* egress and ingress in aq commands means from switch but not port */
7936 mirr_rule->rule_type =
7937 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7938 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7939 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7941 case ETH_MIRROR_UPLINK_PORT:
7942 /* egress and ingress in aq commands means from switch but not port*/
7943 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7945 case ETH_MIRROR_DOWNLINK_PORT:
7946 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7949 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7950 mirror_conf->rule_type);
7951 rte_free(mirr_rule);
7955 /* If the dst_pool is equal to vf_num, consider it as PF */
7956 if (mirror_conf->dst_pool == pf->vf_num)
7957 dst_seid = pf->main_vsi_seid;
7959 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7961 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7962 mirr_rule->rule_type, mirr_rule->entries,
7965 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7966 " ret = %d, aq_err = %d.",
7967 ret, hw->aq.asq_last_status);
7968 rte_free(mirr_rule);
7972 mirr_rule->index = sw_id;
7973 mirr_rule->num_entries = j;
7974 mirr_rule->id = rule_id;
7975 mirr_rule->dst_vsi_seid = dst_seid;
7978 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7980 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7982 pf->nb_mirror_rule++;
7987 * i40e_mirror_rule_reset
7988 * @dev: pointer to the device
7989 * @sw_id: mirror rule's sw_id
7991 * reset a mirror rule.
7995 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7997 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7998 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7999 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8003 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8005 seid = pf->main_vsi->veb->seid;
8007 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8008 if (sw_id == it->index) {
8014 ret = i40e_aq_del_mirror_rule(hw, seid,
8015 mirr_rule->rule_type,
8017 mirr_rule->num_entries, mirr_rule->id);
8019 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8020 " status = %d, aq_err = %d.",
8021 ret, hw->aq.asq_last_status);
8024 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8025 rte_free(mirr_rule);
8026 pf->nb_mirror_rule--;
8028 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8035 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8037 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8038 uint64_t systim_cycles;
8040 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8041 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8044 return systim_cycles;
8048 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8050 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8053 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8054 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8061 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8063 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8066 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8067 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8074 i40e_start_timecounters(struct rte_eth_dev *dev)
8076 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8077 struct i40e_adapter *adapter =
8078 (struct i40e_adapter *)dev->data->dev_private;
8079 struct rte_eth_link link;
8080 uint32_t tsync_inc_l;
8081 uint32_t tsync_inc_h;
8083 /* Get current link speed. */
8084 memset(&link, 0, sizeof(link));
8085 i40e_dev_link_update(dev, 1);
8086 rte_i40e_dev_atomic_read_link_status(dev, &link);
8088 switch (link.link_speed) {
8089 case ETH_LINK_SPEED_40G:
8090 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8091 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8093 case ETH_LINK_SPEED_10G:
8094 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8095 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8097 case ETH_LINK_SPEED_1000:
8098 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8099 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8106 /* Set the timesync increment value. */
8107 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8108 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8110 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8111 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8112 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8114 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8115 adapter->systime_tc.cc_shift = 0;
8116 adapter->systime_tc.nsec_mask = 0;
8118 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8119 adapter->rx_tstamp_tc.cc_shift = 0;
8120 adapter->rx_tstamp_tc.nsec_mask = 0;
8122 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8123 adapter->tx_tstamp_tc.cc_shift = 0;
8124 adapter->tx_tstamp_tc.nsec_mask = 0;
8128 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8130 struct i40e_adapter *adapter =
8131 (struct i40e_adapter *)dev->data->dev_private;
8133 adapter->systime_tc.nsec += delta;
8134 adapter->rx_tstamp_tc.nsec += delta;
8135 adapter->tx_tstamp_tc.nsec += delta;
8141 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8144 struct i40e_adapter *adapter =
8145 (struct i40e_adapter *)dev->data->dev_private;
8147 ns = rte_timespec_to_ns(ts);
8149 /* Set the timecounters to a new value. */
8150 adapter->systime_tc.nsec = ns;
8151 adapter->rx_tstamp_tc.nsec = ns;
8152 adapter->tx_tstamp_tc.nsec = ns;
8158 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8160 uint64_t ns, systime_cycles;
8161 struct i40e_adapter *adapter =
8162 (struct i40e_adapter *)dev->data->dev_private;
8164 systime_cycles = i40e_read_systime_cyclecounter(dev);
8165 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8166 *ts = rte_ns_to_timespec(ns);
8172 i40e_timesync_enable(struct rte_eth_dev *dev)
8174 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8175 uint32_t tsync_ctl_l;
8176 uint32_t tsync_ctl_h;
8178 /* Stop the timesync system time. */
8179 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8180 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8181 /* Reset the timesync system time value. */
8182 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8183 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8185 i40e_start_timecounters(dev);
8187 /* Clear timesync registers. */
8188 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8189 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8190 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8191 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8192 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8193 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8195 /* Enable timestamping of PTP packets. */
8196 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8197 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8199 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8200 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8201 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8203 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8204 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8210 i40e_timesync_disable(struct rte_eth_dev *dev)
8212 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8213 uint32_t tsync_ctl_l;
8214 uint32_t tsync_ctl_h;
8216 /* Disable timestamping of transmitted PTP packets. */
8217 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8218 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8220 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8221 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8223 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8224 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8226 /* Reset the timesync increment value. */
8227 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8228 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8234 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8235 struct timespec *timestamp, uint32_t flags)
8237 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8238 struct i40e_adapter *adapter =
8239 (struct i40e_adapter *)dev->data->dev_private;
8241 uint32_t sync_status;
8242 uint32_t index = flags & 0x03;
8243 uint64_t rx_tstamp_cycles;
8246 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8247 if ((sync_status & (1 << index)) == 0)
8250 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8251 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8252 *timestamp = rte_ns_to_timespec(ns);
8258 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8259 struct timespec *timestamp)
8261 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8262 struct i40e_adapter *adapter =
8263 (struct i40e_adapter *)dev->data->dev_private;
8265 uint32_t sync_status;
8266 uint64_t tx_tstamp_cycles;
8269 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8270 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8273 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8274 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8275 *timestamp = rte_ns_to_timespec(ns);
8281 * i40e_parse_dcb_configure - parse dcb configure from user
8282 * @dev: the device being configured
8283 * @dcb_cfg: pointer of the result of parse
8284 * @*tc_map: bit map of enabled traffic classes
8286 * Returns 0 on success, negative value on failure
8289 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8290 struct i40e_dcbx_config *dcb_cfg,
8293 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8294 uint8_t i, tc_bw, bw_lf;
8296 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8298 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8299 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8300 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8304 /* assume each tc has the same bw */
8305 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8306 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8307 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8308 /* to ensure the sum of tcbw is equal to 100 */
8309 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8310 for (i = 0; i < bw_lf; i++)
8311 dcb_cfg->etscfg.tcbwtable[i]++;
8313 /* assume each tc has the same Transmission Selection Algorithm */
8314 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8315 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8317 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8318 dcb_cfg->etscfg.prioritytable[i] =
8319 dcb_rx_conf->dcb_tc[i];
8321 /* FW needs one App to configure HW */
8322 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8323 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8324 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8325 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8327 if (dcb_rx_conf->nb_tcs == 0)
8328 *tc_map = 1; /* tc0 only */
8330 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8332 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8333 dcb_cfg->pfc.willing = 0;
8334 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8335 dcb_cfg->pfc.pfcenable = *tc_map;
8341 static enum i40e_status_code
8342 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8343 struct i40e_aqc_vsi_properties_data *info,
8344 uint8_t enabled_tcmap)
8346 enum i40e_status_code ret;
8347 int i, total_tc = 0;
8348 uint16_t qpnum_per_tc, bsf, qp_idx;
8349 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8350 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8351 uint16_t used_queues;
8353 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8354 if (ret != I40E_SUCCESS)
8357 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8358 if (enabled_tcmap & (1 << i))
8363 vsi->enabled_tc = enabled_tcmap;
8365 /* different VSI has different queues assigned */
8366 if (vsi->type == I40E_VSI_MAIN)
8367 used_queues = dev_data->nb_rx_queues -
8368 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8369 else if (vsi->type == I40E_VSI_VMDQ2)
8370 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8372 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8373 return I40E_ERR_NO_AVAILABLE_VSI;
8376 qpnum_per_tc = used_queues / total_tc;
8377 /* Number of queues per enabled TC */
8378 if (qpnum_per_tc == 0) {
8379 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8380 return I40E_ERR_INVALID_QP_ID;
8382 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8384 bsf = rte_bsf32(qpnum_per_tc);
8387 * Configure TC and queue mapping parameters, for enabled TC,
8388 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8389 * default queue will serve it.
8392 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8393 if (vsi->enabled_tc & (1 << i)) {
8394 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8395 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8396 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8397 qp_idx += qpnum_per_tc;
8399 info->tc_mapping[i] = 0;
8402 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8403 if (vsi->type == I40E_VSI_SRIOV) {
8404 info->mapping_flags |=
8405 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8406 for (i = 0; i < vsi->nb_qps; i++)
8407 info->queue_mapping[i] =
8408 rte_cpu_to_le_16(vsi->base_queue + i);
8410 info->mapping_flags |=
8411 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8412 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8414 info->valid_sections |=
8415 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8417 return I40E_SUCCESS;
8421 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8422 * @veb: VEB to be configured
8423 * @tc_map: enabled TC bitmap
8425 * Returns 0 on success, negative value on failure
8427 static enum i40e_status_code
8428 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8430 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8431 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8432 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8433 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8434 enum i40e_status_code ret = I40E_SUCCESS;
8438 /* Check if enabled_tc is same as existing or new TCs */
8439 if (veb->enabled_tc == tc_map)
8442 /* configure tc bandwidth */
8443 memset(&veb_bw, 0, sizeof(veb_bw));
8444 veb_bw.tc_valid_bits = tc_map;
8445 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8446 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8447 if (tc_map & BIT_ULL(i))
8448 veb_bw.tc_bw_share_credits[i] = 1;
8450 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8453 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8454 " per TC failed = %d",
8455 hw->aq.asq_last_status);
8459 memset(&ets_query, 0, sizeof(ets_query));
8460 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8462 if (ret != I40E_SUCCESS) {
8463 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8464 " configuration %u", hw->aq.asq_last_status);
8467 memset(&bw_query, 0, sizeof(bw_query));
8468 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8470 if (ret != I40E_SUCCESS) {
8471 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8472 " configuration %u", hw->aq.asq_last_status);
8476 /* store and print out BW info */
8477 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8478 veb->bw_info.bw_max = ets_query.tc_bw_max;
8479 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8480 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8481 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8482 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8484 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8485 veb->bw_info.bw_ets_share_credits[i] =
8486 bw_query.tc_bw_share_credits[i];
8487 veb->bw_info.bw_ets_credits[i] =
8488 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8489 /* 4 bits per TC, 4th bit is reserved */
8490 veb->bw_info.bw_ets_max[i] =
8491 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8492 RTE_LEN2MASK(3, uint8_t));
8493 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8494 veb->bw_info.bw_ets_share_credits[i]);
8495 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8496 veb->bw_info.bw_ets_credits[i]);
8497 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8498 veb->bw_info.bw_ets_max[i]);
8501 veb->enabled_tc = tc_map;
8508 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8509 * @vsi: VSI to be configured
8510 * @tc_map: enabled TC bitmap
8512 * Returns 0 on success, negative value on failure
8514 static enum i40e_status_code
8515 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8517 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8518 struct i40e_vsi_context ctxt;
8519 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8520 enum i40e_status_code ret = I40E_SUCCESS;
8523 /* Check if enabled_tc is same as existing or new TCs */
8524 if (vsi->enabled_tc == tc_map)
8527 /* configure tc bandwidth */
8528 memset(&bw_data, 0, sizeof(bw_data));
8529 bw_data.tc_valid_bits = tc_map;
8530 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8531 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8532 if (tc_map & BIT_ULL(i))
8533 bw_data.tc_bw_credits[i] = 1;
8535 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8537 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8538 " per TC failed = %d",
8539 hw->aq.asq_last_status);
8542 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8543 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8545 /* Update Queue Pairs Mapping for currently enabled UPs */
8546 ctxt.seid = vsi->seid;
8547 ctxt.pf_num = hw->pf_id;
8549 ctxt.uplink_seid = vsi->uplink_seid;
8550 ctxt.info = vsi->info;
8552 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8556 /* Update the VSI after updating the VSI queue-mapping information */
8557 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8559 PMD_INIT_LOG(ERR, "Failed to configure "
8560 "TC queue mapping = %d",
8561 hw->aq.asq_last_status);
8564 /* update the local VSI info with updated queue map */
8565 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8566 sizeof(vsi->info.tc_mapping));
8567 (void)rte_memcpy(&vsi->info.queue_mapping,
8568 &ctxt.info.queue_mapping,
8569 sizeof(vsi->info.queue_mapping));
8570 vsi->info.mapping_flags = ctxt.info.mapping_flags;
8571 vsi->info.valid_sections = 0;
8573 /* query and update current VSI BW information */
8574 ret = i40e_vsi_get_bw_config(vsi);
8577 "Failed updating vsi bw info, err %s aq_err %s",
8578 i40e_stat_str(hw, ret),
8579 i40e_aq_str(hw, hw->aq.asq_last_status));
8583 vsi->enabled_tc = tc_map;
8590 * i40e_dcb_hw_configure - program the dcb setting to hw
8591 * @pf: pf the configuration is taken on
8592 * @new_cfg: new configuration
8593 * @tc_map: enabled TC bitmap
8595 * Returns 0 on success, negative value on failure
8597 static enum i40e_status_code
8598 i40e_dcb_hw_configure(struct i40e_pf *pf,
8599 struct i40e_dcbx_config *new_cfg,
8602 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8603 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8604 struct i40e_vsi *main_vsi = pf->main_vsi;
8605 struct i40e_vsi_list *vsi_list;
8606 enum i40e_status_code ret;
8610 /* Use the FW API if FW > v4.4*/
8611 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8612 (hw->aq.fw_maj_ver >= 5))) {
8613 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8614 " to configure DCB");
8615 return I40E_ERR_FIRMWARE_API_VERSION;
8618 /* Check if need reconfiguration */
8619 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8620 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8621 return I40E_SUCCESS;
8624 /* Copy the new config to the current config */
8625 *old_cfg = *new_cfg;
8626 old_cfg->etsrec = old_cfg->etscfg;
8627 ret = i40e_set_dcb_config(hw);
8630 "Set DCB Config failed, err %s aq_err %s\n",
8631 i40e_stat_str(hw, ret),
8632 i40e_aq_str(hw, hw->aq.asq_last_status));
8635 /* set receive Arbiter to RR mode and ETS scheme by default */
8636 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8637 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8638 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
8639 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8640 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8641 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8642 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8643 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8644 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8645 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8646 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8647 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8648 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8650 /* get local mib to check whether it is configured correctly */
8652 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8653 /* Get Local DCB Config */
8654 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8655 &hw->local_dcbx_config);
8657 /* if Veb is created, need to update TC of it at first */
8658 if (main_vsi->veb) {
8659 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8661 PMD_INIT_LOG(WARNING,
8662 "Failed configuring TC for VEB seid=%d\n",
8663 main_vsi->veb->seid);
8665 /* Update each VSI */
8666 i40e_vsi_config_tc(main_vsi, tc_map);
8667 if (main_vsi->veb) {
8668 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8669 /* Beside main VSI and VMDQ VSIs, only enable default
8672 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8673 ret = i40e_vsi_config_tc(vsi_list->vsi,
8676 ret = i40e_vsi_config_tc(vsi_list->vsi,
8677 I40E_DEFAULT_TCMAP);
8679 PMD_INIT_LOG(WARNING,
8680 "Failed configuring TC for VSI seid=%d\n",
8681 vsi_list->vsi->seid);
8685 return I40E_SUCCESS;
8689 * i40e_dcb_init_configure - initial dcb config
8690 * @dev: device being configured
8691 * @sw_dcb: indicate whether dcb is sw configured or hw offload
8693 * Returns 0 on success, negative value on failure
8696 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8698 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8699 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8702 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8703 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8707 /* DCB initialization:
8708 * Update DCB configuration from the Firmware and configure
8709 * LLDP MIB change event.
8711 if (sw_dcb == TRUE) {
8712 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8713 if (ret != I40E_SUCCESS)
8714 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8716 ret = i40e_init_dcb(hw);
8717 /* if sw_dcb, lldp agent is stopped, the return from
8718 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8721 if (ret != I40E_SUCCESS &&
8722 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8723 memset(&hw->local_dcbx_config, 0,
8724 sizeof(struct i40e_dcbx_config));
8725 /* set dcb default configuration */
8726 hw->local_dcbx_config.etscfg.willing = 0;
8727 hw->local_dcbx_config.etscfg.maxtcs = 0;
8728 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8729 hw->local_dcbx_config.etscfg.tsatable[0] =
8731 hw->local_dcbx_config.etsrec =
8732 hw->local_dcbx_config.etscfg;
8733 hw->local_dcbx_config.pfc.willing = 0;
8734 hw->local_dcbx_config.pfc.pfccap =
8735 I40E_MAX_TRAFFIC_CLASS;
8736 /* FW needs one App to configure HW */
8737 hw->local_dcbx_config.numapps = 1;
8738 hw->local_dcbx_config.app[0].selector =
8739 I40E_APP_SEL_ETHTYPE;
8740 hw->local_dcbx_config.app[0].priority = 3;
8741 hw->local_dcbx_config.app[0].protocolid =
8742 I40E_APP_PROTOID_FCOE;
8743 ret = i40e_set_dcb_config(hw);
8745 PMD_INIT_LOG(ERR, "default dcb config fails."
8746 " err = %d, aq_err = %d.", ret,
8747 hw->aq.asq_last_status);
8751 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8752 " aq_err = %d.", ret,
8753 hw->aq.asq_last_status);
8757 ret = i40e_aq_start_lldp(hw, NULL);
8758 if (ret != I40E_SUCCESS)
8759 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8761 ret = i40e_init_dcb(hw);
8763 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8764 PMD_INIT_LOG(ERR, "HW doesn't support"
8769 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8770 " aq_err = %d.", ret,
8771 hw->aq.asq_last_status);
8779 * i40e_dcb_setup - setup dcb related config
8780 * @dev: device being configured
8782 * Returns 0 on success, negative value on failure
8785 i40e_dcb_setup(struct rte_eth_dev *dev)
8787 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8788 struct i40e_dcbx_config dcb_cfg;
8792 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8793 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8797 if (pf->vf_num != 0)
8798 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8800 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8802 PMD_INIT_LOG(ERR, "invalid dcb config");
8805 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8807 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8815 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8816 struct rte_eth_dcb_info *dcb_info)
8818 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8819 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8820 struct i40e_vsi *vsi = pf->main_vsi;
8821 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8822 uint16_t bsf, tc_mapping;
8825 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8826 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8828 dcb_info->nb_tcs = 1;
8829 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8830 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8831 for (i = 0; i < dcb_info->nb_tcs; i++)
8832 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8836 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8837 if (!(vsi->enabled_tc & (1 << i)))
8839 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8840 /* only main vsi support multi TCs */
8841 dcb_info->tc_queue.tc_rxq[j][i].base =
8842 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8843 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8844 dcb_info->tc_queue.tc_txq[j][i].base =
8845 dcb_info->tc_queue.tc_rxq[j][i].base;
8846 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8847 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8848 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8849 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8850 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8852 vsi = pf->vmdq[j].vsi;
8854 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
8859 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8861 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8862 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8864 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8867 msix_intr = intr_handle->intr_vec[queue_id];
8868 if (msix_intr == I40E_MISC_VEC_ID)
8869 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8870 I40E_PFINT_DYN_CTLN_INTENA_MASK |
8871 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8872 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8874 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8877 I40E_PFINT_DYN_CTLN(msix_intr -
8879 I40E_PFINT_DYN_CTLN_INTENA_MASK |
8880 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8881 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8883 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8885 I40E_WRITE_FLUSH(hw);
8886 rte_intr_enable(&dev->pci_dev->intr_handle);
8892 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8894 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8895 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8898 msix_intr = intr_handle->intr_vec[queue_id];
8899 if (msix_intr == I40E_MISC_VEC_ID)
8900 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8903 I40E_PFINT_DYN_CTLN(msix_intr -
8906 I40E_WRITE_FLUSH(hw);
8911 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
8913 /* Highest base addr + 32-bit word */
8914 return I40E_GLGEN_STAT_CLEAR + 4;
8917 static int i40e_get_regs(struct rte_eth_dev *dev,
8918 struct rte_dev_reg_info *regs)
8920 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8921 uint32_t *ptr_data = regs->data;
8922 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
8923 const struct i40e_reg_info *reg_info;
8925 /* The first few registers have to be read using AQ operations */
8927 while (i40e_regs_adminq[reg_idx].name) {
8928 reg_info = &i40e_regs_adminq[reg_idx++];
8929 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
8931 arr_idx2 <= reg_info->count2;
8933 reg_offset = arr_idx * reg_info->stride1 +
8934 arr_idx2 * reg_info->stride2;
8935 ptr_data[reg_offset >> 2] =
8936 i40e_read_rx_ctl(hw, reg_offset);
8940 /* The remaining registers can be read using primitives */
8942 while (i40e_regs_others[reg_idx].name) {
8943 reg_info = &i40e_regs_others[reg_idx++];
8944 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
8946 arr_idx2 <= reg_info->count2;
8948 reg_offset = arr_idx * reg_info->stride1 +
8949 arr_idx2 * reg_info->stride2;
8950 ptr_data[reg_offset >> 2] =
8951 I40E_READ_REG(hw, reg_offset);
8958 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
8960 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8962 /* Convert word count to byte count */
8963 return hw->nvm.sr_size << 1;
8966 static int i40e_get_eeprom(struct rte_eth_dev *dev,
8967 struct rte_dev_eeprom_info *eeprom)
8969 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8970 uint16_t *data = eeprom->data;
8971 uint16_t offset, length, cnt_words;
8974 offset = eeprom->offset >> 1;
8975 length = eeprom->length >> 1;
8978 if (offset > hw->nvm.sr_size ||
8979 offset + length > hw->nvm.sr_size) {
8980 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
8984 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
8986 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
8987 if (ret_code != I40E_SUCCESS || cnt_words != length) {
8988 PMD_DRV_LOG(ERR, "EEPROM read failed.");
8995 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
8996 struct ether_addr *mac_addr)
8998 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9000 if (!is_valid_assigned_ether_addr(mac_addr)) {
9001 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9005 /* Flags: 0x3 updates port address */
9006 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);