4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
54 #include <rte_hash_crc.h>
56 #include "i40e_logs.h"
57 #include "base/i40e_prototype.h"
58 #include "base/i40e_adminq_cmd.h"
59 #include "base/i40e_type.h"
60 #include "base/i40e_register.h"
61 #include "base/i40e_dcb.h"
62 #include "i40e_ethdev.h"
63 #include "i40e_rxtx.h"
65 #include "i40e_regs.h"
66 #include "rte_pmd_i40e.h"
68 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
69 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
71 #define I40E_CLEAR_PXE_WAIT_MS 200
73 /* Maximun number of capability elements */
74 #define I40E_MAX_CAP_ELE_NUM 128
76 /* Wait count and inteval */
77 #define I40E_CHK_Q_ENA_COUNT 1000
78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
80 /* Maximun number of VSI */
81 #define I40E_MAX_NUM_VSIS (384UL)
83 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
85 /* Flow control default timer */
86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
88 /* Flow control default high water */
89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
91 /* Flow control default low water */
92 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
94 /* Flow control enable fwd bit */
95 #define I40E_PRTMAC_FWD_CTRL 0x00000001
97 /* Receive Packet Buffer size */
98 #define I40E_RXPBSIZE (968 * 1024)
100 /* Kilobytes shift */
101 #define I40E_KILOSHIFT 10
103 /* Receive Average Packet Size in Byte*/
104 #define I40E_PACKET_AVERAGE_SIZE 128
106 /* Mask of PF interrupt causes */
107 #define I40E_PFINT_ICR0_ENA_MASK ( \
108 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
109 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
110 I40E_PFINT_ICR0_ENA_GRST_MASK | \
111 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
112 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
113 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
114 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
115 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
116 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
118 #define I40E_FLOW_TYPES ( \
119 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
124 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
129 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
131 /* Additional timesync values. */
132 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
133 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
134 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
135 #define I40E_PRTTSYN_TSYNENA 0x80000000
136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
137 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
139 #define I40E_MAX_PERCENT 100
140 #define I40E_DEFAULT_DCB_APP_NUM 1
141 #define I40E_DEFAULT_DCB_APP_PRIO 3
144 * Below are values for writing un-exposed registers suggested
147 /* Destination MAC address */
148 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
149 /* Source MAC address */
150 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
152 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
154 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
155 /* Single VLAN tag in the inner L2 header */
156 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
157 /* Source IPv4 address */
158 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
159 /* Destination IPv4 address */
160 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
161 /* Source IPv4 address for X722 */
162 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
163 /* Destination IPv4 address for X722 */
164 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
165 /* IPv4 Protocol for X722 */
166 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
167 /* IPv4 Time to Live for X722 */
168 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
169 /* IPv4 Type of Service (TOS) */
170 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
172 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
173 /* IPv4 Time to Live */
174 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
175 /* Source IPv6 address */
176 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
177 /* Destination IPv6 address */
178 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
179 /* IPv6 Traffic Class (TC) */
180 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
181 /* IPv6 Next Header */
182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
186 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
187 /* Destination L4 port */
188 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
189 /* SCTP verification tag */
190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
193 /* Source port of tunneling UDP */
194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
195 /* Destination port of tunneling UDP */
196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
197 /* UDP Tunneling ID, NVGRE/GRE key */
198 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
199 /* Last ether type */
200 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
201 /* Tunneling outer destination IPv4 address */
202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
203 /* Tunneling outer destination IPv6 address */
204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
205 /* 1st word of flex payload */
206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
207 /* 2nd word of flex payload */
208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
209 /* 3rd word of flex payload */
210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
211 /* 4th word of flex payload */
212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
213 /* 5th word of flex payload */
214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
215 /* 6th word of flex payload */
216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
217 /* 7th word of flex payload */
218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
219 /* 8th word of flex payload */
220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
221 /* all 8 words flex payload */
222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
223 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
225 #define I40E_TRANSLATE_INSET 0
226 #define I40E_TRANSLATE_REG 1
228 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
229 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
230 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
231 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
233 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
235 /* PCI offset for querying capability */
236 #define PCI_DEV_CAP_REG 0xA4
237 /* PCI offset for enabling/disabling Extended Tag */
238 #define PCI_DEV_CTRL_REG 0xA8
239 /* Bit mask of Extended Tag capability */
240 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
241 /* Bit shift of Extended Tag enable/disable */
242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
243 /* Bit mask of Extended Tag enable/disable */
244 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
246 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
247 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
248 static int i40e_dev_configure(struct rte_eth_dev *dev);
249 static int i40e_dev_start(struct rte_eth_dev *dev);
250 static void i40e_dev_stop(struct rte_eth_dev *dev);
251 static void i40e_dev_close(struct rte_eth_dev *dev);
252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
258 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
259 struct rte_eth_stats *stats);
260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
261 struct rte_eth_xstat *xstats, unsigned n);
262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
263 struct rte_eth_xstat_name *xstats_names,
265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
271 char *fw_version, size_t fw_size);
272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
273 struct rte_eth_dev_info *dev_info);
274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
278 enum rte_vlan_type vlan_type,
280 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
288 struct rte_eth_fc_conf *fc_conf);
289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
290 struct rte_eth_fc_conf *fc_conf);
291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
292 struct rte_eth_pfc_conf *pfc_conf);
293 static void i40e_macaddr_add(struct rte_eth_dev *dev,
294 struct ether_addr *mac_addr,
297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
299 struct rte_eth_rss_reta_entry64 *reta_conf,
301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
302 struct rte_eth_rss_reta_entry64 *reta_conf,
305 static int i40e_get_cap(struct i40e_hw *hw);
306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
307 static int i40e_pf_setup(struct i40e_pf *pf);
308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
310 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
311 static int i40e_dcb_setup(struct rte_eth_dev *dev);
312 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
313 bool offset_loaded, uint64_t *offset, uint64_t *stat);
314 static void i40e_stat_update_48(struct i40e_hw *hw,
320 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
321 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
324 uint32_t base, uint32_t num);
325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
331 static int i40e_veb_release(struct i40e_veb *veb);
332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
333 struct i40e_vsi *vsi);
334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
336 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
337 struct i40e_macvlan_filter *mv_f,
339 struct ether_addr *addr);
340 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
341 struct i40e_macvlan_filter *mv_f,
344 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
345 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
346 struct rte_eth_rss_conf *rss_conf);
347 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
348 struct rte_eth_rss_conf *rss_conf);
349 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
350 struct rte_eth_udp_tunnel *udp_tunnel);
351 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
352 struct rte_eth_udp_tunnel *udp_tunnel);
353 static void i40e_filter_input_set_init(struct i40e_pf *pf);
354 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
355 enum rte_filter_op filter_op,
357 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
358 enum rte_filter_type filter_type,
359 enum rte_filter_op filter_op,
361 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
362 struct rte_eth_dcb_info *dcb_info);
363 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
364 static void i40e_configure_registers(struct i40e_hw *hw);
365 static void i40e_hw_init(struct rte_eth_dev *dev);
366 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
368 struct rte_eth_mirror_conf *mirror_conf,
369 uint8_t sw_id, uint8_t on);
370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
375 struct timespec *timestamp,
377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
378 struct timespec *timestamp);
379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
384 struct timespec *timestamp);
385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
386 const struct timespec *timestamp);
388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
393 static int i40e_get_regs(struct rte_eth_dev *dev,
394 struct rte_dev_reg_info *regs);
396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
399 struct rte_dev_eeprom_info *eeprom);
401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
402 struct ether_addr *mac_addr);
404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
406 static int i40e_ethertype_filter_convert(
407 const struct rte_eth_ethertype_filter *input,
408 struct i40e_ethertype_filter *filter);
409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
410 struct i40e_ethertype_filter *filter);
412 static int i40e_tunnel_filter_convert(
413 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
414 struct i40e_tunnel_filter *tunnel_filter);
415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
416 struct i40e_tunnel_filter *tunnel_filter);
418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
420 static void i40e_filter_restore(struct i40e_pf *pf);
422 static const struct rte_pci_id pci_id_i40e_map[] = {
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
443 { .vendor_id = 0, /* sentinel */ },
446 static const struct eth_dev_ops i40e_eth_dev_ops = {
447 .dev_configure = i40e_dev_configure,
448 .dev_start = i40e_dev_start,
449 .dev_stop = i40e_dev_stop,
450 .dev_close = i40e_dev_close,
451 .promiscuous_enable = i40e_dev_promiscuous_enable,
452 .promiscuous_disable = i40e_dev_promiscuous_disable,
453 .allmulticast_enable = i40e_dev_allmulticast_enable,
454 .allmulticast_disable = i40e_dev_allmulticast_disable,
455 .dev_set_link_up = i40e_dev_set_link_up,
456 .dev_set_link_down = i40e_dev_set_link_down,
457 .link_update = i40e_dev_link_update,
458 .stats_get = i40e_dev_stats_get,
459 .xstats_get = i40e_dev_xstats_get,
460 .xstats_get_names = i40e_dev_xstats_get_names,
461 .stats_reset = i40e_dev_stats_reset,
462 .xstats_reset = i40e_dev_stats_reset,
463 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
464 .fw_version_get = i40e_fw_version_get,
465 .dev_infos_get = i40e_dev_info_get,
466 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
467 .vlan_filter_set = i40e_vlan_filter_set,
468 .vlan_tpid_set = i40e_vlan_tpid_set,
469 .vlan_offload_set = i40e_vlan_offload_set,
470 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
471 .vlan_pvid_set = i40e_vlan_pvid_set,
472 .rx_queue_start = i40e_dev_rx_queue_start,
473 .rx_queue_stop = i40e_dev_rx_queue_stop,
474 .tx_queue_start = i40e_dev_tx_queue_start,
475 .tx_queue_stop = i40e_dev_tx_queue_stop,
476 .rx_queue_setup = i40e_dev_rx_queue_setup,
477 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
478 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
479 .rx_queue_release = i40e_dev_rx_queue_release,
480 .rx_queue_count = i40e_dev_rx_queue_count,
481 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
482 .tx_queue_setup = i40e_dev_tx_queue_setup,
483 .tx_queue_release = i40e_dev_tx_queue_release,
484 .dev_led_on = i40e_dev_led_on,
485 .dev_led_off = i40e_dev_led_off,
486 .flow_ctrl_get = i40e_flow_ctrl_get,
487 .flow_ctrl_set = i40e_flow_ctrl_set,
488 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
489 .mac_addr_add = i40e_macaddr_add,
490 .mac_addr_remove = i40e_macaddr_remove,
491 .reta_update = i40e_dev_rss_reta_update,
492 .reta_query = i40e_dev_rss_reta_query,
493 .rss_hash_update = i40e_dev_rss_hash_update,
494 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
495 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
496 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
497 .filter_ctrl = i40e_dev_filter_ctrl,
498 .rxq_info_get = i40e_rxq_info_get,
499 .txq_info_get = i40e_txq_info_get,
500 .mirror_rule_set = i40e_mirror_rule_set,
501 .mirror_rule_reset = i40e_mirror_rule_reset,
502 .timesync_enable = i40e_timesync_enable,
503 .timesync_disable = i40e_timesync_disable,
504 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
505 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
506 .get_dcb_info = i40e_dev_get_dcb_info,
507 .timesync_adjust_time = i40e_timesync_adjust_time,
508 .timesync_read_time = i40e_timesync_read_time,
509 .timesync_write_time = i40e_timesync_write_time,
510 .get_reg = i40e_get_regs,
511 .get_eeprom_length = i40e_get_eeprom_length,
512 .get_eeprom = i40e_get_eeprom,
513 .mac_addr_set = i40e_set_default_mac_addr,
514 .mtu_set = i40e_dev_mtu_set,
517 /* store statistics names and its offset in stats structure */
518 struct rte_i40e_xstats_name_off {
519 char name[RTE_ETH_XSTATS_NAME_SIZE];
523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
524 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
525 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
526 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
527 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
528 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
529 rx_unknown_protocol)},
530 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
531 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
532 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
533 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
537 sizeof(rte_i40e_stats_strings[0]))
539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
540 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
541 tx_dropped_link_down)},
542 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
543 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
545 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
546 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
548 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
550 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
552 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
553 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
554 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
555 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
556 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
557 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
559 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
571 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
573 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
574 mac_short_packet_dropped)},
575 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
577 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
578 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
579 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
581 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
583 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
591 {"rx_flow_director_atr_match_packets",
592 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
593 {"rx_flow_director_sb_match_packets",
594 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
595 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
597 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
599 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
601 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
606 sizeof(rte_i40e_hw_port_strings[0]))
608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
609 {"xon_packets", offsetof(struct i40e_hw_port_stats,
611 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
616 sizeof(rte_i40e_rxq_prio_strings[0]))
618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
619 {"xon_packets", offsetof(struct i40e_hw_port_stats,
621 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
623 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
624 priority_xon_2_xoff)},
627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
628 sizeof(rte_i40e_txq_prio_strings[0]))
630 static struct eth_driver rte_i40e_pmd = {
632 .id_table = pci_id_i40e_map,
633 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
634 .probe = rte_eth_dev_pci_probe,
635 .remove = rte_eth_dev_pci_remove,
637 .eth_dev_init = eth_i40e_dev_init,
638 .eth_dev_uninit = eth_i40e_dev_uninit,
639 .dev_private_size = sizeof(struct i40e_adapter),
643 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
644 struct rte_eth_link *link)
646 struct rte_eth_link *dst = link;
647 struct rte_eth_link *src = &(dev->data->dev_link);
649 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
650 *(uint64_t *)src) == 0)
657 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
658 struct rte_eth_link *link)
660 struct rte_eth_link *dst = &(dev->data->dev_link);
661 struct rte_eth_link *src = link;
663 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
664 *(uint64_t *)src) == 0)
670 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
671 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
672 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
674 #ifndef I40E_GLQF_ORT
675 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
677 #ifndef I40E_GLQF_PIT
678 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
681 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
684 * Initialize registers for flexible payload, which should be set by NVM.
685 * This should be removed from code once it is fixed in NVM.
687 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
688 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
689 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
690 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
691 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
692 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
693 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
694 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
695 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
696 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
697 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
698 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
700 /* Initialize registers for parsing packet type of QinQ */
701 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
702 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
705 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
708 * Add a ethertype filter to drop all flow control frames transmitted
712 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
714 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
715 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
716 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
717 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
720 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
721 I40E_FLOW_CONTROL_ETHERTYPE, flags,
722 pf->main_vsi_seid, 0,
726 "Failed to add filter to drop flow control frames from VSIs.");
730 floating_veb_list_handler(__rte_unused const char *key,
731 const char *floating_veb_value,
735 unsigned int count = 0;
738 bool *vf_floating_veb = opaque;
740 while (isblank(*floating_veb_value))
741 floating_veb_value++;
743 /* Reset floating VEB configuration for VFs */
744 for (idx = 0; idx < I40E_MAX_VF; idx++)
745 vf_floating_veb[idx] = false;
749 while (isblank(*floating_veb_value))
750 floating_veb_value++;
751 if (*floating_veb_value == '\0')
754 idx = strtoul(floating_veb_value, &end, 10);
755 if (errno || end == NULL)
757 while (isblank(*end))
761 } else if ((*end == ';') || (*end == '\0')) {
763 if (min == I40E_MAX_VF)
765 if (max >= I40E_MAX_VF)
766 max = I40E_MAX_VF - 1;
767 for (idx = min; idx <= max; idx++) {
768 vf_floating_veb[idx] = true;
775 floating_veb_value = end + 1;
776 } while (*end != '\0');
785 config_vf_floating_veb(struct rte_devargs *devargs,
786 uint16_t floating_veb,
787 bool *vf_floating_veb)
789 struct rte_kvargs *kvlist;
791 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
795 /* All the VFs attach to the floating VEB by default
796 * when the floating VEB is enabled.
798 for (i = 0; i < I40E_MAX_VF; i++)
799 vf_floating_veb[i] = true;
804 kvlist = rte_kvargs_parse(devargs->args, NULL);
808 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
809 rte_kvargs_free(kvlist);
812 /* When the floating_veb_list parameter exists, all the VFs
813 * will attach to the legacy VEB firstly, then configure VFs
814 * to the floating VEB according to the floating_veb_list.
816 if (rte_kvargs_process(kvlist, floating_veb_list,
817 floating_veb_list_handler,
818 vf_floating_veb) < 0) {
819 rte_kvargs_free(kvlist);
822 rte_kvargs_free(kvlist);
826 i40e_check_floating_handler(__rte_unused const char *key,
828 __rte_unused void *opaque)
830 if (strcmp(value, "1"))
837 is_floating_veb_supported(struct rte_devargs *devargs)
839 struct rte_kvargs *kvlist;
840 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
845 kvlist = rte_kvargs_parse(devargs->args, NULL);
849 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
850 rte_kvargs_free(kvlist);
853 /* Floating VEB is enabled when there's key-value:
854 * enable_floating_veb=1
856 if (rte_kvargs_process(kvlist, floating_veb_key,
857 i40e_check_floating_handler, NULL) < 0) {
858 rte_kvargs_free(kvlist);
861 rte_kvargs_free(kvlist);
867 config_floating_veb(struct rte_eth_dev *dev)
869 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
870 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
873 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
875 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
877 is_floating_veb_supported(pci_dev->device.devargs);
878 config_vf_floating_veb(pci_dev->device.devargs,
880 pf->floating_veb_list);
882 pf->floating_veb = false;
886 #define I40E_L2_TAGS_S_TAG_SHIFT 1
887 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
890 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
892 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
893 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
894 char ethertype_hash_name[RTE_HASH_NAMESIZE];
897 struct rte_hash_parameters ethertype_hash_params = {
898 .name = ethertype_hash_name,
899 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
900 .key_len = sizeof(struct i40e_ethertype_filter_input),
901 .hash_func = rte_hash_crc,
904 /* Initialize ethertype filter rule list and hash */
905 TAILQ_INIT(ðertype_rule->ethertype_list);
906 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
907 "ethertype_%s", dev->data->name);
908 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
909 if (!ethertype_rule->hash_table) {
910 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
913 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
914 sizeof(struct i40e_ethertype_filter *) *
915 I40E_MAX_ETHERTYPE_FILTER_NUM,
917 if (!ethertype_rule->hash_map) {
919 "Failed to allocate memory for ethertype hash map!");
921 goto err_ethertype_hash_map_alloc;
926 err_ethertype_hash_map_alloc:
927 rte_hash_free(ethertype_rule->hash_table);
933 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
935 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
936 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
937 char tunnel_hash_name[RTE_HASH_NAMESIZE];
940 struct rte_hash_parameters tunnel_hash_params = {
941 .name = tunnel_hash_name,
942 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
943 .key_len = sizeof(struct i40e_tunnel_filter_input),
944 .hash_func = rte_hash_crc,
947 /* Initialize tunnel filter rule list and hash */
948 TAILQ_INIT(&tunnel_rule->tunnel_list);
949 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
950 "tunnel_%s", dev->data->name);
951 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
952 if (!tunnel_rule->hash_table) {
953 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
956 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
957 sizeof(struct i40e_tunnel_filter *) *
958 I40E_MAX_TUNNEL_FILTER_NUM,
960 if (!tunnel_rule->hash_map) {
962 "Failed to allocate memory for tunnel hash map!");
964 goto err_tunnel_hash_map_alloc;
969 err_tunnel_hash_map_alloc:
970 rte_hash_free(tunnel_rule->hash_table);
976 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
978 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
979 struct i40e_fdir_info *fdir_info = &pf->fdir;
980 char fdir_hash_name[RTE_HASH_NAMESIZE];
983 struct rte_hash_parameters fdir_hash_params = {
984 .name = fdir_hash_name,
985 .entries = I40E_MAX_FDIR_FILTER_NUM,
986 .key_len = sizeof(struct rte_eth_fdir_input),
987 .hash_func = rte_hash_crc,
990 /* Initialize flow director filter rule list and hash */
991 TAILQ_INIT(&fdir_info->fdir_list);
992 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
993 "fdir_%s", dev->data->name);
994 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
995 if (!fdir_info->hash_table) {
996 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
999 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1000 sizeof(struct i40e_fdir_filter *) *
1001 I40E_MAX_FDIR_FILTER_NUM,
1003 if (!fdir_info->hash_map) {
1005 "Failed to allocate memory for fdir hash map!");
1007 goto err_fdir_hash_map_alloc;
1011 err_fdir_hash_map_alloc:
1012 rte_hash_free(fdir_info->hash_table);
1018 eth_i40e_dev_init(struct rte_eth_dev *dev)
1020 struct rte_pci_device *pci_dev;
1021 struct rte_intr_handle *intr_handle;
1022 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1023 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024 struct i40e_vsi *vsi;
1027 uint8_t aq_fail = 0;
1029 PMD_INIT_FUNC_TRACE();
1031 dev->dev_ops = &i40e_eth_dev_ops;
1032 dev->rx_pkt_burst = i40e_recv_pkts;
1033 dev->tx_pkt_burst = i40e_xmit_pkts;
1034 dev->tx_pkt_prepare = i40e_prep_pkts;
1036 /* for secondary processes, we don't initialise any further as primary
1037 * has already done this work. Only check we don't need a different
1039 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1040 i40e_set_rx_function(dev);
1041 i40e_set_tx_function(dev);
1044 pci_dev = I40E_DEV_TO_PCI(dev);
1045 intr_handle = &pci_dev->intr_handle;
1047 rte_eth_copy_pci_info(dev, pci_dev);
1048 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1050 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1051 pf->adapter->eth_dev = dev;
1052 pf->dev_data = dev->data;
1054 hw->back = I40E_PF_TO_ADAPTER(pf);
1055 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1058 "Hardware is not available, as address is NULL");
1062 hw->vendor_id = pci_dev->id.vendor_id;
1063 hw->device_id = pci_dev->id.device_id;
1064 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1065 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1066 hw->bus.device = pci_dev->addr.devid;
1067 hw->bus.func = pci_dev->addr.function;
1068 hw->adapter_stopped = 0;
1070 /* Make sure all is clean before doing PF reset */
1073 /* Initialize the hardware */
1076 /* Reset here to make sure all is clean for each PF */
1077 ret = i40e_pf_reset(hw);
1079 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1083 /* Initialize the shared code (base driver) */
1084 ret = i40e_init_shared_code(hw);
1086 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1091 * To work around the NVM issue, initialize registers
1092 * for flexible payload and packet type of QinQ by
1093 * software. It should be removed once issues are fixed
1096 i40e_GLQF_reg_init(hw);
1098 /* Initialize the input set for filters (hash and fd) to default value */
1099 i40e_filter_input_set_init(pf);
1101 /* Initialize the parameters for adminq */
1102 i40e_init_adminq_parameter(hw);
1103 ret = i40e_init_adminq(hw);
1104 if (ret != I40E_SUCCESS) {
1105 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1108 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1109 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1110 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1111 ((hw->nvm.version >> 12) & 0xf),
1112 ((hw->nvm.version >> 4) & 0xff),
1113 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1115 /* Need the special FW version to support floating VEB */
1116 config_floating_veb(dev);
1117 /* Clear PXE mode */
1118 i40e_clear_pxe_mode(hw);
1119 ret = i40e_dev_sync_phy_type(hw);
1121 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1122 goto err_sync_phy_type;
1125 * On X710, performance number is far from the expectation on recent
1126 * firmware versions. The fix for this issue may not be integrated in
1127 * the following firmware version. So the workaround in software driver
1128 * is needed. It needs to modify the initial values of 3 internal only
1129 * registers. Note that the workaround can be removed when it is fixed
1130 * in firmware in the future.
1132 i40e_configure_registers(hw);
1134 /* Get hw capabilities */
1135 ret = i40e_get_cap(hw);
1136 if (ret != I40E_SUCCESS) {
1137 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1138 goto err_get_capabilities;
1141 /* Initialize parameters for PF */
1142 ret = i40e_pf_parameter_init(dev);
1144 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1145 goto err_parameter_init;
1148 /* Initialize the queue management */
1149 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1151 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1152 goto err_qp_pool_init;
1154 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1155 hw->func_caps.num_msix_vectors - 1);
1157 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1158 goto err_msix_pool_init;
1161 /* Initialize lan hmc */
1162 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1163 hw->func_caps.num_rx_qp, 0, 0);
1164 if (ret != I40E_SUCCESS) {
1165 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1166 goto err_init_lan_hmc;
1169 /* Configure lan hmc */
1170 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1171 if (ret != I40E_SUCCESS) {
1172 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1173 goto err_configure_lan_hmc;
1176 /* Get and check the mac address */
1177 i40e_get_mac_addr(hw, hw->mac.addr);
1178 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1179 PMD_INIT_LOG(ERR, "mac address is not valid");
1181 goto err_get_mac_addr;
1183 /* Copy the permanent MAC address */
1184 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1185 (struct ether_addr *) hw->mac.perm_addr);
1187 /* Disable flow control */
1188 hw->fc.requested_mode = I40E_FC_NONE;
1189 i40e_set_fc(hw, &aq_fail, TRUE);
1191 /* Set the global registers with default ether type value */
1192 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1193 if (ret != I40E_SUCCESS) {
1195 "Failed to set the default outer VLAN ether type");
1196 goto err_setup_pf_switch;
1199 /* PF setup, which includes VSI setup */
1200 ret = i40e_pf_setup(pf);
1202 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1203 goto err_setup_pf_switch;
1206 /* reset all stats of the device, including pf and main vsi */
1207 i40e_dev_stats_reset(dev);
1211 /* Disable double vlan by default */
1212 i40e_vsi_config_double_vlan(vsi, FALSE);
1214 /* Disable S-TAG identification when floating_veb is disabled */
1215 if (!pf->floating_veb) {
1216 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1217 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1218 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1219 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1223 if (!vsi->max_macaddrs)
1224 len = ETHER_ADDR_LEN;
1226 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1228 /* Should be after VSI initialized */
1229 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1230 if (!dev->data->mac_addrs) {
1232 "Failed to allocated memory for storing mac address");
1235 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1236 &dev->data->mac_addrs[0]);
1238 /* initialize pf host driver to setup SRIOV resource if applicable */
1239 i40e_pf_host_init(dev);
1241 /* register callback func to eal lib */
1242 rte_intr_callback_register(intr_handle,
1243 i40e_dev_interrupt_handler, dev);
1245 /* configure and enable device interrupt */
1246 i40e_pf_config_irq0(hw, TRUE);
1247 i40e_pf_enable_irq0(hw);
1249 /* enable uio intr after callback register */
1250 rte_intr_enable(intr_handle);
1252 * Add an ethertype filter to drop all flow control frames transmitted
1253 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1256 i40e_add_tx_flow_control_drop_filter(pf);
1258 /* Set the max frame size to 0x2600 by default,
1259 * in case other drivers changed the default value.
1261 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1263 /* initialize mirror rule list */
1264 TAILQ_INIT(&pf->mirror_list);
1266 /* Init dcb to sw mode by default */
1267 ret = i40e_dcb_init_configure(dev, TRUE);
1268 if (ret != I40E_SUCCESS) {
1269 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1270 pf->flags &= ~I40E_FLAG_DCB;
1273 ret = i40e_init_ethtype_filter_list(dev);
1275 goto err_init_ethtype_filter_list;
1276 ret = i40e_init_tunnel_filter_list(dev);
1278 goto err_init_tunnel_filter_list;
1279 ret = i40e_init_fdir_filter_list(dev);
1281 goto err_init_fdir_filter_list;
1285 err_init_fdir_filter_list:
1286 rte_free(pf->tunnel.hash_table);
1287 rte_free(pf->tunnel.hash_map);
1288 err_init_tunnel_filter_list:
1289 rte_free(pf->ethertype.hash_table);
1290 rte_free(pf->ethertype.hash_map);
1291 err_init_ethtype_filter_list:
1292 rte_free(dev->data->mac_addrs);
1294 i40e_vsi_release(pf->main_vsi);
1295 err_setup_pf_switch:
1297 err_configure_lan_hmc:
1298 (void)i40e_shutdown_lan_hmc(hw);
1300 i40e_res_pool_destroy(&pf->msix_pool);
1302 i40e_res_pool_destroy(&pf->qp_pool);
1305 err_get_capabilities:
1307 (void)i40e_shutdown_adminq(hw);
1313 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1315 struct i40e_ethertype_filter *p_ethertype;
1316 struct i40e_ethertype_rule *ethertype_rule;
1318 ethertype_rule = &pf->ethertype;
1319 /* Remove all ethertype filter rules and hash */
1320 if (ethertype_rule->hash_map)
1321 rte_free(ethertype_rule->hash_map);
1322 if (ethertype_rule->hash_table)
1323 rte_hash_free(ethertype_rule->hash_table);
1325 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1326 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1327 p_ethertype, rules);
1328 rte_free(p_ethertype);
1333 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1335 struct i40e_tunnel_filter *p_tunnel;
1336 struct i40e_tunnel_rule *tunnel_rule;
1338 tunnel_rule = &pf->tunnel;
1339 /* Remove all tunnel director rules and hash */
1340 if (tunnel_rule->hash_map)
1341 rte_free(tunnel_rule->hash_map);
1342 if (tunnel_rule->hash_table)
1343 rte_hash_free(tunnel_rule->hash_table);
1345 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1346 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1352 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1354 struct i40e_fdir_filter *p_fdir;
1355 struct i40e_fdir_info *fdir_info;
1357 fdir_info = &pf->fdir;
1358 /* Remove all flow director rules and hash */
1359 if (fdir_info->hash_map)
1360 rte_free(fdir_info->hash_map);
1361 if (fdir_info->hash_table)
1362 rte_hash_free(fdir_info->hash_table);
1364 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1365 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1371 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1374 struct rte_pci_device *pci_dev;
1375 struct rte_intr_handle *intr_handle;
1377 struct i40e_filter_control_settings settings;
1378 struct rte_flow *p_flow;
1380 uint8_t aq_fail = 0;
1382 PMD_INIT_FUNC_TRACE();
1384 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1387 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1388 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1389 pci_dev = I40E_DEV_TO_PCI(dev);
1390 intr_handle = &pci_dev->intr_handle;
1392 if (hw->adapter_stopped == 0)
1393 i40e_dev_close(dev);
1395 dev->dev_ops = NULL;
1396 dev->rx_pkt_burst = NULL;
1397 dev->tx_pkt_burst = NULL;
1399 /* Clear PXE mode */
1400 i40e_clear_pxe_mode(hw);
1402 /* Unconfigure filter control */
1403 memset(&settings, 0, sizeof(settings));
1404 ret = i40e_set_filter_control(hw, &settings);
1406 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1409 /* Disable flow control */
1410 hw->fc.requested_mode = I40E_FC_NONE;
1411 i40e_set_fc(hw, &aq_fail, TRUE);
1413 /* uninitialize pf host driver */
1414 i40e_pf_host_uninit(dev);
1416 rte_free(dev->data->mac_addrs);
1417 dev->data->mac_addrs = NULL;
1419 /* disable uio intr before callback unregister */
1420 rte_intr_disable(intr_handle);
1422 /* register callback func to eal lib */
1423 rte_intr_callback_unregister(intr_handle,
1424 i40e_dev_interrupt_handler, dev);
1426 i40e_rm_ethtype_filter_list(pf);
1427 i40e_rm_tunnel_filter_list(pf);
1428 i40e_rm_fdir_filter_list(pf);
1430 /* Remove all flows */
1431 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1432 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1440 i40e_dev_configure(struct rte_eth_dev *dev)
1442 struct i40e_adapter *ad =
1443 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1444 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1445 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1448 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1449 * bulk allocation or vector Rx preconditions we will reset it.
1451 ad->rx_bulk_alloc_allowed = true;
1452 ad->rx_vec_allowed = true;
1453 ad->tx_simple_allowed = true;
1454 ad->tx_vec_allowed = true;
1456 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1457 ret = i40e_fdir_setup(pf);
1458 if (ret != I40E_SUCCESS) {
1459 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1462 ret = i40e_fdir_configure(dev);
1464 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1468 i40e_fdir_teardown(pf);
1470 ret = i40e_dev_init_vlan(dev);
1475 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1476 * RSS setting have different requirements.
1477 * General PMD driver call sequence are NIC init, configure,
1478 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1479 * will try to lookup the VSI that specific queue belongs to if VMDQ
1480 * applicable. So, VMDQ setting has to be done before
1481 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1482 * For RSS setting, it will try to calculate actual configured RX queue
1483 * number, which will be available after rx_queue_setup(). dev_start()
1484 * function is good to place RSS setup.
1486 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1487 ret = i40e_vmdq_setup(dev);
1492 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1493 ret = i40e_dcb_setup(dev);
1495 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1500 TAILQ_INIT(&pf->flow_list);
1505 /* need to release vmdq resource if exists */
1506 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1507 i40e_vsi_release(pf->vmdq[i].vsi);
1508 pf->vmdq[i].vsi = NULL;
1513 /* need to release fdir resource if exists */
1514 i40e_fdir_teardown(pf);
1519 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1521 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1522 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1523 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1524 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1525 uint16_t msix_vect = vsi->msix_intr;
1528 for (i = 0; i < vsi->nb_qps; i++) {
1529 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1530 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1534 if (vsi->type != I40E_VSI_SRIOV) {
1535 if (!rte_intr_allow_others(intr_handle)) {
1536 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1537 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1539 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1542 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1543 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1545 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1550 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1551 vsi->user_param + (msix_vect - 1);
1553 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1554 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1556 I40E_WRITE_FLUSH(hw);
1560 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1561 int base_queue, int nb_queue)
1565 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1567 /* Bind all RX queues to allocated MSIX interrupt */
1568 for (i = 0; i < nb_queue; i++) {
1569 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1570 I40E_QINT_RQCTL_ITR_INDX_MASK |
1571 ((base_queue + i + 1) <<
1572 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1573 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1574 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1576 if (i == nb_queue - 1)
1577 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1578 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1581 /* Write first RX queue to Link list register as the head element */
1582 if (vsi->type != I40E_VSI_SRIOV) {
1584 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1586 if (msix_vect == I40E_MISC_VEC_ID) {
1587 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1589 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1591 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1593 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1596 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1598 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1600 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1602 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1609 if (msix_vect == I40E_MISC_VEC_ID) {
1611 I40E_VPINT_LNKLST0(vsi->user_param),
1613 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1615 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1617 /* num_msix_vectors_vf needs to minus irq0 */
1618 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1619 vsi->user_param + (msix_vect - 1);
1621 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1623 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1625 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1629 I40E_WRITE_FLUSH(hw);
1633 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1635 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1636 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1637 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1638 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1639 uint16_t msix_vect = vsi->msix_intr;
1640 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1641 uint16_t queue_idx = 0;
1646 for (i = 0; i < vsi->nb_qps; i++) {
1647 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1648 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1651 /* INTENA flag is not auto-cleared for interrupt */
1652 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1653 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1654 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1655 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1656 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1658 /* VF bind interrupt */
1659 if (vsi->type == I40E_VSI_SRIOV) {
1660 __vsi_queues_bind_intr(vsi, msix_vect,
1661 vsi->base_queue, vsi->nb_qps);
1665 /* PF & VMDq bind interrupt */
1666 if (rte_intr_dp_is_en(intr_handle)) {
1667 if (vsi->type == I40E_VSI_MAIN) {
1670 } else if (vsi->type == I40E_VSI_VMDQ2) {
1671 struct i40e_vsi *main_vsi =
1672 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1673 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1678 for (i = 0; i < vsi->nb_used_qps; i++) {
1680 if (!rte_intr_allow_others(intr_handle))
1681 /* allow to share MISC_VEC_ID */
1682 msix_vect = I40E_MISC_VEC_ID;
1684 /* no enough msix_vect, map all to one */
1685 __vsi_queues_bind_intr(vsi, msix_vect,
1686 vsi->base_queue + i,
1687 vsi->nb_used_qps - i);
1688 for (; !!record && i < vsi->nb_used_qps; i++)
1689 intr_handle->intr_vec[queue_idx + i] =
1693 /* 1:1 queue/msix_vect mapping */
1694 __vsi_queues_bind_intr(vsi, msix_vect,
1695 vsi->base_queue + i, 1);
1697 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1705 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1707 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1708 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1709 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1710 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1711 uint16_t interval = i40e_calc_itr_interval(\
1712 RTE_LIBRTE_I40E_ITR_INTERVAL);
1713 uint16_t msix_intr, i;
1715 if (rte_intr_allow_others(intr_handle))
1716 for (i = 0; i < vsi->nb_msix; i++) {
1717 msix_intr = vsi->msix_intr + i;
1718 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1719 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1720 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1721 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1723 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1726 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1727 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1728 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1729 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1731 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1733 I40E_WRITE_FLUSH(hw);
1737 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1739 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1740 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1741 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1742 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1743 uint16_t msix_intr, i;
1745 if (rte_intr_allow_others(intr_handle))
1746 for (i = 0; i < vsi->nb_msix; i++) {
1747 msix_intr = vsi->msix_intr + i;
1748 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1752 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1754 I40E_WRITE_FLUSH(hw);
1757 static inline uint8_t
1758 i40e_parse_link_speeds(uint16_t link_speeds)
1760 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1762 if (link_speeds & ETH_LINK_SPEED_40G)
1763 link_speed |= I40E_LINK_SPEED_40GB;
1764 if (link_speeds & ETH_LINK_SPEED_25G)
1765 link_speed |= I40E_LINK_SPEED_25GB;
1766 if (link_speeds & ETH_LINK_SPEED_20G)
1767 link_speed |= I40E_LINK_SPEED_20GB;
1768 if (link_speeds & ETH_LINK_SPEED_10G)
1769 link_speed |= I40E_LINK_SPEED_10GB;
1770 if (link_speeds & ETH_LINK_SPEED_1G)
1771 link_speed |= I40E_LINK_SPEED_1GB;
1772 if (link_speeds & ETH_LINK_SPEED_100M)
1773 link_speed |= I40E_LINK_SPEED_100MB;
1779 i40e_phy_conf_link(struct i40e_hw *hw,
1781 uint8_t force_speed)
1783 enum i40e_status_code status;
1784 struct i40e_aq_get_phy_abilities_resp phy_ab;
1785 struct i40e_aq_set_phy_config phy_conf;
1786 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1787 I40E_AQ_PHY_FLAG_PAUSE_RX |
1788 I40E_AQ_PHY_FLAG_PAUSE_RX |
1789 I40E_AQ_PHY_FLAG_LOW_POWER;
1790 const uint8_t advt = I40E_LINK_SPEED_40GB |
1791 I40E_LINK_SPEED_25GB |
1792 I40E_LINK_SPEED_10GB |
1793 I40E_LINK_SPEED_1GB |
1794 I40E_LINK_SPEED_100MB;
1798 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1803 memset(&phy_conf, 0, sizeof(phy_conf));
1805 /* bits 0-2 use the values from get_phy_abilities_resp */
1807 abilities |= phy_ab.abilities & mask;
1809 /* update ablities and speed */
1810 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1811 phy_conf.link_speed = advt;
1813 phy_conf.link_speed = force_speed;
1815 phy_conf.abilities = abilities;
1817 /* use get_phy_abilities_resp value for the rest */
1818 phy_conf.phy_type = phy_ab.phy_type;
1819 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1820 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1821 phy_conf.eee_capability = phy_ab.eee_capability;
1822 phy_conf.eeer = phy_ab.eeer_val;
1823 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1825 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1826 phy_ab.abilities, phy_ab.link_speed);
1827 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1828 phy_conf.abilities, phy_conf.link_speed);
1830 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1834 return I40E_SUCCESS;
1838 i40e_apply_link_speed(struct rte_eth_dev *dev)
1841 uint8_t abilities = 0;
1842 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843 struct rte_eth_conf *conf = &dev->data->dev_conf;
1845 speed = i40e_parse_link_speeds(conf->link_speeds);
1846 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1847 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1848 abilities |= I40E_AQ_PHY_AN_ENABLED;
1849 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1851 /* Skip changing speed on 40G interfaces, FW does not support */
1852 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1853 speed = I40E_LINK_SPEED_UNKNOWN;
1854 abilities |= I40E_AQ_PHY_AN_ENABLED;
1857 return i40e_phy_conf_link(hw, abilities, speed);
1861 i40e_dev_start(struct rte_eth_dev *dev)
1863 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1864 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1865 struct i40e_vsi *main_vsi = pf->main_vsi;
1867 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1868 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1869 uint32_t intr_vector = 0;
1871 hw->adapter_stopped = 0;
1873 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1874 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1875 dev->data->port_id);
1879 rte_intr_disable(intr_handle);
1881 if ((rte_intr_cap_multiple(intr_handle) ||
1882 !RTE_ETH_DEV_SRIOV(dev).active) &&
1883 dev->data->dev_conf.intr_conf.rxq != 0) {
1884 intr_vector = dev->data->nb_rx_queues;
1885 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1890 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1891 intr_handle->intr_vec =
1892 rte_zmalloc("intr_vec",
1893 dev->data->nb_rx_queues * sizeof(int),
1895 if (!intr_handle->intr_vec) {
1897 "Failed to allocate %d rx_queues intr_vec",
1898 dev->data->nb_rx_queues);
1903 /* Initialize VSI */
1904 ret = i40e_dev_rxtx_init(pf);
1905 if (ret != I40E_SUCCESS) {
1906 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1910 /* Map queues with MSIX interrupt */
1911 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1912 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1913 i40e_vsi_queues_bind_intr(main_vsi);
1914 i40e_vsi_enable_queues_intr(main_vsi);
1916 /* Map VMDQ VSI queues with MSIX interrupt */
1917 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1918 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1919 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1920 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1923 /* enable FDIR MSIX interrupt */
1924 if (pf->fdir.fdir_vsi) {
1925 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1926 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1929 /* Enable all queues which have been configured */
1930 ret = i40e_dev_switch_queues(pf, TRUE);
1931 if (ret != I40E_SUCCESS) {
1932 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1936 /* Enable receiving broadcast packets */
1937 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1938 if (ret != I40E_SUCCESS)
1939 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1941 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1942 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1944 if (ret != I40E_SUCCESS)
1945 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1948 /* Apply link configure */
1949 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1950 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1951 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1952 ETH_LINK_SPEED_40G)) {
1953 PMD_DRV_LOG(ERR, "Invalid link setting");
1956 ret = i40e_apply_link_speed(dev);
1957 if (I40E_SUCCESS != ret) {
1958 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1962 if (!rte_intr_allow_others(intr_handle)) {
1963 rte_intr_callback_unregister(intr_handle,
1964 i40e_dev_interrupt_handler,
1966 /* configure and enable device interrupt */
1967 i40e_pf_config_irq0(hw, FALSE);
1968 i40e_pf_enable_irq0(hw);
1970 if (dev->data->dev_conf.intr_conf.lsc != 0)
1972 "lsc won't enable because of no intr multiplex");
1973 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1974 ret = i40e_aq_set_phy_int_mask(hw,
1975 ~(I40E_AQ_EVENT_LINK_UPDOWN |
1976 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1977 I40E_AQ_EVENT_MEDIA_NA), NULL);
1978 if (ret != I40E_SUCCESS)
1979 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1981 /* Call get_link_info aq commond to enable LSE */
1982 i40e_dev_link_update(dev, 0);
1985 /* enable uio intr after callback register */
1986 rte_intr_enable(intr_handle);
1988 i40e_filter_restore(pf);
1990 return I40E_SUCCESS;
1993 i40e_dev_switch_queues(pf, FALSE);
1994 i40e_dev_clear_queues(dev);
2000 i40e_dev_stop(struct rte_eth_dev *dev)
2002 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2003 struct i40e_vsi *main_vsi = pf->main_vsi;
2004 struct i40e_mirror_rule *p_mirror;
2005 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2006 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2009 /* Disable all queues */
2010 i40e_dev_switch_queues(pf, FALSE);
2012 /* un-map queues with interrupt registers */
2013 i40e_vsi_disable_queues_intr(main_vsi);
2014 i40e_vsi_queues_unbind_intr(main_vsi);
2016 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2017 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2018 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2021 if (pf->fdir.fdir_vsi) {
2022 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2023 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2025 /* Clear all queues and release memory */
2026 i40e_dev_clear_queues(dev);
2029 i40e_dev_set_link_down(dev);
2031 /* Remove all mirror rules */
2032 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2033 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2036 pf->nb_mirror_rule = 0;
2038 if (!rte_intr_allow_others(intr_handle))
2039 /* resume to the default handler */
2040 rte_intr_callback_register(intr_handle,
2041 i40e_dev_interrupt_handler,
2044 /* Clean datapath event and queue/vec mapping */
2045 rte_intr_efd_disable(intr_handle);
2046 if (intr_handle->intr_vec) {
2047 rte_free(intr_handle->intr_vec);
2048 intr_handle->intr_vec = NULL;
2053 i40e_dev_close(struct rte_eth_dev *dev)
2055 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2056 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2058 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2062 PMD_INIT_FUNC_TRACE();
2065 hw->adapter_stopped = 1;
2066 i40e_dev_free_queues(dev);
2068 /* Disable interrupt */
2069 i40e_pf_disable_irq0(hw);
2070 rte_intr_disable(intr_handle);
2072 /* shutdown and destroy the HMC */
2073 i40e_shutdown_lan_hmc(hw);
2075 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2076 i40e_vsi_release(pf->vmdq[i].vsi);
2077 pf->vmdq[i].vsi = NULL;
2082 /* release all the existing VSIs and VEBs */
2083 i40e_fdir_teardown(pf);
2084 i40e_vsi_release(pf->main_vsi);
2086 /* shutdown the adminq */
2087 i40e_aq_queue_shutdown(hw, true);
2088 i40e_shutdown_adminq(hw);
2090 i40e_res_pool_destroy(&pf->qp_pool);
2091 i40e_res_pool_destroy(&pf->msix_pool);
2093 /* force a PF reset to clean anything leftover */
2094 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2095 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2096 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2097 I40E_WRITE_FLUSH(hw);
2101 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2103 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2104 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105 struct i40e_vsi *vsi = pf->main_vsi;
2108 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2110 if (status != I40E_SUCCESS)
2111 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2113 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2115 if (status != I40E_SUCCESS)
2116 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2121 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2123 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2124 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125 struct i40e_vsi *vsi = pf->main_vsi;
2128 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2130 if (status != I40E_SUCCESS)
2131 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2133 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2135 if (status != I40E_SUCCESS)
2136 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2140 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2142 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2143 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144 struct i40e_vsi *vsi = pf->main_vsi;
2147 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2148 if (ret != I40E_SUCCESS)
2149 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2153 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2155 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2156 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2157 struct i40e_vsi *vsi = pf->main_vsi;
2160 if (dev->data->promiscuous == 1)
2161 return; /* must remain in all_multicast mode */
2163 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2164 vsi->seid, FALSE, NULL);
2165 if (ret != I40E_SUCCESS)
2166 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2170 * Set device link up.
2173 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2175 /* re-apply link speed setting */
2176 return i40e_apply_link_speed(dev);
2180 * Set device link down.
2183 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2185 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2186 uint8_t abilities = 0;
2187 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2190 return i40e_phy_conf_link(hw, abilities, speed);
2194 i40e_dev_link_update(struct rte_eth_dev *dev,
2195 int wait_to_complete)
2197 #define CHECK_INTERVAL 100 /* 100ms */
2198 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2199 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200 struct i40e_link_status link_status;
2201 struct rte_eth_link link, old;
2203 unsigned rep_cnt = MAX_REPEAT_TIME;
2204 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2206 memset(&link, 0, sizeof(link));
2207 memset(&old, 0, sizeof(old));
2208 memset(&link_status, 0, sizeof(link_status));
2209 rte_i40e_dev_atomic_read_link_status(dev, &old);
2212 /* Get link status information from hardware */
2213 status = i40e_aq_get_link_info(hw, enable_lse,
2214 &link_status, NULL);
2215 if (status != I40E_SUCCESS) {
2216 link.link_speed = ETH_SPEED_NUM_100M;
2217 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2218 PMD_DRV_LOG(ERR, "Failed to get link info");
2222 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2223 if (!wait_to_complete)
2226 rte_delay_ms(CHECK_INTERVAL);
2227 } while (!link.link_status && rep_cnt--);
2229 if (!link.link_status)
2232 /* i40e uses full duplex only */
2233 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2235 /* Parse the link status */
2236 switch (link_status.link_speed) {
2237 case I40E_LINK_SPEED_100MB:
2238 link.link_speed = ETH_SPEED_NUM_100M;
2240 case I40E_LINK_SPEED_1GB:
2241 link.link_speed = ETH_SPEED_NUM_1G;
2243 case I40E_LINK_SPEED_10GB:
2244 link.link_speed = ETH_SPEED_NUM_10G;
2246 case I40E_LINK_SPEED_20GB:
2247 link.link_speed = ETH_SPEED_NUM_20G;
2249 case I40E_LINK_SPEED_25GB:
2250 link.link_speed = ETH_SPEED_NUM_25G;
2252 case I40E_LINK_SPEED_40GB:
2253 link.link_speed = ETH_SPEED_NUM_40G;
2256 link.link_speed = ETH_SPEED_NUM_100M;
2260 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2261 ETH_LINK_SPEED_FIXED);
2264 rte_i40e_dev_atomic_write_link_status(dev, &link);
2265 if (link.link_status == old.link_status)
2271 /* Get all the statistics of a VSI */
2273 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2275 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2276 struct i40e_eth_stats *nes = &vsi->eth_stats;
2277 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2278 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2280 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2281 vsi->offset_loaded, &oes->rx_bytes,
2283 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2284 vsi->offset_loaded, &oes->rx_unicast,
2286 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2287 vsi->offset_loaded, &oes->rx_multicast,
2288 &nes->rx_multicast);
2289 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2290 vsi->offset_loaded, &oes->rx_broadcast,
2291 &nes->rx_broadcast);
2292 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2293 &oes->rx_discards, &nes->rx_discards);
2294 /* GLV_REPC not supported */
2295 /* GLV_RMPC not supported */
2296 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2297 &oes->rx_unknown_protocol,
2298 &nes->rx_unknown_protocol);
2299 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2300 vsi->offset_loaded, &oes->tx_bytes,
2302 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2303 vsi->offset_loaded, &oes->tx_unicast,
2305 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2306 vsi->offset_loaded, &oes->tx_multicast,
2307 &nes->tx_multicast);
2308 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2309 vsi->offset_loaded, &oes->tx_broadcast,
2310 &nes->tx_broadcast);
2311 /* GLV_TDPC not supported */
2312 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2313 &oes->tx_errors, &nes->tx_errors);
2314 vsi->offset_loaded = true;
2316 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2318 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2319 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2320 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2321 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2322 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2323 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2324 nes->rx_unknown_protocol);
2325 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2326 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2327 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2328 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2329 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2330 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2331 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2336 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2339 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2340 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2342 /* Get statistics of struct i40e_eth_stats */
2343 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2344 I40E_GLPRT_GORCL(hw->port),
2345 pf->offset_loaded, &os->eth.rx_bytes,
2347 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2348 I40E_GLPRT_UPRCL(hw->port),
2349 pf->offset_loaded, &os->eth.rx_unicast,
2350 &ns->eth.rx_unicast);
2351 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2352 I40E_GLPRT_MPRCL(hw->port),
2353 pf->offset_loaded, &os->eth.rx_multicast,
2354 &ns->eth.rx_multicast);
2355 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2356 I40E_GLPRT_BPRCL(hw->port),
2357 pf->offset_loaded, &os->eth.rx_broadcast,
2358 &ns->eth.rx_broadcast);
2359 /* Workaround: CRC size should not be included in byte statistics,
2360 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2362 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2363 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2365 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2366 pf->offset_loaded, &os->eth.rx_discards,
2367 &ns->eth.rx_discards);
2368 /* GLPRT_REPC not supported */
2369 /* GLPRT_RMPC not supported */
2370 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2372 &os->eth.rx_unknown_protocol,
2373 &ns->eth.rx_unknown_protocol);
2374 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2375 I40E_GLPRT_GOTCL(hw->port),
2376 pf->offset_loaded, &os->eth.tx_bytes,
2378 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2379 I40E_GLPRT_UPTCL(hw->port),
2380 pf->offset_loaded, &os->eth.tx_unicast,
2381 &ns->eth.tx_unicast);
2382 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2383 I40E_GLPRT_MPTCL(hw->port),
2384 pf->offset_loaded, &os->eth.tx_multicast,
2385 &ns->eth.tx_multicast);
2386 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2387 I40E_GLPRT_BPTCL(hw->port),
2388 pf->offset_loaded, &os->eth.tx_broadcast,
2389 &ns->eth.tx_broadcast);
2390 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2391 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2392 /* GLPRT_TEPC not supported */
2394 /* additional port specific stats */
2395 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2396 pf->offset_loaded, &os->tx_dropped_link_down,
2397 &ns->tx_dropped_link_down);
2398 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2399 pf->offset_loaded, &os->crc_errors,
2401 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2402 pf->offset_loaded, &os->illegal_bytes,
2403 &ns->illegal_bytes);
2404 /* GLPRT_ERRBC not supported */
2405 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2406 pf->offset_loaded, &os->mac_local_faults,
2407 &ns->mac_local_faults);
2408 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2409 pf->offset_loaded, &os->mac_remote_faults,
2410 &ns->mac_remote_faults);
2411 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2412 pf->offset_loaded, &os->rx_length_errors,
2413 &ns->rx_length_errors);
2414 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2415 pf->offset_loaded, &os->link_xon_rx,
2417 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2418 pf->offset_loaded, &os->link_xoff_rx,
2420 for (i = 0; i < 8; i++) {
2421 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2423 &os->priority_xon_rx[i],
2424 &ns->priority_xon_rx[i]);
2425 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2427 &os->priority_xoff_rx[i],
2428 &ns->priority_xoff_rx[i]);
2430 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2431 pf->offset_loaded, &os->link_xon_tx,
2433 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2434 pf->offset_loaded, &os->link_xoff_tx,
2436 for (i = 0; i < 8; i++) {
2437 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2439 &os->priority_xon_tx[i],
2440 &ns->priority_xon_tx[i]);
2441 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2443 &os->priority_xoff_tx[i],
2444 &ns->priority_xoff_tx[i]);
2445 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2447 &os->priority_xon_2_xoff[i],
2448 &ns->priority_xon_2_xoff[i]);
2450 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2451 I40E_GLPRT_PRC64L(hw->port),
2452 pf->offset_loaded, &os->rx_size_64,
2454 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2455 I40E_GLPRT_PRC127L(hw->port),
2456 pf->offset_loaded, &os->rx_size_127,
2458 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2459 I40E_GLPRT_PRC255L(hw->port),
2460 pf->offset_loaded, &os->rx_size_255,
2462 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2463 I40E_GLPRT_PRC511L(hw->port),
2464 pf->offset_loaded, &os->rx_size_511,
2466 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2467 I40E_GLPRT_PRC1023L(hw->port),
2468 pf->offset_loaded, &os->rx_size_1023,
2470 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2471 I40E_GLPRT_PRC1522L(hw->port),
2472 pf->offset_loaded, &os->rx_size_1522,
2474 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2475 I40E_GLPRT_PRC9522L(hw->port),
2476 pf->offset_loaded, &os->rx_size_big,
2478 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2479 pf->offset_loaded, &os->rx_undersize,
2481 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2482 pf->offset_loaded, &os->rx_fragments,
2484 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2485 pf->offset_loaded, &os->rx_oversize,
2487 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2488 pf->offset_loaded, &os->rx_jabber,
2490 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2491 I40E_GLPRT_PTC64L(hw->port),
2492 pf->offset_loaded, &os->tx_size_64,
2494 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2495 I40E_GLPRT_PTC127L(hw->port),
2496 pf->offset_loaded, &os->tx_size_127,
2498 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2499 I40E_GLPRT_PTC255L(hw->port),
2500 pf->offset_loaded, &os->tx_size_255,
2502 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2503 I40E_GLPRT_PTC511L(hw->port),
2504 pf->offset_loaded, &os->tx_size_511,
2506 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2507 I40E_GLPRT_PTC1023L(hw->port),
2508 pf->offset_loaded, &os->tx_size_1023,
2510 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2511 I40E_GLPRT_PTC1522L(hw->port),
2512 pf->offset_loaded, &os->tx_size_1522,
2514 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2515 I40E_GLPRT_PTC9522L(hw->port),
2516 pf->offset_loaded, &os->tx_size_big,
2518 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2520 &os->fd_sb_match, &ns->fd_sb_match);
2521 /* GLPRT_MSPDC not supported */
2522 /* GLPRT_XEC not supported */
2524 pf->offset_loaded = true;
2527 i40e_update_vsi_stats(pf->main_vsi);
2530 /* Get all statistics of a port */
2532 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2534 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2535 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2539 /* call read registers - updates values, now write them to struct */
2540 i40e_read_stats_registers(pf, hw);
2542 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2543 pf->main_vsi->eth_stats.rx_multicast +
2544 pf->main_vsi->eth_stats.rx_broadcast -
2545 pf->main_vsi->eth_stats.rx_discards;
2546 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2547 pf->main_vsi->eth_stats.tx_multicast +
2548 pf->main_vsi->eth_stats.tx_broadcast;
2549 stats->ibytes = ns->eth.rx_bytes;
2550 stats->obytes = ns->eth.tx_bytes;
2551 stats->oerrors = ns->eth.tx_errors +
2552 pf->main_vsi->eth_stats.tx_errors;
2555 stats->imissed = ns->eth.rx_discards +
2556 pf->main_vsi->eth_stats.rx_discards;
2557 stats->ierrors = ns->crc_errors +
2558 ns->rx_length_errors + ns->rx_undersize +
2559 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2561 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2562 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2563 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2564 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2565 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2566 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2567 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2568 ns->eth.rx_unknown_protocol);
2569 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2570 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2571 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2572 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2573 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2574 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2576 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2577 ns->tx_dropped_link_down);
2578 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2579 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2581 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2582 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2583 ns->mac_local_faults);
2584 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2585 ns->mac_remote_faults);
2586 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2587 ns->rx_length_errors);
2588 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2589 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2590 for (i = 0; i < 8; i++) {
2591 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2592 i, ns->priority_xon_rx[i]);
2593 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2594 i, ns->priority_xoff_rx[i]);
2596 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2597 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2598 for (i = 0; i < 8; i++) {
2599 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2600 i, ns->priority_xon_tx[i]);
2601 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2602 i, ns->priority_xoff_tx[i]);
2603 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2604 i, ns->priority_xon_2_xoff[i]);
2606 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2607 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2608 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2609 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2610 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2611 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2612 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2613 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2614 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2615 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2616 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2617 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2618 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2619 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2620 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2621 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2622 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2623 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2624 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2625 ns->mac_short_packet_dropped);
2626 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2627 ns->checksum_error);
2628 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2629 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2632 /* Reset the statistics */
2634 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2636 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2637 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2639 /* Mark PF and VSI stats to update the offset, aka "reset" */
2640 pf->offset_loaded = false;
2642 pf->main_vsi->offset_loaded = false;
2644 /* read the stats, reading current register values into offset */
2645 i40e_read_stats_registers(pf, hw);
2649 i40e_xstats_calc_num(void)
2651 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2652 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2653 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2656 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2657 struct rte_eth_xstat_name *xstats_names,
2658 __rte_unused unsigned limit)
2663 if (xstats_names == NULL)
2664 return i40e_xstats_calc_num();
2666 /* Note: limit checked in rte_eth_xstats_names() */
2668 /* Get stats from i40e_eth_stats struct */
2669 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2670 snprintf(xstats_names[count].name,
2671 sizeof(xstats_names[count].name),
2672 "%s", rte_i40e_stats_strings[i].name);
2676 /* Get individiual stats from i40e_hw_port struct */
2677 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2678 snprintf(xstats_names[count].name,
2679 sizeof(xstats_names[count].name),
2680 "%s", rte_i40e_hw_port_strings[i].name);
2684 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2685 for (prio = 0; prio < 8; prio++) {
2686 snprintf(xstats_names[count].name,
2687 sizeof(xstats_names[count].name),
2688 "rx_priority%u_%s", prio,
2689 rte_i40e_rxq_prio_strings[i].name);
2694 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2695 for (prio = 0; prio < 8; prio++) {
2696 snprintf(xstats_names[count].name,
2697 sizeof(xstats_names[count].name),
2698 "tx_priority%u_%s", prio,
2699 rte_i40e_txq_prio_strings[i].name);
2707 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2710 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2711 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2712 unsigned i, count, prio;
2713 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2715 count = i40e_xstats_calc_num();
2719 i40e_read_stats_registers(pf, hw);
2726 /* Get stats from i40e_eth_stats struct */
2727 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2728 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2729 rte_i40e_stats_strings[i].offset);
2730 xstats[count].id = count;
2734 /* Get individiual stats from i40e_hw_port struct */
2735 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2736 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2737 rte_i40e_hw_port_strings[i].offset);
2738 xstats[count].id = count;
2742 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2743 for (prio = 0; prio < 8; prio++) {
2744 xstats[count].value =
2745 *(uint64_t *)(((char *)hw_stats) +
2746 rte_i40e_rxq_prio_strings[i].offset +
2747 (sizeof(uint64_t) * prio));
2748 xstats[count].id = count;
2753 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2754 for (prio = 0; prio < 8; prio++) {
2755 xstats[count].value =
2756 *(uint64_t *)(((char *)hw_stats) +
2757 rte_i40e_txq_prio_strings[i].offset +
2758 (sizeof(uint64_t) * prio));
2759 xstats[count].id = count;
2768 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2769 __rte_unused uint16_t queue_id,
2770 __rte_unused uint8_t stat_idx,
2771 __rte_unused uint8_t is_rx)
2773 PMD_INIT_FUNC_TRACE();
2779 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2787 full_ver = hw->nvm.oem_ver;
2788 ver = (u8)(full_ver >> 24);
2789 build = (u16)((full_ver >> 8) & 0xffff);
2790 patch = (u8)(full_ver & 0xff);
2792 ret = snprintf(fw_version, fw_size,
2793 "%d.%d%d 0x%08x %d.%d.%d",
2794 ((hw->nvm.version >> 12) & 0xf),
2795 ((hw->nvm.version >> 4) & 0xff),
2796 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2799 ret += 1; /* add the size of '\0' */
2800 if (fw_size < (u32)ret)
2807 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2809 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2810 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811 struct i40e_vsi *vsi = pf->main_vsi;
2812 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2814 dev_info->pci_dev = pci_dev;
2815 dev_info->max_rx_queues = vsi->nb_qps;
2816 dev_info->max_tx_queues = vsi->nb_qps;
2817 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2818 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2819 dev_info->max_mac_addrs = vsi->max_macaddrs;
2820 dev_info->max_vfs = pci_dev->max_vfs;
2821 dev_info->rx_offload_capa =
2822 DEV_RX_OFFLOAD_VLAN_STRIP |
2823 DEV_RX_OFFLOAD_QINQ_STRIP |
2824 DEV_RX_OFFLOAD_IPV4_CKSUM |
2825 DEV_RX_OFFLOAD_UDP_CKSUM |
2826 DEV_RX_OFFLOAD_TCP_CKSUM;
2827 dev_info->tx_offload_capa =
2828 DEV_TX_OFFLOAD_VLAN_INSERT |
2829 DEV_TX_OFFLOAD_QINQ_INSERT |
2830 DEV_TX_OFFLOAD_IPV4_CKSUM |
2831 DEV_TX_OFFLOAD_UDP_CKSUM |
2832 DEV_TX_OFFLOAD_TCP_CKSUM |
2833 DEV_TX_OFFLOAD_SCTP_CKSUM |
2834 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2835 DEV_TX_OFFLOAD_TCP_TSO |
2836 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2837 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2838 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2839 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2840 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2842 dev_info->reta_size = pf->hash_lut_size;
2843 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2845 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2847 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2848 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2849 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2851 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2855 dev_info->default_txconf = (struct rte_eth_txconf) {
2857 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2858 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2859 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2861 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2862 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2863 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2864 ETH_TXQ_FLAGS_NOOFFLOADS,
2867 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2868 .nb_max = I40E_MAX_RING_DESC,
2869 .nb_min = I40E_MIN_RING_DESC,
2870 .nb_align = I40E_ALIGN_RING_DESC,
2873 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2874 .nb_max = I40E_MAX_RING_DESC,
2875 .nb_min = I40E_MIN_RING_DESC,
2876 .nb_align = I40E_ALIGN_RING_DESC,
2877 .nb_seg_max = I40E_TX_MAX_SEG,
2878 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2881 if (pf->flags & I40E_FLAG_VMDQ) {
2882 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2883 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2884 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2885 pf->max_nb_vmdq_vsi;
2886 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2887 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2888 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2891 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2893 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2894 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2896 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2899 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2903 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2905 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2906 struct i40e_vsi *vsi = pf->main_vsi;
2907 PMD_INIT_FUNC_TRACE();
2910 return i40e_vsi_add_vlan(vsi, vlan_id);
2912 return i40e_vsi_delete_vlan(vsi, vlan_id);
2916 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2917 enum rte_vlan_type vlan_type,
2920 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2921 uint64_t reg_r = 0, reg_w = 0;
2922 uint16_t reg_id = 0;
2924 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2926 switch (vlan_type) {
2927 case ETH_VLAN_TYPE_OUTER:
2933 case ETH_VLAN_TYPE_INNER:
2939 "Unsupported vlan type in single vlan.");
2945 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2948 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2950 if (ret != I40E_SUCCESS) {
2952 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2958 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2961 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2962 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2963 if (reg_r == reg_w) {
2965 PMD_DRV_LOG(DEBUG, "No need to write");
2969 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2971 if (ret != I40E_SUCCESS) {
2974 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
2979 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
2986 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2988 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2989 struct i40e_vsi *vsi = pf->main_vsi;
2991 if (mask & ETH_VLAN_FILTER_MASK) {
2992 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2993 i40e_vsi_config_vlan_filter(vsi, TRUE);
2995 i40e_vsi_config_vlan_filter(vsi, FALSE);
2998 if (mask & ETH_VLAN_STRIP_MASK) {
2999 /* Enable or disable VLAN stripping */
3000 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3001 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3003 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3006 if (mask & ETH_VLAN_EXTEND_MASK) {
3007 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3008 i40e_vsi_config_double_vlan(vsi, TRUE);
3009 /* Set global registers with default ether type value */
3010 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3012 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3016 i40e_vsi_config_double_vlan(vsi, FALSE);
3021 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3022 __rte_unused uint16_t queue,
3023 __rte_unused int on)
3025 PMD_INIT_FUNC_TRACE();
3029 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3031 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3032 struct i40e_vsi *vsi = pf->main_vsi;
3033 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3034 struct i40e_vsi_vlan_pvid_info info;
3036 memset(&info, 0, sizeof(info));
3039 info.config.pvid = pvid;
3041 info.config.reject.tagged =
3042 data->dev_conf.txmode.hw_vlan_reject_tagged;
3043 info.config.reject.untagged =
3044 data->dev_conf.txmode.hw_vlan_reject_untagged;
3047 return i40e_vsi_vlan_pvid_set(vsi, &info);
3051 i40e_dev_led_on(struct rte_eth_dev *dev)
3053 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3054 uint32_t mode = i40e_led_get(hw);
3057 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3063 i40e_dev_led_off(struct rte_eth_dev *dev)
3065 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3066 uint32_t mode = i40e_led_get(hw);
3069 i40e_led_set(hw, 0, false);
3075 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3077 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3078 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3080 fc_conf->pause_time = pf->fc_conf.pause_time;
3081 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3082 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3084 /* Return current mode according to actual setting*/
3085 switch (hw->fc.current_mode) {
3087 fc_conf->mode = RTE_FC_FULL;
3089 case I40E_FC_TX_PAUSE:
3090 fc_conf->mode = RTE_FC_TX_PAUSE;
3092 case I40E_FC_RX_PAUSE:
3093 fc_conf->mode = RTE_FC_RX_PAUSE;
3097 fc_conf->mode = RTE_FC_NONE;
3104 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3106 uint32_t mflcn_reg, fctrl_reg, reg;
3107 uint32_t max_high_water;
3108 uint8_t i, aq_failure;
3112 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3113 [RTE_FC_NONE] = I40E_FC_NONE,
3114 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3115 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3116 [RTE_FC_FULL] = I40E_FC_FULL
3119 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3121 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3122 if ((fc_conf->high_water > max_high_water) ||
3123 (fc_conf->high_water < fc_conf->low_water)) {
3125 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3130 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3131 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3132 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3134 pf->fc_conf.pause_time = fc_conf->pause_time;
3135 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3136 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3138 PMD_INIT_FUNC_TRACE();
3140 /* All the link flow control related enable/disable register
3141 * configuration is handle by the F/W
3143 err = i40e_set_fc(hw, &aq_failure, true);
3147 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3148 /* Configure flow control refresh threshold,
3149 * the value for stat_tx_pause_refresh_timer[8]
3150 * is used for global pause operation.
3154 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3155 pf->fc_conf.pause_time);
3157 /* configure the timer value included in transmitted pause
3159 * the value for stat_tx_pause_quanta[8] is used for global
3162 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3163 pf->fc_conf.pause_time);
3165 fctrl_reg = I40E_READ_REG(hw,
3166 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3168 if (fc_conf->mac_ctrl_frame_fwd != 0)
3169 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3171 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3173 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3176 /* Configure pause time (2 TCs per register) */
3177 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3178 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3179 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3181 /* Configure flow control refresh threshold value */
3182 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3183 pf->fc_conf.pause_time / 2);
3185 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3187 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3188 *depending on configuration
3190 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3191 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3192 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3194 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3195 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3198 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3201 /* config the water marker both based on the packets and bytes */
3202 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3203 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3204 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3205 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3206 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3207 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3208 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3209 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3211 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3212 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3215 I40E_WRITE_FLUSH(hw);
3221 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3222 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3224 PMD_INIT_FUNC_TRACE();
3229 /* Add a MAC address, and update filters */
3231 i40e_macaddr_add(struct rte_eth_dev *dev,
3232 struct ether_addr *mac_addr,
3233 __rte_unused uint32_t index,
3236 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3237 struct i40e_mac_filter_info mac_filter;
3238 struct i40e_vsi *vsi;
3241 /* If VMDQ not enabled or configured, return */
3242 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3243 !pf->nb_cfg_vmdq_vsi)) {
3244 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3245 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3250 if (pool > pf->nb_cfg_vmdq_vsi) {
3251 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3252 pool, pf->nb_cfg_vmdq_vsi);
3256 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3257 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3258 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3260 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3265 vsi = pf->vmdq[pool - 1].vsi;
3267 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3268 if (ret != I40E_SUCCESS) {
3269 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3274 /* Remove a MAC address, and update filters */
3276 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3278 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3279 struct i40e_vsi *vsi;
3280 struct rte_eth_dev_data *data = dev->data;
3281 struct ether_addr *macaddr;
3286 macaddr = &(data->mac_addrs[index]);
3288 pool_sel = dev->data->mac_pool_sel[index];
3290 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3291 if (pool_sel & (1ULL << i)) {
3295 /* No VMDQ pool enabled or configured */
3296 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3297 (i > pf->nb_cfg_vmdq_vsi)) {
3299 "No VMDQ pool enabled/configured");
3302 vsi = pf->vmdq[i - 1].vsi;
3304 ret = i40e_vsi_delete_mac(vsi, macaddr);
3307 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3314 /* Set perfect match or hash match of MAC and VLAN for a VF */
3316 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3317 struct rte_eth_mac_filter *filter,
3321 struct i40e_mac_filter_info mac_filter;
3322 struct ether_addr old_mac;
3323 struct ether_addr *new_mac;
3324 struct i40e_pf_vf *vf = NULL;
3329 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3332 hw = I40E_PF_TO_HW(pf);
3334 if (filter == NULL) {
3335 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3339 new_mac = &filter->mac_addr;
3341 if (is_zero_ether_addr(new_mac)) {
3342 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3346 vf_id = filter->dst_id;
3348 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3349 PMD_DRV_LOG(ERR, "Invalid argument.");
3352 vf = &pf->vfs[vf_id];
3354 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3355 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3360 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3361 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3363 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3366 mac_filter.filter_type = filter->filter_type;
3367 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3368 if (ret != I40E_SUCCESS) {
3369 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3372 ether_addr_copy(new_mac, &pf->dev_addr);
3374 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3376 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3377 if (ret != I40E_SUCCESS) {
3378 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3382 /* Clear device address as it has been removed */
3383 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3384 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3390 /* MAC filter handle */
3392 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3395 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3396 struct rte_eth_mac_filter *filter;
3397 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3398 int ret = I40E_NOT_SUPPORTED;
3400 filter = (struct rte_eth_mac_filter *)(arg);
3402 switch (filter_op) {
3403 case RTE_ETH_FILTER_NOP:
3406 case RTE_ETH_FILTER_ADD:
3407 i40e_pf_disable_irq0(hw);
3409 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3410 i40e_pf_enable_irq0(hw);
3412 case RTE_ETH_FILTER_DELETE:
3413 i40e_pf_disable_irq0(hw);
3415 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3416 i40e_pf_enable_irq0(hw);
3419 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3420 ret = I40E_ERR_PARAM;
3428 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3430 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3431 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3437 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3438 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3441 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3445 uint32_t *lut_dw = (uint32_t *)lut;
3446 uint16_t i, lut_size_dw = lut_size / 4;
3448 for (i = 0; i < lut_size_dw; i++)
3449 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3456 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3465 pf = I40E_VSI_TO_PF(vsi);
3466 hw = I40E_VSI_TO_HW(vsi);
3468 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3469 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3472 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3476 uint32_t *lut_dw = (uint32_t *)lut;
3477 uint16_t i, lut_size_dw = lut_size / 4;
3479 for (i = 0; i < lut_size_dw; i++)
3480 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3481 I40E_WRITE_FLUSH(hw);
3488 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3489 struct rte_eth_rss_reta_entry64 *reta_conf,
3492 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3493 uint16_t i, lut_size = pf->hash_lut_size;
3494 uint16_t idx, shift;
3498 if (reta_size != lut_size ||
3499 reta_size > ETH_RSS_RETA_SIZE_512) {
3501 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3502 reta_size, lut_size);
3506 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3508 PMD_DRV_LOG(ERR, "No memory can be allocated");
3511 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3514 for (i = 0; i < reta_size; i++) {
3515 idx = i / RTE_RETA_GROUP_SIZE;
3516 shift = i % RTE_RETA_GROUP_SIZE;
3517 if (reta_conf[idx].mask & (1ULL << shift))
3518 lut[i] = reta_conf[idx].reta[shift];
3520 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3529 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3530 struct rte_eth_rss_reta_entry64 *reta_conf,
3533 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3534 uint16_t i, lut_size = pf->hash_lut_size;
3535 uint16_t idx, shift;
3539 if (reta_size != lut_size ||
3540 reta_size > ETH_RSS_RETA_SIZE_512) {
3542 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3543 reta_size, lut_size);
3547 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3549 PMD_DRV_LOG(ERR, "No memory can be allocated");
3553 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3556 for (i = 0; i < reta_size; i++) {
3557 idx = i / RTE_RETA_GROUP_SIZE;
3558 shift = i % RTE_RETA_GROUP_SIZE;
3559 if (reta_conf[idx].mask & (1ULL << shift))
3560 reta_conf[idx].reta[shift] = lut[i];
3570 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3571 * @hw: pointer to the HW structure
3572 * @mem: pointer to mem struct to fill out
3573 * @size: size of memory requested
3574 * @alignment: what to align the allocation to
3576 enum i40e_status_code
3577 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3578 struct i40e_dma_mem *mem,
3582 const struct rte_memzone *mz = NULL;
3583 char z_name[RTE_MEMZONE_NAMESIZE];
3586 return I40E_ERR_PARAM;
3588 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3589 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3590 alignment, RTE_PGSIZE_2M);
3592 return I40E_ERR_NO_MEMORY;
3596 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3597 mem->zone = (const void *)mz;
3599 "memzone %s allocated with physical address: %"PRIu64,
3602 return I40E_SUCCESS;
3606 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3607 * @hw: pointer to the HW structure
3608 * @mem: ptr to mem struct to free
3610 enum i40e_status_code
3611 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3612 struct i40e_dma_mem *mem)
3615 return I40E_ERR_PARAM;
3618 "memzone %s to be freed with physical address: %"PRIu64,
3619 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3620 rte_memzone_free((const struct rte_memzone *)mem->zone);
3625 return I40E_SUCCESS;
3629 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3630 * @hw: pointer to the HW structure
3631 * @mem: pointer to mem struct to fill out
3632 * @size: size of memory requested
3634 enum i40e_status_code
3635 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3636 struct i40e_virt_mem *mem,
3640 return I40E_ERR_PARAM;
3643 mem->va = rte_zmalloc("i40e", size, 0);
3646 return I40E_SUCCESS;
3648 return I40E_ERR_NO_MEMORY;
3652 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3653 * @hw: pointer to the HW structure
3654 * @mem: pointer to mem struct to free
3656 enum i40e_status_code
3657 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3658 struct i40e_virt_mem *mem)
3661 return I40E_ERR_PARAM;
3666 return I40E_SUCCESS;
3670 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3672 rte_spinlock_init(&sp->spinlock);
3676 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3678 rte_spinlock_lock(&sp->spinlock);
3682 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3684 rte_spinlock_unlock(&sp->spinlock);
3688 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3694 * Get the hardware capabilities, which will be parsed
3695 * and saved into struct i40e_hw.
3698 i40e_get_cap(struct i40e_hw *hw)
3700 struct i40e_aqc_list_capabilities_element_resp *buf;
3701 uint16_t len, size = 0;
3704 /* Calculate a huge enough buff for saving response data temporarily */
3705 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3706 I40E_MAX_CAP_ELE_NUM;
3707 buf = rte_zmalloc("i40e", len, 0);
3709 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3710 return I40E_ERR_NO_MEMORY;
3713 /* Get, parse the capabilities and save it to hw */
3714 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3715 i40e_aqc_opc_list_func_capabilities, NULL);
3716 if (ret != I40E_SUCCESS)
3717 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3719 /* Free the temporary buffer after being used */
3726 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3728 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3729 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3730 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3731 uint16_t qp_count = 0, vsi_count = 0;
3733 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3734 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3737 /* Add the parameter init for LFC */
3738 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3739 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3740 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3742 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3743 pf->max_num_vsi = hw->func_caps.num_vsis;
3744 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3745 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3746 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3748 /* FDir queue/VSI allocation */
3749 pf->fdir_qp_offset = 0;
3750 if (hw->func_caps.fd) {
3751 pf->flags |= I40E_FLAG_FDIR;
3752 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3754 pf->fdir_nb_qps = 0;
3756 qp_count += pf->fdir_nb_qps;
3759 /* LAN queue/VSI allocation */
3760 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3761 if (!hw->func_caps.rss) {
3764 pf->flags |= I40E_FLAG_RSS;
3765 if (hw->mac.type == I40E_MAC_X722)
3766 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3767 pf->lan_nb_qps = pf->lan_nb_qp_max;
3769 qp_count += pf->lan_nb_qps;
3772 /* VF queue/VSI allocation */
3773 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3774 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3775 pf->flags |= I40E_FLAG_SRIOV;
3776 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3777 pf->vf_num = pci_dev->max_vfs;
3779 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3780 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3785 qp_count += pf->vf_nb_qps * pf->vf_num;
3786 vsi_count += pf->vf_num;
3788 /* VMDq queue/VSI allocation */
3789 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3790 pf->vmdq_nb_qps = 0;
3791 pf->max_nb_vmdq_vsi = 0;
3792 if (hw->func_caps.vmdq) {
3793 if (qp_count < hw->func_caps.num_tx_qp &&
3794 vsi_count < hw->func_caps.num_vsis) {
3795 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3796 qp_count) / pf->vmdq_nb_qp_max;
3798 /* Limit the maximum number of VMDq vsi to the maximum
3799 * ethdev can support
3801 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3802 hw->func_caps.num_vsis - vsi_count);
3803 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3805 if (pf->max_nb_vmdq_vsi) {
3806 pf->flags |= I40E_FLAG_VMDQ;
3807 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3809 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3810 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3811 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3814 "No enough queues left for VMDq");
3817 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3820 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3821 vsi_count += pf->max_nb_vmdq_vsi;
3823 if (hw->func_caps.dcb)
3824 pf->flags |= I40E_FLAG_DCB;
3826 if (qp_count > hw->func_caps.num_tx_qp) {
3828 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3829 qp_count, hw->func_caps.num_tx_qp);
3832 if (vsi_count > hw->func_caps.num_vsis) {
3834 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3835 vsi_count, hw->func_caps.num_vsis);
3843 i40e_pf_get_switch_config(struct i40e_pf *pf)
3845 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3846 struct i40e_aqc_get_switch_config_resp *switch_config;
3847 struct i40e_aqc_switch_config_element_resp *element;
3848 uint16_t start_seid = 0, num_reported;
3851 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3852 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3853 if (!switch_config) {
3854 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3858 /* Get the switch configurations */
3859 ret = i40e_aq_get_switch_config(hw, switch_config,
3860 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3861 if (ret != I40E_SUCCESS) {
3862 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3865 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3866 if (num_reported != 1) { /* The number should be 1 */
3867 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3871 /* Parse the switch configuration elements */
3872 element = &(switch_config->element[0]);
3873 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3874 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3875 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3877 PMD_DRV_LOG(INFO, "Unknown element type");
3880 rte_free(switch_config);
3886 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3889 struct pool_entry *entry;
3891 if (pool == NULL || num == 0)
3894 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3895 if (entry == NULL) {
3896 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3900 /* queue heap initialize */
3901 pool->num_free = num;
3902 pool->num_alloc = 0;
3904 LIST_INIT(&pool->alloc_list);
3905 LIST_INIT(&pool->free_list);
3907 /* Initialize element */
3911 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3916 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3918 struct pool_entry *entry, *next_entry;
3923 for (entry = LIST_FIRST(&pool->alloc_list);
3924 entry && (next_entry = LIST_NEXT(entry, next), 1);
3925 entry = next_entry) {
3926 LIST_REMOVE(entry, next);
3930 for (entry = LIST_FIRST(&pool->free_list);
3931 entry && (next_entry = LIST_NEXT(entry, next), 1);
3932 entry = next_entry) {
3933 LIST_REMOVE(entry, next);
3938 pool->num_alloc = 0;
3940 LIST_INIT(&pool->alloc_list);
3941 LIST_INIT(&pool->free_list);
3945 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3948 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3949 uint32_t pool_offset;
3953 PMD_DRV_LOG(ERR, "Invalid parameter");
3957 pool_offset = base - pool->base;
3958 /* Lookup in alloc list */
3959 LIST_FOREACH(entry, &pool->alloc_list, next) {
3960 if (entry->base == pool_offset) {
3961 valid_entry = entry;
3962 LIST_REMOVE(entry, next);
3967 /* Not find, return */
3968 if (valid_entry == NULL) {
3969 PMD_DRV_LOG(ERR, "Failed to find entry");
3974 * Found it, move it to free list and try to merge.
3975 * In order to make merge easier, always sort it by qbase.
3976 * Find adjacent prev and last entries.
3979 LIST_FOREACH(entry, &pool->free_list, next) {
3980 if (entry->base > valid_entry->base) {
3988 /* Try to merge with next one*/
3990 /* Merge with next one */
3991 if (valid_entry->base + valid_entry->len == next->base) {
3992 next->base = valid_entry->base;
3993 next->len += valid_entry->len;
3994 rte_free(valid_entry);
4001 /* Merge with previous one */
4002 if (prev->base + prev->len == valid_entry->base) {
4003 prev->len += valid_entry->len;
4004 /* If it merge with next one, remove next node */
4006 LIST_REMOVE(valid_entry, next);
4007 rte_free(valid_entry);
4009 rte_free(valid_entry);
4015 /* Not find any entry to merge, insert */
4018 LIST_INSERT_AFTER(prev, valid_entry, next);
4019 else if (next != NULL)
4020 LIST_INSERT_BEFORE(next, valid_entry, next);
4021 else /* It's empty list, insert to head */
4022 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4025 pool->num_free += valid_entry->len;
4026 pool->num_alloc -= valid_entry->len;
4032 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4035 struct pool_entry *entry, *valid_entry;
4037 if (pool == NULL || num == 0) {
4038 PMD_DRV_LOG(ERR, "Invalid parameter");
4042 if (pool->num_free < num) {
4043 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4044 num, pool->num_free);
4049 /* Lookup in free list and find most fit one */
4050 LIST_FOREACH(entry, &pool->free_list, next) {
4051 if (entry->len >= num) {
4053 if (entry->len == num) {
4054 valid_entry = entry;
4057 if (valid_entry == NULL || valid_entry->len > entry->len)
4058 valid_entry = entry;
4062 /* Not find one to satisfy the request, return */
4063 if (valid_entry == NULL) {
4064 PMD_DRV_LOG(ERR, "No valid entry found");
4068 * The entry have equal queue number as requested,
4069 * remove it from alloc_list.
4071 if (valid_entry->len == num) {
4072 LIST_REMOVE(valid_entry, next);
4075 * The entry have more numbers than requested,
4076 * create a new entry for alloc_list and minus its
4077 * queue base and number in free_list.
4079 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4080 if (entry == NULL) {
4082 "Failed to allocate memory for resource pool");
4085 entry->base = valid_entry->base;
4087 valid_entry->base += num;
4088 valid_entry->len -= num;
4089 valid_entry = entry;
4092 /* Insert it into alloc list, not sorted */
4093 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4095 pool->num_free -= valid_entry->len;
4096 pool->num_alloc += valid_entry->len;
4098 return valid_entry->base + pool->base;
4102 * bitmap_is_subset - Check whether src2 is subset of src1
4105 bitmap_is_subset(uint8_t src1, uint8_t src2)
4107 return !((src1 ^ src2) & src2);
4110 static enum i40e_status_code
4111 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4113 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4115 /* If DCB is not supported, only default TC is supported */
4116 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4117 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4118 return I40E_NOT_SUPPORTED;
4121 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4123 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4124 hw->func_caps.enabled_tcmap, enabled_tcmap);
4125 return I40E_NOT_SUPPORTED;
4127 return I40E_SUCCESS;
4131 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4132 struct i40e_vsi_vlan_pvid_info *info)
4135 struct i40e_vsi_context ctxt;
4136 uint8_t vlan_flags = 0;
4139 if (vsi == NULL || info == NULL) {
4140 PMD_DRV_LOG(ERR, "invalid parameters");
4141 return I40E_ERR_PARAM;
4145 vsi->info.pvid = info->config.pvid;
4147 * If insert pvid is enabled, only tagged pkts are
4148 * allowed to be sent out.
4150 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4151 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4154 if (info->config.reject.tagged == 0)
4155 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4157 if (info->config.reject.untagged == 0)
4158 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4160 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4161 I40E_AQ_VSI_PVLAN_MODE_MASK);
4162 vsi->info.port_vlan_flags |= vlan_flags;
4163 vsi->info.valid_sections =
4164 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4165 memset(&ctxt, 0, sizeof(ctxt));
4166 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4167 ctxt.seid = vsi->seid;
4169 hw = I40E_VSI_TO_HW(vsi);
4170 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4171 if (ret != I40E_SUCCESS)
4172 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4178 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4180 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4182 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4184 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4185 if (ret != I40E_SUCCESS)
4189 PMD_DRV_LOG(ERR, "seid not valid");
4193 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4194 tc_bw_data.tc_valid_bits = enabled_tcmap;
4195 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4196 tc_bw_data.tc_bw_credits[i] =
4197 (enabled_tcmap & (1 << i)) ? 1 : 0;
4199 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4200 if (ret != I40E_SUCCESS) {
4201 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4205 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4206 sizeof(vsi->info.qs_handle));
4207 return I40E_SUCCESS;
4210 static enum i40e_status_code
4211 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4212 struct i40e_aqc_vsi_properties_data *info,
4213 uint8_t enabled_tcmap)
4215 enum i40e_status_code ret;
4216 int i, total_tc = 0;
4217 uint16_t qpnum_per_tc, bsf, qp_idx;
4219 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4220 if (ret != I40E_SUCCESS)
4223 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4224 if (enabled_tcmap & (1 << i))
4226 vsi->enabled_tc = enabled_tcmap;
4228 /* Number of queues per enabled TC */
4229 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4230 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4231 bsf = rte_bsf32(qpnum_per_tc);
4233 /* Adjust the queue number to actual queues that can be applied */
4234 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4235 vsi->nb_qps = qpnum_per_tc * total_tc;
4238 * Configure TC and queue mapping parameters, for enabled TC,
4239 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4240 * default queue will serve it.
4243 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4244 if (vsi->enabled_tc & (1 << i)) {
4245 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4246 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4247 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4248 qp_idx += qpnum_per_tc;
4250 info->tc_mapping[i] = 0;
4253 /* Associate queue number with VSI */
4254 if (vsi->type == I40E_VSI_SRIOV) {
4255 info->mapping_flags |=
4256 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4257 for (i = 0; i < vsi->nb_qps; i++)
4258 info->queue_mapping[i] =
4259 rte_cpu_to_le_16(vsi->base_queue + i);
4261 info->mapping_flags |=
4262 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4263 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4265 info->valid_sections |=
4266 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4268 return I40E_SUCCESS;
4272 i40e_veb_release(struct i40e_veb *veb)
4274 struct i40e_vsi *vsi;
4280 if (!TAILQ_EMPTY(&veb->head)) {
4281 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4284 /* associate_vsi field is NULL for floating VEB */
4285 if (veb->associate_vsi != NULL) {
4286 vsi = veb->associate_vsi;
4287 hw = I40E_VSI_TO_HW(vsi);
4289 vsi->uplink_seid = veb->uplink_seid;
4292 veb->associate_pf->main_vsi->floating_veb = NULL;
4293 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4296 i40e_aq_delete_element(hw, veb->seid, NULL);
4298 return I40E_SUCCESS;
4302 static struct i40e_veb *
4303 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4305 struct i40e_veb *veb;
4311 "veb setup failed, associated PF shouldn't null");
4314 hw = I40E_PF_TO_HW(pf);
4316 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4318 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4322 veb->associate_vsi = vsi;
4323 veb->associate_pf = pf;
4324 TAILQ_INIT(&veb->head);
4325 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4327 /* create floating veb if vsi is NULL */
4329 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4330 I40E_DEFAULT_TCMAP, false,
4331 &veb->seid, false, NULL);
4333 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4334 true, &veb->seid, false, NULL);
4337 if (ret != I40E_SUCCESS) {
4338 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4339 hw->aq.asq_last_status);
4343 /* get statistics index */
4344 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4345 &veb->stats_idx, NULL, NULL, NULL);
4346 if (ret != I40E_SUCCESS) {
4347 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4348 hw->aq.asq_last_status);
4351 /* Get VEB bandwidth, to be implemented */
4352 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4354 vsi->uplink_seid = veb->seid;
4363 i40e_vsi_release(struct i40e_vsi *vsi)
4367 struct i40e_vsi_list *vsi_list;
4370 struct i40e_mac_filter *f;
4371 uint16_t user_param;
4374 return I40E_SUCCESS;
4379 user_param = vsi->user_param;
4381 pf = I40E_VSI_TO_PF(vsi);
4382 hw = I40E_VSI_TO_HW(vsi);
4384 /* VSI has child to attach, release child first */
4386 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4387 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4390 i40e_veb_release(vsi->veb);
4393 if (vsi->floating_veb) {
4394 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4395 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4400 /* Remove all macvlan filters of the VSI */
4401 i40e_vsi_remove_all_macvlan_filter(vsi);
4402 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4405 if (vsi->type != I40E_VSI_MAIN &&
4406 ((vsi->type != I40E_VSI_SRIOV) ||
4407 !pf->floating_veb_list[user_param])) {
4408 /* Remove vsi from parent's sibling list */
4409 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4410 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4411 return I40E_ERR_PARAM;
4413 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4414 &vsi->sib_vsi_list, list);
4416 /* Remove all switch element of the VSI */
4417 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4418 if (ret != I40E_SUCCESS)
4419 PMD_DRV_LOG(ERR, "Failed to delete element");
4422 if ((vsi->type == I40E_VSI_SRIOV) &&
4423 pf->floating_veb_list[user_param]) {
4424 /* Remove vsi from parent's sibling list */
4425 if (vsi->parent_vsi == NULL ||
4426 vsi->parent_vsi->floating_veb == NULL) {
4427 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4428 return I40E_ERR_PARAM;
4430 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4431 &vsi->sib_vsi_list, list);
4433 /* Remove all switch element of the VSI */
4434 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4435 if (ret != I40E_SUCCESS)
4436 PMD_DRV_LOG(ERR, "Failed to delete element");
4439 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4441 if (vsi->type != I40E_VSI_SRIOV)
4442 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4445 return I40E_SUCCESS;
4449 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4451 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4452 struct i40e_aqc_remove_macvlan_element_data def_filter;
4453 struct i40e_mac_filter_info filter;
4456 if (vsi->type != I40E_VSI_MAIN)
4457 return I40E_ERR_CONFIG;
4458 memset(&def_filter, 0, sizeof(def_filter));
4459 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4461 def_filter.vlan_tag = 0;
4462 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4463 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4464 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4465 if (ret != I40E_SUCCESS) {
4466 struct i40e_mac_filter *f;
4467 struct ether_addr *mac;
4469 PMD_DRV_LOG(WARNING,
4470 "Cannot remove the default macvlan filter");
4471 /* It needs to add the permanent mac into mac list */
4472 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4474 PMD_DRV_LOG(ERR, "failed to allocate memory");
4475 return I40E_ERR_NO_MEMORY;
4477 mac = &f->mac_info.mac_addr;
4478 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4480 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4481 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4486 (void)rte_memcpy(&filter.mac_addr,
4487 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4488 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4489 return i40e_vsi_add_mac(vsi, &filter);
4493 * i40e_vsi_get_bw_config - Query VSI BW Information
4494 * @vsi: the VSI to be queried
4496 * Returns 0 on success, negative value on failure
4498 static enum i40e_status_code
4499 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4501 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4502 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4503 struct i40e_hw *hw = &vsi->adapter->hw;
4508 memset(&bw_config, 0, sizeof(bw_config));
4509 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4510 if (ret != I40E_SUCCESS) {
4511 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4512 hw->aq.asq_last_status);
4516 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4517 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4518 &ets_sla_config, NULL);
4519 if (ret != I40E_SUCCESS) {
4521 "VSI failed to get TC bandwdith configuration %u",
4522 hw->aq.asq_last_status);
4526 /* store and print out BW info */
4527 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4528 vsi->bw_info.bw_max = bw_config.max_bw;
4529 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4530 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4531 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4532 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4534 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4535 vsi->bw_info.bw_ets_share_credits[i] =
4536 ets_sla_config.share_credits[i];
4537 vsi->bw_info.bw_ets_credits[i] =
4538 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4539 /* 4 bits per TC, 4th bit is reserved */
4540 vsi->bw_info.bw_ets_max[i] =
4541 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4542 RTE_LEN2MASK(3, uint8_t));
4543 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4544 vsi->bw_info.bw_ets_share_credits[i]);
4545 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4546 vsi->bw_info.bw_ets_credits[i]);
4547 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4548 vsi->bw_info.bw_ets_max[i]);
4551 return I40E_SUCCESS;
4554 /* i40e_enable_pf_lb
4555 * @pf: pointer to the pf structure
4557 * allow loopback on pf
4560 i40e_enable_pf_lb(struct i40e_pf *pf)
4562 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4563 struct i40e_vsi_context ctxt;
4566 /* Use the FW API if FW >= v5.0 */
4567 if (hw->aq.fw_maj_ver < 5) {
4568 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4572 memset(&ctxt, 0, sizeof(ctxt));
4573 ctxt.seid = pf->main_vsi_seid;
4574 ctxt.pf_num = hw->pf_id;
4575 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4577 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4578 ret, hw->aq.asq_last_status);
4581 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4582 ctxt.info.valid_sections =
4583 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4584 ctxt.info.switch_id |=
4585 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4587 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4589 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4590 hw->aq.asq_last_status);
4595 i40e_vsi_setup(struct i40e_pf *pf,
4596 enum i40e_vsi_type type,
4597 struct i40e_vsi *uplink_vsi,
4598 uint16_t user_param)
4600 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4601 struct i40e_vsi *vsi;
4602 struct i40e_mac_filter_info filter;
4604 struct i40e_vsi_context ctxt;
4605 struct ether_addr broadcast =
4606 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4608 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4609 uplink_vsi == NULL) {
4611 "VSI setup failed, VSI link shouldn't be NULL");
4615 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4617 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4622 * 1.type is not MAIN and uplink vsi is not NULL
4623 * If uplink vsi didn't setup VEB, create one first under veb field
4624 * 2.type is SRIOV and the uplink is NULL
4625 * If floating VEB is NULL, create one veb under floating veb field
4628 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4629 uplink_vsi->veb == NULL) {
4630 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4632 if (uplink_vsi->veb == NULL) {
4633 PMD_DRV_LOG(ERR, "VEB setup failed");
4636 /* set ALLOWLOOPBACk on pf, when veb is created */
4637 i40e_enable_pf_lb(pf);
4640 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4641 pf->main_vsi->floating_veb == NULL) {
4642 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4644 if (pf->main_vsi->floating_veb == NULL) {
4645 PMD_DRV_LOG(ERR, "VEB setup failed");
4650 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4652 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4655 TAILQ_INIT(&vsi->mac_list);
4657 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4658 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4659 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4660 vsi->user_param = user_param;
4661 vsi->vlan_anti_spoof_on = 0;
4662 /* Allocate queues */
4663 switch (vsi->type) {
4664 case I40E_VSI_MAIN :
4665 vsi->nb_qps = pf->lan_nb_qps;
4667 case I40E_VSI_SRIOV :
4668 vsi->nb_qps = pf->vf_nb_qps;
4670 case I40E_VSI_VMDQ2:
4671 vsi->nb_qps = pf->vmdq_nb_qps;
4674 vsi->nb_qps = pf->fdir_nb_qps;
4680 * The filter status descriptor is reported in rx queue 0,
4681 * while the tx queue for fdir filter programming has no
4682 * such constraints, can be non-zero queues.
4683 * To simplify it, choose FDIR vsi use queue 0 pair.
4684 * To make sure it will use queue 0 pair, queue allocation
4685 * need be done before this function is called
4687 if (type != I40E_VSI_FDIR) {
4688 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4690 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4694 vsi->base_queue = ret;
4696 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4698 /* VF has MSIX interrupt in VF range, don't allocate here */
4699 if (type == I40E_VSI_MAIN) {
4700 ret = i40e_res_pool_alloc(&pf->msix_pool,
4701 RTE_MIN(vsi->nb_qps,
4702 RTE_MAX_RXTX_INTR_VEC_ID));
4704 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4706 goto fail_queue_alloc;
4708 vsi->msix_intr = ret;
4709 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4710 } else if (type != I40E_VSI_SRIOV) {
4711 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4713 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4714 goto fail_queue_alloc;
4716 vsi->msix_intr = ret;
4724 if (type == I40E_VSI_MAIN) {
4725 /* For main VSI, no need to add since it's default one */
4726 vsi->uplink_seid = pf->mac_seid;
4727 vsi->seid = pf->main_vsi_seid;
4728 /* Bind queues with specific MSIX interrupt */
4730 * Needs 2 interrupt at least, one for misc cause which will
4731 * enabled from OS side, Another for queues binding the
4732 * interrupt from device side only.
4735 /* Get default VSI parameters from hardware */
4736 memset(&ctxt, 0, sizeof(ctxt));
4737 ctxt.seid = vsi->seid;
4738 ctxt.pf_num = hw->pf_id;
4739 ctxt.uplink_seid = vsi->uplink_seid;
4741 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4742 if (ret != I40E_SUCCESS) {
4743 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4744 goto fail_msix_alloc;
4746 (void)rte_memcpy(&vsi->info, &ctxt.info,
4747 sizeof(struct i40e_aqc_vsi_properties_data));
4748 vsi->vsi_id = ctxt.vsi_number;
4749 vsi->info.valid_sections = 0;
4751 /* Configure tc, enabled TC0 only */
4752 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4754 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4755 goto fail_msix_alloc;
4758 /* TC, queue mapping */
4759 memset(&ctxt, 0, sizeof(ctxt));
4760 vsi->info.valid_sections |=
4761 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4762 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4763 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4764 (void)rte_memcpy(&ctxt.info, &vsi->info,
4765 sizeof(struct i40e_aqc_vsi_properties_data));
4766 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4767 I40E_DEFAULT_TCMAP);
4768 if (ret != I40E_SUCCESS) {
4770 "Failed to configure TC queue mapping");
4771 goto fail_msix_alloc;
4773 ctxt.seid = vsi->seid;
4774 ctxt.pf_num = hw->pf_id;
4775 ctxt.uplink_seid = vsi->uplink_seid;
4778 /* Update VSI parameters */
4779 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4780 if (ret != I40E_SUCCESS) {
4781 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4782 goto fail_msix_alloc;
4785 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4786 sizeof(vsi->info.tc_mapping));
4787 (void)rte_memcpy(&vsi->info.queue_mapping,
4788 &ctxt.info.queue_mapping,
4789 sizeof(vsi->info.queue_mapping));
4790 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4791 vsi->info.valid_sections = 0;
4793 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4797 * Updating default filter settings are necessary to prevent
4798 * reception of tagged packets.
4799 * Some old firmware configurations load a default macvlan
4800 * filter which accepts both tagged and untagged packets.
4801 * The updating is to use a normal filter instead if needed.
4802 * For NVM 4.2.2 or after, the updating is not needed anymore.
4803 * The firmware with correct configurations load the default
4804 * macvlan filter which is expected and cannot be removed.
4806 i40e_update_default_filter_setting(vsi);
4807 i40e_config_qinq(hw, vsi);
4808 } else if (type == I40E_VSI_SRIOV) {
4809 memset(&ctxt, 0, sizeof(ctxt));
4811 * For other VSI, the uplink_seid equals to uplink VSI's
4812 * uplink_seid since they share same VEB
4814 if (uplink_vsi == NULL)
4815 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4817 vsi->uplink_seid = uplink_vsi->uplink_seid;
4818 ctxt.pf_num = hw->pf_id;
4819 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4820 ctxt.uplink_seid = vsi->uplink_seid;
4821 ctxt.connection_type = 0x1;
4822 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4824 /* Use the VEB configuration if FW >= v5.0 */
4825 if (hw->aq.fw_maj_ver >= 5) {
4826 /* Configure switch ID */
4827 ctxt.info.valid_sections |=
4828 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4829 ctxt.info.switch_id =
4830 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4833 /* Configure port/vlan */
4834 ctxt.info.valid_sections |=
4835 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4836 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4837 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4838 I40E_DEFAULT_TCMAP);
4839 if (ret != I40E_SUCCESS) {
4841 "Failed to configure TC queue mapping");
4842 goto fail_msix_alloc;
4844 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4845 ctxt.info.valid_sections |=
4846 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4848 * Since VSI is not created yet, only configure parameter,
4849 * will add vsi below.
4852 i40e_config_qinq(hw, vsi);
4853 } else if (type == I40E_VSI_VMDQ2) {
4854 memset(&ctxt, 0, sizeof(ctxt));
4856 * For other VSI, the uplink_seid equals to uplink VSI's
4857 * uplink_seid since they share same VEB
4859 vsi->uplink_seid = uplink_vsi->uplink_seid;
4860 ctxt.pf_num = hw->pf_id;
4862 ctxt.uplink_seid = vsi->uplink_seid;
4863 ctxt.connection_type = 0x1;
4864 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4866 ctxt.info.valid_sections |=
4867 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4868 /* user_param carries flag to enable loop back */
4870 ctxt.info.switch_id =
4871 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4872 ctxt.info.switch_id |=
4873 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4876 /* Configure port/vlan */
4877 ctxt.info.valid_sections |=
4878 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4879 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4880 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4881 I40E_DEFAULT_TCMAP);
4882 if (ret != I40E_SUCCESS) {
4884 "Failed to configure TC queue mapping");
4885 goto fail_msix_alloc;
4887 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4888 ctxt.info.valid_sections |=
4889 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4890 } else if (type == I40E_VSI_FDIR) {
4891 memset(&ctxt, 0, sizeof(ctxt));
4892 vsi->uplink_seid = uplink_vsi->uplink_seid;
4893 ctxt.pf_num = hw->pf_id;
4895 ctxt.uplink_seid = vsi->uplink_seid;
4896 ctxt.connection_type = 0x1; /* regular data port */
4897 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4898 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4899 I40E_DEFAULT_TCMAP);
4900 if (ret != I40E_SUCCESS) {
4902 "Failed to configure TC queue mapping.");
4903 goto fail_msix_alloc;
4905 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4906 ctxt.info.valid_sections |=
4907 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4909 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4910 goto fail_msix_alloc;
4913 if (vsi->type != I40E_VSI_MAIN) {
4914 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4915 if (ret != I40E_SUCCESS) {
4916 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4917 hw->aq.asq_last_status);
4918 goto fail_msix_alloc;
4920 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4921 vsi->info.valid_sections = 0;
4922 vsi->seid = ctxt.seid;
4923 vsi->vsi_id = ctxt.vsi_number;
4924 vsi->sib_vsi_list.vsi = vsi;
4925 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4926 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4927 &vsi->sib_vsi_list, list);
4929 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4930 &vsi->sib_vsi_list, list);
4934 /* MAC/VLAN configuration */
4935 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4936 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4938 ret = i40e_vsi_add_mac(vsi, &filter);
4939 if (ret != I40E_SUCCESS) {
4940 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4941 goto fail_msix_alloc;
4944 /* Get VSI BW information */
4945 i40e_vsi_get_bw_config(vsi);
4948 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4950 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4956 /* Configure vlan filter on or off */
4958 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4961 struct i40e_mac_filter *f;
4963 struct i40e_mac_filter_info *mac_filter;
4964 enum rte_mac_filter_type desired_filter;
4965 int ret = I40E_SUCCESS;
4968 /* Filter to match MAC and VLAN */
4969 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4971 /* Filter to match only MAC */
4972 desired_filter = RTE_MAC_PERFECT_MATCH;
4977 mac_filter = rte_zmalloc("mac_filter_info_data",
4978 num * sizeof(*mac_filter), 0);
4979 if (mac_filter == NULL) {
4980 PMD_DRV_LOG(ERR, "failed to allocate memory");
4981 return I40E_ERR_NO_MEMORY;
4986 /* Remove all existing mac */
4987 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4988 mac_filter[i] = f->mac_info;
4989 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4991 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4992 on ? "enable" : "disable");
4998 /* Override with new filter */
4999 for (i = 0; i < num; i++) {
5000 mac_filter[i].filter_type = desired_filter;
5001 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5003 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5004 on ? "enable" : "disable");
5010 rte_free(mac_filter);
5014 /* Configure vlan stripping on or off */
5016 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5018 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5019 struct i40e_vsi_context ctxt;
5021 int ret = I40E_SUCCESS;
5023 /* Check if it has been already on or off */
5024 if (vsi->info.valid_sections &
5025 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5027 if ((vsi->info.port_vlan_flags &
5028 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5029 return 0; /* already on */
5031 if ((vsi->info.port_vlan_flags &
5032 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5033 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5034 return 0; /* already off */
5039 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5041 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5042 vsi->info.valid_sections =
5043 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5044 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5045 vsi->info.port_vlan_flags |= vlan_flags;
5046 ctxt.seid = vsi->seid;
5047 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5048 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5050 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5051 on ? "enable" : "disable");
5057 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5059 struct rte_eth_dev_data *data = dev->data;
5063 /* Apply vlan offload setting */
5064 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5065 i40e_vlan_offload_set(dev, mask);
5067 /* Apply double-vlan setting, not implemented yet */
5069 /* Apply pvid setting */
5070 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5071 data->dev_conf.txmode.hw_vlan_insert_pvid);
5073 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5079 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5081 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5083 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5087 i40e_update_flow_control(struct i40e_hw *hw)
5089 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5090 struct i40e_link_status link_status;
5091 uint32_t rxfc = 0, txfc = 0, reg;
5095 memset(&link_status, 0, sizeof(link_status));
5096 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5097 if (ret != I40E_SUCCESS) {
5098 PMD_DRV_LOG(ERR, "Failed to get link status information");
5099 goto write_reg; /* Disable flow control */
5102 an_info = hw->phy.link_info.an_info;
5103 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5104 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5105 ret = I40E_ERR_NOT_READY;
5106 goto write_reg; /* Disable flow control */
5109 * If link auto negotiation is enabled, flow control needs to
5110 * be configured according to it
5112 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5113 case I40E_LINK_PAUSE_RXTX:
5116 hw->fc.current_mode = I40E_FC_FULL;
5118 case I40E_AQ_LINK_PAUSE_RX:
5120 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5122 case I40E_AQ_LINK_PAUSE_TX:
5124 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5127 hw->fc.current_mode = I40E_FC_NONE;
5132 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5133 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5134 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5135 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5136 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5137 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5144 i40e_pf_setup(struct i40e_pf *pf)
5146 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5147 struct i40e_filter_control_settings settings;
5148 struct i40e_vsi *vsi;
5151 /* Clear all stats counters */
5152 pf->offset_loaded = FALSE;
5153 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5154 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5156 ret = i40e_pf_get_switch_config(pf);
5157 if (ret != I40E_SUCCESS) {
5158 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5161 if (pf->flags & I40E_FLAG_FDIR) {
5162 /* make queue allocated first, let FDIR use queue pair 0*/
5163 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5164 if (ret != I40E_FDIR_QUEUE_ID) {
5166 "queue allocation fails for FDIR: ret =%d",
5168 pf->flags &= ~I40E_FLAG_FDIR;
5171 /* main VSI setup */
5172 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5174 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5175 return I40E_ERR_NOT_READY;
5179 /* Configure filter control */
5180 memset(&settings, 0, sizeof(settings));
5181 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5182 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5183 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5184 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5186 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5187 hw->func_caps.rss_table_size);
5188 return I40E_ERR_PARAM;
5190 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5191 hw->func_caps.rss_table_size);
5192 pf->hash_lut_size = hw->func_caps.rss_table_size;
5194 /* Enable ethtype and macvlan filters */
5195 settings.enable_ethtype = TRUE;
5196 settings.enable_macvlan = TRUE;
5197 ret = i40e_set_filter_control(hw, &settings);
5199 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5202 /* Update flow control according to the auto negotiation */
5203 i40e_update_flow_control(hw);
5205 return I40E_SUCCESS;
5209 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5215 * Set or clear TX Queue Disable flags,
5216 * which is required by hardware.
5218 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5219 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5221 /* Wait until the request is finished */
5222 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5223 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5224 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5225 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5226 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5232 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5233 return I40E_SUCCESS; /* already on, skip next steps */
5235 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5236 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5238 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5239 return I40E_SUCCESS; /* already off, skip next steps */
5240 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5242 /* Write the register */
5243 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5244 /* Check the result */
5245 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5246 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5247 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5249 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5250 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5253 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5254 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5258 /* Check if it is timeout */
5259 if (j >= I40E_CHK_Q_ENA_COUNT) {
5260 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5261 (on ? "enable" : "disable"), q_idx);
5262 return I40E_ERR_TIMEOUT;
5265 return I40E_SUCCESS;
5268 /* Swith on or off the tx queues */
5270 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5272 struct rte_eth_dev_data *dev_data = pf->dev_data;
5273 struct i40e_tx_queue *txq;
5274 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5278 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5279 txq = dev_data->tx_queues[i];
5280 /* Don't operate the queue if not configured or
5281 * if starting only per queue */
5282 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5285 ret = i40e_dev_tx_queue_start(dev, i);
5287 ret = i40e_dev_tx_queue_stop(dev, i);
5288 if ( ret != I40E_SUCCESS)
5292 return I40E_SUCCESS;
5296 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5301 /* Wait until the request is finished */
5302 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5303 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5304 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5305 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5306 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5311 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5312 return I40E_SUCCESS; /* Already on, skip next steps */
5313 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5315 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5316 return I40E_SUCCESS; /* Already off, skip next steps */
5317 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5320 /* Write the register */
5321 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5322 /* Check the result */
5323 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5324 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5325 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5327 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5328 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5331 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5332 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5337 /* Check if it is timeout */
5338 if (j >= I40E_CHK_Q_ENA_COUNT) {
5339 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5340 (on ? "enable" : "disable"), q_idx);
5341 return I40E_ERR_TIMEOUT;
5344 return I40E_SUCCESS;
5346 /* Switch on or off the rx queues */
5348 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5350 struct rte_eth_dev_data *dev_data = pf->dev_data;
5351 struct i40e_rx_queue *rxq;
5352 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5356 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5357 rxq = dev_data->rx_queues[i];
5358 /* Don't operate the queue if not configured or
5359 * if starting only per queue */
5360 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5363 ret = i40e_dev_rx_queue_start(dev, i);
5365 ret = i40e_dev_rx_queue_stop(dev, i);
5366 if (ret != I40E_SUCCESS)
5370 return I40E_SUCCESS;
5373 /* Switch on or off all the rx/tx queues */
5375 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5380 /* enable rx queues before enabling tx queues */
5381 ret = i40e_dev_switch_rx_queues(pf, on);
5383 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5386 ret = i40e_dev_switch_tx_queues(pf, on);
5388 /* Stop tx queues before stopping rx queues */
5389 ret = i40e_dev_switch_tx_queues(pf, on);
5391 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5394 ret = i40e_dev_switch_rx_queues(pf, on);
5400 /* Initialize VSI for TX */
5402 i40e_dev_tx_init(struct i40e_pf *pf)
5404 struct rte_eth_dev_data *data = pf->dev_data;
5406 uint32_t ret = I40E_SUCCESS;
5407 struct i40e_tx_queue *txq;
5409 for (i = 0; i < data->nb_tx_queues; i++) {
5410 txq = data->tx_queues[i];
5411 if (!txq || !txq->q_set)
5413 ret = i40e_tx_queue_init(txq);
5414 if (ret != I40E_SUCCESS)
5417 if (ret == I40E_SUCCESS)
5418 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5424 /* Initialize VSI for RX */
5426 i40e_dev_rx_init(struct i40e_pf *pf)
5428 struct rte_eth_dev_data *data = pf->dev_data;
5429 int ret = I40E_SUCCESS;
5431 struct i40e_rx_queue *rxq;
5433 i40e_pf_config_mq_rx(pf);
5434 for (i = 0; i < data->nb_rx_queues; i++) {
5435 rxq = data->rx_queues[i];
5436 if (!rxq || !rxq->q_set)
5439 ret = i40e_rx_queue_init(rxq);
5440 if (ret != I40E_SUCCESS) {
5442 "Failed to do RX queue initialization");
5446 if (ret == I40E_SUCCESS)
5447 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5454 i40e_dev_rxtx_init(struct i40e_pf *pf)
5458 err = i40e_dev_tx_init(pf);
5460 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5463 err = i40e_dev_rx_init(pf);
5465 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5473 i40e_vmdq_setup(struct rte_eth_dev *dev)
5475 struct rte_eth_conf *conf = &dev->data->dev_conf;
5476 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5477 int i, err, conf_vsis, j, loop;
5478 struct i40e_vsi *vsi;
5479 struct i40e_vmdq_info *vmdq_info;
5480 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5481 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5484 * Disable interrupt to avoid message from VF. Furthermore, it will
5485 * avoid race condition in VSI creation/destroy.
5487 i40e_pf_disable_irq0(hw);
5489 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5490 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5494 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5495 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5496 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5497 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5498 pf->max_nb_vmdq_vsi);
5502 if (pf->vmdq != NULL) {
5503 PMD_INIT_LOG(INFO, "VMDQ already configured");
5507 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5508 sizeof(*vmdq_info) * conf_vsis, 0);
5510 if (pf->vmdq == NULL) {
5511 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5515 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5517 /* Create VMDQ VSI */
5518 for (i = 0; i < conf_vsis; i++) {
5519 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5520 vmdq_conf->enable_loop_back);
5522 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5526 vmdq_info = &pf->vmdq[i];
5528 vmdq_info->vsi = vsi;
5530 pf->nb_cfg_vmdq_vsi = conf_vsis;
5532 /* Configure Vlan */
5533 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5534 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5535 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5536 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5537 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5538 vmdq_conf->pool_map[i].vlan_id, j);
5540 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5541 vmdq_conf->pool_map[i].vlan_id);
5543 PMD_INIT_LOG(ERR, "Failed to add vlan");
5551 i40e_pf_enable_irq0(hw);
5556 for (i = 0; i < conf_vsis; i++)
5557 if (pf->vmdq[i].vsi == NULL)
5560 i40e_vsi_release(pf->vmdq[i].vsi);
5564 i40e_pf_enable_irq0(hw);
5569 i40e_stat_update_32(struct i40e_hw *hw,
5577 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5581 if (new_data >= *offset)
5582 *stat = (uint64_t)(new_data - *offset);
5584 *stat = (uint64_t)((new_data +
5585 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5589 i40e_stat_update_48(struct i40e_hw *hw,
5598 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5599 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5600 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5605 if (new_data >= *offset)
5606 *stat = new_data - *offset;
5608 *stat = (uint64_t)((new_data +
5609 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5611 *stat &= I40E_48_BIT_MASK;
5616 i40e_pf_disable_irq0(struct i40e_hw *hw)
5618 /* Disable all interrupt types */
5619 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5620 I40E_WRITE_FLUSH(hw);
5625 i40e_pf_enable_irq0(struct i40e_hw *hw)
5627 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5628 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5629 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5630 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5631 I40E_WRITE_FLUSH(hw);
5635 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5637 /* read pending request and disable first */
5638 i40e_pf_disable_irq0(hw);
5639 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5640 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5641 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5644 /* Link no queues with irq0 */
5645 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5646 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5650 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5652 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5653 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5656 uint32_t index, offset, val;
5661 * Try to find which VF trigger a reset, use absolute VF id to access
5662 * since the reg is global register.
5664 for (i = 0; i < pf->vf_num; i++) {
5665 abs_vf_id = hw->func_caps.vf_base_id + i;
5666 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5667 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5668 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5669 /* VFR event occured */
5670 if (val & (0x1 << offset)) {
5673 /* Clear the event first */
5674 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5676 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5678 * Only notify a VF reset event occured,
5679 * don't trigger another SW reset
5681 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5682 if (ret != I40E_SUCCESS)
5683 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5689 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5691 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5692 struct i40e_virtchnl_pf_event event;
5695 event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5696 event.event_data.link_event.link_status =
5697 dev->data->dev_link.link_status;
5698 event.event_data.link_event.link_speed =
5699 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5701 for (i = 0; i < pf->vf_num; i++)
5702 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5703 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5707 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5709 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5710 struct i40e_arq_event_info info;
5711 uint16_t pending, opcode;
5714 info.buf_len = I40E_AQ_BUF_SZ;
5715 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5716 if (!info.msg_buf) {
5717 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5723 ret = i40e_clean_arq_element(hw, &info, &pending);
5725 if (ret != I40E_SUCCESS) {
5727 "Failed to read msg from AdminQ, aq_err: %u",
5728 hw->aq.asq_last_status);
5731 opcode = rte_le_to_cpu_16(info.desc.opcode);
5734 case i40e_aqc_opc_send_msg_to_pf:
5735 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5736 i40e_pf_host_handle_vf_msg(dev,
5737 rte_le_to_cpu_16(info.desc.retval),
5738 rte_le_to_cpu_32(info.desc.cookie_high),
5739 rte_le_to_cpu_32(info.desc.cookie_low),
5743 case i40e_aqc_opc_get_link_status:
5744 ret = i40e_dev_link_update(dev, 0);
5746 i40e_notify_all_vfs_link_status(dev);
5747 _rte_eth_dev_callback_process(dev,
5748 RTE_ETH_EVENT_INTR_LSC, NULL);
5752 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5757 rte_free(info.msg_buf);
5761 * Interrupt handler triggered by NIC for handling
5762 * specific interrupt.
5765 * Pointer to interrupt handle.
5767 * The address of parameter (struct rte_eth_dev *) regsitered before.
5773 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5776 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5777 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5780 /* Disable interrupt */
5781 i40e_pf_disable_irq0(hw);
5783 /* read out interrupt causes */
5784 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5786 /* No interrupt event indicated */
5787 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5788 PMD_DRV_LOG(INFO, "No interrupt event");
5791 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5792 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5793 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5794 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5795 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5796 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5797 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5798 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5799 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5800 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5801 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5802 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5803 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5804 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5805 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5806 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5808 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5809 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5810 i40e_dev_handle_vfr_event(dev);
5812 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5813 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5814 i40e_dev_handle_aq_msg(dev);
5818 /* Enable interrupt */
5819 i40e_pf_enable_irq0(hw);
5820 rte_intr_enable(intr_handle);
5824 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5825 struct i40e_macvlan_filter *filter,
5828 int ele_num, ele_buff_size;
5829 int num, actual_num, i;
5831 int ret = I40E_SUCCESS;
5832 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5833 struct i40e_aqc_add_macvlan_element_data *req_list;
5835 if (filter == NULL || total == 0)
5836 return I40E_ERR_PARAM;
5837 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5838 ele_buff_size = hw->aq.asq_buf_size;
5840 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5841 if (req_list == NULL) {
5842 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5843 return I40E_ERR_NO_MEMORY;
5848 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5849 memset(req_list, 0, ele_buff_size);
5851 for (i = 0; i < actual_num; i++) {
5852 (void)rte_memcpy(req_list[i].mac_addr,
5853 &filter[num + i].macaddr, ETH_ADDR_LEN);
5854 req_list[i].vlan_tag =
5855 rte_cpu_to_le_16(filter[num + i].vlan_id);
5857 switch (filter[num + i].filter_type) {
5858 case RTE_MAC_PERFECT_MATCH:
5859 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5860 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5862 case RTE_MACVLAN_PERFECT_MATCH:
5863 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5865 case RTE_MAC_HASH_MATCH:
5866 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5867 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5869 case RTE_MACVLAN_HASH_MATCH:
5870 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5873 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5874 ret = I40E_ERR_PARAM;
5878 req_list[i].queue_number = 0;
5880 req_list[i].flags = rte_cpu_to_le_16(flags);
5883 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5885 if (ret != I40E_SUCCESS) {
5886 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5890 } while (num < total);
5898 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5899 struct i40e_macvlan_filter *filter,
5902 int ele_num, ele_buff_size;
5903 int num, actual_num, i;
5905 int ret = I40E_SUCCESS;
5906 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5907 struct i40e_aqc_remove_macvlan_element_data *req_list;
5909 if (filter == NULL || total == 0)
5910 return I40E_ERR_PARAM;
5912 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5913 ele_buff_size = hw->aq.asq_buf_size;
5915 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5916 if (req_list == NULL) {
5917 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5918 return I40E_ERR_NO_MEMORY;
5923 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5924 memset(req_list, 0, ele_buff_size);
5926 for (i = 0; i < actual_num; i++) {
5927 (void)rte_memcpy(req_list[i].mac_addr,
5928 &filter[num + i].macaddr, ETH_ADDR_LEN);
5929 req_list[i].vlan_tag =
5930 rte_cpu_to_le_16(filter[num + i].vlan_id);
5932 switch (filter[num + i].filter_type) {
5933 case RTE_MAC_PERFECT_MATCH:
5934 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5935 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5937 case RTE_MACVLAN_PERFECT_MATCH:
5938 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5940 case RTE_MAC_HASH_MATCH:
5941 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5942 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5944 case RTE_MACVLAN_HASH_MATCH:
5945 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5948 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5949 ret = I40E_ERR_PARAM;
5952 req_list[i].flags = rte_cpu_to_le_16(flags);
5955 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5957 if (ret != I40E_SUCCESS) {
5958 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5962 } while (num < total);
5969 /* Find out specific MAC filter */
5970 static struct i40e_mac_filter *
5971 i40e_find_mac_filter(struct i40e_vsi *vsi,
5972 struct ether_addr *macaddr)
5974 struct i40e_mac_filter *f;
5976 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5977 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5985 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5988 uint32_t vid_idx, vid_bit;
5990 if (vlan_id > ETH_VLAN_ID_MAX)
5993 vid_idx = I40E_VFTA_IDX(vlan_id);
5994 vid_bit = I40E_VFTA_BIT(vlan_id);
5996 if (vsi->vfta[vid_idx] & vid_bit)
6003 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6004 uint16_t vlan_id, bool on)
6006 uint32_t vid_idx, vid_bit;
6008 vid_idx = I40E_VFTA_IDX(vlan_id);
6009 vid_bit = I40E_VFTA_BIT(vlan_id);
6012 vsi->vfta[vid_idx] |= vid_bit;
6014 vsi->vfta[vid_idx] &= ~vid_bit;
6018 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6019 uint16_t vlan_id, bool on)
6021 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6022 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6025 if (vlan_id > ETH_VLAN_ID_MAX)
6028 i40e_store_vlan_filter(vsi, vlan_id, on);
6030 if (!vsi->vlan_anti_spoof_on || !vlan_id)
6033 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6036 ret = i40e_aq_add_vlan(hw, vsi->seid,
6037 &vlan_data, 1, NULL);
6038 if (ret != I40E_SUCCESS)
6039 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6041 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6042 &vlan_data, 1, NULL);
6043 if (ret != I40E_SUCCESS)
6045 "Failed to remove vlan filter");
6050 * Find all vlan options for specific mac addr,
6051 * return with actual vlan found.
6054 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6055 struct i40e_macvlan_filter *mv_f,
6056 int num, struct ether_addr *addr)
6062 * Not to use i40e_find_vlan_filter to decrease the loop time,
6063 * although the code looks complex.
6065 if (num < vsi->vlan_num)
6066 return I40E_ERR_PARAM;
6069 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6071 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6072 if (vsi->vfta[j] & (1 << k)) {
6075 "vlan number doesn't match");
6076 return I40E_ERR_PARAM;
6078 (void)rte_memcpy(&mv_f[i].macaddr,
6079 addr, ETH_ADDR_LEN);
6081 j * I40E_UINT32_BIT_SIZE + k;
6087 return I40E_SUCCESS;
6091 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6092 struct i40e_macvlan_filter *mv_f,
6097 struct i40e_mac_filter *f;
6099 if (num < vsi->mac_num)
6100 return I40E_ERR_PARAM;
6102 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6104 PMD_DRV_LOG(ERR, "buffer number not match");
6105 return I40E_ERR_PARAM;
6107 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6109 mv_f[i].vlan_id = vlan;
6110 mv_f[i].filter_type = f->mac_info.filter_type;
6114 return I40E_SUCCESS;
6118 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6121 struct i40e_mac_filter *f;
6122 struct i40e_macvlan_filter *mv_f;
6123 int ret = I40E_SUCCESS;
6125 if (vsi == NULL || vsi->mac_num == 0)
6126 return I40E_ERR_PARAM;
6128 /* Case that no vlan is set */
6129 if (vsi->vlan_num == 0)
6132 num = vsi->mac_num * vsi->vlan_num;
6134 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6136 PMD_DRV_LOG(ERR, "failed to allocate memory");
6137 return I40E_ERR_NO_MEMORY;
6141 if (vsi->vlan_num == 0) {
6142 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6143 (void)rte_memcpy(&mv_f[i].macaddr,
6144 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6145 mv_f[i].filter_type = f->mac_info.filter_type;
6146 mv_f[i].vlan_id = 0;
6150 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6151 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6152 vsi->vlan_num, &f->mac_info.mac_addr);
6153 if (ret != I40E_SUCCESS)
6155 for (j = i; j < i + vsi->vlan_num; j++)
6156 mv_f[j].filter_type = f->mac_info.filter_type;
6161 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6169 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6171 struct i40e_macvlan_filter *mv_f;
6173 int ret = I40E_SUCCESS;
6175 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6176 return I40E_ERR_PARAM;
6178 /* If it's already set, just return */
6179 if (i40e_find_vlan_filter(vsi,vlan))
6180 return I40E_SUCCESS;
6182 mac_num = vsi->mac_num;
6185 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6186 return I40E_ERR_PARAM;
6189 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6192 PMD_DRV_LOG(ERR, "failed to allocate memory");
6193 return I40E_ERR_NO_MEMORY;
6196 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6198 if (ret != I40E_SUCCESS)
6201 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6203 if (ret != I40E_SUCCESS)
6206 i40e_set_vlan_filter(vsi, vlan, 1);
6216 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6218 struct i40e_macvlan_filter *mv_f;
6220 int ret = I40E_SUCCESS;
6223 * Vlan 0 is the generic filter for untagged packets
6224 * and can't be removed.
6226 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6227 return I40E_ERR_PARAM;
6229 /* If can't find it, just return */
6230 if (!i40e_find_vlan_filter(vsi, vlan))
6231 return I40E_ERR_PARAM;
6233 mac_num = vsi->mac_num;
6236 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6237 return I40E_ERR_PARAM;
6240 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6243 PMD_DRV_LOG(ERR, "failed to allocate memory");
6244 return I40E_ERR_NO_MEMORY;
6247 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6249 if (ret != I40E_SUCCESS)
6252 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6254 if (ret != I40E_SUCCESS)
6257 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6258 if (vsi->vlan_num == 1) {
6259 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6260 if (ret != I40E_SUCCESS)
6263 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6264 if (ret != I40E_SUCCESS)
6268 i40e_set_vlan_filter(vsi, vlan, 0);
6278 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6280 struct i40e_mac_filter *f;
6281 struct i40e_macvlan_filter *mv_f;
6282 int i, vlan_num = 0;
6283 int ret = I40E_SUCCESS;
6285 /* If it's add and we've config it, return */
6286 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6288 return I40E_SUCCESS;
6289 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6290 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6293 * If vlan_num is 0, that's the first time to add mac,
6294 * set mask for vlan_id 0.
6296 if (vsi->vlan_num == 0) {
6297 i40e_set_vlan_filter(vsi, 0, 1);
6300 vlan_num = vsi->vlan_num;
6301 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6302 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6305 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6307 PMD_DRV_LOG(ERR, "failed to allocate memory");
6308 return I40E_ERR_NO_MEMORY;
6311 for (i = 0; i < vlan_num; i++) {
6312 mv_f[i].filter_type = mac_filter->filter_type;
6313 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6317 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6318 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6319 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6320 &mac_filter->mac_addr);
6321 if (ret != I40E_SUCCESS)
6325 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6326 if (ret != I40E_SUCCESS)
6329 /* Add the mac addr into mac list */
6330 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6332 PMD_DRV_LOG(ERR, "failed to allocate memory");
6333 ret = I40E_ERR_NO_MEMORY;
6336 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6338 f->mac_info.filter_type = mac_filter->filter_type;
6339 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6350 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6352 struct i40e_mac_filter *f;
6353 struct i40e_macvlan_filter *mv_f;
6355 enum rte_mac_filter_type filter_type;
6356 int ret = I40E_SUCCESS;
6358 /* Can't find it, return an error */
6359 f = i40e_find_mac_filter(vsi, addr);
6361 return I40E_ERR_PARAM;
6363 vlan_num = vsi->vlan_num;
6364 filter_type = f->mac_info.filter_type;
6365 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6366 filter_type == RTE_MACVLAN_HASH_MATCH) {
6367 if (vlan_num == 0) {
6368 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6369 return I40E_ERR_PARAM;
6371 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6372 filter_type == RTE_MAC_HASH_MATCH)
6375 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6377 PMD_DRV_LOG(ERR, "failed to allocate memory");
6378 return I40E_ERR_NO_MEMORY;
6381 for (i = 0; i < vlan_num; i++) {
6382 mv_f[i].filter_type = filter_type;
6383 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6386 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6387 filter_type == RTE_MACVLAN_HASH_MATCH) {
6388 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6389 if (ret != I40E_SUCCESS)
6393 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6394 if (ret != I40E_SUCCESS)
6397 /* Remove the mac addr into mac list */
6398 TAILQ_REMOVE(&vsi->mac_list, f, next);
6408 /* Configure hash enable flags for RSS */
6410 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6417 if (flags & ETH_RSS_FRAG_IPV4)
6418 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6419 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6420 if (type == I40E_MAC_X722) {
6421 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6422 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6424 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6426 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6427 if (type == I40E_MAC_X722) {
6428 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6429 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6430 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6432 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6434 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6435 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6436 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6437 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6438 if (flags & ETH_RSS_FRAG_IPV6)
6439 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6440 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6441 if (type == I40E_MAC_X722) {
6442 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6443 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6445 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6447 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6448 if (type == I40E_MAC_X722) {
6449 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6450 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6451 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6453 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6455 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6456 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6457 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6458 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6459 if (flags & ETH_RSS_L2_PAYLOAD)
6460 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6465 /* Parse the hash enable flags */
6467 i40e_parse_hena(uint64_t flags)
6469 uint64_t rss_hf = 0;
6473 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6474 rss_hf |= ETH_RSS_FRAG_IPV4;
6475 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6476 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6477 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6478 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6479 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6480 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6481 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6482 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6483 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6484 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6485 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6486 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6487 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6488 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6489 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6490 rss_hf |= ETH_RSS_FRAG_IPV6;
6491 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6492 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6493 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6494 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6495 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6496 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6497 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6498 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6499 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6500 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6501 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6502 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6503 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6504 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6505 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6506 rss_hf |= ETH_RSS_L2_PAYLOAD;
6513 i40e_pf_disable_rss(struct i40e_pf *pf)
6515 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6518 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6519 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6520 if (hw->mac.type == I40E_MAC_X722)
6521 hena &= ~I40E_RSS_HENA_ALL_X722;
6523 hena &= ~I40E_RSS_HENA_ALL;
6524 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6525 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6526 I40E_WRITE_FLUSH(hw);
6530 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6532 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6533 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6536 if (!key || key_len == 0) {
6537 PMD_DRV_LOG(DEBUG, "No key to be configured");
6539 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6541 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6545 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6546 struct i40e_aqc_get_set_rss_key_data *key_dw =
6547 (struct i40e_aqc_get_set_rss_key_data *)key;
6549 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6551 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6553 uint32_t *hash_key = (uint32_t *)key;
6556 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6557 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6558 I40E_WRITE_FLUSH(hw);
6565 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6567 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6568 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6571 if (!key || !key_len)
6574 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6575 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6576 (struct i40e_aqc_get_set_rss_key_data *)key);
6578 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6582 uint32_t *key_dw = (uint32_t *)key;
6585 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6586 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6588 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6594 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6596 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6601 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6602 rss_conf->rss_key_len);
6606 rss_hf = rss_conf->rss_hf;
6607 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6608 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6609 if (hw->mac.type == I40E_MAC_X722)
6610 hena &= ~I40E_RSS_HENA_ALL_X722;
6612 hena &= ~I40E_RSS_HENA_ALL;
6613 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6614 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6615 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6616 I40E_WRITE_FLUSH(hw);
6622 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6623 struct rte_eth_rss_conf *rss_conf)
6625 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6626 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6627 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6630 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6631 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6632 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6633 ? I40E_RSS_HENA_ALL_X722
6634 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6635 if (rss_hf != 0) /* Enable RSS */
6637 return 0; /* Nothing to do */
6640 if (rss_hf == 0) /* Disable RSS */
6643 return i40e_hw_rss_hash_set(pf, rss_conf);
6647 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6648 struct rte_eth_rss_conf *rss_conf)
6650 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6651 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6654 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6655 &rss_conf->rss_key_len);
6657 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6658 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6659 rss_conf->rss_hf = i40e_parse_hena(hena);
6665 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6667 switch (filter_type) {
6668 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6669 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6671 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6672 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6674 case RTE_TUNNEL_FILTER_IMAC_TENID:
6675 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6677 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6678 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6680 case ETH_TUNNEL_FILTER_IMAC:
6681 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6683 case ETH_TUNNEL_FILTER_OIP:
6684 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6686 case ETH_TUNNEL_FILTER_IIP:
6687 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6690 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6697 /* Convert tunnel filter structure */
6699 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6701 struct i40e_tunnel_filter *tunnel_filter)
6703 ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6704 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6705 ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6706 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6707 tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6708 if ((rte_le_to_cpu_16(cld_filter->flags) &
6709 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6710 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6711 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6713 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6714 tunnel_filter->input.flags = cld_filter->flags;
6715 tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6716 tunnel_filter->queue = cld_filter->queue_number;
6721 /* Check if there exists the tunnel filter */
6722 struct i40e_tunnel_filter *
6723 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6724 const struct i40e_tunnel_filter_input *input)
6728 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6732 return tunnel_rule->hash_map[ret];
6735 /* Add a tunnel filter into the SW list */
6737 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6738 struct i40e_tunnel_filter *tunnel_filter)
6740 struct i40e_tunnel_rule *rule = &pf->tunnel;
6743 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6746 "Failed to insert tunnel filter to hash table %d!",
6750 rule->hash_map[ret] = tunnel_filter;
6752 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6757 /* Delete a tunnel filter from the SW list */
6759 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6760 struct i40e_tunnel_filter_input *input)
6762 struct i40e_tunnel_rule *rule = &pf->tunnel;
6763 struct i40e_tunnel_filter *tunnel_filter;
6766 ret = rte_hash_del_key(rule->hash_table, input);
6769 "Failed to delete tunnel filter to hash table %d!",
6773 tunnel_filter = rule->hash_map[ret];
6774 rule->hash_map[ret] = NULL;
6776 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6777 rte_free(tunnel_filter);
6783 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6784 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6789 uint8_t i, tun_type = 0;
6790 /* internal varialbe to convert ipv6 byte order */
6791 uint32_t convert_ipv6[4];
6793 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6794 struct i40e_vsi *vsi = pf->main_vsi;
6795 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6796 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6797 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6798 struct i40e_tunnel_filter *tunnel, *node;
6799 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6801 cld_filter = rte_zmalloc("tunnel_filter",
6802 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6805 if (NULL == cld_filter) {
6806 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6809 pfilter = cld_filter;
6811 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6812 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6814 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6815 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6816 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6817 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6818 rte_memcpy(&pfilter->ipaddr.v4.data,
6819 &rte_cpu_to_le_32(ipv4_addr),
6820 sizeof(pfilter->ipaddr.v4.data));
6822 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6823 for (i = 0; i < 4; i++) {
6825 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6827 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6828 sizeof(pfilter->ipaddr.v6.data));
6831 /* check tunneled type */
6832 switch (tunnel_filter->tunnel_type) {
6833 case RTE_TUNNEL_TYPE_VXLAN:
6834 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6836 case RTE_TUNNEL_TYPE_NVGRE:
6837 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6839 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6840 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6843 /* Other tunnel types is not supported. */
6844 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6845 rte_free(cld_filter);
6849 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6852 rte_free(cld_filter);
6856 pfilter->flags |= rte_cpu_to_le_16(
6857 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6858 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6859 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6860 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6862 /* Check if there is the filter in SW list */
6863 memset(&check_filter, 0, sizeof(check_filter));
6864 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6865 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6867 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6871 if (!add && !node) {
6872 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6877 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6879 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6882 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6883 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6884 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6886 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6889 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6892 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6895 rte_free(cld_filter);
6900 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6904 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6905 if (pf->vxlan_ports[i] == port)
6913 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6917 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6919 idx = i40e_get_vxlan_port_idx(pf, port);
6921 /* Check if port already exists */
6923 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6927 /* Now check if there is space to add the new port */
6928 idx = i40e_get_vxlan_port_idx(pf, 0);
6931 "Maximum number of UDP ports reached, not adding port %d",
6936 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6939 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6943 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6946 /* New port: add it and mark its index in the bitmap */
6947 pf->vxlan_ports[idx] = port;
6948 pf->vxlan_bitmap |= (1 << idx);
6950 if (!(pf->flags & I40E_FLAG_VXLAN))
6951 pf->flags |= I40E_FLAG_VXLAN;
6957 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6960 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6962 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6963 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6967 idx = i40e_get_vxlan_port_idx(pf, port);
6970 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6974 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6975 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6979 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6982 pf->vxlan_ports[idx] = 0;
6983 pf->vxlan_bitmap &= ~(1 << idx);
6985 if (!pf->vxlan_bitmap)
6986 pf->flags &= ~I40E_FLAG_VXLAN;
6991 /* Add UDP tunneling port */
6993 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6994 struct rte_eth_udp_tunnel *udp_tunnel)
6997 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6999 if (udp_tunnel == NULL)
7002 switch (udp_tunnel->prot_type) {
7003 case RTE_TUNNEL_TYPE_VXLAN:
7004 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7007 case RTE_TUNNEL_TYPE_GENEVE:
7008 case RTE_TUNNEL_TYPE_TEREDO:
7009 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7014 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7022 /* Remove UDP tunneling port */
7024 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7025 struct rte_eth_udp_tunnel *udp_tunnel)
7028 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7030 if (udp_tunnel == NULL)
7033 switch (udp_tunnel->prot_type) {
7034 case RTE_TUNNEL_TYPE_VXLAN:
7035 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7037 case RTE_TUNNEL_TYPE_GENEVE:
7038 case RTE_TUNNEL_TYPE_TEREDO:
7039 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7043 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7051 /* Calculate the maximum number of contiguous PF queues that are configured */
7053 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7055 struct rte_eth_dev_data *data = pf->dev_data;
7057 struct i40e_rx_queue *rxq;
7060 for (i = 0; i < pf->lan_nb_qps; i++) {
7061 rxq = data->rx_queues[i];
7062 if (rxq && rxq->q_set)
7073 i40e_pf_config_rss(struct i40e_pf *pf)
7075 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7076 struct rte_eth_rss_conf rss_conf;
7077 uint32_t i, lut = 0;
7081 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7082 * It's necessary to calulate the actual PF queues that are configured.
7084 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7085 num = i40e_pf_calc_configured_queues_num(pf);
7087 num = pf->dev_data->nb_rx_queues;
7089 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7090 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7094 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7098 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7101 lut = (lut << 8) | (j & ((0x1 <<
7102 hw->func_caps.rss_table_entry_width) - 1));
7104 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7107 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7108 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7109 i40e_pf_disable_rss(pf);
7112 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7113 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7114 /* Random default keys */
7115 static uint32_t rss_key_default[] = {0x6b793944,
7116 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7117 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7118 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7120 rss_conf.rss_key = (uint8_t *)rss_key_default;
7121 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7125 return i40e_hw_rss_hash_set(pf, &rss_conf);
7129 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7130 struct rte_eth_tunnel_filter_conf *filter)
7132 if (pf == NULL || filter == NULL) {
7133 PMD_DRV_LOG(ERR, "Invalid parameter");
7137 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7138 PMD_DRV_LOG(ERR, "Invalid queue ID");
7142 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7143 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7147 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7148 (is_zero_ether_addr(&filter->outer_mac))) {
7149 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7153 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7154 (is_zero_ether_addr(&filter->inner_mac))) {
7155 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7162 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7163 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7165 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7170 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7171 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7174 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7175 } else if (len == 4) {
7176 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7178 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7183 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7190 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7191 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7197 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7204 switch (cfg->cfg_type) {
7205 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7206 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7209 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7217 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7218 enum rte_filter_op filter_op,
7221 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7222 int ret = I40E_ERR_PARAM;
7224 switch (filter_op) {
7225 case RTE_ETH_FILTER_SET:
7226 ret = i40e_dev_global_config_set(hw,
7227 (struct rte_eth_global_cfg *)arg);
7230 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7238 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7239 enum rte_filter_op filter_op,
7242 struct rte_eth_tunnel_filter_conf *filter;
7243 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7244 int ret = I40E_SUCCESS;
7246 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7248 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7249 return I40E_ERR_PARAM;
7251 switch (filter_op) {
7252 case RTE_ETH_FILTER_NOP:
7253 if (!(pf->flags & I40E_FLAG_VXLAN))
7254 ret = I40E_NOT_SUPPORTED;
7256 case RTE_ETH_FILTER_ADD:
7257 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7259 case RTE_ETH_FILTER_DELETE:
7260 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7263 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7264 ret = I40E_ERR_PARAM;
7272 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7275 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7278 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7279 ret = i40e_pf_config_rss(pf);
7281 i40e_pf_disable_rss(pf);
7286 /* Get the symmetric hash enable configurations per port */
7288 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7290 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7292 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7295 /* Set the symmetric hash enable configurations per port */
7297 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7299 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7302 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7304 "Symmetric hash has already been enabled");
7307 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7309 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7311 "Symmetric hash has already been disabled");
7314 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7316 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7317 I40E_WRITE_FLUSH(hw);
7321 * Get global configurations of hash function type and symmetric hash enable
7322 * per flow type (pctype). Note that global configuration means it affects all
7323 * the ports on the same NIC.
7326 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7327 struct rte_eth_hash_global_conf *g_cfg)
7329 uint32_t reg, mask = I40E_FLOW_TYPES;
7331 enum i40e_filter_pctype pctype;
7333 memset(g_cfg, 0, sizeof(*g_cfg));
7334 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7335 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7336 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7338 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7339 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7340 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7342 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7343 if (!(mask & (1UL << i)))
7345 mask &= ~(1UL << i);
7346 /* Bit set indicats the coresponding flow type is supported */
7347 g_cfg->valid_bit_mask[0] |= (1UL << i);
7348 /* if flowtype is invalid, continue */
7349 if (!I40E_VALID_FLOW(i))
7351 pctype = i40e_flowtype_to_pctype(i);
7352 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7353 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7354 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7361 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7364 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7366 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7367 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7368 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7369 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7375 * As i40e supports less than 32 flow types, only first 32 bits need to
7378 mask0 = g_cfg->valid_bit_mask[0];
7379 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7381 /* Check if any unsupported flow type configured */
7382 if ((mask0 | i40e_mask) ^ i40e_mask)
7385 if (g_cfg->valid_bit_mask[i])
7393 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7399 * Set global configurations of hash function type and symmetric hash enable
7400 * per flow type (pctype). Note any modifying global configuration will affect
7401 * all the ports on the same NIC.
7404 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7405 struct rte_eth_hash_global_conf *g_cfg)
7410 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7411 enum i40e_filter_pctype pctype;
7413 /* Check the input parameters */
7414 ret = i40e_hash_global_config_check(g_cfg);
7418 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7419 if (!(mask0 & (1UL << i)))
7421 mask0 &= ~(1UL << i);
7422 /* if flowtype is invalid, continue */
7423 if (!I40E_VALID_FLOW(i))
7425 pctype = i40e_flowtype_to_pctype(i);
7426 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7427 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7428 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7431 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7432 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7434 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7436 "Hash function already set to Toeplitz");
7439 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7440 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7442 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7444 "Hash function already set to Simple XOR");
7447 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7449 /* Use the default, and keep it as it is */
7452 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7455 I40E_WRITE_FLUSH(hw);
7461 * Valid input sets for hash and flow director filters per PCTYPE
7464 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7465 enum rte_filter_type filter)
7469 static const uint64_t valid_hash_inset_table[] = {
7470 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7471 I40E_INSET_DMAC | I40E_INSET_SMAC |
7472 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7473 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7474 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7475 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7476 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7477 I40E_INSET_FLEX_PAYLOAD,
7478 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7479 I40E_INSET_DMAC | I40E_INSET_SMAC |
7480 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7481 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7482 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7483 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7484 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7485 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7486 I40E_INSET_FLEX_PAYLOAD,
7487 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7488 I40E_INSET_DMAC | I40E_INSET_SMAC |
7489 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7490 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7491 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7492 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7493 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7494 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7495 I40E_INSET_FLEX_PAYLOAD,
7496 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7497 I40E_INSET_DMAC | I40E_INSET_SMAC |
7498 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7499 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7500 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7501 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7502 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7503 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7504 I40E_INSET_FLEX_PAYLOAD,
7505 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7506 I40E_INSET_DMAC | I40E_INSET_SMAC |
7507 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7508 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7509 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7510 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7511 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7512 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7513 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7514 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7515 I40E_INSET_DMAC | I40E_INSET_SMAC |
7516 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7517 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7518 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7519 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7520 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7521 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7522 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7523 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7524 I40E_INSET_DMAC | I40E_INSET_SMAC |
7525 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7526 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7527 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7528 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7529 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7530 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7531 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7532 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7533 I40E_INSET_DMAC | I40E_INSET_SMAC |
7534 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7535 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7536 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7537 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7538 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7539 I40E_INSET_FLEX_PAYLOAD,
7540 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7541 I40E_INSET_DMAC | I40E_INSET_SMAC |
7542 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7543 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7544 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7545 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7546 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7547 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7548 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7549 I40E_INSET_DMAC | I40E_INSET_SMAC |
7550 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7551 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7552 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7553 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7554 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7555 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7556 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7557 I40E_INSET_DMAC | I40E_INSET_SMAC |
7558 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7559 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7560 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7561 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7562 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7563 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7564 I40E_INSET_FLEX_PAYLOAD,
7565 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7566 I40E_INSET_DMAC | I40E_INSET_SMAC |
7567 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7568 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7569 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7570 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7571 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7572 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7573 I40E_INSET_FLEX_PAYLOAD,
7574 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7575 I40E_INSET_DMAC | I40E_INSET_SMAC |
7576 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7577 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7578 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7579 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7580 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7581 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7582 I40E_INSET_FLEX_PAYLOAD,
7583 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7584 I40E_INSET_DMAC | I40E_INSET_SMAC |
7585 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7586 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7587 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7588 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7589 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7590 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7591 I40E_INSET_FLEX_PAYLOAD,
7592 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7593 I40E_INSET_DMAC | I40E_INSET_SMAC |
7594 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7595 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7596 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7597 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7598 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7599 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7600 I40E_INSET_FLEX_PAYLOAD,
7601 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7602 I40E_INSET_DMAC | I40E_INSET_SMAC |
7603 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7604 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7605 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7606 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7607 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7608 I40E_INSET_FLEX_PAYLOAD,
7609 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7610 I40E_INSET_DMAC | I40E_INSET_SMAC |
7611 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7612 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7613 I40E_INSET_FLEX_PAYLOAD,
7617 * Flow director supports only fields defined in
7618 * union rte_eth_fdir_flow.
7620 static const uint64_t valid_fdir_inset_table[] = {
7621 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7622 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7623 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7624 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7625 I40E_INSET_IPV4_TTL,
7626 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7627 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7628 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7629 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7630 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7631 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7632 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7633 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7634 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7635 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7636 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7637 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7638 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7639 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7640 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7641 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7642 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7643 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7644 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7645 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7646 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7647 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7648 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7649 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7650 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7651 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7652 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7653 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7654 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7655 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7657 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7658 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7659 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7660 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7661 I40E_INSET_IPV4_TTL,
7662 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7663 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7664 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7665 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7666 I40E_INSET_IPV6_HOP_LIMIT,
7667 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7668 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7669 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7670 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7671 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7672 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7673 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7674 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7675 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7676 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7677 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7678 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7679 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7680 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7681 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7682 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7683 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7684 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7685 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7686 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7687 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7688 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7689 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7690 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7691 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7692 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7693 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7694 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7695 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7696 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7698 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7699 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7700 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7701 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7702 I40E_INSET_IPV6_HOP_LIMIT,
7703 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7704 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7705 I40E_INSET_LAST_ETHER_TYPE,
7708 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7710 if (filter == RTE_ETH_FILTER_HASH)
7711 valid = valid_hash_inset_table[pctype];
7713 valid = valid_fdir_inset_table[pctype];
7719 * Validate if the input set is allowed for a specific PCTYPE
7722 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7723 enum rte_filter_type filter, uint64_t inset)
7727 valid = i40e_get_valid_input_set(pctype, filter);
7728 if (inset & (~valid))
7734 /* default input set fields combination per pctype */
7736 i40e_get_default_input_set(uint16_t pctype)
7738 static const uint64_t default_inset_table[] = {
7739 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7740 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7741 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7742 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7743 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7744 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7745 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7746 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7747 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7748 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7749 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7750 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7751 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7752 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7753 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7754 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7755 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7756 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7757 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7758 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7760 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7761 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7762 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7763 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7764 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7765 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7766 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7767 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7768 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7769 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7770 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7771 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7772 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7773 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7774 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7775 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7776 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7777 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7778 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7779 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7780 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7781 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7783 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7784 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7785 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7786 I40E_INSET_LAST_ETHER_TYPE,
7789 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7792 return default_inset_table[pctype];
7796 * Parse the input set from index to logical bit masks
7799 i40e_parse_input_set(uint64_t *inset,
7800 enum i40e_filter_pctype pctype,
7801 enum rte_eth_input_set_field *field,
7807 static const struct {
7808 enum rte_eth_input_set_field field;
7810 } inset_convert_table[] = {
7811 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7812 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7813 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7814 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7815 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7816 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7817 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7818 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7819 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7820 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7821 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7822 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7823 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7824 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7825 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7826 I40E_INSET_IPV6_NEXT_HDR},
7827 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7828 I40E_INSET_IPV6_HOP_LIMIT},
7829 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7830 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7831 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7832 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7833 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7834 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7835 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7836 I40E_INSET_SCTP_VT},
7837 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7838 I40E_INSET_TUNNEL_DMAC},
7839 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7840 I40E_INSET_VLAN_TUNNEL},
7841 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7842 I40E_INSET_TUNNEL_ID},
7843 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7844 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7845 I40E_INSET_FLEX_PAYLOAD_W1},
7846 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7847 I40E_INSET_FLEX_PAYLOAD_W2},
7848 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7849 I40E_INSET_FLEX_PAYLOAD_W3},
7850 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7851 I40E_INSET_FLEX_PAYLOAD_W4},
7852 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7853 I40E_INSET_FLEX_PAYLOAD_W5},
7854 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7855 I40E_INSET_FLEX_PAYLOAD_W6},
7856 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7857 I40E_INSET_FLEX_PAYLOAD_W7},
7858 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7859 I40E_INSET_FLEX_PAYLOAD_W8},
7862 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7865 /* Only one item allowed for default or all */
7867 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7868 *inset = i40e_get_default_input_set(pctype);
7870 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7871 *inset = I40E_INSET_NONE;
7876 for (i = 0, *inset = 0; i < size; i++) {
7877 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7878 if (field[i] == inset_convert_table[j].field) {
7879 *inset |= inset_convert_table[j].inset;
7884 /* It contains unsupported input set, return immediately */
7885 if (j == RTE_DIM(inset_convert_table))
7893 * Translate the input set from bit masks to register aware bit masks
7897 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7907 static const struct inset_map inset_map_common[] = {
7908 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7909 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7910 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7911 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7912 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7913 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7914 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7915 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7916 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7917 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7918 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7919 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7920 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7921 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7922 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7923 {I40E_INSET_TUNNEL_DMAC,
7924 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7925 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7926 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7927 {I40E_INSET_TUNNEL_SRC_PORT,
7928 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7929 {I40E_INSET_TUNNEL_DST_PORT,
7930 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7931 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7932 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7933 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7934 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7935 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7936 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7937 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7938 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7939 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7942 /* some different registers map in x722*/
7943 static const struct inset_map inset_map_diff_x722[] = {
7944 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7945 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7946 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7947 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7950 static const struct inset_map inset_map_diff_not_x722[] = {
7951 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7952 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7953 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7954 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7960 /* Translate input set to register aware inset */
7961 if (type == I40E_MAC_X722) {
7962 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7963 if (input & inset_map_diff_x722[i].inset)
7964 val |= inset_map_diff_x722[i].inset_reg;
7967 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7968 if (input & inset_map_diff_not_x722[i].inset)
7969 val |= inset_map_diff_not_x722[i].inset_reg;
7973 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7974 if (input & inset_map_common[i].inset)
7975 val |= inset_map_common[i].inset_reg;
7982 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7985 uint64_t inset_need_mask = inset;
7987 static const struct {
7990 } inset_mask_map[] = {
7991 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7992 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7993 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7994 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7995 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7996 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7997 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7998 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8001 if (!inset || !mask || !nb_elem)
8004 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8005 /* Clear the inset bit, if no MASK is required,
8006 * for example proto + ttl
8008 if ((inset & inset_mask_map[i].inset) ==
8009 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8010 inset_need_mask &= ~inset_mask_map[i].inset;
8011 if (!inset_need_mask)
8014 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8015 if ((inset_need_mask & inset_mask_map[i].inset) ==
8016 inset_mask_map[i].inset) {
8017 if (idx >= nb_elem) {
8018 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8021 mask[idx] = inset_mask_map[i].mask;
8030 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8032 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8034 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8036 i40e_write_rx_ctl(hw, addr, val);
8037 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8038 (uint32_t)i40e_read_rx_ctl(hw, addr));
8042 i40e_filter_input_set_init(struct i40e_pf *pf)
8044 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8045 enum i40e_filter_pctype pctype;
8046 uint64_t input_set, inset_reg;
8047 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8050 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8051 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8052 if (hw->mac.type == I40E_MAC_X722) {
8053 if (!I40E_VALID_PCTYPE_X722(pctype))
8056 if (!I40E_VALID_PCTYPE(pctype))
8060 input_set = i40e_get_default_input_set(pctype);
8062 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8063 I40E_INSET_MASK_NUM_REG);
8066 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8069 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8070 (uint32_t)(inset_reg & UINT32_MAX));
8071 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8072 (uint32_t)((inset_reg >>
8073 I40E_32_BIT_WIDTH) & UINT32_MAX));
8074 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8075 (uint32_t)(inset_reg & UINT32_MAX));
8076 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8077 (uint32_t)((inset_reg >>
8078 I40E_32_BIT_WIDTH) & UINT32_MAX));
8080 for (i = 0; i < num; i++) {
8081 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8083 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8086 /*clear unused mask registers of the pctype */
8087 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8088 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8090 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8093 I40E_WRITE_FLUSH(hw);
8095 /* store the default input set */
8096 pf->hash_input_set[pctype] = input_set;
8097 pf->fdir.input_set[pctype] = input_set;
8102 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8103 struct rte_eth_input_set_conf *conf)
8105 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8106 enum i40e_filter_pctype pctype;
8107 uint64_t input_set, inset_reg = 0;
8108 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8112 PMD_DRV_LOG(ERR, "Invalid pointer");
8115 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8116 conf->op != RTE_ETH_INPUT_SET_ADD) {
8117 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8121 if (!I40E_VALID_FLOW(conf->flow_type)) {
8122 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8126 if (hw->mac.type == I40E_MAC_X722) {
8127 /* get translated pctype value in fd pctype register */
8128 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8129 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8132 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8134 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8137 PMD_DRV_LOG(ERR, "Failed to parse input set");
8140 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8142 PMD_DRV_LOG(ERR, "Invalid input set");
8145 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8146 /* get inset value in register */
8147 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8148 inset_reg <<= I40E_32_BIT_WIDTH;
8149 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8150 input_set |= pf->hash_input_set[pctype];
8152 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8153 I40E_INSET_MASK_NUM_REG);
8157 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8159 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8160 (uint32_t)(inset_reg & UINT32_MAX));
8161 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8162 (uint32_t)((inset_reg >>
8163 I40E_32_BIT_WIDTH) & UINT32_MAX));
8165 for (i = 0; i < num; i++)
8166 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8168 /*clear unused mask registers of the pctype */
8169 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8170 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8172 I40E_WRITE_FLUSH(hw);
8174 pf->hash_input_set[pctype] = input_set;
8179 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8180 struct rte_eth_input_set_conf *conf)
8182 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8183 enum i40e_filter_pctype pctype;
8184 uint64_t input_set, inset_reg = 0;
8185 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8189 PMD_DRV_LOG(ERR, "Invalid pointer");
8192 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8193 conf->op != RTE_ETH_INPUT_SET_ADD) {
8194 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8198 if (!I40E_VALID_FLOW(conf->flow_type)) {
8199 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8203 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8205 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8208 PMD_DRV_LOG(ERR, "Failed to parse input set");
8211 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8213 PMD_DRV_LOG(ERR, "Invalid input set");
8217 /* get inset value in register */
8218 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8219 inset_reg <<= I40E_32_BIT_WIDTH;
8220 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8222 /* Can not change the inset reg for flex payload for fdir,
8223 * it is done by writing I40E_PRTQF_FD_FLXINSET
8224 * in i40e_set_flex_mask_on_pctype.
8226 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8227 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8229 input_set |= pf->fdir.input_set[pctype];
8230 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8231 I40E_INSET_MASK_NUM_REG);
8235 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8237 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8238 (uint32_t)(inset_reg & UINT32_MAX));
8239 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8240 (uint32_t)((inset_reg >>
8241 I40E_32_BIT_WIDTH) & UINT32_MAX));
8243 for (i = 0; i < num; i++)
8244 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8246 /*clear unused mask registers of the pctype */
8247 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8248 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8250 I40E_WRITE_FLUSH(hw);
8252 pf->fdir.input_set[pctype] = input_set;
8257 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8262 PMD_DRV_LOG(ERR, "Invalid pointer");
8266 switch (info->info_type) {
8267 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8268 i40e_get_symmetric_hash_enable_per_port(hw,
8269 &(info->info.enable));
8271 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8272 ret = i40e_get_hash_filter_global_config(hw,
8273 &(info->info.global_conf));
8276 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8286 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8291 PMD_DRV_LOG(ERR, "Invalid pointer");
8295 switch (info->info_type) {
8296 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8297 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8299 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8300 ret = i40e_set_hash_filter_global_config(hw,
8301 &(info->info.global_conf));
8303 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8304 ret = i40e_hash_filter_inset_select(hw,
8305 &(info->info.input_set_conf));
8309 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8318 /* Operations for hash function */
8320 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8321 enum rte_filter_op filter_op,
8324 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8327 switch (filter_op) {
8328 case RTE_ETH_FILTER_NOP:
8330 case RTE_ETH_FILTER_GET:
8331 ret = i40e_hash_filter_get(hw,
8332 (struct rte_eth_hash_filter_info *)arg);
8334 case RTE_ETH_FILTER_SET:
8335 ret = i40e_hash_filter_set(hw,
8336 (struct rte_eth_hash_filter_info *)arg);
8339 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8348 /* Convert ethertype filter structure */
8350 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8351 struct i40e_ethertype_filter *filter)
8353 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8354 filter->input.ether_type = input->ether_type;
8355 filter->flags = input->flags;
8356 filter->queue = input->queue;
8361 /* Check if there exists the ehtertype filter */
8362 struct i40e_ethertype_filter *
8363 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8364 const struct i40e_ethertype_filter_input *input)
8368 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8372 return ethertype_rule->hash_map[ret];
8375 /* Add ethertype filter in SW list */
8377 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8378 struct i40e_ethertype_filter *filter)
8380 struct i40e_ethertype_rule *rule = &pf->ethertype;
8383 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8386 "Failed to insert ethertype filter"
8387 " to hash table %d!",
8391 rule->hash_map[ret] = filter;
8393 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8398 /* Delete ethertype filter in SW list */
8400 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8401 struct i40e_ethertype_filter_input *input)
8403 struct i40e_ethertype_rule *rule = &pf->ethertype;
8404 struct i40e_ethertype_filter *filter;
8407 ret = rte_hash_del_key(rule->hash_table, input);
8410 "Failed to delete ethertype filter"
8411 " to hash table %d!",
8415 filter = rule->hash_map[ret];
8416 rule->hash_map[ret] = NULL;
8418 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8425 * Configure ethertype filter, which can director packet by filtering
8426 * with mac address and ether_type or only ether_type
8429 i40e_ethertype_filter_set(struct i40e_pf *pf,
8430 struct rte_eth_ethertype_filter *filter,
8433 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8434 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8435 struct i40e_ethertype_filter *ethertype_filter, *node;
8436 struct i40e_ethertype_filter check_filter;
8437 struct i40e_control_filter_stats stats;
8441 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8442 PMD_DRV_LOG(ERR, "Invalid queue ID");
8445 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8446 filter->ether_type == ETHER_TYPE_IPv6) {
8448 "unsupported ether_type(0x%04x) in control packet filter.",
8449 filter->ether_type);
8452 if (filter->ether_type == ETHER_TYPE_VLAN)
8453 PMD_DRV_LOG(WARNING,
8454 "filter vlan ether_type in first tag is not supported.");
8456 /* Check if there is the filter in SW list */
8457 memset(&check_filter, 0, sizeof(check_filter));
8458 i40e_ethertype_filter_convert(filter, &check_filter);
8459 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8460 &check_filter.input);
8462 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8466 if (!add && !node) {
8467 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8471 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8472 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8473 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8474 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8475 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8477 memset(&stats, 0, sizeof(stats));
8478 ret = i40e_aq_add_rem_control_packet_filter(hw,
8479 filter->mac_addr.addr_bytes,
8480 filter->ether_type, flags,
8482 filter->queue, add, &stats, NULL);
8485 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8486 ret, stats.mac_etype_used, stats.etype_used,
8487 stats.mac_etype_free, stats.etype_free);
8491 /* Add or delete a filter in SW list */
8493 ethertype_filter = rte_zmalloc("ethertype_filter",
8494 sizeof(*ethertype_filter), 0);
8495 rte_memcpy(ethertype_filter, &check_filter,
8496 sizeof(check_filter));
8497 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8499 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8506 * Handle operations for ethertype filter.
8509 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8510 enum rte_filter_op filter_op,
8513 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8516 if (filter_op == RTE_ETH_FILTER_NOP)
8520 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8525 switch (filter_op) {
8526 case RTE_ETH_FILTER_ADD:
8527 ret = i40e_ethertype_filter_set(pf,
8528 (struct rte_eth_ethertype_filter *)arg,
8531 case RTE_ETH_FILTER_DELETE:
8532 ret = i40e_ethertype_filter_set(pf,
8533 (struct rte_eth_ethertype_filter *)arg,
8537 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8545 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8546 enum rte_filter_type filter_type,
8547 enum rte_filter_op filter_op,
8555 switch (filter_type) {
8556 case RTE_ETH_FILTER_NONE:
8557 /* For global configuration */
8558 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8560 case RTE_ETH_FILTER_HASH:
8561 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8563 case RTE_ETH_FILTER_MACVLAN:
8564 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8566 case RTE_ETH_FILTER_ETHERTYPE:
8567 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8569 case RTE_ETH_FILTER_TUNNEL:
8570 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8572 case RTE_ETH_FILTER_FDIR:
8573 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8575 case RTE_ETH_FILTER_GENERIC:
8576 if (filter_op != RTE_ETH_FILTER_GET)
8578 *(const void **)arg = &i40e_flow_ops;
8581 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8591 * Check and enable Extended Tag.
8592 * Enabling Extended Tag is important for 40G performance.
8595 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8597 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8601 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8604 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8608 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8609 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8614 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8617 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8621 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8622 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8625 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8626 ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8629 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8636 * As some registers wouldn't be reset unless a global hardware reset,
8637 * hardware initialization is needed to put those registers into an
8638 * expected initial state.
8641 i40e_hw_init(struct rte_eth_dev *dev)
8643 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8645 i40e_enable_extended_tag(dev);
8647 /* clear the PF Queue Filter control register */
8648 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8650 /* Disable symmetric hash per port */
8651 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8654 enum i40e_filter_pctype
8655 i40e_flowtype_to_pctype(uint16_t flow_type)
8657 static const enum i40e_filter_pctype pctype_table[] = {
8658 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8659 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8660 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8661 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8662 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8663 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8664 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8665 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8666 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8667 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8668 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8669 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8670 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8671 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8672 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8673 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8674 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8675 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8676 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8679 return pctype_table[flow_type];
8683 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8685 static const uint16_t flowtype_table[] = {
8686 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8687 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8688 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8689 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8690 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8691 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8692 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8693 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8694 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8695 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8696 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8697 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8698 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8699 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8700 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8701 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8702 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8703 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8704 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8705 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8706 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8707 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8708 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8709 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8710 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8711 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8712 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8713 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8714 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8715 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8716 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8719 return flowtype_table[pctype];
8723 * On X710, performance number is far from the expectation on recent firmware
8724 * versions; on XL710, performance number is also far from the expectation on
8725 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8726 * mode is enabled and port MAC address is equal to the packet destination MAC
8727 * address. The fix for this issue may not be integrated in the following
8728 * firmware version. So the workaround in software driver is needed. It needs
8729 * to modify the initial values of 3 internal only registers for both X710 and
8730 * XL710. Note that the values for X710 or XL710 could be different, and the
8731 * workaround can be removed when it is fixed in firmware in the future.
8734 /* For both X710 and XL710 */
8735 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8736 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
8738 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8739 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
8742 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8743 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8746 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
8748 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
8749 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
8752 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8754 enum i40e_status_code status;
8755 struct i40e_aq_get_phy_abilities_resp phy_ab;
8758 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8768 i40e_configure_registers(struct i40e_hw *hw)
8774 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8775 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8776 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8782 for (i = 0; i < RTE_DIM(reg_table); i++) {
8783 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8784 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8786 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8787 else /* For X710/XL710/XXV710 */
8789 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8792 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8793 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8795 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8796 else /* For X710/XL710/XXV710 */
8798 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8801 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8802 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8803 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8805 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8808 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8811 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8814 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8818 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8819 reg_table[i].addr, reg);
8820 if (reg == reg_table[i].val)
8823 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8824 reg_table[i].val, NULL);
8827 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
8828 reg_table[i].val, reg_table[i].addr);
8831 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8832 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8836 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
8837 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
8838 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
8839 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8841 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8846 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8847 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8851 /* Configure for double VLAN RX stripping */
8852 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8853 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8854 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8855 ret = i40e_aq_debug_write_register(hw,
8856 I40E_VSI_TSR(vsi->vsi_id),
8859 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8861 return I40E_ERR_CONFIG;
8865 /* Configure for double VLAN TX insertion */
8866 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8867 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8868 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8869 ret = i40e_aq_debug_write_register(hw,
8870 I40E_VSI_L2TAGSTXVALID(
8871 vsi->vsi_id), reg, NULL);
8874 "Failed to update VSI_L2TAGSTXVALID[%d]",
8876 return I40E_ERR_CONFIG;
8884 * i40e_aq_add_mirror_rule
8885 * @hw: pointer to the hardware structure
8886 * @seid: VEB seid to add mirror rule to
8887 * @dst_id: destination vsi seid
8888 * @entries: Buffer which contains the entities to be mirrored
8889 * @count: number of entities contained in the buffer
8890 * @rule_id:the rule_id of the rule to be added
8892 * Add a mirror rule for a given veb.
8895 static enum i40e_status_code
8896 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8897 uint16_t seid, uint16_t dst_id,
8898 uint16_t rule_type, uint16_t *entries,
8899 uint16_t count, uint16_t *rule_id)
8901 struct i40e_aq_desc desc;
8902 struct i40e_aqc_add_delete_mirror_rule cmd;
8903 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8904 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8907 enum i40e_status_code status;
8909 i40e_fill_default_direct_cmd_desc(&desc,
8910 i40e_aqc_opc_add_mirror_rule);
8911 memset(&cmd, 0, sizeof(cmd));
8913 buff_len = sizeof(uint16_t) * count;
8914 desc.datalen = rte_cpu_to_le_16(buff_len);
8916 desc.flags |= rte_cpu_to_le_16(
8917 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8918 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8919 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8920 cmd.num_entries = rte_cpu_to_le_16(count);
8921 cmd.seid = rte_cpu_to_le_16(seid);
8922 cmd.destination = rte_cpu_to_le_16(dst_id);
8924 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8925 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8927 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
8928 hw->aq.asq_last_status, resp->rule_id,
8929 resp->mirror_rules_used, resp->mirror_rules_free);
8930 *rule_id = rte_le_to_cpu_16(resp->rule_id);
8936 * i40e_aq_del_mirror_rule
8937 * @hw: pointer to the hardware structure
8938 * @seid: VEB seid to add mirror rule to
8939 * @entries: Buffer which contains the entities to be mirrored
8940 * @count: number of entities contained in the buffer
8941 * @rule_id:the rule_id of the rule to be delete
8943 * Delete a mirror rule for a given veb.
8946 static enum i40e_status_code
8947 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8948 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8949 uint16_t count, uint16_t rule_id)
8951 struct i40e_aq_desc desc;
8952 struct i40e_aqc_add_delete_mirror_rule cmd;
8953 uint16_t buff_len = 0;
8954 enum i40e_status_code status;
8957 i40e_fill_default_direct_cmd_desc(&desc,
8958 i40e_aqc_opc_delete_mirror_rule);
8959 memset(&cmd, 0, sizeof(cmd));
8960 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8961 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8963 cmd.num_entries = count;
8964 buff_len = sizeof(uint16_t) * count;
8965 desc.datalen = rte_cpu_to_le_16(buff_len);
8966 buff = (void *)entries;
8968 /* rule id is filled in destination field for deleting mirror rule */
8969 cmd.destination = rte_cpu_to_le_16(rule_id);
8971 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8972 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8973 cmd.seid = rte_cpu_to_le_16(seid);
8975 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8976 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8982 * i40e_mirror_rule_set
8983 * @dev: pointer to the hardware structure
8984 * @mirror_conf: mirror rule info
8985 * @sw_id: mirror rule's sw_id
8986 * @on: enable/disable
8988 * set a mirror rule.
8992 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8993 struct rte_eth_mirror_conf *mirror_conf,
8994 uint8_t sw_id, uint8_t on)
8996 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8997 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8998 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8999 struct i40e_mirror_rule *parent = NULL;
9000 uint16_t seid, dst_seid, rule_id;
9004 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9006 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9008 "mirror rule can not be configured without veb or vfs.");
9011 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9012 PMD_DRV_LOG(ERR, "mirror table is full.");
9015 if (mirror_conf->dst_pool > pf->vf_num) {
9016 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9017 mirror_conf->dst_pool);
9021 seid = pf->main_vsi->veb->seid;
9023 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9024 if (sw_id <= it->index) {
9030 if (mirr_rule && sw_id == mirr_rule->index) {
9032 PMD_DRV_LOG(ERR, "mirror rule exists.");
9035 ret = i40e_aq_del_mirror_rule(hw, seid,
9036 mirr_rule->rule_type,
9038 mirr_rule->num_entries, mirr_rule->id);
9041 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9042 ret, hw->aq.asq_last_status);
9045 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9046 rte_free(mirr_rule);
9047 pf->nb_mirror_rule--;
9051 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9055 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9056 sizeof(struct i40e_mirror_rule) , 0);
9058 PMD_DRV_LOG(ERR, "failed to allocate memory");
9059 return I40E_ERR_NO_MEMORY;
9061 switch (mirror_conf->rule_type) {
9062 case ETH_MIRROR_VLAN:
9063 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9064 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9065 mirr_rule->entries[j] =
9066 mirror_conf->vlan.vlan_id[i];
9071 PMD_DRV_LOG(ERR, "vlan is not specified.");
9072 rte_free(mirr_rule);
9075 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9077 case ETH_MIRROR_VIRTUAL_POOL_UP:
9078 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9079 /* check if the specified pool bit is out of range */
9080 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9081 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9082 rte_free(mirr_rule);
9085 for (i = 0, j = 0; i < pf->vf_num; i++) {
9086 if (mirror_conf->pool_mask & (1ULL << i)) {
9087 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9091 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9092 /* add pf vsi to entries */
9093 mirr_rule->entries[j] = pf->main_vsi_seid;
9097 PMD_DRV_LOG(ERR, "pool is not specified.");
9098 rte_free(mirr_rule);
9101 /* egress and ingress in aq commands means from switch but not port */
9102 mirr_rule->rule_type =
9103 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9104 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9105 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9107 case ETH_MIRROR_UPLINK_PORT:
9108 /* egress and ingress in aq commands means from switch but not port*/
9109 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9111 case ETH_MIRROR_DOWNLINK_PORT:
9112 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9115 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9116 mirror_conf->rule_type);
9117 rte_free(mirr_rule);
9121 /* If the dst_pool is equal to vf_num, consider it as PF */
9122 if (mirror_conf->dst_pool == pf->vf_num)
9123 dst_seid = pf->main_vsi_seid;
9125 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9127 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9128 mirr_rule->rule_type, mirr_rule->entries,
9132 "failed to add mirror rule: ret = %d, aq_err = %d.",
9133 ret, hw->aq.asq_last_status);
9134 rte_free(mirr_rule);
9138 mirr_rule->index = sw_id;
9139 mirr_rule->num_entries = j;
9140 mirr_rule->id = rule_id;
9141 mirr_rule->dst_vsi_seid = dst_seid;
9144 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9146 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9148 pf->nb_mirror_rule++;
9153 * i40e_mirror_rule_reset
9154 * @dev: pointer to the device
9155 * @sw_id: mirror rule's sw_id
9157 * reset a mirror rule.
9161 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9163 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9164 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9165 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9169 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9171 seid = pf->main_vsi->veb->seid;
9173 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9174 if (sw_id == it->index) {
9180 ret = i40e_aq_del_mirror_rule(hw, seid,
9181 mirr_rule->rule_type,
9183 mirr_rule->num_entries, mirr_rule->id);
9186 "failed to remove mirror rule: status = %d, aq_err = %d.",
9187 ret, hw->aq.asq_last_status);
9190 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9191 rte_free(mirr_rule);
9192 pf->nb_mirror_rule--;
9194 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9201 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9203 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9204 uint64_t systim_cycles;
9206 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9207 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9210 return systim_cycles;
9214 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9216 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9219 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9220 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9227 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9229 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9232 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9233 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9240 i40e_start_timecounters(struct rte_eth_dev *dev)
9242 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9243 struct i40e_adapter *adapter =
9244 (struct i40e_adapter *)dev->data->dev_private;
9245 struct rte_eth_link link;
9246 uint32_t tsync_inc_l;
9247 uint32_t tsync_inc_h;
9249 /* Get current link speed. */
9250 memset(&link, 0, sizeof(link));
9251 i40e_dev_link_update(dev, 1);
9252 rte_i40e_dev_atomic_read_link_status(dev, &link);
9254 switch (link.link_speed) {
9255 case ETH_SPEED_NUM_40G:
9256 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9257 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9259 case ETH_SPEED_NUM_10G:
9260 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9261 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9263 case ETH_SPEED_NUM_1G:
9264 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9265 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9272 /* Set the timesync increment value. */
9273 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9274 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9276 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9277 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9278 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9280 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9281 adapter->systime_tc.cc_shift = 0;
9282 adapter->systime_tc.nsec_mask = 0;
9284 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9285 adapter->rx_tstamp_tc.cc_shift = 0;
9286 adapter->rx_tstamp_tc.nsec_mask = 0;
9288 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9289 adapter->tx_tstamp_tc.cc_shift = 0;
9290 adapter->tx_tstamp_tc.nsec_mask = 0;
9294 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9296 struct i40e_adapter *adapter =
9297 (struct i40e_adapter *)dev->data->dev_private;
9299 adapter->systime_tc.nsec += delta;
9300 adapter->rx_tstamp_tc.nsec += delta;
9301 adapter->tx_tstamp_tc.nsec += delta;
9307 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9310 struct i40e_adapter *adapter =
9311 (struct i40e_adapter *)dev->data->dev_private;
9313 ns = rte_timespec_to_ns(ts);
9315 /* Set the timecounters to a new value. */
9316 adapter->systime_tc.nsec = ns;
9317 adapter->rx_tstamp_tc.nsec = ns;
9318 adapter->tx_tstamp_tc.nsec = ns;
9324 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9326 uint64_t ns, systime_cycles;
9327 struct i40e_adapter *adapter =
9328 (struct i40e_adapter *)dev->data->dev_private;
9330 systime_cycles = i40e_read_systime_cyclecounter(dev);
9331 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9332 *ts = rte_ns_to_timespec(ns);
9338 i40e_timesync_enable(struct rte_eth_dev *dev)
9340 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9341 uint32_t tsync_ctl_l;
9342 uint32_t tsync_ctl_h;
9344 /* Stop the timesync system time. */
9345 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9346 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9347 /* Reset the timesync system time value. */
9348 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9349 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9351 i40e_start_timecounters(dev);
9353 /* Clear timesync registers. */
9354 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9355 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9356 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9357 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9358 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9359 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9361 /* Enable timestamping of PTP packets. */
9362 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9363 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9365 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9366 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9367 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9369 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9370 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9376 i40e_timesync_disable(struct rte_eth_dev *dev)
9378 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9379 uint32_t tsync_ctl_l;
9380 uint32_t tsync_ctl_h;
9382 /* Disable timestamping of transmitted PTP packets. */
9383 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9384 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9386 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9387 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9389 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9390 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9392 /* Reset the timesync increment value. */
9393 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9394 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9400 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9401 struct timespec *timestamp, uint32_t flags)
9403 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9404 struct i40e_adapter *adapter =
9405 (struct i40e_adapter *)dev->data->dev_private;
9407 uint32_t sync_status;
9408 uint32_t index = flags & 0x03;
9409 uint64_t rx_tstamp_cycles;
9412 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9413 if ((sync_status & (1 << index)) == 0)
9416 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9417 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9418 *timestamp = rte_ns_to_timespec(ns);
9424 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9425 struct timespec *timestamp)
9427 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9428 struct i40e_adapter *adapter =
9429 (struct i40e_adapter *)dev->data->dev_private;
9431 uint32_t sync_status;
9432 uint64_t tx_tstamp_cycles;
9435 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9436 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9439 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9440 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9441 *timestamp = rte_ns_to_timespec(ns);
9447 * i40e_parse_dcb_configure - parse dcb configure from user
9448 * @dev: the device being configured
9449 * @dcb_cfg: pointer of the result of parse
9450 * @*tc_map: bit map of enabled traffic classes
9452 * Returns 0 on success, negative value on failure
9455 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9456 struct i40e_dcbx_config *dcb_cfg,
9459 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9460 uint8_t i, tc_bw, bw_lf;
9462 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9464 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9465 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9466 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9470 /* assume each tc has the same bw */
9471 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9472 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9473 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9474 /* to ensure the sum of tcbw is equal to 100 */
9475 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9476 for (i = 0; i < bw_lf; i++)
9477 dcb_cfg->etscfg.tcbwtable[i]++;
9479 /* assume each tc has the same Transmission Selection Algorithm */
9480 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9481 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9483 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9484 dcb_cfg->etscfg.prioritytable[i] =
9485 dcb_rx_conf->dcb_tc[i];
9487 /* FW needs one App to configure HW */
9488 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9489 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9490 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9491 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9493 if (dcb_rx_conf->nb_tcs == 0)
9494 *tc_map = 1; /* tc0 only */
9496 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9498 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9499 dcb_cfg->pfc.willing = 0;
9500 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9501 dcb_cfg->pfc.pfcenable = *tc_map;
9507 static enum i40e_status_code
9508 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9509 struct i40e_aqc_vsi_properties_data *info,
9510 uint8_t enabled_tcmap)
9512 enum i40e_status_code ret;
9513 int i, total_tc = 0;
9514 uint16_t qpnum_per_tc, bsf, qp_idx;
9515 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9516 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9517 uint16_t used_queues;
9519 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9520 if (ret != I40E_SUCCESS)
9523 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9524 if (enabled_tcmap & (1 << i))
9529 vsi->enabled_tc = enabled_tcmap;
9531 /* different VSI has different queues assigned */
9532 if (vsi->type == I40E_VSI_MAIN)
9533 used_queues = dev_data->nb_rx_queues -
9534 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9535 else if (vsi->type == I40E_VSI_VMDQ2)
9536 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9538 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9539 return I40E_ERR_NO_AVAILABLE_VSI;
9542 qpnum_per_tc = used_queues / total_tc;
9543 /* Number of queues per enabled TC */
9544 if (qpnum_per_tc == 0) {
9545 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9546 return I40E_ERR_INVALID_QP_ID;
9548 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9550 bsf = rte_bsf32(qpnum_per_tc);
9553 * Configure TC and queue mapping parameters, for enabled TC,
9554 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9555 * default queue will serve it.
9558 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9559 if (vsi->enabled_tc & (1 << i)) {
9560 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9561 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9562 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9563 qp_idx += qpnum_per_tc;
9565 info->tc_mapping[i] = 0;
9568 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9569 if (vsi->type == I40E_VSI_SRIOV) {
9570 info->mapping_flags |=
9571 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9572 for (i = 0; i < vsi->nb_qps; i++)
9573 info->queue_mapping[i] =
9574 rte_cpu_to_le_16(vsi->base_queue + i);
9576 info->mapping_flags |=
9577 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9578 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9580 info->valid_sections |=
9581 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9583 return I40E_SUCCESS;
9587 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9588 * @veb: VEB to be configured
9589 * @tc_map: enabled TC bitmap
9591 * Returns 0 on success, negative value on failure
9593 static enum i40e_status_code
9594 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9596 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9597 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9598 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9599 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9600 enum i40e_status_code ret = I40E_SUCCESS;
9604 /* Check if enabled_tc is same as existing or new TCs */
9605 if (veb->enabled_tc == tc_map)
9608 /* configure tc bandwidth */
9609 memset(&veb_bw, 0, sizeof(veb_bw));
9610 veb_bw.tc_valid_bits = tc_map;
9611 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9612 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9613 if (tc_map & BIT_ULL(i))
9614 veb_bw.tc_bw_share_credits[i] = 1;
9616 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9620 "AQ command Config switch_comp BW allocation per TC failed = %d",
9621 hw->aq.asq_last_status);
9625 memset(&ets_query, 0, sizeof(ets_query));
9626 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9628 if (ret != I40E_SUCCESS) {
9630 "Failed to get switch_comp ETS configuration %u",
9631 hw->aq.asq_last_status);
9634 memset(&bw_query, 0, sizeof(bw_query));
9635 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9637 if (ret != I40E_SUCCESS) {
9639 "Failed to get switch_comp bandwidth configuration %u",
9640 hw->aq.asq_last_status);
9644 /* store and print out BW info */
9645 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9646 veb->bw_info.bw_max = ets_query.tc_bw_max;
9647 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9648 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9649 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9650 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9652 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9653 veb->bw_info.bw_ets_share_credits[i] =
9654 bw_query.tc_bw_share_credits[i];
9655 veb->bw_info.bw_ets_credits[i] =
9656 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9657 /* 4 bits per TC, 4th bit is reserved */
9658 veb->bw_info.bw_ets_max[i] =
9659 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9660 RTE_LEN2MASK(3, uint8_t));
9661 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9662 veb->bw_info.bw_ets_share_credits[i]);
9663 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9664 veb->bw_info.bw_ets_credits[i]);
9665 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9666 veb->bw_info.bw_ets_max[i]);
9669 veb->enabled_tc = tc_map;
9676 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9677 * @vsi: VSI to be configured
9678 * @tc_map: enabled TC bitmap
9680 * Returns 0 on success, negative value on failure
9682 static enum i40e_status_code
9683 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9685 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9686 struct i40e_vsi_context ctxt;
9687 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9688 enum i40e_status_code ret = I40E_SUCCESS;
9691 /* Check if enabled_tc is same as existing or new TCs */
9692 if (vsi->enabled_tc == tc_map)
9695 /* configure tc bandwidth */
9696 memset(&bw_data, 0, sizeof(bw_data));
9697 bw_data.tc_valid_bits = tc_map;
9698 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9699 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9700 if (tc_map & BIT_ULL(i))
9701 bw_data.tc_bw_credits[i] = 1;
9703 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9706 "AQ command Config VSI BW allocation per TC failed = %d",
9707 hw->aq.asq_last_status);
9710 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9711 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9713 /* Update Queue Pairs Mapping for currently enabled UPs */
9714 ctxt.seid = vsi->seid;
9715 ctxt.pf_num = hw->pf_id;
9717 ctxt.uplink_seid = vsi->uplink_seid;
9718 ctxt.info = vsi->info;
9720 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9724 /* Update the VSI after updating the VSI queue-mapping information */
9725 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9727 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
9728 hw->aq.asq_last_status);
9731 /* update the local VSI info with updated queue map */
9732 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9733 sizeof(vsi->info.tc_mapping));
9734 (void)rte_memcpy(&vsi->info.queue_mapping,
9735 &ctxt.info.queue_mapping,
9736 sizeof(vsi->info.queue_mapping));
9737 vsi->info.mapping_flags = ctxt.info.mapping_flags;
9738 vsi->info.valid_sections = 0;
9740 /* query and update current VSI BW information */
9741 ret = i40e_vsi_get_bw_config(vsi);
9744 "Failed updating vsi bw info, err %s aq_err %s",
9745 i40e_stat_str(hw, ret),
9746 i40e_aq_str(hw, hw->aq.asq_last_status));
9750 vsi->enabled_tc = tc_map;
9757 * i40e_dcb_hw_configure - program the dcb setting to hw
9758 * @pf: pf the configuration is taken on
9759 * @new_cfg: new configuration
9760 * @tc_map: enabled TC bitmap
9762 * Returns 0 on success, negative value on failure
9764 static enum i40e_status_code
9765 i40e_dcb_hw_configure(struct i40e_pf *pf,
9766 struct i40e_dcbx_config *new_cfg,
9769 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9770 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9771 struct i40e_vsi *main_vsi = pf->main_vsi;
9772 struct i40e_vsi_list *vsi_list;
9773 enum i40e_status_code ret;
9777 /* Use the FW API if FW > v4.4*/
9778 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9779 (hw->aq.fw_maj_ver >= 5))) {
9781 "FW < v4.4, can not use FW LLDP API to configure DCB");
9782 return I40E_ERR_FIRMWARE_API_VERSION;
9785 /* Check if need reconfiguration */
9786 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9787 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9788 return I40E_SUCCESS;
9791 /* Copy the new config to the current config */
9792 *old_cfg = *new_cfg;
9793 old_cfg->etsrec = old_cfg->etscfg;
9794 ret = i40e_set_dcb_config(hw);
9796 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
9797 i40e_stat_str(hw, ret),
9798 i40e_aq_str(hw, hw->aq.asq_last_status));
9801 /* set receive Arbiter to RR mode and ETS scheme by default */
9802 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9803 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9804 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
9805 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9806 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9807 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9808 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9809 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9810 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9811 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9812 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9813 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9814 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9816 /* get local mib to check whether it is configured correctly */
9818 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9819 /* Get Local DCB Config */
9820 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9821 &hw->local_dcbx_config);
9823 /* if Veb is created, need to update TC of it at first */
9824 if (main_vsi->veb) {
9825 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9827 PMD_INIT_LOG(WARNING,
9828 "Failed configuring TC for VEB seid=%d",
9829 main_vsi->veb->seid);
9831 /* Update each VSI */
9832 i40e_vsi_config_tc(main_vsi, tc_map);
9833 if (main_vsi->veb) {
9834 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9835 /* Beside main VSI and VMDQ VSIs, only enable default
9838 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9839 ret = i40e_vsi_config_tc(vsi_list->vsi,
9842 ret = i40e_vsi_config_tc(vsi_list->vsi,
9843 I40E_DEFAULT_TCMAP);
9845 PMD_INIT_LOG(WARNING,
9846 "Failed configuring TC for VSI seid=%d",
9847 vsi_list->vsi->seid);
9851 return I40E_SUCCESS;
9855 * i40e_dcb_init_configure - initial dcb config
9856 * @dev: device being configured
9857 * @sw_dcb: indicate whether dcb is sw configured or hw offload
9859 * Returns 0 on success, negative value on failure
9862 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9864 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9865 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9868 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9869 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9873 /* DCB initialization:
9874 * Update DCB configuration from the Firmware and configure
9875 * LLDP MIB change event.
9877 if (sw_dcb == TRUE) {
9878 ret = i40e_init_dcb(hw);
9879 /* If lldp agent is stopped, the return value from
9880 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9881 * adminq status. Otherwise, it should return success.
9883 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9884 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9885 memset(&hw->local_dcbx_config, 0,
9886 sizeof(struct i40e_dcbx_config));
9887 /* set dcb default configuration */
9888 hw->local_dcbx_config.etscfg.willing = 0;
9889 hw->local_dcbx_config.etscfg.maxtcs = 0;
9890 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9891 hw->local_dcbx_config.etscfg.tsatable[0] =
9893 hw->local_dcbx_config.etsrec =
9894 hw->local_dcbx_config.etscfg;
9895 hw->local_dcbx_config.pfc.willing = 0;
9896 hw->local_dcbx_config.pfc.pfccap =
9897 I40E_MAX_TRAFFIC_CLASS;
9898 /* FW needs one App to configure HW */
9899 hw->local_dcbx_config.numapps = 1;
9900 hw->local_dcbx_config.app[0].selector =
9901 I40E_APP_SEL_ETHTYPE;
9902 hw->local_dcbx_config.app[0].priority = 3;
9903 hw->local_dcbx_config.app[0].protocolid =
9904 I40E_APP_PROTOID_FCOE;
9905 ret = i40e_set_dcb_config(hw);
9908 "default dcb config fails. err = %d, aq_err = %d.",
9909 ret, hw->aq.asq_last_status);
9914 "DCB initialization in FW fails, err = %d, aq_err = %d.",
9915 ret, hw->aq.asq_last_status);
9919 ret = i40e_aq_start_lldp(hw, NULL);
9920 if (ret != I40E_SUCCESS)
9921 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9923 ret = i40e_init_dcb(hw);
9925 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9927 "HW doesn't support DCBX offload.");
9932 "DCBX configuration failed, err = %d, aq_err = %d.",
9933 ret, hw->aq.asq_last_status);
9941 * i40e_dcb_setup - setup dcb related config
9942 * @dev: device being configured
9944 * Returns 0 on success, negative value on failure
9947 i40e_dcb_setup(struct rte_eth_dev *dev)
9949 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9950 struct i40e_dcbx_config dcb_cfg;
9954 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9955 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9959 if (pf->vf_num != 0)
9960 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9962 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9964 PMD_INIT_LOG(ERR, "invalid dcb config");
9967 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9969 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9977 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9978 struct rte_eth_dcb_info *dcb_info)
9980 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9981 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9982 struct i40e_vsi *vsi = pf->main_vsi;
9983 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9984 uint16_t bsf, tc_mapping;
9987 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9988 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9990 dcb_info->nb_tcs = 1;
9991 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9992 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9993 for (i = 0; i < dcb_info->nb_tcs; i++)
9994 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9996 /* get queue mapping if vmdq is disabled */
9997 if (!pf->nb_cfg_vmdq_vsi) {
9998 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9999 if (!(vsi->enabled_tc & (1 << i)))
10001 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10002 dcb_info->tc_queue.tc_rxq[j][i].base =
10003 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10004 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10005 dcb_info->tc_queue.tc_txq[j][i].base =
10006 dcb_info->tc_queue.tc_rxq[j][i].base;
10007 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10008 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10009 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10010 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10011 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10016 /* get queue mapping if vmdq is enabled */
10018 vsi = pf->vmdq[j].vsi;
10019 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10020 if (!(vsi->enabled_tc & (1 << i)))
10022 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10023 dcb_info->tc_queue.tc_rxq[j][i].base =
10024 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10025 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10026 dcb_info->tc_queue.tc_txq[j][i].base =
10027 dcb_info->tc_queue.tc_rxq[j][i].base;
10028 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10029 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10030 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10031 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10032 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10035 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10040 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10042 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10043 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10044 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10045 uint16_t interval =
10046 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10047 uint16_t msix_intr;
10049 msix_intr = intr_handle->intr_vec[queue_id];
10050 if (msix_intr == I40E_MISC_VEC_ID)
10051 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10052 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10053 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10054 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10056 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10059 I40E_PFINT_DYN_CTLN(msix_intr -
10060 I40E_RX_VEC_START),
10061 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10062 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10063 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10065 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10067 I40E_WRITE_FLUSH(hw);
10068 rte_intr_enable(&pci_dev->intr_handle);
10074 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10076 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10077 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10078 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10079 uint16_t msix_intr;
10081 msix_intr = intr_handle->intr_vec[queue_id];
10082 if (msix_intr == I40E_MISC_VEC_ID)
10083 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10086 I40E_PFINT_DYN_CTLN(msix_intr -
10087 I40E_RX_VEC_START),
10089 I40E_WRITE_FLUSH(hw);
10094 static int i40e_get_regs(struct rte_eth_dev *dev,
10095 struct rte_dev_reg_info *regs)
10097 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10098 uint32_t *ptr_data = regs->data;
10099 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10100 const struct i40e_reg_info *reg_info;
10102 if (ptr_data == NULL) {
10103 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10104 regs->width = sizeof(uint32_t);
10108 /* The first few registers have to be read using AQ operations */
10110 while (i40e_regs_adminq[reg_idx].name) {
10111 reg_info = &i40e_regs_adminq[reg_idx++];
10112 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10114 arr_idx2 <= reg_info->count2;
10116 reg_offset = arr_idx * reg_info->stride1 +
10117 arr_idx2 * reg_info->stride2;
10118 reg_offset += reg_info->base_addr;
10119 ptr_data[reg_offset >> 2] =
10120 i40e_read_rx_ctl(hw, reg_offset);
10124 /* The remaining registers can be read using primitives */
10126 while (i40e_regs_others[reg_idx].name) {
10127 reg_info = &i40e_regs_others[reg_idx++];
10128 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10130 arr_idx2 <= reg_info->count2;
10132 reg_offset = arr_idx * reg_info->stride1 +
10133 arr_idx2 * reg_info->stride2;
10134 reg_offset += reg_info->base_addr;
10135 ptr_data[reg_offset >> 2] =
10136 I40E_READ_REG(hw, reg_offset);
10143 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10145 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10147 /* Convert word count to byte count */
10148 return hw->nvm.sr_size << 1;
10151 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10152 struct rte_dev_eeprom_info *eeprom)
10154 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10155 uint16_t *data = eeprom->data;
10156 uint16_t offset, length, cnt_words;
10159 offset = eeprom->offset >> 1;
10160 length = eeprom->length >> 1;
10161 cnt_words = length;
10163 if (offset > hw->nvm.sr_size ||
10164 offset + length > hw->nvm.sr_size) {
10165 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10169 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10171 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10172 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10173 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10180 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10181 struct ether_addr *mac_addr)
10183 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10185 if (!is_valid_assigned_ether_addr(mac_addr)) {
10186 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10190 /* Flags: 0x3 updates port address */
10191 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10195 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10197 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10198 struct rte_eth_dev_data *dev_data = pf->dev_data;
10199 uint32_t frame_size = mtu + ETHER_HDR_LEN
10200 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10203 /* check if mtu is within the allowed range */
10204 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10207 /* mtu setting is forbidden if port is start */
10208 if (dev_data->dev_started) {
10209 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10210 dev_data->port_id);
10214 if (frame_size > ETHER_MAX_LEN)
10215 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10217 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10219 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10224 /* Restore ethertype filter */
10226 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10228 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10229 struct i40e_ethertype_filter_list
10230 *ethertype_list = &pf->ethertype.ethertype_list;
10231 struct i40e_ethertype_filter *f;
10232 struct i40e_control_filter_stats stats;
10235 TAILQ_FOREACH(f, ethertype_list, rules) {
10237 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10238 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10239 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10240 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10241 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10243 memset(&stats, 0, sizeof(stats));
10244 i40e_aq_add_rem_control_packet_filter(hw,
10245 f->input.mac_addr.addr_bytes,
10246 f->input.ether_type,
10247 flags, pf->main_vsi->seid,
10248 f->queue, 1, &stats, NULL);
10250 PMD_DRV_LOG(INFO, "Ethertype filter:"
10251 " mac_etype_used = %u, etype_used = %u,"
10252 " mac_etype_free = %u, etype_free = %u",
10253 stats.mac_etype_used, stats.etype_used,
10254 stats.mac_etype_free, stats.etype_free);
10257 /* Restore tunnel filter */
10259 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10261 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10262 struct i40e_vsi *vsi = pf->main_vsi;
10263 struct i40e_tunnel_filter_list
10264 *tunnel_list = &pf->tunnel.tunnel_list;
10265 struct i40e_tunnel_filter *f;
10266 struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10268 TAILQ_FOREACH(f, tunnel_list, rules) {
10269 memset(&cld_filter, 0, sizeof(cld_filter));
10270 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10271 cld_filter.queue_number = f->queue;
10272 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10277 i40e_filter_restore(struct i40e_pf *pf)
10279 i40e_ethertype_filter_restore(pf);
10280 i40e_tunnel_filter_restore(pf);
10281 i40e_fdir_filter_restore(pf);
10285 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10287 if (strcmp(dev->driver->pci_drv.driver.name,
10288 drv->pci_drv.driver.name))
10295 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10297 struct rte_eth_dev *dev;
10298 struct i40e_pf *pf;
10300 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10302 dev = &rte_eth_devices[port];
10304 if (!is_device_supported(dev, &rte_i40e_pmd))
10307 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10309 if (vf >= pf->vf_num || !pf->vfs) {
10310 PMD_DRV_LOG(ERR, "Invalid argument.");
10314 i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10320 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10322 struct rte_eth_dev *dev;
10323 struct i40e_pf *pf;
10324 struct i40e_vsi *vsi;
10325 struct i40e_hw *hw;
10326 struct i40e_vsi_context ctxt;
10329 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10331 dev = &rte_eth_devices[port];
10333 if (!is_device_supported(dev, &rte_i40e_pmd))
10336 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10338 if (vf_id >= pf->vf_num || !pf->vfs) {
10339 PMD_DRV_LOG(ERR, "Invalid argument.");
10343 vsi = pf->vfs[vf_id].vsi;
10345 PMD_DRV_LOG(ERR, "Invalid VSI.");
10349 /* Check if it has been already on or off */
10350 if (vsi->info.valid_sections &
10351 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10353 if ((vsi->info.sec_flags &
10354 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10355 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10356 return 0; /* already on */
10358 if ((vsi->info.sec_flags &
10359 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10360 return 0; /* already off */
10364 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10366 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10368 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10370 memset(&ctxt, 0, sizeof(ctxt));
10371 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10372 ctxt.seid = vsi->seid;
10374 hw = I40E_VSI_TO_HW(vsi);
10375 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10376 if (ret != I40E_SUCCESS) {
10378 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10385 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10389 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10390 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10393 for (j = 0; j < I40E_VFTA_SIZE; j++) {
10397 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10398 if (!(vsi->vfta[j] & (1 << k)))
10401 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10405 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10407 ret = i40e_aq_add_vlan(hw, vsi->seid,
10408 &vlan_data, 1, NULL);
10410 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10411 &vlan_data, 1, NULL);
10412 if (ret != I40E_SUCCESS) {
10414 "Failed to add/rm vlan filter");
10420 return I40E_SUCCESS;
10424 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10426 struct rte_eth_dev *dev;
10427 struct i40e_pf *pf;
10428 struct i40e_vsi *vsi;
10429 struct i40e_hw *hw;
10430 struct i40e_vsi_context ctxt;
10433 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10435 dev = &rte_eth_devices[port];
10437 if (!is_device_supported(dev, &rte_i40e_pmd))
10440 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10442 if (vf_id >= pf->vf_num || !pf->vfs) {
10443 PMD_DRV_LOG(ERR, "Invalid argument.");
10447 vsi = pf->vfs[vf_id].vsi;
10449 PMD_DRV_LOG(ERR, "Invalid VSI.");
10453 /* Check if it has been already on or off */
10454 if (vsi->vlan_anti_spoof_on == on)
10455 return 0; /* already on or off */
10457 vsi->vlan_anti_spoof_on = on;
10458 ret = i40e_add_rm_all_vlan_filter(vsi, on);
10460 PMD_DRV_LOG(ERR, "Failed to remove VLAN filters.");
10464 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10466 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10468 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10470 memset(&ctxt, 0, sizeof(ctxt));
10471 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10472 ctxt.seid = vsi->seid;
10474 hw = I40E_VSI_TO_HW(vsi);
10475 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10476 if (ret != I40E_SUCCESS) {
10478 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10485 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10487 struct i40e_mac_filter *f;
10488 struct i40e_macvlan_filter *mv_f;
10490 enum rte_mac_filter_type filter_type;
10491 int ret = I40E_SUCCESS;
10494 /* remove all the MACs */
10495 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10496 vlan_num = vsi->vlan_num;
10497 filter_type = f->mac_info.filter_type;
10498 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10499 filter_type == RTE_MACVLAN_HASH_MATCH) {
10500 if (vlan_num == 0) {
10501 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10502 return I40E_ERR_PARAM;
10504 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10505 filter_type == RTE_MAC_HASH_MATCH)
10508 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10510 PMD_DRV_LOG(ERR, "failed to allocate memory");
10511 return I40E_ERR_NO_MEMORY;
10514 for (i = 0; i < vlan_num; i++) {
10515 mv_f[i].filter_type = filter_type;
10516 (void)rte_memcpy(&mv_f[i].macaddr,
10517 &f->mac_info.mac_addr,
10520 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10521 filter_type == RTE_MACVLAN_HASH_MATCH) {
10522 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10523 &f->mac_info.mac_addr);
10524 if (ret != I40E_SUCCESS) {
10530 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10531 if (ret != I40E_SUCCESS) {
10537 ret = I40E_SUCCESS;
10544 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10546 struct i40e_mac_filter *f;
10547 struct i40e_macvlan_filter *mv_f;
10548 int i, vlan_num = 0;
10549 int ret = I40E_SUCCESS;
10552 /* restore all the MACs */
10553 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10554 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10555 (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10557 * If vlan_num is 0, that's the first time to add mac,
10558 * set mask for vlan_id 0.
10560 if (vsi->vlan_num == 0) {
10561 i40e_set_vlan_filter(vsi, 0, 1);
10564 vlan_num = vsi->vlan_num;
10565 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10566 (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10569 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10571 PMD_DRV_LOG(ERR, "failed to allocate memory");
10572 return I40E_ERR_NO_MEMORY;
10575 for (i = 0; i < vlan_num; i++) {
10576 mv_f[i].filter_type = f->mac_info.filter_type;
10577 (void)rte_memcpy(&mv_f[i].macaddr,
10578 &f->mac_info.mac_addr,
10582 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10583 f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10584 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10585 &f->mac_info.mac_addr);
10586 if (ret != I40E_SUCCESS) {
10592 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10593 if (ret != I40E_SUCCESS) {
10599 ret = I40E_SUCCESS;
10606 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
10608 struct i40e_vsi_context ctxt;
10609 struct i40e_hw *hw;
10615 hw = I40E_VSI_TO_HW(vsi);
10617 /* Use the FW API if FW >= v5.0 */
10618 if (hw->aq.fw_maj_ver < 5) {
10619 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
10623 /* Check if it has been already on or off */
10624 if (vsi->info.valid_sections &
10625 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
10627 if ((vsi->info.switch_id &
10628 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
10629 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
10630 return 0; /* already on */
10632 if ((vsi->info.switch_id &
10633 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
10634 return 0; /* already off */
10638 /* remove all the MAC and VLAN first */
10639 ret = i40e_vsi_rm_mac_filter(vsi);
10641 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
10644 if (vsi->vlan_anti_spoof_on) {
10645 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
10647 PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
10652 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
10654 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10656 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10658 memset(&ctxt, 0, sizeof(ctxt));
10659 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10660 ctxt.seid = vsi->seid;
10662 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10663 if (ret != I40E_SUCCESS) {
10664 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10668 /* add all the MAC and VLAN back */
10669 ret = i40e_vsi_restore_mac_filter(vsi);
10672 if (vsi->vlan_anti_spoof_on) {
10673 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
10682 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
10684 struct rte_eth_dev *dev;
10685 struct i40e_pf *pf;
10686 struct i40e_pf_vf *vf;
10687 struct i40e_vsi *vsi;
10691 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10693 dev = &rte_eth_devices[port];
10695 if (!is_device_supported(dev, &rte_i40e_pmd))
10698 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10700 /* setup PF TX loopback */
10701 vsi = pf->main_vsi;
10702 ret = i40e_vsi_set_tx_loopback(vsi, on);
10706 /* setup TX loopback for all the VFs */
10708 /* if no VF, do nothing. */
10712 for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
10713 vf = &pf->vfs[vf_id];
10716 ret = i40e_vsi_set_tx_loopback(vsi, on);
10725 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10727 struct rte_eth_dev *dev;
10728 struct i40e_pf *pf;
10729 struct i40e_vsi *vsi;
10730 struct i40e_hw *hw;
10733 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10735 dev = &rte_eth_devices[port];
10737 if (!is_device_supported(dev, &rte_i40e_pmd))
10740 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10742 if (vf_id >= pf->vf_num || !pf->vfs) {
10743 PMD_DRV_LOG(ERR, "Invalid argument.");
10747 vsi = pf->vfs[vf_id].vsi;
10749 PMD_DRV_LOG(ERR, "Invalid VSI.");
10753 hw = I40E_VSI_TO_HW(vsi);
10755 ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
10757 if (ret != I40E_SUCCESS) {
10759 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
10766 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10768 struct rte_eth_dev *dev;
10769 struct i40e_pf *pf;
10770 struct i40e_vsi *vsi;
10771 struct i40e_hw *hw;
10774 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10776 dev = &rte_eth_devices[port];
10778 if (!is_device_supported(dev, &rte_i40e_pmd))
10781 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10783 if (vf_id >= pf->vf_num || !pf->vfs) {
10784 PMD_DRV_LOG(ERR, "Invalid argument.");
10788 vsi = pf->vfs[vf_id].vsi;
10790 PMD_DRV_LOG(ERR, "Invalid VSI.");
10794 hw = I40E_VSI_TO_HW(vsi);
10796 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
10798 if (ret != I40E_SUCCESS) {
10800 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
10807 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
10808 struct ether_addr *mac_addr)
10810 struct i40e_mac_filter *f;
10811 struct rte_eth_dev *dev;
10812 struct i40e_pf_vf *vf;
10813 struct i40e_vsi *vsi;
10814 struct i40e_pf *pf;
10817 if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
10820 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10822 dev = &rte_eth_devices[port];
10824 if (!is_device_supported(dev, &rte_i40e_pmd))
10827 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10829 if (vf_id >= pf->vf_num || !pf->vfs)
10832 vf = &pf->vfs[vf_id];
10835 PMD_DRV_LOG(ERR, "Invalid VSI.");
10839 ether_addr_copy(mac_addr, &vf->mac_addr);
10841 /* Remove all existing mac */
10842 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
10843 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
10848 /* Set vlan strip on/off for specific VF from host */
10850 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
10852 struct rte_eth_dev *dev;
10853 struct i40e_pf *pf;
10854 struct i40e_vsi *vsi;
10857 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10859 dev = &rte_eth_devices[port];
10861 if (!is_device_supported(dev, &rte_i40e_pmd))
10864 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10866 if (vf_id >= pf->vf_num || !pf->vfs) {
10867 PMD_DRV_LOG(ERR, "Invalid argument.");
10871 vsi = pf->vfs[vf_id].vsi;
10876 ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
10877 if (ret != I40E_SUCCESS) {
10879 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
10885 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
10888 struct rte_eth_dev *dev;
10889 struct i40e_pf *pf;
10890 struct i40e_hw *hw;
10891 struct i40e_vsi *vsi;
10892 struct i40e_vsi_context ctxt;
10895 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10897 if (vlan_id > ETHER_MAX_VLAN_ID) {
10898 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
10902 dev = &rte_eth_devices[port];
10904 if (!is_device_supported(dev, &rte_i40e_pmd))
10907 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10908 hw = I40E_PF_TO_HW(pf);
10911 * return -ENODEV if SRIOV not enabled, VF number not configured
10912 * or no queue assigned.
10914 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10915 pf->vf_nb_qps == 0)
10918 if (vf_id >= pf->vf_num || !pf->vfs) {
10919 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10923 vsi = pf->vfs[vf_id].vsi;
10925 PMD_DRV_LOG(ERR, "Invalid VSI.");
10929 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
10930 vsi->info.pvid = vlan_id;
10932 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
10934 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
10936 memset(&ctxt, 0, sizeof(ctxt));
10937 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10938 ctxt.seid = vsi->seid;
10940 hw = I40E_VSI_TO_HW(vsi);
10941 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10942 if (ret != I40E_SUCCESS) {
10944 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10950 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
10953 struct rte_eth_dev *dev;
10954 struct i40e_pf *pf;
10955 struct i40e_vsi *vsi;
10956 struct i40e_hw *hw;
10959 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10962 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
10966 dev = &rte_eth_devices[port];
10968 if (!is_device_supported(dev, &rte_i40e_pmd))
10971 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10972 hw = I40E_PF_TO_HW(pf);
10974 if (vf_id >= pf->vf_num || !pf->vfs) {
10975 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10980 * return -ENODEV if SRIOV not enabled, VF number not configured
10981 * or no queue assigned.
10983 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10984 pf->vf_nb_qps == 0) {
10985 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
10989 vsi = pf->vfs[vf_id].vsi;
10991 PMD_DRV_LOG(ERR, "Invalid VSI.");
10995 hw = I40E_VSI_TO_HW(vsi);
10997 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, on, NULL);
10998 if (ret != I40E_SUCCESS) {
11000 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11006 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11008 struct rte_eth_dev *dev;
11009 struct i40e_pf *pf;
11010 struct i40e_hw *hw;
11011 struct i40e_vsi *vsi;
11012 struct i40e_vsi_context ctxt;
11015 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11018 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11022 dev = &rte_eth_devices[port];
11024 if (!is_device_supported(dev, &rte_i40e_pmd))
11027 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11028 hw = I40E_PF_TO_HW(pf);
11031 * return -ENODEV if SRIOV not enabled, VF number not configured
11032 * or no queue assigned.
11034 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11035 pf->vf_nb_qps == 0) {
11036 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11040 if (vf_id >= pf->vf_num || !pf->vfs) {
11041 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11045 vsi = pf->vfs[vf_id].vsi;
11047 PMD_DRV_LOG(ERR, "Invalid VSI.");
11051 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11053 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11054 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11056 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11057 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11060 memset(&ctxt, 0, sizeof(ctxt));
11061 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11062 ctxt.seid = vsi->seid;
11064 hw = I40E_VSI_TO_HW(vsi);
11065 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11066 if (ret != I40E_SUCCESS) {
11068 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11074 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11075 uint64_t vf_mask, uint8_t on)
11077 struct rte_eth_dev *dev;
11078 struct i40e_pf *pf;
11079 struct i40e_hw *hw;
11081 int ret = I40E_SUCCESS;
11083 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11085 dev = &rte_eth_devices[port];
11087 if (!is_device_supported(dev, &rte_i40e_pmd))
11090 if (vlan_id > ETHER_MAX_VLAN_ID) {
11091 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11095 if (vf_mask == 0) {
11096 PMD_DRV_LOG(ERR, "No VF.");
11101 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11105 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11106 hw = I40E_PF_TO_HW(pf);
11109 * return -ENODEV if SRIOV not enabled, VF number not configured
11110 * or no queue assigned.
11112 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11113 pf->vf_nb_qps == 0) {
11114 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11118 for (vf_idx = 0; vf_idx < 64 && ret == I40E_SUCCESS; vf_idx++) {
11119 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11121 ret = i40e_vsi_add_vlan(pf->vfs[vf_idx].vsi,
11124 ret = i40e_vsi_delete_vlan(pf->vfs[vf_idx].vsi,
11129 if (ret != I40E_SUCCESS) {
11131 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11138 rte_pmd_i40e_get_vf_stats(uint8_t port,
11140 struct rte_eth_stats *stats)
11142 struct rte_eth_dev *dev;
11143 struct i40e_pf *pf;
11144 struct i40e_vsi *vsi;
11146 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11148 dev = &rte_eth_devices[port];
11150 if (!is_device_supported(dev, &rte_i40e_pmd))
11153 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11155 if (vf_id >= pf->vf_num || !pf->vfs) {
11156 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11160 vsi = pf->vfs[vf_id].vsi;
11162 PMD_DRV_LOG(ERR, "Invalid VSI.");
11166 i40e_update_vsi_stats(vsi);
11168 stats->ipackets = vsi->eth_stats.rx_unicast +
11169 vsi->eth_stats.rx_multicast +
11170 vsi->eth_stats.rx_broadcast;
11171 stats->opackets = vsi->eth_stats.tx_unicast +
11172 vsi->eth_stats.tx_multicast +
11173 vsi->eth_stats.tx_broadcast;
11174 stats->ibytes = vsi->eth_stats.rx_bytes;
11175 stats->obytes = vsi->eth_stats.tx_bytes;
11176 stats->ierrors = vsi->eth_stats.rx_discards;
11177 stats->oerrors = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11183 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11186 struct rte_eth_dev *dev;
11187 struct i40e_pf *pf;
11188 struct i40e_vsi *vsi;
11190 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11192 dev = &rte_eth_devices[port];
11194 if (!is_device_supported(dev, &rte_i40e_pmd))
11197 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11199 if (vf_id >= pf->vf_num || !pf->vfs) {
11200 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11204 vsi = pf->vfs[vf_id].vsi;
11206 PMD_DRV_LOG(ERR, "Invalid VSI.");
11210 vsi->offset_loaded = false;
11211 i40e_update_vsi_stats(vsi);