4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memzone.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_alarm.h>
54 #include <rte_eth_ctrl.h>
55 #include <rte_tailq.h>
56 #include <rte_hash_crc.h>
58 #include "i40e_logs.h"
59 #include "base/i40e_prototype.h"
60 #include "base/i40e_adminq_cmd.h"
61 #include "base/i40e_type.h"
62 #include "base/i40e_register.h"
63 #include "base/i40e_dcb.h"
64 #include "i40e_ethdev.h"
65 #include "i40e_rxtx.h"
67 #include "i40e_regs.h"
69 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
70 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
72 #define I40E_CLEAR_PXE_WAIT_MS 200
74 /* Maximun number of capability elements */
75 #define I40E_MAX_CAP_ELE_NUM 128
77 /* Wait count and interval */
78 #define I40E_CHK_Q_ENA_COUNT 1000
79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
81 /* Maximun number of VSI */
82 #define I40E_MAX_NUM_VSIS (384UL)
84 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
86 /* Flow control default timer */
87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
89 /* Flow control default high water */
90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
92 /* Flow control default low water */
93 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
95 /* Flow control enable fwd bit */
96 #define I40E_PRTMAC_FWD_CTRL 0x00000001
98 /* Receive Packet Buffer size */
99 #define I40E_RXPBSIZE (968 * 1024)
101 /* Kilobytes shift */
102 #define I40E_KILOSHIFT 10
104 /* Receive Average Packet Size in Byte*/
105 #define I40E_PACKET_AVERAGE_SIZE 128
107 /* Mask of PF interrupt causes */
108 #define I40E_PFINT_ICR0_ENA_MASK ( \
109 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_GRST_MASK | \
112 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
113 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 /* Additional timesync values. */
133 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
134 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
135 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
136 #define I40E_PRTTSYN_TSYNENA 0x80000000
137 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
140 #define I40E_MAX_PERCENT 100
141 #define I40E_DEFAULT_DCB_APP_NUM 1
142 #define I40E_DEFAULT_DCB_APP_PRIO 3
145 * Below are values for writing un-exposed registers suggested
148 /* Destination MAC address */
149 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
150 /* Source MAC address */
151 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
153 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
155 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
156 /* Single VLAN tag in the inner L2 header */
157 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
158 /* Source IPv4 address */
159 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
160 /* Destination IPv4 address */
161 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
162 /* Source IPv4 address for X722 */
163 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
164 /* Destination IPv4 address for X722 */
165 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
166 /* IPv4 Protocol for X722 */
167 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
168 /* IPv4 Time to Live for X722 */
169 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
170 /* IPv4 Type of Service (TOS) */
171 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
173 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
174 /* IPv4 Time to Live */
175 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
176 /* Source IPv6 address */
177 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
178 /* Destination IPv6 address */
179 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
180 /* IPv6 Traffic Class (TC) */
181 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
182 /* IPv6 Next Header */
183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
187 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
188 /* Destination L4 port */
189 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
190 /* SCTP verification tag */
191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
194 /* Source port of tunneling UDP */
195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
196 /* Destination port of tunneling UDP */
197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
198 /* UDP Tunneling ID, NVGRE/GRE key */
199 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
200 /* Last ether type */
201 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
202 /* Tunneling outer destination IPv4 address */
203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
204 /* Tunneling outer destination IPv6 address */
205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
206 /* 1st word of flex payload */
207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
208 /* 2nd word of flex payload */
209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
210 /* 3rd word of flex payload */
211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
212 /* 4th word of flex payload */
213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
214 /* 5th word of flex payload */
215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
216 /* 6th word of flex payload */
217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
218 /* 7th word of flex payload */
219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
220 /* 8th word of flex payload */
221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
222 /* all 8 words flex payload */
223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
224 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
226 #define I40E_TRANSLATE_INSET 0
227 #define I40E_TRANSLATE_REG 1
229 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
230 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
231 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
232 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
234 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
236 /* PCI offset for querying capability */
237 #define PCI_DEV_CAP_REG 0xA4
238 /* PCI offset for enabling/disabling Extended Tag */
239 #define PCI_DEV_CTRL_REG 0xA8
240 /* Bit mask of Extended Tag capability */
241 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
242 /* Bit shift of Extended Tag enable/disable */
243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
244 /* Bit mask of Extended Tag enable/disable */
245 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int i40e_dev_configure(struct rte_eth_dev *dev);
250 static int i40e_dev_start(struct rte_eth_dev *dev);
251 static void i40e_dev_stop(struct rte_eth_dev *dev);
252 static void i40e_dev_close(struct rte_eth_dev *dev);
253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
260 struct rte_eth_stats *stats);
261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
262 struct rte_eth_xstat *xstats, unsigned n);
263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
264 struct rte_eth_xstat_name *xstats_names,
266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
272 char *fw_version, size_t fw_size);
273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
274 struct rte_eth_dev_info *dev_info);
275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
279 enum rte_vlan_type vlan_type,
281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
289 struct rte_eth_fc_conf *fc_conf);
290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
291 struct rte_eth_fc_conf *fc_conf);
292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
293 struct rte_eth_pfc_conf *pfc_conf);
294 static int i40e_macaddr_add(struct rte_eth_dev *dev,
295 struct ether_addr *mac_addr,
298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
300 struct rte_eth_rss_reta_entry64 *reta_conf,
302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
303 struct rte_eth_rss_reta_entry64 *reta_conf,
306 static int i40e_get_cap(struct i40e_hw *hw);
307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
308 static int i40e_pf_setup(struct i40e_pf *pf);
309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
314 bool offset_loaded, uint64_t *offset, uint64_t *stat);
315 static void i40e_stat_update_48(struct i40e_hw *hw,
321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
322 static void i40e_dev_interrupt_handler(void *param);
323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
324 uint32_t base, uint32_t num);
325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
331 static int i40e_veb_release(struct i40e_veb *veb);
332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
333 struct i40e_vsi *vsi);
334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
337 struct i40e_macvlan_filter *mv_f,
340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
342 struct rte_eth_rss_conf *rss_conf);
343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
344 struct rte_eth_rss_conf *rss_conf);
345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
346 struct rte_eth_udp_tunnel *udp_tunnel);
347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
348 struct rte_eth_udp_tunnel *udp_tunnel);
349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
351 enum rte_filter_op filter_op,
353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
354 enum rte_filter_type filter_type,
355 enum rte_filter_op filter_op,
357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
358 struct rte_eth_dcb_info *dcb_info);
359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
360 static void i40e_configure_registers(struct i40e_hw *hw);
361 static void i40e_hw_init(struct rte_eth_dev *dev);
362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
364 struct rte_eth_mirror_conf *mirror_conf,
365 uint8_t sw_id, uint8_t on);
366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
371 struct timespec *timestamp,
373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
374 struct timespec *timestamp);
375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
380 struct timespec *timestamp);
381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
382 const struct timespec *timestamp);
384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
389 static int i40e_get_regs(struct rte_eth_dev *dev,
390 struct rte_dev_reg_info *regs);
392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
395 struct rte_dev_eeprom_info *eeprom);
397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
398 struct ether_addr *mac_addr);
400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
402 static int i40e_ethertype_filter_convert(
403 const struct rte_eth_ethertype_filter *input,
404 struct i40e_ethertype_filter *filter);
405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
406 struct i40e_ethertype_filter *filter);
408 static int i40e_tunnel_filter_convert(
409 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
410 struct i40e_tunnel_filter *tunnel_filter);
411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
412 struct i40e_tunnel_filter *tunnel_filter);
413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
417 static void i40e_filter_restore(struct i40e_pf *pf);
418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
420 int i40e_logtype_init;
421 int i40e_logtype_driver;
423 static const struct rte_pci_id pci_id_i40e_map[] = {
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
444 { .vendor_id = 0, /* sentinel */ },
447 static const struct eth_dev_ops i40e_eth_dev_ops = {
448 .dev_configure = i40e_dev_configure,
449 .dev_start = i40e_dev_start,
450 .dev_stop = i40e_dev_stop,
451 .dev_close = i40e_dev_close,
452 .promiscuous_enable = i40e_dev_promiscuous_enable,
453 .promiscuous_disable = i40e_dev_promiscuous_disable,
454 .allmulticast_enable = i40e_dev_allmulticast_enable,
455 .allmulticast_disable = i40e_dev_allmulticast_disable,
456 .dev_set_link_up = i40e_dev_set_link_up,
457 .dev_set_link_down = i40e_dev_set_link_down,
458 .link_update = i40e_dev_link_update,
459 .stats_get = i40e_dev_stats_get,
460 .xstats_get = i40e_dev_xstats_get,
461 .xstats_get_names = i40e_dev_xstats_get_names,
462 .stats_reset = i40e_dev_stats_reset,
463 .xstats_reset = i40e_dev_stats_reset,
464 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
465 .fw_version_get = i40e_fw_version_get,
466 .dev_infos_get = i40e_dev_info_get,
467 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
468 .vlan_filter_set = i40e_vlan_filter_set,
469 .vlan_tpid_set = i40e_vlan_tpid_set,
470 .vlan_offload_set = i40e_vlan_offload_set,
471 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
472 .vlan_pvid_set = i40e_vlan_pvid_set,
473 .rx_queue_start = i40e_dev_rx_queue_start,
474 .rx_queue_stop = i40e_dev_rx_queue_stop,
475 .tx_queue_start = i40e_dev_tx_queue_start,
476 .tx_queue_stop = i40e_dev_tx_queue_stop,
477 .rx_queue_setup = i40e_dev_rx_queue_setup,
478 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
479 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
480 .rx_queue_release = i40e_dev_rx_queue_release,
481 .rx_queue_count = i40e_dev_rx_queue_count,
482 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
483 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
484 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
485 .tx_queue_setup = i40e_dev_tx_queue_setup,
486 .tx_queue_release = i40e_dev_tx_queue_release,
487 .dev_led_on = i40e_dev_led_on,
488 .dev_led_off = i40e_dev_led_off,
489 .flow_ctrl_get = i40e_flow_ctrl_get,
490 .flow_ctrl_set = i40e_flow_ctrl_set,
491 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
492 .mac_addr_add = i40e_macaddr_add,
493 .mac_addr_remove = i40e_macaddr_remove,
494 .reta_update = i40e_dev_rss_reta_update,
495 .reta_query = i40e_dev_rss_reta_query,
496 .rss_hash_update = i40e_dev_rss_hash_update,
497 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
498 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
499 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
500 .filter_ctrl = i40e_dev_filter_ctrl,
501 .rxq_info_get = i40e_rxq_info_get,
502 .txq_info_get = i40e_txq_info_get,
503 .mirror_rule_set = i40e_mirror_rule_set,
504 .mirror_rule_reset = i40e_mirror_rule_reset,
505 .timesync_enable = i40e_timesync_enable,
506 .timesync_disable = i40e_timesync_disable,
507 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
508 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
509 .get_dcb_info = i40e_dev_get_dcb_info,
510 .timesync_adjust_time = i40e_timesync_adjust_time,
511 .timesync_read_time = i40e_timesync_read_time,
512 .timesync_write_time = i40e_timesync_write_time,
513 .get_reg = i40e_get_regs,
514 .get_eeprom_length = i40e_get_eeprom_length,
515 .get_eeprom = i40e_get_eeprom,
516 .mac_addr_set = i40e_set_default_mac_addr,
517 .mtu_set = i40e_dev_mtu_set,
518 .tm_ops_get = i40e_tm_ops_get,
521 /* store statistics names and its offset in stats structure */
522 struct rte_i40e_xstats_name_off {
523 char name[RTE_ETH_XSTATS_NAME_SIZE];
527 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
528 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
529 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
530 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
531 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
532 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
533 rx_unknown_protocol)},
534 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
535 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
536 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
537 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
540 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
541 sizeof(rte_i40e_stats_strings[0]))
543 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
544 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
545 tx_dropped_link_down)},
546 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
547 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
549 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
550 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
552 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
554 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
556 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
557 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
558 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
559 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
560 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
561 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
573 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
575 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
577 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
578 mac_short_packet_dropped)},
579 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
581 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
582 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
583 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
591 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
593 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
595 {"rx_flow_director_atr_match_packets",
596 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
597 {"rx_flow_director_sb_match_packets",
598 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
599 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
601 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
603 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
605 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
609 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
610 sizeof(rte_i40e_hw_port_strings[0]))
612 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
613 {"xon_packets", offsetof(struct i40e_hw_port_stats,
615 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
619 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
620 sizeof(rte_i40e_rxq_prio_strings[0]))
622 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
623 {"xon_packets", offsetof(struct i40e_hw_port_stats,
625 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
627 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
628 priority_xon_2_xoff)},
631 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
632 sizeof(rte_i40e_txq_prio_strings[0]))
634 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
635 struct rte_pci_device *pci_dev)
637 return rte_eth_dev_pci_generic_probe(pci_dev,
638 sizeof(struct i40e_adapter), eth_i40e_dev_init);
641 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
643 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
646 static struct rte_pci_driver rte_i40e_pmd = {
647 .id_table = pci_id_i40e_map,
648 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
649 .probe = eth_i40e_pci_probe,
650 .remove = eth_i40e_pci_remove,
654 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
655 struct rte_eth_link *link)
657 struct rte_eth_link *dst = link;
658 struct rte_eth_link *src = &(dev->data->dev_link);
660 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
661 *(uint64_t *)src) == 0)
668 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
669 struct rte_eth_link *link)
671 struct rte_eth_link *dst = &(dev->data->dev_link);
672 struct rte_eth_link *src = link;
674 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
675 *(uint64_t *)src) == 0)
681 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
682 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
683 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
685 #ifndef I40E_GLQF_ORT
686 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
688 #ifndef I40E_GLQF_PIT
689 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
691 #ifndef I40E_GLQF_L3_MAP
692 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
695 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
698 * Initialize registers for flexible payload, which should be set by NVM.
699 * This should be removed from code once it is fixed in NVM.
701 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
702 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
703 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
704 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
705 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
706 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
707 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
708 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
710 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
711 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
712 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
714 /* Initialize registers for parsing packet type of QinQ */
715 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
716 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
719 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
722 * Add a ethertype filter to drop all flow control frames transmitted
726 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
728 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
729 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
730 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
731 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
734 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
735 I40E_FLOW_CONTROL_ETHERTYPE, flags,
736 pf->main_vsi_seid, 0,
740 "Failed to add filter to drop flow control frames from VSIs.");
744 floating_veb_list_handler(__rte_unused const char *key,
745 const char *floating_veb_value,
749 unsigned int count = 0;
752 bool *vf_floating_veb = opaque;
754 while (isblank(*floating_veb_value))
755 floating_veb_value++;
757 /* Reset floating VEB configuration for VFs */
758 for (idx = 0; idx < I40E_MAX_VF; idx++)
759 vf_floating_veb[idx] = false;
763 while (isblank(*floating_veb_value))
764 floating_veb_value++;
765 if (*floating_veb_value == '\0')
768 idx = strtoul(floating_veb_value, &end, 10);
769 if (errno || end == NULL)
771 while (isblank(*end))
775 } else if ((*end == ';') || (*end == '\0')) {
777 if (min == I40E_MAX_VF)
779 if (max >= I40E_MAX_VF)
780 max = I40E_MAX_VF - 1;
781 for (idx = min; idx <= max; idx++) {
782 vf_floating_veb[idx] = true;
789 floating_veb_value = end + 1;
790 } while (*end != '\0');
799 config_vf_floating_veb(struct rte_devargs *devargs,
800 uint16_t floating_veb,
801 bool *vf_floating_veb)
803 struct rte_kvargs *kvlist;
805 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
809 /* All the VFs attach to the floating VEB by default
810 * when the floating VEB is enabled.
812 for (i = 0; i < I40E_MAX_VF; i++)
813 vf_floating_veb[i] = true;
818 kvlist = rte_kvargs_parse(devargs->args, NULL);
822 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
823 rte_kvargs_free(kvlist);
826 /* When the floating_veb_list parameter exists, all the VFs
827 * will attach to the legacy VEB firstly, then configure VFs
828 * to the floating VEB according to the floating_veb_list.
830 if (rte_kvargs_process(kvlist, floating_veb_list,
831 floating_veb_list_handler,
832 vf_floating_veb) < 0) {
833 rte_kvargs_free(kvlist);
836 rte_kvargs_free(kvlist);
840 i40e_check_floating_handler(__rte_unused const char *key,
842 __rte_unused void *opaque)
844 if (strcmp(value, "1"))
851 is_floating_veb_supported(struct rte_devargs *devargs)
853 struct rte_kvargs *kvlist;
854 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
859 kvlist = rte_kvargs_parse(devargs->args, NULL);
863 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
864 rte_kvargs_free(kvlist);
867 /* Floating VEB is enabled when there's key-value:
868 * enable_floating_veb=1
870 if (rte_kvargs_process(kvlist, floating_veb_key,
871 i40e_check_floating_handler, NULL) < 0) {
872 rte_kvargs_free(kvlist);
875 rte_kvargs_free(kvlist);
881 config_floating_veb(struct rte_eth_dev *dev)
883 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
884 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
885 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
887 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
889 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
891 is_floating_veb_supported(pci_dev->device.devargs);
892 config_vf_floating_veb(pci_dev->device.devargs,
894 pf->floating_veb_list);
896 pf->floating_veb = false;
900 #define I40E_L2_TAGS_S_TAG_SHIFT 1
901 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
904 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
906 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
907 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
908 char ethertype_hash_name[RTE_HASH_NAMESIZE];
911 struct rte_hash_parameters ethertype_hash_params = {
912 .name = ethertype_hash_name,
913 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
914 .key_len = sizeof(struct i40e_ethertype_filter_input),
915 .hash_func = rte_hash_crc,
916 .hash_func_init_val = 0,
917 .socket_id = rte_socket_id(),
920 /* Initialize ethertype filter rule list and hash */
921 TAILQ_INIT(ðertype_rule->ethertype_list);
922 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
923 "ethertype_%s", dev->device->name);
924 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
925 if (!ethertype_rule->hash_table) {
926 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
929 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
930 sizeof(struct i40e_ethertype_filter *) *
931 I40E_MAX_ETHERTYPE_FILTER_NUM,
933 if (!ethertype_rule->hash_map) {
935 "Failed to allocate memory for ethertype hash map!");
937 goto err_ethertype_hash_map_alloc;
942 err_ethertype_hash_map_alloc:
943 rte_hash_free(ethertype_rule->hash_table);
949 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
951 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
952 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
953 char tunnel_hash_name[RTE_HASH_NAMESIZE];
956 struct rte_hash_parameters tunnel_hash_params = {
957 .name = tunnel_hash_name,
958 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
959 .key_len = sizeof(struct i40e_tunnel_filter_input),
960 .hash_func = rte_hash_crc,
961 .hash_func_init_val = 0,
962 .socket_id = rte_socket_id(),
965 /* Initialize tunnel filter rule list and hash */
966 TAILQ_INIT(&tunnel_rule->tunnel_list);
967 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
968 "tunnel_%s", dev->device->name);
969 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
970 if (!tunnel_rule->hash_table) {
971 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
974 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
975 sizeof(struct i40e_tunnel_filter *) *
976 I40E_MAX_TUNNEL_FILTER_NUM,
978 if (!tunnel_rule->hash_map) {
980 "Failed to allocate memory for tunnel hash map!");
982 goto err_tunnel_hash_map_alloc;
987 err_tunnel_hash_map_alloc:
988 rte_hash_free(tunnel_rule->hash_table);
994 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
996 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
997 struct i40e_fdir_info *fdir_info = &pf->fdir;
998 char fdir_hash_name[RTE_HASH_NAMESIZE];
1001 struct rte_hash_parameters fdir_hash_params = {
1002 .name = fdir_hash_name,
1003 .entries = I40E_MAX_FDIR_FILTER_NUM,
1004 .key_len = sizeof(struct rte_eth_fdir_input),
1005 .hash_func = rte_hash_crc,
1006 .hash_func_init_val = 0,
1007 .socket_id = rte_socket_id(),
1010 /* Initialize flow director filter rule list and hash */
1011 TAILQ_INIT(&fdir_info->fdir_list);
1012 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1013 "fdir_%s", dev->device->name);
1014 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1015 if (!fdir_info->hash_table) {
1016 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1019 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1020 sizeof(struct i40e_fdir_filter *) *
1021 I40E_MAX_FDIR_FILTER_NUM,
1023 if (!fdir_info->hash_map) {
1025 "Failed to allocate memory for fdir hash map!");
1027 goto err_fdir_hash_map_alloc;
1031 err_fdir_hash_map_alloc:
1032 rte_hash_free(fdir_info->hash_table);
1038 eth_i40e_dev_init(struct rte_eth_dev *dev)
1040 struct rte_pci_device *pci_dev;
1041 struct rte_intr_handle *intr_handle;
1042 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1043 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044 struct i40e_vsi *vsi;
1047 uint8_t aq_fail = 0;
1049 PMD_INIT_FUNC_TRACE();
1051 dev->dev_ops = &i40e_eth_dev_ops;
1052 dev->rx_pkt_burst = i40e_recv_pkts;
1053 dev->tx_pkt_burst = i40e_xmit_pkts;
1054 dev->tx_pkt_prepare = i40e_prep_pkts;
1056 /* for secondary processes, we don't initialise any further as primary
1057 * has already done this work. Only check we don't need a different
1059 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1060 i40e_set_rx_function(dev);
1061 i40e_set_tx_function(dev);
1064 i40e_set_default_ptype_table(dev);
1065 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1066 intr_handle = &pci_dev->intr_handle;
1068 rte_eth_copy_pci_info(dev, pci_dev);
1069 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1071 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1072 pf->adapter->eth_dev = dev;
1073 pf->dev_data = dev->data;
1075 hw->back = I40E_PF_TO_ADAPTER(pf);
1076 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1079 "Hardware is not available, as address is NULL");
1083 hw->vendor_id = pci_dev->id.vendor_id;
1084 hw->device_id = pci_dev->id.device_id;
1085 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1086 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1087 hw->bus.device = pci_dev->addr.devid;
1088 hw->bus.func = pci_dev->addr.function;
1089 hw->adapter_stopped = 0;
1091 /* Make sure all is clean before doing PF reset */
1094 /* Initialize the hardware */
1097 /* Reset here to make sure all is clean for each PF */
1098 ret = i40e_pf_reset(hw);
1100 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1104 /* Initialize the shared code (base driver) */
1105 ret = i40e_init_shared_code(hw);
1107 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1112 * To work around the NVM issue, initialize registers
1113 * for flexible payload and packet type of QinQ by
1114 * software. It should be removed once issues are fixed
1117 i40e_GLQF_reg_init(hw);
1119 /* Initialize the input set for filters (hash and fd) to default value */
1120 i40e_filter_input_set_init(pf);
1122 /* Initialize the parameters for adminq */
1123 i40e_init_adminq_parameter(hw);
1124 ret = i40e_init_adminq(hw);
1125 if (ret != I40E_SUCCESS) {
1126 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1129 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1130 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1131 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1132 ((hw->nvm.version >> 12) & 0xf),
1133 ((hw->nvm.version >> 4) & 0xff),
1134 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1136 /* initialise the L3_MAP register */
1137 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1140 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1142 /* Need the special FW version to support floating VEB */
1143 config_floating_veb(dev);
1144 /* Clear PXE mode */
1145 i40e_clear_pxe_mode(hw);
1146 i40e_dev_sync_phy_type(hw);
1149 * On X710, performance number is far from the expectation on recent
1150 * firmware versions. The fix for this issue may not be integrated in
1151 * the following firmware version. So the workaround in software driver
1152 * is needed. It needs to modify the initial values of 3 internal only
1153 * registers. Note that the workaround can be removed when it is fixed
1154 * in firmware in the future.
1156 i40e_configure_registers(hw);
1158 /* Get hw capabilities */
1159 ret = i40e_get_cap(hw);
1160 if (ret != I40E_SUCCESS) {
1161 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1162 goto err_get_capabilities;
1165 /* Initialize parameters for PF */
1166 ret = i40e_pf_parameter_init(dev);
1168 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1169 goto err_parameter_init;
1172 /* Initialize the queue management */
1173 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1175 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1176 goto err_qp_pool_init;
1178 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1179 hw->func_caps.num_msix_vectors - 1);
1181 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1182 goto err_msix_pool_init;
1185 /* Initialize lan hmc */
1186 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1187 hw->func_caps.num_rx_qp, 0, 0);
1188 if (ret != I40E_SUCCESS) {
1189 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1190 goto err_init_lan_hmc;
1193 /* Configure lan hmc */
1194 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1195 if (ret != I40E_SUCCESS) {
1196 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1197 goto err_configure_lan_hmc;
1200 /* Get and check the mac address */
1201 i40e_get_mac_addr(hw, hw->mac.addr);
1202 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1203 PMD_INIT_LOG(ERR, "mac address is not valid");
1205 goto err_get_mac_addr;
1207 /* Copy the permanent MAC address */
1208 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1209 (struct ether_addr *) hw->mac.perm_addr);
1211 /* Disable flow control */
1212 hw->fc.requested_mode = I40E_FC_NONE;
1213 i40e_set_fc(hw, &aq_fail, TRUE);
1215 /* Set the global registers with default ether type value */
1216 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1217 if (ret != I40E_SUCCESS) {
1219 "Failed to set the default outer VLAN ether type");
1220 goto err_setup_pf_switch;
1223 /* PF setup, which includes VSI setup */
1224 ret = i40e_pf_setup(pf);
1226 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1227 goto err_setup_pf_switch;
1230 /* reset all stats of the device, including pf and main vsi */
1231 i40e_dev_stats_reset(dev);
1235 /* Disable double vlan by default */
1236 i40e_vsi_config_double_vlan(vsi, FALSE);
1238 /* Disable S-TAG identification when floating_veb is disabled */
1239 if (!pf->floating_veb) {
1240 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1241 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1242 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1243 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1247 if (!vsi->max_macaddrs)
1248 len = ETHER_ADDR_LEN;
1250 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1252 /* Should be after VSI initialized */
1253 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1254 if (!dev->data->mac_addrs) {
1256 "Failed to allocated memory for storing mac address");
1259 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1260 &dev->data->mac_addrs[0]);
1262 /* Init dcb to sw mode by default */
1263 ret = i40e_dcb_init_configure(dev, TRUE);
1264 if (ret != I40E_SUCCESS) {
1265 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1266 pf->flags &= ~I40E_FLAG_DCB;
1268 /* Update HW struct after DCB configuration */
1271 /* initialize pf host driver to setup SRIOV resource if applicable */
1272 i40e_pf_host_init(dev);
1274 /* register callback func to eal lib */
1275 rte_intr_callback_register(intr_handle,
1276 i40e_dev_interrupt_handler, dev);
1278 /* configure and enable device interrupt */
1279 i40e_pf_config_irq0(hw, TRUE);
1280 i40e_pf_enable_irq0(hw);
1282 /* enable uio intr after callback register */
1283 rte_intr_enable(intr_handle);
1285 * Add an ethertype filter to drop all flow control frames transmitted
1286 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1289 i40e_add_tx_flow_control_drop_filter(pf);
1291 /* Set the max frame size to 0x2600 by default,
1292 * in case other drivers changed the default value.
1294 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1296 /* initialize mirror rule list */
1297 TAILQ_INIT(&pf->mirror_list);
1299 /* initialize Traffic Manager configuration */
1300 i40e_tm_conf_init(dev);
1302 ret = i40e_init_ethtype_filter_list(dev);
1304 goto err_init_ethtype_filter_list;
1305 ret = i40e_init_tunnel_filter_list(dev);
1307 goto err_init_tunnel_filter_list;
1308 ret = i40e_init_fdir_filter_list(dev);
1310 goto err_init_fdir_filter_list;
1314 err_init_fdir_filter_list:
1315 rte_free(pf->tunnel.hash_table);
1316 rte_free(pf->tunnel.hash_map);
1317 err_init_tunnel_filter_list:
1318 rte_free(pf->ethertype.hash_table);
1319 rte_free(pf->ethertype.hash_map);
1320 err_init_ethtype_filter_list:
1321 rte_free(dev->data->mac_addrs);
1323 i40e_vsi_release(pf->main_vsi);
1324 err_setup_pf_switch:
1326 err_configure_lan_hmc:
1327 (void)i40e_shutdown_lan_hmc(hw);
1329 i40e_res_pool_destroy(&pf->msix_pool);
1331 i40e_res_pool_destroy(&pf->qp_pool);
1334 err_get_capabilities:
1335 (void)i40e_shutdown_adminq(hw);
1341 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1343 struct i40e_ethertype_filter *p_ethertype;
1344 struct i40e_ethertype_rule *ethertype_rule;
1346 ethertype_rule = &pf->ethertype;
1347 /* Remove all ethertype filter rules and hash */
1348 if (ethertype_rule->hash_map)
1349 rte_free(ethertype_rule->hash_map);
1350 if (ethertype_rule->hash_table)
1351 rte_hash_free(ethertype_rule->hash_table);
1353 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1354 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1355 p_ethertype, rules);
1356 rte_free(p_ethertype);
1361 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1363 struct i40e_tunnel_filter *p_tunnel;
1364 struct i40e_tunnel_rule *tunnel_rule;
1366 tunnel_rule = &pf->tunnel;
1367 /* Remove all tunnel director rules and hash */
1368 if (tunnel_rule->hash_map)
1369 rte_free(tunnel_rule->hash_map);
1370 if (tunnel_rule->hash_table)
1371 rte_hash_free(tunnel_rule->hash_table);
1373 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1374 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1380 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1382 struct i40e_fdir_filter *p_fdir;
1383 struct i40e_fdir_info *fdir_info;
1385 fdir_info = &pf->fdir;
1386 /* Remove all flow director rules and hash */
1387 if (fdir_info->hash_map)
1388 rte_free(fdir_info->hash_map);
1389 if (fdir_info->hash_table)
1390 rte_hash_free(fdir_info->hash_table);
1392 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1393 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1399 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1402 struct rte_pci_device *pci_dev;
1403 struct rte_intr_handle *intr_handle;
1405 struct i40e_filter_control_settings settings;
1406 struct rte_flow *p_flow;
1408 uint8_t aq_fail = 0;
1410 PMD_INIT_FUNC_TRACE();
1412 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1415 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1418 intr_handle = &pci_dev->intr_handle;
1420 if (hw->adapter_stopped == 0)
1421 i40e_dev_close(dev);
1423 dev->dev_ops = NULL;
1424 dev->rx_pkt_burst = NULL;
1425 dev->tx_pkt_burst = NULL;
1427 /* Clear PXE mode */
1428 i40e_clear_pxe_mode(hw);
1430 /* Unconfigure filter control */
1431 memset(&settings, 0, sizeof(settings));
1432 ret = i40e_set_filter_control(hw, &settings);
1434 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1437 /* Disable flow control */
1438 hw->fc.requested_mode = I40E_FC_NONE;
1439 i40e_set_fc(hw, &aq_fail, TRUE);
1441 /* uninitialize pf host driver */
1442 i40e_pf_host_uninit(dev);
1444 rte_free(dev->data->mac_addrs);
1445 dev->data->mac_addrs = NULL;
1447 /* disable uio intr before callback unregister */
1448 rte_intr_disable(intr_handle);
1450 /* register callback func to eal lib */
1451 rte_intr_callback_unregister(intr_handle,
1452 i40e_dev_interrupt_handler, dev);
1454 i40e_rm_ethtype_filter_list(pf);
1455 i40e_rm_tunnel_filter_list(pf);
1456 i40e_rm_fdir_filter_list(pf);
1458 /* Remove all flows */
1459 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1460 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1464 /* Remove all Traffic Manager configuration */
1465 i40e_tm_conf_uninit(dev);
1471 i40e_dev_configure(struct rte_eth_dev *dev)
1473 struct i40e_adapter *ad =
1474 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1475 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1476 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1480 ret = i40e_dev_sync_phy_type(hw);
1484 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1485 * bulk allocation or vector Rx preconditions we will reset it.
1487 ad->rx_bulk_alloc_allowed = true;
1488 ad->rx_vec_allowed = true;
1489 ad->tx_simple_allowed = true;
1490 ad->tx_vec_allowed = true;
1492 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1493 ret = i40e_fdir_setup(pf);
1494 if (ret != I40E_SUCCESS) {
1495 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1498 ret = i40e_fdir_configure(dev);
1500 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1504 i40e_fdir_teardown(pf);
1506 ret = i40e_dev_init_vlan(dev);
1511 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1512 * RSS setting have different requirements.
1513 * General PMD driver call sequence are NIC init, configure,
1514 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1515 * will try to lookup the VSI that specific queue belongs to if VMDQ
1516 * applicable. So, VMDQ setting has to be done before
1517 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1518 * For RSS setting, it will try to calculate actual configured RX queue
1519 * number, which will be available after rx_queue_setup(). dev_start()
1520 * function is good to place RSS setup.
1522 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1523 ret = i40e_vmdq_setup(dev);
1528 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1529 ret = i40e_dcb_setup(dev);
1531 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1536 TAILQ_INIT(&pf->flow_list);
1541 /* need to release vmdq resource if exists */
1542 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1543 i40e_vsi_release(pf->vmdq[i].vsi);
1544 pf->vmdq[i].vsi = NULL;
1549 /* need to release fdir resource if exists */
1550 i40e_fdir_teardown(pf);
1555 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1557 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1558 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1559 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1560 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1561 uint16_t msix_vect = vsi->msix_intr;
1564 for (i = 0; i < vsi->nb_qps; i++) {
1565 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1566 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1570 if (vsi->type != I40E_VSI_SRIOV) {
1571 if (!rte_intr_allow_others(intr_handle)) {
1572 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1573 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1575 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1578 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1579 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1581 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1586 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1587 vsi->user_param + (msix_vect - 1);
1589 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1590 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1592 I40E_WRITE_FLUSH(hw);
1596 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1597 int base_queue, int nb_queue)
1601 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1603 /* Bind all RX queues to allocated MSIX interrupt */
1604 for (i = 0; i < nb_queue; i++) {
1605 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1606 I40E_QINT_RQCTL_ITR_INDX_MASK |
1607 ((base_queue + i + 1) <<
1608 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1609 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1610 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1612 if (i == nb_queue - 1)
1613 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1614 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1617 /* Write first RX queue to Link list register as the head element */
1618 if (vsi->type != I40E_VSI_SRIOV) {
1620 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1622 if (msix_vect == I40E_MISC_VEC_ID) {
1623 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1625 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1627 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1629 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1632 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1634 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1636 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1638 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1645 if (msix_vect == I40E_MISC_VEC_ID) {
1647 I40E_VPINT_LNKLST0(vsi->user_param),
1649 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1651 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1653 /* num_msix_vectors_vf needs to minus irq0 */
1654 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1655 vsi->user_param + (msix_vect - 1);
1657 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1659 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1661 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1665 I40E_WRITE_FLUSH(hw);
1669 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1671 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1672 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1673 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1674 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1675 uint16_t msix_vect = vsi->msix_intr;
1676 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1677 uint16_t queue_idx = 0;
1682 for (i = 0; i < vsi->nb_qps; i++) {
1683 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1684 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1687 /* INTENA flag is not auto-cleared for interrupt */
1688 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1689 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1690 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1691 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1692 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1694 /* VF bind interrupt */
1695 if (vsi->type == I40E_VSI_SRIOV) {
1696 __vsi_queues_bind_intr(vsi, msix_vect,
1697 vsi->base_queue, vsi->nb_qps);
1701 /* PF & VMDq bind interrupt */
1702 if (rte_intr_dp_is_en(intr_handle)) {
1703 if (vsi->type == I40E_VSI_MAIN) {
1706 } else if (vsi->type == I40E_VSI_VMDQ2) {
1707 struct i40e_vsi *main_vsi =
1708 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1709 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1714 for (i = 0; i < vsi->nb_used_qps; i++) {
1716 if (!rte_intr_allow_others(intr_handle))
1717 /* allow to share MISC_VEC_ID */
1718 msix_vect = I40E_MISC_VEC_ID;
1720 /* no enough msix_vect, map all to one */
1721 __vsi_queues_bind_intr(vsi, msix_vect,
1722 vsi->base_queue + i,
1723 vsi->nb_used_qps - i);
1724 for (; !!record && i < vsi->nb_used_qps; i++)
1725 intr_handle->intr_vec[queue_idx + i] =
1729 /* 1:1 queue/msix_vect mapping */
1730 __vsi_queues_bind_intr(vsi, msix_vect,
1731 vsi->base_queue + i, 1);
1733 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1741 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1743 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1744 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1745 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1746 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1747 uint16_t interval = i40e_calc_itr_interval(\
1748 RTE_LIBRTE_I40E_ITR_INTERVAL);
1749 uint16_t msix_intr, i;
1751 if (rte_intr_allow_others(intr_handle))
1752 for (i = 0; i < vsi->nb_msix; i++) {
1753 msix_intr = vsi->msix_intr + i;
1754 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1755 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1756 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1757 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1759 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1762 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1763 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1764 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1765 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1767 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1769 I40E_WRITE_FLUSH(hw);
1773 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1775 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1776 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1777 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1778 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779 uint16_t msix_intr, i;
1781 if (rte_intr_allow_others(intr_handle))
1782 for (i = 0; i < vsi->nb_msix; i++) {
1783 msix_intr = vsi->msix_intr + i;
1784 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1788 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1790 I40E_WRITE_FLUSH(hw);
1793 static inline uint8_t
1794 i40e_parse_link_speeds(uint16_t link_speeds)
1796 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1798 if (link_speeds & ETH_LINK_SPEED_40G)
1799 link_speed |= I40E_LINK_SPEED_40GB;
1800 if (link_speeds & ETH_LINK_SPEED_25G)
1801 link_speed |= I40E_LINK_SPEED_25GB;
1802 if (link_speeds & ETH_LINK_SPEED_20G)
1803 link_speed |= I40E_LINK_SPEED_20GB;
1804 if (link_speeds & ETH_LINK_SPEED_10G)
1805 link_speed |= I40E_LINK_SPEED_10GB;
1806 if (link_speeds & ETH_LINK_SPEED_1G)
1807 link_speed |= I40E_LINK_SPEED_1GB;
1808 if (link_speeds & ETH_LINK_SPEED_100M)
1809 link_speed |= I40E_LINK_SPEED_100MB;
1815 i40e_phy_conf_link(struct i40e_hw *hw,
1817 uint8_t force_speed)
1819 enum i40e_status_code status;
1820 struct i40e_aq_get_phy_abilities_resp phy_ab;
1821 struct i40e_aq_set_phy_config phy_conf;
1822 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1823 I40E_AQ_PHY_FLAG_PAUSE_RX |
1824 I40E_AQ_PHY_FLAG_PAUSE_RX |
1825 I40E_AQ_PHY_FLAG_LOW_POWER;
1826 const uint8_t advt = I40E_LINK_SPEED_40GB |
1827 I40E_LINK_SPEED_25GB |
1828 I40E_LINK_SPEED_10GB |
1829 I40E_LINK_SPEED_1GB |
1830 I40E_LINK_SPEED_100MB;
1834 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1839 memset(&phy_conf, 0, sizeof(phy_conf));
1841 /* bits 0-2 use the values from get_phy_abilities_resp */
1843 abilities |= phy_ab.abilities & mask;
1845 /* update ablities and speed */
1846 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1847 phy_conf.link_speed = advt;
1849 phy_conf.link_speed = force_speed;
1851 phy_conf.abilities = abilities;
1853 /* use get_phy_abilities_resp value for the rest */
1854 phy_conf.phy_type = phy_ab.phy_type;
1855 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1856 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1857 phy_conf.eee_capability = phy_ab.eee_capability;
1858 phy_conf.eeer = phy_ab.eeer_val;
1859 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1861 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1862 phy_ab.abilities, phy_ab.link_speed);
1863 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1864 phy_conf.abilities, phy_conf.link_speed);
1866 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1870 return I40E_SUCCESS;
1874 i40e_apply_link_speed(struct rte_eth_dev *dev)
1877 uint8_t abilities = 0;
1878 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879 struct rte_eth_conf *conf = &dev->data->dev_conf;
1881 speed = i40e_parse_link_speeds(conf->link_speeds);
1882 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1883 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1884 abilities |= I40E_AQ_PHY_AN_ENABLED;
1885 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1887 /* Skip changing speed on 40G interfaces, FW does not support */
1888 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1889 speed = I40E_LINK_SPEED_UNKNOWN;
1890 abilities |= I40E_AQ_PHY_AN_ENABLED;
1893 return i40e_phy_conf_link(hw, abilities, speed);
1897 i40e_dev_start(struct rte_eth_dev *dev)
1899 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1900 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901 struct i40e_vsi *main_vsi = pf->main_vsi;
1903 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1904 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1905 uint32_t intr_vector = 0;
1906 struct i40e_vsi *vsi;
1908 hw->adapter_stopped = 0;
1910 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1911 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1912 dev->data->port_id);
1916 rte_intr_disable(intr_handle);
1918 if ((rte_intr_cap_multiple(intr_handle) ||
1919 !RTE_ETH_DEV_SRIOV(dev).active) &&
1920 dev->data->dev_conf.intr_conf.rxq != 0) {
1921 intr_vector = dev->data->nb_rx_queues;
1922 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1927 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1928 intr_handle->intr_vec =
1929 rte_zmalloc("intr_vec",
1930 dev->data->nb_rx_queues * sizeof(int),
1932 if (!intr_handle->intr_vec) {
1934 "Failed to allocate %d rx_queues intr_vec",
1935 dev->data->nb_rx_queues);
1940 /* Initialize VSI */
1941 ret = i40e_dev_rxtx_init(pf);
1942 if (ret != I40E_SUCCESS) {
1943 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1947 /* Map queues with MSIX interrupt */
1948 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1949 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1950 i40e_vsi_queues_bind_intr(main_vsi);
1951 i40e_vsi_enable_queues_intr(main_vsi);
1953 /* Map VMDQ VSI queues with MSIX interrupt */
1954 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1955 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1956 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1957 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1960 /* enable FDIR MSIX interrupt */
1961 if (pf->fdir.fdir_vsi) {
1962 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1963 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1966 /* Enable all queues which have been configured */
1967 ret = i40e_dev_switch_queues(pf, TRUE);
1968 if (ret != I40E_SUCCESS) {
1969 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1973 /* Enable receiving broadcast packets */
1974 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1975 if (ret != I40E_SUCCESS)
1976 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1978 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1979 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1981 if (ret != I40E_SUCCESS)
1982 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1985 /* Enable the VLAN promiscuous mode. */
1987 for (i = 0; i < pf->vf_num; i++) {
1988 vsi = pf->vfs[i].vsi;
1989 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1994 /* Apply link configure */
1995 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1996 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1997 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1998 ETH_LINK_SPEED_40G)) {
1999 PMD_DRV_LOG(ERR, "Invalid link setting");
2002 ret = i40e_apply_link_speed(dev);
2003 if (I40E_SUCCESS != ret) {
2004 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2008 if (!rte_intr_allow_others(intr_handle)) {
2009 rte_intr_callback_unregister(intr_handle,
2010 i40e_dev_interrupt_handler,
2012 /* configure and enable device interrupt */
2013 i40e_pf_config_irq0(hw, FALSE);
2014 i40e_pf_enable_irq0(hw);
2016 if (dev->data->dev_conf.intr_conf.lsc != 0)
2018 "lsc won't enable because of no intr multiplex");
2020 ret = i40e_aq_set_phy_int_mask(hw,
2021 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2022 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2023 I40E_AQ_EVENT_MEDIA_NA), NULL);
2024 if (ret != I40E_SUCCESS)
2025 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2027 /* Call get_link_info aq commond to enable/disable LSE */
2028 i40e_dev_link_update(dev, 0);
2031 /* enable uio intr after callback register */
2032 rte_intr_enable(intr_handle);
2034 i40e_filter_restore(pf);
2036 if (!pf->tm_conf.committed)
2037 PMD_DRV_LOG(WARNING,
2038 "please call hierarchy_commit() "
2039 "before starting the port");
2041 return I40E_SUCCESS;
2044 i40e_dev_switch_queues(pf, FALSE);
2045 i40e_dev_clear_queues(dev);
2051 i40e_dev_stop(struct rte_eth_dev *dev)
2053 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2054 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055 struct i40e_vsi *main_vsi = pf->main_vsi;
2056 struct i40e_mirror_rule *p_mirror;
2057 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2058 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2061 if (hw->adapter_stopped == 1)
2063 /* Disable all queues */
2064 i40e_dev_switch_queues(pf, FALSE);
2066 /* un-map queues with interrupt registers */
2067 i40e_vsi_disable_queues_intr(main_vsi);
2068 i40e_vsi_queues_unbind_intr(main_vsi);
2070 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2071 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2072 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2075 if (pf->fdir.fdir_vsi) {
2076 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2077 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2079 /* Clear all queues and release memory */
2080 i40e_dev_clear_queues(dev);
2083 i40e_dev_set_link_down(dev);
2085 /* Remove all mirror rules */
2086 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2087 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2090 pf->nb_mirror_rule = 0;
2092 if (!rte_intr_allow_others(intr_handle))
2093 /* resume to the default handler */
2094 rte_intr_callback_register(intr_handle,
2095 i40e_dev_interrupt_handler,
2098 /* Clean datapath event and queue/vec mapping */
2099 rte_intr_efd_disable(intr_handle);
2100 if (intr_handle->intr_vec) {
2101 rte_free(intr_handle->intr_vec);
2102 intr_handle->intr_vec = NULL;
2105 /* reset hierarchy commit */
2106 pf->tm_conf.committed = false;
2108 hw->adapter_stopped = 1;
2112 i40e_dev_close(struct rte_eth_dev *dev)
2114 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2115 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2116 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2117 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2121 PMD_INIT_FUNC_TRACE();
2124 i40e_dev_free_queues(dev);
2126 /* Disable interrupt */
2127 i40e_pf_disable_irq0(hw);
2128 rte_intr_disable(intr_handle);
2130 /* shutdown and destroy the HMC */
2131 i40e_shutdown_lan_hmc(hw);
2133 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2134 i40e_vsi_release(pf->vmdq[i].vsi);
2135 pf->vmdq[i].vsi = NULL;
2140 /* release all the existing VSIs and VEBs */
2141 i40e_fdir_teardown(pf);
2142 i40e_vsi_release(pf->main_vsi);
2144 /* shutdown the adminq */
2145 i40e_aq_queue_shutdown(hw, true);
2146 i40e_shutdown_adminq(hw);
2148 i40e_res_pool_destroy(&pf->qp_pool);
2149 i40e_res_pool_destroy(&pf->msix_pool);
2151 /* force a PF reset to clean anything leftover */
2152 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2153 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2154 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2155 I40E_WRITE_FLUSH(hw);
2159 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2161 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2162 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163 struct i40e_vsi *vsi = pf->main_vsi;
2166 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2168 if (status != I40E_SUCCESS)
2169 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2171 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2173 if (status != I40E_SUCCESS)
2174 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2179 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2181 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2182 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183 struct i40e_vsi *vsi = pf->main_vsi;
2186 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2188 if (status != I40E_SUCCESS)
2189 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2191 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2193 if (status != I40E_SUCCESS)
2194 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2198 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2200 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2201 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202 struct i40e_vsi *vsi = pf->main_vsi;
2205 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2206 if (ret != I40E_SUCCESS)
2207 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2211 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2213 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2214 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2215 struct i40e_vsi *vsi = pf->main_vsi;
2218 if (dev->data->promiscuous == 1)
2219 return; /* must remain in all_multicast mode */
2221 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2222 vsi->seid, FALSE, NULL);
2223 if (ret != I40E_SUCCESS)
2224 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2228 * Set device link up.
2231 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2233 /* re-apply link speed setting */
2234 return i40e_apply_link_speed(dev);
2238 * Set device link down.
2241 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2243 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2244 uint8_t abilities = 0;
2245 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2247 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2248 return i40e_phy_conf_link(hw, abilities, speed);
2252 i40e_dev_link_update(struct rte_eth_dev *dev,
2253 int wait_to_complete)
2255 #define CHECK_INTERVAL 100 /* 100ms */
2256 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2257 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2258 struct i40e_link_status link_status;
2259 struct rte_eth_link link, old;
2261 unsigned rep_cnt = MAX_REPEAT_TIME;
2262 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2264 memset(&link, 0, sizeof(link));
2265 memset(&old, 0, sizeof(old));
2266 memset(&link_status, 0, sizeof(link_status));
2267 rte_i40e_dev_atomic_read_link_status(dev, &old);
2270 /* Get link status information from hardware */
2271 status = i40e_aq_get_link_info(hw, enable_lse,
2272 &link_status, NULL);
2273 if (status != I40E_SUCCESS) {
2274 link.link_speed = ETH_SPEED_NUM_100M;
2275 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2276 PMD_DRV_LOG(ERR, "Failed to get link info");
2280 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2281 if (!wait_to_complete || link.link_status)
2284 rte_delay_ms(CHECK_INTERVAL);
2285 } while (--rep_cnt);
2287 if (!link.link_status)
2290 /* i40e uses full duplex only */
2291 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2293 /* Parse the link status */
2294 switch (link_status.link_speed) {
2295 case I40E_LINK_SPEED_100MB:
2296 link.link_speed = ETH_SPEED_NUM_100M;
2298 case I40E_LINK_SPEED_1GB:
2299 link.link_speed = ETH_SPEED_NUM_1G;
2301 case I40E_LINK_SPEED_10GB:
2302 link.link_speed = ETH_SPEED_NUM_10G;
2304 case I40E_LINK_SPEED_20GB:
2305 link.link_speed = ETH_SPEED_NUM_20G;
2307 case I40E_LINK_SPEED_25GB:
2308 link.link_speed = ETH_SPEED_NUM_25G;
2310 case I40E_LINK_SPEED_40GB:
2311 link.link_speed = ETH_SPEED_NUM_40G;
2314 link.link_speed = ETH_SPEED_NUM_100M;
2318 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2319 ETH_LINK_SPEED_FIXED);
2322 rte_i40e_dev_atomic_write_link_status(dev, &link);
2323 if (link.link_status == old.link_status)
2326 i40e_notify_all_vfs_link_status(dev);
2331 /* Get all the statistics of a VSI */
2333 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2335 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2336 struct i40e_eth_stats *nes = &vsi->eth_stats;
2337 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2338 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2340 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2341 vsi->offset_loaded, &oes->rx_bytes,
2343 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2344 vsi->offset_loaded, &oes->rx_unicast,
2346 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2347 vsi->offset_loaded, &oes->rx_multicast,
2348 &nes->rx_multicast);
2349 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2350 vsi->offset_loaded, &oes->rx_broadcast,
2351 &nes->rx_broadcast);
2352 /* exclude CRC bytes */
2353 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2354 nes->rx_broadcast) * ETHER_CRC_LEN;
2356 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2357 &oes->rx_discards, &nes->rx_discards);
2358 /* GLV_REPC not supported */
2359 /* GLV_RMPC not supported */
2360 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2361 &oes->rx_unknown_protocol,
2362 &nes->rx_unknown_protocol);
2363 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2364 vsi->offset_loaded, &oes->tx_bytes,
2366 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2367 vsi->offset_loaded, &oes->tx_unicast,
2369 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2370 vsi->offset_loaded, &oes->tx_multicast,
2371 &nes->tx_multicast);
2372 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2373 vsi->offset_loaded, &oes->tx_broadcast,
2374 &nes->tx_broadcast);
2375 /* GLV_TDPC not supported */
2376 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2377 &oes->tx_errors, &nes->tx_errors);
2378 vsi->offset_loaded = true;
2380 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2382 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2383 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2384 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2385 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2386 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2387 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2388 nes->rx_unknown_protocol);
2389 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2390 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2391 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2392 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2393 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2394 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2395 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2400 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2403 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2404 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2406 /* Get rx/tx bytes of internal transfer packets */
2407 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2408 I40E_GLV_GORCL(hw->port),
2410 &pf->internal_stats_offset.rx_bytes,
2411 &pf->internal_stats.rx_bytes);
2413 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2414 I40E_GLV_GOTCL(hw->port),
2416 &pf->internal_stats_offset.tx_bytes,
2417 &pf->internal_stats.tx_bytes);
2418 /* Get total internal rx packet count */
2419 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2420 I40E_GLV_UPRCL(hw->port),
2422 &pf->internal_stats_offset.rx_unicast,
2423 &pf->internal_stats.rx_unicast);
2424 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2425 I40E_GLV_MPRCL(hw->port),
2427 &pf->internal_stats_offset.rx_multicast,
2428 &pf->internal_stats.rx_multicast);
2429 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2430 I40E_GLV_BPRCL(hw->port),
2432 &pf->internal_stats_offset.rx_broadcast,
2433 &pf->internal_stats.rx_broadcast);
2435 /* exclude CRC size */
2436 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2437 pf->internal_stats.rx_multicast +
2438 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2440 /* Get statistics of struct i40e_eth_stats */
2441 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2442 I40E_GLPRT_GORCL(hw->port),
2443 pf->offset_loaded, &os->eth.rx_bytes,
2445 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2446 I40E_GLPRT_UPRCL(hw->port),
2447 pf->offset_loaded, &os->eth.rx_unicast,
2448 &ns->eth.rx_unicast);
2449 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2450 I40E_GLPRT_MPRCL(hw->port),
2451 pf->offset_loaded, &os->eth.rx_multicast,
2452 &ns->eth.rx_multicast);
2453 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2454 I40E_GLPRT_BPRCL(hw->port),
2455 pf->offset_loaded, &os->eth.rx_broadcast,
2456 &ns->eth.rx_broadcast);
2457 /* Workaround: CRC size should not be included in byte statistics,
2458 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2460 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2461 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2463 /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2464 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2467 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2468 ns->eth.rx_bytes = 0;
2469 /* exlude internal rx bytes */
2471 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2473 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2474 pf->offset_loaded, &os->eth.rx_discards,
2475 &ns->eth.rx_discards);
2476 /* GLPRT_REPC not supported */
2477 /* GLPRT_RMPC not supported */
2478 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2480 &os->eth.rx_unknown_protocol,
2481 &ns->eth.rx_unknown_protocol);
2482 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2483 I40E_GLPRT_GOTCL(hw->port),
2484 pf->offset_loaded, &os->eth.tx_bytes,
2486 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2487 I40E_GLPRT_UPTCL(hw->port),
2488 pf->offset_loaded, &os->eth.tx_unicast,
2489 &ns->eth.tx_unicast);
2490 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2491 I40E_GLPRT_MPTCL(hw->port),
2492 pf->offset_loaded, &os->eth.tx_multicast,
2493 &ns->eth.tx_multicast);
2494 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2495 I40E_GLPRT_BPTCL(hw->port),
2496 pf->offset_loaded, &os->eth.tx_broadcast,
2497 &ns->eth.tx_broadcast);
2498 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2499 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2501 /* exclude internal tx bytes */
2502 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2503 ns->eth.tx_bytes = 0;
2505 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2507 /* GLPRT_TEPC not supported */
2509 /* additional port specific stats */
2510 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2511 pf->offset_loaded, &os->tx_dropped_link_down,
2512 &ns->tx_dropped_link_down);
2513 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2514 pf->offset_loaded, &os->crc_errors,
2516 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2517 pf->offset_loaded, &os->illegal_bytes,
2518 &ns->illegal_bytes);
2519 /* GLPRT_ERRBC not supported */
2520 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2521 pf->offset_loaded, &os->mac_local_faults,
2522 &ns->mac_local_faults);
2523 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2524 pf->offset_loaded, &os->mac_remote_faults,
2525 &ns->mac_remote_faults);
2526 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2527 pf->offset_loaded, &os->rx_length_errors,
2528 &ns->rx_length_errors);
2529 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2530 pf->offset_loaded, &os->link_xon_rx,
2532 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2533 pf->offset_loaded, &os->link_xoff_rx,
2535 for (i = 0; i < 8; i++) {
2536 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2538 &os->priority_xon_rx[i],
2539 &ns->priority_xon_rx[i]);
2540 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2542 &os->priority_xoff_rx[i],
2543 &ns->priority_xoff_rx[i]);
2545 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2546 pf->offset_loaded, &os->link_xon_tx,
2548 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2549 pf->offset_loaded, &os->link_xoff_tx,
2551 for (i = 0; i < 8; i++) {
2552 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2554 &os->priority_xon_tx[i],
2555 &ns->priority_xon_tx[i]);
2556 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2558 &os->priority_xoff_tx[i],
2559 &ns->priority_xoff_tx[i]);
2560 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2562 &os->priority_xon_2_xoff[i],
2563 &ns->priority_xon_2_xoff[i]);
2565 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2566 I40E_GLPRT_PRC64L(hw->port),
2567 pf->offset_loaded, &os->rx_size_64,
2569 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2570 I40E_GLPRT_PRC127L(hw->port),
2571 pf->offset_loaded, &os->rx_size_127,
2573 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2574 I40E_GLPRT_PRC255L(hw->port),
2575 pf->offset_loaded, &os->rx_size_255,
2577 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2578 I40E_GLPRT_PRC511L(hw->port),
2579 pf->offset_loaded, &os->rx_size_511,
2581 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2582 I40E_GLPRT_PRC1023L(hw->port),
2583 pf->offset_loaded, &os->rx_size_1023,
2585 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2586 I40E_GLPRT_PRC1522L(hw->port),
2587 pf->offset_loaded, &os->rx_size_1522,
2589 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2590 I40E_GLPRT_PRC9522L(hw->port),
2591 pf->offset_loaded, &os->rx_size_big,
2593 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2594 pf->offset_loaded, &os->rx_undersize,
2596 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2597 pf->offset_loaded, &os->rx_fragments,
2599 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2600 pf->offset_loaded, &os->rx_oversize,
2602 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2603 pf->offset_loaded, &os->rx_jabber,
2605 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2606 I40E_GLPRT_PTC64L(hw->port),
2607 pf->offset_loaded, &os->tx_size_64,
2609 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2610 I40E_GLPRT_PTC127L(hw->port),
2611 pf->offset_loaded, &os->tx_size_127,
2613 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2614 I40E_GLPRT_PTC255L(hw->port),
2615 pf->offset_loaded, &os->tx_size_255,
2617 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2618 I40E_GLPRT_PTC511L(hw->port),
2619 pf->offset_loaded, &os->tx_size_511,
2621 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2622 I40E_GLPRT_PTC1023L(hw->port),
2623 pf->offset_loaded, &os->tx_size_1023,
2625 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2626 I40E_GLPRT_PTC1522L(hw->port),
2627 pf->offset_loaded, &os->tx_size_1522,
2629 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2630 I40E_GLPRT_PTC9522L(hw->port),
2631 pf->offset_loaded, &os->tx_size_big,
2633 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2635 &os->fd_sb_match, &ns->fd_sb_match);
2636 /* GLPRT_MSPDC not supported */
2637 /* GLPRT_XEC not supported */
2639 pf->offset_loaded = true;
2642 i40e_update_vsi_stats(pf->main_vsi);
2645 /* Get all statistics of a port */
2647 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2649 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2650 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2651 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2654 /* call read registers - updates values, now write them to struct */
2655 i40e_read_stats_registers(pf, hw);
2657 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2658 pf->main_vsi->eth_stats.rx_multicast +
2659 pf->main_vsi->eth_stats.rx_broadcast -
2660 pf->main_vsi->eth_stats.rx_discards;
2661 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2662 pf->main_vsi->eth_stats.tx_multicast +
2663 pf->main_vsi->eth_stats.tx_broadcast;
2664 stats->ibytes = ns->eth.rx_bytes;
2665 stats->obytes = ns->eth.tx_bytes;
2666 stats->oerrors = ns->eth.tx_errors +
2667 pf->main_vsi->eth_stats.tx_errors;
2670 stats->imissed = ns->eth.rx_discards +
2671 pf->main_vsi->eth_stats.rx_discards;
2672 stats->ierrors = ns->crc_errors +
2673 ns->rx_length_errors + ns->rx_undersize +
2674 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2676 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2677 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2678 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2679 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2680 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2681 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2682 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2683 ns->eth.rx_unknown_protocol);
2684 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2685 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2686 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2687 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2688 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2689 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2691 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2692 ns->tx_dropped_link_down);
2693 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2694 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2696 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2697 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2698 ns->mac_local_faults);
2699 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2700 ns->mac_remote_faults);
2701 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2702 ns->rx_length_errors);
2703 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2704 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2705 for (i = 0; i < 8; i++) {
2706 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2707 i, ns->priority_xon_rx[i]);
2708 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2709 i, ns->priority_xoff_rx[i]);
2711 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2712 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2713 for (i = 0; i < 8; i++) {
2714 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2715 i, ns->priority_xon_tx[i]);
2716 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2717 i, ns->priority_xoff_tx[i]);
2718 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2719 i, ns->priority_xon_2_xoff[i]);
2721 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2722 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2723 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2724 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2725 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2726 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2727 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2728 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2729 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2730 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2731 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2732 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2733 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2734 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2735 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2736 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2737 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2738 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2739 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2740 ns->mac_short_packet_dropped);
2741 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2742 ns->checksum_error);
2743 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2744 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2747 /* Reset the statistics */
2749 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2751 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2752 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2754 /* Mark PF and VSI stats to update the offset, aka "reset" */
2755 pf->offset_loaded = false;
2757 pf->main_vsi->offset_loaded = false;
2759 /* read the stats, reading current register values into offset */
2760 i40e_read_stats_registers(pf, hw);
2764 i40e_xstats_calc_num(void)
2766 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2767 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2768 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2771 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2772 struct rte_eth_xstat_name *xstats_names,
2773 __rte_unused unsigned limit)
2778 if (xstats_names == NULL)
2779 return i40e_xstats_calc_num();
2781 /* Note: limit checked in rte_eth_xstats_names() */
2783 /* Get stats from i40e_eth_stats struct */
2784 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2785 snprintf(xstats_names[count].name,
2786 sizeof(xstats_names[count].name),
2787 "%s", rte_i40e_stats_strings[i].name);
2791 /* Get individiual stats from i40e_hw_port struct */
2792 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2793 snprintf(xstats_names[count].name,
2794 sizeof(xstats_names[count].name),
2795 "%s", rte_i40e_hw_port_strings[i].name);
2799 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2800 for (prio = 0; prio < 8; prio++) {
2801 snprintf(xstats_names[count].name,
2802 sizeof(xstats_names[count].name),
2803 "rx_priority%u_%s", prio,
2804 rte_i40e_rxq_prio_strings[i].name);
2809 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2810 for (prio = 0; prio < 8; prio++) {
2811 snprintf(xstats_names[count].name,
2812 sizeof(xstats_names[count].name),
2813 "tx_priority%u_%s", prio,
2814 rte_i40e_txq_prio_strings[i].name);
2822 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2825 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2826 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2827 unsigned i, count, prio;
2828 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2830 count = i40e_xstats_calc_num();
2834 i40e_read_stats_registers(pf, hw);
2841 /* Get stats from i40e_eth_stats struct */
2842 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2843 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2844 rte_i40e_stats_strings[i].offset);
2845 xstats[count].id = count;
2849 /* Get individiual stats from i40e_hw_port struct */
2850 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2851 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2852 rte_i40e_hw_port_strings[i].offset);
2853 xstats[count].id = count;
2857 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2858 for (prio = 0; prio < 8; prio++) {
2859 xstats[count].value =
2860 *(uint64_t *)(((char *)hw_stats) +
2861 rte_i40e_rxq_prio_strings[i].offset +
2862 (sizeof(uint64_t) * prio));
2863 xstats[count].id = count;
2868 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2869 for (prio = 0; prio < 8; prio++) {
2870 xstats[count].value =
2871 *(uint64_t *)(((char *)hw_stats) +
2872 rte_i40e_txq_prio_strings[i].offset +
2873 (sizeof(uint64_t) * prio));
2874 xstats[count].id = count;
2883 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2884 __rte_unused uint16_t queue_id,
2885 __rte_unused uint8_t stat_idx,
2886 __rte_unused uint8_t is_rx)
2888 PMD_INIT_FUNC_TRACE();
2894 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2896 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2902 full_ver = hw->nvm.oem_ver;
2903 ver = (u8)(full_ver >> 24);
2904 build = (u16)((full_ver >> 8) & 0xffff);
2905 patch = (u8)(full_ver & 0xff);
2907 ret = snprintf(fw_version, fw_size,
2908 "%d.%d%d 0x%08x %d.%d.%d",
2909 ((hw->nvm.version >> 12) & 0xf),
2910 ((hw->nvm.version >> 4) & 0xff),
2911 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2914 ret += 1; /* add the size of '\0' */
2915 if (fw_size < (u32)ret)
2922 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2924 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2925 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2926 struct i40e_vsi *vsi = pf->main_vsi;
2927 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2929 dev_info->pci_dev = pci_dev;
2930 dev_info->max_rx_queues = vsi->nb_qps;
2931 dev_info->max_tx_queues = vsi->nb_qps;
2932 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2933 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2934 dev_info->max_mac_addrs = vsi->max_macaddrs;
2935 dev_info->max_vfs = pci_dev->max_vfs;
2936 dev_info->rx_offload_capa =
2937 DEV_RX_OFFLOAD_VLAN_STRIP |
2938 DEV_RX_OFFLOAD_QINQ_STRIP |
2939 DEV_RX_OFFLOAD_IPV4_CKSUM |
2940 DEV_RX_OFFLOAD_UDP_CKSUM |
2941 DEV_RX_OFFLOAD_TCP_CKSUM;
2942 dev_info->tx_offload_capa =
2943 DEV_TX_OFFLOAD_VLAN_INSERT |
2944 DEV_TX_OFFLOAD_QINQ_INSERT |
2945 DEV_TX_OFFLOAD_IPV4_CKSUM |
2946 DEV_TX_OFFLOAD_UDP_CKSUM |
2947 DEV_TX_OFFLOAD_TCP_CKSUM |
2948 DEV_TX_OFFLOAD_SCTP_CKSUM |
2949 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2950 DEV_TX_OFFLOAD_TCP_TSO |
2951 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2952 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2953 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2954 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2955 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2957 dev_info->reta_size = pf->hash_lut_size;
2958 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2960 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2962 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2963 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2964 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2966 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2970 dev_info->default_txconf = (struct rte_eth_txconf) {
2972 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2973 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2974 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2976 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2977 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2978 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2979 ETH_TXQ_FLAGS_NOOFFLOADS,
2982 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2983 .nb_max = I40E_MAX_RING_DESC,
2984 .nb_min = I40E_MIN_RING_DESC,
2985 .nb_align = I40E_ALIGN_RING_DESC,
2988 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2989 .nb_max = I40E_MAX_RING_DESC,
2990 .nb_min = I40E_MIN_RING_DESC,
2991 .nb_align = I40E_ALIGN_RING_DESC,
2992 .nb_seg_max = I40E_TX_MAX_SEG,
2993 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2996 if (pf->flags & I40E_FLAG_VMDQ) {
2997 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2998 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2999 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3000 pf->max_nb_vmdq_vsi;
3001 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3002 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3003 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3006 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3008 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3009 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3011 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3014 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3018 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3020 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3021 struct i40e_vsi *vsi = pf->main_vsi;
3022 PMD_INIT_FUNC_TRACE();
3025 return i40e_vsi_add_vlan(vsi, vlan_id);
3027 return i40e_vsi_delete_vlan(vsi, vlan_id);
3031 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3032 enum rte_vlan_type vlan_type,
3033 uint16_t tpid, int qinq)
3035 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3038 uint16_t reg_id = 3;
3042 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3046 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3048 if (ret != I40E_SUCCESS) {
3050 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3055 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3058 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3059 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3060 if (reg_r == reg_w) {
3061 PMD_DRV_LOG(DEBUG, "No need to write");
3065 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3067 if (ret != I40E_SUCCESS) {
3069 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3074 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3081 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3082 enum rte_vlan_type vlan_type,
3085 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3086 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3089 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3090 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3091 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3093 "Unsupported vlan type.");
3096 /* 802.1ad frames ability is added in NVM API 1.7*/
3097 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3099 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3100 hw->first_tag = rte_cpu_to_le_16(tpid);
3101 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3102 hw->second_tag = rte_cpu_to_le_16(tpid);
3104 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3105 hw->second_tag = rte_cpu_to_le_16(tpid);
3107 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3108 if (ret != I40E_SUCCESS) {
3110 "Set switch config failed aq_err: %d",
3111 hw->aq.asq_last_status);
3115 /* If NVM API < 1.7, keep the register setting */
3116 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3123 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3125 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3126 struct i40e_vsi *vsi = pf->main_vsi;
3128 if (mask & ETH_VLAN_FILTER_MASK) {
3129 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3130 i40e_vsi_config_vlan_filter(vsi, TRUE);
3132 i40e_vsi_config_vlan_filter(vsi, FALSE);
3135 if (mask & ETH_VLAN_STRIP_MASK) {
3136 /* Enable or disable VLAN stripping */
3137 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3138 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3140 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3143 if (mask & ETH_VLAN_EXTEND_MASK) {
3144 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3145 i40e_vsi_config_double_vlan(vsi, TRUE);
3146 /* Set global registers with default ethertype. */
3147 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3149 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3153 i40e_vsi_config_double_vlan(vsi, FALSE);
3158 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3159 __rte_unused uint16_t queue,
3160 __rte_unused int on)
3162 PMD_INIT_FUNC_TRACE();
3166 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3168 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3169 struct i40e_vsi *vsi = pf->main_vsi;
3170 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3171 struct i40e_vsi_vlan_pvid_info info;
3173 memset(&info, 0, sizeof(info));
3176 info.config.pvid = pvid;
3178 info.config.reject.tagged =
3179 data->dev_conf.txmode.hw_vlan_reject_tagged;
3180 info.config.reject.untagged =
3181 data->dev_conf.txmode.hw_vlan_reject_untagged;
3184 return i40e_vsi_vlan_pvid_set(vsi, &info);
3188 i40e_dev_led_on(struct rte_eth_dev *dev)
3190 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3191 uint32_t mode = i40e_led_get(hw);
3194 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3200 i40e_dev_led_off(struct rte_eth_dev *dev)
3202 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3203 uint32_t mode = i40e_led_get(hw);
3206 i40e_led_set(hw, 0, false);
3212 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3214 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3215 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3217 fc_conf->pause_time = pf->fc_conf.pause_time;
3218 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3219 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3221 /* Return current mode according to actual setting*/
3222 switch (hw->fc.current_mode) {
3224 fc_conf->mode = RTE_FC_FULL;
3226 case I40E_FC_TX_PAUSE:
3227 fc_conf->mode = RTE_FC_TX_PAUSE;
3229 case I40E_FC_RX_PAUSE:
3230 fc_conf->mode = RTE_FC_RX_PAUSE;
3234 fc_conf->mode = RTE_FC_NONE;
3241 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3243 uint32_t mflcn_reg, fctrl_reg, reg;
3244 uint32_t max_high_water;
3245 uint8_t i, aq_failure;
3249 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3250 [RTE_FC_NONE] = I40E_FC_NONE,
3251 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3252 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3253 [RTE_FC_FULL] = I40E_FC_FULL
3256 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3258 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3259 if ((fc_conf->high_water > max_high_water) ||
3260 (fc_conf->high_water < fc_conf->low_water)) {
3262 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3267 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3268 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3269 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3271 pf->fc_conf.pause_time = fc_conf->pause_time;
3272 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3273 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3275 PMD_INIT_FUNC_TRACE();
3277 /* All the link flow control related enable/disable register
3278 * configuration is handle by the F/W
3280 err = i40e_set_fc(hw, &aq_failure, true);
3284 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3285 /* Configure flow control refresh threshold,
3286 * the value for stat_tx_pause_refresh_timer[8]
3287 * is used for global pause operation.
3291 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3292 pf->fc_conf.pause_time);
3294 /* configure the timer value included in transmitted pause
3296 * the value for stat_tx_pause_quanta[8] is used for global
3299 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3300 pf->fc_conf.pause_time);
3302 fctrl_reg = I40E_READ_REG(hw,
3303 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3305 if (fc_conf->mac_ctrl_frame_fwd != 0)
3306 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3308 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3310 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3313 /* Configure pause time (2 TCs per register) */
3314 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3315 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3316 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3318 /* Configure flow control refresh threshold value */
3319 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3320 pf->fc_conf.pause_time / 2);
3322 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3324 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3325 *depending on configuration
3327 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3328 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3329 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3331 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3332 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3335 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3338 /* config the water marker both based on the packets and bytes */
3339 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3340 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3341 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3342 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3343 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3344 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3345 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3346 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3348 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3349 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3352 I40E_WRITE_FLUSH(hw);
3358 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3359 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3361 PMD_INIT_FUNC_TRACE();
3366 /* Add a MAC address, and update filters */
3368 i40e_macaddr_add(struct rte_eth_dev *dev,
3369 struct ether_addr *mac_addr,
3370 __rte_unused uint32_t index,
3373 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3374 struct i40e_mac_filter_info mac_filter;
3375 struct i40e_vsi *vsi;
3378 /* If VMDQ not enabled or configured, return */
3379 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3380 !pf->nb_cfg_vmdq_vsi)) {
3381 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3382 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3387 if (pool > pf->nb_cfg_vmdq_vsi) {
3388 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3389 pool, pf->nb_cfg_vmdq_vsi);
3393 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3394 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3395 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3397 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3402 vsi = pf->vmdq[pool - 1].vsi;
3404 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3405 if (ret != I40E_SUCCESS) {
3406 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3412 /* Remove a MAC address, and update filters */
3414 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3416 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3417 struct i40e_vsi *vsi;
3418 struct rte_eth_dev_data *data = dev->data;
3419 struct ether_addr *macaddr;
3424 macaddr = &(data->mac_addrs[index]);
3426 pool_sel = dev->data->mac_pool_sel[index];
3428 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3429 if (pool_sel & (1ULL << i)) {
3433 /* No VMDQ pool enabled or configured */
3434 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3435 (i > pf->nb_cfg_vmdq_vsi)) {
3437 "No VMDQ pool enabled/configured");
3440 vsi = pf->vmdq[i - 1].vsi;
3442 ret = i40e_vsi_delete_mac(vsi, macaddr);
3445 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3452 /* Set perfect match or hash match of MAC and VLAN for a VF */
3454 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3455 struct rte_eth_mac_filter *filter,
3459 struct i40e_mac_filter_info mac_filter;
3460 struct ether_addr old_mac;
3461 struct ether_addr *new_mac;
3462 struct i40e_pf_vf *vf = NULL;
3467 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3470 hw = I40E_PF_TO_HW(pf);
3472 if (filter == NULL) {
3473 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3477 new_mac = &filter->mac_addr;
3479 if (is_zero_ether_addr(new_mac)) {
3480 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3484 vf_id = filter->dst_id;
3486 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3487 PMD_DRV_LOG(ERR, "Invalid argument.");
3490 vf = &pf->vfs[vf_id];
3492 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3493 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3498 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3499 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3501 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3504 mac_filter.filter_type = filter->filter_type;
3505 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3506 if (ret != I40E_SUCCESS) {
3507 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3510 ether_addr_copy(new_mac, &pf->dev_addr);
3512 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3514 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3515 if (ret != I40E_SUCCESS) {
3516 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3520 /* Clear device address as it has been removed */
3521 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3522 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3528 /* MAC filter handle */
3530 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3533 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3534 struct rte_eth_mac_filter *filter;
3535 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3536 int ret = I40E_NOT_SUPPORTED;
3538 filter = (struct rte_eth_mac_filter *)(arg);
3540 switch (filter_op) {
3541 case RTE_ETH_FILTER_NOP:
3544 case RTE_ETH_FILTER_ADD:
3545 i40e_pf_disable_irq0(hw);
3547 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3548 i40e_pf_enable_irq0(hw);
3550 case RTE_ETH_FILTER_DELETE:
3551 i40e_pf_disable_irq0(hw);
3553 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3554 i40e_pf_enable_irq0(hw);
3557 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3558 ret = I40E_ERR_PARAM;
3566 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3568 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3569 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3575 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3576 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3579 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3583 uint32_t *lut_dw = (uint32_t *)lut;
3584 uint16_t i, lut_size_dw = lut_size / 4;
3586 for (i = 0; i < lut_size_dw; i++)
3587 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3594 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3603 pf = I40E_VSI_TO_PF(vsi);
3604 hw = I40E_VSI_TO_HW(vsi);
3606 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3607 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3610 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3614 uint32_t *lut_dw = (uint32_t *)lut;
3615 uint16_t i, lut_size_dw = lut_size / 4;
3617 for (i = 0; i < lut_size_dw; i++)
3618 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3619 I40E_WRITE_FLUSH(hw);
3626 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3627 struct rte_eth_rss_reta_entry64 *reta_conf,
3630 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3631 uint16_t i, lut_size = pf->hash_lut_size;
3632 uint16_t idx, shift;
3636 if (reta_size != lut_size ||
3637 reta_size > ETH_RSS_RETA_SIZE_512) {
3639 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3640 reta_size, lut_size);
3644 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3646 PMD_DRV_LOG(ERR, "No memory can be allocated");
3649 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3652 for (i = 0; i < reta_size; i++) {
3653 idx = i / RTE_RETA_GROUP_SIZE;
3654 shift = i % RTE_RETA_GROUP_SIZE;
3655 if (reta_conf[idx].mask & (1ULL << shift))
3656 lut[i] = reta_conf[idx].reta[shift];
3658 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3667 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3668 struct rte_eth_rss_reta_entry64 *reta_conf,
3671 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3672 uint16_t i, lut_size = pf->hash_lut_size;
3673 uint16_t idx, shift;
3677 if (reta_size != lut_size ||
3678 reta_size > ETH_RSS_RETA_SIZE_512) {
3680 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3681 reta_size, lut_size);
3685 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3687 PMD_DRV_LOG(ERR, "No memory can be allocated");
3691 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3694 for (i = 0; i < reta_size; i++) {
3695 idx = i / RTE_RETA_GROUP_SIZE;
3696 shift = i % RTE_RETA_GROUP_SIZE;
3697 if (reta_conf[idx].mask & (1ULL << shift))
3698 reta_conf[idx].reta[shift] = lut[i];
3708 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3709 * @hw: pointer to the HW structure
3710 * @mem: pointer to mem struct to fill out
3711 * @size: size of memory requested
3712 * @alignment: what to align the allocation to
3714 enum i40e_status_code
3715 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3716 struct i40e_dma_mem *mem,
3720 const struct rte_memzone *mz = NULL;
3721 char z_name[RTE_MEMZONE_NAMESIZE];
3724 return I40E_ERR_PARAM;
3726 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3727 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3728 alignment, RTE_PGSIZE_2M);
3730 return I40E_ERR_NO_MEMORY;
3734 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3735 mem->zone = (const void *)mz;
3737 "memzone %s allocated with physical address: %"PRIu64,
3740 return I40E_SUCCESS;
3744 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3745 * @hw: pointer to the HW structure
3746 * @mem: ptr to mem struct to free
3748 enum i40e_status_code
3749 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3750 struct i40e_dma_mem *mem)
3753 return I40E_ERR_PARAM;
3756 "memzone %s to be freed with physical address: %"PRIu64,
3757 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3758 rte_memzone_free((const struct rte_memzone *)mem->zone);
3763 return I40E_SUCCESS;
3767 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3768 * @hw: pointer to the HW structure
3769 * @mem: pointer to mem struct to fill out
3770 * @size: size of memory requested
3772 enum i40e_status_code
3773 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3774 struct i40e_virt_mem *mem,
3778 return I40E_ERR_PARAM;
3781 mem->va = rte_zmalloc("i40e", size, 0);
3784 return I40E_SUCCESS;
3786 return I40E_ERR_NO_MEMORY;
3790 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3791 * @hw: pointer to the HW structure
3792 * @mem: pointer to mem struct to free
3794 enum i40e_status_code
3795 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3796 struct i40e_virt_mem *mem)
3799 return I40E_ERR_PARAM;
3804 return I40E_SUCCESS;
3808 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3810 rte_spinlock_init(&sp->spinlock);
3814 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3816 rte_spinlock_lock(&sp->spinlock);
3820 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3822 rte_spinlock_unlock(&sp->spinlock);
3826 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3832 * Get the hardware capabilities, which will be parsed
3833 * and saved into struct i40e_hw.
3836 i40e_get_cap(struct i40e_hw *hw)
3838 struct i40e_aqc_list_capabilities_element_resp *buf;
3839 uint16_t len, size = 0;
3842 /* Calculate a huge enough buff for saving response data temporarily */
3843 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3844 I40E_MAX_CAP_ELE_NUM;
3845 buf = rte_zmalloc("i40e", len, 0);
3847 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3848 return I40E_ERR_NO_MEMORY;
3851 /* Get, parse the capabilities and save it to hw */
3852 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3853 i40e_aqc_opc_list_func_capabilities, NULL);
3854 if (ret != I40E_SUCCESS)
3855 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3857 /* Free the temporary buffer after being used */
3864 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3866 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3867 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3868 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3869 uint16_t qp_count = 0, vsi_count = 0;
3871 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3872 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3875 /* Add the parameter init for LFC */
3876 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3877 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3878 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3880 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3881 pf->max_num_vsi = hw->func_caps.num_vsis;
3882 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3883 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3884 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3886 /* FDir queue/VSI allocation */
3887 pf->fdir_qp_offset = 0;
3888 if (hw->func_caps.fd) {
3889 pf->flags |= I40E_FLAG_FDIR;
3890 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3892 pf->fdir_nb_qps = 0;
3894 qp_count += pf->fdir_nb_qps;
3897 /* LAN queue/VSI allocation */
3898 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3899 if (!hw->func_caps.rss) {
3902 pf->flags |= I40E_FLAG_RSS;
3903 if (hw->mac.type == I40E_MAC_X722)
3904 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3905 pf->lan_nb_qps = pf->lan_nb_qp_max;
3907 qp_count += pf->lan_nb_qps;
3910 /* VF queue/VSI allocation */
3911 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3912 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3913 pf->flags |= I40E_FLAG_SRIOV;
3914 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3915 pf->vf_num = pci_dev->max_vfs;
3917 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3918 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3923 qp_count += pf->vf_nb_qps * pf->vf_num;
3924 vsi_count += pf->vf_num;
3926 /* VMDq queue/VSI allocation */
3927 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3928 pf->vmdq_nb_qps = 0;
3929 pf->max_nb_vmdq_vsi = 0;
3930 if (hw->func_caps.vmdq) {
3931 if (qp_count < hw->func_caps.num_tx_qp &&
3932 vsi_count < hw->func_caps.num_vsis) {
3933 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3934 qp_count) / pf->vmdq_nb_qp_max;
3936 /* Limit the maximum number of VMDq vsi to the maximum
3937 * ethdev can support
3939 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3940 hw->func_caps.num_vsis - vsi_count);
3941 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3943 if (pf->max_nb_vmdq_vsi) {
3944 pf->flags |= I40E_FLAG_VMDQ;
3945 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3947 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3948 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3949 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3952 "No enough queues left for VMDq");
3955 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3958 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3959 vsi_count += pf->max_nb_vmdq_vsi;
3961 if (hw->func_caps.dcb)
3962 pf->flags |= I40E_FLAG_DCB;
3964 if (qp_count > hw->func_caps.num_tx_qp) {
3966 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3967 qp_count, hw->func_caps.num_tx_qp);
3970 if (vsi_count > hw->func_caps.num_vsis) {
3972 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3973 vsi_count, hw->func_caps.num_vsis);
3981 i40e_pf_get_switch_config(struct i40e_pf *pf)
3983 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3984 struct i40e_aqc_get_switch_config_resp *switch_config;
3985 struct i40e_aqc_switch_config_element_resp *element;
3986 uint16_t start_seid = 0, num_reported;
3989 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3990 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3991 if (!switch_config) {
3992 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3996 /* Get the switch configurations */
3997 ret = i40e_aq_get_switch_config(hw, switch_config,
3998 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3999 if (ret != I40E_SUCCESS) {
4000 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4003 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4004 if (num_reported != 1) { /* The number should be 1 */
4005 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4009 /* Parse the switch configuration elements */
4010 element = &(switch_config->element[0]);
4011 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4012 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4013 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4015 PMD_DRV_LOG(INFO, "Unknown element type");
4018 rte_free(switch_config);
4024 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4027 struct pool_entry *entry;
4029 if (pool == NULL || num == 0)
4032 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4033 if (entry == NULL) {
4034 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4038 /* queue heap initialize */
4039 pool->num_free = num;
4040 pool->num_alloc = 0;
4042 LIST_INIT(&pool->alloc_list);
4043 LIST_INIT(&pool->free_list);
4045 /* Initialize element */
4049 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4054 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4056 struct pool_entry *entry, *next_entry;
4061 for (entry = LIST_FIRST(&pool->alloc_list);
4062 entry && (next_entry = LIST_NEXT(entry, next), 1);
4063 entry = next_entry) {
4064 LIST_REMOVE(entry, next);
4068 for (entry = LIST_FIRST(&pool->free_list);
4069 entry && (next_entry = LIST_NEXT(entry, next), 1);
4070 entry = next_entry) {
4071 LIST_REMOVE(entry, next);
4076 pool->num_alloc = 0;
4078 LIST_INIT(&pool->alloc_list);
4079 LIST_INIT(&pool->free_list);
4083 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4086 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4087 uint32_t pool_offset;
4091 PMD_DRV_LOG(ERR, "Invalid parameter");
4095 pool_offset = base - pool->base;
4096 /* Lookup in alloc list */
4097 LIST_FOREACH(entry, &pool->alloc_list, next) {
4098 if (entry->base == pool_offset) {
4099 valid_entry = entry;
4100 LIST_REMOVE(entry, next);
4105 /* Not find, return */
4106 if (valid_entry == NULL) {
4107 PMD_DRV_LOG(ERR, "Failed to find entry");
4112 * Found it, move it to free list and try to merge.
4113 * In order to make merge easier, always sort it by qbase.
4114 * Find adjacent prev and last entries.
4117 LIST_FOREACH(entry, &pool->free_list, next) {
4118 if (entry->base > valid_entry->base) {
4126 /* Try to merge with next one*/
4128 /* Merge with next one */
4129 if (valid_entry->base + valid_entry->len == next->base) {
4130 next->base = valid_entry->base;
4131 next->len += valid_entry->len;
4132 rte_free(valid_entry);
4139 /* Merge with previous one */
4140 if (prev->base + prev->len == valid_entry->base) {
4141 prev->len += valid_entry->len;
4142 /* If it merge with next one, remove next node */
4144 LIST_REMOVE(valid_entry, next);
4145 rte_free(valid_entry);
4147 rte_free(valid_entry);
4153 /* Not find any entry to merge, insert */
4156 LIST_INSERT_AFTER(prev, valid_entry, next);
4157 else if (next != NULL)
4158 LIST_INSERT_BEFORE(next, valid_entry, next);
4159 else /* It's empty list, insert to head */
4160 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4163 pool->num_free += valid_entry->len;
4164 pool->num_alloc -= valid_entry->len;
4170 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4173 struct pool_entry *entry, *valid_entry;
4175 if (pool == NULL || num == 0) {
4176 PMD_DRV_LOG(ERR, "Invalid parameter");
4180 if (pool->num_free < num) {
4181 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4182 num, pool->num_free);
4187 /* Lookup in free list and find most fit one */
4188 LIST_FOREACH(entry, &pool->free_list, next) {
4189 if (entry->len >= num) {
4191 if (entry->len == num) {
4192 valid_entry = entry;
4195 if (valid_entry == NULL || valid_entry->len > entry->len)
4196 valid_entry = entry;
4200 /* Not find one to satisfy the request, return */
4201 if (valid_entry == NULL) {
4202 PMD_DRV_LOG(ERR, "No valid entry found");
4206 * The entry have equal queue number as requested,
4207 * remove it from alloc_list.
4209 if (valid_entry->len == num) {
4210 LIST_REMOVE(valid_entry, next);
4213 * The entry have more numbers than requested,
4214 * create a new entry for alloc_list and minus its
4215 * queue base and number in free_list.
4217 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4218 if (entry == NULL) {
4220 "Failed to allocate memory for resource pool");
4223 entry->base = valid_entry->base;
4225 valid_entry->base += num;
4226 valid_entry->len -= num;
4227 valid_entry = entry;
4230 /* Insert it into alloc list, not sorted */
4231 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4233 pool->num_free -= valid_entry->len;
4234 pool->num_alloc += valid_entry->len;
4236 return valid_entry->base + pool->base;
4240 * bitmap_is_subset - Check whether src2 is subset of src1
4243 bitmap_is_subset(uint8_t src1, uint8_t src2)
4245 return !((src1 ^ src2) & src2);
4248 static enum i40e_status_code
4249 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4251 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4253 /* If DCB is not supported, only default TC is supported */
4254 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4255 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4256 return I40E_NOT_SUPPORTED;
4259 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4261 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4262 hw->func_caps.enabled_tcmap, enabled_tcmap);
4263 return I40E_NOT_SUPPORTED;
4265 return I40E_SUCCESS;
4269 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4270 struct i40e_vsi_vlan_pvid_info *info)
4273 struct i40e_vsi_context ctxt;
4274 uint8_t vlan_flags = 0;
4277 if (vsi == NULL || info == NULL) {
4278 PMD_DRV_LOG(ERR, "invalid parameters");
4279 return I40E_ERR_PARAM;
4283 vsi->info.pvid = info->config.pvid;
4285 * If insert pvid is enabled, only tagged pkts are
4286 * allowed to be sent out.
4288 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4289 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4292 if (info->config.reject.tagged == 0)
4293 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4295 if (info->config.reject.untagged == 0)
4296 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4298 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4299 I40E_AQ_VSI_PVLAN_MODE_MASK);
4300 vsi->info.port_vlan_flags |= vlan_flags;
4301 vsi->info.valid_sections =
4302 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4303 memset(&ctxt, 0, sizeof(ctxt));
4304 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4305 ctxt.seid = vsi->seid;
4307 hw = I40E_VSI_TO_HW(vsi);
4308 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4309 if (ret != I40E_SUCCESS)
4310 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4316 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4318 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4320 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4322 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4323 if (ret != I40E_SUCCESS)
4327 PMD_DRV_LOG(ERR, "seid not valid");
4331 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4332 tc_bw_data.tc_valid_bits = enabled_tcmap;
4333 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4334 tc_bw_data.tc_bw_credits[i] =
4335 (enabled_tcmap & (1 << i)) ? 1 : 0;
4337 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4338 if (ret != I40E_SUCCESS) {
4339 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4343 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4344 sizeof(vsi->info.qs_handle));
4345 return I40E_SUCCESS;
4348 static enum i40e_status_code
4349 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4350 struct i40e_aqc_vsi_properties_data *info,
4351 uint8_t enabled_tcmap)
4353 enum i40e_status_code ret;
4354 int i, total_tc = 0;
4355 uint16_t qpnum_per_tc, bsf, qp_idx;
4357 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4358 if (ret != I40E_SUCCESS)
4361 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4362 if (enabled_tcmap & (1 << i))
4366 vsi->enabled_tc = enabled_tcmap;
4368 /* Number of queues per enabled TC */
4369 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4370 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4371 bsf = rte_bsf32(qpnum_per_tc);
4373 /* Adjust the queue number to actual queues that can be applied */
4374 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4375 vsi->nb_qps = qpnum_per_tc * total_tc;
4378 * Configure TC and queue mapping parameters, for enabled TC,
4379 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4380 * default queue will serve it.
4383 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4384 if (vsi->enabled_tc & (1 << i)) {
4385 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4386 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4387 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4388 qp_idx += qpnum_per_tc;
4390 info->tc_mapping[i] = 0;
4393 /* Associate queue number with VSI */
4394 if (vsi->type == I40E_VSI_SRIOV) {
4395 info->mapping_flags |=
4396 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4397 for (i = 0; i < vsi->nb_qps; i++)
4398 info->queue_mapping[i] =
4399 rte_cpu_to_le_16(vsi->base_queue + i);
4401 info->mapping_flags |=
4402 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4403 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4405 info->valid_sections |=
4406 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4408 return I40E_SUCCESS;
4412 i40e_veb_release(struct i40e_veb *veb)
4414 struct i40e_vsi *vsi;
4420 if (!TAILQ_EMPTY(&veb->head)) {
4421 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4424 /* associate_vsi field is NULL for floating VEB */
4425 if (veb->associate_vsi != NULL) {
4426 vsi = veb->associate_vsi;
4427 hw = I40E_VSI_TO_HW(vsi);
4429 vsi->uplink_seid = veb->uplink_seid;
4432 veb->associate_pf->main_vsi->floating_veb = NULL;
4433 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4436 i40e_aq_delete_element(hw, veb->seid, NULL);
4438 return I40E_SUCCESS;
4442 static struct i40e_veb *
4443 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4445 struct i40e_veb *veb;
4451 "veb setup failed, associated PF shouldn't null");
4454 hw = I40E_PF_TO_HW(pf);
4456 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4458 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4462 veb->associate_vsi = vsi;
4463 veb->associate_pf = pf;
4464 TAILQ_INIT(&veb->head);
4465 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4467 /* create floating veb if vsi is NULL */
4469 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4470 I40E_DEFAULT_TCMAP, false,
4471 &veb->seid, false, NULL);
4473 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4474 true, &veb->seid, false, NULL);
4477 if (ret != I40E_SUCCESS) {
4478 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4479 hw->aq.asq_last_status);
4482 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4484 /* get statistics index */
4485 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4486 &veb->stats_idx, NULL, NULL, NULL);
4487 if (ret != I40E_SUCCESS) {
4488 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4489 hw->aq.asq_last_status);
4492 /* Get VEB bandwidth, to be implemented */
4493 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4495 vsi->uplink_seid = veb->seid;
4504 i40e_vsi_release(struct i40e_vsi *vsi)
4508 struct i40e_vsi_list *vsi_list;
4511 struct i40e_mac_filter *f;
4512 uint16_t user_param;
4515 return I40E_SUCCESS;
4520 user_param = vsi->user_param;
4522 pf = I40E_VSI_TO_PF(vsi);
4523 hw = I40E_VSI_TO_HW(vsi);
4525 /* VSI has child to attach, release child first */
4527 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4528 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4531 i40e_veb_release(vsi->veb);
4534 if (vsi->floating_veb) {
4535 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4536 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4541 /* Remove all macvlan filters of the VSI */
4542 i40e_vsi_remove_all_macvlan_filter(vsi);
4543 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4546 if (vsi->type != I40E_VSI_MAIN &&
4547 ((vsi->type != I40E_VSI_SRIOV) ||
4548 !pf->floating_veb_list[user_param])) {
4549 /* Remove vsi from parent's sibling list */
4550 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4551 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4552 return I40E_ERR_PARAM;
4554 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4555 &vsi->sib_vsi_list, list);
4557 /* Remove all switch element of the VSI */
4558 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4559 if (ret != I40E_SUCCESS)
4560 PMD_DRV_LOG(ERR, "Failed to delete element");
4563 if ((vsi->type == I40E_VSI_SRIOV) &&
4564 pf->floating_veb_list[user_param]) {
4565 /* Remove vsi from parent's sibling list */
4566 if (vsi->parent_vsi == NULL ||
4567 vsi->parent_vsi->floating_veb == NULL) {
4568 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4569 return I40E_ERR_PARAM;
4571 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4572 &vsi->sib_vsi_list, list);
4574 /* Remove all switch element of the VSI */
4575 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4576 if (ret != I40E_SUCCESS)
4577 PMD_DRV_LOG(ERR, "Failed to delete element");
4580 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4582 if (vsi->type != I40E_VSI_SRIOV)
4583 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4586 return I40E_SUCCESS;
4590 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4592 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4593 struct i40e_aqc_remove_macvlan_element_data def_filter;
4594 struct i40e_mac_filter_info filter;
4597 if (vsi->type != I40E_VSI_MAIN)
4598 return I40E_ERR_CONFIG;
4599 memset(&def_filter, 0, sizeof(def_filter));
4600 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4602 def_filter.vlan_tag = 0;
4603 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4604 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4605 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4606 if (ret != I40E_SUCCESS) {
4607 struct i40e_mac_filter *f;
4608 struct ether_addr *mac;
4611 "Cannot remove the default macvlan filter");
4612 /* It needs to add the permanent mac into mac list */
4613 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4615 PMD_DRV_LOG(ERR, "failed to allocate memory");
4616 return I40E_ERR_NO_MEMORY;
4618 mac = &f->mac_info.mac_addr;
4619 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4621 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4622 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4627 (void)rte_memcpy(&filter.mac_addr,
4628 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4629 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4630 return i40e_vsi_add_mac(vsi, &filter);
4634 * i40e_vsi_get_bw_config - Query VSI BW Information
4635 * @vsi: the VSI to be queried
4637 * Returns 0 on success, negative value on failure
4639 static enum i40e_status_code
4640 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4642 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4643 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4644 struct i40e_hw *hw = &vsi->adapter->hw;
4649 memset(&bw_config, 0, sizeof(bw_config));
4650 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4651 if (ret != I40E_SUCCESS) {
4652 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4653 hw->aq.asq_last_status);
4657 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4658 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4659 &ets_sla_config, NULL);
4660 if (ret != I40E_SUCCESS) {
4662 "VSI failed to get TC bandwdith configuration %u",
4663 hw->aq.asq_last_status);
4667 /* store and print out BW info */
4668 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4669 vsi->bw_info.bw_max = bw_config.max_bw;
4670 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4671 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4672 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4673 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4675 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4676 vsi->bw_info.bw_ets_share_credits[i] =
4677 ets_sla_config.share_credits[i];
4678 vsi->bw_info.bw_ets_credits[i] =
4679 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4680 /* 4 bits per TC, 4th bit is reserved */
4681 vsi->bw_info.bw_ets_max[i] =
4682 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4683 RTE_LEN2MASK(3, uint8_t));
4684 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4685 vsi->bw_info.bw_ets_share_credits[i]);
4686 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4687 vsi->bw_info.bw_ets_credits[i]);
4688 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4689 vsi->bw_info.bw_ets_max[i]);
4692 return I40E_SUCCESS;
4695 /* i40e_enable_pf_lb
4696 * @pf: pointer to the pf structure
4698 * allow loopback on pf
4701 i40e_enable_pf_lb(struct i40e_pf *pf)
4703 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4704 struct i40e_vsi_context ctxt;
4707 /* Use the FW API if FW >= v5.0 */
4708 if (hw->aq.fw_maj_ver < 5) {
4709 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4713 memset(&ctxt, 0, sizeof(ctxt));
4714 ctxt.seid = pf->main_vsi_seid;
4715 ctxt.pf_num = hw->pf_id;
4716 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4718 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4719 ret, hw->aq.asq_last_status);
4722 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4723 ctxt.info.valid_sections =
4724 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4725 ctxt.info.switch_id |=
4726 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4728 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4730 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4731 hw->aq.asq_last_status);
4736 i40e_vsi_setup(struct i40e_pf *pf,
4737 enum i40e_vsi_type type,
4738 struct i40e_vsi *uplink_vsi,
4739 uint16_t user_param)
4741 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4742 struct i40e_vsi *vsi;
4743 struct i40e_mac_filter_info filter;
4745 struct i40e_vsi_context ctxt;
4746 struct ether_addr broadcast =
4747 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4749 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4750 uplink_vsi == NULL) {
4752 "VSI setup failed, VSI link shouldn't be NULL");
4756 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4758 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4763 * 1.type is not MAIN and uplink vsi is not NULL
4764 * If uplink vsi didn't setup VEB, create one first under veb field
4765 * 2.type is SRIOV and the uplink is NULL
4766 * If floating VEB is NULL, create one veb under floating veb field
4769 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4770 uplink_vsi->veb == NULL) {
4771 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4773 if (uplink_vsi->veb == NULL) {
4774 PMD_DRV_LOG(ERR, "VEB setup failed");
4777 /* set ALLOWLOOPBACk on pf, when veb is created */
4778 i40e_enable_pf_lb(pf);
4781 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4782 pf->main_vsi->floating_veb == NULL) {
4783 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4785 if (pf->main_vsi->floating_veb == NULL) {
4786 PMD_DRV_LOG(ERR, "VEB setup failed");
4791 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4793 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4796 TAILQ_INIT(&vsi->mac_list);
4798 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4799 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4800 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4801 vsi->user_param = user_param;
4802 vsi->vlan_anti_spoof_on = 0;
4803 vsi->vlan_filter_on = 0;
4804 /* Allocate queues */
4805 switch (vsi->type) {
4806 case I40E_VSI_MAIN :
4807 vsi->nb_qps = pf->lan_nb_qps;
4809 case I40E_VSI_SRIOV :
4810 vsi->nb_qps = pf->vf_nb_qps;
4812 case I40E_VSI_VMDQ2:
4813 vsi->nb_qps = pf->vmdq_nb_qps;
4816 vsi->nb_qps = pf->fdir_nb_qps;
4822 * The filter status descriptor is reported in rx queue 0,
4823 * while the tx queue for fdir filter programming has no
4824 * such constraints, can be non-zero queues.
4825 * To simplify it, choose FDIR vsi use queue 0 pair.
4826 * To make sure it will use queue 0 pair, queue allocation
4827 * need be done before this function is called
4829 if (type != I40E_VSI_FDIR) {
4830 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4832 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4836 vsi->base_queue = ret;
4838 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4840 /* VF has MSIX interrupt in VF range, don't allocate here */
4841 if (type == I40E_VSI_MAIN) {
4842 ret = i40e_res_pool_alloc(&pf->msix_pool,
4843 RTE_MIN(vsi->nb_qps,
4844 RTE_MAX_RXTX_INTR_VEC_ID));
4846 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4848 goto fail_queue_alloc;
4850 vsi->msix_intr = ret;
4851 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4852 } else if (type != I40E_VSI_SRIOV) {
4853 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4855 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4856 goto fail_queue_alloc;
4858 vsi->msix_intr = ret;
4866 if (type == I40E_VSI_MAIN) {
4867 /* For main VSI, no need to add since it's default one */
4868 vsi->uplink_seid = pf->mac_seid;
4869 vsi->seid = pf->main_vsi_seid;
4870 /* Bind queues with specific MSIX interrupt */
4872 * Needs 2 interrupt at least, one for misc cause which will
4873 * enabled from OS side, Another for queues binding the
4874 * interrupt from device side only.
4877 /* Get default VSI parameters from hardware */
4878 memset(&ctxt, 0, sizeof(ctxt));
4879 ctxt.seid = vsi->seid;
4880 ctxt.pf_num = hw->pf_id;
4881 ctxt.uplink_seid = vsi->uplink_seid;
4883 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4884 if (ret != I40E_SUCCESS) {
4885 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4886 goto fail_msix_alloc;
4888 (void)rte_memcpy(&vsi->info, &ctxt.info,
4889 sizeof(struct i40e_aqc_vsi_properties_data));
4890 vsi->vsi_id = ctxt.vsi_number;
4891 vsi->info.valid_sections = 0;
4893 /* Configure tc, enabled TC0 only */
4894 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4896 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4897 goto fail_msix_alloc;
4900 /* TC, queue mapping */
4901 memset(&ctxt, 0, sizeof(ctxt));
4902 vsi->info.valid_sections |=
4903 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4904 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4905 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4906 (void)rte_memcpy(&ctxt.info, &vsi->info,
4907 sizeof(struct i40e_aqc_vsi_properties_data));
4908 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4909 I40E_DEFAULT_TCMAP);
4910 if (ret != I40E_SUCCESS) {
4912 "Failed to configure TC queue mapping");
4913 goto fail_msix_alloc;
4915 ctxt.seid = vsi->seid;
4916 ctxt.pf_num = hw->pf_id;
4917 ctxt.uplink_seid = vsi->uplink_seid;
4920 /* Update VSI parameters */
4921 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4922 if (ret != I40E_SUCCESS) {
4923 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4924 goto fail_msix_alloc;
4927 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4928 sizeof(vsi->info.tc_mapping));
4929 (void)rte_memcpy(&vsi->info.queue_mapping,
4930 &ctxt.info.queue_mapping,
4931 sizeof(vsi->info.queue_mapping));
4932 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4933 vsi->info.valid_sections = 0;
4935 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4939 * Updating default filter settings are necessary to prevent
4940 * reception of tagged packets.
4941 * Some old firmware configurations load a default macvlan
4942 * filter which accepts both tagged and untagged packets.
4943 * The updating is to use a normal filter instead if needed.
4944 * For NVM 4.2.2 or after, the updating is not needed anymore.
4945 * The firmware with correct configurations load the default
4946 * macvlan filter which is expected and cannot be removed.
4948 i40e_update_default_filter_setting(vsi);
4949 i40e_config_qinq(hw, vsi);
4950 } else if (type == I40E_VSI_SRIOV) {
4951 memset(&ctxt, 0, sizeof(ctxt));
4953 * For other VSI, the uplink_seid equals to uplink VSI's
4954 * uplink_seid since they share same VEB
4956 if (uplink_vsi == NULL)
4957 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4959 vsi->uplink_seid = uplink_vsi->uplink_seid;
4960 ctxt.pf_num = hw->pf_id;
4961 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4962 ctxt.uplink_seid = vsi->uplink_seid;
4963 ctxt.connection_type = 0x1;
4964 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4966 /* Use the VEB configuration if FW >= v5.0 */
4967 if (hw->aq.fw_maj_ver >= 5) {
4968 /* Configure switch ID */
4969 ctxt.info.valid_sections |=
4970 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4971 ctxt.info.switch_id =
4972 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4975 /* Configure port/vlan */
4976 ctxt.info.valid_sections |=
4977 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4978 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4979 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4980 hw->func_caps.enabled_tcmap);
4981 if (ret != I40E_SUCCESS) {
4983 "Failed to configure TC queue mapping");
4984 goto fail_msix_alloc;
4987 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4988 ctxt.info.valid_sections |=
4989 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4991 * Since VSI is not created yet, only configure parameter,
4992 * will add vsi below.
4995 i40e_config_qinq(hw, vsi);
4996 } else if (type == I40E_VSI_VMDQ2) {
4997 memset(&ctxt, 0, sizeof(ctxt));
4999 * For other VSI, the uplink_seid equals to uplink VSI's
5000 * uplink_seid since they share same VEB
5002 vsi->uplink_seid = uplink_vsi->uplink_seid;
5003 ctxt.pf_num = hw->pf_id;
5005 ctxt.uplink_seid = vsi->uplink_seid;
5006 ctxt.connection_type = 0x1;
5007 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5009 ctxt.info.valid_sections |=
5010 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5011 /* user_param carries flag to enable loop back */
5013 ctxt.info.switch_id =
5014 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5015 ctxt.info.switch_id |=
5016 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5019 /* Configure port/vlan */
5020 ctxt.info.valid_sections |=
5021 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5022 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5023 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5024 I40E_DEFAULT_TCMAP);
5025 if (ret != I40E_SUCCESS) {
5027 "Failed to configure TC queue mapping");
5028 goto fail_msix_alloc;
5030 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5031 ctxt.info.valid_sections |=
5032 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5033 } else if (type == I40E_VSI_FDIR) {
5034 memset(&ctxt, 0, sizeof(ctxt));
5035 vsi->uplink_seid = uplink_vsi->uplink_seid;
5036 ctxt.pf_num = hw->pf_id;
5038 ctxt.uplink_seid = vsi->uplink_seid;
5039 ctxt.connection_type = 0x1; /* regular data port */
5040 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5041 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5042 I40E_DEFAULT_TCMAP);
5043 if (ret != I40E_SUCCESS) {
5045 "Failed to configure TC queue mapping.");
5046 goto fail_msix_alloc;
5048 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5049 ctxt.info.valid_sections |=
5050 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5052 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5053 goto fail_msix_alloc;
5056 if (vsi->type != I40E_VSI_MAIN) {
5057 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5058 if (ret != I40E_SUCCESS) {
5059 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5060 hw->aq.asq_last_status);
5061 goto fail_msix_alloc;
5063 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5064 vsi->info.valid_sections = 0;
5065 vsi->seid = ctxt.seid;
5066 vsi->vsi_id = ctxt.vsi_number;
5067 vsi->sib_vsi_list.vsi = vsi;
5068 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5069 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5070 &vsi->sib_vsi_list, list);
5072 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5073 &vsi->sib_vsi_list, list);
5077 /* MAC/VLAN configuration */
5078 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5079 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5081 ret = i40e_vsi_add_mac(vsi, &filter);
5082 if (ret != I40E_SUCCESS) {
5083 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5084 goto fail_msix_alloc;
5087 /* Get VSI BW information */
5088 i40e_vsi_get_bw_config(vsi);
5091 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5093 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5099 /* Configure vlan filter on or off */
5101 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5104 struct i40e_mac_filter *f;
5106 struct i40e_mac_filter_info *mac_filter;
5107 enum rte_mac_filter_type desired_filter;
5108 int ret = I40E_SUCCESS;
5111 /* Filter to match MAC and VLAN */
5112 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5114 /* Filter to match only MAC */
5115 desired_filter = RTE_MAC_PERFECT_MATCH;
5120 mac_filter = rte_zmalloc("mac_filter_info_data",
5121 num * sizeof(*mac_filter), 0);
5122 if (mac_filter == NULL) {
5123 PMD_DRV_LOG(ERR, "failed to allocate memory");
5124 return I40E_ERR_NO_MEMORY;
5129 /* Remove all existing mac */
5130 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5131 mac_filter[i] = f->mac_info;
5132 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5134 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5135 on ? "enable" : "disable");
5141 /* Override with new filter */
5142 for (i = 0; i < num; i++) {
5143 mac_filter[i].filter_type = desired_filter;
5144 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5146 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5147 on ? "enable" : "disable");
5153 rte_free(mac_filter);
5157 /* Configure vlan stripping on or off */
5159 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5161 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5162 struct i40e_vsi_context ctxt;
5164 int ret = I40E_SUCCESS;
5166 /* Check if it has been already on or off */
5167 if (vsi->info.valid_sections &
5168 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5170 if ((vsi->info.port_vlan_flags &
5171 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5172 return 0; /* already on */
5174 if ((vsi->info.port_vlan_flags &
5175 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5176 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5177 return 0; /* already off */
5182 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5184 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5185 vsi->info.valid_sections =
5186 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5187 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5188 vsi->info.port_vlan_flags |= vlan_flags;
5189 ctxt.seid = vsi->seid;
5190 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5191 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5193 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5194 on ? "enable" : "disable");
5200 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5202 struct rte_eth_dev_data *data = dev->data;
5206 /* Apply vlan offload setting */
5207 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5208 i40e_vlan_offload_set(dev, mask);
5210 /* Apply double-vlan setting, not implemented yet */
5212 /* Apply pvid setting */
5213 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5214 data->dev_conf.txmode.hw_vlan_insert_pvid);
5216 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5222 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5224 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5226 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5230 i40e_update_flow_control(struct i40e_hw *hw)
5232 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5233 struct i40e_link_status link_status;
5234 uint32_t rxfc = 0, txfc = 0, reg;
5238 memset(&link_status, 0, sizeof(link_status));
5239 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5240 if (ret != I40E_SUCCESS) {
5241 PMD_DRV_LOG(ERR, "Failed to get link status information");
5242 goto write_reg; /* Disable flow control */
5245 an_info = hw->phy.link_info.an_info;
5246 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5247 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5248 ret = I40E_ERR_NOT_READY;
5249 goto write_reg; /* Disable flow control */
5252 * If link auto negotiation is enabled, flow control needs to
5253 * be configured according to it
5255 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5256 case I40E_LINK_PAUSE_RXTX:
5259 hw->fc.current_mode = I40E_FC_FULL;
5261 case I40E_AQ_LINK_PAUSE_RX:
5263 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5265 case I40E_AQ_LINK_PAUSE_TX:
5267 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5270 hw->fc.current_mode = I40E_FC_NONE;
5275 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5276 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5277 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5278 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5279 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5280 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5287 i40e_pf_setup(struct i40e_pf *pf)
5289 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5290 struct i40e_filter_control_settings settings;
5291 struct i40e_vsi *vsi;
5294 /* Clear all stats counters */
5295 pf->offset_loaded = FALSE;
5296 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5297 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5298 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5299 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5301 ret = i40e_pf_get_switch_config(pf);
5302 if (ret != I40E_SUCCESS) {
5303 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5306 if (pf->flags & I40E_FLAG_FDIR) {
5307 /* make queue allocated first, let FDIR use queue pair 0*/
5308 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5309 if (ret != I40E_FDIR_QUEUE_ID) {
5311 "queue allocation fails for FDIR: ret =%d",
5313 pf->flags &= ~I40E_FLAG_FDIR;
5316 /* main VSI setup */
5317 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5319 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5320 return I40E_ERR_NOT_READY;
5324 /* Configure filter control */
5325 memset(&settings, 0, sizeof(settings));
5326 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5327 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5328 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5329 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5331 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5332 hw->func_caps.rss_table_size);
5333 return I40E_ERR_PARAM;
5335 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5336 hw->func_caps.rss_table_size);
5337 pf->hash_lut_size = hw->func_caps.rss_table_size;
5339 /* Enable ethtype and macvlan filters */
5340 settings.enable_ethtype = TRUE;
5341 settings.enable_macvlan = TRUE;
5342 ret = i40e_set_filter_control(hw, &settings);
5344 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5347 /* Update flow control according to the auto negotiation */
5348 i40e_update_flow_control(hw);
5350 return I40E_SUCCESS;
5354 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5360 * Set or clear TX Queue Disable flags,
5361 * which is required by hardware.
5363 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5364 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5366 /* Wait until the request is finished */
5367 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5368 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5369 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5370 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5371 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5377 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5378 return I40E_SUCCESS; /* already on, skip next steps */
5380 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5381 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5383 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5384 return I40E_SUCCESS; /* already off, skip next steps */
5385 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5387 /* Write the register */
5388 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5389 /* Check the result */
5390 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5391 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5392 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5394 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5395 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5398 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5399 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5403 /* Check if it is timeout */
5404 if (j >= I40E_CHK_Q_ENA_COUNT) {
5405 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5406 (on ? "enable" : "disable"), q_idx);
5407 return I40E_ERR_TIMEOUT;
5410 return I40E_SUCCESS;
5413 /* Swith on or off the tx queues */
5415 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5417 struct rte_eth_dev_data *dev_data = pf->dev_data;
5418 struct i40e_tx_queue *txq;
5419 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5423 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5424 txq = dev_data->tx_queues[i];
5425 /* Don't operate the queue if not configured or
5426 * if starting only per queue */
5427 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5430 ret = i40e_dev_tx_queue_start(dev, i);
5432 ret = i40e_dev_tx_queue_stop(dev, i);
5433 if ( ret != I40E_SUCCESS)
5437 return I40E_SUCCESS;
5441 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5446 /* Wait until the request is finished */
5447 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5448 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5449 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5450 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5451 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5456 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5457 return I40E_SUCCESS; /* Already on, skip next steps */
5458 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5460 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5461 return I40E_SUCCESS; /* Already off, skip next steps */
5462 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5465 /* Write the register */
5466 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5467 /* Check the result */
5468 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5469 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5470 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5472 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5473 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5476 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5477 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5482 /* Check if it is timeout */
5483 if (j >= I40E_CHK_Q_ENA_COUNT) {
5484 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5485 (on ? "enable" : "disable"), q_idx);
5486 return I40E_ERR_TIMEOUT;
5489 return I40E_SUCCESS;
5491 /* Switch on or off the rx queues */
5493 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5495 struct rte_eth_dev_data *dev_data = pf->dev_data;
5496 struct i40e_rx_queue *rxq;
5497 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5501 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5502 rxq = dev_data->rx_queues[i];
5503 /* Don't operate the queue if not configured or
5504 * if starting only per queue */
5505 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5508 ret = i40e_dev_rx_queue_start(dev, i);
5510 ret = i40e_dev_rx_queue_stop(dev, i);
5511 if (ret != I40E_SUCCESS)
5515 return I40E_SUCCESS;
5518 /* Switch on or off all the rx/tx queues */
5520 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5525 /* enable rx queues before enabling tx queues */
5526 ret = i40e_dev_switch_rx_queues(pf, on);
5528 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5531 ret = i40e_dev_switch_tx_queues(pf, on);
5533 /* Stop tx queues before stopping rx queues */
5534 ret = i40e_dev_switch_tx_queues(pf, on);
5536 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5539 ret = i40e_dev_switch_rx_queues(pf, on);
5545 /* Initialize VSI for TX */
5547 i40e_dev_tx_init(struct i40e_pf *pf)
5549 struct rte_eth_dev_data *data = pf->dev_data;
5551 uint32_t ret = I40E_SUCCESS;
5552 struct i40e_tx_queue *txq;
5554 for (i = 0; i < data->nb_tx_queues; i++) {
5555 txq = data->tx_queues[i];
5556 if (!txq || !txq->q_set)
5558 ret = i40e_tx_queue_init(txq);
5559 if (ret != I40E_SUCCESS)
5562 if (ret == I40E_SUCCESS)
5563 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5569 /* Initialize VSI for RX */
5571 i40e_dev_rx_init(struct i40e_pf *pf)
5573 struct rte_eth_dev_data *data = pf->dev_data;
5574 int ret = I40E_SUCCESS;
5576 struct i40e_rx_queue *rxq;
5578 i40e_pf_config_mq_rx(pf);
5579 for (i = 0; i < data->nb_rx_queues; i++) {
5580 rxq = data->rx_queues[i];
5581 if (!rxq || !rxq->q_set)
5584 ret = i40e_rx_queue_init(rxq);
5585 if (ret != I40E_SUCCESS) {
5587 "Failed to do RX queue initialization");
5591 if (ret == I40E_SUCCESS)
5592 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5599 i40e_dev_rxtx_init(struct i40e_pf *pf)
5603 err = i40e_dev_tx_init(pf);
5605 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5608 err = i40e_dev_rx_init(pf);
5610 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5618 i40e_vmdq_setup(struct rte_eth_dev *dev)
5620 struct rte_eth_conf *conf = &dev->data->dev_conf;
5621 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5622 int i, err, conf_vsis, j, loop;
5623 struct i40e_vsi *vsi;
5624 struct i40e_vmdq_info *vmdq_info;
5625 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5626 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5629 * Disable interrupt to avoid message from VF. Furthermore, it will
5630 * avoid race condition in VSI creation/destroy.
5632 i40e_pf_disable_irq0(hw);
5634 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5635 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5639 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5640 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5641 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5642 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5643 pf->max_nb_vmdq_vsi);
5647 if (pf->vmdq != NULL) {
5648 PMD_INIT_LOG(INFO, "VMDQ already configured");
5652 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5653 sizeof(*vmdq_info) * conf_vsis, 0);
5655 if (pf->vmdq == NULL) {
5656 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5660 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5662 /* Create VMDQ VSI */
5663 for (i = 0; i < conf_vsis; i++) {
5664 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5665 vmdq_conf->enable_loop_back);
5667 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5671 vmdq_info = &pf->vmdq[i];
5673 vmdq_info->vsi = vsi;
5675 pf->nb_cfg_vmdq_vsi = conf_vsis;
5677 /* Configure Vlan */
5678 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5679 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5680 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5681 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5682 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5683 vmdq_conf->pool_map[i].vlan_id, j);
5685 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5686 vmdq_conf->pool_map[i].vlan_id);
5688 PMD_INIT_LOG(ERR, "Failed to add vlan");
5696 i40e_pf_enable_irq0(hw);
5701 for (i = 0; i < conf_vsis; i++)
5702 if (pf->vmdq[i].vsi == NULL)
5705 i40e_vsi_release(pf->vmdq[i].vsi);
5709 i40e_pf_enable_irq0(hw);
5714 i40e_stat_update_32(struct i40e_hw *hw,
5722 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5726 if (new_data >= *offset)
5727 *stat = (uint64_t)(new_data - *offset);
5729 *stat = (uint64_t)((new_data +
5730 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5734 i40e_stat_update_48(struct i40e_hw *hw,
5743 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5744 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5745 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5750 if (new_data >= *offset)
5751 *stat = new_data - *offset;
5753 *stat = (uint64_t)((new_data +
5754 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5756 *stat &= I40E_48_BIT_MASK;
5761 i40e_pf_disable_irq0(struct i40e_hw *hw)
5763 /* Disable all interrupt types */
5764 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5765 I40E_WRITE_FLUSH(hw);
5770 i40e_pf_enable_irq0(struct i40e_hw *hw)
5772 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5773 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5774 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5775 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5776 I40E_WRITE_FLUSH(hw);
5780 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5782 /* read pending request and disable first */
5783 i40e_pf_disable_irq0(hw);
5784 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5785 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5786 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5789 /* Link no queues with irq0 */
5790 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5791 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5795 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5797 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5798 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5801 uint32_t index, offset, val;
5806 * Try to find which VF trigger a reset, use absolute VF id to access
5807 * since the reg is global register.
5809 for (i = 0; i < pf->vf_num; i++) {
5810 abs_vf_id = hw->func_caps.vf_base_id + i;
5811 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5812 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5813 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5814 /* VFR event occurred */
5815 if (val & (0x1 << offset)) {
5818 /* Clear the event first */
5819 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5821 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5823 * Only notify a VF reset event occurred,
5824 * don't trigger another SW reset
5826 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5827 if (ret != I40E_SUCCESS)
5828 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5834 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5836 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5839 for (i = 0; i < pf->vf_num; i++)
5840 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5844 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5846 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5847 struct i40e_arq_event_info info;
5848 uint16_t pending, opcode;
5851 info.buf_len = I40E_AQ_BUF_SZ;
5852 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5853 if (!info.msg_buf) {
5854 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5860 ret = i40e_clean_arq_element(hw, &info, &pending);
5862 if (ret != I40E_SUCCESS) {
5864 "Failed to read msg from AdminQ, aq_err: %u",
5865 hw->aq.asq_last_status);
5868 opcode = rte_le_to_cpu_16(info.desc.opcode);
5871 case i40e_aqc_opc_send_msg_to_pf:
5872 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5873 i40e_pf_host_handle_vf_msg(dev,
5874 rte_le_to_cpu_16(info.desc.retval),
5875 rte_le_to_cpu_32(info.desc.cookie_high),
5876 rte_le_to_cpu_32(info.desc.cookie_low),
5880 case i40e_aqc_opc_get_link_status:
5881 ret = i40e_dev_link_update(dev, 0);
5883 _rte_eth_dev_callback_process(dev,
5884 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5887 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5892 rte_free(info.msg_buf);
5896 * Interrupt handler triggered by NIC for handling
5897 * specific interrupt.
5900 * Pointer to interrupt handle.
5902 * The address of parameter (struct rte_eth_dev *) regsitered before.
5908 i40e_dev_interrupt_handler(void *param)
5910 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5911 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5914 /* Disable interrupt */
5915 i40e_pf_disable_irq0(hw);
5917 /* read out interrupt causes */
5918 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5920 /* No interrupt event indicated */
5921 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5922 PMD_DRV_LOG(INFO, "No interrupt event");
5925 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5926 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5927 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5928 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5929 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5930 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5931 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5932 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5933 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5934 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5935 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5936 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5937 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5938 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5940 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5941 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5942 i40e_dev_handle_vfr_event(dev);
5944 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5945 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5946 i40e_dev_handle_aq_msg(dev);
5950 /* Enable interrupt */
5951 i40e_pf_enable_irq0(hw);
5952 rte_intr_enable(dev->intr_handle);
5956 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5957 struct i40e_macvlan_filter *filter,
5960 int ele_num, ele_buff_size;
5961 int num, actual_num, i;
5963 int ret = I40E_SUCCESS;
5964 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5965 struct i40e_aqc_add_macvlan_element_data *req_list;
5967 if (filter == NULL || total == 0)
5968 return I40E_ERR_PARAM;
5969 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5970 ele_buff_size = hw->aq.asq_buf_size;
5972 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5973 if (req_list == NULL) {
5974 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5975 return I40E_ERR_NO_MEMORY;
5980 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5981 memset(req_list, 0, ele_buff_size);
5983 for (i = 0; i < actual_num; i++) {
5984 (void)rte_memcpy(req_list[i].mac_addr,
5985 &filter[num + i].macaddr, ETH_ADDR_LEN);
5986 req_list[i].vlan_tag =
5987 rte_cpu_to_le_16(filter[num + i].vlan_id);
5989 switch (filter[num + i].filter_type) {
5990 case RTE_MAC_PERFECT_MATCH:
5991 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5992 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5994 case RTE_MACVLAN_PERFECT_MATCH:
5995 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5997 case RTE_MAC_HASH_MATCH:
5998 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5999 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6001 case RTE_MACVLAN_HASH_MATCH:
6002 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6005 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6006 ret = I40E_ERR_PARAM;
6010 req_list[i].queue_number = 0;
6012 req_list[i].flags = rte_cpu_to_le_16(flags);
6015 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6017 if (ret != I40E_SUCCESS) {
6018 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6022 } while (num < total);
6030 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6031 struct i40e_macvlan_filter *filter,
6034 int ele_num, ele_buff_size;
6035 int num, actual_num, i;
6037 int ret = I40E_SUCCESS;
6038 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6039 struct i40e_aqc_remove_macvlan_element_data *req_list;
6041 if (filter == NULL || total == 0)
6042 return I40E_ERR_PARAM;
6044 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6045 ele_buff_size = hw->aq.asq_buf_size;
6047 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6048 if (req_list == NULL) {
6049 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6050 return I40E_ERR_NO_MEMORY;
6055 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6056 memset(req_list, 0, ele_buff_size);
6058 for (i = 0; i < actual_num; i++) {
6059 (void)rte_memcpy(req_list[i].mac_addr,
6060 &filter[num + i].macaddr, ETH_ADDR_LEN);
6061 req_list[i].vlan_tag =
6062 rte_cpu_to_le_16(filter[num + i].vlan_id);
6064 switch (filter[num + i].filter_type) {
6065 case RTE_MAC_PERFECT_MATCH:
6066 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6067 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6069 case RTE_MACVLAN_PERFECT_MATCH:
6070 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6072 case RTE_MAC_HASH_MATCH:
6073 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6074 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6076 case RTE_MACVLAN_HASH_MATCH:
6077 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6080 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6081 ret = I40E_ERR_PARAM;
6084 req_list[i].flags = rte_cpu_to_le_16(flags);
6087 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6089 if (ret != I40E_SUCCESS) {
6090 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6094 } while (num < total);
6101 /* Find out specific MAC filter */
6102 static struct i40e_mac_filter *
6103 i40e_find_mac_filter(struct i40e_vsi *vsi,
6104 struct ether_addr *macaddr)
6106 struct i40e_mac_filter *f;
6108 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6109 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6117 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6120 uint32_t vid_idx, vid_bit;
6122 if (vlan_id > ETH_VLAN_ID_MAX)
6125 vid_idx = I40E_VFTA_IDX(vlan_id);
6126 vid_bit = I40E_VFTA_BIT(vlan_id);
6128 if (vsi->vfta[vid_idx] & vid_bit)
6135 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6136 uint16_t vlan_id, bool on)
6138 uint32_t vid_idx, vid_bit;
6140 vid_idx = I40E_VFTA_IDX(vlan_id);
6141 vid_bit = I40E_VFTA_BIT(vlan_id);
6144 vsi->vfta[vid_idx] |= vid_bit;
6146 vsi->vfta[vid_idx] &= ~vid_bit;
6150 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6151 uint16_t vlan_id, bool on)
6153 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6154 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6157 if (vlan_id > ETH_VLAN_ID_MAX)
6160 i40e_store_vlan_filter(vsi, vlan_id, on);
6162 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6165 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6168 ret = i40e_aq_add_vlan(hw, vsi->seid,
6169 &vlan_data, 1, NULL);
6170 if (ret != I40E_SUCCESS)
6171 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6173 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6174 &vlan_data, 1, NULL);
6175 if (ret != I40E_SUCCESS)
6177 "Failed to remove vlan filter");
6182 * Find all vlan options for specific mac addr,
6183 * return with actual vlan found.
6186 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6187 struct i40e_macvlan_filter *mv_f,
6188 int num, struct ether_addr *addr)
6194 * Not to use i40e_find_vlan_filter to decrease the loop time,
6195 * although the code looks complex.
6197 if (num < vsi->vlan_num)
6198 return I40E_ERR_PARAM;
6201 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6203 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6204 if (vsi->vfta[j] & (1 << k)) {
6207 "vlan number doesn't match");
6208 return I40E_ERR_PARAM;
6210 (void)rte_memcpy(&mv_f[i].macaddr,
6211 addr, ETH_ADDR_LEN);
6213 j * I40E_UINT32_BIT_SIZE + k;
6219 return I40E_SUCCESS;
6223 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6224 struct i40e_macvlan_filter *mv_f,
6229 struct i40e_mac_filter *f;
6231 if (num < vsi->mac_num)
6232 return I40E_ERR_PARAM;
6234 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6236 PMD_DRV_LOG(ERR, "buffer number not match");
6237 return I40E_ERR_PARAM;
6239 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6241 mv_f[i].vlan_id = vlan;
6242 mv_f[i].filter_type = f->mac_info.filter_type;
6246 return I40E_SUCCESS;
6250 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6253 struct i40e_mac_filter *f;
6254 struct i40e_macvlan_filter *mv_f;
6255 int ret = I40E_SUCCESS;
6257 if (vsi == NULL || vsi->mac_num == 0)
6258 return I40E_ERR_PARAM;
6260 /* Case that no vlan is set */
6261 if (vsi->vlan_num == 0)
6264 num = vsi->mac_num * vsi->vlan_num;
6266 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6268 PMD_DRV_LOG(ERR, "failed to allocate memory");
6269 return I40E_ERR_NO_MEMORY;
6273 if (vsi->vlan_num == 0) {
6274 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6275 (void)rte_memcpy(&mv_f[i].macaddr,
6276 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6277 mv_f[i].filter_type = f->mac_info.filter_type;
6278 mv_f[i].vlan_id = 0;
6282 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6283 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6284 vsi->vlan_num, &f->mac_info.mac_addr);
6285 if (ret != I40E_SUCCESS)
6287 for (j = i; j < i + vsi->vlan_num; j++)
6288 mv_f[j].filter_type = f->mac_info.filter_type;
6293 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6301 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6303 struct i40e_macvlan_filter *mv_f;
6305 int ret = I40E_SUCCESS;
6307 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6308 return I40E_ERR_PARAM;
6310 /* If it's already set, just return */
6311 if (i40e_find_vlan_filter(vsi,vlan))
6312 return I40E_SUCCESS;
6314 mac_num = vsi->mac_num;
6317 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6318 return I40E_ERR_PARAM;
6321 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6324 PMD_DRV_LOG(ERR, "failed to allocate memory");
6325 return I40E_ERR_NO_MEMORY;
6328 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6330 if (ret != I40E_SUCCESS)
6333 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6335 if (ret != I40E_SUCCESS)
6338 i40e_set_vlan_filter(vsi, vlan, 1);
6348 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6350 struct i40e_macvlan_filter *mv_f;
6352 int ret = I40E_SUCCESS;
6355 * Vlan 0 is the generic filter for untagged packets
6356 * and can't be removed.
6358 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6359 return I40E_ERR_PARAM;
6361 /* If can't find it, just return */
6362 if (!i40e_find_vlan_filter(vsi, vlan))
6363 return I40E_ERR_PARAM;
6365 mac_num = vsi->mac_num;
6368 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6369 return I40E_ERR_PARAM;
6372 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6375 PMD_DRV_LOG(ERR, "failed to allocate memory");
6376 return I40E_ERR_NO_MEMORY;
6379 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6381 if (ret != I40E_SUCCESS)
6384 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6386 if (ret != I40E_SUCCESS)
6389 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6390 if (vsi->vlan_num == 1) {
6391 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6392 if (ret != I40E_SUCCESS)
6395 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6396 if (ret != I40E_SUCCESS)
6400 i40e_set_vlan_filter(vsi, vlan, 0);
6410 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6412 struct i40e_mac_filter *f;
6413 struct i40e_macvlan_filter *mv_f;
6414 int i, vlan_num = 0;
6415 int ret = I40E_SUCCESS;
6417 /* If it's add and we've config it, return */
6418 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6420 return I40E_SUCCESS;
6421 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6422 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6425 * If vlan_num is 0, that's the first time to add mac,
6426 * set mask for vlan_id 0.
6428 if (vsi->vlan_num == 0) {
6429 i40e_set_vlan_filter(vsi, 0, 1);
6432 vlan_num = vsi->vlan_num;
6433 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6434 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6437 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6439 PMD_DRV_LOG(ERR, "failed to allocate memory");
6440 return I40E_ERR_NO_MEMORY;
6443 for (i = 0; i < vlan_num; i++) {
6444 mv_f[i].filter_type = mac_filter->filter_type;
6445 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6449 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6450 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6451 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6452 &mac_filter->mac_addr);
6453 if (ret != I40E_SUCCESS)
6457 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6458 if (ret != I40E_SUCCESS)
6461 /* Add the mac addr into mac list */
6462 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6464 PMD_DRV_LOG(ERR, "failed to allocate memory");
6465 ret = I40E_ERR_NO_MEMORY;
6468 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6470 f->mac_info.filter_type = mac_filter->filter_type;
6471 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6482 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6484 struct i40e_mac_filter *f;
6485 struct i40e_macvlan_filter *mv_f;
6487 enum rte_mac_filter_type filter_type;
6488 int ret = I40E_SUCCESS;
6490 /* Can't find it, return an error */
6491 f = i40e_find_mac_filter(vsi, addr);
6493 return I40E_ERR_PARAM;
6495 vlan_num = vsi->vlan_num;
6496 filter_type = f->mac_info.filter_type;
6497 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6498 filter_type == RTE_MACVLAN_HASH_MATCH) {
6499 if (vlan_num == 0) {
6500 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6501 return I40E_ERR_PARAM;
6503 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6504 filter_type == RTE_MAC_HASH_MATCH)
6507 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6509 PMD_DRV_LOG(ERR, "failed to allocate memory");
6510 return I40E_ERR_NO_MEMORY;
6513 for (i = 0; i < vlan_num; i++) {
6514 mv_f[i].filter_type = filter_type;
6515 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6518 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6519 filter_type == RTE_MACVLAN_HASH_MATCH) {
6520 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6521 if (ret != I40E_SUCCESS)
6525 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6526 if (ret != I40E_SUCCESS)
6529 /* Remove the mac addr into mac list */
6530 TAILQ_REMOVE(&vsi->mac_list, f, next);
6540 /* Configure hash enable flags for RSS */
6542 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6549 if (flags & ETH_RSS_FRAG_IPV4)
6550 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6551 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6552 if (type == I40E_MAC_X722) {
6553 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6554 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6556 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6558 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6559 if (type == I40E_MAC_X722) {
6560 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6561 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6562 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6564 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6566 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6567 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6568 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6569 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6570 if (flags & ETH_RSS_FRAG_IPV6)
6571 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6572 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6573 if (type == I40E_MAC_X722) {
6574 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6575 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6577 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6579 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6580 if (type == I40E_MAC_X722) {
6581 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6582 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6583 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6585 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6587 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6588 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6589 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6590 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6591 if (flags & ETH_RSS_L2_PAYLOAD)
6592 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6597 /* Parse the hash enable flags */
6599 i40e_parse_hena(uint64_t flags)
6601 uint64_t rss_hf = 0;
6605 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6606 rss_hf |= ETH_RSS_FRAG_IPV4;
6607 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6608 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6609 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6610 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6611 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6612 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6613 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6614 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6615 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6616 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6617 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6618 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6619 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6620 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6621 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6622 rss_hf |= ETH_RSS_FRAG_IPV6;
6623 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6624 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6625 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6626 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6627 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6628 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6629 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6630 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6631 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6632 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6633 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6634 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6635 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6636 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6637 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6638 rss_hf |= ETH_RSS_L2_PAYLOAD;
6645 i40e_pf_disable_rss(struct i40e_pf *pf)
6647 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6650 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6651 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6652 if (hw->mac.type == I40E_MAC_X722)
6653 hena &= ~I40E_RSS_HENA_ALL_X722;
6655 hena &= ~I40E_RSS_HENA_ALL;
6656 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6657 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6658 I40E_WRITE_FLUSH(hw);
6662 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6664 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6665 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6668 if (!key || key_len == 0) {
6669 PMD_DRV_LOG(DEBUG, "No key to be configured");
6671 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6673 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6677 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6678 struct i40e_aqc_get_set_rss_key_data *key_dw =
6679 (struct i40e_aqc_get_set_rss_key_data *)key;
6681 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6683 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6685 uint32_t *hash_key = (uint32_t *)key;
6688 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6689 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6690 I40E_WRITE_FLUSH(hw);
6697 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6699 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6700 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6703 if (!key || !key_len)
6706 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6707 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6708 (struct i40e_aqc_get_set_rss_key_data *)key);
6710 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6714 uint32_t *key_dw = (uint32_t *)key;
6717 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6718 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6720 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6726 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6728 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6733 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6734 rss_conf->rss_key_len);
6738 rss_hf = rss_conf->rss_hf;
6739 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6740 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6741 if (hw->mac.type == I40E_MAC_X722)
6742 hena &= ~I40E_RSS_HENA_ALL_X722;
6744 hena &= ~I40E_RSS_HENA_ALL;
6745 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6746 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6747 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6748 I40E_WRITE_FLUSH(hw);
6754 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6755 struct rte_eth_rss_conf *rss_conf)
6757 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6758 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6759 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6762 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6763 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6764 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6765 ? I40E_RSS_HENA_ALL_X722
6766 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6767 if (rss_hf != 0) /* Enable RSS */
6769 return 0; /* Nothing to do */
6772 if (rss_hf == 0) /* Disable RSS */
6775 return i40e_hw_rss_hash_set(pf, rss_conf);
6779 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6780 struct rte_eth_rss_conf *rss_conf)
6782 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6783 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6786 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6787 &rss_conf->rss_key_len);
6789 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6790 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6791 rss_conf->rss_hf = i40e_parse_hena(hena);
6797 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6799 switch (filter_type) {
6800 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6801 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6803 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6804 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6806 case RTE_TUNNEL_FILTER_IMAC_TENID:
6807 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6809 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6810 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6812 case ETH_TUNNEL_FILTER_IMAC:
6813 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6815 case ETH_TUNNEL_FILTER_OIP:
6816 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6818 case ETH_TUNNEL_FILTER_IIP:
6819 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6822 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6829 /* Convert tunnel filter structure */
6831 i40e_tunnel_filter_convert(
6832 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6833 struct i40e_tunnel_filter *tunnel_filter)
6835 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6836 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6837 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6838 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6839 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6840 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6841 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6842 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6843 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6845 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6846 tunnel_filter->input.flags = cld_filter->element.flags;
6847 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6848 tunnel_filter->queue = cld_filter->element.queue_number;
6849 rte_memcpy(tunnel_filter->input.general_fields,
6850 cld_filter->general_fields,
6851 sizeof(cld_filter->general_fields));
6856 /* Check if there exists the tunnel filter */
6857 struct i40e_tunnel_filter *
6858 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6859 const struct i40e_tunnel_filter_input *input)
6863 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6867 return tunnel_rule->hash_map[ret];
6870 /* Add a tunnel filter into the SW list */
6872 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6873 struct i40e_tunnel_filter *tunnel_filter)
6875 struct i40e_tunnel_rule *rule = &pf->tunnel;
6878 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6881 "Failed to insert tunnel filter to hash table %d!",
6885 rule->hash_map[ret] = tunnel_filter;
6887 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6892 /* Delete a tunnel filter from the SW list */
6894 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6895 struct i40e_tunnel_filter_input *input)
6897 struct i40e_tunnel_rule *rule = &pf->tunnel;
6898 struct i40e_tunnel_filter *tunnel_filter;
6901 ret = rte_hash_del_key(rule->hash_table, input);
6904 "Failed to delete tunnel filter to hash table %d!",
6908 tunnel_filter = rule->hash_map[ret];
6909 rule->hash_map[ret] = NULL;
6911 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6912 rte_free(tunnel_filter);
6918 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6919 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6924 uint8_t i, tun_type = 0;
6925 /* internal varialbe to convert ipv6 byte order */
6926 uint32_t convert_ipv6[4];
6928 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6929 struct i40e_vsi *vsi = pf->main_vsi;
6930 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6931 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6932 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6933 struct i40e_tunnel_filter *tunnel, *node;
6934 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6936 cld_filter = rte_zmalloc("tunnel_filter",
6937 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6940 if (NULL == cld_filter) {
6941 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6944 pfilter = cld_filter;
6946 ether_addr_copy(&tunnel_filter->outer_mac,
6947 (struct ether_addr *)&pfilter->element.outer_mac);
6948 ether_addr_copy(&tunnel_filter->inner_mac,
6949 (struct ether_addr *)&pfilter->element.inner_mac);
6951 pfilter->element.inner_vlan =
6952 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6953 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6954 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6955 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6956 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6957 &rte_cpu_to_le_32(ipv4_addr),
6958 sizeof(pfilter->element.ipaddr.v4.data));
6960 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6961 for (i = 0; i < 4; i++) {
6963 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6965 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6967 sizeof(pfilter->element.ipaddr.v6.data));
6970 /* check tunneled type */
6971 switch (tunnel_filter->tunnel_type) {
6972 case RTE_TUNNEL_TYPE_VXLAN:
6973 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6975 case RTE_TUNNEL_TYPE_NVGRE:
6976 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6978 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6979 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6982 /* Other tunnel types is not supported. */
6983 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6984 rte_free(cld_filter);
6988 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6989 &pfilter->element.flags);
6991 rte_free(cld_filter);
6995 pfilter->element.flags |= rte_cpu_to_le_16(
6996 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6997 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6998 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6999 pfilter->element.queue_number =
7000 rte_cpu_to_le_16(tunnel_filter->queue_id);
7002 /* Check if there is the filter in SW list */
7003 memset(&check_filter, 0, sizeof(check_filter));
7004 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7005 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7007 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7011 if (!add && !node) {
7012 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7017 ret = i40e_aq_add_cloud_filters(hw,
7018 vsi->seid, &cld_filter->element, 1);
7020 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7023 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7024 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7025 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7027 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7028 &cld_filter->element, 1);
7030 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7033 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7036 rte_free(cld_filter);
7040 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7041 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7042 #define I40E_TR_GENEVE_KEY_MASK 0x8
7043 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7044 #define I40E_TR_GRE_KEY_MASK 0x400
7045 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7046 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7049 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7051 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7052 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7053 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7054 enum i40e_status_code status = I40E_SUCCESS;
7056 memset(&filter_replace, 0,
7057 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7058 memset(&filter_replace_buf, 0,
7059 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7061 /* create L1 filter */
7062 filter_replace.old_filter_type =
7063 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7064 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7065 filter_replace.tr_bit = 0;
7067 /* Prepare the buffer, 3 entries */
7068 filter_replace_buf.data[0] =
7069 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7070 filter_replace_buf.data[0] |=
7071 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7072 filter_replace_buf.data[2] = 0xFF;
7073 filter_replace_buf.data[3] = 0xFF;
7074 filter_replace_buf.data[4] =
7075 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7076 filter_replace_buf.data[4] |=
7077 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7078 filter_replace_buf.data[7] = 0xF0;
7079 filter_replace_buf.data[8]
7080 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7081 filter_replace_buf.data[8] |=
7082 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7083 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7084 I40E_TR_GENEVE_KEY_MASK |
7085 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7086 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7087 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7088 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7090 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7091 &filter_replace_buf);
7096 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7098 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7099 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7100 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7101 enum i40e_status_code status = I40E_SUCCESS;
7104 memset(&filter_replace, 0,
7105 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7106 memset(&filter_replace_buf, 0,
7107 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7108 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7109 I40E_AQC_MIRROR_CLOUD_FILTER;
7110 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7111 filter_replace.new_filter_type =
7112 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7113 /* Prepare the buffer, 2 entries */
7114 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7115 filter_replace_buf.data[0] |=
7116 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7117 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7118 filter_replace_buf.data[4] |=
7119 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7120 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7121 &filter_replace_buf);
7126 memset(&filter_replace, 0,
7127 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7128 memset(&filter_replace_buf, 0,
7129 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7131 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7132 I40E_AQC_MIRROR_CLOUD_FILTER;
7133 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7134 filter_replace.new_filter_type =
7135 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7136 /* Prepare the buffer, 2 entries */
7137 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7138 filter_replace_buf.data[0] |=
7139 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7140 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7141 filter_replace_buf.data[4] |=
7142 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7144 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7145 &filter_replace_buf);
7150 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7151 struct i40e_tunnel_filter_conf *tunnel_filter,
7156 uint8_t i, tun_type = 0;
7157 /* internal variable to convert ipv6 byte order */
7158 uint32_t convert_ipv6[4];
7160 struct i40e_pf_vf *vf = NULL;
7161 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7162 struct i40e_vsi *vsi;
7163 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7164 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7165 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7166 struct i40e_tunnel_filter *tunnel, *node;
7167 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7169 bool big_buffer = 0;
7171 cld_filter = rte_zmalloc("tunnel_filter",
7172 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7175 if (cld_filter == NULL) {
7176 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7179 pfilter = cld_filter;
7181 ether_addr_copy(&tunnel_filter->outer_mac,
7182 (struct ether_addr *)&pfilter->element.outer_mac);
7183 ether_addr_copy(&tunnel_filter->inner_mac,
7184 (struct ether_addr *)&pfilter->element.inner_mac);
7186 pfilter->element.inner_vlan =
7187 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7188 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7189 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7190 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7191 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7192 &rte_cpu_to_le_32(ipv4_addr),
7193 sizeof(pfilter->element.ipaddr.v4.data));
7195 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7196 for (i = 0; i < 4; i++) {
7198 rte_cpu_to_le_32(rte_be_to_cpu_32(
7199 tunnel_filter->ip_addr.ipv6_addr[i]));
7201 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7203 sizeof(pfilter->element.ipaddr.v6.data));
7206 /* check tunneled type */
7207 switch (tunnel_filter->tunnel_type) {
7208 case I40E_TUNNEL_TYPE_VXLAN:
7209 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7211 case I40E_TUNNEL_TYPE_NVGRE:
7212 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7214 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7215 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7217 case I40E_TUNNEL_TYPE_MPLSoUDP:
7218 if (!pf->mpls_replace_flag) {
7219 i40e_replace_mpls_l1_filter(pf);
7220 i40e_replace_mpls_cloud_filter(pf);
7221 pf->mpls_replace_flag = 1;
7223 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7224 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7226 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7227 (teid_le & 0xF) << 12;
7228 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7231 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7233 case I40E_TUNNEL_TYPE_MPLSoGRE:
7234 if (!pf->mpls_replace_flag) {
7235 i40e_replace_mpls_l1_filter(pf);
7236 i40e_replace_mpls_cloud_filter(pf);
7237 pf->mpls_replace_flag = 1;
7239 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7240 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7242 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7243 (teid_le & 0xF) << 12;
7244 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7247 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7249 case I40E_TUNNEL_TYPE_QINQ:
7250 if (!pf->qinq_replace_flag) {
7251 ret = i40e_cloud_filter_qinq_create(pf);
7254 "QinQ tunnel filter already created.");
7255 pf->qinq_replace_flag = 1;
7257 /* Add in the General fields the values of
7258 * the Outer and Inner VLAN
7259 * Big Buffer should be set, see changes in
7260 * i40e_aq_add_cloud_filters
7262 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7263 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7267 /* Other tunnel types is not supported. */
7268 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7269 rte_free(cld_filter);
7273 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7274 pfilter->element.flags =
7275 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7276 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7277 pfilter->element.flags =
7278 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7279 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7280 pfilter->element.flags |=
7281 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7283 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7284 &pfilter->element.flags);
7286 rte_free(cld_filter);
7291 pfilter->element.flags |= rte_cpu_to_le_16(
7292 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7293 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7294 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7295 pfilter->element.queue_number =
7296 rte_cpu_to_le_16(tunnel_filter->queue_id);
7298 if (!tunnel_filter->is_to_vf)
7301 if (tunnel_filter->vf_id >= pf->vf_num) {
7302 PMD_DRV_LOG(ERR, "Invalid argument.");
7305 vf = &pf->vfs[tunnel_filter->vf_id];
7309 /* Check if there is the filter in SW list */
7310 memset(&check_filter, 0, sizeof(check_filter));
7311 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7312 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7313 check_filter.vf_id = tunnel_filter->vf_id;
7314 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7316 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7320 if (!add && !node) {
7321 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7327 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7328 vsi->seid, cld_filter, 1);
7330 ret = i40e_aq_add_cloud_filters(hw,
7331 vsi->seid, &cld_filter->element, 1);
7333 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7336 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7337 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7338 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7341 ret = i40e_aq_remove_cloud_filters_big_buffer(
7342 hw, vsi->seid, cld_filter, 1);
7344 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7345 &cld_filter->element, 1);
7347 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7350 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7353 rte_free(cld_filter);
7358 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7362 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7363 if (pf->vxlan_ports[i] == port)
7371 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7375 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7377 idx = i40e_get_vxlan_port_idx(pf, port);
7379 /* Check if port already exists */
7381 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7385 /* Now check if there is space to add the new port */
7386 idx = i40e_get_vxlan_port_idx(pf, 0);
7389 "Maximum number of UDP ports reached, not adding port %d",
7394 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7397 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7401 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7404 /* New port: add it and mark its index in the bitmap */
7405 pf->vxlan_ports[idx] = port;
7406 pf->vxlan_bitmap |= (1 << idx);
7408 if (!(pf->flags & I40E_FLAG_VXLAN))
7409 pf->flags |= I40E_FLAG_VXLAN;
7415 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7418 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7420 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7421 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7425 idx = i40e_get_vxlan_port_idx(pf, port);
7428 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7432 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7433 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7437 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7440 pf->vxlan_ports[idx] = 0;
7441 pf->vxlan_bitmap &= ~(1 << idx);
7443 if (!pf->vxlan_bitmap)
7444 pf->flags &= ~I40E_FLAG_VXLAN;
7449 /* Add UDP tunneling port */
7451 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7452 struct rte_eth_udp_tunnel *udp_tunnel)
7455 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7457 if (udp_tunnel == NULL)
7460 switch (udp_tunnel->prot_type) {
7461 case RTE_TUNNEL_TYPE_VXLAN:
7462 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7465 case RTE_TUNNEL_TYPE_GENEVE:
7466 case RTE_TUNNEL_TYPE_TEREDO:
7467 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7472 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7480 /* Remove UDP tunneling port */
7482 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7483 struct rte_eth_udp_tunnel *udp_tunnel)
7486 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7488 if (udp_tunnel == NULL)
7491 switch (udp_tunnel->prot_type) {
7492 case RTE_TUNNEL_TYPE_VXLAN:
7493 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7495 case RTE_TUNNEL_TYPE_GENEVE:
7496 case RTE_TUNNEL_TYPE_TEREDO:
7497 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7501 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7509 /* Calculate the maximum number of contiguous PF queues that are configured */
7511 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7513 struct rte_eth_dev_data *data = pf->dev_data;
7515 struct i40e_rx_queue *rxq;
7518 for (i = 0; i < pf->lan_nb_qps; i++) {
7519 rxq = data->rx_queues[i];
7520 if (rxq && rxq->q_set)
7531 i40e_pf_config_rss(struct i40e_pf *pf)
7533 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7534 struct rte_eth_rss_conf rss_conf;
7535 uint32_t i, lut = 0;
7539 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7540 * It's necessary to calculate the actual PF queues that are configured.
7542 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7543 num = i40e_pf_calc_configured_queues_num(pf);
7545 num = pf->dev_data->nb_rx_queues;
7547 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7548 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7552 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7556 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7559 lut = (lut << 8) | (j & ((0x1 <<
7560 hw->func_caps.rss_table_entry_width) - 1));
7562 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7565 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7566 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7567 i40e_pf_disable_rss(pf);
7570 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7571 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7572 /* Random default keys */
7573 static uint32_t rss_key_default[] = {0x6b793944,
7574 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7575 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7576 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7578 rss_conf.rss_key = (uint8_t *)rss_key_default;
7579 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7583 return i40e_hw_rss_hash_set(pf, &rss_conf);
7587 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7588 struct rte_eth_tunnel_filter_conf *filter)
7590 if (pf == NULL || filter == NULL) {
7591 PMD_DRV_LOG(ERR, "Invalid parameter");
7595 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7596 PMD_DRV_LOG(ERR, "Invalid queue ID");
7600 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7601 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7605 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7606 (is_zero_ether_addr(&filter->outer_mac))) {
7607 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7611 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7612 (is_zero_ether_addr(&filter->inner_mac))) {
7613 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7620 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7621 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7623 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7628 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7629 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7632 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7633 } else if (len == 4) {
7634 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7636 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7641 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7648 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7649 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7655 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7662 switch (cfg->cfg_type) {
7663 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7664 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7667 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7675 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7676 enum rte_filter_op filter_op,
7679 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7680 int ret = I40E_ERR_PARAM;
7682 switch (filter_op) {
7683 case RTE_ETH_FILTER_SET:
7684 ret = i40e_dev_global_config_set(hw,
7685 (struct rte_eth_global_cfg *)arg);
7688 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7696 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7697 enum rte_filter_op filter_op,
7700 struct rte_eth_tunnel_filter_conf *filter;
7701 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7702 int ret = I40E_SUCCESS;
7704 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7706 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7707 return I40E_ERR_PARAM;
7709 switch (filter_op) {
7710 case RTE_ETH_FILTER_NOP:
7711 if (!(pf->flags & I40E_FLAG_VXLAN))
7712 ret = I40E_NOT_SUPPORTED;
7714 case RTE_ETH_FILTER_ADD:
7715 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7717 case RTE_ETH_FILTER_DELETE:
7718 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7721 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7722 ret = I40E_ERR_PARAM;
7730 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7733 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7736 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7737 ret = i40e_pf_config_rss(pf);
7739 i40e_pf_disable_rss(pf);
7744 /* Get the symmetric hash enable configurations per port */
7746 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7748 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7750 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7753 /* Set the symmetric hash enable configurations per port */
7755 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7757 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7760 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7762 "Symmetric hash has already been enabled");
7765 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7767 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7769 "Symmetric hash has already been disabled");
7772 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7774 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7775 I40E_WRITE_FLUSH(hw);
7779 * Get global configurations of hash function type and symmetric hash enable
7780 * per flow type (pctype). Note that global configuration means it affects all
7781 * the ports on the same NIC.
7784 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7785 struct rte_eth_hash_global_conf *g_cfg)
7787 uint32_t reg, mask = I40E_FLOW_TYPES;
7789 enum i40e_filter_pctype pctype;
7791 memset(g_cfg, 0, sizeof(*g_cfg));
7792 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7793 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7794 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7796 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7797 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7798 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7800 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7801 if (!(mask & (1UL << i)))
7803 mask &= ~(1UL << i);
7804 /* Bit set indicats the coresponding flow type is supported */
7805 g_cfg->valid_bit_mask[0] |= (1UL << i);
7806 /* if flowtype is invalid, continue */
7807 if (!I40E_VALID_FLOW(i))
7809 pctype = i40e_flowtype_to_pctype(i);
7810 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7811 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7812 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7819 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7822 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7824 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7825 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7826 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7827 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7833 * As i40e supports less than 32 flow types, only first 32 bits need to
7836 mask0 = g_cfg->valid_bit_mask[0];
7837 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7839 /* Check if any unsupported flow type configured */
7840 if ((mask0 | i40e_mask) ^ i40e_mask)
7843 if (g_cfg->valid_bit_mask[i])
7851 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7857 * Set global configurations of hash function type and symmetric hash enable
7858 * per flow type (pctype). Note any modifying global configuration will affect
7859 * all the ports on the same NIC.
7862 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7863 struct rte_eth_hash_global_conf *g_cfg)
7868 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7869 enum i40e_filter_pctype pctype;
7871 /* Check the input parameters */
7872 ret = i40e_hash_global_config_check(g_cfg);
7876 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7877 if (!(mask0 & (1UL << i)))
7879 mask0 &= ~(1UL << i);
7880 /* if flowtype is invalid, continue */
7881 if (!I40E_VALID_FLOW(i))
7883 pctype = i40e_flowtype_to_pctype(i);
7884 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7885 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7886 if (hw->mac.type == I40E_MAC_X722) {
7887 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7888 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7889 I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7890 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7891 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7893 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7894 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7896 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7897 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7898 I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7899 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7900 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7902 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7903 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7904 I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7905 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7906 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7908 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7909 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7911 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7912 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7913 I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7914 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7915 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7918 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7922 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7926 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7927 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7929 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7931 "Hash function already set to Toeplitz");
7934 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7935 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7937 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7939 "Hash function already set to Simple XOR");
7942 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7944 /* Use the default, and keep it as it is */
7947 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7950 I40E_WRITE_FLUSH(hw);
7956 * Valid input sets for hash and flow director filters per PCTYPE
7959 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7960 enum rte_filter_type filter)
7964 static const uint64_t valid_hash_inset_table[] = {
7965 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7966 I40E_INSET_DMAC | I40E_INSET_SMAC |
7967 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7968 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7969 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7970 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7971 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7972 I40E_INSET_FLEX_PAYLOAD,
7973 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7974 I40E_INSET_DMAC | I40E_INSET_SMAC |
7975 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7976 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7977 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7978 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7979 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7980 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7981 I40E_INSET_FLEX_PAYLOAD,
7982 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7983 I40E_INSET_DMAC | I40E_INSET_SMAC |
7984 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7985 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7986 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7987 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7988 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7989 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7990 I40E_INSET_FLEX_PAYLOAD,
7991 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7992 I40E_INSET_DMAC | I40E_INSET_SMAC |
7993 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7994 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7995 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7996 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7997 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7998 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7999 I40E_INSET_FLEX_PAYLOAD,
8000 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8001 I40E_INSET_DMAC | I40E_INSET_SMAC |
8002 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8003 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8004 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8005 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8006 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8007 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8008 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8009 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8010 I40E_INSET_DMAC | I40E_INSET_SMAC |
8011 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8012 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8013 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8014 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8015 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8016 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8017 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8018 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8019 I40E_INSET_DMAC | I40E_INSET_SMAC |
8020 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8021 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8022 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8023 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8024 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8025 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8026 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8027 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8028 I40E_INSET_DMAC | I40E_INSET_SMAC |
8029 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8030 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8031 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8032 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8033 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8034 I40E_INSET_FLEX_PAYLOAD,
8035 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8036 I40E_INSET_DMAC | I40E_INSET_SMAC |
8037 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8038 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8039 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8040 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8041 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8042 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8043 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8044 I40E_INSET_DMAC | I40E_INSET_SMAC |
8045 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8046 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8047 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8048 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8049 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8050 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8051 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8052 I40E_INSET_DMAC | I40E_INSET_SMAC |
8053 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8054 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8055 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8056 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8057 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8058 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8059 I40E_INSET_FLEX_PAYLOAD,
8060 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8061 I40E_INSET_DMAC | I40E_INSET_SMAC |
8062 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8063 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8064 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8065 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8066 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8067 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8068 I40E_INSET_FLEX_PAYLOAD,
8069 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8070 I40E_INSET_DMAC | I40E_INSET_SMAC |
8071 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8072 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8073 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8074 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8075 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8076 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8077 I40E_INSET_FLEX_PAYLOAD,
8078 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8079 I40E_INSET_DMAC | I40E_INSET_SMAC |
8080 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8081 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8082 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8083 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8084 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8085 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8086 I40E_INSET_FLEX_PAYLOAD,
8087 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8088 I40E_INSET_DMAC | I40E_INSET_SMAC |
8089 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8090 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8091 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8092 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8093 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8094 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8095 I40E_INSET_FLEX_PAYLOAD,
8096 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8097 I40E_INSET_DMAC | I40E_INSET_SMAC |
8098 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8099 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8100 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8101 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8102 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8103 I40E_INSET_FLEX_PAYLOAD,
8104 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8105 I40E_INSET_DMAC | I40E_INSET_SMAC |
8106 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8107 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8108 I40E_INSET_FLEX_PAYLOAD,
8112 * Flow director supports only fields defined in
8113 * union rte_eth_fdir_flow.
8115 static const uint64_t valid_fdir_inset_table[] = {
8116 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8117 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8118 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8119 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8120 I40E_INSET_IPV4_TTL,
8121 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8122 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8123 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8124 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8125 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8126 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8127 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8128 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8129 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8130 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8131 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8132 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8133 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8134 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8135 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8136 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8137 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8138 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8139 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8140 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8141 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8142 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8143 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8144 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8145 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8146 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8147 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8148 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8149 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8150 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8152 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8153 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8154 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8155 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8156 I40E_INSET_IPV4_TTL,
8157 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8158 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8159 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8160 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8161 I40E_INSET_IPV6_HOP_LIMIT,
8162 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8163 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8164 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8165 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8166 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8167 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8168 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8169 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8170 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8171 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8172 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8173 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8174 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8175 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8176 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8177 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8178 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8179 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8180 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8181 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8182 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8183 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8184 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8185 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8186 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8187 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8188 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8189 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8190 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8191 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8193 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8194 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8195 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8196 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8197 I40E_INSET_IPV6_HOP_LIMIT,
8198 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8199 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8200 I40E_INSET_LAST_ETHER_TYPE,
8203 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8205 if (filter == RTE_ETH_FILTER_HASH)
8206 valid = valid_hash_inset_table[pctype];
8208 valid = valid_fdir_inset_table[pctype];
8214 * Validate if the input set is allowed for a specific PCTYPE
8217 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8218 enum rte_filter_type filter, uint64_t inset)
8222 valid = i40e_get_valid_input_set(pctype, filter);
8223 if (inset & (~valid))
8229 /* default input set fields combination per pctype */
8231 i40e_get_default_input_set(uint16_t pctype)
8233 static const uint64_t default_inset_table[] = {
8234 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8235 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8236 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8237 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8238 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8239 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8240 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8241 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8242 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8243 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8244 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8245 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8246 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8247 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8248 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8249 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8250 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8251 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8252 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8253 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8255 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8256 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8257 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8258 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8259 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8260 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8261 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8262 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8263 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8264 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8265 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8266 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8267 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8268 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8269 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8270 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8271 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8272 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8273 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8274 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8275 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8276 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8278 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8279 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8280 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8281 I40E_INSET_LAST_ETHER_TYPE,
8284 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8287 return default_inset_table[pctype];
8291 * Parse the input set from index to logical bit masks
8294 i40e_parse_input_set(uint64_t *inset,
8295 enum i40e_filter_pctype pctype,
8296 enum rte_eth_input_set_field *field,
8302 static const struct {
8303 enum rte_eth_input_set_field field;
8305 } inset_convert_table[] = {
8306 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8307 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8308 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8309 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8310 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8311 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8312 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8313 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8314 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8315 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8316 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8317 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8318 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8319 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8320 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8321 I40E_INSET_IPV6_NEXT_HDR},
8322 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8323 I40E_INSET_IPV6_HOP_LIMIT},
8324 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8325 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8326 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8327 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8328 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8329 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8330 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8331 I40E_INSET_SCTP_VT},
8332 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8333 I40E_INSET_TUNNEL_DMAC},
8334 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8335 I40E_INSET_VLAN_TUNNEL},
8336 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8337 I40E_INSET_TUNNEL_ID},
8338 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8339 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8340 I40E_INSET_FLEX_PAYLOAD_W1},
8341 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8342 I40E_INSET_FLEX_PAYLOAD_W2},
8343 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8344 I40E_INSET_FLEX_PAYLOAD_W3},
8345 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8346 I40E_INSET_FLEX_PAYLOAD_W4},
8347 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8348 I40E_INSET_FLEX_PAYLOAD_W5},
8349 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8350 I40E_INSET_FLEX_PAYLOAD_W6},
8351 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8352 I40E_INSET_FLEX_PAYLOAD_W7},
8353 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8354 I40E_INSET_FLEX_PAYLOAD_W8},
8357 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8360 /* Only one item allowed for default or all */
8362 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8363 *inset = i40e_get_default_input_set(pctype);
8365 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8366 *inset = I40E_INSET_NONE;
8371 for (i = 0, *inset = 0; i < size; i++) {
8372 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8373 if (field[i] == inset_convert_table[j].field) {
8374 *inset |= inset_convert_table[j].inset;
8379 /* It contains unsupported input set, return immediately */
8380 if (j == RTE_DIM(inset_convert_table))
8388 * Translate the input set from bit masks to register aware bit masks
8392 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8402 static const struct inset_map inset_map_common[] = {
8403 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8404 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8405 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8406 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8407 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8408 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8409 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8410 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8411 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8412 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8413 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8414 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8415 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8416 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8417 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8418 {I40E_INSET_TUNNEL_DMAC,
8419 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8420 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8421 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8422 {I40E_INSET_TUNNEL_SRC_PORT,
8423 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8424 {I40E_INSET_TUNNEL_DST_PORT,
8425 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8426 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8427 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8428 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8429 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8430 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8431 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8432 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8433 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8434 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8437 /* some different registers map in x722*/
8438 static const struct inset_map inset_map_diff_x722[] = {
8439 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8440 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8441 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8442 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8445 static const struct inset_map inset_map_diff_not_x722[] = {
8446 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8447 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8448 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8449 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8455 /* Translate input set to register aware inset */
8456 if (type == I40E_MAC_X722) {
8457 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8458 if (input & inset_map_diff_x722[i].inset)
8459 val |= inset_map_diff_x722[i].inset_reg;
8462 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8463 if (input & inset_map_diff_not_x722[i].inset)
8464 val |= inset_map_diff_not_x722[i].inset_reg;
8468 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8469 if (input & inset_map_common[i].inset)
8470 val |= inset_map_common[i].inset_reg;
8477 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8480 uint64_t inset_need_mask = inset;
8482 static const struct {
8485 } inset_mask_map[] = {
8486 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8487 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8488 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8489 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8490 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8491 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8492 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8493 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8496 if (!inset || !mask || !nb_elem)
8499 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8500 /* Clear the inset bit, if no MASK is required,
8501 * for example proto + ttl
8503 if ((inset & inset_mask_map[i].inset) ==
8504 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8505 inset_need_mask &= ~inset_mask_map[i].inset;
8506 if (!inset_need_mask)
8509 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8510 if ((inset_need_mask & inset_mask_map[i].inset) ==
8511 inset_mask_map[i].inset) {
8512 if (idx >= nb_elem) {
8513 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8516 mask[idx] = inset_mask_map[i].mask;
8525 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8527 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8529 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8531 i40e_write_rx_ctl(hw, addr, val);
8532 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8533 (uint32_t)i40e_read_rx_ctl(hw, addr));
8537 i40e_filter_input_set_init(struct i40e_pf *pf)
8539 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8540 enum i40e_filter_pctype pctype;
8541 uint64_t input_set, inset_reg;
8542 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8545 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8546 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8547 if (hw->mac.type == I40E_MAC_X722) {
8548 if (!I40E_VALID_PCTYPE_X722(pctype))
8551 if (!I40E_VALID_PCTYPE(pctype))
8555 input_set = i40e_get_default_input_set(pctype);
8557 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8558 I40E_INSET_MASK_NUM_REG);
8561 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8564 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8565 (uint32_t)(inset_reg & UINT32_MAX));
8566 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8567 (uint32_t)((inset_reg >>
8568 I40E_32_BIT_WIDTH) & UINT32_MAX));
8569 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8570 (uint32_t)(inset_reg & UINT32_MAX));
8571 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8572 (uint32_t)((inset_reg >>
8573 I40E_32_BIT_WIDTH) & UINT32_MAX));
8575 for (i = 0; i < num; i++) {
8576 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8578 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8581 /*clear unused mask registers of the pctype */
8582 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8583 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8585 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8588 I40E_WRITE_FLUSH(hw);
8590 /* store the default input set */
8591 pf->hash_input_set[pctype] = input_set;
8592 pf->fdir.input_set[pctype] = input_set;
8597 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8598 struct rte_eth_input_set_conf *conf)
8600 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8601 enum i40e_filter_pctype pctype;
8602 uint64_t input_set, inset_reg = 0;
8603 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8607 PMD_DRV_LOG(ERR, "Invalid pointer");
8610 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8611 conf->op != RTE_ETH_INPUT_SET_ADD) {
8612 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8616 if (!I40E_VALID_FLOW(conf->flow_type)) {
8617 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8621 if (hw->mac.type == I40E_MAC_X722) {
8622 /* get translated pctype value in fd pctype register */
8623 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8624 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8627 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8629 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8632 PMD_DRV_LOG(ERR, "Failed to parse input set");
8635 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8637 PMD_DRV_LOG(ERR, "Invalid input set");
8640 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8641 /* get inset value in register */
8642 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8643 inset_reg <<= I40E_32_BIT_WIDTH;
8644 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8645 input_set |= pf->hash_input_set[pctype];
8647 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8648 I40E_INSET_MASK_NUM_REG);
8652 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8654 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8655 (uint32_t)(inset_reg & UINT32_MAX));
8656 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8657 (uint32_t)((inset_reg >>
8658 I40E_32_BIT_WIDTH) & UINT32_MAX));
8660 for (i = 0; i < num; i++)
8661 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8663 /*clear unused mask registers of the pctype */
8664 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8665 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8667 I40E_WRITE_FLUSH(hw);
8669 pf->hash_input_set[pctype] = input_set;
8674 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8675 struct rte_eth_input_set_conf *conf)
8677 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8678 enum i40e_filter_pctype pctype;
8679 uint64_t input_set, inset_reg = 0;
8680 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8684 PMD_DRV_LOG(ERR, "Invalid pointer");
8687 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8688 conf->op != RTE_ETH_INPUT_SET_ADD) {
8689 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8693 if (!I40E_VALID_FLOW(conf->flow_type)) {
8694 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8698 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8700 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8703 PMD_DRV_LOG(ERR, "Failed to parse input set");
8706 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8708 PMD_DRV_LOG(ERR, "Invalid input set");
8712 /* get inset value in register */
8713 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8714 inset_reg <<= I40E_32_BIT_WIDTH;
8715 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8717 /* Can not change the inset reg for flex payload for fdir,
8718 * it is done by writing I40E_PRTQF_FD_FLXINSET
8719 * in i40e_set_flex_mask_on_pctype.
8721 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8722 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8724 input_set |= pf->fdir.input_set[pctype];
8725 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8726 I40E_INSET_MASK_NUM_REG);
8730 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8732 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8733 (uint32_t)(inset_reg & UINT32_MAX));
8734 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8735 (uint32_t)((inset_reg >>
8736 I40E_32_BIT_WIDTH) & UINT32_MAX));
8738 for (i = 0; i < num; i++)
8739 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8741 /*clear unused mask registers of the pctype */
8742 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8743 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8745 I40E_WRITE_FLUSH(hw);
8747 pf->fdir.input_set[pctype] = input_set;
8752 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8757 PMD_DRV_LOG(ERR, "Invalid pointer");
8761 switch (info->info_type) {
8762 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8763 i40e_get_symmetric_hash_enable_per_port(hw,
8764 &(info->info.enable));
8766 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8767 ret = i40e_get_hash_filter_global_config(hw,
8768 &(info->info.global_conf));
8771 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8781 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8786 PMD_DRV_LOG(ERR, "Invalid pointer");
8790 switch (info->info_type) {
8791 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8792 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8794 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8795 ret = i40e_set_hash_filter_global_config(hw,
8796 &(info->info.global_conf));
8798 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8799 ret = i40e_hash_filter_inset_select(hw,
8800 &(info->info.input_set_conf));
8804 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8813 /* Operations for hash function */
8815 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8816 enum rte_filter_op filter_op,
8819 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8822 switch (filter_op) {
8823 case RTE_ETH_FILTER_NOP:
8825 case RTE_ETH_FILTER_GET:
8826 ret = i40e_hash_filter_get(hw,
8827 (struct rte_eth_hash_filter_info *)arg);
8829 case RTE_ETH_FILTER_SET:
8830 ret = i40e_hash_filter_set(hw,
8831 (struct rte_eth_hash_filter_info *)arg);
8834 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8843 /* Convert ethertype filter structure */
8845 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8846 struct i40e_ethertype_filter *filter)
8848 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8849 filter->input.ether_type = input->ether_type;
8850 filter->flags = input->flags;
8851 filter->queue = input->queue;
8856 /* Check if there exists the ehtertype filter */
8857 struct i40e_ethertype_filter *
8858 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8859 const struct i40e_ethertype_filter_input *input)
8863 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8867 return ethertype_rule->hash_map[ret];
8870 /* Add ethertype filter in SW list */
8872 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8873 struct i40e_ethertype_filter *filter)
8875 struct i40e_ethertype_rule *rule = &pf->ethertype;
8878 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8881 "Failed to insert ethertype filter"
8882 " to hash table %d!",
8886 rule->hash_map[ret] = filter;
8888 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8893 /* Delete ethertype filter in SW list */
8895 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8896 struct i40e_ethertype_filter_input *input)
8898 struct i40e_ethertype_rule *rule = &pf->ethertype;
8899 struct i40e_ethertype_filter *filter;
8902 ret = rte_hash_del_key(rule->hash_table, input);
8905 "Failed to delete ethertype filter"
8906 " to hash table %d!",
8910 filter = rule->hash_map[ret];
8911 rule->hash_map[ret] = NULL;
8913 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8920 * Configure ethertype filter, which can director packet by filtering
8921 * with mac address and ether_type or only ether_type
8924 i40e_ethertype_filter_set(struct i40e_pf *pf,
8925 struct rte_eth_ethertype_filter *filter,
8928 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8929 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8930 struct i40e_ethertype_filter *ethertype_filter, *node;
8931 struct i40e_ethertype_filter check_filter;
8932 struct i40e_control_filter_stats stats;
8936 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8937 PMD_DRV_LOG(ERR, "Invalid queue ID");
8940 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8941 filter->ether_type == ETHER_TYPE_IPv6) {
8943 "unsupported ether_type(0x%04x) in control packet filter.",
8944 filter->ether_type);
8947 if (filter->ether_type == ETHER_TYPE_VLAN)
8948 PMD_DRV_LOG(WARNING,
8949 "filter vlan ether_type in first tag is not supported.");
8951 /* Check if there is the filter in SW list */
8952 memset(&check_filter, 0, sizeof(check_filter));
8953 i40e_ethertype_filter_convert(filter, &check_filter);
8954 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8955 &check_filter.input);
8957 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8961 if (!add && !node) {
8962 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8966 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8967 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8968 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8969 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8970 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8972 memset(&stats, 0, sizeof(stats));
8973 ret = i40e_aq_add_rem_control_packet_filter(hw,
8974 filter->mac_addr.addr_bytes,
8975 filter->ether_type, flags,
8977 filter->queue, add, &stats, NULL);
8980 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8981 ret, stats.mac_etype_used, stats.etype_used,
8982 stats.mac_etype_free, stats.etype_free);
8986 /* Add or delete a filter in SW list */
8988 ethertype_filter = rte_zmalloc("ethertype_filter",
8989 sizeof(*ethertype_filter), 0);
8990 rte_memcpy(ethertype_filter, &check_filter,
8991 sizeof(check_filter));
8992 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8994 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9001 * Handle operations for ethertype filter.
9004 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9005 enum rte_filter_op filter_op,
9008 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9011 if (filter_op == RTE_ETH_FILTER_NOP)
9015 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9020 switch (filter_op) {
9021 case RTE_ETH_FILTER_ADD:
9022 ret = i40e_ethertype_filter_set(pf,
9023 (struct rte_eth_ethertype_filter *)arg,
9026 case RTE_ETH_FILTER_DELETE:
9027 ret = i40e_ethertype_filter_set(pf,
9028 (struct rte_eth_ethertype_filter *)arg,
9032 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9040 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9041 enum rte_filter_type filter_type,
9042 enum rte_filter_op filter_op,
9050 switch (filter_type) {
9051 case RTE_ETH_FILTER_NONE:
9052 /* For global configuration */
9053 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9055 case RTE_ETH_FILTER_HASH:
9056 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9058 case RTE_ETH_FILTER_MACVLAN:
9059 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9061 case RTE_ETH_FILTER_ETHERTYPE:
9062 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9064 case RTE_ETH_FILTER_TUNNEL:
9065 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9067 case RTE_ETH_FILTER_FDIR:
9068 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9070 case RTE_ETH_FILTER_GENERIC:
9071 if (filter_op != RTE_ETH_FILTER_GET)
9073 *(const void **)arg = &i40e_flow_ops;
9076 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9086 * Check and enable Extended Tag.
9087 * Enabling Extended Tag is important for 40G performance.
9090 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9092 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9096 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9099 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9103 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9104 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9109 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9112 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9116 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9117 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9120 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9121 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9124 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9131 * As some registers wouldn't be reset unless a global hardware reset,
9132 * hardware initialization is needed to put those registers into an
9133 * expected initial state.
9136 i40e_hw_init(struct rte_eth_dev *dev)
9138 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9140 i40e_enable_extended_tag(dev);
9142 /* clear the PF Queue Filter control register */
9143 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9145 /* Disable symmetric hash per port */
9146 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9149 enum i40e_filter_pctype
9150 i40e_flowtype_to_pctype(uint16_t flow_type)
9152 static const enum i40e_filter_pctype pctype_table[] = {
9153 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9154 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9155 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9156 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9157 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9158 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9159 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9160 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9161 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9162 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9163 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9164 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9165 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9166 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9167 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9168 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9169 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9170 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9171 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9174 return pctype_table[flow_type];
9178 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9180 static const uint16_t flowtype_table[] = {
9181 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9182 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9183 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9184 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9185 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9186 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9187 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9188 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9189 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9190 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9191 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9192 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9193 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9194 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9195 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9196 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9197 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9198 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9199 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9200 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9201 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9202 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9203 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9204 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9205 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9206 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9207 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9208 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9209 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9210 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9211 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9214 return flowtype_table[pctype];
9218 * On X710, performance number is far from the expectation on recent firmware
9219 * versions; on XL710, performance number is also far from the expectation on
9220 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9221 * mode is enabled and port MAC address is equal to the packet destination MAC
9222 * address. The fix for this issue may not be integrated in the following
9223 * firmware version. So the workaround in software driver is needed. It needs
9224 * to modify the initial values of 3 internal only registers for both X710 and
9225 * XL710. Note that the values for X710 or XL710 could be different, and the
9226 * workaround can be removed when it is fixed in firmware in the future.
9229 /* For both X710 and XL710 */
9230 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9231 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x20000200
9232 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9234 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9235 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9238 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9239 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9242 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9244 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9245 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9248 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9250 enum i40e_status_code status;
9251 struct i40e_aq_get_phy_abilities_resp phy_ab;
9254 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9258 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9267 i40e_configure_registers(struct i40e_hw *hw)
9273 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9274 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9275 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9281 for (i = 0; i < RTE_DIM(reg_table); i++) {
9282 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9283 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9285 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9286 else /* For X710/XL710/XXV710 */
9287 if (hw->aq.fw_maj_ver < 6)
9289 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9292 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9295 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9296 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9298 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9299 else /* For X710/XL710/XXV710 */
9301 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9304 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9305 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9306 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9308 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9311 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9314 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9317 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9321 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9322 reg_table[i].addr, reg);
9323 if (reg == reg_table[i].val)
9326 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9327 reg_table[i].val, NULL);
9330 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9331 reg_table[i].val, reg_table[i].addr);
9334 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9335 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9339 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9340 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9341 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9342 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9344 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9349 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9350 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9354 /* Configure for double VLAN RX stripping */
9355 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9356 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9357 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9358 ret = i40e_aq_debug_write_register(hw,
9359 I40E_VSI_TSR(vsi->vsi_id),
9362 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9364 return I40E_ERR_CONFIG;
9368 /* Configure for double VLAN TX insertion */
9369 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9370 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9371 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9372 ret = i40e_aq_debug_write_register(hw,
9373 I40E_VSI_L2TAGSTXVALID(
9374 vsi->vsi_id), reg, NULL);
9377 "Failed to update VSI_L2TAGSTXVALID[%d]",
9379 return I40E_ERR_CONFIG;
9387 * i40e_aq_add_mirror_rule
9388 * @hw: pointer to the hardware structure
9389 * @seid: VEB seid to add mirror rule to
9390 * @dst_id: destination vsi seid
9391 * @entries: Buffer which contains the entities to be mirrored
9392 * @count: number of entities contained in the buffer
9393 * @rule_id:the rule_id of the rule to be added
9395 * Add a mirror rule for a given veb.
9398 static enum i40e_status_code
9399 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9400 uint16_t seid, uint16_t dst_id,
9401 uint16_t rule_type, uint16_t *entries,
9402 uint16_t count, uint16_t *rule_id)
9404 struct i40e_aq_desc desc;
9405 struct i40e_aqc_add_delete_mirror_rule cmd;
9406 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9407 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9410 enum i40e_status_code status;
9412 i40e_fill_default_direct_cmd_desc(&desc,
9413 i40e_aqc_opc_add_mirror_rule);
9414 memset(&cmd, 0, sizeof(cmd));
9416 buff_len = sizeof(uint16_t) * count;
9417 desc.datalen = rte_cpu_to_le_16(buff_len);
9419 desc.flags |= rte_cpu_to_le_16(
9420 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9421 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9422 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9423 cmd.num_entries = rte_cpu_to_le_16(count);
9424 cmd.seid = rte_cpu_to_le_16(seid);
9425 cmd.destination = rte_cpu_to_le_16(dst_id);
9427 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9428 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9430 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9431 hw->aq.asq_last_status, resp->rule_id,
9432 resp->mirror_rules_used, resp->mirror_rules_free);
9433 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9439 * i40e_aq_del_mirror_rule
9440 * @hw: pointer to the hardware structure
9441 * @seid: VEB seid to add mirror rule to
9442 * @entries: Buffer which contains the entities to be mirrored
9443 * @count: number of entities contained in the buffer
9444 * @rule_id:the rule_id of the rule to be delete
9446 * Delete a mirror rule for a given veb.
9449 static enum i40e_status_code
9450 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9451 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9452 uint16_t count, uint16_t rule_id)
9454 struct i40e_aq_desc desc;
9455 struct i40e_aqc_add_delete_mirror_rule cmd;
9456 uint16_t buff_len = 0;
9457 enum i40e_status_code status;
9460 i40e_fill_default_direct_cmd_desc(&desc,
9461 i40e_aqc_opc_delete_mirror_rule);
9462 memset(&cmd, 0, sizeof(cmd));
9463 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9464 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9466 cmd.num_entries = count;
9467 buff_len = sizeof(uint16_t) * count;
9468 desc.datalen = rte_cpu_to_le_16(buff_len);
9469 buff = (void *)entries;
9471 /* rule id is filled in destination field for deleting mirror rule */
9472 cmd.destination = rte_cpu_to_le_16(rule_id);
9474 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9475 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9476 cmd.seid = rte_cpu_to_le_16(seid);
9478 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9479 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9485 * i40e_mirror_rule_set
9486 * @dev: pointer to the hardware structure
9487 * @mirror_conf: mirror rule info
9488 * @sw_id: mirror rule's sw_id
9489 * @on: enable/disable
9491 * set a mirror rule.
9495 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9496 struct rte_eth_mirror_conf *mirror_conf,
9497 uint8_t sw_id, uint8_t on)
9499 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9500 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9501 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9502 struct i40e_mirror_rule *parent = NULL;
9503 uint16_t seid, dst_seid, rule_id;
9507 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9509 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9511 "mirror rule can not be configured without veb or vfs.");
9514 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9515 PMD_DRV_LOG(ERR, "mirror table is full.");
9518 if (mirror_conf->dst_pool > pf->vf_num) {
9519 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9520 mirror_conf->dst_pool);
9524 seid = pf->main_vsi->veb->seid;
9526 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9527 if (sw_id <= it->index) {
9533 if (mirr_rule && sw_id == mirr_rule->index) {
9535 PMD_DRV_LOG(ERR, "mirror rule exists.");
9538 ret = i40e_aq_del_mirror_rule(hw, seid,
9539 mirr_rule->rule_type,
9541 mirr_rule->num_entries, mirr_rule->id);
9544 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9545 ret, hw->aq.asq_last_status);
9548 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9549 rte_free(mirr_rule);
9550 pf->nb_mirror_rule--;
9554 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9558 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9559 sizeof(struct i40e_mirror_rule) , 0);
9561 PMD_DRV_LOG(ERR, "failed to allocate memory");
9562 return I40E_ERR_NO_MEMORY;
9564 switch (mirror_conf->rule_type) {
9565 case ETH_MIRROR_VLAN:
9566 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9567 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9568 mirr_rule->entries[j] =
9569 mirror_conf->vlan.vlan_id[i];
9574 PMD_DRV_LOG(ERR, "vlan is not specified.");
9575 rte_free(mirr_rule);
9578 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9580 case ETH_MIRROR_VIRTUAL_POOL_UP:
9581 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9582 /* check if the specified pool bit is out of range */
9583 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9584 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9585 rte_free(mirr_rule);
9588 for (i = 0, j = 0; i < pf->vf_num; i++) {
9589 if (mirror_conf->pool_mask & (1ULL << i)) {
9590 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9594 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9595 /* add pf vsi to entries */
9596 mirr_rule->entries[j] = pf->main_vsi_seid;
9600 PMD_DRV_LOG(ERR, "pool is not specified.");
9601 rte_free(mirr_rule);
9604 /* egress and ingress in aq commands means from switch but not port */
9605 mirr_rule->rule_type =
9606 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9607 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9608 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9610 case ETH_MIRROR_UPLINK_PORT:
9611 /* egress and ingress in aq commands means from switch but not port*/
9612 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9614 case ETH_MIRROR_DOWNLINK_PORT:
9615 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9618 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9619 mirror_conf->rule_type);
9620 rte_free(mirr_rule);
9624 /* If the dst_pool is equal to vf_num, consider it as PF */
9625 if (mirror_conf->dst_pool == pf->vf_num)
9626 dst_seid = pf->main_vsi_seid;
9628 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9630 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9631 mirr_rule->rule_type, mirr_rule->entries,
9635 "failed to add mirror rule: ret = %d, aq_err = %d.",
9636 ret, hw->aq.asq_last_status);
9637 rte_free(mirr_rule);
9641 mirr_rule->index = sw_id;
9642 mirr_rule->num_entries = j;
9643 mirr_rule->id = rule_id;
9644 mirr_rule->dst_vsi_seid = dst_seid;
9647 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9649 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9651 pf->nb_mirror_rule++;
9656 * i40e_mirror_rule_reset
9657 * @dev: pointer to the device
9658 * @sw_id: mirror rule's sw_id
9660 * reset a mirror rule.
9664 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9666 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9667 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9668 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9672 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9674 seid = pf->main_vsi->veb->seid;
9676 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9677 if (sw_id == it->index) {
9683 ret = i40e_aq_del_mirror_rule(hw, seid,
9684 mirr_rule->rule_type,
9686 mirr_rule->num_entries, mirr_rule->id);
9689 "failed to remove mirror rule: status = %d, aq_err = %d.",
9690 ret, hw->aq.asq_last_status);
9693 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9694 rte_free(mirr_rule);
9695 pf->nb_mirror_rule--;
9697 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9704 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9706 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9707 uint64_t systim_cycles;
9709 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9710 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9713 return systim_cycles;
9717 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9719 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9722 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9723 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9730 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9732 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9735 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9736 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9743 i40e_start_timecounters(struct rte_eth_dev *dev)
9745 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9746 struct i40e_adapter *adapter =
9747 (struct i40e_adapter *)dev->data->dev_private;
9748 struct rte_eth_link link;
9749 uint32_t tsync_inc_l;
9750 uint32_t tsync_inc_h;
9752 /* Get current link speed. */
9753 memset(&link, 0, sizeof(link));
9754 i40e_dev_link_update(dev, 1);
9755 rte_i40e_dev_atomic_read_link_status(dev, &link);
9757 switch (link.link_speed) {
9758 case ETH_SPEED_NUM_40G:
9759 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9760 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9762 case ETH_SPEED_NUM_10G:
9763 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9764 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9766 case ETH_SPEED_NUM_1G:
9767 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9768 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9775 /* Set the timesync increment value. */
9776 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9777 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9779 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9780 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9781 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9783 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9784 adapter->systime_tc.cc_shift = 0;
9785 adapter->systime_tc.nsec_mask = 0;
9787 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9788 adapter->rx_tstamp_tc.cc_shift = 0;
9789 adapter->rx_tstamp_tc.nsec_mask = 0;
9791 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9792 adapter->tx_tstamp_tc.cc_shift = 0;
9793 adapter->tx_tstamp_tc.nsec_mask = 0;
9797 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9799 struct i40e_adapter *adapter =
9800 (struct i40e_adapter *)dev->data->dev_private;
9802 adapter->systime_tc.nsec += delta;
9803 adapter->rx_tstamp_tc.nsec += delta;
9804 adapter->tx_tstamp_tc.nsec += delta;
9810 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9813 struct i40e_adapter *adapter =
9814 (struct i40e_adapter *)dev->data->dev_private;
9816 ns = rte_timespec_to_ns(ts);
9818 /* Set the timecounters to a new value. */
9819 adapter->systime_tc.nsec = ns;
9820 adapter->rx_tstamp_tc.nsec = ns;
9821 adapter->tx_tstamp_tc.nsec = ns;
9827 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9829 uint64_t ns, systime_cycles;
9830 struct i40e_adapter *adapter =
9831 (struct i40e_adapter *)dev->data->dev_private;
9833 systime_cycles = i40e_read_systime_cyclecounter(dev);
9834 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9835 *ts = rte_ns_to_timespec(ns);
9841 i40e_timesync_enable(struct rte_eth_dev *dev)
9843 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9844 uint32_t tsync_ctl_l;
9845 uint32_t tsync_ctl_h;
9847 /* Stop the timesync system time. */
9848 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9849 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9850 /* Reset the timesync system time value. */
9851 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9852 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9854 i40e_start_timecounters(dev);
9856 /* Clear timesync registers. */
9857 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9858 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9859 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9860 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9861 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9862 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9864 /* Enable timestamping of PTP packets. */
9865 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9866 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9868 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9869 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9870 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9872 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9873 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9879 i40e_timesync_disable(struct rte_eth_dev *dev)
9881 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9882 uint32_t tsync_ctl_l;
9883 uint32_t tsync_ctl_h;
9885 /* Disable timestamping of transmitted PTP packets. */
9886 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9887 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9889 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9890 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9892 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9893 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9895 /* Reset the timesync increment value. */
9896 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9897 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9903 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9904 struct timespec *timestamp, uint32_t flags)
9906 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9907 struct i40e_adapter *adapter =
9908 (struct i40e_adapter *)dev->data->dev_private;
9910 uint32_t sync_status;
9911 uint32_t index = flags & 0x03;
9912 uint64_t rx_tstamp_cycles;
9915 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9916 if ((sync_status & (1 << index)) == 0)
9919 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9920 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9921 *timestamp = rte_ns_to_timespec(ns);
9927 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9928 struct timespec *timestamp)
9930 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9931 struct i40e_adapter *adapter =
9932 (struct i40e_adapter *)dev->data->dev_private;
9934 uint32_t sync_status;
9935 uint64_t tx_tstamp_cycles;
9938 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9939 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9942 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9943 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9944 *timestamp = rte_ns_to_timespec(ns);
9950 * i40e_parse_dcb_configure - parse dcb configure from user
9951 * @dev: the device being configured
9952 * @dcb_cfg: pointer of the result of parse
9953 * @*tc_map: bit map of enabled traffic classes
9955 * Returns 0 on success, negative value on failure
9958 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9959 struct i40e_dcbx_config *dcb_cfg,
9962 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9963 uint8_t i, tc_bw, bw_lf;
9965 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9967 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9968 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9969 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9973 /* assume each tc has the same bw */
9974 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9975 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9976 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9977 /* to ensure the sum of tcbw is equal to 100 */
9978 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9979 for (i = 0; i < bw_lf; i++)
9980 dcb_cfg->etscfg.tcbwtable[i]++;
9982 /* assume each tc has the same Transmission Selection Algorithm */
9983 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9984 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9986 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9987 dcb_cfg->etscfg.prioritytable[i] =
9988 dcb_rx_conf->dcb_tc[i];
9990 /* FW needs one App to configure HW */
9991 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9992 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9993 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9994 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9996 if (dcb_rx_conf->nb_tcs == 0)
9997 *tc_map = 1; /* tc0 only */
9999 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10001 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10002 dcb_cfg->pfc.willing = 0;
10003 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10004 dcb_cfg->pfc.pfcenable = *tc_map;
10010 static enum i40e_status_code
10011 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10012 struct i40e_aqc_vsi_properties_data *info,
10013 uint8_t enabled_tcmap)
10015 enum i40e_status_code ret;
10016 int i, total_tc = 0;
10017 uint16_t qpnum_per_tc, bsf, qp_idx;
10018 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10019 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10020 uint16_t used_queues;
10022 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10023 if (ret != I40E_SUCCESS)
10026 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10027 if (enabled_tcmap & (1 << i))
10032 vsi->enabled_tc = enabled_tcmap;
10034 /* different VSI has different queues assigned */
10035 if (vsi->type == I40E_VSI_MAIN)
10036 used_queues = dev_data->nb_rx_queues -
10037 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10038 else if (vsi->type == I40E_VSI_VMDQ2)
10039 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10041 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10042 return I40E_ERR_NO_AVAILABLE_VSI;
10045 qpnum_per_tc = used_queues / total_tc;
10046 /* Number of queues per enabled TC */
10047 if (qpnum_per_tc == 0) {
10048 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10049 return I40E_ERR_INVALID_QP_ID;
10051 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10052 I40E_MAX_Q_PER_TC);
10053 bsf = rte_bsf32(qpnum_per_tc);
10056 * Configure TC and queue mapping parameters, for enabled TC,
10057 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10058 * default queue will serve it.
10061 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10062 if (vsi->enabled_tc & (1 << i)) {
10063 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10064 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10065 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10066 qp_idx += qpnum_per_tc;
10068 info->tc_mapping[i] = 0;
10071 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10072 if (vsi->type == I40E_VSI_SRIOV) {
10073 info->mapping_flags |=
10074 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10075 for (i = 0; i < vsi->nb_qps; i++)
10076 info->queue_mapping[i] =
10077 rte_cpu_to_le_16(vsi->base_queue + i);
10079 info->mapping_flags |=
10080 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10081 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10083 info->valid_sections |=
10084 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10086 return I40E_SUCCESS;
10090 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10091 * @veb: VEB to be configured
10092 * @tc_map: enabled TC bitmap
10094 * Returns 0 on success, negative value on failure
10096 static enum i40e_status_code
10097 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10099 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10100 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10101 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10102 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10103 enum i40e_status_code ret = I40E_SUCCESS;
10107 /* Check if enabled_tc is same as existing or new TCs */
10108 if (veb->enabled_tc == tc_map)
10111 /* configure tc bandwidth */
10112 memset(&veb_bw, 0, sizeof(veb_bw));
10113 veb_bw.tc_valid_bits = tc_map;
10114 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10115 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10116 if (tc_map & BIT_ULL(i))
10117 veb_bw.tc_bw_share_credits[i] = 1;
10119 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10123 "AQ command Config switch_comp BW allocation per TC failed = %d",
10124 hw->aq.asq_last_status);
10128 memset(&ets_query, 0, sizeof(ets_query));
10129 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10131 if (ret != I40E_SUCCESS) {
10133 "Failed to get switch_comp ETS configuration %u",
10134 hw->aq.asq_last_status);
10137 memset(&bw_query, 0, sizeof(bw_query));
10138 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10140 if (ret != I40E_SUCCESS) {
10142 "Failed to get switch_comp bandwidth configuration %u",
10143 hw->aq.asq_last_status);
10147 /* store and print out BW info */
10148 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10149 veb->bw_info.bw_max = ets_query.tc_bw_max;
10150 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10151 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10152 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10153 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10154 I40E_16_BIT_WIDTH);
10155 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10156 veb->bw_info.bw_ets_share_credits[i] =
10157 bw_query.tc_bw_share_credits[i];
10158 veb->bw_info.bw_ets_credits[i] =
10159 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10160 /* 4 bits per TC, 4th bit is reserved */
10161 veb->bw_info.bw_ets_max[i] =
10162 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10163 RTE_LEN2MASK(3, uint8_t));
10164 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10165 veb->bw_info.bw_ets_share_credits[i]);
10166 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10167 veb->bw_info.bw_ets_credits[i]);
10168 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10169 veb->bw_info.bw_ets_max[i]);
10172 veb->enabled_tc = tc_map;
10179 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10180 * @vsi: VSI to be configured
10181 * @tc_map: enabled TC bitmap
10183 * Returns 0 on success, negative value on failure
10185 static enum i40e_status_code
10186 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10188 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10189 struct i40e_vsi_context ctxt;
10190 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10191 enum i40e_status_code ret = I40E_SUCCESS;
10194 /* Check if enabled_tc is same as existing or new TCs */
10195 if (vsi->enabled_tc == tc_map)
10198 /* configure tc bandwidth */
10199 memset(&bw_data, 0, sizeof(bw_data));
10200 bw_data.tc_valid_bits = tc_map;
10201 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10202 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10203 if (tc_map & BIT_ULL(i))
10204 bw_data.tc_bw_credits[i] = 1;
10206 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10209 "AQ command Config VSI BW allocation per TC failed = %d",
10210 hw->aq.asq_last_status);
10213 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10214 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10216 /* Update Queue Pairs Mapping for currently enabled UPs */
10217 ctxt.seid = vsi->seid;
10218 ctxt.pf_num = hw->pf_id;
10220 ctxt.uplink_seid = vsi->uplink_seid;
10221 ctxt.info = vsi->info;
10223 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10227 /* Update the VSI after updating the VSI queue-mapping information */
10228 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10230 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10231 hw->aq.asq_last_status);
10234 /* update the local VSI info with updated queue map */
10235 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10236 sizeof(vsi->info.tc_mapping));
10237 (void)rte_memcpy(&vsi->info.queue_mapping,
10238 &ctxt.info.queue_mapping,
10239 sizeof(vsi->info.queue_mapping));
10240 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10241 vsi->info.valid_sections = 0;
10243 /* query and update current VSI BW information */
10244 ret = i40e_vsi_get_bw_config(vsi);
10247 "Failed updating vsi bw info, err %s aq_err %s",
10248 i40e_stat_str(hw, ret),
10249 i40e_aq_str(hw, hw->aq.asq_last_status));
10253 vsi->enabled_tc = tc_map;
10260 * i40e_dcb_hw_configure - program the dcb setting to hw
10261 * @pf: pf the configuration is taken on
10262 * @new_cfg: new configuration
10263 * @tc_map: enabled TC bitmap
10265 * Returns 0 on success, negative value on failure
10267 static enum i40e_status_code
10268 i40e_dcb_hw_configure(struct i40e_pf *pf,
10269 struct i40e_dcbx_config *new_cfg,
10272 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10273 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10274 struct i40e_vsi *main_vsi = pf->main_vsi;
10275 struct i40e_vsi_list *vsi_list;
10276 enum i40e_status_code ret;
10280 /* Use the FW API if FW > v4.4*/
10281 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10282 (hw->aq.fw_maj_ver >= 5))) {
10284 "FW < v4.4, can not use FW LLDP API to configure DCB");
10285 return I40E_ERR_FIRMWARE_API_VERSION;
10288 /* Check if need reconfiguration */
10289 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10290 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10291 return I40E_SUCCESS;
10294 /* Copy the new config to the current config */
10295 *old_cfg = *new_cfg;
10296 old_cfg->etsrec = old_cfg->etscfg;
10297 ret = i40e_set_dcb_config(hw);
10299 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10300 i40e_stat_str(hw, ret),
10301 i40e_aq_str(hw, hw->aq.asq_last_status));
10304 /* set receive Arbiter to RR mode and ETS scheme by default */
10305 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10306 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10307 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10308 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10309 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10310 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10311 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10312 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10313 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10314 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10315 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10316 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10317 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10319 /* get local mib to check whether it is configured correctly */
10321 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10322 /* Get Local DCB Config */
10323 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10324 &hw->local_dcbx_config);
10326 /* if Veb is created, need to update TC of it at first */
10327 if (main_vsi->veb) {
10328 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10330 PMD_INIT_LOG(WARNING,
10331 "Failed configuring TC for VEB seid=%d",
10332 main_vsi->veb->seid);
10334 /* Update each VSI */
10335 i40e_vsi_config_tc(main_vsi, tc_map);
10336 if (main_vsi->veb) {
10337 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10338 /* Beside main VSI and VMDQ VSIs, only enable default
10339 * TC for other VSIs
10341 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10342 ret = i40e_vsi_config_tc(vsi_list->vsi,
10345 ret = i40e_vsi_config_tc(vsi_list->vsi,
10346 I40E_DEFAULT_TCMAP);
10348 PMD_INIT_LOG(WARNING,
10349 "Failed configuring TC for VSI seid=%d",
10350 vsi_list->vsi->seid);
10354 return I40E_SUCCESS;
10358 * i40e_dcb_init_configure - initial dcb config
10359 * @dev: device being configured
10360 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10362 * Returns 0 on success, negative value on failure
10365 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10367 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10368 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10371 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10372 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10376 /* DCB initialization:
10377 * Update DCB configuration from the Firmware and configure
10378 * LLDP MIB change event.
10380 if (sw_dcb == TRUE) {
10381 ret = i40e_init_dcb(hw);
10382 /* If lldp agent is stopped, the return value from
10383 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10384 * adminq status. Otherwise, it should return success.
10386 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10387 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10388 memset(&hw->local_dcbx_config, 0,
10389 sizeof(struct i40e_dcbx_config));
10390 /* set dcb default configuration */
10391 hw->local_dcbx_config.etscfg.willing = 0;
10392 hw->local_dcbx_config.etscfg.maxtcs = 0;
10393 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10394 hw->local_dcbx_config.etscfg.tsatable[0] =
10396 /* all UPs mapping to TC0 */
10397 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10398 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10399 hw->local_dcbx_config.etsrec =
10400 hw->local_dcbx_config.etscfg;
10401 hw->local_dcbx_config.pfc.willing = 0;
10402 hw->local_dcbx_config.pfc.pfccap =
10403 I40E_MAX_TRAFFIC_CLASS;
10404 /* FW needs one App to configure HW */
10405 hw->local_dcbx_config.numapps = 1;
10406 hw->local_dcbx_config.app[0].selector =
10407 I40E_APP_SEL_ETHTYPE;
10408 hw->local_dcbx_config.app[0].priority = 3;
10409 hw->local_dcbx_config.app[0].protocolid =
10410 I40E_APP_PROTOID_FCOE;
10411 ret = i40e_set_dcb_config(hw);
10414 "default dcb config fails. err = %d, aq_err = %d.",
10415 ret, hw->aq.asq_last_status);
10420 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10421 ret, hw->aq.asq_last_status);
10425 ret = i40e_aq_start_lldp(hw, NULL);
10426 if (ret != I40E_SUCCESS)
10427 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10429 ret = i40e_init_dcb(hw);
10431 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10433 "HW doesn't support DCBX offload.");
10438 "DCBX configuration failed, err = %d, aq_err = %d.",
10439 ret, hw->aq.asq_last_status);
10447 * i40e_dcb_setup - setup dcb related config
10448 * @dev: device being configured
10450 * Returns 0 on success, negative value on failure
10453 i40e_dcb_setup(struct rte_eth_dev *dev)
10455 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10456 struct i40e_dcbx_config dcb_cfg;
10457 uint8_t tc_map = 0;
10460 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10461 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10465 if (pf->vf_num != 0)
10466 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10468 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10470 PMD_INIT_LOG(ERR, "invalid dcb config");
10473 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10475 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10483 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10484 struct rte_eth_dcb_info *dcb_info)
10486 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10487 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10488 struct i40e_vsi *vsi = pf->main_vsi;
10489 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10490 uint16_t bsf, tc_mapping;
10493 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10494 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10496 dcb_info->nb_tcs = 1;
10497 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10498 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10499 for (i = 0; i < dcb_info->nb_tcs; i++)
10500 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10502 /* get queue mapping if vmdq is disabled */
10503 if (!pf->nb_cfg_vmdq_vsi) {
10504 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10505 if (!(vsi->enabled_tc & (1 << i)))
10507 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10508 dcb_info->tc_queue.tc_rxq[j][i].base =
10509 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10510 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10511 dcb_info->tc_queue.tc_txq[j][i].base =
10512 dcb_info->tc_queue.tc_rxq[j][i].base;
10513 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10514 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10515 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10516 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10517 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10522 /* get queue mapping if vmdq is enabled */
10524 vsi = pf->vmdq[j].vsi;
10525 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10526 if (!(vsi->enabled_tc & (1 << i)))
10528 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10529 dcb_info->tc_queue.tc_rxq[j][i].base =
10530 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10531 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10532 dcb_info->tc_queue.tc_txq[j][i].base =
10533 dcb_info->tc_queue.tc_rxq[j][i].base;
10534 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10535 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10536 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10537 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10538 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10541 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10546 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10548 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10549 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10550 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10551 uint16_t interval =
10552 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10553 uint16_t msix_intr;
10555 msix_intr = intr_handle->intr_vec[queue_id];
10556 if (msix_intr == I40E_MISC_VEC_ID)
10557 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10558 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10559 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10560 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10562 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10565 I40E_PFINT_DYN_CTLN(msix_intr -
10566 I40E_RX_VEC_START),
10567 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10568 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10569 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10571 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10573 I40E_WRITE_FLUSH(hw);
10574 rte_intr_enable(&pci_dev->intr_handle);
10580 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10582 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10583 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10584 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10585 uint16_t msix_intr;
10587 msix_intr = intr_handle->intr_vec[queue_id];
10588 if (msix_intr == I40E_MISC_VEC_ID)
10589 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10592 I40E_PFINT_DYN_CTLN(msix_intr -
10593 I40E_RX_VEC_START),
10595 I40E_WRITE_FLUSH(hw);
10600 static int i40e_get_regs(struct rte_eth_dev *dev,
10601 struct rte_dev_reg_info *regs)
10603 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10604 uint32_t *ptr_data = regs->data;
10605 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10606 const struct i40e_reg_info *reg_info;
10608 if (ptr_data == NULL) {
10609 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10610 regs->width = sizeof(uint32_t);
10614 /* The first few registers have to be read using AQ operations */
10616 while (i40e_regs_adminq[reg_idx].name) {
10617 reg_info = &i40e_regs_adminq[reg_idx++];
10618 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10620 arr_idx2 <= reg_info->count2;
10622 reg_offset = arr_idx * reg_info->stride1 +
10623 arr_idx2 * reg_info->stride2;
10624 reg_offset += reg_info->base_addr;
10625 ptr_data[reg_offset >> 2] =
10626 i40e_read_rx_ctl(hw, reg_offset);
10630 /* The remaining registers can be read using primitives */
10632 while (i40e_regs_others[reg_idx].name) {
10633 reg_info = &i40e_regs_others[reg_idx++];
10634 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10636 arr_idx2 <= reg_info->count2;
10638 reg_offset = arr_idx * reg_info->stride1 +
10639 arr_idx2 * reg_info->stride2;
10640 reg_offset += reg_info->base_addr;
10641 ptr_data[reg_offset >> 2] =
10642 I40E_READ_REG(hw, reg_offset);
10649 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10651 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10653 /* Convert word count to byte count */
10654 return hw->nvm.sr_size << 1;
10657 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10658 struct rte_dev_eeprom_info *eeprom)
10660 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10661 uint16_t *data = eeprom->data;
10662 uint16_t offset, length, cnt_words;
10665 offset = eeprom->offset >> 1;
10666 length = eeprom->length >> 1;
10667 cnt_words = length;
10669 if (offset > hw->nvm.sr_size ||
10670 offset + length > hw->nvm.sr_size) {
10671 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10675 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10677 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10678 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10679 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10686 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10687 struct ether_addr *mac_addr)
10689 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10691 if (!is_valid_assigned_ether_addr(mac_addr)) {
10692 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10696 /* Flags: 0x3 updates port address */
10697 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10701 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10703 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10704 struct rte_eth_dev_data *dev_data = pf->dev_data;
10705 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10708 /* check if mtu is within the allowed range */
10709 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10712 /* mtu setting is forbidden if port is start */
10713 if (dev_data->dev_started) {
10714 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10715 dev_data->port_id);
10719 if (frame_size > ETHER_MAX_LEN)
10720 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10722 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10724 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10729 /* Restore ethertype filter */
10731 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10733 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10734 struct i40e_ethertype_filter_list
10735 *ethertype_list = &pf->ethertype.ethertype_list;
10736 struct i40e_ethertype_filter *f;
10737 struct i40e_control_filter_stats stats;
10740 TAILQ_FOREACH(f, ethertype_list, rules) {
10742 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10743 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10744 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10745 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10746 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10748 memset(&stats, 0, sizeof(stats));
10749 i40e_aq_add_rem_control_packet_filter(hw,
10750 f->input.mac_addr.addr_bytes,
10751 f->input.ether_type,
10752 flags, pf->main_vsi->seid,
10753 f->queue, 1, &stats, NULL);
10755 PMD_DRV_LOG(INFO, "Ethertype filter:"
10756 " mac_etype_used = %u, etype_used = %u,"
10757 " mac_etype_free = %u, etype_free = %u",
10758 stats.mac_etype_used, stats.etype_used,
10759 stats.mac_etype_free, stats.etype_free);
10762 /* Restore tunnel filter */
10764 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10766 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10767 struct i40e_vsi *vsi;
10768 struct i40e_pf_vf *vf;
10769 struct i40e_tunnel_filter_list
10770 *tunnel_list = &pf->tunnel.tunnel_list;
10771 struct i40e_tunnel_filter *f;
10772 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10773 bool big_buffer = 0;
10775 TAILQ_FOREACH(f, tunnel_list, rules) {
10777 vsi = pf->main_vsi;
10779 vf = &pf->vfs[f->vf_id];
10782 memset(&cld_filter, 0, sizeof(cld_filter));
10783 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10784 (struct ether_addr *)&cld_filter.element.outer_mac);
10785 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10786 (struct ether_addr *)&cld_filter.element.inner_mac);
10787 cld_filter.element.inner_vlan = f->input.inner_vlan;
10788 cld_filter.element.flags = f->input.flags;
10789 cld_filter.element.tenant_id = f->input.tenant_id;
10790 cld_filter.element.queue_number = f->queue;
10791 rte_memcpy(cld_filter.general_fields,
10792 f->input.general_fields,
10793 sizeof(f->input.general_fields));
10795 if (((f->input.flags &
10796 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10797 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10799 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10800 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10802 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10803 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10807 i40e_aq_add_cloud_filters_big_buffer(hw,
10808 vsi->seid, &cld_filter, 1);
10810 i40e_aq_add_cloud_filters(hw, vsi->seid,
10811 &cld_filter.element, 1);
10816 i40e_filter_restore(struct i40e_pf *pf)
10818 i40e_ethertype_filter_restore(pf);
10819 i40e_tunnel_filter_restore(pf);
10820 i40e_fdir_filter_restore(pf);
10824 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10826 if (strcmp(dev->device->driver->name, drv->driver.name))
10833 is_i40e_supported(struct rte_eth_dev *dev)
10835 return is_device_supported(dev, &rte_i40e_pmd);
10838 /* Create a QinQ cloud filter
10840 * The Fortville NIC has limited resources for tunnel filters,
10841 * so we can only reuse existing filters.
10843 * In step 1 we define which Field Vector fields can be used for
10845 * As we do not have the inner tag defined as a field,
10846 * we have to define it first, by reusing one of L1 entries.
10848 * In step 2 we are replacing one of existing filter types with
10849 * a new one for QinQ.
10850 * As we reusing L1 and replacing L2, some of the default filter
10851 * types will disappear,which depends on L1 and L2 entries we reuse.
10853 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10855 * 1. Create L1 filter of outer vlan (12b) which will be in use
10856 * later when we define the cloud filter.
10857 * a. Valid_flags.replace_cloud = 0
10858 * b. Old_filter = 10 (Stag_Inner_Vlan)
10859 * c. New_filter = 0x10
10860 * d. TR bit = 0xff (optional, not used here)
10861 * e. Buffer – 2 entries:
10862 * i. Byte 0 = 8 (outer vlan FV index).
10864 * Byte 2-3 = 0x0fff
10865 * ii. Byte 0 = 37 (inner vlan FV index).
10867 * Byte 2-3 = 0x0fff
10870 * 2. Create cloud filter using two L1 filters entries: stag and
10871 * new filter(outer vlan+ inner vlan)
10872 * a. Valid_flags.replace_cloud = 1
10873 * b. Old_filter = 1 (instead of outer IP)
10874 * c. New_filter = 0x10
10875 * d. Buffer – 2 entries:
10876 * i. Byte 0 = 0x80 | 7 (valid | Stag).
10877 * Byte 1-3 = 0 (rsv)
10878 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10879 * Byte 9-11 = 0 (rsv)
10882 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10884 int ret = -ENOTSUP;
10885 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
10886 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
10887 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10890 memset(&filter_replace, 0,
10891 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10892 memset(&filter_replace_buf, 0,
10893 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10895 /* create L1 filter */
10896 filter_replace.old_filter_type =
10897 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10898 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10899 filter_replace.tr_bit = 0;
10901 /* Prepare the buffer, 2 entries */
10902 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10903 filter_replace_buf.data[0] |=
10904 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10905 /* Field Vector 12b mask */
10906 filter_replace_buf.data[2] = 0xff;
10907 filter_replace_buf.data[3] = 0x0f;
10908 filter_replace_buf.data[4] =
10909 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10910 filter_replace_buf.data[4] |=
10911 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10912 /* Field Vector 12b mask */
10913 filter_replace_buf.data[6] = 0xff;
10914 filter_replace_buf.data[7] = 0x0f;
10915 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10916 &filter_replace_buf);
10917 if (ret != I40E_SUCCESS)
10920 /* Apply the second L2 cloud filter */
10921 memset(&filter_replace, 0,
10922 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10923 memset(&filter_replace_buf, 0,
10924 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10926 /* create L2 filter, input for L2 filter will be L1 filter */
10927 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10928 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10929 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10931 /* Prepare the buffer, 2 entries */
10932 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10933 filter_replace_buf.data[0] |=
10934 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10935 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10936 filter_replace_buf.data[4] |=
10937 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10938 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10939 &filter_replace_buf);
10943 RTE_INIT(i40e_init_log);
10945 i40e_init_log(void)
10947 i40e_logtype_init = rte_log_register("pmd.i40e.init");
10948 if (i40e_logtype_init >= 0)
10949 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10950 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10951 if (i40e_logtype_driver >= 0)
10952 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);