1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
15 #include <rte_string_fns.h>
17 #include <rte_bus_pci.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_memzone.h>
22 #include <rte_malloc.h>
23 #include <rte_memcpy.h>
24 #include <rte_alarm.h>
26 #include <rte_eth_ctrl.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "i40e_ethdev.h"
37 #include "i40e_rxtx.h"
39 #include "i40e_regs.h"
40 #include "rte_pmd_i40e.h"
42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
45 #define I40E_CLEAR_PXE_WAIT_MS 200
47 /* Maximun number of capability elements */
48 #define I40E_MAX_CAP_ELE_NUM 128
50 /* Wait count and interval */
51 #define I40E_CHK_Q_ENA_COUNT 1000
52 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
54 /* Maximun number of VSI */
55 #define I40E_MAX_NUM_VSIS (384UL)
57 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
59 /* Flow control default timer */
60 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
62 /* Flow control enable fwd bit */
63 #define I40E_PRTMAC_FWD_CTRL 0x00000001
65 /* Receive Packet Buffer size */
66 #define I40E_RXPBSIZE (968 * 1024)
69 #define I40E_KILOSHIFT 10
71 /* Flow control default high water */
72 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
74 /* Flow control default low water */
75 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
77 /* Receive Average Packet Size in Byte*/
78 #define I40E_PACKET_AVERAGE_SIZE 128
80 /* Mask of PF interrupt causes */
81 #define I40E_PFINT_ICR0_ENA_MASK ( \
82 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
83 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
84 I40E_PFINT_ICR0_ENA_GRST_MASK | \
85 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
86 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
88 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
89 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
90 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
92 #define I40E_FLOW_TYPES ( \
93 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
94 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
95 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
96 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
98 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
103 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
105 /* Additional timesync values. */
106 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
107 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
108 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
109 #define I40E_PRTTSYN_TSYNENA 0x80000000
110 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
111 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
114 * Below are values for writing un-exposed registers suggested
117 /* Destination MAC address */
118 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
119 /* Source MAC address */
120 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
121 /* Outer (S-Tag) VLAN tag in the outer L2 header */
122 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
123 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
124 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
125 /* Single VLAN tag in the inner L2 header */
126 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
127 /* Source IPv4 address */
128 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
129 /* Destination IPv4 address */
130 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
131 /* Source IPv4 address for X722 */
132 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
133 /* Destination IPv4 address for X722 */
134 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
135 /* IPv4 Protocol for X722 */
136 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
137 /* IPv4 Time to Live for X722 */
138 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
139 /* IPv4 Type of Service (TOS) */
140 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
142 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
143 /* IPv4 Time to Live */
144 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
145 /* Source IPv6 address */
146 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
147 /* Destination IPv6 address */
148 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
149 /* IPv6 Traffic Class (TC) */
150 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
151 /* IPv6 Next Header */
152 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
154 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
156 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
157 /* Destination L4 port */
158 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
159 /* SCTP verification tag */
160 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
161 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
162 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
163 /* Source port of tunneling UDP */
164 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
165 /* Destination port of tunneling UDP */
166 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
167 /* UDP Tunneling ID, NVGRE/GRE key */
168 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
169 /* Last ether type */
170 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
171 /* Tunneling outer destination IPv4 address */
172 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
173 /* Tunneling outer destination IPv6 address */
174 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
175 /* 1st word of flex payload */
176 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
177 /* 2nd word of flex payload */
178 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
179 /* 3rd word of flex payload */
180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
181 /* 4th word of flex payload */
182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
183 /* 5th word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
185 /* 6th word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
187 /* 7th word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
189 /* 8th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
191 /* all 8 words flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
193 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
195 #define I40E_TRANSLATE_INSET 0
196 #define I40E_TRANSLATE_REG 1
198 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
199 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
200 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
201 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
202 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
203 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
205 /* PCI offset for querying capability */
206 #define PCI_DEV_CAP_REG 0xA4
207 /* PCI offset for enabling/disabling Extended Tag */
208 #define PCI_DEV_CTRL_REG 0xA8
209 /* Bit mask of Extended Tag capability */
210 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
211 /* Bit shift of Extended Tag enable/disable */
212 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
213 /* Bit mask of Extended Tag enable/disable */
214 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
216 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
217 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
218 static int i40e_dev_configure(struct rte_eth_dev *dev);
219 static int i40e_dev_start(struct rte_eth_dev *dev);
220 static void i40e_dev_stop(struct rte_eth_dev *dev);
221 static void i40e_dev_close(struct rte_eth_dev *dev);
222 static int i40e_dev_reset(struct rte_eth_dev *dev);
223 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
224 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
225 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
226 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
227 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
228 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
229 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
230 struct rte_eth_stats *stats);
231 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
232 struct rte_eth_xstat *xstats, unsigned n);
233 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
234 struct rte_eth_xstat_name *xstats_names,
236 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
237 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
242 char *fw_version, size_t fw_size);
243 static void i40e_dev_info_get(struct rte_eth_dev *dev,
244 struct rte_eth_dev_info *dev_info);
245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
249 enum rte_vlan_type vlan_type,
251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
259 struct rte_eth_fc_conf *fc_conf);
260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
261 struct rte_eth_fc_conf *fc_conf);
262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
263 struct rte_eth_pfc_conf *pfc_conf);
264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
265 struct ether_addr *mac_addr,
268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
270 struct rte_eth_rss_reta_entry64 *reta_conf,
272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
273 struct rte_eth_rss_reta_entry64 *reta_conf,
276 static int i40e_get_cap(struct i40e_hw *hw);
277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
278 static int i40e_pf_setup(struct i40e_pf *pf);
279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
283 bool offset_loaded, uint64_t *offset, uint64_t *stat);
284 static void i40e_stat_update_48(struct i40e_hw *hw,
290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
291 static void i40e_dev_interrupt_handler(void *param);
292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
293 uint32_t base, uint32_t num);
294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
300 static int i40e_veb_release(struct i40e_veb *veb);
301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
302 struct i40e_vsi *vsi);
303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
306 struct i40e_macvlan_filter *mv_f,
309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
311 struct rte_eth_rss_conf *rss_conf);
312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
313 struct rte_eth_rss_conf *rss_conf);
314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
315 struct rte_eth_udp_tunnel *udp_tunnel);
316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
317 struct rte_eth_udp_tunnel *udp_tunnel);
318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
320 enum rte_filter_op filter_op,
322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
323 enum rte_filter_type filter_type,
324 enum rte_filter_op filter_op,
326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
327 struct rte_eth_dcb_info *dcb_info);
328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
329 static void i40e_configure_registers(struct i40e_hw *hw);
330 static void i40e_hw_init(struct rte_eth_dev *dev);
331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
339 struct rte_eth_mirror_conf *mirror_conf,
340 uint8_t sw_id, uint8_t on);
341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
346 struct timespec *timestamp,
348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
349 struct timespec *timestamp);
350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
355 struct timespec *timestamp);
356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
357 const struct timespec *timestamp);
359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
364 static int i40e_get_regs(struct rte_eth_dev *dev,
365 struct rte_dev_reg_info *regs);
367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
370 struct rte_dev_eeprom_info *eeprom);
372 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
373 struct ether_addr *mac_addr);
375 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
377 static int i40e_ethertype_filter_convert(
378 const struct rte_eth_ethertype_filter *input,
379 struct i40e_ethertype_filter *filter);
380 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
381 struct i40e_ethertype_filter *filter);
383 static int i40e_tunnel_filter_convert(
384 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
385 struct i40e_tunnel_filter *tunnel_filter);
386 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
387 struct i40e_tunnel_filter *tunnel_filter);
388 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
390 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
391 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
392 static void i40e_filter_restore(struct i40e_pf *pf);
393 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
395 int i40e_logtype_init;
396 int i40e_logtype_driver;
398 static const struct rte_pci_id pci_id_i40e_map[] = {
399 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
400 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
401 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
402 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
403 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
404 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
405 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
406 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
407 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
408 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
409 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
410 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
411 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
419 { .vendor_id = 0, /* sentinel */ },
422 static const struct eth_dev_ops i40e_eth_dev_ops = {
423 .dev_configure = i40e_dev_configure,
424 .dev_start = i40e_dev_start,
425 .dev_stop = i40e_dev_stop,
426 .dev_close = i40e_dev_close,
427 .dev_reset = i40e_dev_reset,
428 .promiscuous_enable = i40e_dev_promiscuous_enable,
429 .promiscuous_disable = i40e_dev_promiscuous_disable,
430 .allmulticast_enable = i40e_dev_allmulticast_enable,
431 .allmulticast_disable = i40e_dev_allmulticast_disable,
432 .dev_set_link_up = i40e_dev_set_link_up,
433 .dev_set_link_down = i40e_dev_set_link_down,
434 .link_update = i40e_dev_link_update,
435 .stats_get = i40e_dev_stats_get,
436 .xstats_get = i40e_dev_xstats_get,
437 .xstats_get_names = i40e_dev_xstats_get_names,
438 .stats_reset = i40e_dev_stats_reset,
439 .xstats_reset = i40e_dev_stats_reset,
440 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
441 .fw_version_get = i40e_fw_version_get,
442 .dev_infos_get = i40e_dev_info_get,
443 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
444 .vlan_filter_set = i40e_vlan_filter_set,
445 .vlan_tpid_set = i40e_vlan_tpid_set,
446 .vlan_offload_set = i40e_vlan_offload_set,
447 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
448 .vlan_pvid_set = i40e_vlan_pvid_set,
449 .rx_queue_start = i40e_dev_rx_queue_start,
450 .rx_queue_stop = i40e_dev_rx_queue_stop,
451 .tx_queue_start = i40e_dev_tx_queue_start,
452 .tx_queue_stop = i40e_dev_tx_queue_stop,
453 .rx_queue_setup = i40e_dev_rx_queue_setup,
454 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
455 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
456 .rx_queue_release = i40e_dev_rx_queue_release,
457 .rx_queue_count = i40e_dev_rx_queue_count,
458 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
459 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
460 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
461 .tx_queue_setup = i40e_dev_tx_queue_setup,
462 .tx_queue_release = i40e_dev_tx_queue_release,
463 .dev_led_on = i40e_dev_led_on,
464 .dev_led_off = i40e_dev_led_off,
465 .flow_ctrl_get = i40e_flow_ctrl_get,
466 .flow_ctrl_set = i40e_flow_ctrl_set,
467 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
468 .mac_addr_add = i40e_macaddr_add,
469 .mac_addr_remove = i40e_macaddr_remove,
470 .reta_update = i40e_dev_rss_reta_update,
471 .reta_query = i40e_dev_rss_reta_query,
472 .rss_hash_update = i40e_dev_rss_hash_update,
473 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
474 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
475 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
476 .filter_ctrl = i40e_dev_filter_ctrl,
477 .rxq_info_get = i40e_rxq_info_get,
478 .txq_info_get = i40e_txq_info_get,
479 .mirror_rule_set = i40e_mirror_rule_set,
480 .mirror_rule_reset = i40e_mirror_rule_reset,
481 .timesync_enable = i40e_timesync_enable,
482 .timesync_disable = i40e_timesync_disable,
483 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
484 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
485 .get_dcb_info = i40e_dev_get_dcb_info,
486 .timesync_adjust_time = i40e_timesync_adjust_time,
487 .timesync_read_time = i40e_timesync_read_time,
488 .timesync_write_time = i40e_timesync_write_time,
489 .get_reg = i40e_get_regs,
490 .get_eeprom_length = i40e_get_eeprom_length,
491 .get_eeprom = i40e_get_eeprom,
492 .mac_addr_set = i40e_set_default_mac_addr,
493 .mtu_set = i40e_dev_mtu_set,
494 .tm_ops_get = i40e_tm_ops_get,
497 /* store statistics names and its offset in stats structure */
498 struct rte_i40e_xstats_name_off {
499 char name[RTE_ETH_XSTATS_NAME_SIZE];
503 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
504 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
505 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
506 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
507 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
508 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
509 rx_unknown_protocol)},
510 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
511 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
512 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
513 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
516 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
517 sizeof(rte_i40e_stats_strings[0]))
519 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
520 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
521 tx_dropped_link_down)},
522 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
523 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
525 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
526 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
528 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
530 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
532 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
533 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
534 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
535 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
536 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
537 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
539 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
541 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
543 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
545 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
547 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
549 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
551 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
553 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
554 mac_short_packet_dropped)},
555 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
557 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
558 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
559 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
561 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
563 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
565 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
567 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
569 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_flow_director_atr_match_packets",
572 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
573 {"rx_flow_director_sb_match_packets",
574 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
575 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
577 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
579 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
581 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
585 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
586 sizeof(rte_i40e_hw_port_strings[0]))
588 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
589 {"xon_packets", offsetof(struct i40e_hw_port_stats,
591 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
595 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
596 sizeof(rte_i40e_rxq_prio_strings[0]))
598 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
599 {"xon_packets", offsetof(struct i40e_hw_port_stats,
601 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
603 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
604 priority_xon_2_xoff)},
607 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
608 sizeof(rte_i40e_txq_prio_strings[0]))
610 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
611 struct rte_pci_device *pci_dev)
613 return rte_eth_dev_pci_generic_probe(pci_dev,
614 sizeof(struct i40e_adapter), eth_i40e_dev_init);
617 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
619 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
622 static struct rte_pci_driver rte_i40e_pmd = {
623 .id_table = pci_id_i40e_map,
624 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
625 RTE_PCI_DRV_IOVA_AS_VA,
626 .probe = eth_i40e_pci_probe,
627 .remove = eth_i40e_pci_remove,
631 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
632 struct rte_eth_link *link)
634 struct rte_eth_link *dst = link;
635 struct rte_eth_link *src = &(dev->data->dev_link);
637 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
638 *(uint64_t *)src) == 0)
645 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
646 struct rte_eth_link *link)
648 struct rte_eth_link *dst = &(dev->data->dev_link);
649 struct rte_eth_link *src = link;
651 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
652 *(uint64_t *)src) == 0)
658 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
659 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
660 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
662 #ifndef I40E_GLQF_ORT
663 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
665 #ifndef I40E_GLQF_PIT
666 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
668 #ifndef I40E_GLQF_L3_MAP
669 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
672 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
675 * Initialize registers for parsing packet type of QinQ
676 * This should be removed from code once proper
677 * configuration API is added to avoid configuration conflicts
678 * between ports of the same device.
680 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
681 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
684 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
687 * Add a ethertype filter to drop all flow control frames transmitted
691 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
693 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
694 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
695 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
696 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
699 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
700 I40E_FLOW_CONTROL_ETHERTYPE, flags,
701 pf->main_vsi_seid, 0,
705 "Failed to add filter to drop flow control frames from VSIs.");
709 floating_veb_list_handler(__rte_unused const char *key,
710 const char *floating_veb_value,
714 unsigned int count = 0;
717 bool *vf_floating_veb = opaque;
719 while (isblank(*floating_veb_value))
720 floating_veb_value++;
722 /* Reset floating VEB configuration for VFs */
723 for (idx = 0; idx < I40E_MAX_VF; idx++)
724 vf_floating_veb[idx] = false;
728 while (isblank(*floating_veb_value))
729 floating_veb_value++;
730 if (*floating_veb_value == '\0')
733 idx = strtoul(floating_veb_value, &end, 10);
734 if (errno || end == NULL)
736 while (isblank(*end))
740 } else if ((*end == ';') || (*end == '\0')) {
742 if (min == I40E_MAX_VF)
744 if (max >= I40E_MAX_VF)
745 max = I40E_MAX_VF - 1;
746 for (idx = min; idx <= max; idx++) {
747 vf_floating_veb[idx] = true;
754 floating_veb_value = end + 1;
755 } while (*end != '\0');
764 config_vf_floating_veb(struct rte_devargs *devargs,
765 uint16_t floating_veb,
766 bool *vf_floating_veb)
768 struct rte_kvargs *kvlist;
770 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
774 /* All the VFs attach to the floating VEB by default
775 * when the floating VEB is enabled.
777 for (i = 0; i < I40E_MAX_VF; i++)
778 vf_floating_veb[i] = true;
783 kvlist = rte_kvargs_parse(devargs->args, NULL);
787 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
788 rte_kvargs_free(kvlist);
791 /* When the floating_veb_list parameter exists, all the VFs
792 * will attach to the legacy VEB firstly, then configure VFs
793 * to the floating VEB according to the floating_veb_list.
795 if (rte_kvargs_process(kvlist, floating_veb_list,
796 floating_veb_list_handler,
797 vf_floating_veb) < 0) {
798 rte_kvargs_free(kvlist);
801 rte_kvargs_free(kvlist);
805 i40e_check_floating_handler(__rte_unused const char *key,
807 __rte_unused void *opaque)
809 if (strcmp(value, "1"))
816 is_floating_veb_supported(struct rte_devargs *devargs)
818 struct rte_kvargs *kvlist;
819 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
824 kvlist = rte_kvargs_parse(devargs->args, NULL);
828 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
829 rte_kvargs_free(kvlist);
832 /* Floating VEB is enabled when there's key-value:
833 * enable_floating_veb=1
835 if (rte_kvargs_process(kvlist, floating_veb_key,
836 i40e_check_floating_handler, NULL) < 0) {
837 rte_kvargs_free(kvlist);
840 rte_kvargs_free(kvlist);
846 config_floating_veb(struct rte_eth_dev *dev)
848 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
849 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
850 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
852 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
854 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
856 is_floating_veb_supported(pci_dev->device.devargs);
857 config_vf_floating_veb(pci_dev->device.devargs,
859 pf->floating_veb_list);
861 pf->floating_veb = false;
865 #define I40E_L2_TAGS_S_TAG_SHIFT 1
866 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
869 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
871 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
872 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
873 char ethertype_hash_name[RTE_HASH_NAMESIZE];
876 struct rte_hash_parameters ethertype_hash_params = {
877 .name = ethertype_hash_name,
878 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
879 .key_len = sizeof(struct i40e_ethertype_filter_input),
880 .hash_func = rte_hash_crc,
881 .hash_func_init_val = 0,
882 .socket_id = rte_socket_id(),
885 /* Initialize ethertype filter rule list and hash */
886 TAILQ_INIT(ðertype_rule->ethertype_list);
887 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
888 "ethertype_%s", dev->device->name);
889 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
890 if (!ethertype_rule->hash_table) {
891 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
894 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
895 sizeof(struct i40e_ethertype_filter *) *
896 I40E_MAX_ETHERTYPE_FILTER_NUM,
898 if (!ethertype_rule->hash_map) {
900 "Failed to allocate memory for ethertype hash map!");
902 goto err_ethertype_hash_map_alloc;
907 err_ethertype_hash_map_alloc:
908 rte_hash_free(ethertype_rule->hash_table);
914 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
916 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
917 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
918 char tunnel_hash_name[RTE_HASH_NAMESIZE];
921 struct rte_hash_parameters tunnel_hash_params = {
922 .name = tunnel_hash_name,
923 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
924 .key_len = sizeof(struct i40e_tunnel_filter_input),
925 .hash_func = rte_hash_crc,
926 .hash_func_init_val = 0,
927 .socket_id = rte_socket_id(),
930 /* Initialize tunnel filter rule list and hash */
931 TAILQ_INIT(&tunnel_rule->tunnel_list);
932 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
933 "tunnel_%s", dev->device->name);
934 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
935 if (!tunnel_rule->hash_table) {
936 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
939 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
940 sizeof(struct i40e_tunnel_filter *) *
941 I40E_MAX_TUNNEL_FILTER_NUM,
943 if (!tunnel_rule->hash_map) {
945 "Failed to allocate memory for tunnel hash map!");
947 goto err_tunnel_hash_map_alloc;
952 err_tunnel_hash_map_alloc:
953 rte_hash_free(tunnel_rule->hash_table);
959 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
961 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
962 struct i40e_fdir_info *fdir_info = &pf->fdir;
963 char fdir_hash_name[RTE_HASH_NAMESIZE];
966 struct rte_hash_parameters fdir_hash_params = {
967 .name = fdir_hash_name,
968 .entries = I40E_MAX_FDIR_FILTER_NUM,
969 .key_len = sizeof(struct i40e_fdir_input),
970 .hash_func = rte_hash_crc,
971 .hash_func_init_val = 0,
972 .socket_id = rte_socket_id(),
975 /* Initialize flow director filter rule list and hash */
976 TAILQ_INIT(&fdir_info->fdir_list);
977 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
978 "fdir_%s", dev->device->name);
979 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
980 if (!fdir_info->hash_table) {
981 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
984 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
985 sizeof(struct i40e_fdir_filter *) *
986 I40E_MAX_FDIR_FILTER_NUM,
988 if (!fdir_info->hash_map) {
990 "Failed to allocate memory for fdir hash map!");
992 goto err_fdir_hash_map_alloc;
996 err_fdir_hash_map_alloc:
997 rte_hash_free(fdir_info->hash_table);
1003 i40e_init_customized_info(struct i40e_pf *pf)
1007 /* Initialize customized pctype */
1008 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1009 pf->customized_pctype[i].index = i;
1010 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1011 pf->customized_pctype[i].valid = false;
1014 pf->gtp_support = false;
1018 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1020 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1021 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1022 struct i40e_queue_regions *info = &pf->queue_region;
1025 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1026 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1028 memset(info, 0, sizeof(struct i40e_queue_regions));
1032 eth_i40e_dev_init(struct rte_eth_dev *dev)
1034 struct rte_pci_device *pci_dev;
1035 struct rte_intr_handle *intr_handle;
1036 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1037 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038 struct i40e_vsi *vsi;
1041 uint8_t aq_fail = 0;
1043 PMD_INIT_FUNC_TRACE();
1045 dev->dev_ops = &i40e_eth_dev_ops;
1046 dev->rx_pkt_burst = i40e_recv_pkts;
1047 dev->tx_pkt_burst = i40e_xmit_pkts;
1048 dev->tx_pkt_prepare = i40e_prep_pkts;
1050 /* for secondary processes, we don't initialise any further as primary
1051 * has already done this work. Only check we don't need a different
1053 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1054 i40e_set_rx_function(dev);
1055 i40e_set_tx_function(dev);
1058 i40e_set_default_ptype_table(dev);
1059 i40e_set_default_pctype_table(dev);
1060 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1061 intr_handle = &pci_dev->intr_handle;
1063 rte_eth_copy_pci_info(dev, pci_dev);
1065 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1066 pf->adapter->eth_dev = dev;
1067 pf->dev_data = dev->data;
1069 hw->back = I40E_PF_TO_ADAPTER(pf);
1070 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1073 "Hardware is not available, as address is NULL");
1077 hw->vendor_id = pci_dev->id.vendor_id;
1078 hw->device_id = pci_dev->id.device_id;
1079 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1080 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1081 hw->bus.device = pci_dev->addr.devid;
1082 hw->bus.func = pci_dev->addr.function;
1083 hw->adapter_stopped = 0;
1085 /* Make sure all is clean before doing PF reset */
1088 /* Initialize the hardware */
1091 /* Reset here to make sure all is clean for each PF */
1092 ret = i40e_pf_reset(hw);
1094 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1098 /* Initialize the shared code (base driver) */
1099 ret = i40e_init_shared_code(hw);
1101 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1106 * To work around the NVM issue, initialize registers
1107 * for packet type of QinQ by software.
1108 * It should be removed once issues are fixed in NVM.
1110 i40e_GLQF_reg_init(hw);
1112 /* Initialize the input set for filters (hash and fd) to default value */
1113 i40e_filter_input_set_init(pf);
1115 /* Initialize the parameters for adminq */
1116 i40e_init_adminq_parameter(hw);
1117 ret = i40e_init_adminq(hw);
1118 if (ret != I40E_SUCCESS) {
1119 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1122 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1123 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1124 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1125 ((hw->nvm.version >> 12) & 0xf),
1126 ((hw->nvm.version >> 4) & 0xff),
1127 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1129 /* initialise the L3_MAP register */
1130 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1133 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1135 /* Need the special FW version to support floating VEB */
1136 config_floating_veb(dev);
1137 /* Clear PXE mode */
1138 i40e_clear_pxe_mode(hw);
1139 i40e_dev_sync_phy_type(hw);
1142 * On X710, performance number is far from the expectation on recent
1143 * firmware versions. The fix for this issue may not be integrated in
1144 * the following firmware version. So the workaround in software driver
1145 * is needed. It needs to modify the initial values of 3 internal only
1146 * registers. Note that the workaround can be removed when it is fixed
1147 * in firmware in the future.
1149 i40e_configure_registers(hw);
1151 /* Get hw capabilities */
1152 ret = i40e_get_cap(hw);
1153 if (ret != I40E_SUCCESS) {
1154 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1155 goto err_get_capabilities;
1158 /* Initialize parameters for PF */
1159 ret = i40e_pf_parameter_init(dev);
1161 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1162 goto err_parameter_init;
1165 /* Initialize the queue management */
1166 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1168 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1169 goto err_qp_pool_init;
1171 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1172 hw->func_caps.num_msix_vectors - 1);
1174 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1175 goto err_msix_pool_init;
1178 /* Initialize lan hmc */
1179 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1180 hw->func_caps.num_rx_qp, 0, 0);
1181 if (ret != I40E_SUCCESS) {
1182 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1183 goto err_init_lan_hmc;
1186 /* Configure lan hmc */
1187 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1188 if (ret != I40E_SUCCESS) {
1189 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1190 goto err_configure_lan_hmc;
1193 /* Get and check the mac address */
1194 i40e_get_mac_addr(hw, hw->mac.addr);
1195 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1196 PMD_INIT_LOG(ERR, "mac address is not valid");
1198 goto err_get_mac_addr;
1200 /* Copy the permanent MAC address */
1201 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1202 (struct ether_addr *) hw->mac.perm_addr);
1204 /* Disable flow control */
1205 hw->fc.requested_mode = I40E_FC_NONE;
1206 i40e_set_fc(hw, &aq_fail, TRUE);
1208 /* Set the global registers with default ether type value */
1209 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1210 if (ret != I40E_SUCCESS) {
1212 "Failed to set the default outer VLAN ether type");
1213 goto err_setup_pf_switch;
1216 /* PF setup, which includes VSI setup */
1217 ret = i40e_pf_setup(pf);
1219 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1220 goto err_setup_pf_switch;
1223 /* reset all stats of the device, including pf and main vsi */
1224 i40e_dev_stats_reset(dev);
1228 /* Disable double vlan by default */
1229 i40e_vsi_config_double_vlan(vsi, FALSE);
1231 /* Disable S-TAG identification when floating_veb is disabled */
1232 if (!pf->floating_veb) {
1233 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1234 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1235 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1236 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1240 if (!vsi->max_macaddrs)
1241 len = ETHER_ADDR_LEN;
1243 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1245 /* Should be after VSI initialized */
1246 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1247 if (!dev->data->mac_addrs) {
1249 "Failed to allocated memory for storing mac address");
1252 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1253 &dev->data->mac_addrs[0]);
1255 /* Init dcb to sw mode by default */
1256 ret = i40e_dcb_init_configure(dev, TRUE);
1257 if (ret != I40E_SUCCESS) {
1258 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1259 pf->flags &= ~I40E_FLAG_DCB;
1261 /* Update HW struct after DCB configuration */
1264 /* initialize pf host driver to setup SRIOV resource if applicable */
1265 i40e_pf_host_init(dev);
1267 /* register callback func to eal lib */
1268 rte_intr_callback_register(intr_handle,
1269 i40e_dev_interrupt_handler, dev);
1271 /* configure and enable device interrupt */
1272 i40e_pf_config_irq0(hw, TRUE);
1273 i40e_pf_enable_irq0(hw);
1275 /* enable uio intr after callback register */
1276 rte_intr_enable(intr_handle);
1278 /* By default disable flexible payload in global configuration */
1279 i40e_flex_payload_reg_set_default(hw);
1282 * Add an ethertype filter to drop all flow control frames transmitted
1283 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1286 i40e_add_tx_flow_control_drop_filter(pf);
1288 /* Set the max frame size to 0x2600 by default,
1289 * in case other drivers changed the default value.
1291 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1293 /* initialize mirror rule list */
1294 TAILQ_INIT(&pf->mirror_list);
1296 /* initialize Traffic Manager configuration */
1297 i40e_tm_conf_init(dev);
1299 /* Initialize customized information */
1300 i40e_init_customized_info(pf);
1302 ret = i40e_init_ethtype_filter_list(dev);
1304 goto err_init_ethtype_filter_list;
1305 ret = i40e_init_tunnel_filter_list(dev);
1307 goto err_init_tunnel_filter_list;
1308 ret = i40e_init_fdir_filter_list(dev);
1310 goto err_init_fdir_filter_list;
1312 /* initialize queue region configuration */
1313 i40e_init_queue_region_conf(dev);
1317 err_init_fdir_filter_list:
1318 rte_free(pf->tunnel.hash_table);
1319 rte_free(pf->tunnel.hash_map);
1320 err_init_tunnel_filter_list:
1321 rte_free(pf->ethertype.hash_table);
1322 rte_free(pf->ethertype.hash_map);
1323 err_init_ethtype_filter_list:
1324 rte_free(dev->data->mac_addrs);
1326 i40e_vsi_release(pf->main_vsi);
1327 err_setup_pf_switch:
1329 err_configure_lan_hmc:
1330 (void)i40e_shutdown_lan_hmc(hw);
1332 i40e_res_pool_destroy(&pf->msix_pool);
1334 i40e_res_pool_destroy(&pf->qp_pool);
1337 err_get_capabilities:
1338 (void)i40e_shutdown_adminq(hw);
1344 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1346 struct i40e_ethertype_filter *p_ethertype;
1347 struct i40e_ethertype_rule *ethertype_rule;
1349 ethertype_rule = &pf->ethertype;
1350 /* Remove all ethertype filter rules and hash */
1351 if (ethertype_rule->hash_map)
1352 rte_free(ethertype_rule->hash_map);
1353 if (ethertype_rule->hash_table)
1354 rte_hash_free(ethertype_rule->hash_table);
1356 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1357 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1358 p_ethertype, rules);
1359 rte_free(p_ethertype);
1364 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1366 struct i40e_tunnel_filter *p_tunnel;
1367 struct i40e_tunnel_rule *tunnel_rule;
1369 tunnel_rule = &pf->tunnel;
1370 /* Remove all tunnel director rules and hash */
1371 if (tunnel_rule->hash_map)
1372 rte_free(tunnel_rule->hash_map);
1373 if (tunnel_rule->hash_table)
1374 rte_hash_free(tunnel_rule->hash_table);
1376 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1377 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1383 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1385 struct i40e_fdir_filter *p_fdir;
1386 struct i40e_fdir_info *fdir_info;
1388 fdir_info = &pf->fdir;
1389 /* Remove all flow director rules and hash */
1390 if (fdir_info->hash_map)
1391 rte_free(fdir_info->hash_map);
1392 if (fdir_info->hash_table)
1393 rte_hash_free(fdir_info->hash_table);
1395 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1396 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1401 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1404 * Disable by default flexible payload
1405 * for corresponding L2/L3/L4 layers.
1407 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1408 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1409 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1413 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1416 struct rte_pci_device *pci_dev;
1417 struct rte_intr_handle *intr_handle;
1419 struct i40e_filter_control_settings settings;
1420 struct rte_flow *p_flow;
1422 uint8_t aq_fail = 0;
1424 PMD_INIT_FUNC_TRACE();
1426 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1429 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1430 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1431 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1432 intr_handle = &pci_dev->intr_handle;
1434 if (hw->adapter_stopped == 0)
1435 i40e_dev_close(dev);
1437 dev->dev_ops = NULL;
1438 dev->rx_pkt_burst = NULL;
1439 dev->tx_pkt_burst = NULL;
1441 /* Clear PXE mode */
1442 i40e_clear_pxe_mode(hw);
1444 /* Unconfigure filter control */
1445 memset(&settings, 0, sizeof(settings));
1446 ret = i40e_set_filter_control(hw, &settings);
1448 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1451 /* Disable flow control */
1452 hw->fc.requested_mode = I40E_FC_NONE;
1453 i40e_set_fc(hw, &aq_fail, TRUE);
1455 /* uninitialize pf host driver */
1456 i40e_pf_host_uninit(dev);
1458 rte_free(dev->data->mac_addrs);
1459 dev->data->mac_addrs = NULL;
1461 /* disable uio intr before callback unregister */
1462 rte_intr_disable(intr_handle);
1464 /* register callback func to eal lib */
1465 rte_intr_callback_unregister(intr_handle,
1466 i40e_dev_interrupt_handler, dev);
1468 i40e_rm_ethtype_filter_list(pf);
1469 i40e_rm_tunnel_filter_list(pf);
1470 i40e_rm_fdir_filter_list(pf);
1472 /* Remove all flows */
1473 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1474 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1478 /* Remove all Traffic Manager configuration */
1479 i40e_tm_conf_uninit(dev);
1485 i40e_dev_configure(struct rte_eth_dev *dev)
1487 struct i40e_adapter *ad =
1488 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1489 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1490 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1491 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1494 ret = i40e_dev_sync_phy_type(hw);
1498 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1499 * bulk allocation or vector Rx preconditions we will reset it.
1501 ad->rx_bulk_alloc_allowed = true;
1502 ad->rx_vec_allowed = true;
1503 ad->tx_simple_allowed = true;
1504 ad->tx_vec_allowed = true;
1506 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1507 ret = i40e_fdir_setup(pf);
1508 if (ret != I40E_SUCCESS) {
1509 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1512 ret = i40e_fdir_configure(dev);
1514 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1518 i40e_fdir_teardown(pf);
1520 ret = i40e_dev_init_vlan(dev);
1525 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1526 * RSS setting have different requirements.
1527 * General PMD driver call sequence are NIC init, configure,
1528 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1529 * will try to lookup the VSI that specific queue belongs to if VMDQ
1530 * applicable. So, VMDQ setting has to be done before
1531 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1532 * For RSS setting, it will try to calculate actual configured RX queue
1533 * number, which will be available after rx_queue_setup(). dev_start()
1534 * function is good to place RSS setup.
1536 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1537 ret = i40e_vmdq_setup(dev);
1542 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1543 ret = i40e_dcb_setup(dev);
1545 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1550 TAILQ_INIT(&pf->flow_list);
1555 /* need to release vmdq resource if exists */
1556 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1557 i40e_vsi_release(pf->vmdq[i].vsi);
1558 pf->vmdq[i].vsi = NULL;
1563 /* need to release fdir resource if exists */
1564 i40e_fdir_teardown(pf);
1569 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1571 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1572 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1573 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1574 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1575 uint16_t msix_vect = vsi->msix_intr;
1578 for (i = 0; i < vsi->nb_qps; i++) {
1579 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1580 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1584 if (vsi->type != I40E_VSI_SRIOV) {
1585 if (!rte_intr_allow_others(intr_handle)) {
1586 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1587 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1589 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1592 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1593 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1595 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1600 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1601 vsi->user_param + (msix_vect - 1);
1603 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1604 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1606 I40E_WRITE_FLUSH(hw);
1610 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1611 int base_queue, int nb_queue,
1616 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1618 /* Bind all RX queues to allocated MSIX interrupt */
1619 for (i = 0; i < nb_queue; i++) {
1620 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1621 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1622 ((base_queue + i + 1) <<
1623 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1624 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1625 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1627 if (i == nb_queue - 1)
1628 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1629 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1632 /* Write first RX queue to Link list register as the head element */
1633 if (vsi->type != I40E_VSI_SRIOV) {
1635 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1637 if (msix_vect == I40E_MISC_VEC_ID) {
1638 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1640 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1642 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1644 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1647 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1649 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1651 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1653 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1660 if (msix_vect == I40E_MISC_VEC_ID) {
1662 I40E_VPINT_LNKLST0(vsi->user_param),
1664 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1666 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1668 /* num_msix_vectors_vf needs to minus irq0 */
1669 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1670 vsi->user_param + (msix_vect - 1);
1672 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1674 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1676 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1680 I40E_WRITE_FLUSH(hw);
1684 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1686 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1687 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1688 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1689 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1690 uint16_t msix_vect = vsi->msix_intr;
1691 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1692 uint16_t queue_idx = 0;
1697 for (i = 0; i < vsi->nb_qps; i++) {
1698 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1699 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1702 /* INTENA flag is not auto-cleared for interrupt */
1703 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1704 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1705 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1706 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1707 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1709 /* VF bind interrupt */
1710 if (vsi->type == I40E_VSI_SRIOV) {
1711 __vsi_queues_bind_intr(vsi, msix_vect,
1712 vsi->base_queue, vsi->nb_qps,
1717 /* PF & VMDq bind interrupt */
1718 if (rte_intr_dp_is_en(intr_handle)) {
1719 if (vsi->type == I40E_VSI_MAIN) {
1722 } else if (vsi->type == I40E_VSI_VMDQ2) {
1723 struct i40e_vsi *main_vsi =
1724 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1725 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1730 for (i = 0; i < vsi->nb_used_qps; i++) {
1732 if (!rte_intr_allow_others(intr_handle))
1733 /* allow to share MISC_VEC_ID */
1734 msix_vect = I40E_MISC_VEC_ID;
1736 /* no enough msix_vect, map all to one */
1737 __vsi_queues_bind_intr(vsi, msix_vect,
1738 vsi->base_queue + i,
1739 vsi->nb_used_qps - i,
1741 for (; !!record && i < vsi->nb_used_qps; i++)
1742 intr_handle->intr_vec[queue_idx + i] =
1746 /* 1:1 queue/msix_vect mapping */
1747 __vsi_queues_bind_intr(vsi, msix_vect,
1748 vsi->base_queue + i, 1,
1751 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1759 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1761 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1762 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1763 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1764 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1765 uint16_t interval = i40e_calc_itr_interval(\
1766 RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1767 uint16_t msix_intr, i;
1769 if (rte_intr_allow_others(intr_handle))
1770 for (i = 0; i < vsi->nb_msix; i++) {
1771 msix_intr = vsi->msix_intr + i;
1772 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1773 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1774 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1775 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1777 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1780 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1781 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1782 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1783 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1785 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1787 I40E_WRITE_FLUSH(hw);
1791 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1793 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1794 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1795 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1796 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1797 uint16_t msix_intr, i;
1799 if (rte_intr_allow_others(intr_handle))
1800 for (i = 0; i < vsi->nb_msix; i++) {
1801 msix_intr = vsi->msix_intr + i;
1802 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1806 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1808 I40E_WRITE_FLUSH(hw);
1811 static inline uint8_t
1812 i40e_parse_link_speeds(uint16_t link_speeds)
1814 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1816 if (link_speeds & ETH_LINK_SPEED_40G)
1817 link_speed |= I40E_LINK_SPEED_40GB;
1818 if (link_speeds & ETH_LINK_SPEED_25G)
1819 link_speed |= I40E_LINK_SPEED_25GB;
1820 if (link_speeds & ETH_LINK_SPEED_20G)
1821 link_speed |= I40E_LINK_SPEED_20GB;
1822 if (link_speeds & ETH_LINK_SPEED_10G)
1823 link_speed |= I40E_LINK_SPEED_10GB;
1824 if (link_speeds & ETH_LINK_SPEED_1G)
1825 link_speed |= I40E_LINK_SPEED_1GB;
1826 if (link_speeds & ETH_LINK_SPEED_100M)
1827 link_speed |= I40E_LINK_SPEED_100MB;
1833 i40e_phy_conf_link(struct i40e_hw *hw,
1835 uint8_t force_speed,
1838 enum i40e_status_code status;
1839 struct i40e_aq_get_phy_abilities_resp phy_ab;
1840 struct i40e_aq_set_phy_config phy_conf;
1841 enum i40e_aq_phy_type cnt;
1842 uint32_t phy_type_mask = 0;
1844 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1845 I40E_AQ_PHY_FLAG_PAUSE_RX |
1846 I40E_AQ_PHY_FLAG_PAUSE_RX |
1847 I40E_AQ_PHY_FLAG_LOW_POWER;
1848 const uint8_t advt = I40E_LINK_SPEED_40GB |
1849 I40E_LINK_SPEED_25GB |
1850 I40E_LINK_SPEED_10GB |
1851 I40E_LINK_SPEED_1GB |
1852 I40E_LINK_SPEED_100MB;
1856 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1861 /* If link already up, no need to set up again */
1862 if (is_up && phy_ab.phy_type != 0)
1863 return I40E_SUCCESS;
1865 memset(&phy_conf, 0, sizeof(phy_conf));
1867 /* bits 0-2 use the values from get_phy_abilities_resp */
1869 abilities |= phy_ab.abilities & mask;
1871 /* update ablities and speed */
1872 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1873 phy_conf.link_speed = advt;
1875 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1877 phy_conf.abilities = abilities;
1881 /* To enable link, phy_type mask needs to include each type */
1882 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1883 phy_type_mask |= 1 << cnt;
1885 /* use get_phy_abilities_resp value for the rest */
1886 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1887 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1888 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1889 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1890 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1891 phy_conf.eee_capability = phy_ab.eee_capability;
1892 phy_conf.eeer = phy_ab.eeer_val;
1893 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1895 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1896 phy_ab.abilities, phy_ab.link_speed);
1897 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1898 phy_conf.abilities, phy_conf.link_speed);
1900 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1904 return I40E_SUCCESS;
1908 i40e_apply_link_speed(struct rte_eth_dev *dev)
1911 uint8_t abilities = 0;
1912 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913 struct rte_eth_conf *conf = &dev->data->dev_conf;
1915 speed = i40e_parse_link_speeds(conf->link_speeds);
1916 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1917 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1918 abilities |= I40E_AQ_PHY_AN_ENABLED;
1919 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1921 return i40e_phy_conf_link(hw, abilities, speed, true);
1925 i40e_dev_start(struct rte_eth_dev *dev)
1927 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1928 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929 struct i40e_vsi *main_vsi = pf->main_vsi;
1931 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1932 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1933 uint32_t intr_vector = 0;
1934 struct i40e_vsi *vsi;
1936 hw->adapter_stopped = 0;
1938 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1940 "Invalid link_speeds for port %u, autonegotiation disabled",
1941 dev->data->port_id);
1945 rte_intr_disable(intr_handle);
1947 if ((rte_intr_cap_multiple(intr_handle) ||
1948 !RTE_ETH_DEV_SRIOV(dev).active) &&
1949 dev->data->dev_conf.intr_conf.rxq != 0) {
1950 intr_vector = dev->data->nb_rx_queues;
1951 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1956 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1957 intr_handle->intr_vec =
1958 rte_zmalloc("intr_vec",
1959 dev->data->nb_rx_queues * sizeof(int),
1961 if (!intr_handle->intr_vec) {
1963 "Failed to allocate %d rx_queues intr_vec",
1964 dev->data->nb_rx_queues);
1969 /* Initialize VSI */
1970 ret = i40e_dev_rxtx_init(pf);
1971 if (ret != I40E_SUCCESS) {
1972 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1976 /* Map queues with MSIX interrupt */
1977 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1978 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1979 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1980 i40e_vsi_enable_queues_intr(main_vsi);
1982 /* Map VMDQ VSI queues with MSIX interrupt */
1983 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1984 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1985 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1986 I40E_ITR_INDEX_DEFAULT);
1987 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1990 /* enable FDIR MSIX interrupt */
1991 if (pf->fdir.fdir_vsi) {
1992 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1993 I40E_ITR_INDEX_NONE);
1994 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1997 /* Enable all queues which have been configured */
1998 ret = i40e_dev_switch_queues(pf, TRUE);
1999 if (ret != I40E_SUCCESS) {
2000 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2004 /* Enable receiving broadcast packets */
2005 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2006 if (ret != I40E_SUCCESS)
2007 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2009 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2010 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2012 if (ret != I40E_SUCCESS)
2013 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2016 /* Enable the VLAN promiscuous mode. */
2018 for (i = 0; i < pf->vf_num; i++) {
2019 vsi = pf->vfs[i].vsi;
2020 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2025 /* Enable mac loopback mode */
2026 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2027 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2028 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2029 if (ret != I40E_SUCCESS) {
2030 PMD_DRV_LOG(ERR, "fail to set loopback link");
2035 /* Apply link configure */
2036 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2037 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2038 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2039 ETH_LINK_SPEED_40G)) {
2040 PMD_DRV_LOG(ERR, "Invalid link setting");
2043 ret = i40e_apply_link_speed(dev);
2044 if (I40E_SUCCESS != ret) {
2045 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2049 if (!rte_intr_allow_others(intr_handle)) {
2050 rte_intr_callback_unregister(intr_handle,
2051 i40e_dev_interrupt_handler,
2053 /* configure and enable device interrupt */
2054 i40e_pf_config_irq0(hw, FALSE);
2055 i40e_pf_enable_irq0(hw);
2057 if (dev->data->dev_conf.intr_conf.lsc != 0)
2059 "lsc won't enable because of no intr multiplex");
2061 ret = i40e_aq_set_phy_int_mask(hw,
2062 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2063 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2064 I40E_AQ_EVENT_MEDIA_NA), NULL);
2065 if (ret != I40E_SUCCESS)
2066 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2068 /* Call get_link_info aq commond to enable/disable LSE */
2069 i40e_dev_link_update(dev, 0);
2072 /* enable uio intr after callback register */
2073 rte_intr_enable(intr_handle);
2075 i40e_filter_restore(pf);
2077 if (pf->tm_conf.root && !pf->tm_conf.committed)
2078 PMD_DRV_LOG(WARNING,
2079 "please call hierarchy_commit() "
2080 "before starting the port");
2082 return I40E_SUCCESS;
2085 i40e_dev_switch_queues(pf, FALSE);
2086 i40e_dev_clear_queues(dev);
2092 i40e_dev_stop(struct rte_eth_dev *dev)
2094 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2095 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2096 struct i40e_vsi *main_vsi = pf->main_vsi;
2097 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2098 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2101 if (hw->adapter_stopped == 1)
2103 /* Disable all queues */
2104 i40e_dev_switch_queues(pf, FALSE);
2106 /* un-map queues with interrupt registers */
2107 i40e_vsi_disable_queues_intr(main_vsi);
2108 i40e_vsi_queues_unbind_intr(main_vsi);
2110 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2111 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2112 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2115 if (pf->fdir.fdir_vsi) {
2116 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2117 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2119 /* Clear all queues and release memory */
2120 i40e_dev_clear_queues(dev);
2123 i40e_dev_set_link_down(dev);
2125 if (!rte_intr_allow_others(intr_handle))
2126 /* resume to the default handler */
2127 rte_intr_callback_register(intr_handle,
2128 i40e_dev_interrupt_handler,
2131 /* Clean datapath event and queue/vec mapping */
2132 rte_intr_efd_disable(intr_handle);
2133 if (intr_handle->intr_vec) {
2134 rte_free(intr_handle->intr_vec);
2135 intr_handle->intr_vec = NULL;
2138 /* reset hierarchy commit */
2139 pf->tm_conf.committed = false;
2141 /* Remove all the queue region configuration */
2142 i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
2144 hw->adapter_stopped = 1;
2148 i40e_dev_close(struct rte_eth_dev *dev)
2150 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2151 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2152 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2153 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2154 struct i40e_mirror_rule *p_mirror;
2159 PMD_INIT_FUNC_TRACE();
2163 /* Remove all mirror rules */
2164 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2165 ret = i40e_aq_del_mirror_rule(hw,
2166 pf->main_vsi->veb->seid,
2167 p_mirror->rule_type,
2169 p_mirror->num_entries,
2172 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2173 "status = %d, aq_err = %d.", ret,
2174 hw->aq.asq_last_status);
2176 /* remove mirror software resource anyway */
2177 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2179 pf->nb_mirror_rule--;
2182 i40e_dev_free_queues(dev);
2184 /* Disable interrupt */
2185 i40e_pf_disable_irq0(hw);
2186 rte_intr_disable(intr_handle);
2188 /* shutdown and destroy the HMC */
2189 i40e_shutdown_lan_hmc(hw);
2191 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2192 i40e_vsi_release(pf->vmdq[i].vsi);
2193 pf->vmdq[i].vsi = NULL;
2198 /* release all the existing VSIs and VEBs */
2199 i40e_fdir_teardown(pf);
2200 i40e_vsi_release(pf->main_vsi);
2202 /* shutdown the adminq */
2203 i40e_aq_queue_shutdown(hw, true);
2204 i40e_shutdown_adminq(hw);
2206 i40e_res_pool_destroy(&pf->qp_pool);
2207 i40e_res_pool_destroy(&pf->msix_pool);
2209 /* Disable flexible payload in global configuration */
2210 i40e_flex_payload_reg_set_default(hw);
2212 /* force a PF reset to clean anything leftover */
2213 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2214 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2215 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2216 I40E_WRITE_FLUSH(hw);
2220 * Reset PF device only to re-initialize resources in PMD layer
2223 i40e_dev_reset(struct rte_eth_dev *dev)
2227 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2228 * its VF to make them align with it. The detailed notification
2229 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2230 * To avoid unexpected behavior in VF, currently reset of PF with
2231 * SR-IOV activation is not supported. It might be supported later.
2233 if (dev->data->sriov.active)
2236 ret = eth_i40e_dev_uninit(dev);
2240 ret = eth_i40e_dev_init(dev);
2246 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2248 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2249 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250 struct i40e_vsi *vsi = pf->main_vsi;
2253 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2255 if (status != I40E_SUCCESS)
2256 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2258 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2260 if (status != I40E_SUCCESS)
2261 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2266 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2268 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2269 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2270 struct i40e_vsi *vsi = pf->main_vsi;
2273 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2275 if (status != I40E_SUCCESS)
2276 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2278 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2280 if (status != I40E_SUCCESS)
2281 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2285 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2287 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2288 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2289 struct i40e_vsi *vsi = pf->main_vsi;
2292 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2293 if (ret != I40E_SUCCESS)
2294 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2298 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2300 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2301 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302 struct i40e_vsi *vsi = pf->main_vsi;
2305 if (dev->data->promiscuous == 1)
2306 return; /* must remain in all_multicast mode */
2308 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2309 vsi->seid, FALSE, NULL);
2310 if (ret != I40E_SUCCESS)
2311 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2315 * Set device link up.
2318 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2320 /* re-apply link speed setting */
2321 return i40e_apply_link_speed(dev);
2325 * Set device link down.
2328 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2330 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2331 uint8_t abilities = 0;
2332 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2334 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2335 return i40e_phy_conf_link(hw, abilities, speed, false);
2339 i40e_dev_link_update(struct rte_eth_dev *dev,
2340 int wait_to_complete)
2342 #define CHECK_INTERVAL 100 /* 100ms */
2343 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2344 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2345 struct i40e_link_status link_status;
2346 struct rte_eth_link link, old;
2348 unsigned rep_cnt = MAX_REPEAT_TIME;
2349 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2351 memset(&link, 0, sizeof(link));
2352 memset(&old, 0, sizeof(old));
2353 memset(&link_status, 0, sizeof(link_status));
2354 rte_i40e_dev_atomic_read_link_status(dev, &old);
2357 /* Get link status information from hardware */
2358 status = i40e_aq_get_link_info(hw, enable_lse,
2359 &link_status, NULL);
2360 if (status != I40E_SUCCESS) {
2361 link.link_speed = ETH_SPEED_NUM_100M;
2362 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2363 PMD_DRV_LOG(ERR, "Failed to get link info");
2367 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2368 if (!wait_to_complete || link.link_status)
2371 rte_delay_ms(CHECK_INTERVAL);
2372 } while (--rep_cnt);
2374 if (!link.link_status)
2377 /* i40e uses full duplex only */
2378 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2380 /* Parse the link status */
2381 switch (link_status.link_speed) {
2382 case I40E_LINK_SPEED_100MB:
2383 link.link_speed = ETH_SPEED_NUM_100M;
2385 case I40E_LINK_SPEED_1GB:
2386 link.link_speed = ETH_SPEED_NUM_1G;
2388 case I40E_LINK_SPEED_10GB:
2389 link.link_speed = ETH_SPEED_NUM_10G;
2391 case I40E_LINK_SPEED_20GB:
2392 link.link_speed = ETH_SPEED_NUM_20G;
2394 case I40E_LINK_SPEED_25GB:
2395 link.link_speed = ETH_SPEED_NUM_25G;
2397 case I40E_LINK_SPEED_40GB:
2398 link.link_speed = ETH_SPEED_NUM_40G;
2401 link.link_speed = ETH_SPEED_NUM_100M;
2405 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2406 ETH_LINK_SPEED_FIXED);
2409 rte_i40e_dev_atomic_write_link_status(dev, &link);
2410 if (link.link_status == old.link_status)
2413 i40e_notify_all_vfs_link_status(dev);
2418 /* Get all the statistics of a VSI */
2420 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2422 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2423 struct i40e_eth_stats *nes = &vsi->eth_stats;
2424 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2425 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2427 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2428 vsi->offset_loaded, &oes->rx_bytes,
2430 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2431 vsi->offset_loaded, &oes->rx_unicast,
2433 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2434 vsi->offset_loaded, &oes->rx_multicast,
2435 &nes->rx_multicast);
2436 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2437 vsi->offset_loaded, &oes->rx_broadcast,
2438 &nes->rx_broadcast);
2439 /* exclude CRC bytes */
2440 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2441 nes->rx_broadcast) * ETHER_CRC_LEN;
2443 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2444 &oes->rx_discards, &nes->rx_discards);
2445 /* GLV_REPC not supported */
2446 /* GLV_RMPC not supported */
2447 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2448 &oes->rx_unknown_protocol,
2449 &nes->rx_unknown_protocol);
2450 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2451 vsi->offset_loaded, &oes->tx_bytes,
2453 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2454 vsi->offset_loaded, &oes->tx_unicast,
2456 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2457 vsi->offset_loaded, &oes->tx_multicast,
2458 &nes->tx_multicast);
2459 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2460 vsi->offset_loaded, &oes->tx_broadcast,
2461 &nes->tx_broadcast);
2462 /* GLV_TDPC not supported */
2463 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2464 &oes->tx_errors, &nes->tx_errors);
2465 vsi->offset_loaded = true;
2467 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2469 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2470 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2471 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2472 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2473 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2474 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2475 nes->rx_unknown_protocol);
2476 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2477 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2478 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2479 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2480 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2481 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2482 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2487 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2490 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2491 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2493 /* Get rx/tx bytes of internal transfer packets */
2494 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2495 I40E_GLV_GORCL(hw->port),
2497 &pf->internal_stats_offset.rx_bytes,
2498 &pf->internal_stats.rx_bytes);
2500 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2501 I40E_GLV_GOTCL(hw->port),
2503 &pf->internal_stats_offset.tx_bytes,
2504 &pf->internal_stats.tx_bytes);
2505 /* Get total internal rx packet count */
2506 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2507 I40E_GLV_UPRCL(hw->port),
2509 &pf->internal_stats_offset.rx_unicast,
2510 &pf->internal_stats.rx_unicast);
2511 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2512 I40E_GLV_MPRCL(hw->port),
2514 &pf->internal_stats_offset.rx_multicast,
2515 &pf->internal_stats.rx_multicast);
2516 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2517 I40E_GLV_BPRCL(hw->port),
2519 &pf->internal_stats_offset.rx_broadcast,
2520 &pf->internal_stats.rx_broadcast);
2522 /* exclude CRC size */
2523 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2524 pf->internal_stats.rx_multicast +
2525 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2527 /* Get statistics of struct i40e_eth_stats */
2528 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2529 I40E_GLPRT_GORCL(hw->port),
2530 pf->offset_loaded, &os->eth.rx_bytes,
2532 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2533 I40E_GLPRT_UPRCL(hw->port),
2534 pf->offset_loaded, &os->eth.rx_unicast,
2535 &ns->eth.rx_unicast);
2536 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2537 I40E_GLPRT_MPRCL(hw->port),
2538 pf->offset_loaded, &os->eth.rx_multicast,
2539 &ns->eth.rx_multicast);
2540 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2541 I40E_GLPRT_BPRCL(hw->port),
2542 pf->offset_loaded, &os->eth.rx_broadcast,
2543 &ns->eth.rx_broadcast);
2544 /* Workaround: CRC size should not be included in byte statistics,
2545 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2547 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2548 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2550 /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2551 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2554 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2555 ns->eth.rx_bytes = 0;
2556 /* exlude internal rx bytes */
2558 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2560 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2561 pf->offset_loaded, &os->eth.rx_discards,
2562 &ns->eth.rx_discards);
2563 /* GLPRT_REPC not supported */
2564 /* GLPRT_RMPC not supported */
2565 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2567 &os->eth.rx_unknown_protocol,
2568 &ns->eth.rx_unknown_protocol);
2569 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2570 I40E_GLPRT_GOTCL(hw->port),
2571 pf->offset_loaded, &os->eth.tx_bytes,
2573 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2574 I40E_GLPRT_UPTCL(hw->port),
2575 pf->offset_loaded, &os->eth.tx_unicast,
2576 &ns->eth.tx_unicast);
2577 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2578 I40E_GLPRT_MPTCL(hw->port),
2579 pf->offset_loaded, &os->eth.tx_multicast,
2580 &ns->eth.tx_multicast);
2581 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2582 I40E_GLPRT_BPTCL(hw->port),
2583 pf->offset_loaded, &os->eth.tx_broadcast,
2584 &ns->eth.tx_broadcast);
2585 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2586 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2588 /* exclude internal tx bytes */
2589 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2590 ns->eth.tx_bytes = 0;
2592 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2594 /* GLPRT_TEPC not supported */
2596 /* additional port specific stats */
2597 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2598 pf->offset_loaded, &os->tx_dropped_link_down,
2599 &ns->tx_dropped_link_down);
2600 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2601 pf->offset_loaded, &os->crc_errors,
2603 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2604 pf->offset_loaded, &os->illegal_bytes,
2605 &ns->illegal_bytes);
2606 /* GLPRT_ERRBC not supported */
2607 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2608 pf->offset_loaded, &os->mac_local_faults,
2609 &ns->mac_local_faults);
2610 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2611 pf->offset_loaded, &os->mac_remote_faults,
2612 &ns->mac_remote_faults);
2613 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2614 pf->offset_loaded, &os->rx_length_errors,
2615 &ns->rx_length_errors);
2616 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2617 pf->offset_loaded, &os->link_xon_rx,
2619 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2620 pf->offset_loaded, &os->link_xoff_rx,
2622 for (i = 0; i < 8; i++) {
2623 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2625 &os->priority_xon_rx[i],
2626 &ns->priority_xon_rx[i]);
2627 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2629 &os->priority_xoff_rx[i],
2630 &ns->priority_xoff_rx[i]);
2632 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2633 pf->offset_loaded, &os->link_xon_tx,
2635 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2636 pf->offset_loaded, &os->link_xoff_tx,
2638 for (i = 0; i < 8; i++) {
2639 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2641 &os->priority_xon_tx[i],
2642 &ns->priority_xon_tx[i]);
2643 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2645 &os->priority_xoff_tx[i],
2646 &ns->priority_xoff_tx[i]);
2647 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2649 &os->priority_xon_2_xoff[i],
2650 &ns->priority_xon_2_xoff[i]);
2652 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2653 I40E_GLPRT_PRC64L(hw->port),
2654 pf->offset_loaded, &os->rx_size_64,
2656 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2657 I40E_GLPRT_PRC127L(hw->port),
2658 pf->offset_loaded, &os->rx_size_127,
2660 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2661 I40E_GLPRT_PRC255L(hw->port),
2662 pf->offset_loaded, &os->rx_size_255,
2664 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2665 I40E_GLPRT_PRC511L(hw->port),
2666 pf->offset_loaded, &os->rx_size_511,
2668 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2669 I40E_GLPRT_PRC1023L(hw->port),
2670 pf->offset_loaded, &os->rx_size_1023,
2672 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2673 I40E_GLPRT_PRC1522L(hw->port),
2674 pf->offset_loaded, &os->rx_size_1522,
2676 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2677 I40E_GLPRT_PRC9522L(hw->port),
2678 pf->offset_loaded, &os->rx_size_big,
2680 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2681 pf->offset_loaded, &os->rx_undersize,
2683 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2684 pf->offset_loaded, &os->rx_fragments,
2686 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2687 pf->offset_loaded, &os->rx_oversize,
2689 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2690 pf->offset_loaded, &os->rx_jabber,
2692 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2693 I40E_GLPRT_PTC64L(hw->port),
2694 pf->offset_loaded, &os->tx_size_64,
2696 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2697 I40E_GLPRT_PTC127L(hw->port),
2698 pf->offset_loaded, &os->tx_size_127,
2700 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2701 I40E_GLPRT_PTC255L(hw->port),
2702 pf->offset_loaded, &os->tx_size_255,
2704 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2705 I40E_GLPRT_PTC511L(hw->port),
2706 pf->offset_loaded, &os->tx_size_511,
2708 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2709 I40E_GLPRT_PTC1023L(hw->port),
2710 pf->offset_loaded, &os->tx_size_1023,
2712 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2713 I40E_GLPRT_PTC1522L(hw->port),
2714 pf->offset_loaded, &os->tx_size_1522,
2716 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2717 I40E_GLPRT_PTC9522L(hw->port),
2718 pf->offset_loaded, &os->tx_size_big,
2720 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2722 &os->fd_sb_match, &ns->fd_sb_match);
2723 /* GLPRT_MSPDC not supported */
2724 /* GLPRT_XEC not supported */
2726 pf->offset_loaded = true;
2729 i40e_update_vsi_stats(pf->main_vsi);
2732 /* Get all statistics of a port */
2734 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2736 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2737 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2741 /* call read registers - updates values, now write them to struct */
2742 i40e_read_stats_registers(pf, hw);
2744 stats->ipackets = ns->eth.rx_unicast +
2745 ns->eth.rx_multicast +
2746 ns->eth.rx_broadcast -
2747 ns->eth.rx_discards -
2748 pf->main_vsi->eth_stats.rx_discards;
2749 stats->opackets = ns->eth.tx_unicast +
2750 ns->eth.tx_multicast +
2751 ns->eth.tx_broadcast;
2752 stats->ibytes = ns->eth.rx_bytes;
2753 stats->obytes = ns->eth.tx_bytes;
2754 stats->oerrors = ns->eth.tx_errors +
2755 pf->main_vsi->eth_stats.tx_errors;
2758 stats->imissed = ns->eth.rx_discards +
2759 pf->main_vsi->eth_stats.rx_discards;
2760 stats->ierrors = ns->crc_errors +
2761 ns->rx_length_errors + ns->rx_undersize +
2762 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2764 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2765 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2766 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2767 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2768 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2769 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2770 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2771 ns->eth.rx_unknown_protocol);
2772 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2773 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2774 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2775 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2776 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2777 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2779 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2780 ns->tx_dropped_link_down);
2781 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2782 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2784 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2785 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2786 ns->mac_local_faults);
2787 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2788 ns->mac_remote_faults);
2789 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2790 ns->rx_length_errors);
2791 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2792 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2793 for (i = 0; i < 8; i++) {
2794 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2795 i, ns->priority_xon_rx[i]);
2796 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2797 i, ns->priority_xoff_rx[i]);
2799 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2800 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2801 for (i = 0; i < 8; i++) {
2802 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2803 i, ns->priority_xon_tx[i]);
2804 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2805 i, ns->priority_xoff_tx[i]);
2806 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2807 i, ns->priority_xon_2_xoff[i]);
2809 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2810 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2811 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2812 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2813 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2814 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2815 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2816 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2817 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2818 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2819 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2820 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2821 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2822 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2823 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2824 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2825 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2826 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2827 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2828 ns->mac_short_packet_dropped);
2829 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2830 ns->checksum_error);
2831 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2832 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2836 /* Reset the statistics */
2838 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2840 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2841 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843 /* Mark PF and VSI stats to update the offset, aka "reset" */
2844 pf->offset_loaded = false;
2846 pf->main_vsi->offset_loaded = false;
2848 /* read the stats, reading current register values into offset */
2849 i40e_read_stats_registers(pf, hw);
2853 i40e_xstats_calc_num(void)
2855 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2856 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2857 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2860 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2861 struct rte_eth_xstat_name *xstats_names,
2862 __rte_unused unsigned limit)
2867 if (xstats_names == NULL)
2868 return i40e_xstats_calc_num();
2870 /* Note: limit checked in rte_eth_xstats_names() */
2872 /* Get stats from i40e_eth_stats struct */
2873 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2874 snprintf(xstats_names[count].name,
2875 sizeof(xstats_names[count].name),
2876 "%s", rte_i40e_stats_strings[i].name);
2880 /* Get individiual stats from i40e_hw_port struct */
2881 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2882 snprintf(xstats_names[count].name,
2883 sizeof(xstats_names[count].name),
2884 "%s", rte_i40e_hw_port_strings[i].name);
2888 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2889 for (prio = 0; prio < 8; prio++) {
2890 snprintf(xstats_names[count].name,
2891 sizeof(xstats_names[count].name),
2892 "rx_priority%u_%s", prio,
2893 rte_i40e_rxq_prio_strings[i].name);
2898 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2899 for (prio = 0; prio < 8; prio++) {
2900 snprintf(xstats_names[count].name,
2901 sizeof(xstats_names[count].name),
2902 "tx_priority%u_%s", prio,
2903 rte_i40e_txq_prio_strings[i].name);
2911 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2914 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2915 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2916 unsigned i, count, prio;
2917 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2919 count = i40e_xstats_calc_num();
2923 i40e_read_stats_registers(pf, hw);
2930 /* Get stats from i40e_eth_stats struct */
2931 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2932 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2933 rte_i40e_stats_strings[i].offset);
2934 xstats[count].id = count;
2938 /* Get individiual stats from i40e_hw_port struct */
2939 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2940 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2941 rte_i40e_hw_port_strings[i].offset);
2942 xstats[count].id = count;
2946 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2947 for (prio = 0; prio < 8; prio++) {
2948 xstats[count].value =
2949 *(uint64_t *)(((char *)hw_stats) +
2950 rte_i40e_rxq_prio_strings[i].offset +
2951 (sizeof(uint64_t) * prio));
2952 xstats[count].id = count;
2957 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2958 for (prio = 0; prio < 8; prio++) {
2959 xstats[count].value =
2960 *(uint64_t *)(((char *)hw_stats) +
2961 rte_i40e_txq_prio_strings[i].offset +
2962 (sizeof(uint64_t) * prio));
2963 xstats[count].id = count;
2972 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2973 __rte_unused uint16_t queue_id,
2974 __rte_unused uint8_t stat_idx,
2975 __rte_unused uint8_t is_rx)
2977 PMD_INIT_FUNC_TRACE();
2983 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2985 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2991 full_ver = hw->nvm.oem_ver;
2992 ver = (u8)(full_ver >> 24);
2993 build = (u16)((full_ver >> 8) & 0xffff);
2994 patch = (u8)(full_ver & 0xff);
2996 ret = snprintf(fw_version, fw_size,
2997 "%d.%d%d 0x%08x %d.%d.%d",
2998 ((hw->nvm.version >> 12) & 0xf),
2999 ((hw->nvm.version >> 4) & 0xff),
3000 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3003 ret += 1; /* add the size of '\0' */
3004 if (fw_size < (u32)ret)
3011 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3013 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3014 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3015 struct i40e_vsi *vsi = pf->main_vsi;
3016 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3018 dev_info->pci_dev = pci_dev;
3019 dev_info->max_rx_queues = vsi->nb_qps;
3020 dev_info->max_tx_queues = vsi->nb_qps;
3021 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3022 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3023 dev_info->max_mac_addrs = vsi->max_macaddrs;
3024 dev_info->max_vfs = pci_dev->max_vfs;
3025 dev_info->rx_offload_capa =
3026 DEV_RX_OFFLOAD_VLAN_STRIP |
3027 DEV_RX_OFFLOAD_QINQ_STRIP |
3028 DEV_RX_OFFLOAD_IPV4_CKSUM |
3029 DEV_RX_OFFLOAD_UDP_CKSUM |
3030 DEV_RX_OFFLOAD_TCP_CKSUM;
3031 dev_info->tx_offload_capa =
3032 DEV_TX_OFFLOAD_VLAN_INSERT |
3033 DEV_TX_OFFLOAD_QINQ_INSERT |
3034 DEV_TX_OFFLOAD_IPV4_CKSUM |
3035 DEV_TX_OFFLOAD_UDP_CKSUM |
3036 DEV_TX_OFFLOAD_TCP_CKSUM |
3037 DEV_TX_OFFLOAD_SCTP_CKSUM |
3038 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3039 DEV_TX_OFFLOAD_TCP_TSO |
3040 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3041 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3042 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3043 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3044 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3046 dev_info->reta_size = pf->hash_lut_size;
3047 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3049 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3051 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3052 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3053 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3055 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3059 dev_info->default_txconf = (struct rte_eth_txconf) {
3061 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3062 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3063 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3065 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3066 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3067 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3068 ETH_TXQ_FLAGS_NOOFFLOADS,
3071 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3072 .nb_max = I40E_MAX_RING_DESC,
3073 .nb_min = I40E_MIN_RING_DESC,
3074 .nb_align = I40E_ALIGN_RING_DESC,
3077 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3078 .nb_max = I40E_MAX_RING_DESC,
3079 .nb_min = I40E_MIN_RING_DESC,
3080 .nb_align = I40E_ALIGN_RING_DESC,
3081 .nb_seg_max = I40E_TX_MAX_SEG,
3082 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3085 if (pf->flags & I40E_FLAG_VMDQ) {
3086 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3087 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3088 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3089 pf->max_nb_vmdq_vsi;
3090 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3091 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3092 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3095 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3097 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3098 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3100 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3103 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3107 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3109 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3110 struct i40e_vsi *vsi = pf->main_vsi;
3111 PMD_INIT_FUNC_TRACE();
3114 return i40e_vsi_add_vlan(vsi, vlan_id);
3116 return i40e_vsi_delete_vlan(vsi, vlan_id);
3120 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3121 enum rte_vlan_type vlan_type,
3122 uint16_t tpid, int qinq)
3124 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3127 uint16_t reg_id = 3;
3131 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3135 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3137 if (ret != I40E_SUCCESS) {
3139 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3144 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3147 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3148 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3149 if (reg_r == reg_w) {
3150 PMD_DRV_LOG(DEBUG, "No need to write");
3154 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3156 if (ret != I40E_SUCCESS) {
3158 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3163 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3170 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3171 enum rte_vlan_type vlan_type,
3174 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3175 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3178 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3179 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3180 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3182 "Unsupported vlan type.");
3185 /* 802.1ad frames ability is added in NVM API 1.7*/
3186 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3188 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3189 hw->first_tag = rte_cpu_to_le_16(tpid);
3190 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3191 hw->second_tag = rte_cpu_to_le_16(tpid);
3193 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3194 hw->second_tag = rte_cpu_to_le_16(tpid);
3196 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3197 if (ret != I40E_SUCCESS) {
3199 "Set switch config failed aq_err: %d",
3200 hw->aq.asq_last_status);
3204 /* If NVM API < 1.7, keep the register setting */
3205 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3212 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3214 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3215 struct i40e_vsi *vsi = pf->main_vsi;
3217 if (mask & ETH_VLAN_FILTER_MASK) {
3218 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3219 i40e_vsi_config_vlan_filter(vsi, TRUE);
3221 i40e_vsi_config_vlan_filter(vsi, FALSE);
3224 if (mask & ETH_VLAN_STRIP_MASK) {
3225 /* Enable or disable VLAN stripping */
3226 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3227 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3229 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3232 if (mask & ETH_VLAN_EXTEND_MASK) {
3233 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3234 i40e_vsi_config_double_vlan(vsi, TRUE);
3235 /* Set global registers with default ethertype. */
3236 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3238 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3242 i40e_vsi_config_double_vlan(vsi, FALSE);
3249 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3250 __rte_unused uint16_t queue,
3251 __rte_unused int on)
3253 PMD_INIT_FUNC_TRACE();
3257 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3259 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3260 struct i40e_vsi *vsi = pf->main_vsi;
3261 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3262 struct i40e_vsi_vlan_pvid_info info;
3264 memset(&info, 0, sizeof(info));
3267 info.config.pvid = pvid;
3269 info.config.reject.tagged =
3270 data->dev_conf.txmode.hw_vlan_reject_tagged;
3271 info.config.reject.untagged =
3272 data->dev_conf.txmode.hw_vlan_reject_untagged;
3275 return i40e_vsi_vlan_pvid_set(vsi, &info);
3279 i40e_dev_led_on(struct rte_eth_dev *dev)
3281 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3282 uint32_t mode = i40e_led_get(hw);
3285 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3291 i40e_dev_led_off(struct rte_eth_dev *dev)
3293 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3294 uint32_t mode = i40e_led_get(hw);
3297 i40e_led_set(hw, 0, false);
3303 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3305 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3306 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3308 fc_conf->pause_time = pf->fc_conf.pause_time;
3310 /* read out from register, in case they are modified by other port */
3311 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3312 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3313 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3314 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3316 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3317 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3319 /* Return current mode according to actual setting*/
3320 switch (hw->fc.current_mode) {
3322 fc_conf->mode = RTE_FC_FULL;
3324 case I40E_FC_TX_PAUSE:
3325 fc_conf->mode = RTE_FC_TX_PAUSE;
3327 case I40E_FC_RX_PAUSE:
3328 fc_conf->mode = RTE_FC_RX_PAUSE;
3332 fc_conf->mode = RTE_FC_NONE;
3339 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3341 uint32_t mflcn_reg, fctrl_reg, reg;
3342 uint32_t max_high_water;
3343 uint8_t i, aq_failure;
3347 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3348 [RTE_FC_NONE] = I40E_FC_NONE,
3349 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3350 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3351 [RTE_FC_FULL] = I40E_FC_FULL
3354 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3356 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3357 if ((fc_conf->high_water > max_high_water) ||
3358 (fc_conf->high_water < fc_conf->low_water)) {
3360 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3365 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3366 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3367 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3369 pf->fc_conf.pause_time = fc_conf->pause_time;
3370 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3371 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3373 PMD_INIT_FUNC_TRACE();
3375 /* All the link flow control related enable/disable register
3376 * configuration is handle by the F/W
3378 err = i40e_set_fc(hw, &aq_failure, true);
3382 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3383 /* Configure flow control refresh threshold,
3384 * the value for stat_tx_pause_refresh_timer[8]
3385 * is used for global pause operation.
3389 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3390 pf->fc_conf.pause_time);
3392 /* configure the timer value included in transmitted pause
3394 * the value for stat_tx_pause_quanta[8] is used for global
3397 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3398 pf->fc_conf.pause_time);
3400 fctrl_reg = I40E_READ_REG(hw,
3401 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3403 if (fc_conf->mac_ctrl_frame_fwd != 0)
3404 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3406 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3408 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3411 /* Configure pause time (2 TCs per register) */
3412 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3413 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3414 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3416 /* Configure flow control refresh threshold value */
3417 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3418 pf->fc_conf.pause_time / 2);
3420 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3422 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3423 *depending on configuration
3425 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3426 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3427 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3429 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3430 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3433 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3436 /* config the water marker both based on the packets and bytes */
3437 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3438 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3439 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3440 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3441 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3442 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3443 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3444 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3446 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3447 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3450 I40E_WRITE_FLUSH(hw);
3456 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3457 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3459 PMD_INIT_FUNC_TRACE();
3464 /* Add a MAC address, and update filters */
3466 i40e_macaddr_add(struct rte_eth_dev *dev,
3467 struct ether_addr *mac_addr,
3468 __rte_unused uint32_t index,
3471 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3472 struct i40e_mac_filter_info mac_filter;
3473 struct i40e_vsi *vsi;
3476 /* If VMDQ not enabled or configured, return */
3477 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3478 !pf->nb_cfg_vmdq_vsi)) {
3479 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3480 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3485 if (pool > pf->nb_cfg_vmdq_vsi) {
3486 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3487 pool, pf->nb_cfg_vmdq_vsi);
3491 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3492 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3493 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3495 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3500 vsi = pf->vmdq[pool - 1].vsi;
3502 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3503 if (ret != I40E_SUCCESS) {
3504 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3510 /* Remove a MAC address, and update filters */
3512 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3514 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3515 struct i40e_vsi *vsi;
3516 struct rte_eth_dev_data *data = dev->data;
3517 struct ether_addr *macaddr;
3522 macaddr = &(data->mac_addrs[index]);
3524 pool_sel = dev->data->mac_pool_sel[index];
3526 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3527 if (pool_sel & (1ULL << i)) {
3531 /* No VMDQ pool enabled or configured */
3532 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3533 (i > pf->nb_cfg_vmdq_vsi)) {
3535 "No VMDQ pool enabled/configured");
3538 vsi = pf->vmdq[i - 1].vsi;
3540 ret = i40e_vsi_delete_mac(vsi, macaddr);
3543 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3550 /* Set perfect match or hash match of MAC and VLAN for a VF */
3552 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3553 struct rte_eth_mac_filter *filter,
3557 struct i40e_mac_filter_info mac_filter;
3558 struct ether_addr old_mac;
3559 struct ether_addr *new_mac;
3560 struct i40e_pf_vf *vf = NULL;
3565 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3568 hw = I40E_PF_TO_HW(pf);
3570 if (filter == NULL) {
3571 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3575 new_mac = &filter->mac_addr;
3577 if (is_zero_ether_addr(new_mac)) {
3578 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3582 vf_id = filter->dst_id;
3584 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3585 PMD_DRV_LOG(ERR, "Invalid argument.");
3588 vf = &pf->vfs[vf_id];
3590 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3591 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3596 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3597 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3599 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3602 mac_filter.filter_type = filter->filter_type;
3603 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3604 if (ret != I40E_SUCCESS) {
3605 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3608 ether_addr_copy(new_mac, &pf->dev_addr);
3610 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3612 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3613 if (ret != I40E_SUCCESS) {
3614 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3618 /* Clear device address as it has been removed */
3619 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3620 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3626 /* MAC filter handle */
3628 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3631 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3632 struct rte_eth_mac_filter *filter;
3633 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3634 int ret = I40E_NOT_SUPPORTED;
3636 filter = (struct rte_eth_mac_filter *)(arg);
3638 switch (filter_op) {
3639 case RTE_ETH_FILTER_NOP:
3642 case RTE_ETH_FILTER_ADD:
3643 i40e_pf_disable_irq0(hw);
3645 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3646 i40e_pf_enable_irq0(hw);
3648 case RTE_ETH_FILTER_DELETE:
3649 i40e_pf_disable_irq0(hw);
3651 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3652 i40e_pf_enable_irq0(hw);
3655 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3656 ret = I40E_ERR_PARAM;
3664 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3666 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3667 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3673 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3674 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3677 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3681 uint32_t *lut_dw = (uint32_t *)lut;
3682 uint16_t i, lut_size_dw = lut_size / 4;
3684 for (i = 0; i < lut_size_dw; i++)
3685 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3692 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3701 pf = I40E_VSI_TO_PF(vsi);
3702 hw = I40E_VSI_TO_HW(vsi);
3704 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3705 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3708 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3712 uint32_t *lut_dw = (uint32_t *)lut;
3713 uint16_t i, lut_size_dw = lut_size / 4;
3715 for (i = 0; i < lut_size_dw; i++)
3716 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3717 I40E_WRITE_FLUSH(hw);
3724 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3725 struct rte_eth_rss_reta_entry64 *reta_conf,
3728 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3729 uint16_t i, lut_size = pf->hash_lut_size;
3730 uint16_t idx, shift;
3734 if (reta_size != lut_size ||
3735 reta_size > ETH_RSS_RETA_SIZE_512) {
3737 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3738 reta_size, lut_size);
3742 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3744 PMD_DRV_LOG(ERR, "No memory can be allocated");
3747 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3750 for (i = 0; i < reta_size; i++) {
3751 idx = i / RTE_RETA_GROUP_SIZE;
3752 shift = i % RTE_RETA_GROUP_SIZE;
3753 if (reta_conf[idx].mask & (1ULL << shift))
3754 lut[i] = reta_conf[idx].reta[shift];
3756 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3765 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3766 struct rte_eth_rss_reta_entry64 *reta_conf,
3769 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3770 uint16_t i, lut_size = pf->hash_lut_size;
3771 uint16_t idx, shift;
3775 if (reta_size != lut_size ||
3776 reta_size > ETH_RSS_RETA_SIZE_512) {
3778 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3779 reta_size, lut_size);
3783 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3785 PMD_DRV_LOG(ERR, "No memory can be allocated");
3789 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3792 for (i = 0; i < reta_size; i++) {
3793 idx = i / RTE_RETA_GROUP_SIZE;
3794 shift = i % RTE_RETA_GROUP_SIZE;
3795 if (reta_conf[idx].mask & (1ULL << shift))
3796 reta_conf[idx].reta[shift] = lut[i];
3806 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3807 * @hw: pointer to the HW structure
3808 * @mem: pointer to mem struct to fill out
3809 * @size: size of memory requested
3810 * @alignment: what to align the allocation to
3812 enum i40e_status_code
3813 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3814 struct i40e_dma_mem *mem,
3818 const struct rte_memzone *mz = NULL;
3819 char z_name[RTE_MEMZONE_NAMESIZE];
3822 return I40E_ERR_PARAM;
3824 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3825 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3826 alignment, RTE_PGSIZE_2M);
3828 return I40E_ERR_NO_MEMORY;
3833 mem->zone = (const void *)mz;
3835 "memzone %s allocated with physical address: %"PRIu64,
3838 return I40E_SUCCESS;
3842 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3843 * @hw: pointer to the HW structure
3844 * @mem: ptr to mem struct to free
3846 enum i40e_status_code
3847 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3848 struct i40e_dma_mem *mem)
3851 return I40E_ERR_PARAM;
3854 "memzone %s to be freed with physical address: %"PRIu64,
3855 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3856 rte_memzone_free((const struct rte_memzone *)mem->zone);
3861 return I40E_SUCCESS;
3865 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3866 * @hw: pointer to the HW structure
3867 * @mem: pointer to mem struct to fill out
3868 * @size: size of memory requested
3870 enum i40e_status_code
3871 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3872 struct i40e_virt_mem *mem,
3876 return I40E_ERR_PARAM;
3879 mem->va = rte_zmalloc("i40e", size, 0);
3882 return I40E_SUCCESS;
3884 return I40E_ERR_NO_MEMORY;
3888 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3889 * @hw: pointer to the HW structure
3890 * @mem: pointer to mem struct to free
3892 enum i40e_status_code
3893 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3894 struct i40e_virt_mem *mem)
3897 return I40E_ERR_PARAM;
3902 return I40E_SUCCESS;
3906 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3908 rte_spinlock_init(&sp->spinlock);
3912 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3914 rte_spinlock_lock(&sp->spinlock);
3918 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3920 rte_spinlock_unlock(&sp->spinlock);
3924 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3930 * Get the hardware capabilities, which will be parsed
3931 * and saved into struct i40e_hw.
3934 i40e_get_cap(struct i40e_hw *hw)
3936 struct i40e_aqc_list_capabilities_element_resp *buf;
3937 uint16_t len, size = 0;
3940 /* Calculate a huge enough buff for saving response data temporarily */
3941 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3942 I40E_MAX_CAP_ELE_NUM;
3943 buf = rte_zmalloc("i40e", len, 0);
3945 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3946 return I40E_ERR_NO_MEMORY;
3949 /* Get, parse the capabilities and save it to hw */
3950 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3951 i40e_aqc_opc_list_func_capabilities, NULL);
3952 if (ret != I40E_SUCCESS)
3953 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3955 /* Free the temporary buffer after being used */
3961 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
3962 #define QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
3963 RTE_PMD_REGISTER_PARAM_STRING(net_i40e, QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16");
3965 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
3973 pf = (struct i40e_pf *)opaque;
3977 num = strtoul(value, &end, 0);
3978 if (errno != 0 || end == value || *end != 0) {
3979 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
3980 "kept the value = %hu", value, pf->vf_nb_qp_max);
3984 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
3985 pf->vf_nb_qp_max = (uint16_t)num;
3987 /* here return 0 to make next valid same argument work */
3988 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
3989 "power of 2 and equal or less than 16 !, Now it is "
3990 "kept the value = %hu", num, pf->vf_nb_qp_max);
3995 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
3997 static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
3998 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3999 struct rte_kvargs *kvlist;
4001 /* set default queue number per VF as 4 */
4002 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4004 if (dev->device->devargs == NULL)
4007 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4011 if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4012 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4013 "the first invalid or last valid one is used !",
4014 QUEUE_NUM_PER_VF_ARG);
4016 rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4017 i40e_pf_parse_vf_queue_number_handler, pf);
4019 rte_kvargs_free(kvlist);
4025 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4027 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4028 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4029 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4030 uint16_t qp_count = 0, vsi_count = 0;
4032 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4033 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4037 i40e_pf_config_vf_rxq_number(dev);
4039 /* Add the parameter init for LFC */
4040 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4041 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4042 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4044 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4045 pf->max_num_vsi = hw->func_caps.num_vsis;
4046 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4047 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4049 /* FDir queue/VSI allocation */
4050 pf->fdir_qp_offset = 0;
4051 if (hw->func_caps.fd) {
4052 pf->flags |= I40E_FLAG_FDIR;
4053 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4055 pf->fdir_nb_qps = 0;
4057 qp_count += pf->fdir_nb_qps;
4060 /* LAN queue/VSI allocation */
4061 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4062 if (!hw->func_caps.rss) {
4065 pf->flags |= I40E_FLAG_RSS;
4066 if (hw->mac.type == I40E_MAC_X722)
4067 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4068 pf->lan_nb_qps = pf->lan_nb_qp_max;
4070 qp_count += pf->lan_nb_qps;
4073 /* VF queue/VSI allocation */
4074 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4075 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4076 pf->flags |= I40E_FLAG_SRIOV;
4077 pf->vf_nb_qps = pf->vf_nb_qp_max;
4078 pf->vf_num = pci_dev->max_vfs;
4080 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4081 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4086 qp_count += pf->vf_nb_qps * pf->vf_num;
4087 vsi_count += pf->vf_num;
4089 /* VMDq queue/VSI allocation */
4090 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4091 pf->vmdq_nb_qps = 0;
4092 pf->max_nb_vmdq_vsi = 0;
4093 if (hw->func_caps.vmdq) {
4094 if (qp_count < hw->func_caps.num_tx_qp &&
4095 vsi_count < hw->func_caps.num_vsis) {
4096 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4097 qp_count) / pf->vmdq_nb_qp_max;
4099 /* Limit the maximum number of VMDq vsi to the maximum
4100 * ethdev can support
4102 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4103 hw->func_caps.num_vsis - vsi_count);
4104 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4106 if (pf->max_nb_vmdq_vsi) {
4107 pf->flags |= I40E_FLAG_VMDQ;
4108 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4110 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4111 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4112 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4115 "No enough queues left for VMDq");
4118 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4121 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4122 vsi_count += pf->max_nb_vmdq_vsi;
4124 if (hw->func_caps.dcb)
4125 pf->flags |= I40E_FLAG_DCB;
4127 if (qp_count > hw->func_caps.num_tx_qp) {
4129 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4130 qp_count, hw->func_caps.num_tx_qp);
4133 if (vsi_count > hw->func_caps.num_vsis) {
4135 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4136 vsi_count, hw->func_caps.num_vsis);
4144 i40e_pf_get_switch_config(struct i40e_pf *pf)
4146 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4147 struct i40e_aqc_get_switch_config_resp *switch_config;
4148 struct i40e_aqc_switch_config_element_resp *element;
4149 uint16_t start_seid = 0, num_reported;
4152 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4153 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4154 if (!switch_config) {
4155 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4159 /* Get the switch configurations */
4160 ret = i40e_aq_get_switch_config(hw, switch_config,
4161 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4162 if (ret != I40E_SUCCESS) {
4163 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4166 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4167 if (num_reported != 1) { /* The number should be 1 */
4168 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4172 /* Parse the switch configuration elements */
4173 element = &(switch_config->element[0]);
4174 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4175 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4176 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4178 PMD_DRV_LOG(INFO, "Unknown element type");
4181 rte_free(switch_config);
4187 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4190 struct pool_entry *entry;
4192 if (pool == NULL || num == 0)
4195 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4196 if (entry == NULL) {
4197 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4201 /* queue heap initialize */
4202 pool->num_free = num;
4203 pool->num_alloc = 0;
4205 LIST_INIT(&pool->alloc_list);
4206 LIST_INIT(&pool->free_list);
4208 /* Initialize element */
4212 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4217 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4219 struct pool_entry *entry, *next_entry;
4224 for (entry = LIST_FIRST(&pool->alloc_list);
4225 entry && (next_entry = LIST_NEXT(entry, next), 1);
4226 entry = next_entry) {
4227 LIST_REMOVE(entry, next);
4231 for (entry = LIST_FIRST(&pool->free_list);
4232 entry && (next_entry = LIST_NEXT(entry, next), 1);
4233 entry = next_entry) {
4234 LIST_REMOVE(entry, next);
4239 pool->num_alloc = 0;
4241 LIST_INIT(&pool->alloc_list);
4242 LIST_INIT(&pool->free_list);
4246 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4249 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4250 uint32_t pool_offset;
4254 PMD_DRV_LOG(ERR, "Invalid parameter");
4258 pool_offset = base - pool->base;
4259 /* Lookup in alloc list */
4260 LIST_FOREACH(entry, &pool->alloc_list, next) {
4261 if (entry->base == pool_offset) {
4262 valid_entry = entry;
4263 LIST_REMOVE(entry, next);
4268 /* Not find, return */
4269 if (valid_entry == NULL) {
4270 PMD_DRV_LOG(ERR, "Failed to find entry");
4275 * Found it, move it to free list and try to merge.
4276 * In order to make merge easier, always sort it by qbase.
4277 * Find adjacent prev and last entries.
4280 LIST_FOREACH(entry, &pool->free_list, next) {
4281 if (entry->base > valid_entry->base) {
4289 /* Try to merge with next one*/
4291 /* Merge with next one */
4292 if (valid_entry->base + valid_entry->len == next->base) {
4293 next->base = valid_entry->base;
4294 next->len += valid_entry->len;
4295 rte_free(valid_entry);
4302 /* Merge with previous one */
4303 if (prev->base + prev->len == valid_entry->base) {
4304 prev->len += valid_entry->len;
4305 /* If it merge with next one, remove next node */
4307 LIST_REMOVE(valid_entry, next);
4308 rte_free(valid_entry);
4310 rte_free(valid_entry);
4316 /* Not find any entry to merge, insert */
4319 LIST_INSERT_AFTER(prev, valid_entry, next);
4320 else if (next != NULL)
4321 LIST_INSERT_BEFORE(next, valid_entry, next);
4322 else /* It's empty list, insert to head */
4323 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4326 pool->num_free += valid_entry->len;
4327 pool->num_alloc -= valid_entry->len;
4333 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4336 struct pool_entry *entry, *valid_entry;
4338 if (pool == NULL || num == 0) {
4339 PMD_DRV_LOG(ERR, "Invalid parameter");
4343 if (pool->num_free < num) {
4344 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4345 num, pool->num_free);
4350 /* Lookup in free list and find most fit one */
4351 LIST_FOREACH(entry, &pool->free_list, next) {
4352 if (entry->len >= num) {
4354 if (entry->len == num) {
4355 valid_entry = entry;
4358 if (valid_entry == NULL || valid_entry->len > entry->len)
4359 valid_entry = entry;
4363 /* Not find one to satisfy the request, return */
4364 if (valid_entry == NULL) {
4365 PMD_DRV_LOG(ERR, "No valid entry found");
4369 * The entry have equal queue number as requested,
4370 * remove it from alloc_list.
4372 if (valid_entry->len == num) {
4373 LIST_REMOVE(valid_entry, next);
4376 * The entry have more numbers than requested,
4377 * create a new entry for alloc_list and minus its
4378 * queue base and number in free_list.
4380 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4381 if (entry == NULL) {
4383 "Failed to allocate memory for resource pool");
4386 entry->base = valid_entry->base;
4388 valid_entry->base += num;
4389 valid_entry->len -= num;
4390 valid_entry = entry;
4393 /* Insert it into alloc list, not sorted */
4394 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4396 pool->num_free -= valid_entry->len;
4397 pool->num_alloc += valid_entry->len;
4399 return valid_entry->base + pool->base;
4403 * bitmap_is_subset - Check whether src2 is subset of src1
4406 bitmap_is_subset(uint8_t src1, uint8_t src2)
4408 return !((src1 ^ src2) & src2);
4411 static enum i40e_status_code
4412 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4414 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4416 /* If DCB is not supported, only default TC is supported */
4417 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4418 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4419 return I40E_NOT_SUPPORTED;
4422 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4424 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4425 hw->func_caps.enabled_tcmap, enabled_tcmap);
4426 return I40E_NOT_SUPPORTED;
4428 return I40E_SUCCESS;
4432 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4433 struct i40e_vsi_vlan_pvid_info *info)
4436 struct i40e_vsi_context ctxt;
4437 uint8_t vlan_flags = 0;
4440 if (vsi == NULL || info == NULL) {
4441 PMD_DRV_LOG(ERR, "invalid parameters");
4442 return I40E_ERR_PARAM;
4446 vsi->info.pvid = info->config.pvid;
4448 * If insert pvid is enabled, only tagged pkts are
4449 * allowed to be sent out.
4451 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4452 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4455 if (info->config.reject.tagged == 0)
4456 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4458 if (info->config.reject.untagged == 0)
4459 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4461 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4462 I40E_AQ_VSI_PVLAN_MODE_MASK);
4463 vsi->info.port_vlan_flags |= vlan_flags;
4464 vsi->info.valid_sections =
4465 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4466 memset(&ctxt, 0, sizeof(ctxt));
4467 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4468 ctxt.seid = vsi->seid;
4470 hw = I40E_VSI_TO_HW(vsi);
4471 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4472 if (ret != I40E_SUCCESS)
4473 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4479 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4481 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4483 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4485 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4486 if (ret != I40E_SUCCESS)
4490 PMD_DRV_LOG(ERR, "seid not valid");
4494 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4495 tc_bw_data.tc_valid_bits = enabled_tcmap;
4496 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4497 tc_bw_data.tc_bw_credits[i] =
4498 (enabled_tcmap & (1 << i)) ? 1 : 0;
4500 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4501 if (ret != I40E_SUCCESS) {
4502 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4506 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4507 sizeof(vsi->info.qs_handle));
4508 return I40E_SUCCESS;
4511 static enum i40e_status_code
4512 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4513 struct i40e_aqc_vsi_properties_data *info,
4514 uint8_t enabled_tcmap)
4516 enum i40e_status_code ret;
4517 int i, total_tc = 0;
4518 uint16_t qpnum_per_tc, bsf, qp_idx;
4520 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4521 if (ret != I40E_SUCCESS)
4524 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4525 if (enabled_tcmap & (1 << i))
4529 vsi->enabled_tc = enabled_tcmap;
4531 /* Number of queues per enabled TC */
4532 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4533 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4534 bsf = rte_bsf32(qpnum_per_tc);
4536 /* Adjust the queue number to actual queues that can be applied */
4537 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4538 vsi->nb_qps = qpnum_per_tc * total_tc;
4541 * Configure TC and queue mapping parameters, for enabled TC,
4542 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4543 * default queue will serve it.
4546 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4547 if (vsi->enabled_tc & (1 << i)) {
4548 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4549 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4550 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4551 qp_idx += qpnum_per_tc;
4553 info->tc_mapping[i] = 0;
4556 /* Associate queue number with VSI */
4557 if (vsi->type == I40E_VSI_SRIOV) {
4558 info->mapping_flags |=
4559 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4560 for (i = 0; i < vsi->nb_qps; i++)
4561 info->queue_mapping[i] =
4562 rte_cpu_to_le_16(vsi->base_queue + i);
4564 info->mapping_flags |=
4565 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4566 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4568 info->valid_sections |=
4569 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4571 return I40E_SUCCESS;
4575 i40e_veb_release(struct i40e_veb *veb)
4577 struct i40e_vsi *vsi;
4583 if (!TAILQ_EMPTY(&veb->head)) {
4584 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4587 /* associate_vsi field is NULL for floating VEB */
4588 if (veb->associate_vsi != NULL) {
4589 vsi = veb->associate_vsi;
4590 hw = I40E_VSI_TO_HW(vsi);
4592 vsi->uplink_seid = veb->uplink_seid;
4595 veb->associate_pf->main_vsi->floating_veb = NULL;
4596 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4599 i40e_aq_delete_element(hw, veb->seid, NULL);
4601 return I40E_SUCCESS;
4605 static struct i40e_veb *
4606 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4608 struct i40e_veb *veb;
4614 "veb setup failed, associated PF shouldn't null");
4617 hw = I40E_PF_TO_HW(pf);
4619 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4621 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4625 veb->associate_vsi = vsi;
4626 veb->associate_pf = pf;
4627 TAILQ_INIT(&veb->head);
4628 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4630 /* create floating veb if vsi is NULL */
4632 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4633 I40E_DEFAULT_TCMAP, false,
4634 &veb->seid, false, NULL);
4636 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4637 true, &veb->seid, false, NULL);
4640 if (ret != I40E_SUCCESS) {
4641 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4642 hw->aq.asq_last_status);
4645 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4647 /* get statistics index */
4648 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4649 &veb->stats_idx, NULL, NULL, NULL);
4650 if (ret != I40E_SUCCESS) {
4651 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4652 hw->aq.asq_last_status);
4655 /* Get VEB bandwidth, to be implemented */
4656 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4658 vsi->uplink_seid = veb->seid;
4667 i40e_vsi_release(struct i40e_vsi *vsi)
4671 struct i40e_vsi_list *vsi_list;
4674 struct i40e_mac_filter *f;
4675 uint16_t user_param;
4678 return I40E_SUCCESS;
4683 user_param = vsi->user_param;
4685 pf = I40E_VSI_TO_PF(vsi);
4686 hw = I40E_VSI_TO_HW(vsi);
4688 /* VSI has child to attach, release child first */
4690 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4691 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4694 i40e_veb_release(vsi->veb);
4697 if (vsi->floating_veb) {
4698 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4699 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4704 /* Remove all macvlan filters of the VSI */
4705 i40e_vsi_remove_all_macvlan_filter(vsi);
4706 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4709 if (vsi->type != I40E_VSI_MAIN &&
4710 ((vsi->type != I40E_VSI_SRIOV) ||
4711 !pf->floating_veb_list[user_param])) {
4712 /* Remove vsi from parent's sibling list */
4713 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4714 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4715 return I40E_ERR_PARAM;
4717 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4718 &vsi->sib_vsi_list, list);
4720 /* Remove all switch element of the VSI */
4721 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4722 if (ret != I40E_SUCCESS)
4723 PMD_DRV_LOG(ERR, "Failed to delete element");
4726 if ((vsi->type == I40E_VSI_SRIOV) &&
4727 pf->floating_veb_list[user_param]) {
4728 /* Remove vsi from parent's sibling list */
4729 if (vsi->parent_vsi == NULL ||
4730 vsi->parent_vsi->floating_veb == NULL) {
4731 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4732 return I40E_ERR_PARAM;
4734 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4735 &vsi->sib_vsi_list, list);
4737 /* Remove all switch element of the VSI */
4738 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4739 if (ret != I40E_SUCCESS)
4740 PMD_DRV_LOG(ERR, "Failed to delete element");
4743 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4745 if (vsi->type != I40E_VSI_SRIOV)
4746 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4749 return I40E_SUCCESS;
4753 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4755 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4756 struct i40e_aqc_remove_macvlan_element_data def_filter;
4757 struct i40e_mac_filter_info filter;
4760 if (vsi->type != I40E_VSI_MAIN)
4761 return I40E_ERR_CONFIG;
4762 memset(&def_filter, 0, sizeof(def_filter));
4763 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4765 def_filter.vlan_tag = 0;
4766 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4767 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4768 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4769 if (ret != I40E_SUCCESS) {
4770 struct i40e_mac_filter *f;
4771 struct ether_addr *mac;
4774 "Cannot remove the default macvlan filter");
4775 /* It needs to add the permanent mac into mac list */
4776 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4778 PMD_DRV_LOG(ERR, "failed to allocate memory");
4779 return I40E_ERR_NO_MEMORY;
4781 mac = &f->mac_info.mac_addr;
4782 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4784 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4785 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4790 rte_memcpy(&filter.mac_addr,
4791 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4792 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4793 return i40e_vsi_add_mac(vsi, &filter);
4797 * i40e_vsi_get_bw_config - Query VSI BW Information
4798 * @vsi: the VSI to be queried
4800 * Returns 0 on success, negative value on failure
4802 static enum i40e_status_code
4803 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4805 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4806 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4807 struct i40e_hw *hw = &vsi->adapter->hw;
4812 memset(&bw_config, 0, sizeof(bw_config));
4813 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4814 if (ret != I40E_SUCCESS) {
4815 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4816 hw->aq.asq_last_status);
4820 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4821 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4822 &ets_sla_config, NULL);
4823 if (ret != I40E_SUCCESS) {
4825 "VSI failed to get TC bandwdith configuration %u",
4826 hw->aq.asq_last_status);
4830 /* store and print out BW info */
4831 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4832 vsi->bw_info.bw_max = bw_config.max_bw;
4833 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4834 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4835 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4836 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4838 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4839 vsi->bw_info.bw_ets_share_credits[i] =
4840 ets_sla_config.share_credits[i];
4841 vsi->bw_info.bw_ets_credits[i] =
4842 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4843 /* 4 bits per TC, 4th bit is reserved */
4844 vsi->bw_info.bw_ets_max[i] =
4845 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4846 RTE_LEN2MASK(3, uint8_t));
4847 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4848 vsi->bw_info.bw_ets_share_credits[i]);
4849 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4850 vsi->bw_info.bw_ets_credits[i]);
4851 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4852 vsi->bw_info.bw_ets_max[i]);
4855 return I40E_SUCCESS;
4858 /* i40e_enable_pf_lb
4859 * @pf: pointer to the pf structure
4861 * allow loopback on pf
4864 i40e_enable_pf_lb(struct i40e_pf *pf)
4866 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4867 struct i40e_vsi_context ctxt;
4870 /* Use the FW API if FW >= v5.0 */
4871 if (hw->aq.fw_maj_ver < 5) {
4872 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4876 memset(&ctxt, 0, sizeof(ctxt));
4877 ctxt.seid = pf->main_vsi_seid;
4878 ctxt.pf_num = hw->pf_id;
4879 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4881 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4882 ret, hw->aq.asq_last_status);
4885 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4886 ctxt.info.valid_sections =
4887 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4888 ctxt.info.switch_id |=
4889 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4891 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4893 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4894 hw->aq.asq_last_status);
4899 i40e_vsi_setup(struct i40e_pf *pf,
4900 enum i40e_vsi_type type,
4901 struct i40e_vsi *uplink_vsi,
4902 uint16_t user_param)
4904 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4905 struct i40e_vsi *vsi;
4906 struct i40e_mac_filter_info filter;
4908 struct i40e_vsi_context ctxt;
4909 struct ether_addr broadcast =
4910 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4912 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4913 uplink_vsi == NULL) {
4915 "VSI setup failed, VSI link shouldn't be NULL");
4919 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4921 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4926 * 1.type is not MAIN and uplink vsi is not NULL
4927 * If uplink vsi didn't setup VEB, create one first under veb field
4928 * 2.type is SRIOV and the uplink is NULL
4929 * If floating VEB is NULL, create one veb under floating veb field
4932 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4933 uplink_vsi->veb == NULL) {
4934 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4936 if (uplink_vsi->veb == NULL) {
4937 PMD_DRV_LOG(ERR, "VEB setup failed");
4940 /* set ALLOWLOOPBACk on pf, when veb is created */
4941 i40e_enable_pf_lb(pf);
4944 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4945 pf->main_vsi->floating_veb == NULL) {
4946 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4948 if (pf->main_vsi->floating_veb == NULL) {
4949 PMD_DRV_LOG(ERR, "VEB setup failed");
4954 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4956 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4959 TAILQ_INIT(&vsi->mac_list);
4961 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4962 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4963 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4964 vsi->user_param = user_param;
4965 vsi->vlan_anti_spoof_on = 0;
4966 vsi->vlan_filter_on = 0;
4967 /* Allocate queues */
4968 switch (vsi->type) {
4969 case I40E_VSI_MAIN :
4970 vsi->nb_qps = pf->lan_nb_qps;
4972 case I40E_VSI_SRIOV :
4973 vsi->nb_qps = pf->vf_nb_qps;
4975 case I40E_VSI_VMDQ2:
4976 vsi->nb_qps = pf->vmdq_nb_qps;
4979 vsi->nb_qps = pf->fdir_nb_qps;
4985 * The filter status descriptor is reported in rx queue 0,
4986 * while the tx queue for fdir filter programming has no
4987 * such constraints, can be non-zero queues.
4988 * To simplify it, choose FDIR vsi use queue 0 pair.
4989 * To make sure it will use queue 0 pair, queue allocation
4990 * need be done before this function is called
4992 if (type != I40E_VSI_FDIR) {
4993 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4995 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4999 vsi->base_queue = ret;
5001 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5003 /* VF has MSIX interrupt in VF range, don't allocate here */
5004 if (type == I40E_VSI_MAIN) {
5005 ret = i40e_res_pool_alloc(&pf->msix_pool,
5006 RTE_MIN(vsi->nb_qps,
5007 RTE_MAX_RXTX_INTR_VEC_ID));
5009 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
5011 goto fail_queue_alloc;
5013 vsi->msix_intr = ret;
5014 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
5015 } else if (type != I40E_VSI_SRIOV) {
5016 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5018 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5019 goto fail_queue_alloc;
5021 vsi->msix_intr = ret;
5029 if (type == I40E_VSI_MAIN) {
5030 /* For main VSI, no need to add since it's default one */
5031 vsi->uplink_seid = pf->mac_seid;
5032 vsi->seid = pf->main_vsi_seid;
5033 /* Bind queues with specific MSIX interrupt */
5035 * Needs 2 interrupt at least, one for misc cause which will
5036 * enabled from OS side, Another for queues binding the
5037 * interrupt from device side only.
5040 /* Get default VSI parameters from hardware */
5041 memset(&ctxt, 0, sizeof(ctxt));
5042 ctxt.seid = vsi->seid;
5043 ctxt.pf_num = hw->pf_id;
5044 ctxt.uplink_seid = vsi->uplink_seid;
5046 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5047 if (ret != I40E_SUCCESS) {
5048 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5049 goto fail_msix_alloc;
5051 rte_memcpy(&vsi->info, &ctxt.info,
5052 sizeof(struct i40e_aqc_vsi_properties_data));
5053 vsi->vsi_id = ctxt.vsi_number;
5054 vsi->info.valid_sections = 0;
5056 /* Configure tc, enabled TC0 only */
5057 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5059 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5060 goto fail_msix_alloc;
5063 /* TC, queue mapping */
5064 memset(&ctxt, 0, sizeof(ctxt));
5065 vsi->info.valid_sections |=
5066 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5067 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5068 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5069 rte_memcpy(&ctxt.info, &vsi->info,
5070 sizeof(struct i40e_aqc_vsi_properties_data));
5071 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5072 I40E_DEFAULT_TCMAP);
5073 if (ret != I40E_SUCCESS) {
5075 "Failed to configure TC queue mapping");
5076 goto fail_msix_alloc;
5078 ctxt.seid = vsi->seid;
5079 ctxt.pf_num = hw->pf_id;
5080 ctxt.uplink_seid = vsi->uplink_seid;
5083 /* Update VSI parameters */
5084 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5085 if (ret != I40E_SUCCESS) {
5086 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5087 goto fail_msix_alloc;
5090 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5091 sizeof(vsi->info.tc_mapping));
5092 rte_memcpy(&vsi->info.queue_mapping,
5093 &ctxt.info.queue_mapping,
5094 sizeof(vsi->info.queue_mapping));
5095 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5096 vsi->info.valid_sections = 0;
5098 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5102 * Updating default filter settings are necessary to prevent
5103 * reception of tagged packets.
5104 * Some old firmware configurations load a default macvlan
5105 * filter which accepts both tagged and untagged packets.
5106 * The updating is to use a normal filter instead if needed.
5107 * For NVM 4.2.2 or after, the updating is not needed anymore.
5108 * The firmware with correct configurations load the default
5109 * macvlan filter which is expected and cannot be removed.
5111 i40e_update_default_filter_setting(vsi);
5112 i40e_config_qinq(hw, vsi);
5113 } else if (type == I40E_VSI_SRIOV) {
5114 memset(&ctxt, 0, sizeof(ctxt));
5116 * For other VSI, the uplink_seid equals to uplink VSI's
5117 * uplink_seid since they share same VEB
5119 if (uplink_vsi == NULL)
5120 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5122 vsi->uplink_seid = uplink_vsi->uplink_seid;
5123 ctxt.pf_num = hw->pf_id;
5124 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5125 ctxt.uplink_seid = vsi->uplink_seid;
5126 ctxt.connection_type = 0x1;
5127 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5129 /* Use the VEB configuration if FW >= v5.0 */
5130 if (hw->aq.fw_maj_ver >= 5) {
5131 /* Configure switch ID */
5132 ctxt.info.valid_sections |=
5133 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5134 ctxt.info.switch_id =
5135 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5138 /* Configure port/vlan */
5139 ctxt.info.valid_sections |=
5140 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5141 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5142 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5143 hw->func_caps.enabled_tcmap);
5144 if (ret != I40E_SUCCESS) {
5146 "Failed to configure TC queue mapping");
5147 goto fail_msix_alloc;
5150 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5151 ctxt.info.valid_sections |=
5152 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5154 * Since VSI is not created yet, only configure parameter,
5155 * will add vsi below.
5158 i40e_config_qinq(hw, vsi);
5159 } else if (type == I40E_VSI_VMDQ2) {
5160 memset(&ctxt, 0, sizeof(ctxt));
5162 * For other VSI, the uplink_seid equals to uplink VSI's
5163 * uplink_seid since they share same VEB
5165 vsi->uplink_seid = uplink_vsi->uplink_seid;
5166 ctxt.pf_num = hw->pf_id;
5168 ctxt.uplink_seid = vsi->uplink_seid;
5169 ctxt.connection_type = 0x1;
5170 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5172 ctxt.info.valid_sections |=
5173 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5174 /* user_param carries flag to enable loop back */
5176 ctxt.info.switch_id =
5177 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5178 ctxt.info.switch_id |=
5179 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5182 /* Configure port/vlan */
5183 ctxt.info.valid_sections |=
5184 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5185 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5186 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5187 I40E_DEFAULT_TCMAP);
5188 if (ret != I40E_SUCCESS) {
5190 "Failed to configure TC queue mapping");
5191 goto fail_msix_alloc;
5193 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5194 ctxt.info.valid_sections |=
5195 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5196 } else if (type == I40E_VSI_FDIR) {
5197 memset(&ctxt, 0, sizeof(ctxt));
5198 vsi->uplink_seid = uplink_vsi->uplink_seid;
5199 ctxt.pf_num = hw->pf_id;
5201 ctxt.uplink_seid = vsi->uplink_seid;
5202 ctxt.connection_type = 0x1; /* regular data port */
5203 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5204 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5205 I40E_DEFAULT_TCMAP);
5206 if (ret != I40E_SUCCESS) {
5208 "Failed to configure TC queue mapping.");
5209 goto fail_msix_alloc;
5211 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5212 ctxt.info.valid_sections |=
5213 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5215 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5216 goto fail_msix_alloc;
5219 if (vsi->type != I40E_VSI_MAIN) {
5220 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5221 if (ret != I40E_SUCCESS) {
5222 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5223 hw->aq.asq_last_status);
5224 goto fail_msix_alloc;
5226 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5227 vsi->info.valid_sections = 0;
5228 vsi->seid = ctxt.seid;
5229 vsi->vsi_id = ctxt.vsi_number;
5230 vsi->sib_vsi_list.vsi = vsi;
5231 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5232 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5233 &vsi->sib_vsi_list, list);
5235 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5236 &vsi->sib_vsi_list, list);
5240 /* MAC/VLAN configuration */
5241 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5242 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5244 ret = i40e_vsi_add_mac(vsi, &filter);
5245 if (ret != I40E_SUCCESS) {
5246 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5247 goto fail_msix_alloc;
5250 /* Get VSI BW information */
5251 i40e_vsi_get_bw_config(vsi);
5254 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5256 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5262 /* Configure vlan filter on or off */
5264 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5267 struct i40e_mac_filter *f;
5269 struct i40e_mac_filter_info *mac_filter;
5270 enum rte_mac_filter_type desired_filter;
5271 int ret = I40E_SUCCESS;
5274 /* Filter to match MAC and VLAN */
5275 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5277 /* Filter to match only MAC */
5278 desired_filter = RTE_MAC_PERFECT_MATCH;
5283 mac_filter = rte_zmalloc("mac_filter_info_data",
5284 num * sizeof(*mac_filter), 0);
5285 if (mac_filter == NULL) {
5286 PMD_DRV_LOG(ERR, "failed to allocate memory");
5287 return I40E_ERR_NO_MEMORY;
5292 /* Remove all existing mac */
5293 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5294 mac_filter[i] = f->mac_info;
5295 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5297 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5298 on ? "enable" : "disable");
5304 /* Override with new filter */
5305 for (i = 0; i < num; i++) {
5306 mac_filter[i].filter_type = desired_filter;
5307 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5309 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5310 on ? "enable" : "disable");
5316 rte_free(mac_filter);
5320 /* Configure vlan stripping on or off */
5322 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5324 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5325 struct i40e_vsi_context ctxt;
5327 int ret = I40E_SUCCESS;
5329 /* Check if it has been already on or off */
5330 if (vsi->info.valid_sections &
5331 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5333 if ((vsi->info.port_vlan_flags &
5334 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5335 return 0; /* already on */
5337 if ((vsi->info.port_vlan_flags &
5338 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5339 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5340 return 0; /* already off */
5345 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5347 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5348 vsi->info.valid_sections =
5349 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5350 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5351 vsi->info.port_vlan_flags |= vlan_flags;
5352 ctxt.seid = vsi->seid;
5353 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5354 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5356 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5357 on ? "enable" : "disable");
5363 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5365 struct rte_eth_dev_data *data = dev->data;
5369 /* Apply vlan offload setting */
5370 mask = ETH_VLAN_STRIP_MASK |
5371 ETH_VLAN_FILTER_MASK |
5372 ETH_VLAN_EXTEND_MASK;
5373 ret = i40e_vlan_offload_set(dev, mask);
5375 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5379 /* Apply pvid setting */
5380 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5381 data->dev_conf.txmode.hw_vlan_insert_pvid);
5383 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5389 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5391 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5393 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5397 i40e_update_flow_control(struct i40e_hw *hw)
5399 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5400 struct i40e_link_status link_status;
5401 uint32_t rxfc = 0, txfc = 0, reg;
5405 memset(&link_status, 0, sizeof(link_status));
5406 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5407 if (ret != I40E_SUCCESS) {
5408 PMD_DRV_LOG(ERR, "Failed to get link status information");
5409 goto write_reg; /* Disable flow control */
5412 an_info = hw->phy.link_info.an_info;
5413 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5414 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5415 ret = I40E_ERR_NOT_READY;
5416 goto write_reg; /* Disable flow control */
5419 * If link auto negotiation is enabled, flow control needs to
5420 * be configured according to it
5422 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5423 case I40E_LINK_PAUSE_RXTX:
5426 hw->fc.current_mode = I40E_FC_FULL;
5428 case I40E_AQ_LINK_PAUSE_RX:
5430 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5432 case I40E_AQ_LINK_PAUSE_TX:
5434 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5437 hw->fc.current_mode = I40E_FC_NONE;
5442 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5443 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5444 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5445 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5446 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5447 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5454 i40e_pf_setup(struct i40e_pf *pf)
5456 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5457 struct i40e_filter_control_settings settings;
5458 struct i40e_vsi *vsi;
5461 /* Clear all stats counters */
5462 pf->offset_loaded = FALSE;
5463 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5464 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5465 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5466 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5468 ret = i40e_pf_get_switch_config(pf);
5469 if (ret != I40E_SUCCESS) {
5470 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5473 if (pf->flags & I40E_FLAG_FDIR) {
5474 /* make queue allocated first, let FDIR use queue pair 0*/
5475 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5476 if (ret != I40E_FDIR_QUEUE_ID) {
5478 "queue allocation fails for FDIR: ret =%d",
5480 pf->flags &= ~I40E_FLAG_FDIR;
5483 /* main VSI setup */
5484 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5486 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5487 return I40E_ERR_NOT_READY;
5491 /* Configure filter control */
5492 memset(&settings, 0, sizeof(settings));
5493 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5494 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5495 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5496 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5498 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5499 hw->func_caps.rss_table_size);
5500 return I40E_ERR_PARAM;
5502 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5503 hw->func_caps.rss_table_size);
5504 pf->hash_lut_size = hw->func_caps.rss_table_size;
5506 /* Enable ethtype and macvlan filters */
5507 settings.enable_ethtype = TRUE;
5508 settings.enable_macvlan = TRUE;
5509 ret = i40e_set_filter_control(hw, &settings);
5511 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5514 /* Update flow control according to the auto negotiation */
5515 i40e_update_flow_control(hw);
5517 return I40E_SUCCESS;
5521 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5527 * Set or clear TX Queue Disable flags,
5528 * which is required by hardware.
5530 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5531 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5533 /* Wait until the request is finished */
5534 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5535 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5536 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5537 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5538 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5544 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5545 return I40E_SUCCESS; /* already on, skip next steps */
5547 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5548 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5550 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5551 return I40E_SUCCESS; /* already off, skip next steps */
5552 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5554 /* Write the register */
5555 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5556 /* Check the result */
5557 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5558 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5559 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5561 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5562 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5565 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5566 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5570 /* Check if it is timeout */
5571 if (j >= I40E_CHK_Q_ENA_COUNT) {
5572 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5573 (on ? "enable" : "disable"), q_idx);
5574 return I40E_ERR_TIMEOUT;
5577 return I40E_SUCCESS;
5580 /* Swith on or off the tx queues */
5582 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5584 struct rte_eth_dev_data *dev_data = pf->dev_data;
5585 struct i40e_tx_queue *txq;
5586 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5590 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5591 txq = dev_data->tx_queues[i];
5592 /* Don't operate the queue if not configured or
5593 * if starting only per queue */
5594 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5597 ret = i40e_dev_tx_queue_start(dev, i);
5599 ret = i40e_dev_tx_queue_stop(dev, i);
5600 if ( ret != I40E_SUCCESS)
5604 return I40E_SUCCESS;
5608 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5613 /* Wait until the request is finished */
5614 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5615 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5616 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5617 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5618 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5623 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5624 return I40E_SUCCESS; /* Already on, skip next steps */
5625 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5627 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5628 return I40E_SUCCESS; /* Already off, skip next steps */
5629 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5632 /* Write the register */
5633 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5634 /* Check the result */
5635 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5636 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5637 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5639 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5640 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5643 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5644 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5649 /* Check if it is timeout */
5650 if (j >= I40E_CHK_Q_ENA_COUNT) {
5651 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5652 (on ? "enable" : "disable"), q_idx);
5653 return I40E_ERR_TIMEOUT;
5656 return I40E_SUCCESS;
5658 /* Switch on or off the rx queues */
5660 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5662 struct rte_eth_dev_data *dev_data = pf->dev_data;
5663 struct i40e_rx_queue *rxq;
5664 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5668 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5669 rxq = dev_data->rx_queues[i];
5670 /* Don't operate the queue if not configured or
5671 * if starting only per queue */
5672 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5675 ret = i40e_dev_rx_queue_start(dev, i);
5677 ret = i40e_dev_rx_queue_stop(dev, i);
5678 if (ret != I40E_SUCCESS)
5682 return I40E_SUCCESS;
5685 /* Switch on or off all the rx/tx queues */
5687 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5692 /* enable rx queues before enabling tx queues */
5693 ret = i40e_dev_switch_rx_queues(pf, on);
5695 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5698 ret = i40e_dev_switch_tx_queues(pf, on);
5700 /* Stop tx queues before stopping rx queues */
5701 ret = i40e_dev_switch_tx_queues(pf, on);
5703 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5706 ret = i40e_dev_switch_rx_queues(pf, on);
5712 /* Initialize VSI for TX */
5714 i40e_dev_tx_init(struct i40e_pf *pf)
5716 struct rte_eth_dev_data *data = pf->dev_data;
5718 uint32_t ret = I40E_SUCCESS;
5719 struct i40e_tx_queue *txq;
5721 for (i = 0; i < data->nb_tx_queues; i++) {
5722 txq = data->tx_queues[i];
5723 if (!txq || !txq->q_set)
5725 ret = i40e_tx_queue_init(txq);
5726 if (ret != I40E_SUCCESS)
5729 if (ret == I40E_SUCCESS)
5730 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5736 /* Initialize VSI for RX */
5738 i40e_dev_rx_init(struct i40e_pf *pf)
5740 struct rte_eth_dev_data *data = pf->dev_data;
5741 int ret = I40E_SUCCESS;
5743 struct i40e_rx_queue *rxq;
5745 i40e_pf_config_mq_rx(pf);
5746 for (i = 0; i < data->nb_rx_queues; i++) {
5747 rxq = data->rx_queues[i];
5748 if (!rxq || !rxq->q_set)
5751 ret = i40e_rx_queue_init(rxq);
5752 if (ret != I40E_SUCCESS) {
5754 "Failed to do RX queue initialization");
5758 if (ret == I40E_SUCCESS)
5759 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5766 i40e_dev_rxtx_init(struct i40e_pf *pf)
5770 err = i40e_dev_tx_init(pf);
5772 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5775 err = i40e_dev_rx_init(pf);
5777 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5785 i40e_vmdq_setup(struct rte_eth_dev *dev)
5787 struct rte_eth_conf *conf = &dev->data->dev_conf;
5788 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5789 int i, err, conf_vsis, j, loop;
5790 struct i40e_vsi *vsi;
5791 struct i40e_vmdq_info *vmdq_info;
5792 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5793 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5796 * Disable interrupt to avoid message from VF. Furthermore, it will
5797 * avoid race condition in VSI creation/destroy.
5799 i40e_pf_disable_irq0(hw);
5801 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5802 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5806 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5807 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5808 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5809 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5810 pf->max_nb_vmdq_vsi);
5814 if (pf->vmdq != NULL) {
5815 PMD_INIT_LOG(INFO, "VMDQ already configured");
5819 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5820 sizeof(*vmdq_info) * conf_vsis, 0);
5822 if (pf->vmdq == NULL) {
5823 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5827 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5829 /* Create VMDQ VSI */
5830 for (i = 0; i < conf_vsis; i++) {
5831 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5832 vmdq_conf->enable_loop_back);
5834 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5838 vmdq_info = &pf->vmdq[i];
5840 vmdq_info->vsi = vsi;
5842 pf->nb_cfg_vmdq_vsi = conf_vsis;
5844 /* Configure Vlan */
5845 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5846 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5847 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5848 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5849 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5850 vmdq_conf->pool_map[i].vlan_id, j);
5852 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5853 vmdq_conf->pool_map[i].vlan_id);
5855 PMD_INIT_LOG(ERR, "Failed to add vlan");
5863 i40e_pf_enable_irq0(hw);
5868 for (i = 0; i < conf_vsis; i++)
5869 if (pf->vmdq[i].vsi == NULL)
5872 i40e_vsi_release(pf->vmdq[i].vsi);
5876 i40e_pf_enable_irq0(hw);
5881 i40e_stat_update_32(struct i40e_hw *hw,
5889 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5893 if (new_data >= *offset)
5894 *stat = (uint64_t)(new_data - *offset);
5896 *stat = (uint64_t)((new_data +
5897 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5901 i40e_stat_update_48(struct i40e_hw *hw,
5910 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5911 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5912 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5917 if (new_data >= *offset)
5918 *stat = new_data - *offset;
5920 *stat = (uint64_t)((new_data +
5921 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5923 *stat &= I40E_48_BIT_MASK;
5928 i40e_pf_disable_irq0(struct i40e_hw *hw)
5930 /* Disable all interrupt types */
5931 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5932 I40E_WRITE_FLUSH(hw);
5937 i40e_pf_enable_irq0(struct i40e_hw *hw)
5939 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5940 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5941 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5942 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5943 I40E_WRITE_FLUSH(hw);
5947 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5949 /* read pending request and disable first */
5950 i40e_pf_disable_irq0(hw);
5951 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5952 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5953 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5956 /* Link no queues with irq0 */
5957 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5958 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5962 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5964 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5965 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5968 uint32_t index, offset, val;
5973 * Try to find which VF trigger a reset, use absolute VF id to access
5974 * since the reg is global register.
5976 for (i = 0; i < pf->vf_num; i++) {
5977 abs_vf_id = hw->func_caps.vf_base_id + i;
5978 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5979 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5980 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5981 /* VFR event occurred */
5982 if (val & (0x1 << offset)) {
5985 /* Clear the event first */
5986 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5988 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5990 * Only notify a VF reset event occurred,
5991 * don't trigger another SW reset
5993 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5994 if (ret != I40E_SUCCESS)
5995 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6001 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6003 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6006 for (i = 0; i < pf->vf_num; i++)
6007 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6011 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6013 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6014 struct i40e_arq_event_info info;
6015 uint16_t pending, opcode;
6018 info.buf_len = I40E_AQ_BUF_SZ;
6019 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6020 if (!info.msg_buf) {
6021 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6027 ret = i40e_clean_arq_element(hw, &info, &pending);
6029 if (ret != I40E_SUCCESS) {
6031 "Failed to read msg from AdminQ, aq_err: %u",
6032 hw->aq.asq_last_status);
6035 opcode = rte_le_to_cpu_16(info.desc.opcode);
6038 case i40e_aqc_opc_send_msg_to_pf:
6039 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6040 i40e_pf_host_handle_vf_msg(dev,
6041 rte_le_to_cpu_16(info.desc.retval),
6042 rte_le_to_cpu_32(info.desc.cookie_high),
6043 rte_le_to_cpu_32(info.desc.cookie_low),
6047 case i40e_aqc_opc_get_link_status:
6048 ret = i40e_dev_link_update(dev, 0);
6050 _rte_eth_dev_callback_process(dev,
6051 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
6054 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6059 rte_free(info.msg_buf);
6063 * Interrupt handler triggered by NIC for handling
6064 * specific interrupt.
6067 * Pointer to interrupt handle.
6069 * The address of parameter (struct rte_eth_dev *) regsitered before.
6075 i40e_dev_interrupt_handler(void *param)
6077 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6078 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6081 /* Disable interrupt */
6082 i40e_pf_disable_irq0(hw);
6084 /* read out interrupt causes */
6085 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6087 /* No interrupt event indicated */
6088 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6089 PMD_DRV_LOG(INFO, "No interrupt event");
6092 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6093 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6094 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6095 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6096 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6097 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6098 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6099 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6100 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6101 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6102 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6103 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6104 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6105 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6107 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6108 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6109 i40e_dev_handle_vfr_event(dev);
6111 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6112 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6113 i40e_dev_handle_aq_msg(dev);
6117 /* Enable interrupt */
6118 i40e_pf_enable_irq0(hw);
6119 rte_intr_enable(dev->intr_handle);
6123 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6124 struct i40e_macvlan_filter *filter,
6127 int ele_num, ele_buff_size;
6128 int num, actual_num, i;
6130 int ret = I40E_SUCCESS;
6131 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6132 struct i40e_aqc_add_macvlan_element_data *req_list;
6134 if (filter == NULL || total == 0)
6135 return I40E_ERR_PARAM;
6136 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6137 ele_buff_size = hw->aq.asq_buf_size;
6139 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6140 if (req_list == NULL) {
6141 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6142 return I40E_ERR_NO_MEMORY;
6147 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6148 memset(req_list, 0, ele_buff_size);
6150 for (i = 0; i < actual_num; i++) {
6151 rte_memcpy(req_list[i].mac_addr,
6152 &filter[num + i].macaddr, ETH_ADDR_LEN);
6153 req_list[i].vlan_tag =
6154 rte_cpu_to_le_16(filter[num + i].vlan_id);
6156 switch (filter[num + i].filter_type) {
6157 case RTE_MAC_PERFECT_MATCH:
6158 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6159 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6161 case RTE_MACVLAN_PERFECT_MATCH:
6162 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6164 case RTE_MAC_HASH_MATCH:
6165 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6166 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6168 case RTE_MACVLAN_HASH_MATCH:
6169 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6172 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6173 ret = I40E_ERR_PARAM;
6177 req_list[i].queue_number = 0;
6179 req_list[i].flags = rte_cpu_to_le_16(flags);
6182 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6184 if (ret != I40E_SUCCESS) {
6185 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6189 } while (num < total);
6197 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6198 struct i40e_macvlan_filter *filter,
6201 int ele_num, ele_buff_size;
6202 int num, actual_num, i;
6204 int ret = I40E_SUCCESS;
6205 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6206 struct i40e_aqc_remove_macvlan_element_data *req_list;
6208 if (filter == NULL || total == 0)
6209 return I40E_ERR_PARAM;
6211 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6212 ele_buff_size = hw->aq.asq_buf_size;
6214 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6215 if (req_list == NULL) {
6216 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6217 return I40E_ERR_NO_MEMORY;
6222 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6223 memset(req_list, 0, ele_buff_size);
6225 for (i = 0; i < actual_num; i++) {
6226 rte_memcpy(req_list[i].mac_addr,
6227 &filter[num + i].macaddr, ETH_ADDR_LEN);
6228 req_list[i].vlan_tag =
6229 rte_cpu_to_le_16(filter[num + i].vlan_id);
6231 switch (filter[num + i].filter_type) {
6232 case RTE_MAC_PERFECT_MATCH:
6233 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6234 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6236 case RTE_MACVLAN_PERFECT_MATCH:
6237 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6239 case RTE_MAC_HASH_MATCH:
6240 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6241 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6243 case RTE_MACVLAN_HASH_MATCH:
6244 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6247 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6248 ret = I40E_ERR_PARAM;
6251 req_list[i].flags = rte_cpu_to_le_16(flags);
6254 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6256 if (ret != I40E_SUCCESS) {
6257 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6261 } while (num < total);
6268 /* Find out specific MAC filter */
6269 static struct i40e_mac_filter *
6270 i40e_find_mac_filter(struct i40e_vsi *vsi,
6271 struct ether_addr *macaddr)
6273 struct i40e_mac_filter *f;
6275 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6276 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6284 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6287 uint32_t vid_idx, vid_bit;
6289 if (vlan_id > ETH_VLAN_ID_MAX)
6292 vid_idx = I40E_VFTA_IDX(vlan_id);
6293 vid_bit = I40E_VFTA_BIT(vlan_id);
6295 if (vsi->vfta[vid_idx] & vid_bit)
6302 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6303 uint16_t vlan_id, bool on)
6305 uint32_t vid_idx, vid_bit;
6307 vid_idx = I40E_VFTA_IDX(vlan_id);
6308 vid_bit = I40E_VFTA_BIT(vlan_id);
6311 vsi->vfta[vid_idx] |= vid_bit;
6313 vsi->vfta[vid_idx] &= ~vid_bit;
6317 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6318 uint16_t vlan_id, bool on)
6320 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6321 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6324 if (vlan_id > ETH_VLAN_ID_MAX)
6327 i40e_store_vlan_filter(vsi, vlan_id, on);
6329 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6332 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6335 ret = i40e_aq_add_vlan(hw, vsi->seid,
6336 &vlan_data, 1, NULL);
6337 if (ret != I40E_SUCCESS)
6338 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6340 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6341 &vlan_data, 1, NULL);
6342 if (ret != I40E_SUCCESS)
6344 "Failed to remove vlan filter");
6349 * Find all vlan options for specific mac addr,
6350 * return with actual vlan found.
6353 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6354 struct i40e_macvlan_filter *mv_f,
6355 int num, struct ether_addr *addr)
6361 * Not to use i40e_find_vlan_filter to decrease the loop time,
6362 * although the code looks complex.
6364 if (num < vsi->vlan_num)
6365 return I40E_ERR_PARAM;
6368 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6370 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6371 if (vsi->vfta[j] & (1 << k)) {
6374 "vlan number doesn't match");
6375 return I40E_ERR_PARAM;
6377 rte_memcpy(&mv_f[i].macaddr,
6378 addr, ETH_ADDR_LEN);
6380 j * I40E_UINT32_BIT_SIZE + k;
6386 return I40E_SUCCESS;
6390 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6391 struct i40e_macvlan_filter *mv_f,
6396 struct i40e_mac_filter *f;
6398 if (num < vsi->mac_num)
6399 return I40E_ERR_PARAM;
6401 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6403 PMD_DRV_LOG(ERR, "buffer number not match");
6404 return I40E_ERR_PARAM;
6406 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6408 mv_f[i].vlan_id = vlan;
6409 mv_f[i].filter_type = f->mac_info.filter_type;
6413 return I40E_SUCCESS;
6417 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6420 struct i40e_mac_filter *f;
6421 struct i40e_macvlan_filter *mv_f;
6422 int ret = I40E_SUCCESS;
6424 if (vsi == NULL || vsi->mac_num == 0)
6425 return I40E_ERR_PARAM;
6427 /* Case that no vlan is set */
6428 if (vsi->vlan_num == 0)
6431 num = vsi->mac_num * vsi->vlan_num;
6433 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6435 PMD_DRV_LOG(ERR, "failed to allocate memory");
6436 return I40E_ERR_NO_MEMORY;
6440 if (vsi->vlan_num == 0) {
6441 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6442 rte_memcpy(&mv_f[i].macaddr,
6443 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6444 mv_f[i].filter_type = f->mac_info.filter_type;
6445 mv_f[i].vlan_id = 0;
6449 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6450 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6451 vsi->vlan_num, &f->mac_info.mac_addr);
6452 if (ret != I40E_SUCCESS)
6454 for (j = i; j < i + vsi->vlan_num; j++)
6455 mv_f[j].filter_type = f->mac_info.filter_type;
6460 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6468 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6470 struct i40e_macvlan_filter *mv_f;
6472 int ret = I40E_SUCCESS;
6474 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6475 return I40E_ERR_PARAM;
6477 /* If it's already set, just return */
6478 if (i40e_find_vlan_filter(vsi,vlan))
6479 return I40E_SUCCESS;
6481 mac_num = vsi->mac_num;
6484 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6485 return I40E_ERR_PARAM;
6488 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6491 PMD_DRV_LOG(ERR, "failed to allocate memory");
6492 return I40E_ERR_NO_MEMORY;
6495 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6497 if (ret != I40E_SUCCESS)
6500 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6502 if (ret != I40E_SUCCESS)
6505 i40e_set_vlan_filter(vsi, vlan, 1);
6515 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6517 struct i40e_macvlan_filter *mv_f;
6519 int ret = I40E_SUCCESS;
6522 * Vlan 0 is the generic filter for untagged packets
6523 * and can't be removed.
6525 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6526 return I40E_ERR_PARAM;
6528 /* If can't find it, just return */
6529 if (!i40e_find_vlan_filter(vsi, vlan))
6530 return I40E_ERR_PARAM;
6532 mac_num = vsi->mac_num;
6535 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6536 return I40E_ERR_PARAM;
6539 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6542 PMD_DRV_LOG(ERR, "failed to allocate memory");
6543 return I40E_ERR_NO_MEMORY;
6546 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6548 if (ret != I40E_SUCCESS)
6551 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6553 if (ret != I40E_SUCCESS)
6556 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6557 if (vsi->vlan_num == 1) {
6558 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6559 if (ret != I40E_SUCCESS)
6562 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6563 if (ret != I40E_SUCCESS)
6567 i40e_set_vlan_filter(vsi, vlan, 0);
6577 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6579 struct i40e_mac_filter *f;
6580 struct i40e_macvlan_filter *mv_f;
6581 int i, vlan_num = 0;
6582 int ret = I40E_SUCCESS;
6584 /* If it's add and we've config it, return */
6585 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6587 return I40E_SUCCESS;
6588 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6589 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6592 * If vlan_num is 0, that's the first time to add mac,
6593 * set mask for vlan_id 0.
6595 if (vsi->vlan_num == 0) {
6596 i40e_set_vlan_filter(vsi, 0, 1);
6599 vlan_num = vsi->vlan_num;
6600 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6601 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6604 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6606 PMD_DRV_LOG(ERR, "failed to allocate memory");
6607 return I40E_ERR_NO_MEMORY;
6610 for (i = 0; i < vlan_num; i++) {
6611 mv_f[i].filter_type = mac_filter->filter_type;
6612 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6616 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6617 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6618 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6619 &mac_filter->mac_addr);
6620 if (ret != I40E_SUCCESS)
6624 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6625 if (ret != I40E_SUCCESS)
6628 /* Add the mac addr into mac list */
6629 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6631 PMD_DRV_LOG(ERR, "failed to allocate memory");
6632 ret = I40E_ERR_NO_MEMORY;
6635 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6637 f->mac_info.filter_type = mac_filter->filter_type;
6638 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6649 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6651 struct i40e_mac_filter *f;
6652 struct i40e_macvlan_filter *mv_f;
6654 enum rte_mac_filter_type filter_type;
6655 int ret = I40E_SUCCESS;
6657 /* Can't find it, return an error */
6658 f = i40e_find_mac_filter(vsi, addr);
6660 return I40E_ERR_PARAM;
6662 vlan_num = vsi->vlan_num;
6663 filter_type = f->mac_info.filter_type;
6664 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6665 filter_type == RTE_MACVLAN_HASH_MATCH) {
6666 if (vlan_num == 0) {
6667 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6668 return I40E_ERR_PARAM;
6670 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6671 filter_type == RTE_MAC_HASH_MATCH)
6674 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6676 PMD_DRV_LOG(ERR, "failed to allocate memory");
6677 return I40E_ERR_NO_MEMORY;
6680 for (i = 0; i < vlan_num; i++) {
6681 mv_f[i].filter_type = filter_type;
6682 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6685 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6686 filter_type == RTE_MACVLAN_HASH_MATCH) {
6687 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6688 if (ret != I40E_SUCCESS)
6692 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6693 if (ret != I40E_SUCCESS)
6696 /* Remove the mac addr into mac list */
6697 TAILQ_REMOVE(&vsi->mac_list, f, next);
6707 /* Configure hash enable flags for RSS */
6709 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6717 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6718 if (flags & (1ULL << i))
6719 hena |= adapter->pctypes_tbl[i];
6725 /* Parse the hash enable flags */
6727 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6729 uint64_t rss_hf = 0;
6735 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6736 if (flags & adapter->pctypes_tbl[i])
6737 rss_hf |= (1ULL << i);
6744 i40e_pf_disable_rss(struct i40e_pf *pf)
6746 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6748 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6749 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6750 I40E_WRITE_FLUSH(hw);
6754 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6756 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6757 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6760 if (!key || key_len == 0) {
6761 PMD_DRV_LOG(DEBUG, "No key to be configured");
6763 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6765 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6769 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6770 struct i40e_aqc_get_set_rss_key_data *key_dw =
6771 (struct i40e_aqc_get_set_rss_key_data *)key;
6773 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6775 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6777 uint32_t *hash_key = (uint32_t *)key;
6780 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6781 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6782 I40E_WRITE_FLUSH(hw);
6789 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6791 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6792 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6795 if (!key || !key_len)
6798 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6799 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6800 (struct i40e_aqc_get_set_rss_key_data *)key);
6802 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6806 uint32_t *key_dw = (uint32_t *)key;
6809 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6810 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6812 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6818 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6820 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6824 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6825 rss_conf->rss_key_len);
6829 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6830 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6831 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6832 I40E_WRITE_FLUSH(hw);
6838 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6839 struct rte_eth_rss_conf *rss_conf)
6841 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6842 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6843 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6846 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6847 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6849 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6850 if (rss_hf != 0) /* Enable RSS */
6852 return 0; /* Nothing to do */
6855 if (rss_hf == 0) /* Disable RSS */
6858 return i40e_hw_rss_hash_set(pf, rss_conf);
6862 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6863 struct rte_eth_rss_conf *rss_conf)
6865 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6866 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6869 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6870 &rss_conf->rss_key_len);
6872 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6873 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6874 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6880 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6882 switch (filter_type) {
6883 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6884 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6886 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6887 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6889 case RTE_TUNNEL_FILTER_IMAC_TENID:
6890 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6892 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6893 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6895 case ETH_TUNNEL_FILTER_IMAC:
6896 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6898 case ETH_TUNNEL_FILTER_OIP:
6899 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6901 case ETH_TUNNEL_FILTER_IIP:
6902 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6905 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6912 /* Convert tunnel filter structure */
6914 i40e_tunnel_filter_convert(
6915 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6916 struct i40e_tunnel_filter *tunnel_filter)
6918 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6919 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6920 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6921 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6922 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6923 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6924 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6925 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6926 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6928 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6929 tunnel_filter->input.flags = cld_filter->element.flags;
6930 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6931 tunnel_filter->queue = cld_filter->element.queue_number;
6932 rte_memcpy(tunnel_filter->input.general_fields,
6933 cld_filter->general_fields,
6934 sizeof(cld_filter->general_fields));
6939 /* Check if there exists the tunnel filter */
6940 struct i40e_tunnel_filter *
6941 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6942 const struct i40e_tunnel_filter_input *input)
6946 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6950 return tunnel_rule->hash_map[ret];
6953 /* Add a tunnel filter into the SW list */
6955 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6956 struct i40e_tunnel_filter *tunnel_filter)
6958 struct i40e_tunnel_rule *rule = &pf->tunnel;
6961 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6964 "Failed to insert tunnel filter to hash table %d!",
6968 rule->hash_map[ret] = tunnel_filter;
6970 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6975 /* Delete a tunnel filter from the SW list */
6977 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6978 struct i40e_tunnel_filter_input *input)
6980 struct i40e_tunnel_rule *rule = &pf->tunnel;
6981 struct i40e_tunnel_filter *tunnel_filter;
6984 ret = rte_hash_del_key(rule->hash_table, input);
6987 "Failed to delete tunnel filter to hash table %d!",
6991 tunnel_filter = rule->hash_map[ret];
6992 rule->hash_map[ret] = NULL;
6994 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6995 rte_free(tunnel_filter);
7001 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7002 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7006 uint32_t ipv4_addr, ipv4_addr_le;
7007 uint8_t i, tun_type = 0;
7008 /* internal varialbe to convert ipv6 byte order */
7009 uint32_t convert_ipv6[4];
7011 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7012 struct i40e_vsi *vsi = pf->main_vsi;
7013 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7014 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7015 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7016 struct i40e_tunnel_filter *tunnel, *node;
7017 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7019 cld_filter = rte_zmalloc("tunnel_filter",
7020 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7023 if (NULL == cld_filter) {
7024 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7027 pfilter = cld_filter;
7029 ether_addr_copy(&tunnel_filter->outer_mac,
7030 (struct ether_addr *)&pfilter->element.outer_mac);
7031 ether_addr_copy(&tunnel_filter->inner_mac,
7032 (struct ether_addr *)&pfilter->element.inner_mac);
7034 pfilter->element.inner_vlan =
7035 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7036 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7037 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7038 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7039 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7040 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7042 sizeof(pfilter->element.ipaddr.v4.data));
7044 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7045 for (i = 0; i < 4; i++) {
7047 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7049 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7051 sizeof(pfilter->element.ipaddr.v6.data));
7054 /* check tunneled type */
7055 switch (tunnel_filter->tunnel_type) {
7056 case RTE_TUNNEL_TYPE_VXLAN:
7057 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7059 case RTE_TUNNEL_TYPE_NVGRE:
7060 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7062 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7063 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7066 /* Other tunnel types is not supported. */
7067 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7068 rte_free(cld_filter);
7072 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7073 &pfilter->element.flags);
7075 rte_free(cld_filter);
7079 pfilter->element.flags |= rte_cpu_to_le_16(
7080 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7081 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7082 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7083 pfilter->element.queue_number =
7084 rte_cpu_to_le_16(tunnel_filter->queue_id);
7086 /* Check if there is the filter in SW list */
7087 memset(&check_filter, 0, sizeof(check_filter));
7088 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7089 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7091 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7095 if (!add && !node) {
7096 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7101 ret = i40e_aq_add_cloud_filters(hw,
7102 vsi->seid, &cld_filter->element, 1);
7104 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7107 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7108 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7109 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7111 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7112 &cld_filter->element, 1);
7114 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7117 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7120 rte_free(cld_filter);
7124 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7125 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7126 #define I40E_TR_GENEVE_KEY_MASK 0x8
7127 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7128 #define I40E_TR_GRE_KEY_MASK 0x400
7129 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7130 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7133 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7135 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7136 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7137 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7138 enum i40e_status_code status = I40E_SUCCESS;
7140 memset(&filter_replace, 0,
7141 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7142 memset(&filter_replace_buf, 0,
7143 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7145 /* create L1 filter */
7146 filter_replace.old_filter_type =
7147 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7148 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7149 filter_replace.tr_bit = 0;
7151 /* Prepare the buffer, 3 entries */
7152 filter_replace_buf.data[0] =
7153 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7154 filter_replace_buf.data[0] |=
7155 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7156 filter_replace_buf.data[2] = 0xFF;
7157 filter_replace_buf.data[3] = 0xFF;
7158 filter_replace_buf.data[4] =
7159 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7160 filter_replace_buf.data[4] |=
7161 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7162 filter_replace_buf.data[7] = 0xF0;
7163 filter_replace_buf.data[8]
7164 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7165 filter_replace_buf.data[8] |=
7166 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7167 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7168 I40E_TR_GENEVE_KEY_MASK |
7169 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7170 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7171 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7172 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7174 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7175 &filter_replace_buf);
7180 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7182 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7183 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7184 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7185 enum i40e_status_code status = I40E_SUCCESS;
7188 memset(&filter_replace, 0,
7189 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7190 memset(&filter_replace_buf, 0,
7191 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7192 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7193 I40E_AQC_MIRROR_CLOUD_FILTER;
7194 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7195 filter_replace.new_filter_type =
7196 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7197 /* Prepare the buffer, 2 entries */
7198 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7199 filter_replace_buf.data[0] |=
7200 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7201 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7202 filter_replace_buf.data[4] |=
7203 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7204 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7205 &filter_replace_buf);
7210 memset(&filter_replace, 0,
7211 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7212 memset(&filter_replace_buf, 0,
7213 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7215 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7216 I40E_AQC_MIRROR_CLOUD_FILTER;
7217 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7218 filter_replace.new_filter_type =
7219 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7220 /* Prepare the buffer, 2 entries */
7221 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7222 filter_replace_buf.data[0] |=
7223 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7224 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7225 filter_replace_buf.data[4] |=
7226 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7228 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7229 &filter_replace_buf);
7233 static enum i40e_status_code
7234 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7236 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7237 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7238 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7239 enum i40e_status_code status = I40E_SUCCESS;
7242 memset(&filter_replace, 0,
7243 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7244 memset(&filter_replace_buf, 0,
7245 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7246 /* create L1 filter */
7247 filter_replace.old_filter_type =
7248 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7249 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7250 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7251 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7252 /* Prepare the buffer, 2 entries */
7253 filter_replace_buf.data[0] =
7254 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7255 filter_replace_buf.data[0] |=
7256 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7257 filter_replace_buf.data[2] = 0xFF;
7258 filter_replace_buf.data[3] = 0xFF;
7259 filter_replace_buf.data[4] =
7260 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7261 filter_replace_buf.data[4] |=
7262 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7263 filter_replace_buf.data[6] = 0xFF;
7264 filter_replace_buf.data[7] = 0xFF;
7265 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7266 &filter_replace_buf);
7271 memset(&filter_replace, 0,
7272 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7273 memset(&filter_replace_buf, 0,
7274 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7275 /* create L1 filter */
7276 filter_replace.old_filter_type =
7277 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7278 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7279 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7280 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7281 /* Prepare the buffer, 2 entries */
7282 filter_replace_buf.data[0] =
7283 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7284 filter_replace_buf.data[0] |=
7285 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7286 filter_replace_buf.data[2] = 0xFF;
7287 filter_replace_buf.data[3] = 0xFF;
7288 filter_replace_buf.data[4] =
7289 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7290 filter_replace_buf.data[4] |=
7291 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7292 filter_replace_buf.data[6] = 0xFF;
7293 filter_replace_buf.data[7] = 0xFF;
7295 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7296 &filter_replace_buf);
7301 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7303 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7304 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7305 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7306 enum i40e_status_code status = I40E_SUCCESS;
7309 memset(&filter_replace, 0,
7310 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7311 memset(&filter_replace_buf, 0,
7312 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7313 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7314 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7315 filter_replace.new_filter_type =
7316 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7317 /* Prepare the buffer, 2 entries */
7318 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7319 filter_replace_buf.data[0] |=
7320 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7321 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7322 filter_replace_buf.data[4] |=
7323 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7324 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7325 &filter_replace_buf);
7330 memset(&filter_replace, 0,
7331 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7332 memset(&filter_replace_buf, 0,
7333 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7334 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7335 filter_replace.old_filter_type =
7336 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7337 filter_replace.new_filter_type =
7338 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7339 /* Prepare the buffer, 2 entries */
7340 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7341 filter_replace_buf.data[0] |=
7342 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7343 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7344 filter_replace_buf.data[4] |=
7345 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7347 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7348 &filter_replace_buf);
7353 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7354 struct i40e_tunnel_filter_conf *tunnel_filter,
7358 uint32_t ipv4_addr, ipv4_addr_le;
7359 uint8_t i, tun_type = 0;
7360 /* internal variable to convert ipv6 byte order */
7361 uint32_t convert_ipv6[4];
7363 struct i40e_pf_vf *vf = NULL;
7364 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7365 struct i40e_vsi *vsi;
7366 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7367 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7368 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7369 struct i40e_tunnel_filter *tunnel, *node;
7370 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7372 bool big_buffer = 0;
7374 cld_filter = rte_zmalloc("tunnel_filter",
7375 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7378 if (cld_filter == NULL) {
7379 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7382 pfilter = cld_filter;
7384 ether_addr_copy(&tunnel_filter->outer_mac,
7385 (struct ether_addr *)&pfilter->element.outer_mac);
7386 ether_addr_copy(&tunnel_filter->inner_mac,
7387 (struct ether_addr *)&pfilter->element.inner_mac);
7389 pfilter->element.inner_vlan =
7390 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7391 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7392 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7393 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7394 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7395 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7397 sizeof(pfilter->element.ipaddr.v4.data));
7399 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7400 for (i = 0; i < 4; i++) {
7402 rte_cpu_to_le_32(rte_be_to_cpu_32(
7403 tunnel_filter->ip_addr.ipv6_addr[i]));
7405 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7407 sizeof(pfilter->element.ipaddr.v6.data));
7410 /* check tunneled type */
7411 switch (tunnel_filter->tunnel_type) {
7412 case I40E_TUNNEL_TYPE_VXLAN:
7413 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7415 case I40E_TUNNEL_TYPE_NVGRE:
7416 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7418 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7419 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7421 case I40E_TUNNEL_TYPE_MPLSoUDP:
7422 if (!pf->mpls_replace_flag) {
7423 i40e_replace_mpls_l1_filter(pf);
7424 i40e_replace_mpls_cloud_filter(pf);
7425 pf->mpls_replace_flag = 1;
7427 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7428 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7430 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7431 (teid_le & 0xF) << 12;
7432 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7435 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7437 case I40E_TUNNEL_TYPE_MPLSoGRE:
7438 if (!pf->mpls_replace_flag) {
7439 i40e_replace_mpls_l1_filter(pf);
7440 i40e_replace_mpls_cloud_filter(pf);
7441 pf->mpls_replace_flag = 1;
7443 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7444 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7446 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7447 (teid_le & 0xF) << 12;
7448 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7451 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7453 case I40E_TUNNEL_TYPE_GTPC:
7454 if (!pf->gtp_replace_flag) {
7455 i40e_replace_gtp_l1_filter(pf);
7456 i40e_replace_gtp_cloud_filter(pf);
7457 pf->gtp_replace_flag = 1;
7459 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7460 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7461 (teid_le >> 16) & 0xFFFF;
7462 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7464 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7468 case I40E_TUNNEL_TYPE_GTPU:
7469 if (!pf->gtp_replace_flag) {
7470 i40e_replace_gtp_l1_filter(pf);
7471 i40e_replace_gtp_cloud_filter(pf);
7472 pf->gtp_replace_flag = 1;
7474 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7475 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7476 (teid_le >> 16) & 0xFFFF;
7477 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7479 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7483 case I40E_TUNNEL_TYPE_QINQ:
7484 if (!pf->qinq_replace_flag) {
7485 ret = i40e_cloud_filter_qinq_create(pf);
7488 "QinQ tunnel filter already created.");
7489 pf->qinq_replace_flag = 1;
7491 /* Add in the General fields the values of
7492 * the Outer and Inner VLAN
7493 * Big Buffer should be set, see changes in
7494 * i40e_aq_add_cloud_filters
7496 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7497 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7501 /* Other tunnel types is not supported. */
7502 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7503 rte_free(cld_filter);
7507 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7508 pfilter->element.flags =
7509 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7510 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7511 pfilter->element.flags =
7512 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7513 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7514 pfilter->element.flags =
7515 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7516 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7517 pfilter->element.flags =
7518 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7519 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7520 pfilter->element.flags |=
7521 I40E_AQC_ADD_CLOUD_FILTER_0X10;
7523 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7524 &pfilter->element.flags);
7526 rte_free(cld_filter);
7531 pfilter->element.flags |= rte_cpu_to_le_16(
7532 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7533 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7534 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7535 pfilter->element.queue_number =
7536 rte_cpu_to_le_16(tunnel_filter->queue_id);
7538 if (!tunnel_filter->is_to_vf)
7541 if (tunnel_filter->vf_id >= pf->vf_num) {
7542 PMD_DRV_LOG(ERR, "Invalid argument.");
7545 vf = &pf->vfs[tunnel_filter->vf_id];
7549 /* Check if there is the filter in SW list */
7550 memset(&check_filter, 0, sizeof(check_filter));
7551 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7552 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7553 check_filter.vf_id = tunnel_filter->vf_id;
7554 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7556 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7560 if (!add && !node) {
7561 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7567 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7568 vsi->seid, cld_filter, 1);
7570 ret = i40e_aq_add_cloud_filters(hw,
7571 vsi->seid, &cld_filter->element, 1);
7573 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7576 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7577 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7578 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7581 ret = i40e_aq_remove_cloud_filters_big_buffer(
7582 hw, vsi->seid, cld_filter, 1);
7584 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7585 &cld_filter->element, 1);
7587 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7590 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7593 rte_free(cld_filter);
7598 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7602 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7603 if (pf->vxlan_ports[i] == port)
7611 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7615 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7617 idx = i40e_get_vxlan_port_idx(pf, port);
7619 /* Check if port already exists */
7621 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7625 /* Now check if there is space to add the new port */
7626 idx = i40e_get_vxlan_port_idx(pf, 0);
7629 "Maximum number of UDP ports reached, not adding port %d",
7634 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7637 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7641 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7644 /* New port: add it and mark its index in the bitmap */
7645 pf->vxlan_ports[idx] = port;
7646 pf->vxlan_bitmap |= (1 << idx);
7648 if (!(pf->flags & I40E_FLAG_VXLAN))
7649 pf->flags |= I40E_FLAG_VXLAN;
7655 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7658 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7660 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7661 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7665 idx = i40e_get_vxlan_port_idx(pf, port);
7668 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7672 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7673 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7677 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7680 pf->vxlan_ports[idx] = 0;
7681 pf->vxlan_bitmap &= ~(1 << idx);
7683 if (!pf->vxlan_bitmap)
7684 pf->flags &= ~I40E_FLAG_VXLAN;
7689 /* Add UDP tunneling port */
7691 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7692 struct rte_eth_udp_tunnel *udp_tunnel)
7695 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7697 if (udp_tunnel == NULL)
7700 switch (udp_tunnel->prot_type) {
7701 case RTE_TUNNEL_TYPE_VXLAN:
7702 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7705 case RTE_TUNNEL_TYPE_GENEVE:
7706 case RTE_TUNNEL_TYPE_TEREDO:
7707 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7712 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7720 /* Remove UDP tunneling port */
7722 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7723 struct rte_eth_udp_tunnel *udp_tunnel)
7726 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7728 if (udp_tunnel == NULL)
7731 switch (udp_tunnel->prot_type) {
7732 case RTE_TUNNEL_TYPE_VXLAN:
7733 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7735 case RTE_TUNNEL_TYPE_GENEVE:
7736 case RTE_TUNNEL_TYPE_TEREDO:
7737 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7741 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7749 /* Calculate the maximum number of contiguous PF queues that are configured */
7751 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7753 struct rte_eth_dev_data *data = pf->dev_data;
7755 struct i40e_rx_queue *rxq;
7758 for (i = 0; i < pf->lan_nb_qps; i++) {
7759 rxq = data->rx_queues[i];
7760 if (rxq && rxq->q_set)
7771 i40e_pf_config_rss(struct i40e_pf *pf)
7773 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7774 struct rte_eth_rss_conf rss_conf;
7775 uint32_t i, lut = 0;
7779 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7780 * It's necessary to calculate the actual PF queues that are configured.
7782 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7783 num = i40e_pf_calc_configured_queues_num(pf);
7785 num = pf->dev_data->nb_rx_queues;
7787 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7788 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7792 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7796 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7799 lut = (lut << 8) | (j & ((0x1 <<
7800 hw->func_caps.rss_table_entry_width) - 1));
7802 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7805 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7806 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7807 i40e_pf_disable_rss(pf);
7810 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7811 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7812 /* Random default keys */
7813 static uint32_t rss_key_default[] = {0x6b793944,
7814 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7815 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7816 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7818 rss_conf.rss_key = (uint8_t *)rss_key_default;
7819 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7823 return i40e_hw_rss_hash_set(pf, &rss_conf);
7827 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7828 struct rte_eth_tunnel_filter_conf *filter)
7830 if (pf == NULL || filter == NULL) {
7831 PMD_DRV_LOG(ERR, "Invalid parameter");
7835 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7836 PMD_DRV_LOG(ERR, "Invalid queue ID");
7840 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7841 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7845 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7846 (is_zero_ether_addr(&filter->outer_mac))) {
7847 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7851 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7852 (is_zero_ether_addr(&filter->inner_mac))) {
7853 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7860 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7861 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7863 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7868 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7869 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7872 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7873 } else if (len == 4) {
7874 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7876 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7881 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7888 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7889 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7895 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7902 switch (cfg->cfg_type) {
7903 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7904 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7907 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7915 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7916 enum rte_filter_op filter_op,
7919 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7920 int ret = I40E_ERR_PARAM;
7922 switch (filter_op) {
7923 case RTE_ETH_FILTER_SET:
7924 ret = i40e_dev_global_config_set(hw,
7925 (struct rte_eth_global_cfg *)arg);
7928 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7936 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7937 enum rte_filter_op filter_op,
7940 struct rte_eth_tunnel_filter_conf *filter;
7941 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7942 int ret = I40E_SUCCESS;
7944 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7946 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7947 return I40E_ERR_PARAM;
7949 switch (filter_op) {
7950 case RTE_ETH_FILTER_NOP:
7951 if (!(pf->flags & I40E_FLAG_VXLAN))
7952 ret = I40E_NOT_SUPPORTED;
7954 case RTE_ETH_FILTER_ADD:
7955 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7957 case RTE_ETH_FILTER_DELETE:
7958 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7961 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7962 ret = I40E_ERR_PARAM;
7970 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7973 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7976 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7977 ret = i40e_pf_config_rss(pf);
7979 i40e_pf_disable_rss(pf);
7984 /* Get the symmetric hash enable configurations per port */
7986 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7988 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7990 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7993 /* Set the symmetric hash enable configurations per port */
7995 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7997 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8000 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8002 "Symmetric hash has already been enabled");
8005 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8007 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8009 "Symmetric hash has already been disabled");
8012 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8014 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8015 I40E_WRITE_FLUSH(hw);
8019 * Get global configurations of hash function type and symmetric hash enable
8020 * per flow type (pctype). Note that global configuration means it affects all
8021 * the ports on the same NIC.
8024 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8025 struct rte_eth_hash_global_conf *g_cfg)
8027 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8031 memset(g_cfg, 0, sizeof(*g_cfg));
8032 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8033 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8034 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8036 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8037 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8038 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8041 * We work only with lowest 32 bits which is not correct, but to work
8042 * properly the valid_bit_mask size should be increased up to 64 bits
8043 * and this will brake ABI. This modification will be done in next
8046 g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
8048 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
8049 if (!adapter->pctypes_tbl[i])
8051 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8052 j < I40E_FILTER_PCTYPE_MAX; j++) {
8053 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8054 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8055 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8056 g_cfg->sym_hash_enable_mask[0] |=
8067 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8068 const struct rte_eth_hash_global_conf *g_cfg)
8071 uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8073 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8074 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8075 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8076 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8082 * As i40e supports less than 32 flow types, only first 32 bits need to
8085 mask0 = g_cfg->valid_bit_mask[0];
8086 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8088 /* Check if any unsupported flow type configured */
8089 if ((mask0 | i40e_mask) ^ i40e_mask)
8092 if (g_cfg->valid_bit_mask[i])
8100 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8106 * Set global configurations of hash function type and symmetric hash enable
8107 * per flow type (pctype). Note any modifying global configuration will affect
8108 * all the ports on the same NIC.
8111 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8112 struct rte_eth_hash_global_conf *g_cfg)
8114 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8119 * We work only with lowest 32 bits which is not correct, but to work
8120 * properly the valid_bit_mask size should be increased up to 64 bits
8121 * and this will brake ABI. This modification will be done in next
8124 uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8125 (uint32_t)adapter->flow_types_mask;
8127 /* Check the input parameters */
8128 ret = i40e_hash_global_config_check(adapter, g_cfg);
8132 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8133 if (mask0 & (1UL << i)) {
8134 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8135 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8137 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8138 j < I40E_FILTER_PCTYPE_MAX; j++) {
8139 if (adapter->pctypes_tbl[i] & (1ULL << j))
8140 i40e_write_rx_ctl(hw,
8147 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8148 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8150 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8152 "Hash function already set to Toeplitz");
8155 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8156 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8158 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8160 "Hash function already set to Simple XOR");
8163 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8165 /* Use the default, and keep it as it is */
8168 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8171 I40E_WRITE_FLUSH(hw);
8177 * Valid input sets for hash and flow director filters per PCTYPE
8180 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8181 enum rte_filter_type filter)
8185 static const uint64_t valid_hash_inset_table[] = {
8186 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8187 I40E_INSET_DMAC | I40E_INSET_SMAC |
8188 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8189 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8190 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8191 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8192 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8193 I40E_INSET_FLEX_PAYLOAD,
8194 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8195 I40E_INSET_DMAC | I40E_INSET_SMAC |
8196 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8197 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8198 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8199 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8200 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8201 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8202 I40E_INSET_FLEX_PAYLOAD,
8203 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8204 I40E_INSET_DMAC | I40E_INSET_SMAC |
8205 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8206 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8207 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8208 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8209 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8210 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8211 I40E_INSET_FLEX_PAYLOAD,
8212 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8213 I40E_INSET_DMAC | I40E_INSET_SMAC |
8214 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8215 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8216 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8217 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8218 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8219 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8220 I40E_INSET_FLEX_PAYLOAD,
8221 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8222 I40E_INSET_DMAC | I40E_INSET_SMAC |
8223 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8224 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8225 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8226 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8227 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8228 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8229 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8230 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8231 I40E_INSET_DMAC | I40E_INSET_SMAC |
8232 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8233 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8234 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8235 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8236 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8237 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8238 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8239 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8240 I40E_INSET_DMAC | I40E_INSET_SMAC |
8241 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8242 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8243 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8244 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8245 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8246 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8247 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8248 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8249 I40E_INSET_DMAC | I40E_INSET_SMAC |
8250 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8251 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8252 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8253 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8254 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8255 I40E_INSET_FLEX_PAYLOAD,
8256 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8257 I40E_INSET_DMAC | I40E_INSET_SMAC |
8258 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8259 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8260 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8261 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8262 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8263 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8264 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8265 I40E_INSET_DMAC | I40E_INSET_SMAC |
8266 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8267 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8268 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8269 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8270 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8271 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8272 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8273 I40E_INSET_DMAC | I40E_INSET_SMAC |
8274 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8275 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8276 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8277 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8278 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8279 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8280 I40E_INSET_FLEX_PAYLOAD,
8281 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8282 I40E_INSET_DMAC | I40E_INSET_SMAC |
8283 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8284 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8285 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8286 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8287 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8288 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8289 I40E_INSET_FLEX_PAYLOAD,
8290 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8291 I40E_INSET_DMAC | I40E_INSET_SMAC |
8292 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8293 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8294 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8295 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8296 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8297 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8298 I40E_INSET_FLEX_PAYLOAD,
8299 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8300 I40E_INSET_DMAC | I40E_INSET_SMAC |
8301 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8302 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8303 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8304 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8305 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8306 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8307 I40E_INSET_FLEX_PAYLOAD,
8308 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8309 I40E_INSET_DMAC | I40E_INSET_SMAC |
8310 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8311 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8312 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8313 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8314 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8315 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8316 I40E_INSET_FLEX_PAYLOAD,
8317 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8318 I40E_INSET_DMAC | I40E_INSET_SMAC |
8319 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8320 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8321 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8322 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8323 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8324 I40E_INSET_FLEX_PAYLOAD,
8325 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8326 I40E_INSET_DMAC | I40E_INSET_SMAC |
8327 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8328 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8329 I40E_INSET_FLEX_PAYLOAD,
8333 * Flow director supports only fields defined in
8334 * union rte_eth_fdir_flow.
8336 static const uint64_t valid_fdir_inset_table[] = {
8337 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8338 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8339 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8340 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8341 I40E_INSET_IPV4_TTL,
8342 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8343 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8344 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8345 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8346 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8347 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8348 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8349 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8350 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8351 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8352 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8353 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8354 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8355 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8356 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8357 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8358 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8359 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8360 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8361 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8362 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8363 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8364 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8365 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8366 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8367 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8368 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8369 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8370 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8371 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8373 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8374 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8375 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8376 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8377 I40E_INSET_IPV4_TTL,
8378 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8379 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8380 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8381 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8382 I40E_INSET_IPV6_HOP_LIMIT,
8383 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8384 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8385 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8386 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8387 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8388 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8389 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8390 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8391 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8392 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8393 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8394 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8395 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8396 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8397 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8398 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8399 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8400 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8401 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8402 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8403 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8404 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8405 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8406 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8407 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8408 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8409 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8410 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8411 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8412 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8414 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8415 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8416 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8417 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8418 I40E_INSET_IPV6_HOP_LIMIT,
8419 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8420 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8421 I40E_INSET_LAST_ETHER_TYPE,
8424 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8426 if (filter == RTE_ETH_FILTER_HASH)
8427 valid = valid_hash_inset_table[pctype];
8429 valid = valid_fdir_inset_table[pctype];
8435 * Validate if the input set is allowed for a specific PCTYPE
8438 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8439 enum rte_filter_type filter, uint64_t inset)
8443 valid = i40e_get_valid_input_set(pctype, filter);
8444 if (inset & (~valid))
8450 /* default input set fields combination per pctype */
8452 i40e_get_default_input_set(uint16_t pctype)
8454 static const uint64_t default_inset_table[] = {
8455 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8456 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8457 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8458 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8459 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8460 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8461 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8462 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8463 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8464 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8465 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8466 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8467 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8468 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8469 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8470 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8471 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8472 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8473 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8474 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8476 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8477 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8478 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8479 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8480 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8481 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8482 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8483 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8484 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8485 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8486 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8487 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8488 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8489 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8490 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8491 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8492 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8493 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8494 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8495 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8496 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8497 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8499 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8500 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8501 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8502 I40E_INSET_LAST_ETHER_TYPE,
8505 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8508 return default_inset_table[pctype];
8512 * Parse the input set from index to logical bit masks
8515 i40e_parse_input_set(uint64_t *inset,
8516 enum i40e_filter_pctype pctype,
8517 enum rte_eth_input_set_field *field,
8523 static const struct {
8524 enum rte_eth_input_set_field field;
8526 } inset_convert_table[] = {
8527 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8528 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8529 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8530 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8531 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8532 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8533 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8534 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8535 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8536 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8537 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8538 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8539 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8540 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8541 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8542 I40E_INSET_IPV6_NEXT_HDR},
8543 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8544 I40E_INSET_IPV6_HOP_LIMIT},
8545 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8546 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8547 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8548 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8549 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8550 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8551 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8552 I40E_INSET_SCTP_VT},
8553 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8554 I40E_INSET_TUNNEL_DMAC},
8555 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8556 I40E_INSET_VLAN_TUNNEL},
8557 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8558 I40E_INSET_TUNNEL_ID},
8559 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8560 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8561 I40E_INSET_FLEX_PAYLOAD_W1},
8562 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8563 I40E_INSET_FLEX_PAYLOAD_W2},
8564 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8565 I40E_INSET_FLEX_PAYLOAD_W3},
8566 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8567 I40E_INSET_FLEX_PAYLOAD_W4},
8568 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8569 I40E_INSET_FLEX_PAYLOAD_W5},
8570 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8571 I40E_INSET_FLEX_PAYLOAD_W6},
8572 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8573 I40E_INSET_FLEX_PAYLOAD_W7},
8574 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8575 I40E_INSET_FLEX_PAYLOAD_W8},
8578 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8581 /* Only one item allowed for default or all */
8583 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8584 *inset = i40e_get_default_input_set(pctype);
8586 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8587 *inset = I40E_INSET_NONE;
8592 for (i = 0, *inset = 0; i < size; i++) {
8593 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8594 if (field[i] == inset_convert_table[j].field) {
8595 *inset |= inset_convert_table[j].inset;
8600 /* It contains unsupported input set, return immediately */
8601 if (j == RTE_DIM(inset_convert_table))
8609 * Translate the input set from bit masks to register aware bit masks
8613 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8623 static const struct inset_map inset_map_common[] = {
8624 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8625 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8626 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8627 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8628 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8629 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8630 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8631 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8632 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8633 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8634 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8635 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8636 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8637 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8638 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8639 {I40E_INSET_TUNNEL_DMAC,
8640 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8641 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8642 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8643 {I40E_INSET_TUNNEL_SRC_PORT,
8644 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8645 {I40E_INSET_TUNNEL_DST_PORT,
8646 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8647 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8648 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8649 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8650 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8651 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8652 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8653 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8654 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8655 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8658 /* some different registers map in x722*/
8659 static const struct inset_map inset_map_diff_x722[] = {
8660 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8661 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8662 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8663 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8666 static const struct inset_map inset_map_diff_not_x722[] = {
8667 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8668 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8669 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8670 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8676 /* Translate input set to register aware inset */
8677 if (type == I40E_MAC_X722) {
8678 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8679 if (input & inset_map_diff_x722[i].inset)
8680 val |= inset_map_diff_x722[i].inset_reg;
8683 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8684 if (input & inset_map_diff_not_x722[i].inset)
8685 val |= inset_map_diff_not_x722[i].inset_reg;
8689 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8690 if (input & inset_map_common[i].inset)
8691 val |= inset_map_common[i].inset_reg;
8698 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8701 uint64_t inset_need_mask = inset;
8703 static const struct {
8706 } inset_mask_map[] = {
8707 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8708 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8709 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8710 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8711 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8712 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8713 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8714 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8717 if (!inset || !mask || !nb_elem)
8720 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8721 /* Clear the inset bit, if no MASK is required,
8722 * for example proto + ttl
8724 if ((inset & inset_mask_map[i].inset) ==
8725 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8726 inset_need_mask &= ~inset_mask_map[i].inset;
8727 if (!inset_need_mask)
8730 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8731 if ((inset_need_mask & inset_mask_map[i].inset) ==
8732 inset_mask_map[i].inset) {
8733 if (idx >= nb_elem) {
8734 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8737 mask[idx] = inset_mask_map[i].mask;
8746 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8748 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8750 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8752 i40e_write_rx_ctl(hw, addr, val);
8753 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8754 (uint32_t)i40e_read_rx_ctl(hw, addr));
8758 i40e_filter_input_set_init(struct i40e_pf *pf)
8760 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8761 enum i40e_filter_pctype pctype;
8762 uint64_t input_set, inset_reg;
8763 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8767 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8768 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8769 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8771 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8774 input_set = i40e_get_default_input_set(pctype);
8776 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8777 I40E_INSET_MASK_NUM_REG);
8780 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8783 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8784 (uint32_t)(inset_reg & UINT32_MAX));
8785 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8786 (uint32_t)((inset_reg >>
8787 I40E_32_BIT_WIDTH) & UINT32_MAX));
8788 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8789 (uint32_t)(inset_reg & UINT32_MAX));
8790 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8791 (uint32_t)((inset_reg >>
8792 I40E_32_BIT_WIDTH) & UINT32_MAX));
8794 for (i = 0; i < num; i++) {
8795 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8797 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8800 /*clear unused mask registers of the pctype */
8801 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8802 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8804 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8807 I40E_WRITE_FLUSH(hw);
8809 /* store the default input set */
8810 pf->hash_input_set[pctype] = input_set;
8811 pf->fdir.input_set[pctype] = input_set;
8816 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8817 struct rte_eth_input_set_conf *conf)
8819 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8820 enum i40e_filter_pctype pctype;
8821 uint64_t input_set, inset_reg = 0;
8822 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8826 PMD_DRV_LOG(ERR, "Invalid pointer");
8829 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8830 conf->op != RTE_ETH_INPUT_SET_ADD) {
8831 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8835 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8836 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8837 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8841 if (hw->mac.type == I40E_MAC_X722) {
8842 /* get translated pctype value in fd pctype register */
8843 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8844 I40E_GLQF_FD_PCTYPES((int)pctype));
8847 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8850 PMD_DRV_LOG(ERR, "Failed to parse input set");
8854 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8855 /* get inset value in register */
8856 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8857 inset_reg <<= I40E_32_BIT_WIDTH;
8858 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8859 input_set |= pf->hash_input_set[pctype];
8861 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8862 I40E_INSET_MASK_NUM_REG);
8866 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8868 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8869 (uint32_t)(inset_reg & UINT32_MAX));
8870 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8871 (uint32_t)((inset_reg >>
8872 I40E_32_BIT_WIDTH) & UINT32_MAX));
8874 for (i = 0; i < num; i++)
8875 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8877 /*clear unused mask registers of the pctype */
8878 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8879 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8881 I40E_WRITE_FLUSH(hw);
8883 pf->hash_input_set[pctype] = input_set;
8888 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8889 struct rte_eth_input_set_conf *conf)
8891 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8892 enum i40e_filter_pctype pctype;
8893 uint64_t input_set, inset_reg = 0;
8894 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8898 PMD_DRV_LOG(ERR, "Invalid pointer");
8901 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8902 conf->op != RTE_ETH_INPUT_SET_ADD) {
8903 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8907 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8909 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8910 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8914 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8917 PMD_DRV_LOG(ERR, "Failed to parse input set");
8921 /* get inset value in register */
8922 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8923 inset_reg <<= I40E_32_BIT_WIDTH;
8924 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8926 /* Can not change the inset reg for flex payload for fdir,
8927 * it is done by writing I40E_PRTQF_FD_FLXINSET
8928 * in i40e_set_flex_mask_on_pctype.
8930 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8931 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8933 input_set |= pf->fdir.input_set[pctype];
8934 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8935 I40E_INSET_MASK_NUM_REG);
8939 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8941 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8942 (uint32_t)(inset_reg & UINT32_MAX));
8943 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8944 (uint32_t)((inset_reg >>
8945 I40E_32_BIT_WIDTH) & UINT32_MAX));
8947 for (i = 0; i < num; i++)
8948 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8950 /*clear unused mask registers of the pctype */
8951 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8952 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8954 I40E_WRITE_FLUSH(hw);
8956 pf->fdir.input_set[pctype] = input_set;
8961 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8966 PMD_DRV_LOG(ERR, "Invalid pointer");
8970 switch (info->info_type) {
8971 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8972 i40e_get_symmetric_hash_enable_per_port(hw,
8973 &(info->info.enable));
8975 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8976 ret = i40e_get_hash_filter_global_config(hw,
8977 &(info->info.global_conf));
8980 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8990 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8995 PMD_DRV_LOG(ERR, "Invalid pointer");
8999 switch (info->info_type) {
9000 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9001 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9003 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9004 ret = i40e_set_hash_filter_global_config(hw,
9005 &(info->info.global_conf));
9007 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9008 ret = i40e_hash_filter_inset_select(hw,
9009 &(info->info.input_set_conf));
9013 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9022 /* Operations for hash function */
9024 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9025 enum rte_filter_op filter_op,
9028 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9031 switch (filter_op) {
9032 case RTE_ETH_FILTER_NOP:
9034 case RTE_ETH_FILTER_GET:
9035 ret = i40e_hash_filter_get(hw,
9036 (struct rte_eth_hash_filter_info *)arg);
9038 case RTE_ETH_FILTER_SET:
9039 ret = i40e_hash_filter_set(hw,
9040 (struct rte_eth_hash_filter_info *)arg);
9043 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9052 /* Convert ethertype filter structure */
9054 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9055 struct i40e_ethertype_filter *filter)
9057 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9058 filter->input.ether_type = input->ether_type;
9059 filter->flags = input->flags;
9060 filter->queue = input->queue;
9065 /* Check if there exists the ehtertype filter */
9066 struct i40e_ethertype_filter *
9067 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9068 const struct i40e_ethertype_filter_input *input)
9072 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9076 return ethertype_rule->hash_map[ret];
9079 /* Add ethertype filter in SW list */
9081 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9082 struct i40e_ethertype_filter *filter)
9084 struct i40e_ethertype_rule *rule = &pf->ethertype;
9087 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9090 "Failed to insert ethertype filter"
9091 " to hash table %d!",
9095 rule->hash_map[ret] = filter;
9097 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9102 /* Delete ethertype filter in SW list */
9104 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9105 struct i40e_ethertype_filter_input *input)
9107 struct i40e_ethertype_rule *rule = &pf->ethertype;
9108 struct i40e_ethertype_filter *filter;
9111 ret = rte_hash_del_key(rule->hash_table, input);
9114 "Failed to delete ethertype filter"
9115 " to hash table %d!",
9119 filter = rule->hash_map[ret];
9120 rule->hash_map[ret] = NULL;
9122 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9129 * Configure ethertype filter, which can director packet by filtering
9130 * with mac address and ether_type or only ether_type
9133 i40e_ethertype_filter_set(struct i40e_pf *pf,
9134 struct rte_eth_ethertype_filter *filter,
9137 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9138 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9139 struct i40e_ethertype_filter *ethertype_filter, *node;
9140 struct i40e_ethertype_filter check_filter;
9141 struct i40e_control_filter_stats stats;
9145 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9146 PMD_DRV_LOG(ERR, "Invalid queue ID");
9149 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9150 filter->ether_type == ETHER_TYPE_IPv6) {
9152 "unsupported ether_type(0x%04x) in control packet filter.",
9153 filter->ether_type);
9156 if (filter->ether_type == ETHER_TYPE_VLAN)
9157 PMD_DRV_LOG(WARNING,
9158 "filter vlan ether_type in first tag is not supported.");
9160 /* Check if there is the filter in SW list */
9161 memset(&check_filter, 0, sizeof(check_filter));
9162 i40e_ethertype_filter_convert(filter, &check_filter);
9163 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9164 &check_filter.input);
9166 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9170 if (!add && !node) {
9171 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9175 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9176 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9177 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9178 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9179 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9181 memset(&stats, 0, sizeof(stats));
9182 ret = i40e_aq_add_rem_control_packet_filter(hw,
9183 filter->mac_addr.addr_bytes,
9184 filter->ether_type, flags,
9186 filter->queue, add, &stats, NULL);
9189 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9190 ret, stats.mac_etype_used, stats.etype_used,
9191 stats.mac_etype_free, stats.etype_free);
9195 /* Add or delete a filter in SW list */
9197 ethertype_filter = rte_zmalloc("ethertype_filter",
9198 sizeof(*ethertype_filter), 0);
9199 rte_memcpy(ethertype_filter, &check_filter,
9200 sizeof(check_filter));
9201 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9203 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9210 * Handle operations for ethertype filter.
9213 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9214 enum rte_filter_op filter_op,
9217 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9220 if (filter_op == RTE_ETH_FILTER_NOP)
9224 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9229 switch (filter_op) {
9230 case RTE_ETH_FILTER_ADD:
9231 ret = i40e_ethertype_filter_set(pf,
9232 (struct rte_eth_ethertype_filter *)arg,
9235 case RTE_ETH_FILTER_DELETE:
9236 ret = i40e_ethertype_filter_set(pf,
9237 (struct rte_eth_ethertype_filter *)arg,
9241 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9249 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9250 enum rte_filter_type filter_type,
9251 enum rte_filter_op filter_op,
9259 switch (filter_type) {
9260 case RTE_ETH_FILTER_NONE:
9261 /* For global configuration */
9262 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9264 case RTE_ETH_FILTER_HASH:
9265 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9267 case RTE_ETH_FILTER_MACVLAN:
9268 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9270 case RTE_ETH_FILTER_ETHERTYPE:
9271 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9273 case RTE_ETH_FILTER_TUNNEL:
9274 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9276 case RTE_ETH_FILTER_FDIR:
9277 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9279 case RTE_ETH_FILTER_GENERIC:
9280 if (filter_op != RTE_ETH_FILTER_GET)
9282 *(const void **)arg = &i40e_flow_ops;
9285 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9295 * Check and enable Extended Tag.
9296 * Enabling Extended Tag is important for 40G performance.
9299 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9301 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9305 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9308 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9312 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9313 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9318 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9321 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9325 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9326 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9329 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9330 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9333 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9340 * As some registers wouldn't be reset unless a global hardware reset,
9341 * hardware initialization is needed to put those registers into an
9342 * expected initial state.
9345 i40e_hw_init(struct rte_eth_dev *dev)
9347 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9349 i40e_enable_extended_tag(dev);
9351 /* clear the PF Queue Filter control register */
9352 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9354 /* Disable symmetric hash per port */
9355 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9359 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9360 * however this function will return only one highest pctype index,
9361 * which is not quite correct. This is known problem of i40e driver
9362 * and needs to be fixed later.
9364 enum i40e_filter_pctype
9365 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9368 uint64_t pctype_mask;
9370 if (flow_type < I40E_FLOW_TYPE_MAX) {
9371 pctype_mask = adapter->pctypes_tbl[flow_type];
9372 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9373 if (pctype_mask & (1ULL << i))
9374 return (enum i40e_filter_pctype)i;
9377 return I40E_FILTER_PCTYPE_INVALID;
9381 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9382 enum i40e_filter_pctype pctype)
9385 uint64_t pctype_mask = 1ULL << pctype;
9387 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9389 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9393 return RTE_ETH_FLOW_UNKNOWN;
9397 * On X710, performance number is far from the expectation on recent firmware
9398 * versions; on XL710, performance number is also far from the expectation on
9399 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9400 * mode is enabled and port MAC address is equal to the packet destination MAC
9401 * address. The fix for this issue may not be integrated in the following
9402 * firmware version. So the workaround in software driver is needed. It needs
9403 * to modify the initial values of 3 internal only registers for both X710 and
9404 * XL710. Note that the values for X710 or XL710 could be different, and the
9405 * workaround can be removed when it is fixed in firmware in the future.
9408 /* For both X710 and XL710 */
9409 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9410 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
9411 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9413 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9414 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9417 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9418 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9421 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9423 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9424 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9427 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9429 enum i40e_status_code status;
9430 struct i40e_aq_get_phy_abilities_resp phy_ab;
9434 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9438 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9441 rte_delay_us(100000);
9443 status = i40e_aq_get_phy_capabilities(hw, false,
9444 true, &phy_ab, NULL);
9452 i40e_configure_registers(struct i40e_hw *hw)
9458 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9459 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9460 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9466 for (i = 0; i < RTE_DIM(reg_table); i++) {
9467 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9468 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9470 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9471 else /* For X710/XL710/XXV710 */
9472 if (hw->aq.fw_maj_ver < 6)
9474 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9477 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9480 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9481 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9483 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9484 else /* For X710/XL710/XXV710 */
9486 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9489 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9490 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9491 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9493 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9496 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9499 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9502 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9506 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9507 reg_table[i].addr, reg);
9508 if (reg == reg_table[i].val)
9511 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9512 reg_table[i].val, NULL);
9515 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9516 reg_table[i].val, reg_table[i].addr);
9519 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9520 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9524 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9525 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9526 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9527 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9529 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9534 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9535 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9539 /* Configure for double VLAN RX stripping */
9540 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9541 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9542 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9543 ret = i40e_aq_debug_write_register(hw,
9544 I40E_VSI_TSR(vsi->vsi_id),
9547 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9549 return I40E_ERR_CONFIG;
9553 /* Configure for double VLAN TX insertion */
9554 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9555 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9556 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9557 ret = i40e_aq_debug_write_register(hw,
9558 I40E_VSI_L2TAGSTXVALID(
9559 vsi->vsi_id), reg, NULL);
9562 "Failed to update VSI_L2TAGSTXVALID[%d]",
9564 return I40E_ERR_CONFIG;
9572 * i40e_aq_add_mirror_rule
9573 * @hw: pointer to the hardware structure
9574 * @seid: VEB seid to add mirror rule to
9575 * @dst_id: destination vsi seid
9576 * @entries: Buffer which contains the entities to be mirrored
9577 * @count: number of entities contained in the buffer
9578 * @rule_id:the rule_id of the rule to be added
9580 * Add a mirror rule for a given veb.
9583 static enum i40e_status_code
9584 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9585 uint16_t seid, uint16_t dst_id,
9586 uint16_t rule_type, uint16_t *entries,
9587 uint16_t count, uint16_t *rule_id)
9589 struct i40e_aq_desc desc;
9590 struct i40e_aqc_add_delete_mirror_rule cmd;
9591 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9592 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9595 enum i40e_status_code status;
9597 i40e_fill_default_direct_cmd_desc(&desc,
9598 i40e_aqc_opc_add_mirror_rule);
9599 memset(&cmd, 0, sizeof(cmd));
9601 buff_len = sizeof(uint16_t) * count;
9602 desc.datalen = rte_cpu_to_le_16(buff_len);
9604 desc.flags |= rte_cpu_to_le_16(
9605 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9606 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9607 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9608 cmd.num_entries = rte_cpu_to_le_16(count);
9609 cmd.seid = rte_cpu_to_le_16(seid);
9610 cmd.destination = rte_cpu_to_le_16(dst_id);
9612 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9613 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9615 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9616 hw->aq.asq_last_status, resp->rule_id,
9617 resp->mirror_rules_used, resp->mirror_rules_free);
9618 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9624 * i40e_aq_del_mirror_rule
9625 * @hw: pointer to the hardware structure
9626 * @seid: VEB seid to add mirror rule to
9627 * @entries: Buffer which contains the entities to be mirrored
9628 * @count: number of entities contained in the buffer
9629 * @rule_id:the rule_id of the rule to be delete
9631 * Delete a mirror rule for a given veb.
9634 static enum i40e_status_code
9635 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9636 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9637 uint16_t count, uint16_t rule_id)
9639 struct i40e_aq_desc desc;
9640 struct i40e_aqc_add_delete_mirror_rule cmd;
9641 uint16_t buff_len = 0;
9642 enum i40e_status_code status;
9645 i40e_fill_default_direct_cmd_desc(&desc,
9646 i40e_aqc_opc_delete_mirror_rule);
9647 memset(&cmd, 0, sizeof(cmd));
9648 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9649 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9651 cmd.num_entries = count;
9652 buff_len = sizeof(uint16_t) * count;
9653 desc.datalen = rte_cpu_to_le_16(buff_len);
9654 buff = (void *)entries;
9656 /* rule id is filled in destination field for deleting mirror rule */
9657 cmd.destination = rte_cpu_to_le_16(rule_id);
9659 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9660 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9661 cmd.seid = rte_cpu_to_le_16(seid);
9663 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9664 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9670 * i40e_mirror_rule_set
9671 * @dev: pointer to the hardware structure
9672 * @mirror_conf: mirror rule info
9673 * @sw_id: mirror rule's sw_id
9674 * @on: enable/disable
9676 * set a mirror rule.
9680 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9681 struct rte_eth_mirror_conf *mirror_conf,
9682 uint8_t sw_id, uint8_t on)
9684 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9685 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9686 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9687 struct i40e_mirror_rule *parent = NULL;
9688 uint16_t seid, dst_seid, rule_id;
9692 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9694 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9696 "mirror rule can not be configured without veb or vfs.");
9699 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9700 PMD_DRV_LOG(ERR, "mirror table is full.");
9703 if (mirror_conf->dst_pool > pf->vf_num) {
9704 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9705 mirror_conf->dst_pool);
9709 seid = pf->main_vsi->veb->seid;
9711 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9712 if (sw_id <= it->index) {
9718 if (mirr_rule && sw_id == mirr_rule->index) {
9720 PMD_DRV_LOG(ERR, "mirror rule exists.");
9723 ret = i40e_aq_del_mirror_rule(hw, seid,
9724 mirr_rule->rule_type,
9726 mirr_rule->num_entries, mirr_rule->id);
9729 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9730 ret, hw->aq.asq_last_status);
9733 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9734 rte_free(mirr_rule);
9735 pf->nb_mirror_rule--;
9739 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9743 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9744 sizeof(struct i40e_mirror_rule) , 0);
9746 PMD_DRV_LOG(ERR, "failed to allocate memory");
9747 return I40E_ERR_NO_MEMORY;
9749 switch (mirror_conf->rule_type) {
9750 case ETH_MIRROR_VLAN:
9751 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9752 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9753 mirr_rule->entries[j] =
9754 mirror_conf->vlan.vlan_id[i];
9759 PMD_DRV_LOG(ERR, "vlan is not specified.");
9760 rte_free(mirr_rule);
9763 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9765 case ETH_MIRROR_VIRTUAL_POOL_UP:
9766 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9767 /* check if the specified pool bit is out of range */
9768 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9769 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9770 rte_free(mirr_rule);
9773 for (i = 0, j = 0; i < pf->vf_num; i++) {
9774 if (mirror_conf->pool_mask & (1ULL << i)) {
9775 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9779 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9780 /* add pf vsi to entries */
9781 mirr_rule->entries[j] = pf->main_vsi_seid;
9785 PMD_DRV_LOG(ERR, "pool is not specified.");
9786 rte_free(mirr_rule);
9789 /* egress and ingress in aq commands means from switch but not port */
9790 mirr_rule->rule_type =
9791 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9792 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9793 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9795 case ETH_MIRROR_UPLINK_PORT:
9796 /* egress and ingress in aq commands means from switch but not port*/
9797 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9799 case ETH_MIRROR_DOWNLINK_PORT:
9800 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9803 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9804 mirror_conf->rule_type);
9805 rte_free(mirr_rule);
9809 /* If the dst_pool is equal to vf_num, consider it as PF */
9810 if (mirror_conf->dst_pool == pf->vf_num)
9811 dst_seid = pf->main_vsi_seid;
9813 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9815 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9816 mirr_rule->rule_type, mirr_rule->entries,
9820 "failed to add mirror rule: ret = %d, aq_err = %d.",
9821 ret, hw->aq.asq_last_status);
9822 rte_free(mirr_rule);
9826 mirr_rule->index = sw_id;
9827 mirr_rule->num_entries = j;
9828 mirr_rule->id = rule_id;
9829 mirr_rule->dst_vsi_seid = dst_seid;
9832 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9834 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9836 pf->nb_mirror_rule++;
9841 * i40e_mirror_rule_reset
9842 * @dev: pointer to the device
9843 * @sw_id: mirror rule's sw_id
9845 * reset a mirror rule.
9849 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9851 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9852 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9853 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9857 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9859 seid = pf->main_vsi->veb->seid;
9861 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9862 if (sw_id == it->index) {
9868 ret = i40e_aq_del_mirror_rule(hw, seid,
9869 mirr_rule->rule_type,
9871 mirr_rule->num_entries, mirr_rule->id);
9874 "failed to remove mirror rule: status = %d, aq_err = %d.",
9875 ret, hw->aq.asq_last_status);
9878 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9879 rte_free(mirr_rule);
9880 pf->nb_mirror_rule--;
9882 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9889 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9891 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9892 uint64_t systim_cycles;
9894 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9895 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9898 return systim_cycles;
9902 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9904 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9907 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9908 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9915 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9917 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9920 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9921 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9928 i40e_start_timecounters(struct rte_eth_dev *dev)
9930 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9931 struct i40e_adapter *adapter =
9932 (struct i40e_adapter *)dev->data->dev_private;
9933 struct rte_eth_link link;
9934 uint32_t tsync_inc_l;
9935 uint32_t tsync_inc_h;
9937 /* Get current link speed. */
9938 memset(&link, 0, sizeof(link));
9939 i40e_dev_link_update(dev, 1);
9940 rte_i40e_dev_atomic_read_link_status(dev, &link);
9942 switch (link.link_speed) {
9943 case ETH_SPEED_NUM_40G:
9944 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9945 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9947 case ETH_SPEED_NUM_10G:
9948 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9949 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9951 case ETH_SPEED_NUM_1G:
9952 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9953 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9960 /* Set the timesync increment value. */
9961 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9962 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9964 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9965 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9966 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9968 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9969 adapter->systime_tc.cc_shift = 0;
9970 adapter->systime_tc.nsec_mask = 0;
9972 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9973 adapter->rx_tstamp_tc.cc_shift = 0;
9974 adapter->rx_tstamp_tc.nsec_mask = 0;
9976 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9977 adapter->tx_tstamp_tc.cc_shift = 0;
9978 adapter->tx_tstamp_tc.nsec_mask = 0;
9982 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9984 struct i40e_adapter *adapter =
9985 (struct i40e_adapter *)dev->data->dev_private;
9987 adapter->systime_tc.nsec += delta;
9988 adapter->rx_tstamp_tc.nsec += delta;
9989 adapter->tx_tstamp_tc.nsec += delta;
9995 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9998 struct i40e_adapter *adapter =
9999 (struct i40e_adapter *)dev->data->dev_private;
10001 ns = rte_timespec_to_ns(ts);
10003 /* Set the timecounters to a new value. */
10004 adapter->systime_tc.nsec = ns;
10005 adapter->rx_tstamp_tc.nsec = ns;
10006 adapter->tx_tstamp_tc.nsec = ns;
10012 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10014 uint64_t ns, systime_cycles;
10015 struct i40e_adapter *adapter =
10016 (struct i40e_adapter *)dev->data->dev_private;
10018 systime_cycles = i40e_read_systime_cyclecounter(dev);
10019 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10020 *ts = rte_ns_to_timespec(ns);
10026 i40e_timesync_enable(struct rte_eth_dev *dev)
10028 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10029 uint32_t tsync_ctl_l;
10030 uint32_t tsync_ctl_h;
10032 /* Stop the timesync system time. */
10033 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10034 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10035 /* Reset the timesync system time value. */
10036 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10037 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10039 i40e_start_timecounters(dev);
10041 /* Clear timesync registers. */
10042 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10043 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10044 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10045 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10046 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10047 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10049 /* Enable timestamping of PTP packets. */
10050 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10051 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10053 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10054 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10055 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10057 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10058 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10064 i40e_timesync_disable(struct rte_eth_dev *dev)
10066 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10067 uint32_t tsync_ctl_l;
10068 uint32_t tsync_ctl_h;
10070 /* Disable timestamping of transmitted PTP packets. */
10071 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10072 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10074 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10075 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10077 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10078 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10080 /* Reset the timesync increment value. */
10081 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10082 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10088 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10089 struct timespec *timestamp, uint32_t flags)
10091 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10092 struct i40e_adapter *adapter =
10093 (struct i40e_adapter *)dev->data->dev_private;
10095 uint32_t sync_status;
10096 uint32_t index = flags & 0x03;
10097 uint64_t rx_tstamp_cycles;
10100 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10101 if ((sync_status & (1 << index)) == 0)
10104 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10105 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10106 *timestamp = rte_ns_to_timespec(ns);
10112 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10113 struct timespec *timestamp)
10115 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10116 struct i40e_adapter *adapter =
10117 (struct i40e_adapter *)dev->data->dev_private;
10119 uint32_t sync_status;
10120 uint64_t tx_tstamp_cycles;
10123 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10124 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10127 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10128 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10129 *timestamp = rte_ns_to_timespec(ns);
10135 * i40e_parse_dcb_configure - parse dcb configure from user
10136 * @dev: the device being configured
10137 * @dcb_cfg: pointer of the result of parse
10138 * @*tc_map: bit map of enabled traffic classes
10140 * Returns 0 on success, negative value on failure
10143 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10144 struct i40e_dcbx_config *dcb_cfg,
10147 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10148 uint8_t i, tc_bw, bw_lf;
10150 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10152 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10153 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10154 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10158 /* assume each tc has the same bw */
10159 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10160 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10161 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10162 /* to ensure the sum of tcbw is equal to 100 */
10163 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10164 for (i = 0; i < bw_lf; i++)
10165 dcb_cfg->etscfg.tcbwtable[i]++;
10167 /* assume each tc has the same Transmission Selection Algorithm */
10168 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10169 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10171 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10172 dcb_cfg->etscfg.prioritytable[i] =
10173 dcb_rx_conf->dcb_tc[i];
10175 /* FW needs one App to configure HW */
10176 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10177 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10178 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10179 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10181 if (dcb_rx_conf->nb_tcs == 0)
10182 *tc_map = 1; /* tc0 only */
10184 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10186 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10187 dcb_cfg->pfc.willing = 0;
10188 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10189 dcb_cfg->pfc.pfcenable = *tc_map;
10195 static enum i40e_status_code
10196 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10197 struct i40e_aqc_vsi_properties_data *info,
10198 uint8_t enabled_tcmap)
10200 enum i40e_status_code ret;
10201 int i, total_tc = 0;
10202 uint16_t qpnum_per_tc, bsf, qp_idx;
10203 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10204 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10205 uint16_t used_queues;
10207 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10208 if (ret != I40E_SUCCESS)
10211 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10212 if (enabled_tcmap & (1 << i))
10217 vsi->enabled_tc = enabled_tcmap;
10219 /* different VSI has different queues assigned */
10220 if (vsi->type == I40E_VSI_MAIN)
10221 used_queues = dev_data->nb_rx_queues -
10222 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10223 else if (vsi->type == I40E_VSI_VMDQ2)
10224 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10226 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10227 return I40E_ERR_NO_AVAILABLE_VSI;
10230 qpnum_per_tc = used_queues / total_tc;
10231 /* Number of queues per enabled TC */
10232 if (qpnum_per_tc == 0) {
10233 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10234 return I40E_ERR_INVALID_QP_ID;
10236 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10237 I40E_MAX_Q_PER_TC);
10238 bsf = rte_bsf32(qpnum_per_tc);
10241 * Configure TC and queue mapping parameters, for enabled TC,
10242 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10243 * default queue will serve it.
10246 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10247 if (vsi->enabled_tc & (1 << i)) {
10248 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10249 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10250 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10251 qp_idx += qpnum_per_tc;
10253 info->tc_mapping[i] = 0;
10256 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10257 if (vsi->type == I40E_VSI_SRIOV) {
10258 info->mapping_flags |=
10259 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10260 for (i = 0; i < vsi->nb_qps; i++)
10261 info->queue_mapping[i] =
10262 rte_cpu_to_le_16(vsi->base_queue + i);
10264 info->mapping_flags |=
10265 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10266 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10268 info->valid_sections |=
10269 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10271 return I40E_SUCCESS;
10275 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10276 * @veb: VEB to be configured
10277 * @tc_map: enabled TC bitmap
10279 * Returns 0 on success, negative value on failure
10281 static enum i40e_status_code
10282 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10284 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10285 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10286 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10287 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10288 enum i40e_status_code ret = I40E_SUCCESS;
10292 /* Check if enabled_tc is same as existing or new TCs */
10293 if (veb->enabled_tc == tc_map)
10296 /* configure tc bandwidth */
10297 memset(&veb_bw, 0, sizeof(veb_bw));
10298 veb_bw.tc_valid_bits = tc_map;
10299 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10300 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10301 if (tc_map & BIT_ULL(i))
10302 veb_bw.tc_bw_share_credits[i] = 1;
10304 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10308 "AQ command Config switch_comp BW allocation per TC failed = %d",
10309 hw->aq.asq_last_status);
10313 memset(&ets_query, 0, sizeof(ets_query));
10314 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10316 if (ret != I40E_SUCCESS) {
10318 "Failed to get switch_comp ETS configuration %u",
10319 hw->aq.asq_last_status);
10322 memset(&bw_query, 0, sizeof(bw_query));
10323 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10325 if (ret != I40E_SUCCESS) {
10327 "Failed to get switch_comp bandwidth configuration %u",
10328 hw->aq.asq_last_status);
10332 /* store and print out BW info */
10333 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10334 veb->bw_info.bw_max = ets_query.tc_bw_max;
10335 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10336 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10337 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10338 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10339 I40E_16_BIT_WIDTH);
10340 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10341 veb->bw_info.bw_ets_share_credits[i] =
10342 bw_query.tc_bw_share_credits[i];
10343 veb->bw_info.bw_ets_credits[i] =
10344 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10345 /* 4 bits per TC, 4th bit is reserved */
10346 veb->bw_info.bw_ets_max[i] =
10347 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10348 RTE_LEN2MASK(3, uint8_t));
10349 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10350 veb->bw_info.bw_ets_share_credits[i]);
10351 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10352 veb->bw_info.bw_ets_credits[i]);
10353 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10354 veb->bw_info.bw_ets_max[i]);
10357 veb->enabled_tc = tc_map;
10364 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10365 * @vsi: VSI to be configured
10366 * @tc_map: enabled TC bitmap
10368 * Returns 0 on success, negative value on failure
10370 static enum i40e_status_code
10371 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10373 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10374 struct i40e_vsi_context ctxt;
10375 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10376 enum i40e_status_code ret = I40E_SUCCESS;
10379 /* Check if enabled_tc is same as existing or new TCs */
10380 if (vsi->enabled_tc == tc_map)
10383 /* configure tc bandwidth */
10384 memset(&bw_data, 0, sizeof(bw_data));
10385 bw_data.tc_valid_bits = tc_map;
10386 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10387 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10388 if (tc_map & BIT_ULL(i))
10389 bw_data.tc_bw_credits[i] = 1;
10391 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10394 "AQ command Config VSI BW allocation per TC failed = %d",
10395 hw->aq.asq_last_status);
10398 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10399 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10401 /* Update Queue Pairs Mapping for currently enabled UPs */
10402 ctxt.seid = vsi->seid;
10403 ctxt.pf_num = hw->pf_id;
10405 ctxt.uplink_seid = vsi->uplink_seid;
10406 ctxt.info = vsi->info;
10408 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10412 /* Update the VSI after updating the VSI queue-mapping information */
10413 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10415 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10416 hw->aq.asq_last_status);
10419 /* update the local VSI info with updated queue map */
10420 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10421 sizeof(vsi->info.tc_mapping));
10422 rte_memcpy(&vsi->info.queue_mapping,
10423 &ctxt.info.queue_mapping,
10424 sizeof(vsi->info.queue_mapping));
10425 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10426 vsi->info.valid_sections = 0;
10428 /* query and update current VSI BW information */
10429 ret = i40e_vsi_get_bw_config(vsi);
10432 "Failed updating vsi bw info, err %s aq_err %s",
10433 i40e_stat_str(hw, ret),
10434 i40e_aq_str(hw, hw->aq.asq_last_status));
10438 vsi->enabled_tc = tc_map;
10445 * i40e_dcb_hw_configure - program the dcb setting to hw
10446 * @pf: pf the configuration is taken on
10447 * @new_cfg: new configuration
10448 * @tc_map: enabled TC bitmap
10450 * Returns 0 on success, negative value on failure
10452 static enum i40e_status_code
10453 i40e_dcb_hw_configure(struct i40e_pf *pf,
10454 struct i40e_dcbx_config *new_cfg,
10457 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10458 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10459 struct i40e_vsi *main_vsi = pf->main_vsi;
10460 struct i40e_vsi_list *vsi_list;
10461 enum i40e_status_code ret;
10465 /* Use the FW API if FW > v4.4*/
10466 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10467 (hw->aq.fw_maj_ver >= 5))) {
10469 "FW < v4.4, can not use FW LLDP API to configure DCB");
10470 return I40E_ERR_FIRMWARE_API_VERSION;
10473 /* Check if need reconfiguration */
10474 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10475 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10476 return I40E_SUCCESS;
10479 /* Copy the new config to the current config */
10480 *old_cfg = *new_cfg;
10481 old_cfg->etsrec = old_cfg->etscfg;
10482 ret = i40e_set_dcb_config(hw);
10484 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10485 i40e_stat_str(hw, ret),
10486 i40e_aq_str(hw, hw->aq.asq_last_status));
10489 /* set receive Arbiter to RR mode and ETS scheme by default */
10490 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10491 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10492 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10493 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10494 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10495 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10496 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10497 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10498 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10499 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10500 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10501 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10502 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10504 /* get local mib to check whether it is configured correctly */
10506 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10507 /* Get Local DCB Config */
10508 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10509 &hw->local_dcbx_config);
10511 /* if Veb is created, need to update TC of it at first */
10512 if (main_vsi->veb) {
10513 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10515 PMD_INIT_LOG(WARNING,
10516 "Failed configuring TC for VEB seid=%d",
10517 main_vsi->veb->seid);
10519 /* Update each VSI */
10520 i40e_vsi_config_tc(main_vsi, tc_map);
10521 if (main_vsi->veb) {
10522 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10523 /* Beside main VSI and VMDQ VSIs, only enable default
10524 * TC for other VSIs
10526 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10527 ret = i40e_vsi_config_tc(vsi_list->vsi,
10530 ret = i40e_vsi_config_tc(vsi_list->vsi,
10531 I40E_DEFAULT_TCMAP);
10533 PMD_INIT_LOG(WARNING,
10534 "Failed configuring TC for VSI seid=%d",
10535 vsi_list->vsi->seid);
10539 return I40E_SUCCESS;
10543 * i40e_dcb_init_configure - initial dcb config
10544 * @dev: device being configured
10545 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10547 * Returns 0 on success, negative value on failure
10550 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10552 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10553 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10556 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10557 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10561 /* DCB initialization:
10562 * Update DCB configuration from the Firmware and configure
10563 * LLDP MIB change event.
10565 if (sw_dcb == TRUE) {
10566 ret = i40e_init_dcb(hw);
10567 /* If lldp agent is stopped, the return value from
10568 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10569 * adminq status. Otherwise, it should return success.
10571 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10572 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10573 memset(&hw->local_dcbx_config, 0,
10574 sizeof(struct i40e_dcbx_config));
10575 /* set dcb default configuration */
10576 hw->local_dcbx_config.etscfg.willing = 0;
10577 hw->local_dcbx_config.etscfg.maxtcs = 0;
10578 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10579 hw->local_dcbx_config.etscfg.tsatable[0] =
10581 /* all UPs mapping to TC0 */
10582 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10583 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10584 hw->local_dcbx_config.etsrec =
10585 hw->local_dcbx_config.etscfg;
10586 hw->local_dcbx_config.pfc.willing = 0;
10587 hw->local_dcbx_config.pfc.pfccap =
10588 I40E_MAX_TRAFFIC_CLASS;
10589 /* FW needs one App to configure HW */
10590 hw->local_dcbx_config.numapps = 1;
10591 hw->local_dcbx_config.app[0].selector =
10592 I40E_APP_SEL_ETHTYPE;
10593 hw->local_dcbx_config.app[0].priority = 3;
10594 hw->local_dcbx_config.app[0].protocolid =
10595 I40E_APP_PROTOID_FCOE;
10596 ret = i40e_set_dcb_config(hw);
10599 "default dcb config fails. err = %d, aq_err = %d.",
10600 ret, hw->aq.asq_last_status);
10605 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10606 ret, hw->aq.asq_last_status);
10610 ret = i40e_aq_start_lldp(hw, NULL);
10611 if (ret != I40E_SUCCESS)
10612 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10614 ret = i40e_init_dcb(hw);
10616 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10618 "HW doesn't support DCBX offload.");
10623 "DCBX configuration failed, err = %d, aq_err = %d.",
10624 ret, hw->aq.asq_last_status);
10632 * i40e_dcb_setup - setup dcb related config
10633 * @dev: device being configured
10635 * Returns 0 on success, negative value on failure
10638 i40e_dcb_setup(struct rte_eth_dev *dev)
10640 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10641 struct i40e_dcbx_config dcb_cfg;
10642 uint8_t tc_map = 0;
10645 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10646 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10650 if (pf->vf_num != 0)
10651 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10653 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10655 PMD_INIT_LOG(ERR, "invalid dcb config");
10658 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10660 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10668 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10669 struct rte_eth_dcb_info *dcb_info)
10671 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10672 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10673 struct i40e_vsi *vsi = pf->main_vsi;
10674 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10675 uint16_t bsf, tc_mapping;
10678 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10679 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10681 dcb_info->nb_tcs = 1;
10682 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10683 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10684 for (i = 0; i < dcb_info->nb_tcs; i++)
10685 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10687 /* get queue mapping if vmdq is disabled */
10688 if (!pf->nb_cfg_vmdq_vsi) {
10689 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10690 if (!(vsi->enabled_tc & (1 << i)))
10692 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10693 dcb_info->tc_queue.tc_rxq[j][i].base =
10694 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10695 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10696 dcb_info->tc_queue.tc_txq[j][i].base =
10697 dcb_info->tc_queue.tc_rxq[j][i].base;
10698 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10699 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10700 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10701 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10702 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10707 /* get queue mapping if vmdq is enabled */
10709 vsi = pf->vmdq[j].vsi;
10710 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10711 if (!(vsi->enabled_tc & (1 << i)))
10713 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10714 dcb_info->tc_queue.tc_rxq[j][i].base =
10715 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10716 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10717 dcb_info->tc_queue.tc_txq[j][i].base =
10718 dcb_info->tc_queue.tc_rxq[j][i].base;
10719 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10720 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10721 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10722 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10723 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10726 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10731 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10733 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10734 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10735 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10736 uint16_t interval =
10737 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
10738 uint16_t msix_intr;
10740 msix_intr = intr_handle->intr_vec[queue_id];
10741 if (msix_intr == I40E_MISC_VEC_ID)
10742 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10743 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10744 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10745 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10747 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10750 I40E_PFINT_DYN_CTLN(msix_intr -
10751 I40E_RX_VEC_START),
10752 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10753 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10754 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10756 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10758 I40E_WRITE_FLUSH(hw);
10759 rte_intr_enable(&pci_dev->intr_handle);
10765 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10767 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10768 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10769 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10770 uint16_t msix_intr;
10772 msix_intr = intr_handle->intr_vec[queue_id];
10773 if (msix_intr == I40E_MISC_VEC_ID)
10774 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10777 I40E_PFINT_DYN_CTLN(msix_intr -
10778 I40E_RX_VEC_START),
10780 I40E_WRITE_FLUSH(hw);
10785 static int i40e_get_regs(struct rte_eth_dev *dev,
10786 struct rte_dev_reg_info *regs)
10788 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10789 uint32_t *ptr_data = regs->data;
10790 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10791 const struct i40e_reg_info *reg_info;
10793 if (ptr_data == NULL) {
10794 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10795 regs->width = sizeof(uint32_t);
10799 /* The first few registers have to be read using AQ operations */
10801 while (i40e_regs_adminq[reg_idx].name) {
10802 reg_info = &i40e_regs_adminq[reg_idx++];
10803 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10805 arr_idx2 <= reg_info->count2;
10807 reg_offset = arr_idx * reg_info->stride1 +
10808 arr_idx2 * reg_info->stride2;
10809 reg_offset += reg_info->base_addr;
10810 ptr_data[reg_offset >> 2] =
10811 i40e_read_rx_ctl(hw, reg_offset);
10815 /* The remaining registers can be read using primitives */
10817 while (i40e_regs_others[reg_idx].name) {
10818 reg_info = &i40e_regs_others[reg_idx++];
10819 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10821 arr_idx2 <= reg_info->count2;
10823 reg_offset = arr_idx * reg_info->stride1 +
10824 arr_idx2 * reg_info->stride2;
10825 reg_offset += reg_info->base_addr;
10826 ptr_data[reg_offset >> 2] =
10827 I40E_READ_REG(hw, reg_offset);
10834 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10836 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10838 /* Convert word count to byte count */
10839 return hw->nvm.sr_size << 1;
10842 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10843 struct rte_dev_eeprom_info *eeprom)
10845 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10846 uint16_t *data = eeprom->data;
10847 uint16_t offset, length, cnt_words;
10850 offset = eeprom->offset >> 1;
10851 length = eeprom->length >> 1;
10852 cnt_words = length;
10854 if (offset > hw->nvm.sr_size ||
10855 offset + length > hw->nvm.sr_size) {
10856 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10860 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10862 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10863 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10864 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10871 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10872 struct ether_addr *mac_addr)
10874 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10876 if (!is_valid_assigned_ether_addr(mac_addr)) {
10877 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10881 /* Flags: 0x3 updates port address */
10882 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10886 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10888 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10889 struct rte_eth_dev_data *dev_data = pf->dev_data;
10890 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10893 /* check if mtu is within the allowed range */
10894 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10897 /* mtu setting is forbidden if port is start */
10898 if (dev_data->dev_started) {
10899 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10900 dev_data->port_id);
10904 if (frame_size > ETHER_MAX_LEN)
10905 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10907 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10909 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10914 /* Restore ethertype filter */
10916 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10918 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10919 struct i40e_ethertype_filter_list
10920 *ethertype_list = &pf->ethertype.ethertype_list;
10921 struct i40e_ethertype_filter *f;
10922 struct i40e_control_filter_stats stats;
10925 TAILQ_FOREACH(f, ethertype_list, rules) {
10927 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10928 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10929 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10930 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10931 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10933 memset(&stats, 0, sizeof(stats));
10934 i40e_aq_add_rem_control_packet_filter(hw,
10935 f->input.mac_addr.addr_bytes,
10936 f->input.ether_type,
10937 flags, pf->main_vsi->seid,
10938 f->queue, 1, &stats, NULL);
10940 PMD_DRV_LOG(INFO, "Ethertype filter:"
10941 " mac_etype_used = %u, etype_used = %u,"
10942 " mac_etype_free = %u, etype_free = %u",
10943 stats.mac_etype_used, stats.etype_used,
10944 stats.mac_etype_free, stats.etype_free);
10947 /* Restore tunnel filter */
10949 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10951 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10952 struct i40e_vsi *vsi;
10953 struct i40e_pf_vf *vf;
10954 struct i40e_tunnel_filter_list
10955 *tunnel_list = &pf->tunnel.tunnel_list;
10956 struct i40e_tunnel_filter *f;
10957 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10958 bool big_buffer = 0;
10960 TAILQ_FOREACH(f, tunnel_list, rules) {
10962 vsi = pf->main_vsi;
10964 vf = &pf->vfs[f->vf_id];
10967 memset(&cld_filter, 0, sizeof(cld_filter));
10968 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10969 (struct ether_addr *)&cld_filter.element.outer_mac);
10970 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10971 (struct ether_addr *)&cld_filter.element.inner_mac);
10972 cld_filter.element.inner_vlan = f->input.inner_vlan;
10973 cld_filter.element.flags = f->input.flags;
10974 cld_filter.element.tenant_id = f->input.tenant_id;
10975 cld_filter.element.queue_number = f->queue;
10976 rte_memcpy(cld_filter.general_fields,
10977 f->input.general_fields,
10978 sizeof(f->input.general_fields));
10980 if (((f->input.flags &
10981 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
10982 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
10984 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
10985 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
10987 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
10988 I40E_AQC_ADD_CLOUD_FILTER_0X10))
10992 i40e_aq_add_cloud_filters_big_buffer(hw,
10993 vsi->seid, &cld_filter, 1);
10995 i40e_aq_add_cloud_filters(hw, vsi->seid,
10996 &cld_filter.element, 1);
11001 i40e_filter_restore(struct i40e_pf *pf)
11003 i40e_ethertype_filter_restore(pf);
11004 i40e_tunnel_filter_restore(pf);
11005 i40e_fdir_filter_restore(pf);
11009 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11011 if (strcmp(dev->device->driver->name, drv->driver.name))
11018 is_i40e_supported(struct rte_eth_dev *dev)
11020 return is_device_supported(dev, &rte_i40e_pmd);
11023 struct i40e_customized_pctype*
11024 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11028 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11029 if (pf->customized_pctype[i].index == index)
11030 return &pf->customized_pctype[i];
11036 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11037 uint32_t pkg_size, uint32_t proto_num,
11038 struct rte_pmd_i40e_proto_info *proto)
11040 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11041 uint32_t pctype_num;
11042 struct rte_pmd_i40e_ptype_info *pctype;
11043 uint32_t buff_size;
11044 struct i40e_customized_pctype *new_pctype = NULL;
11046 uint8_t pctype_value;
11051 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11052 (uint8_t *)&pctype_num, sizeof(pctype_num),
11053 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11055 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11059 PMD_DRV_LOG(INFO, "No new pctype added");
11063 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11064 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11066 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11069 /* get information about new pctype list */
11070 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11071 (uint8_t *)pctype, buff_size,
11072 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11074 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11079 /* Update customized pctype. */
11080 for (i = 0; i < pctype_num; i++) {
11081 pctype_value = pctype[i].ptype_id;
11082 memset(name, 0, sizeof(name));
11083 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11084 proto_id = pctype[i].protocols[j];
11085 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11087 for (n = 0; n < proto_num; n++) {
11088 if (proto[n].proto_id != proto_id)
11090 strcat(name, proto[n].name);
11095 name[strlen(name) - 1] = '\0';
11096 if (!strcmp(name, "GTPC"))
11098 i40e_find_customized_pctype(pf,
11099 I40E_CUSTOMIZED_GTPC);
11100 else if (!strcmp(name, "GTPU_IPV4"))
11102 i40e_find_customized_pctype(pf,
11103 I40E_CUSTOMIZED_GTPU_IPV4);
11104 else if (!strcmp(name, "GTPU_IPV6"))
11106 i40e_find_customized_pctype(pf,
11107 I40E_CUSTOMIZED_GTPU_IPV6);
11108 else if (!strcmp(name, "GTPU"))
11110 i40e_find_customized_pctype(pf,
11111 I40E_CUSTOMIZED_GTPU);
11113 new_pctype->pctype = pctype_value;
11114 new_pctype->valid = true;
11123 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11124 uint32_t pkg_size, uint32_t proto_num,
11125 struct rte_pmd_i40e_proto_info *proto)
11127 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11128 uint16_t port_id = dev->data->port_id;
11129 uint32_t ptype_num;
11130 struct rte_pmd_i40e_ptype_info *ptype;
11131 uint32_t buff_size;
11133 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11138 /* get information about new ptype num */
11139 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11140 (uint8_t *)&ptype_num, sizeof(ptype_num),
11141 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11143 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11147 PMD_DRV_LOG(INFO, "No new ptype added");
11151 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11152 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11154 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11158 /* get information about new ptype list */
11159 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11160 (uint8_t *)ptype, buff_size,
11161 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11163 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11168 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11169 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11170 if (!ptype_mapping) {
11171 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11176 /* Update ptype mapping table. */
11177 for (i = 0; i < ptype_num; i++) {
11178 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11179 ptype_mapping[i].sw_ptype = 0;
11181 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11182 proto_id = ptype[i].protocols[j];
11183 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11185 for (n = 0; n < proto_num; n++) {
11186 if (proto[n].proto_id != proto_id)
11188 memset(name, 0, sizeof(name));
11189 strcpy(name, proto[n].name);
11190 if (!strncmp(name, "PPPOE", 5))
11191 ptype_mapping[i].sw_ptype |=
11192 RTE_PTYPE_L2_ETHER_PPPOE;
11193 else if (!strncmp(name, "OIPV4", 5)) {
11194 ptype_mapping[i].sw_ptype |=
11195 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11197 } else if (!strncmp(name, "IPV4", 4) &&
11199 ptype_mapping[i].sw_ptype |=
11200 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11201 else if (!strncmp(name, "IPV4FRAG", 8) &&
11203 ptype_mapping[i].sw_ptype |=
11204 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11205 ptype_mapping[i].sw_ptype |=
11206 RTE_PTYPE_INNER_L4_FRAG;
11207 } else if (!strncmp(name, "IPV4", 4) &&
11209 ptype_mapping[i].sw_ptype |=
11210 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11211 else if (!strncmp(name, "OIPV6", 5)) {
11212 ptype_mapping[i].sw_ptype |=
11213 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11215 } else if (!strncmp(name, "IPV6", 4) &&
11217 ptype_mapping[i].sw_ptype |=
11218 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11219 else if (!strncmp(name, "IPV6FRAG", 8) &&
11221 ptype_mapping[i].sw_ptype |=
11222 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11223 ptype_mapping[i].sw_ptype |=
11224 RTE_PTYPE_INNER_L4_FRAG;
11225 } else if (!strncmp(name, "IPV6", 4) &&
11227 ptype_mapping[i].sw_ptype |=
11228 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11229 else if (!strncmp(name, "UDP", 3) && !in_tunnel)
11230 ptype_mapping[i].sw_ptype |=
11232 else if (!strncmp(name, "UDP", 3) && in_tunnel)
11233 ptype_mapping[i].sw_ptype |=
11234 RTE_PTYPE_INNER_L4_UDP;
11235 else if (!strncmp(name, "TCP", 3) && !in_tunnel)
11236 ptype_mapping[i].sw_ptype |=
11238 else if (!strncmp(name, "TCP", 3) && in_tunnel)
11239 ptype_mapping[i].sw_ptype |=
11240 RTE_PTYPE_INNER_L4_TCP;
11241 else if (!strncmp(name, "SCTP", 4) &&
11243 ptype_mapping[i].sw_ptype |=
11245 else if (!strncmp(name, "SCTP", 4) && in_tunnel)
11246 ptype_mapping[i].sw_ptype |=
11247 RTE_PTYPE_INNER_L4_SCTP;
11248 else if ((!strncmp(name, "ICMP", 4) ||
11249 !strncmp(name, "ICMPV6", 6)) &&
11251 ptype_mapping[i].sw_ptype |=
11253 else if ((!strncmp(name, "ICMP", 4) ||
11254 !strncmp(name, "ICMPV6", 6)) &&
11256 ptype_mapping[i].sw_ptype |=
11257 RTE_PTYPE_INNER_L4_ICMP;
11258 else if (!strncmp(name, "GTPC", 4)) {
11259 ptype_mapping[i].sw_ptype |=
11260 RTE_PTYPE_TUNNEL_GTPC;
11262 } else if (!strncmp(name, "GTPU", 4)) {
11263 ptype_mapping[i].sw_ptype |=
11264 RTE_PTYPE_TUNNEL_GTPU;
11266 } else if (!strncmp(name, "GRENAT", 6)) {
11267 ptype_mapping[i].sw_ptype |=
11268 RTE_PTYPE_TUNNEL_GRENAT;
11270 } else if (!strncmp(name, "L2TPv2CTL", 9)) {
11271 ptype_mapping[i].sw_ptype |=
11272 RTE_PTYPE_TUNNEL_L2TP;
11281 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11284 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11286 rte_free(ptype_mapping);
11292 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11295 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11296 uint32_t proto_num;
11297 struct rte_pmd_i40e_proto_info *proto;
11298 uint32_t buff_size;
11302 /* get information about protocol number */
11303 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11304 (uint8_t *)&proto_num, sizeof(proto_num),
11305 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11307 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11311 PMD_DRV_LOG(INFO, "No new protocol added");
11315 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11316 proto = rte_zmalloc("new_proto", buff_size, 0);
11318 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11322 /* get information about protocol list */
11323 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11324 (uint8_t *)proto, buff_size,
11325 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11327 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11332 /* Check if GTP is supported. */
11333 for (i = 0; i < proto_num; i++) {
11334 if (!strncmp(proto[i].name, "GTP", 3)) {
11335 pf->gtp_support = true;
11340 /* Update customized pctype info */
11341 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11344 PMD_DRV_LOG(INFO, "No pctype is updated.");
11346 /* Update customized ptype info */
11347 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11350 PMD_DRV_LOG(INFO, "No ptype is updated.");
11355 /* Create a QinQ cloud filter
11357 * The Fortville NIC has limited resources for tunnel filters,
11358 * so we can only reuse existing filters.
11360 * In step 1 we define which Field Vector fields can be used for
11362 * As we do not have the inner tag defined as a field,
11363 * we have to define it first, by reusing one of L1 entries.
11365 * In step 2 we are replacing one of existing filter types with
11366 * a new one for QinQ.
11367 * As we reusing L1 and replacing L2, some of the default filter
11368 * types will disappear,which depends on L1 and L2 entries we reuse.
11370 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11372 * 1. Create L1 filter of outer vlan (12b) which will be in use
11373 * later when we define the cloud filter.
11374 * a. Valid_flags.replace_cloud = 0
11375 * b. Old_filter = 10 (Stag_Inner_Vlan)
11376 * c. New_filter = 0x10
11377 * d. TR bit = 0xff (optional, not used here)
11378 * e. Buffer – 2 entries:
11379 * i. Byte 0 = 8 (outer vlan FV index).
11381 * Byte 2-3 = 0x0fff
11382 * ii. Byte 0 = 37 (inner vlan FV index).
11384 * Byte 2-3 = 0x0fff
11387 * 2. Create cloud filter using two L1 filters entries: stag and
11388 * new filter(outer vlan+ inner vlan)
11389 * a. Valid_flags.replace_cloud = 1
11390 * b. Old_filter = 1 (instead of outer IP)
11391 * c. New_filter = 0x10
11392 * d. Buffer – 2 entries:
11393 * i. Byte 0 = 0x80 | 7 (valid | Stag).
11394 * Byte 1-3 = 0 (rsv)
11395 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11396 * Byte 9-11 = 0 (rsv)
11399 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11401 int ret = -ENOTSUP;
11402 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
11403 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
11404 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11407 memset(&filter_replace, 0,
11408 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11409 memset(&filter_replace_buf, 0,
11410 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11412 /* create L1 filter */
11413 filter_replace.old_filter_type =
11414 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11415 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11416 filter_replace.tr_bit = 0;
11418 /* Prepare the buffer, 2 entries */
11419 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11420 filter_replace_buf.data[0] |=
11421 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11422 /* Field Vector 12b mask */
11423 filter_replace_buf.data[2] = 0xff;
11424 filter_replace_buf.data[3] = 0x0f;
11425 filter_replace_buf.data[4] =
11426 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11427 filter_replace_buf.data[4] |=
11428 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11429 /* Field Vector 12b mask */
11430 filter_replace_buf.data[6] = 0xff;
11431 filter_replace_buf.data[7] = 0x0f;
11432 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11433 &filter_replace_buf);
11434 if (ret != I40E_SUCCESS)
11437 /* Apply the second L2 cloud filter */
11438 memset(&filter_replace, 0,
11439 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11440 memset(&filter_replace_buf, 0,
11441 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11443 /* create L2 filter, input for L2 filter will be L1 filter */
11444 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11445 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11446 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11448 /* Prepare the buffer, 2 entries */
11449 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11450 filter_replace_buf.data[0] |=
11451 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11452 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11453 filter_replace_buf.data[4] |=
11454 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11455 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11456 &filter_replace_buf);
11460 RTE_INIT(i40e_init_log);
11462 i40e_init_log(void)
11464 i40e_logtype_init = rte_log_register("pmd.i40e.init");
11465 if (i40e_logtype_init >= 0)
11466 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11467 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11468 if (i40e_logtype_driver >= 0)
11469 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);