4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memzone.h>
49 #include <rte_malloc.h>
50 #include <rte_memcpy.h>
51 #include <rte_alarm.h>
53 #include <rte_eth_ctrl.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define I40E_CLEAR_PXE_WAIT_MS 200
68 /* Maximun number of capability elements */
69 #define I40E_MAX_CAP_ELE_NUM 128
71 /* Wait count and inteval */
72 #define I40E_CHK_Q_ENA_COUNT 1000
73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
75 /* Maximun number of VSI */
76 #define I40E_MAX_NUM_VSIS (384UL)
78 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
80 /* Flow control default timer */
81 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
83 /* Flow control default high water */
84 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
86 /* Flow control default low water */
87 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
89 /* Flow control enable fwd bit */
90 #define I40E_PRTMAC_FWD_CTRL 0x00000001
92 /* Receive Packet Buffer size */
93 #define I40E_RXPBSIZE (968 * 1024)
96 #define I40E_KILOSHIFT 10
98 /* Receive Average Packet Size in Byte*/
99 #define I40E_PACKET_AVERAGE_SIZE 128
101 /* Mask of PF interrupt causes */
102 #define I40E_PFINT_ICR0_ENA_MASK ( \
103 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
104 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
105 I40E_PFINT_ICR0_ENA_GRST_MASK | \
106 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
107 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
109 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
111 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
112 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
114 #define I40E_FLOW_TYPES ( \
115 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
116 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
117 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
118 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
125 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
127 /* Additional timesync values. */
128 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
129 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
130 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
131 #define I40E_PRTTSYN_TSYNENA 0x80000000
132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
133 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
135 #define I40E_MAX_PERCENT 100
136 #define I40E_DEFAULT_DCB_APP_NUM 1
137 #define I40E_DEFAULT_DCB_APP_PRIO 3
139 #define I40E_INSET_NONE 0x00000000000000000ULL
142 #define I40E_INSET_DMAC 0x0000000000000001ULL
143 #define I40E_INSET_SMAC 0x0000000000000002ULL
144 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
145 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
146 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
149 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
150 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
151 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
152 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
153 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
154 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
155 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
157 /* bit 16 ~ bit 31 */
158 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
159 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
160 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
161 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
162 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
163 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
164 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
165 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
167 /* bit 32 ~ bit 47, tunnel fields */
168 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
169 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
170 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
171 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
172 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
173 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
175 /* bit 48 ~ bit 55 */
176 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
178 /* bit 56 ~ bit 63, Flex Payload */
179 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
180 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
181 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
182 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD \
188 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
189 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
190 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
191 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
194 * Below are values for writing un-exposed registers suggested
197 /* Destination MAC address */
198 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
199 /* Source MAC address */
200 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
201 /* Outer (S-Tag) VLAN tag in the outer L2 header */
202 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0200000000000000ULL
203 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
204 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
205 /* Single VLAN tag in the inner L2 header */
206 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
207 /* Source IPv4 address */
208 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
209 /* Destination IPv4 address */
210 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
211 /* IPv4 Type of Service (TOS) */
212 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
214 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
215 /* IPv4 Time to Live */
216 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
217 /* Source IPv6 address */
218 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
219 /* Destination IPv6 address */
220 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
221 /* IPv6 Traffic Class (TC) */
222 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
223 /* IPv6 Next Header */
224 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
226 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
228 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
229 /* Destination L4 port */
230 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
231 /* SCTP verification tag */
232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
235 /* Source port of tunneling UDP */
236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
237 /* Destination port of tunneling UDP */
238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
239 /* UDP Tunneling ID, NVGRE/GRE key */
240 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
241 /* Last ether type */
242 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
243 /* Tunneling outer destination IPv4 address */
244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
245 /* Tunneling outer destination IPv6 address */
246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
247 /* 1st word of flex payload */
248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
249 /* 2nd word of flex payload */
250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
251 /* 3rd word of flex payload */
252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
253 /* 4th word of flex payload */
254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
255 /* 5th word of flex payload */
256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
257 /* 6th word of flex payload */
258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
259 /* 7th word of flex payload */
260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
261 /* 8th word of flex payload */
262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
263 /* all 8 words flex payload */
264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
265 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
267 #define I40E_TRANSLATE_INSET 0
268 #define I40E_TRANSLATE_REG 1
270 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
271 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
272 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
273 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
274 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
275 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
277 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
278 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
279 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
280 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
282 /* PCI offset for querying capability */
283 #define PCI_DEV_CAP_REG 0xA4
284 /* PCI offset for enabling/disabling Extended Tag */
285 #define PCI_DEV_CTRL_REG 0xA8
286 /* Bit mask of Extended Tag capability */
287 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
288 /* Bit shift of Extended Tag enable/disable */
289 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
290 /* Bit mask of Extended Tag enable/disable */
291 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
293 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
294 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
295 static int i40e_dev_configure(struct rte_eth_dev *dev);
296 static int i40e_dev_start(struct rte_eth_dev *dev);
297 static void i40e_dev_stop(struct rte_eth_dev *dev);
298 static void i40e_dev_close(struct rte_eth_dev *dev);
299 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
300 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
301 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
302 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
303 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
304 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
305 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
306 struct rte_eth_stats *stats);
307 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
308 struct rte_eth_xstats *xstats, unsigned n);
309 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
310 struct rte_eth_xstat_name *xstats_names,
312 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
313 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
317 static void i40e_dev_info_get(struct rte_eth_dev *dev,
318 struct rte_eth_dev_info *dev_info);
319 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
322 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
323 enum rte_vlan_type vlan_type,
325 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
326 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
329 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
330 static int i40e_dev_led_on(struct rte_eth_dev *dev);
331 static int i40e_dev_led_off(struct rte_eth_dev *dev);
332 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
333 struct rte_eth_fc_conf *fc_conf);
334 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
335 struct rte_eth_fc_conf *fc_conf);
336 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
337 struct rte_eth_pfc_conf *pfc_conf);
338 static void i40e_macaddr_add(struct rte_eth_dev *dev,
339 struct ether_addr *mac_addr,
342 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
343 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
344 struct rte_eth_rss_reta_entry64 *reta_conf,
346 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
347 struct rte_eth_rss_reta_entry64 *reta_conf,
350 static int i40e_get_cap(struct i40e_hw *hw);
351 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
352 static int i40e_pf_setup(struct i40e_pf *pf);
353 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
354 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
355 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
356 static int i40e_dcb_setup(struct rte_eth_dev *dev);
357 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
358 bool offset_loaded, uint64_t *offset, uint64_t *stat);
359 static void i40e_stat_update_48(struct i40e_hw *hw,
365 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
366 static void i40e_dev_interrupt_handler(
367 __rte_unused struct rte_intr_handle *handle, void *param);
368 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
369 uint32_t base, uint32_t num);
370 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
371 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
373 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
375 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
376 static int i40e_veb_release(struct i40e_veb *veb);
377 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
378 struct i40e_vsi *vsi);
379 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
380 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
381 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
382 struct i40e_macvlan_filter *mv_f,
384 struct ether_addr *addr);
385 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
386 struct i40e_macvlan_filter *mv_f,
389 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
390 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
391 struct rte_eth_rss_conf *rss_conf);
392 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
393 struct rte_eth_rss_conf *rss_conf);
394 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
395 struct rte_eth_udp_tunnel *udp_tunnel);
396 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
397 struct rte_eth_udp_tunnel *udp_tunnel);
398 static void i40e_filter_input_set_init(struct i40e_pf *pf);
399 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
400 struct rte_eth_ethertype_filter *filter,
402 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
403 enum rte_filter_op filter_op,
405 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
406 enum rte_filter_type filter_type,
407 enum rte_filter_op filter_op,
409 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
410 struct rte_eth_dcb_info *dcb_info);
411 static void i40e_configure_registers(struct i40e_hw *hw);
412 static void i40e_hw_init(struct rte_eth_dev *dev);
413 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
414 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
415 struct rte_eth_mirror_conf *mirror_conf,
416 uint8_t sw_id, uint8_t on);
417 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
419 static int i40e_timesync_enable(struct rte_eth_dev *dev);
420 static int i40e_timesync_disable(struct rte_eth_dev *dev);
421 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
422 struct timespec *timestamp,
424 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
425 struct timespec *timestamp);
426 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
428 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
430 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
431 struct timespec *timestamp);
432 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
433 const struct timespec *timestamp);
435 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
437 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
440 static int i40e_get_reg_length(struct rte_eth_dev *dev);
442 static int i40e_get_regs(struct rte_eth_dev *dev,
443 struct rte_dev_reg_info *regs);
445 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
447 static int i40e_get_eeprom(struct rte_eth_dev *dev,
448 struct rte_dev_eeprom_info *eeprom);
450 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
451 struct ether_addr *mac_addr);
453 static const struct rte_pci_id pci_id_i40e_map[] = {
454 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
455 #include "rte_pci_dev_ids.h"
456 { .vendor_id = 0, /* sentinel */ },
459 static const struct eth_dev_ops i40e_eth_dev_ops = {
460 .dev_configure = i40e_dev_configure,
461 .dev_start = i40e_dev_start,
462 .dev_stop = i40e_dev_stop,
463 .dev_close = i40e_dev_close,
464 .promiscuous_enable = i40e_dev_promiscuous_enable,
465 .promiscuous_disable = i40e_dev_promiscuous_disable,
466 .allmulticast_enable = i40e_dev_allmulticast_enable,
467 .allmulticast_disable = i40e_dev_allmulticast_disable,
468 .dev_set_link_up = i40e_dev_set_link_up,
469 .dev_set_link_down = i40e_dev_set_link_down,
470 .link_update = i40e_dev_link_update,
471 .stats_get = i40e_dev_stats_get,
472 .xstats_get = i40e_dev_xstats_get,
473 .xstats_get_names = i40e_dev_xstats_get_names,
474 .stats_reset = i40e_dev_stats_reset,
475 .xstats_reset = i40e_dev_stats_reset,
476 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
477 .dev_infos_get = i40e_dev_info_get,
478 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
479 .vlan_filter_set = i40e_vlan_filter_set,
480 .vlan_tpid_set = i40e_vlan_tpid_set,
481 .vlan_offload_set = i40e_vlan_offload_set,
482 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
483 .vlan_pvid_set = i40e_vlan_pvid_set,
484 .rx_queue_start = i40e_dev_rx_queue_start,
485 .rx_queue_stop = i40e_dev_rx_queue_stop,
486 .tx_queue_start = i40e_dev_tx_queue_start,
487 .tx_queue_stop = i40e_dev_tx_queue_stop,
488 .rx_queue_setup = i40e_dev_rx_queue_setup,
489 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
490 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
491 .rx_queue_release = i40e_dev_rx_queue_release,
492 .rx_queue_count = i40e_dev_rx_queue_count,
493 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
494 .tx_queue_setup = i40e_dev_tx_queue_setup,
495 .tx_queue_release = i40e_dev_tx_queue_release,
496 .dev_led_on = i40e_dev_led_on,
497 .dev_led_off = i40e_dev_led_off,
498 .flow_ctrl_get = i40e_flow_ctrl_get,
499 .flow_ctrl_set = i40e_flow_ctrl_set,
500 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
501 .mac_addr_add = i40e_macaddr_add,
502 .mac_addr_remove = i40e_macaddr_remove,
503 .reta_update = i40e_dev_rss_reta_update,
504 .reta_query = i40e_dev_rss_reta_query,
505 .rss_hash_update = i40e_dev_rss_hash_update,
506 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
507 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
508 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
509 .filter_ctrl = i40e_dev_filter_ctrl,
510 .rxq_info_get = i40e_rxq_info_get,
511 .txq_info_get = i40e_txq_info_get,
512 .mirror_rule_set = i40e_mirror_rule_set,
513 .mirror_rule_reset = i40e_mirror_rule_reset,
514 .timesync_enable = i40e_timesync_enable,
515 .timesync_disable = i40e_timesync_disable,
516 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
517 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
518 .get_dcb_info = i40e_dev_get_dcb_info,
519 .timesync_adjust_time = i40e_timesync_adjust_time,
520 .timesync_read_time = i40e_timesync_read_time,
521 .timesync_write_time = i40e_timesync_write_time,
522 .get_reg_length = i40e_get_reg_length,
523 .get_reg = i40e_get_regs,
524 .get_eeprom_length = i40e_get_eeprom_length,
525 .get_eeprom = i40e_get_eeprom,
526 .mac_addr_set = i40e_set_default_mac_addr,
529 /* store statistics names and its offset in stats structure */
530 struct rte_i40e_xstats_name_off {
531 char name[RTE_ETH_XSTATS_NAME_SIZE];
535 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
536 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
537 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
538 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
539 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
540 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
541 rx_unknown_protocol)},
542 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
543 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
544 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
545 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
548 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
549 sizeof(rte_i40e_stats_strings[0]))
551 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
552 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
553 tx_dropped_link_down)},
554 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
555 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
557 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
558 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
560 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
562 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
564 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
565 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
566 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
567 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
568 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
569 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
573 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
577 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
581 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
583 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
585 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
586 mac_short_packet_dropped)},
587 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
589 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
590 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
591 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
593 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
595 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
597 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
599 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
601 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
603 {"rx_flow_director_atr_match_packets",
604 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
605 {"rx_flow_director_sb_match_packets",
606 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
607 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
609 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
611 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
613 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
617 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
618 sizeof(rte_i40e_hw_port_strings[0]))
620 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
621 {"xon_packets", offsetof(struct i40e_hw_port_stats,
623 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
627 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
628 sizeof(rte_i40e_rxq_prio_strings[0]))
630 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
631 {"xon_packets", offsetof(struct i40e_hw_port_stats,
633 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
635 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
636 priority_xon_2_xoff)},
639 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
640 sizeof(rte_i40e_txq_prio_strings[0]))
642 static struct eth_driver rte_i40e_pmd = {
644 .name = "rte_i40e_pmd",
645 .id_table = pci_id_i40e_map,
646 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
647 RTE_PCI_DRV_DETACHABLE,
649 .eth_dev_init = eth_i40e_dev_init,
650 .eth_dev_uninit = eth_i40e_dev_uninit,
651 .dev_private_size = sizeof(struct i40e_adapter),
655 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
656 struct rte_eth_link *link)
658 struct rte_eth_link *dst = link;
659 struct rte_eth_link *src = &(dev->data->dev_link);
661 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
662 *(uint64_t *)src) == 0)
669 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
670 struct rte_eth_link *link)
672 struct rte_eth_link *dst = &(dev->data->dev_link);
673 struct rte_eth_link *src = link;
675 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
676 *(uint64_t *)src) == 0)
683 * Driver initialization routine.
684 * Invoked once at EAL init time.
685 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
688 rte_i40e_pmd_init(const char *name __rte_unused,
689 const char *params __rte_unused)
691 PMD_INIT_FUNC_TRACE();
692 rte_eth_driver_register(&rte_i40e_pmd);
697 static struct rte_driver rte_i40e_driver = {
699 .init = rte_i40e_pmd_init,
702 PMD_REGISTER_DRIVER(rte_i40e_driver);
705 * Initialize registers for flexible payload, which should be set by NVM.
706 * This should be removed from code once it is fixed in NVM.
708 #ifndef I40E_GLQF_ORT
709 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
711 #ifndef I40E_GLQF_PIT
712 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
715 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
717 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
718 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
719 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
720 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
721 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
722 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
723 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
724 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
725 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
726 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
728 /* GLQF_PIT Registers */
729 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
730 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
733 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
736 * Add a ethertype filter to drop all flow control frames transmitted
740 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
742 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
743 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
744 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
745 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
748 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
749 I40E_FLOW_CONTROL_ETHERTYPE, flags,
750 pf->main_vsi_seid, 0,
753 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
754 " frames from VSIs.");
758 eth_i40e_dev_init(struct rte_eth_dev *dev)
760 struct rte_pci_device *pci_dev;
761 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
762 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
763 struct i40e_vsi *vsi;
768 PMD_INIT_FUNC_TRACE();
770 dev->dev_ops = &i40e_eth_dev_ops;
771 dev->rx_pkt_burst = i40e_recv_pkts;
772 dev->tx_pkt_burst = i40e_xmit_pkts;
774 /* for secondary processes, we don't initialise any further as primary
775 * has already done this work. Only check we don't need a different
777 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
778 i40e_set_rx_function(dev);
779 i40e_set_tx_function(dev);
782 pci_dev = dev->pci_dev;
784 rte_eth_copy_pci_info(dev, pci_dev);
786 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
787 pf->adapter->eth_dev = dev;
788 pf->dev_data = dev->data;
790 hw->back = I40E_PF_TO_ADAPTER(pf);
791 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
793 PMD_INIT_LOG(ERR, "Hardware is not available, "
794 "as address is NULL");
798 hw->vendor_id = pci_dev->id.vendor_id;
799 hw->device_id = pci_dev->id.device_id;
800 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
801 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
802 hw->bus.device = pci_dev->addr.devid;
803 hw->bus.func = pci_dev->addr.function;
804 hw->adapter_stopped = 0;
806 /* Make sure all is clean before doing PF reset */
809 /* Initialize the hardware */
812 /* Reset here to make sure all is clean for each PF */
813 ret = i40e_pf_reset(hw);
815 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
819 /* Initialize the shared code (base driver) */
820 ret = i40e_init_shared_code(hw);
822 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
827 * To work around the NVM issue,initialize registers
828 * for flexible payload by software.
829 * It should be removed once issues are fixed in NVM.
831 i40e_flex_payload_reg_init(hw);
833 /* Initialize the input set for filters (hash and fd) to default value */
834 i40e_filter_input_set_init(pf);
836 /* Initialize the parameters for adminq */
837 i40e_init_adminq_parameter(hw);
838 ret = i40e_init_adminq(hw);
839 if (ret != I40E_SUCCESS) {
840 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
843 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
844 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
845 hw->aq.api_maj_ver, hw->aq.api_min_ver,
846 ((hw->nvm.version >> 12) & 0xf),
847 ((hw->nvm.version >> 4) & 0xff),
848 (hw->nvm.version & 0xf), hw->nvm.eetrack);
851 i40e_clear_pxe_mode(hw);
854 * On X710, performance number is far from the expectation on recent
855 * firmware versions. The fix for this issue may not be integrated in
856 * the following firmware version. So the workaround in software driver
857 * is needed. It needs to modify the initial values of 3 internal only
858 * registers. Note that the workaround can be removed when it is fixed
859 * in firmware in the future.
861 i40e_configure_registers(hw);
863 /* Get hw capabilities */
864 ret = i40e_get_cap(hw);
865 if (ret != I40E_SUCCESS) {
866 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
867 goto err_get_capabilities;
870 /* Initialize parameters for PF */
871 ret = i40e_pf_parameter_init(dev);
873 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
874 goto err_parameter_init;
877 /* Initialize the queue management */
878 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
880 PMD_INIT_LOG(ERR, "Failed to init queue pool");
881 goto err_qp_pool_init;
883 ret = i40e_res_pool_init(&pf->msix_pool, 1,
884 hw->func_caps.num_msix_vectors - 1);
886 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
887 goto err_msix_pool_init;
890 /* Initialize lan hmc */
891 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
892 hw->func_caps.num_rx_qp, 0, 0);
893 if (ret != I40E_SUCCESS) {
894 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
895 goto err_init_lan_hmc;
898 /* Configure lan hmc */
899 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
900 if (ret != I40E_SUCCESS) {
901 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
902 goto err_configure_lan_hmc;
905 /* Get and check the mac address */
906 i40e_get_mac_addr(hw, hw->mac.addr);
907 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
908 PMD_INIT_LOG(ERR, "mac address is not valid");
910 goto err_get_mac_addr;
912 /* Copy the permanent MAC address */
913 ether_addr_copy((struct ether_addr *) hw->mac.addr,
914 (struct ether_addr *) hw->mac.perm_addr);
916 /* Disable flow control */
917 hw->fc.requested_mode = I40E_FC_NONE;
918 i40e_set_fc(hw, &aq_fail, TRUE);
920 /* Set the global registers with default ether type value */
921 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
922 if (ret != I40E_SUCCESS) {
923 PMD_INIT_LOG(ERR, "Failed to set the default outer "
925 goto err_setup_pf_switch;
927 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
928 if (ret != I40E_SUCCESS) {
929 PMD_INIT_LOG(ERR, "Failed to set the default outer "
931 goto err_setup_pf_switch;
934 /* PF setup, which includes VSI setup */
935 ret = i40e_pf_setup(pf);
937 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
938 goto err_setup_pf_switch;
941 /* reset all stats of the device, including pf and main vsi */
942 i40e_dev_stats_reset(dev);
946 /* Disable double vlan by default */
947 i40e_vsi_config_double_vlan(vsi, FALSE);
949 if (!vsi->max_macaddrs)
950 len = ETHER_ADDR_LEN;
952 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
954 /* Should be after VSI initialized */
955 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
956 if (!dev->data->mac_addrs) {
957 PMD_INIT_LOG(ERR, "Failed to allocated memory "
958 "for storing mac address");
961 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
962 &dev->data->mac_addrs[0]);
964 /* initialize pf host driver to setup SRIOV resource if applicable */
965 i40e_pf_host_init(dev);
967 /* register callback func to eal lib */
968 rte_intr_callback_register(&(pci_dev->intr_handle),
969 i40e_dev_interrupt_handler, (void *)dev);
971 /* configure and enable device interrupt */
972 i40e_pf_config_irq0(hw, TRUE);
973 i40e_pf_enable_irq0(hw);
975 /* enable uio intr after callback register */
976 rte_intr_enable(&(pci_dev->intr_handle));
978 * Add an ethertype filter to drop all flow control frames transmitted
979 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
982 i40e_add_tx_flow_control_drop_filter(pf);
984 /* Set the max frame size to 0x2600 by default,
985 * in case other drivers changed the default value.
987 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
989 /* initialize mirror rule list */
990 TAILQ_INIT(&pf->mirror_list);
992 /* Init dcb to sw mode by default */
993 ret = i40e_dcb_init_configure(dev, TRUE);
994 if (ret != I40E_SUCCESS) {
995 PMD_INIT_LOG(INFO, "Failed to init dcb.");
996 pf->flags &= ~I40E_FLAG_DCB;
1002 i40e_vsi_release(pf->main_vsi);
1003 err_setup_pf_switch:
1005 err_configure_lan_hmc:
1006 (void)i40e_shutdown_lan_hmc(hw);
1008 i40e_res_pool_destroy(&pf->msix_pool);
1010 i40e_res_pool_destroy(&pf->qp_pool);
1013 err_get_capabilities:
1014 (void)i40e_shutdown_adminq(hw);
1020 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1022 struct rte_pci_device *pci_dev;
1024 struct i40e_filter_control_settings settings;
1026 uint8_t aq_fail = 0;
1028 PMD_INIT_FUNC_TRACE();
1030 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1033 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1034 pci_dev = dev->pci_dev;
1036 if (hw->adapter_stopped == 0)
1037 i40e_dev_close(dev);
1039 dev->dev_ops = NULL;
1040 dev->rx_pkt_burst = NULL;
1041 dev->tx_pkt_burst = NULL;
1044 ret = i40e_aq_stop_lldp(hw, true, NULL);
1045 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1046 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1048 /* Clear PXE mode */
1049 i40e_clear_pxe_mode(hw);
1051 /* Unconfigure filter control */
1052 memset(&settings, 0, sizeof(settings));
1053 ret = i40e_set_filter_control(hw, &settings);
1055 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1058 /* Disable flow control */
1059 hw->fc.requested_mode = I40E_FC_NONE;
1060 i40e_set_fc(hw, &aq_fail, TRUE);
1062 /* uninitialize pf host driver */
1063 i40e_pf_host_uninit(dev);
1065 rte_free(dev->data->mac_addrs);
1066 dev->data->mac_addrs = NULL;
1068 /* disable uio intr before callback unregister */
1069 rte_intr_disable(&(pci_dev->intr_handle));
1071 /* register callback func to eal lib */
1072 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1073 i40e_dev_interrupt_handler, (void *)dev);
1079 i40e_dev_configure(struct rte_eth_dev *dev)
1081 struct i40e_adapter *ad =
1082 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1083 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1084 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1087 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1088 * bulk allocation or vector Rx preconditions we will reset it.
1090 ad->rx_bulk_alloc_allowed = true;
1091 ad->rx_vec_allowed = true;
1092 ad->tx_simple_allowed = true;
1093 ad->tx_vec_allowed = true;
1095 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1096 ret = i40e_fdir_setup(pf);
1097 if (ret != I40E_SUCCESS) {
1098 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1101 ret = i40e_fdir_configure(dev);
1103 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1107 i40e_fdir_teardown(pf);
1109 ret = i40e_dev_init_vlan(dev);
1114 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1115 * RSS setting have different requirements.
1116 * General PMD driver call sequence are NIC init, configure,
1117 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1118 * will try to lookup the VSI that specific queue belongs to if VMDQ
1119 * applicable. So, VMDQ setting has to be done before
1120 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1121 * For RSS setting, it will try to calculate actual configured RX queue
1122 * number, which will be available after rx_queue_setup(). dev_start()
1123 * function is good to place RSS setup.
1125 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1126 ret = i40e_vmdq_setup(dev);
1131 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1132 ret = i40e_dcb_setup(dev);
1134 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1142 /* need to release vmdq resource if exists */
1143 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1144 i40e_vsi_release(pf->vmdq[i].vsi);
1145 pf->vmdq[i].vsi = NULL;
1150 /* need to release fdir resource if exists */
1151 i40e_fdir_teardown(pf);
1156 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1158 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1159 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1160 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1161 uint16_t msix_vect = vsi->msix_intr;
1164 for (i = 0; i < vsi->nb_qps; i++) {
1165 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1166 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1170 if (vsi->type != I40E_VSI_SRIOV) {
1171 if (!rte_intr_allow_others(intr_handle)) {
1172 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1173 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1175 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1178 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1179 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1181 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1186 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1187 vsi->user_param + (msix_vect - 1);
1189 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1190 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1192 I40E_WRITE_FLUSH(hw);
1196 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1197 int base_queue, int nb_queue)
1201 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1203 /* Bind all RX queues to allocated MSIX interrupt */
1204 for (i = 0; i < nb_queue; i++) {
1205 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1206 I40E_QINT_RQCTL_ITR_INDX_MASK |
1207 ((base_queue + i + 1) <<
1208 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1209 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1210 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1212 if (i == nb_queue - 1)
1213 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1214 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1217 /* Write first RX queue to Link list register as the head element */
1218 if (vsi->type != I40E_VSI_SRIOV) {
1220 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1222 if (msix_vect == I40E_MISC_VEC_ID) {
1223 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1225 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1227 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1229 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1232 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1234 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1236 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1238 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1245 if (msix_vect == I40E_MISC_VEC_ID) {
1247 I40E_VPINT_LNKLST0(vsi->user_param),
1249 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1251 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1253 /* num_msix_vectors_vf needs to minus irq0 */
1254 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1255 vsi->user_param + (msix_vect - 1);
1257 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1259 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1261 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1265 I40E_WRITE_FLUSH(hw);
1269 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1271 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1272 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1273 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1274 uint16_t msix_vect = vsi->msix_intr;
1275 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1276 uint16_t queue_idx = 0;
1281 for (i = 0; i < vsi->nb_qps; i++) {
1282 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1283 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1286 /* INTENA flag is not auto-cleared for interrupt */
1287 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1288 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1289 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1290 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1291 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1293 /* VF bind interrupt */
1294 if (vsi->type == I40E_VSI_SRIOV) {
1295 __vsi_queues_bind_intr(vsi, msix_vect,
1296 vsi->base_queue, vsi->nb_qps);
1300 /* PF & VMDq bind interrupt */
1301 if (rte_intr_dp_is_en(intr_handle)) {
1302 if (vsi->type == I40E_VSI_MAIN) {
1305 } else if (vsi->type == I40E_VSI_VMDQ2) {
1306 struct i40e_vsi *main_vsi =
1307 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1308 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1313 for (i = 0; i < vsi->nb_used_qps; i++) {
1315 if (!rte_intr_allow_others(intr_handle))
1316 /* allow to share MISC_VEC_ID */
1317 msix_vect = I40E_MISC_VEC_ID;
1319 /* no enough msix_vect, map all to one */
1320 __vsi_queues_bind_intr(vsi, msix_vect,
1321 vsi->base_queue + i,
1322 vsi->nb_used_qps - i);
1323 for (; !!record && i < vsi->nb_used_qps; i++)
1324 intr_handle->intr_vec[queue_idx + i] =
1328 /* 1:1 queue/msix_vect mapping */
1329 __vsi_queues_bind_intr(vsi, msix_vect,
1330 vsi->base_queue + i, 1);
1332 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1340 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1342 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1343 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1344 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1345 uint16_t interval = i40e_calc_itr_interval(\
1346 RTE_LIBRTE_I40E_ITR_INTERVAL);
1347 uint16_t msix_intr, i;
1349 if (rte_intr_allow_others(intr_handle))
1350 for (i = 0; i < vsi->nb_msix; i++) {
1351 msix_intr = vsi->msix_intr + i;
1352 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1353 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1354 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1355 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1357 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1360 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1361 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1362 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1363 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1365 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1367 I40E_WRITE_FLUSH(hw);
1371 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1373 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1374 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1375 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1376 uint16_t msix_intr, i;
1378 if (rte_intr_allow_others(intr_handle))
1379 for (i = 0; i < vsi->nb_msix; i++) {
1380 msix_intr = vsi->msix_intr + i;
1381 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1385 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1387 I40E_WRITE_FLUSH(hw);
1390 static inline uint8_t
1391 i40e_parse_link_speeds(uint16_t link_speeds)
1393 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1395 if (link_speeds & ETH_LINK_SPEED_40G)
1396 link_speed |= I40E_LINK_SPEED_40GB;
1397 if (link_speeds & ETH_LINK_SPEED_20G)
1398 link_speed |= I40E_LINK_SPEED_20GB;
1399 if (link_speeds & ETH_LINK_SPEED_10G)
1400 link_speed |= I40E_LINK_SPEED_10GB;
1401 if (link_speeds & ETH_LINK_SPEED_1G)
1402 link_speed |= I40E_LINK_SPEED_1GB;
1403 if (link_speeds & ETH_LINK_SPEED_100M)
1404 link_speed |= I40E_LINK_SPEED_100MB;
1410 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1411 __rte_unused uint8_t abilities,
1412 __rte_unused uint8_t force_speed)
1414 /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1415 * for the link control limitation of that all link control should be
1416 * handled by firmware. It should follow up if link control will be
1417 * opened to software driver in future firmware versions.
1419 return I40E_SUCCESS;
1423 i40e_apply_link_speed(struct rte_eth_dev *dev)
1426 uint8_t abilities = 0;
1427 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428 struct rte_eth_conf *conf = &dev->data->dev_conf;
1430 speed = i40e_parse_link_speeds(conf->link_speeds);
1431 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1432 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1433 abilities |= I40E_AQ_PHY_AN_ENABLED;
1435 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1437 return i40e_phy_conf_link(hw, abilities, speed);
1441 i40e_dev_start(struct rte_eth_dev *dev)
1443 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1444 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445 struct i40e_vsi *main_vsi = pf->main_vsi;
1447 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1448 uint32_t intr_vector = 0;
1450 hw->adapter_stopped = 0;
1452 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1453 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1454 dev->data->port_id);
1458 rte_intr_disable(intr_handle);
1460 if ((rte_intr_cap_multiple(intr_handle) ||
1461 !RTE_ETH_DEV_SRIOV(dev).active) &&
1462 dev->data->dev_conf.intr_conf.rxq != 0) {
1463 intr_vector = dev->data->nb_rx_queues;
1464 if (rte_intr_efd_enable(intr_handle, intr_vector))
1468 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1469 intr_handle->intr_vec =
1470 rte_zmalloc("intr_vec",
1471 dev->data->nb_rx_queues * sizeof(int),
1473 if (!intr_handle->intr_vec) {
1474 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1475 " intr_vec\n", dev->data->nb_rx_queues);
1480 /* Initialize VSI */
1481 ret = i40e_dev_rxtx_init(pf);
1482 if (ret != I40E_SUCCESS) {
1483 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1487 /* Map queues with MSIX interrupt */
1488 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1489 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1490 i40e_vsi_queues_bind_intr(main_vsi);
1491 i40e_vsi_enable_queues_intr(main_vsi);
1493 /* Map VMDQ VSI queues with MSIX interrupt */
1494 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1495 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1496 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1497 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1500 /* enable FDIR MSIX interrupt */
1501 if (pf->fdir.fdir_vsi) {
1502 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1503 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1506 /* Enable all queues which have been configured */
1507 ret = i40e_dev_switch_queues(pf, TRUE);
1508 if (ret != I40E_SUCCESS) {
1509 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1513 /* Enable receiving broadcast packets */
1514 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1515 if (ret != I40E_SUCCESS)
1516 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1518 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1519 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1521 if (ret != I40E_SUCCESS)
1522 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1525 /* Apply link configure */
1526 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1527 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1528 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1529 PMD_DRV_LOG(ERR, "Invalid link setting");
1532 ret = i40e_apply_link_speed(dev);
1533 if (I40E_SUCCESS != ret) {
1534 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1538 if (!rte_intr_allow_others(intr_handle)) {
1539 rte_intr_callback_unregister(intr_handle,
1540 i40e_dev_interrupt_handler,
1542 /* configure and enable device interrupt */
1543 i40e_pf_config_irq0(hw, FALSE);
1544 i40e_pf_enable_irq0(hw);
1546 if (dev->data->dev_conf.intr_conf.lsc != 0)
1547 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1548 " no intr multiplex\n");
1551 /* enable uio intr after callback register */
1552 rte_intr_enable(intr_handle);
1554 return I40E_SUCCESS;
1557 i40e_dev_switch_queues(pf, FALSE);
1558 i40e_dev_clear_queues(dev);
1564 i40e_dev_stop(struct rte_eth_dev *dev)
1566 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1567 struct i40e_vsi *main_vsi = pf->main_vsi;
1568 struct i40e_mirror_rule *p_mirror;
1569 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1572 /* Disable all queues */
1573 i40e_dev_switch_queues(pf, FALSE);
1575 /* un-map queues with interrupt registers */
1576 i40e_vsi_disable_queues_intr(main_vsi);
1577 i40e_vsi_queues_unbind_intr(main_vsi);
1579 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1580 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1581 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1584 if (pf->fdir.fdir_vsi) {
1585 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1586 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1588 /* Clear all queues and release memory */
1589 i40e_dev_clear_queues(dev);
1592 i40e_dev_set_link_down(dev);
1594 /* Remove all mirror rules */
1595 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1596 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1599 pf->nb_mirror_rule = 0;
1601 if (!rte_intr_allow_others(intr_handle))
1602 /* resume to the default handler */
1603 rte_intr_callback_register(intr_handle,
1604 i40e_dev_interrupt_handler,
1607 /* Clean datapath event and queue/vec mapping */
1608 rte_intr_efd_disable(intr_handle);
1609 if (intr_handle->intr_vec) {
1610 rte_free(intr_handle->intr_vec);
1611 intr_handle->intr_vec = NULL;
1616 i40e_dev_close(struct rte_eth_dev *dev)
1618 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1619 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623 PMD_INIT_FUNC_TRACE();
1626 hw->adapter_stopped = 1;
1627 i40e_dev_free_queues(dev);
1629 /* Disable interrupt */
1630 i40e_pf_disable_irq0(hw);
1631 rte_intr_disable(&(dev->pci_dev->intr_handle));
1633 /* shutdown and destroy the HMC */
1634 i40e_shutdown_lan_hmc(hw);
1636 /* release all the existing VSIs and VEBs */
1637 i40e_fdir_teardown(pf);
1638 i40e_vsi_release(pf->main_vsi);
1640 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1641 i40e_vsi_release(pf->vmdq[i].vsi);
1642 pf->vmdq[i].vsi = NULL;
1648 /* shutdown the adminq */
1649 i40e_aq_queue_shutdown(hw, true);
1650 i40e_shutdown_adminq(hw);
1652 i40e_res_pool_destroy(&pf->qp_pool);
1653 i40e_res_pool_destroy(&pf->msix_pool);
1655 /* force a PF reset to clean anything leftover */
1656 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1657 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1658 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1659 I40E_WRITE_FLUSH(hw);
1663 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1665 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1666 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1667 struct i40e_vsi *vsi = pf->main_vsi;
1670 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1672 if (status != I40E_SUCCESS)
1673 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1675 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1677 if (status != I40E_SUCCESS)
1678 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1683 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1685 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1686 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687 struct i40e_vsi *vsi = pf->main_vsi;
1690 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1692 if (status != I40E_SUCCESS)
1693 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1695 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1697 if (status != I40E_SUCCESS)
1698 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1702 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1704 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1705 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1706 struct i40e_vsi *vsi = pf->main_vsi;
1709 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1710 if (ret != I40E_SUCCESS)
1711 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1715 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1717 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1718 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719 struct i40e_vsi *vsi = pf->main_vsi;
1722 if (dev->data->promiscuous == 1)
1723 return; /* must remain in all_multicast mode */
1725 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1726 vsi->seid, FALSE, NULL);
1727 if (ret != I40E_SUCCESS)
1728 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1732 * Set device link up.
1735 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1737 /* re-apply link speed setting */
1738 return i40e_apply_link_speed(dev);
1742 * Set device link down.
1745 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1747 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1748 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1749 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1751 return i40e_phy_conf_link(hw, abilities, speed);
1755 i40e_dev_link_update(struct rte_eth_dev *dev,
1756 int wait_to_complete)
1758 #define CHECK_INTERVAL 100 /* 100ms */
1759 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1760 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1761 struct i40e_link_status link_status;
1762 struct rte_eth_link link, old;
1764 unsigned rep_cnt = MAX_REPEAT_TIME;
1766 memset(&link, 0, sizeof(link));
1767 memset(&old, 0, sizeof(old));
1768 memset(&link_status, 0, sizeof(link_status));
1769 rte_i40e_dev_atomic_read_link_status(dev, &old);
1772 /* Get link status information from hardware */
1773 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1774 if (status != I40E_SUCCESS) {
1775 link.link_speed = ETH_SPEED_NUM_100M;
1776 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1777 PMD_DRV_LOG(ERR, "Failed to get link info");
1781 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1782 if (!wait_to_complete)
1785 rte_delay_ms(CHECK_INTERVAL);
1786 } while (!link.link_status && rep_cnt--);
1788 if (!link.link_status)
1791 /* i40e uses full duplex only */
1792 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1794 /* Parse the link status */
1795 switch (link_status.link_speed) {
1796 case I40E_LINK_SPEED_100MB:
1797 link.link_speed = ETH_SPEED_NUM_100M;
1799 case I40E_LINK_SPEED_1GB:
1800 link.link_speed = ETH_SPEED_NUM_1G;
1802 case I40E_LINK_SPEED_10GB:
1803 link.link_speed = ETH_SPEED_NUM_10G;
1805 case I40E_LINK_SPEED_20GB:
1806 link.link_speed = ETH_SPEED_NUM_20G;
1808 case I40E_LINK_SPEED_40GB:
1809 link.link_speed = ETH_SPEED_NUM_40G;
1812 link.link_speed = ETH_SPEED_NUM_100M;
1816 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1817 ETH_LINK_SPEED_FIXED);
1820 rte_i40e_dev_atomic_write_link_status(dev, &link);
1821 if (link.link_status == old.link_status)
1827 /* Get all the statistics of a VSI */
1829 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1831 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1832 struct i40e_eth_stats *nes = &vsi->eth_stats;
1833 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1834 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1836 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1837 vsi->offset_loaded, &oes->rx_bytes,
1839 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1840 vsi->offset_loaded, &oes->rx_unicast,
1842 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1843 vsi->offset_loaded, &oes->rx_multicast,
1844 &nes->rx_multicast);
1845 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1846 vsi->offset_loaded, &oes->rx_broadcast,
1847 &nes->rx_broadcast);
1848 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1849 &oes->rx_discards, &nes->rx_discards);
1850 /* GLV_REPC not supported */
1851 /* GLV_RMPC not supported */
1852 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1853 &oes->rx_unknown_protocol,
1854 &nes->rx_unknown_protocol);
1855 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1856 vsi->offset_loaded, &oes->tx_bytes,
1858 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1859 vsi->offset_loaded, &oes->tx_unicast,
1861 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1862 vsi->offset_loaded, &oes->tx_multicast,
1863 &nes->tx_multicast);
1864 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1865 vsi->offset_loaded, &oes->tx_broadcast,
1866 &nes->tx_broadcast);
1867 /* GLV_TDPC not supported */
1868 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1869 &oes->tx_errors, &nes->tx_errors);
1870 vsi->offset_loaded = true;
1872 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1874 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1875 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1876 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1877 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1878 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1879 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1880 nes->rx_unknown_protocol);
1881 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1882 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1883 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1884 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1885 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1886 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1887 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1892 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1895 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1896 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1898 /* Get statistics of struct i40e_eth_stats */
1899 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1900 I40E_GLPRT_GORCL(hw->port),
1901 pf->offset_loaded, &os->eth.rx_bytes,
1903 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1904 I40E_GLPRT_UPRCL(hw->port),
1905 pf->offset_loaded, &os->eth.rx_unicast,
1906 &ns->eth.rx_unicast);
1907 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1908 I40E_GLPRT_MPRCL(hw->port),
1909 pf->offset_loaded, &os->eth.rx_multicast,
1910 &ns->eth.rx_multicast);
1911 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1912 I40E_GLPRT_BPRCL(hw->port),
1913 pf->offset_loaded, &os->eth.rx_broadcast,
1914 &ns->eth.rx_broadcast);
1915 /* Workaround: CRC size should not be included in byte statistics,
1916 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1918 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1919 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1921 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1922 pf->offset_loaded, &os->eth.rx_discards,
1923 &ns->eth.rx_discards);
1924 /* GLPRT_REPC not supported */
1925 /* GLPRT_RMPC not supported */
1926 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1928 &os->eth.rx_unknown_protocol,
1929 &ns->eth.rx_unknown_protocol);
1930 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1931 I40E_GLPRT_GOTCL(hw->port),
1932 pf->offset_loaded, &os->eth.tx_bytes,
1934 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1935 I40E_GLPRT_UPTCL(hw->port),
1936 pf->offset_loaded, &os->eth.tx_unicast,
1937 &ns->eth.tx_unicast);
1938 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1939 I40E_GLPRT_MPTCL(hw->port),
1940 pf->offset_loaded, &os->eth.tx_multicast,
1941 &ns->eth.tx_multicast);
1942 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1943 I40E_GLPRT_BPTCL(hw->port),
1944 pf->offset_loaded, &os->eth.tx_broadcast,
1945 &ns->eth.tx_broadcast);
1946 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1947 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1948 /* GLPRT_TEPC not supported */
1950 /* additional port specific stats */
1951 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1952 pf->offset_loaded, &os->tx_dropped_link_down,
1953 &ns->tx_dropped_link_down);
1954 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1955 pf->offset_loaded, &os->crc_errors,
1957 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1958 pf->offset_loaded, &os->illegal_bytes,
1959 &ns->illegal_bytes);
1960 /* GLPRT_ERRBC not supported */
1961 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1962 pf->offset_loaded, &os->mac_local_faults,
1963 &ns->mac_local_faults);
1964 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1965 pf->offset_loaded, &os->mac_remote_faults,
1966 &ns->mac_remote_faults);
1967 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1968 pf->offset_loaded, &os->rx_length_errors,
1969 &ns->rx_length_errors);
1970 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1971 pf->offset_loaded, &os->link_xon_rx,
1973 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1974 pf->offset_loaded, &os->link_xoff_rx,
1976 for (i = 0; i < 8; i++) {
1977 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1979 &os->priority_xon_rx[i],
1980 &ns->priority_xon_rx[i]);
1981 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1983 &os->priority_xoff_rx[i],
1984 &ns->priority_xoff_rx[i]);
1986 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1987 pf->offset_loaded, &os->link_xon_tx,
1989 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1990 pf->offset_loaded, &os->link_xoff_tx,
1992 for (i = 0; i < 8; i++) {
1993 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1995 &os->priority_xon_tx[i],
1996 &ns->priority_xon_tx[i]);
1997 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1999 &os->priority_xoff_tx[i],
2000 &ns->priority_xoff_tx[i]);
2001 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2003 &os->priority_xon_2_xoff[i],
2004 &ns->priority_xon_2_xoff[i]);
2006 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2007 I40E_GLPRT_PRC64L(hw->port),
2008 pf->offset_loaded, &os->rx_size_64,
2010 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2011 I40E_GLPRT_PRC127L(hw->port),
2012 pf->offset_loaded, &os->rx_size_127,
2014 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2015 I40E_GLPRT_PRC255L(hw->port),
2016 pf->offset_loaded, &os->rx_size_255,
2018 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2019 I40E_GLPRT_PRC511L(hw->port),
2020 pf->offset_loaded, &os->rx_size_511,
2022 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2023 I40E_GLPRT_PRC1023L(hw->port),
2024 pf->offset_loaded, &os->rx_size_1023,
2026 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2027 I40E_GLPRT_PRC1522L(hw->port),
2028 pf->offset_loaded, &os->rx_size_1522,
2030 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2031 I40E_GLPRT_PRC9522L(hw->port),
2032 pf->offset_loaded, &os->rx_size_big,
2034 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2035 pf->offset_loaded, &os->rx_undersize,
2037 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2038 pf->offset_loaded, &os->rx_fragments,
2040 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2041 pf->offset_loaded, &os->rx_oversize,
2043 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2044 pf->offset_loaded, &os->rx_jabber,
2046 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2047 I40E_GLPRT_PTC64L(hw->port),
2048 pf->offset_loaded, &os->tx_size_64,
2050 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2051 I40E_GLPRT_PTC127L(hw->port),
2052 pf->offset_loaded, &os->tx_size_127,
2054 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2055 I40E_GLPRT_PTC255L(hw->port),
2056 pf->offset_loaded, &os->tx_size_255,
2058 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2059 I40E_GLPRT_PTC511L(hw->port),
2060 pf->offset_loaded, &os->tx_size_511,
2062 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2063 I40E_GLPRT_PTC1023L(hw->port),
2064 pf->offset_loaded, &os->tx_size_1023,
2066 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2067 I40E_GLPRT_PTC1522L(hw->port),
2068 pf->offset_loaded, &os->tx_size_1522,
2070 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2071 I40E_GLPRT_PTC9522L(hw->port),
2072 pf->offset_loaded, &os->tx_size_big,
2074 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2076 &os->fd_sb_match, &ns->fd_sb_match);
2077 /* GLPRT_MSPDC not supported */
2078 /* GLPRT_XEC not supported */
2080 pf->offset_loaded = true;
2083 i40e_update_vsi_stats(pf->main_vsi);
2086 /* Get all statistics of a port */
2088 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2090 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2091 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2092 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2095 /* call read registers - updates values, now write them to struct */
2096 i40e_read_stats_registers(pf, hw);
2098 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2099 pf->main_vsi->eth_stats.rx_multicast +
2100 pf->main_vsi->eth_stats.rx_broadcast -
2101 pf->main_vsi->eth_stats.rx_discards;
2102 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2103 pf->main_vsi->eth_stats.tx_multicast +
2104 pf->main_vsi->eth_stats.tx_broadcast;
2105 stats->ibytes = ns->eth.rx_bytes;
2106 stats->obytes = ns->eth.tx_bytes;
2107 stats->oerrors = ns->eth.tx_errors +
2108 pf->main_vsi->eth_stats.tx_errors;
2111 stats->imissed = ns->eth.rx_discards +
2112 pf->main_vsi->eth_stats.rx_discards;
2113 stats->ierrors = ns->crc_errors +
2114 ns->rx_length_errors + ns->rx_undersize +
2115 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2117 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2118 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2119 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2120 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2121 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2122 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2123 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2124 ns->eth.rx_unknown_protocol);
2125 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2126 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2127 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2128 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2129 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2130 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2132 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2133 ns->tx_dropped_link_down);
2134 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2135 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2137 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2138 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2139 ns->mac_local_faults);
2140 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2141 ns->mac_remote_faults);
2142 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2143 ns->rx_length_errors);
2144 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2145 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2146 for (i = 0; i < 8; i++) {
2147 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2148 i, ns->priority_xon_rx[i]);
2149 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2150 i, ns->priority_xoff_rx[i]);
2152 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2153 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2154 for (i = 0; i < 8; i++) {
2155 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2156 i, ns->priority_xon_tx[i]);
2157 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2158 i, ns->priority_xoff_tx[i]);
2159 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2160 i, ns->priority_xon_2_xoff[i]);
2162 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2163 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2164 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2165 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2166 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2167 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2168 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2169 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2170 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2171 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2172 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2173 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2174 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2175 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2176 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2177 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2178 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2179 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2180 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2181 ns->mac_short_packet_dropped);
2182 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2183 ns->checksum_error);
2184 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2185 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2188 /* Reset the statistics */
2190 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2192 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2193 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195 /* Mark PF and VSI stats to update the offset, aka "reset" */
2196 pf->offset_loaded = false;
2198 pf->main_vsi->offset_loaded = false;
2200 /* read the stats, reading current register values into offset */
2201 i40e_read_stats_registers(pf, hw);
2205 i40e_xstats_calc_num(void)
2207 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2208 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2209 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2212 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2213 struct rte_eth_xstat_name *xstats_names,
2214 __rte_unused unsigned limit)
2219 if (xstats_names == NULL)
2220 return i40e_xstats_calc_num();
2222 /* Note: limit checked in rte_eth_xstats_names() */
2224 /* Get stats from i40e_eth_stats struct */
2225 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2226 snprintf(xstats_names[count].name,
2227 sizeof(xstats_names[count].name),
2228 "%s", rte_i40e_stats_strings[i].name);
2229 xstats_names[count].id = count;
2233 /* Get individiual stats from i40e_hw_port struct */
2234 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2235 snprintf(xstats_names[count].name,
2236 sizeof(xstats_names[count].name),
2237 "%s", rte_i40e_hw_port_strings[i].name);
2238 xstats_names[count].id = count;
2242 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2243 for (prio = 0; prio < 8; prio++) {
2244 snprintf(xstats_names[count].name,
2245 sizeof(xstats_names[count].name),
2246 "rx_priority%u_%s", prio,
2247 rte_i40e_rxq_prio_strings[i].name);
2248 xstats_names[count].id = count;
2253 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2254 for (prio = 0; prio < 8; prio++) {
2255 snprintf(xstats_names[count].name,
2256 sizeof(xstats_names[count].name),
2257 "tx_priority%u_%s", prio,
2258 rte_i40e_txq_prio_strings[i].name);
2259 xstats_names[count].id = count;
2267 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2270 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2271 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2272 unsigned i, count, prio;
2273 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2275 count = i40e_xstats_calc_num();
2279 i40e_read_stats_registers(pf, hw);
2286 /* Get stats from i40e_eth_stats struct */
2287 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2288 xstats[count].name[0] = '\0';
2289 xstats[count].id = count;
2290 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2291 rte_i40e_stats_strings[i].offset);
2295 /* Get individiual stats from i40e_hw_port struct */
2296 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2297 xstats[count].name[0] = '\0';
2298 xstats[count].id = count;
2299 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2300 rte_i40e_hw_port_strings[i].offset);
2304 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2305 for (prio = 0; prio < 8; prio++) {
2306 xstats[count].name[0] = '\0';
2307 xstats[count].id = count;
2308 xstats[count].value =
2309 *(uint64_t *)(((char *)hw_stats) +
2310 rte_i40e_rxq_prio_strings[i].offset +
2311 (sizeof(uint64_t) * prio));
2316 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2317 for (prio = 0; prio < 8; prio++) {
2318 xstats[count].name[0] = '\0';
2319 xstats[count].id = count;
2320 xstats[count].value =
2321 *(uint64_t *)(((char *)hw_stats) +
2322 rte_i40e_txq_prio_strings[i].offset +
2323 (sizeof(uint64_t) * prio));
2332 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2333 __rte_unused uint16_t queue_id,
2334 __rte_unused uint8_t stat_idx,
2335 __rte_unused uint8_t is_rx)
2337 PMD_INIT_FUNC_TRACE();
2343 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2345 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2346 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347 struct i40e_vsi *vsi = pf->main_vsi;
2349 dev_info->max_rx_queues = vsi->nb_qps;
2350 dev_info->max_tx_queues = vsi->nb_qps;
2351 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2352 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2353 dev_info->max_mac_addrs = vsi->max_macaddrs;
2354 dev_info->max_vfs = dev->pci_dev->max_vfs;
2355 dev_info->rx_offload_capa =
2356 DEV_RX_OFFLOAD_VLAN_STRIP |
2357 DEV_RX_OFFLOAD_QINQ_STRIP |
2358 DEV_RX_OFFLOAD_IPV4_CKSUM |
2359 DEV_RX_OFFLOAD_UDP_CKSUM |
2360 DEV_RX_OFFLOAD_TCP_CKSUM;
2361 dev_info->tx_offload_capa =
2362 DEV_TX_OFFLOAD_VLAN_INSERT |
2363 DEV_TX_OFFLOAD_QINQ_INSERT |
2364 DEV_TX_OFFLOAD_IPV4_CKSUM |
2365 DEV_TX_OFFLOAD_UDP_CKSUM |
2366 DEV_TX_OFFLOAD_TCP_CKSUM |
2367 DEV_TX_OFFLOAD_SCTP_CKSUM |
2368 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2369 DEV_TX_OFFLOAD_TCP_TSO;
2370 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2372 dev_info->reta_size = pf->hash_lut_size;
2373 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2375 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2377 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2378 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2379 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2381 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2385 dev_info->default_txconf = (struct rte_eth_txconf) {
2387 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2388 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2389 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2391 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2392 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2393 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2394 ETH_TXQ_FLAGS_NOOFFLOADS,
2397 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2398 .nb_max = I40E_MAX_RING_DESC,
2399 .nb_min = I40E_MIN_RING_DESC,
2400 .nb_align = I40E_ALIGN_RING_DESC,
2403 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2404 .nb_max = I40E_MAX_RING_DESC,
2405 .nb_min = I40E_MIN_RING_DESC,
2406 .nb_align = I40E_ALIGN_RING_DESC,
2409 if (pf->flags & I40E_FLAG_VMDQ) {
2410 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2411 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2412 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2413 pf->max_nb_vmdq_vsi;
2414 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2415 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2416 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2419 if (i40e_is_40G_device(hw->device_id))
2421 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2424 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2428 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2430 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2431 struct i40e_vsi *vsi = pf->main_vsi;
2432 PMD_INIT_FUNC_TRACE();
2435 return i40e_vsi_add_vlan(vsi, vlan_id);
2437 return i40e_vsi_delete_vlan(vsi, vlan_id);
2441 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2442 enum rte_vlan_type vlan_type,
2445 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2446 uint64_t reg_r = 0, reg_w = 0;
2447 uint16_t reg_id = 0;
2450 switch (vlan_type) {
2451 case ETH_VLAN_TYPE_OUTER:
2454 case ETH_VLAN_TYPE_INNER:
2459 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2462 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2464 if (ret != I40E_SUCCESS) {
2465 PMD_DRV_LOG(ERR, "Fail to debug read from "
2466 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2470 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2471 "0x%08"PRIx64"", reg_id, reg_r);
2473 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2474 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2475 if (reg_r == reg_w) {
2477 PMD_DRV_LOG(DEBUG, "No need to write");
2481 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2483 if (ret != I40E_SUCCESS) {
2485 PMD_DRV_LOG(ERR, "Fail to debug write to "
2486 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2489 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2490 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2496 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2498 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2499 struct i40e_vsi *vsi = pf->main_vsi;
2501 if (mask & ETH_VLAN_FILTER_MASK) {
2502 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2503 i40e_vsi_config_vlan_filter(vsi, TRUE);
2505 i40e_vsi_config_vlan_filter(vsi, FALSE);
2508 if (mask & ETH_VLAN_STRIP_MASK) {
2509 /* Enable or disable VLAN stripping */
2510 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2511 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2513 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2516 if (mask & ETH_VLAN_EXTEND_MASK) {
2517 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2518 i40e_vsi_config_double_vlan(vsi, TRUE);
2520 i40e_vsi_config_double_vlan(vsi, FALSE);
2525 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2526 __rte_unused uint16_t queue,
2527 __rte_unused int on)
2529 PMD_INIT_FUNC_TRACE();
2533 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2535 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2536 struct i40e_vsi *vsi = pf->main_vsi;
2537 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2538 struct i40e_vsi_vlan_pvid_info info;
2540 memset(&info, 0, sizeof(info));
2543 info.config.pvid = pvid;
2545 info.config.reject.tagged =
2546 data->dev_conf.txmode.hw_vlan_reject_tagged;
2547 info.config.reject.untagged =
2548 data->dev_conf.txmode.hw_vlan_reject_untagged;
2551 return i40e_vsi_vlan_pvid_set(vsi, &info);
2555 i40e_dev_led_on(struct rte_eth_dev *dev)
2557 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2558 uint32_t mode = i40e_led_get(hw);
2561 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2567 i40e_dev_led_off(struct rte_eth_dev *dev)
2569 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570 uint32_t mode = i40e_led_get(hw);
2573 i40e_led_set(hw, 0, false);
2579 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2581 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2582 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2584 fc_conf->pause_time = pf->fc_conf.pause_time;
2585 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2586 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2588 /* Return current mode according to actual setting*/
2589 switch (hw->fc.current_mode) {
2591 fc_conf->mode = RTE_FC_FULL;
2593 case I40E_FC_TX_PAUSE:
2594 fc_conf->mode = RTE_FC_TX_PAUSE;
2596 case I40E_FC_RX_PAUSE:
2597 fc_conf->mode = RTE_FC_RX_PAUSE;
2601 fc_conf->mode = RTE_FC_NONE;
2608 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2610 uint32_t mflcn_reg, fctrl_reg, reg;
2611 uint32_t max_high_water;
2612 uint8_t i, aq_failure;
2616 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2617 [RTE_FC_NONE] = I40E_FC_NONE,
2618 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2619 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2620 [RTE_FC_FULL] = I40E_FC_FULL
2623 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2625 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2626 if ((fc_conf->high_water > max_high_water) ||
2627 (fc_conf->high_water < fc_conf->low_water)) {
2628 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2629 "High_water must <= %d.", max_high_water);
2633 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2634 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2635 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2637 pf->fc_conf.pause_time = fc_conf->pause_time;
2638 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2639 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2641 PMD_INIT_FUNC_TRACE();
2643 /* All the link flow control related enable/disable register
2644 * configuration is handle by the F/W
2646 err = i40e_set_fc(hw, &aq_failure, true);
2650 if (i40e_is_40G_device(hw->device_id)) {
2651 /* Configure flow control refresh threshold,
2652 * the value for stat_tx_pause_refresh_timer[8]
2653 * is used for global pause operation.
2657 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2658 pf->fc_conf.pause_time);
2660 /* configure the timer value included in transmitted pause
2662 * the value for stat_tx_pause_quanta[8] is used for global
2665 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2666 pf->fc_conf.pause_time);
2668 fctrl_reg = I40E_READ_REG(hw,
2669 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2671 if (fc_conf->mac_ctrl_frame_fwd != 0)
2672 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2674 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2676 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2679 /* Configure pause time (2 TCs per register) */
2680 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2681 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2682 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2684 /* Configure flow control refresh threshold value */
2685 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2686 pf->fc_conf.pause_time / 2);
2688 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2690 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2691 *depending on configuration
2693 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2694 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2695 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2697 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2698 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2701 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2704 /* config the water marker both based on the packets and bytes */
2705 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2706 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2707 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2708 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2709 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2710 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2711 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2712 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2714 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2715 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2718 I40E_WRITE_FLUSH(hw);
2724 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2725 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2727 PMD_INIT_FUNC_TRACE();
2732 /* Add a MAC address, and update filters */
2734 i40e_macaddr_add(struct rte_eth_dev *dev,
2735 struct ether_addr *mac_addr,
2736 __rte_unused uint32_t index,
2739 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2740 struct i40e_mac_filter_info mac_filter;
2741 struct i40e_vsi *vsi;
2744 /* If VMDQ not enabled or configured, return */
2745 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2746 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2747 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2752 if (pool > pf->nb_cfg_vmdq_vsi) {
2753 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2754 pool, pf->nb_cfg_vmdq_vsi);
2758 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2759 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2760 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2762 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2767 vsi = pf->vmdq[pool - 1].vsi;
2769 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2770 if (ret != I40E_SUCCESS) {
2771 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2776 /* Remove a MAC address, and update filters */
2778 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2780 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2781 struct i40e_vsi *vsi;
2782 struct rte_eth_dev_data *data = dev->data;
2783 struct ether_addr *macaddr;
2788 macaddr = &(data->mac_addrs[index]);
2790 pool_sel = dev->data->mac_pool_sel[index];
2792 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2793 if (pool_sel & (1ULL << i)) {
2797 /* No VMDQ pool enabled or configured */
2798 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2799 (i > pf->nb_cfg_vmdq_vsi)) {
2800 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2804 vsi = pf->vmdq[i - 1].vsi;
2806 ret = i40e_vsi_delete_mac(vsi, macaddr);
2809 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2816 /* Set perfect match or hash match of MAC and VLAN for a VF */
2818 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2819 struct rte_eth_mac_filter *filter,
2823 struct i40e_mac_filter_info mac_filter;
2824 struct ether_addr old_mac;
2825 struct ether_addr *new_mac;
2826 struct i40e_pf_vf *vf = NULL;
2831 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2834 hw = I40E_PF_TO_HW(pf);
2836 if (filter == NULL) {
2837 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2841 new_mac = &filter->mac_addr;
2843 if (is_zero_ether_addr(new_mac)) {
2844 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2848 vf_id = filter->dst_id;
2850 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2851 PMD_DRV_LOG(ERR, "Invalid argument.");
2854 vf = &pf->vfs[vf_id];
2856 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2857 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2862 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2863 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2865 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2868 mac_filter.filter_type = filter->filter_type;
2869 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2870 if (ret != I40E_SUCCESS) {
2871 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2874 ether_addr_copy(new_mac, &pf->dev_addr);
2876 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2878 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2879 if (ret != I40E_SUCCESS) {
2880 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2884 /* Clear device address as it has been removed */
2885 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2886 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2892 /* MAC filter handle */
2894 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2897 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2898 struct rte_eth_mac_filter *filter;
2899 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2900 int ret = I40E_NOT_SUPPORTED;
2902 filter = (struct rte_eth_mac_filter *)(arg);
2904 switch (filter_op) {
2905 case RTE_ETH_FILTER_NOP:
2908 case RTE_ETH_FILTER_ADD:
2909 i40e_pf_disable_irq0(hw);
2911 ret = i40e_vf_mac_filter_set(pf, filter, 1);
2912 i40e_pf_enable_irq0(hw);
2914 case RTE_ETH_FILTER_DELETE:
2915 i40e_pf_disable_irq0(hw);
2917 ret = i40e_vf_mac_filter_set(pf, filter, 0);
2918 i40e_pf_enable_irq0(hw);
2921 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2922 ret = I40E_ERR_PARAM;
2930 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2932 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2933 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2939 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2940 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2943 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2947 uint32_t *lut_dw = (uint32_t *)lut;
2948 uint16_t i, lut_size_dw = lut_size / 4;
2950 for (i = 0; i < lut_size_dw; i++)
2951 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2958 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2960 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2961 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2967 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2968 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2971 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2975 uint32_t *lut_dw = (uint32_t *)lut;
2976 uint16_t i, lut_size_dw = lut_size / 4;
2978 for (i = 0; i < lut_size_dw; i++)
2979 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2980 I40E_WRITE_FLUSH(hw);
2987 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2988 struct rte_eth_rss_reta_entry64 *reta_conf,
2991 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2992 uint16_t i, lut_size = pf->hash_lut_size;
2993 uint16_t idx, shift;
2997 if (reta_size != lut_size ||
2998 reta_size > ETH_RSS_RETA_SIZE_512) {
2999 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3000 "(%d) doesn't match the number hardware can supported "
3001 "(%d)\n", reta_size, lut_size);
3005 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3007 PMD_DRV_LOG(ERR, "No memory can be allocated");
3010 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3013 for (i = 0; i < reta_size; i++) {
3014 idx = i / RTE_RETA_GROUP_SIZE;
3015 shift = i % RTE_RETA_GROUP_SIZE;
3016 if (reta_conf[idx].mask & (1ULL << shift))
3017 lut[i] = reta_conf[idx].reta[shift];
3019 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3028 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3029 struct rte_eth_rss_reta_entry64 *reta_conf,
3032 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3033 uint16_t i, lut_size = pf->hash_lut_size;
3034 uint16_t idx, shift;
3038 if (reta_size != lut_size ||
3039 reta_size > ETH_RSS_RETA_SIZE_512) {
3040 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3041 "(%d) doesn't match the number hardware can supported "
3042 "(%d)\n", reta_size, lut_size);
3046 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3048 PMD_DRV_LOG(ERR, "No memory can be allocated");
3052 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3055 for (i = 0; i < reta_size; i++) {
3056 idx = i / RTE_RETA_GROUP_SIZE;
3057 shift = i % RTE_RETA_GROUP_SIZE;
3058 if (reta_conf[idx].mask & (1ULL << shift))
3059 reta_conf[idx].reta[shift] = lut[i];
3069 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3070 * @hw: pointer to the HW structure
3071 * @mem: pointer to mem struct to fill out
3072 * @size: size of memory requested
3073 * @alignment: what to align the allocation to
3075 enum i40e_status_code
3076 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3077 struct i40e_dma_mem *mem,
3081 const struct rte_memzone *mz = NULL;
3082 char z_name[RTE_MEMZONE_NAMESIZE];
3085 return I40E_ERR_PARAM;
3087 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3088 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3089 alignment, RTE_PGSIZE_2M);
3091 return I40E_ERR_NO_MEMORY;
3095 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3096 mem->zone = (const void *)mz;
3097 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3098 "%"PRIu64, mz->name, mem->pa);
3100 return I40E_SUCCESS;
3104 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3105 * @hw: pointer to the HW structure
3106 * @mem: ptr to mem struct to free
3108 enum i40e_status_code
3109 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3110 struct i40e_dma_mem *mem)
3113 return I40E_ERR_PARAM;
3115 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3116 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3118 rte_memzone_free((const struct rte_memzone *)mem->zone);
3123 return I40E_SUCCESS;
3127 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3128 * @hw: pointer to the HW structure
3129 * @mem: pointer to mem struct to fill out
3130 * @size: size of memory requested
3132 enum i40e_status_code
3133 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3134 struct i40e_virt_mem *mem,
3138 return I40E_ERR_PARAM;
3141 mem->va = rte_zmalloc("i40e", size, 0);
3144 return I40E_SUCCESS;
3146 return I40E_ERR_NO_MEMORY;
3150 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3151 * @hw: pointer to the HW structure
3152 * @mem: pointer to mem struct to free
3154 enum i40e_status_code
3155 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3156 struct i40e_virt_mem *mem)
3159 return I40E_ERR_PARAM;
3164 return I40E_SUCCESS;
3168 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3170 rte_spinlock_init(&sp->spinlock);
3174 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3176 rte_spinlock_lock(&sp->spinlock);
3180 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3182 rte_spinlock_unlock(&sp->spinlock);
3186 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3192 * Get the hardware capabilities, which will be parsed
3193 * and saved into struct i40e_hw.
3196 i40e_get_cap(struct i40e_hw *hw)
3198 struct i40e_aqc_list_capabilities_element_resp *buf;
3199 uint16_t len, size = 0;
3202 /* Calculate a huge enough buff for saving response data temporarily */
3203 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3204 I40E_MAX_CAP_ELE_NUM;
3205 buf = rte_zmalloc("i40e", len, 0);
3207 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3208 return I40E_ERR_NO_MEMORY;
3211 /* Get, parse the capabilities and save it to hw */
3212 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3213 i40e_aqc_opc_list_func_capabilities, NULL);
3214 if (ret != I40E_SUCCESS)
3215 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3217 /* Free the temporary buffer after being used */
3224 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3226 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3227 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3228 uint16_t qp_count = 0, vsi_count = 0;
3230 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3231 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3234 /* Add the parameter init for LFC */
3235 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3236 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3237 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3239 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3240 pf->max_num_vsi = hw->func_caps.num_vsis;
3241 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3242 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3243 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3245 /* FDir queue/VSI allocation */
3246 pf->fdir_qp_offset = 0;
3247 if (hw->func_caps.fd) {
3248 pf->flags |= I40E_FLAG_FDIR;
3249 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3251 pf->fdir_nb_qps = 0;
3253 qp_count += pf->fdir_nb_qps;
3256 /* LAN queue/VSI allocation */
3257 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3258 if (!hw->func_caps.rss) {
3261 pf->flags |= I40E_FLAG_RSS;
3262 if (hw->mac.type == I40E_MAC_X722)
3263 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3264 pf->lan_nb_qps = pf->lan_nb_qp_max;
3266 qp_count += pf->lan_nb_qps;
3269 /* VF queue/VSI allocation */
3270 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3271 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3272 pf->flags |= I40E_FLAG_SRIOV;
3273 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3274 pf->vf_num = dev->pci_dev->max_vfs;
3275 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3276 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3277 pf->vf_nb_qps * pf->vf_num);
3282 qp_count += pf->vf_nb_qps * pf->vf_num;
3283 vsi_count += pf->vf_num;
3285 /* VMDq queue/VSI allocation */
3286 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3287 pf->vmdq_nb_qps = 0;
3288 pf->max_nb_vmdq_vsi = 0;
3289 if (hw->func_caps.vmdq) {
3290 if (qp_count < hw->func_caps.num_tx_qp &&
3291 vsi_count < hw->func_caps.num_vsis) {
3292 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3293 qp_count) / pf->vmdq_nb_qp_max;
3295 /* Limit the maximum number of VMDq vsi to the maximum
3296 * ethdev can support
3298 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3299 hw->func_caps.num_vsis - vsi_count);
3300 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3302 if (pf->max_nb_vmdq_vsi) {
3303 pf->flags |= I40E_FLAG_VMDQ;
3304 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3305 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3306 "per VMDQ VSI, in total %u queues",
3307 pf->max_nb_vmdq_vsi,
3308 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3309 pf->max_nb_vmdq_vsi);
3311 PMD_DRV_LOG(INFO, "No enough queues left for "
3315 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3318 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3319 vsi_count += pf->max_nb_vmdq_vsi;
3321 if (hw->func_caps.dcb)
3322 pf->flags |= I40E_FLAG_DCB;
3324 if (qp_count > hw->func_caps.num_tx_qp) {
3325 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3326 "the hardware maximum %u", qp_count,
3327 hw->func_caps.num_tx_qp);
3330 if (vsi_count > hw->func_caps.num_vsis) {
3331 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3332 "the hardware maximum %u", vsi_count,
3333 hw->func_caps.num_vsis);
3341 i40e_pf_get_switch_config(struct i40e_pf *pf)
3343 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3344 struct i40e_aqc_get_switch_config_resp *switch_config;
3345 struct i40e_aqc_switch_config_element_resp *element;
3346 uint16_t start_seid = 0, num_reported;
3349 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3350 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3351 if (!switch_config) {
3352 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3356 /* Get the switch configurations */
3357 ret = i40e_aq_get_switch_config(hw, switch_config,
3358 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3359 if (ret != I40E_SUCCESS) {
3360 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3363 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3364 if (num_reported != 1) { /* The number should be 1 */
3365 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3369 /* Parse the switch configuration elements */
3370 element = &(switch_config->element[0]);
3371 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3372 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3373 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3375 PMD_DRV_LOG(INFO, "Unknown element type");
3378 rte_free(switch_config);
3384 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3387 struct pool_entry *entry;
3389 if (pool == NULL || num == 0)
3392 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3393 if (entry == NULL) {
3394 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3398 /* queue heap initialize */
3399 pool->num_free = num;
3400 pool->num_alloc = 0;
3402 LIST_INIT(&pool->alloc_list);
3403 LIST_INIT(&pool->free_list);
3405 /* Initialize element */
3409 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3414 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3416 struct pool_entry *entry, *next_entry;
3421 for (entry = LIST_FIRST(&pool->alloc_list);
3422 entry && (next_entry = LIST_NEXT(entry, next), 1);
3423 entry = next_entry) {
3424 LIST_REMOVE(entry, next);
3428 for (entry = LIST_FIRST(&pool->free_list);
3429 entry && (next_entry = LIST_NEXT(entry, next), 1);
3430 entry = next_entry) {
3431 LIST_REMOVE(entry, next);
3436 pool->num_alloc = 0;
3438 LIST_INIT(&pool->alloc_list);
3439 LIST_INIT(&pool->free_list);
3443 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3446 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3447 uint32_t pool_offset;
3451 PMD_DRV_LOG(ERR, "Invalid parameter");
3455 pool_offset = base - pool->base;
3456 /* Lookup in alloc list */
3457 LIST_FOREACH(entry, &pool->alloc_list, next) {
3458 if (entry->base == pool_offset) {
3459 valid_entry = entry;
3460 LIST_REMOVE(entry, next);
3465 /* Not find, return */
3466 if (valid_entry == NULL) {
3467 PMD_DRV_LOG(ERR, "Failed to find entry");
3472 * Found it, move it to free list and try to merge.
3473 * In order to make merge easier, always sort it by qbase.
3474 * Find adjacent prev and last entries.
3477 LIST_FOREACH(entry, &pool->free_list, next) {
3478 if (entry->base > valid_entry->base) {
3486 /* Try to merge with next one*/
3488 /* Merge with next one */
3489 if (valid_entry->base + valid_entry->len == next->base) {
3490 next->base = valid_entry->base;
3491 next->len += valid_entry->len;
3492 rte_free(valid_entry);
3499 /* Merge with previous one */
3500 if (prev->base + prev->len == valid_entry->base) {
3501 prev->len += valid_entry->len;
3502 /* If it merge with next one, remove next node */
3504 LIST_REMOVE(valid_entry, next);
3505 rte_free(valid_entry);
3507 rte_free(valid_entry);
3513 /* Not find any entry to merge, insert */
3516 LIST_INSERT_AFTER(prev, valid_entry, next);
3517 else if (next != NULL)
3518 LIST_INSERT_BEFORE(next, valid_entry, next);
3519 else /* It's empty list, insert to head */
3520 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3523 pool->num_free += valid_entry->len;
3524 pool->num_alloc -= valid_entry->len;
3530 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3533 struct pool_entry *entry, *valid_entry;
3535 if (pool == NULL || num == 0) {
3536 PMD_DRV_LOG(ERR, "Invalid parameter");
3540 if (pool->num_free < num) {
3541 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3542 num, pool->num_free);
3547 /* Lookup in free list and find most fit one */
3548 LIST_FOREACH(entry, &pool->free_list, next) {
3549 if (entry->len >= num) {
3551 if (entry->len == num) {
3552 valid_entry = entry;
3555 if (valid_entry == NULL || valid_entry->len > entry->len)
3556 valid_entry = entry;
3560 /* Not find one to satisfy the request, return */
3561 if (valid_entry == NULL) {
3562 PMD_DRV_LOG(ERR, "No valid entry found");
3566 * The entry have equal queue number as requested,
3567 * remove it from alloc_list.
3569 if (valid_entry->len == num) {
3570 LIST_REMOVE(valid_entry, next);
3573 * The entry have more numbers than requested,
3574 * create a new entry for alloc_list and minus its
3575 * queue base and number in free_list.
3577 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3578 if (entry == NULL) {
3579 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3583 entry->base = valid_entry->base;
3585 valid_entry->base += num;
3586 valid_entry->len -= num;
3587 valid_entry = entry;
3590 /* Insert it into alloc list, not sorted */
3591 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3593 pool->num_free -= valid_entry->len;
3594 pool->num_alloc += valid_entry->len;
3596 return valid_entry->base + pool->base;
3600 * bitmap_is_subset - Check whether src2 is subset of src1
3603 bitmap_is_subset(uint8_t src1, uint8_t src2)
3605 return !((src1 ^ src2) & src2);
3608 static enum i40e_status_code
3609 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3611 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3613 /* If DCB is not supported, only default TC is supported */
3614 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3615 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3616 return I40E_NOT_SUPPORTED;
3619 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3620 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3621 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3623 return I40E_NOT_SUPPORTED;
3625 return I40E_SUCCESS;
3629 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3630 struct i40e_vsi_vlan_pvid_info *info)
3633 struct i40e_vsi_context ctxt;
3634 uint8_t vlan_flags = 0;
3637 if (vsi == NULL || info == NULL) {
3638 PMD_DRV_LOG(ERR, "invalid parameters");
3639 return I40E_ERR_PARAM;
3643 vsi->info.pvid = info->config.pvid;
3645 * If insert pvid is enabled, only tagged pkts are
3646 * allowed to be sent out.
3648 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3649 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3652 if (info->config.reject.tagged == 0)
3653 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3655 if (info->config.reject.untagged == 0)
3656 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3658 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3659 I40E_AQ_VSI_PVLAN_MODE_MASK);
3660 vsi->info.port_vlan_flags |= vlan_flags;
3661 vsi->info.valid_sections =
3662 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3663 memset(&ctxt, 0, sizeof(ctxt));
3664 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3665 ctxt.seid = vsi->seid;
3667 hw = I40E_VSI_TO_HW(vsi);
3668 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3669 if (ret != I40E_SUCCESS)
3670 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3676 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3678 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3680 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3682 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3683 if (ret != I40E_SUCCESS)
3687 PMD_DRV_LOG(ERR, "seid not valid");
3691 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3692 tc_bw_data.tc_valid_bits = enabled_tcmap;
3693 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3694 tc_bw_data.tc_bw_credits[i] =
3695 (enabled_tcmap & (1 << i)) ? 1 : 0;
3697 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3698 if (ret != I40E_SUCCESS) {
3699 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3703 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3704 sizeof(vsi->info.qs_handle));
3705 return I40E_SUCCESS;
3708 static enum i40e_status_code
3709 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3710 struct i40e_aqc_vsi_properties_data *info,
3711 uint8_t enabled_tcmap)
3713 enum i40e_status_code ret;
3714 int i, total_tc = 0;
3715 uint16_t qpnum_per_tc, bsf, qp_idx;
3717 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3718 if (ret != I40E_SUCCESS)
3721 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3722 if (enabled_tcmap & (1 << i))
3724 vsi->enabled_tc = enabled_tcmap;
3726 /* Number of queues per enabled TC */
3727 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3728 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3729 bsf = rte_bsf32(qpnum_per_tc);
3731 /* Adjust the queue number to actual queues that can be applied */
3732 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3733 vsi->nb_qps = qpnum_per_tc * total_tc;
3736 * Configure TC and queue mapping parameters, for enabled TC,
3737 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3738 * default queue will serve it.
3741 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3742 if (vsi->enabled_tc & (1 << i)) {
3743 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3744 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3745 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3746 qp_idx += qpnum_per_tc;
3748 info->tc_mapping[i] = 0;
3751 /* Associate queue number with VSI */
3752 if (vsi->type == I40E_VSI_SRIOV) {
3753 info->mapping_flags |=
3754 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3755 for (i = 0; i < vsi->nb_qps; i++)
3756 info->queue_mapping[i] =
3757 rte_cpu_to_le_16(vsi->base_queue + i);
3759 info->mapping_flags |=
3760 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3761 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3763 info->valid_sections |=
3764 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3766 return I40E_SUCCESS;
3770 i40e_veb_release(struct i40e_veb *veb)
3772 struct i40e_vsi *vsi;
3775 if (veb == NULL || veb->associate_vsi == NULL)
3778 if (!TAILQ_EMPTY(&veb->head)) {
3779 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3783 vsi = veb->associate_vsi;
3784 hw = I40E_VSI_TO_HW(vsi);
3786 vsi->uplink_seid = veb->uplink_seid;
3787 i40e_aq_delete_element(hw, veb->seid, NULL);
3790 return I40E_SUCCESS;
3794 static struct i40e_veb *
3795 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3797 struct i40e_veb *veb;
3801 if (NULL == pf || vsi == NULL) {
3802 PMD_DRV_LOG(ERR, "veb setup failed, "
3803 "associated VSI shouldn't null");
3806 hw = I40E_PF_TO_HW(pf);
3808 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3810 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3814 veb->associate_vsi = vsi;
3815 TAILQ_INIT(&veb->head);
3816 veb->uplink_seid = vsi->uplink_seid;
3818 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3819 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3821 if (ret != I40E_SUCCESS) {
3822 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3823 hw->aq.asq_last_status);
3827 /* get statistics index */
3828 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3829 &veb->stats_idx, NULL, NULL, NULL);
3830 if (ret != I40E_SUCCESS) {
3831 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3832 hw->aq.asq_last_status);
3836 /* Get VEB bandwidth, to be implemented */
3837 /* Now associated vsi binding to the VEB, set uplink to this VEB */
3838 vsi->uplink_seid = veb->seid;
3847 i40e_vsi_release(struct i40e_vsi *vsi)
3851 struct i40e_vsi_list *vsi_list;
3853 struct i40e_mac_filter *f;
3856 return I40E_SUCCESS;
3858 pf = I40E_VSI_TO_PF(vsi);
3859 hw = I40E_VSI_TO_HW(vsi);
3861 /* VSI has child to attach, release child first */
3863 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3864 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3866 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3868 i40e_veb_release(vsi->veb);
3871 /* Remove all macvlan filters of the VSI */
3872 i40e_vsi_remove_all_macvlan_filter(vsi);
3873 TAILQ_FOREACH(f, &vsi->mac_list, next)
3876 if (vsi->type != I40E_VSI_MAIN) {
3877 /* Remove vsi from parent's sibling list */
3878 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3879 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3880 return I40E_ERR_PARAM;
3882 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3883 &vsi->sib_vsi_list, list);
3885 /* Remove all switch element of the VSI */
3886 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3887 if (ret != I40E_SUCCESS)
3888 PMD_DRV_LOG(ERR, "Failed to delete element");
3890 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3892 if (vsi->type != I40E_VSI_SRIOV)
3893 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3896 return I40E_SUCCESS;
3900 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3902 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3903 struct i40e_aqc_remove_macvlan_element_data def_filter;
3904 struct i40e_mac_filter_info filter;
3907 if (vsi->type != I40E_VSI_MAIN)
3908 return I40E_ERR_CONFIG;
3909 memset(&def_filter, 0, sizeof(def_filter));
3910 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3912 def_filter.vlan_tag = 0;
3913 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3914 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3915 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3916 if (ret != I40E_SUCCESS) {
3917 struct i40e_mac_filter *f;
3918 struct ether_addr *mac;
3920 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3922 /* It needs to add the permanent mac into mac list */
3923 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3925 PMD_DRV_LOG(ERR, "failed to allocate memory");
3926 return I40E_ERR_NO_MEMORY;
3928 mac = &f->mac_info.mac_addr;
3929 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3931 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3932 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3937 (void)rte_memcpy(&filter.mac_addr,
3938 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3939 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3940 return i40e_vsi_add_mac(vsi, &filter);
3944 * i40e_vsi_get_bw_config - Query VSI BW Information
3945 * @vsi: the VSI to be queried
3947 * Returns 0 on success, negative value on failure
3949 static enum i40e_status_code
3950 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3952 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3953 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3954 struct i40e_hw *hw = &vsi->adapter->hw;
3959 memset(&bw_config, 0, sizeof(bw_config));
3960 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3961 if (ret != I40E_SUCCESS) {
3962 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3963 hw->aq.asq_last_status);
3967 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3968 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3969 &ets_sla_config, NULL);
3970 if (ret != I40E_SUCCESS) {
3971 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3972 "configuration %u", hw->aq.asq_last_status);
3976 /* store and print out BW info */
3977 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3978 vsi->bw_info.bw_max = bw_config.max_bw;
3979 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3980 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3981 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3982 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3984 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3985 vsi->bw_info.bw_ets_share_credits[i] =
3986 ets_sla_config.share_credits[i];
3987 vsi->bw_info.bw_ets_credits[i] =
3988 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3989 /* 4 bits per TC, 4th bit is reserved */
3990 vsi->bw_info.bw_ets_max[i] =
3991 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3992 RTE_LEN2MASK(3, uint8_t));
3993 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3994 vsi->bw_info.bw_ets_share_credits[i]);
3995 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3996 vsi->bw_info.bw_ets_credits[i]);
3997 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3998 vsi->bw_info.bw_ets_max[i]);
4001 return I40E_SUCCESS;
4004 /* i40e_enable_pf_lb
4005 * @pf: pointer to the pf structure
4007 * allow loopback on pf
4010 i40e_enable_pf_lb(struct i40e_pf *pf)
4012 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4013 struct i40e_vsi_context ctxt;
4016 /* Use the FW API if FW >= v5.0 */
4017 if (hw->aq.fw_maj_ver < 5) {
4018 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4022 memset(&ctxt, 0, sizeof(ctxt));
4023 ctxt.seid = pf->main_vsi_seid;
4024 ctxt.pf_num = hw->pf_id;
4025 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4027 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4028 ret, hw->aq.asq_last_status);
4031 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4032 ctxt.info.valid_sections =
4033 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4034 ctxt.info.switch_id |=
4035 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4037 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4039 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4040 hw->aq.asq_last_status);
4045 i40e_vsi_setup(struct i40e_pf *pf,
4046 enum i40e_vsi_type type,
4047 struct i40e_vsi *uplink_vsi,
4048 uint16_t user_param)
4050 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4051 struct i40e_vsi *vsi;
4052 struct i40e_mac_filter_info filter;
4054 struct i40e_vsi_context ctxt;
4055 struct ether_addr broadcast =
4056 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4058 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
4059 PMD_DRV_LOG(ERR, "VSI setup failed, "
4060 "VSI link shouldn't be NULL");
4064 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4065 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4066 "uplink VSI should be NULL");
4070 /* If uplink vsi didn't setup VEB, create one first */
4071 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
4072 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4074 if (NULL == uplink_vsi->veb) {
4075 PMD_DRV_LOG(ERR, "VEB setup failed");
4078 /* set ALLOWLOOPBACk on pf, when veb is created */
4079 i40e_enable_pf_lb(pf);
4082 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4084 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4087 TAILQ_INIT(&vsi->mac_list);
4089 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4090 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4091 vsi->parent_vsi = uplink_vsi;
4092 vsi->user_param = user_param;
4093 /* Allocate queues */
4094 switch (vsi->type) {
4095 case I40E_VSI_MAIN :
4096 vsi->nb_qps = pf->lan_nb_qps;
4098 case I40E_VSI_SRIOV :
4099 vsi->nb_qps = pf->vf_nb_qps;
4101 case I40E_VSI_VMDQ2:
4102 vsi->nb_qps = pf->vmdq_nb_qps;
4105 vsi->nb_qps = pf->fdir_nb_qps;
4111 * The filter status descriptor is reported in rx queue 0,
4112 * while the tx queue for fdir filter programming has no
4113 * such constraints, can be non-zero queues.
4114 * To simplify it, choose FDIR vsi use queue 0 pair.
4115 * To make sure it will use queue 0 pair, queue allocation
4116 * need be done before this function is called
4118 if (type != I40E_VSI_FDIR) {
4119 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4121 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4125 vsi->base_queue = ret;
4127 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4129 /* VF has MSIX interrupt in VF range, don't allocate here */
4130 if (type == I40E_VSI_MAIN) {
4131 ret = i40e_res_pool_alloc(&pf->msix_pool,
4132 RTE_MIN(vsi->nb_qps,
4133 RTE_MAX_RXTX_INTR_VEC_ID));
4135 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4137 goto fail_queue_alloc;
4139 vsi->msix_intr = ret;
4140 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4141 } else if (type != I40E_VSI_SRIOV) {
4142 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4144 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4145 goto fail_queue_alloc;
4147 vsi->msix_intr = ret;
4155 if (type == I40E_VSI_MAIN) {
4156 /* For main VSI, no need to add since it's default one */
4157 vsi->uplink_seid = pf->mac_seid;
4158 vsi->seid = pf->main_vsi_seid;
4159 /* Bind queues with specific MSIX interrupt */
4161 * Needs 2 interrupt at least, one for misc cause which will
4162 * enabled from OS side, Another for queues binding the
4163 * interrupt from device side only.
4166 /* Get default VSI parameters from hardware */
4167 memset(&ctxt, 0, sizeof(ctxt));
4168 ctxt.seid = vsi->seid;
4169 ctxt.pf_num = hw->pf_id;
4170 ctxt.uplink_seid = vsi->uplink_seid;
4172 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4173 if (ret != I40E_SUCCESS) {
4174 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4175 goto fail_msix_alloc;
4177 (void)rte_memcpy(&vsi->info, &ctxt.info,
4178 sizeof(struct i40e_aqc_vsi_properties_data));
4179 vsi->vsi_id = ctxt.vsi_number;
4180 vsi->info.valid_sections = 0;
4182 /* Configure tc, enabled TC0 only */
4183 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4185 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4186 goto fail_msix_alloc;
4189 /* TC, queue mapping */
4190 memset(&ctxt, 0, sizeof(ctxt));
4191 vsi->info.valid_sections |=
4192 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4193 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4194 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4195 (void)rte_memcpy(&ctxt.info, &vsi->info,
4196 sizeof(struct i40e_aqc_vsi_properties_data));
4197 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4198 I40E_DEFAULT_TCMAP);
4199 if (ret != I40E_SUCCESS) {
4200 PMD_DRV_LOG(ERR, "Failed to configure "
4201 "TC queue mapping");
4202 goto fail_msix_alloc;
4204 ctxt.seid = vsi->seid;
4205 ctxt.pf_num = hw->pf_id;
4206 ctxt.uplink_seid = vsi->uplink_seid;
4209 /* Update VSI parameters */
4210 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4211 if (ret != I40E_SUCCESS) {
4212 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4213 goto fail_msix_alloc;
4216 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4217 sizeof(vsi->info.tc_mapping));
4218 (void)rte_memcpy(&vsi->info.queue_mapping,
4219 &ctxt.info.queue_mapping,
4220 sizeof(vsi->info.queue_mapping));
4221 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4222 vsi->info.valid_sections = 0;
4224 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4228 * Updating default filter settings are necessary to prevent
4229 * reception of tagged packets.
4230 * Some old firmware configurations load a default macvlan
4231 * filter which accepts both tagged and untagged packets.
4232 * The updating is to use a normal filter instead if needed.
4233 * For NVM 4.2.2 or after, the updating is not needed anymore.
4234 * The firmware with correct configurations load the default
4235 * macvlan filter which is expected and cannot be removed.
4237 i40e_update_default_filter_setting(vsi);
4238 i40e_config_qinq(hw, vsi);
4239 } else if (type == I40E_VSI_SRIOV) {
4240 memset(&ctxt, 0, sizeof(ctxt));
4242 * For other VSI, the uplink_seid equals to uplink VSI's
4243 * uplink_seid since they share same VEB
4245 vsi->uplink_seid = uplink_vsi->uplink_seid;
4246 ctxt.pf_num = hw->pf_id;
4247 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4248 ctxt.uplink_seid = vsi->uplink_seid;
4249 ctxt.connection_type = 0x1;
4250 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4252 /* Use the VEB configuration if FW >= v5.0 */
4253 if (hw->aq.fw_maj_ver >= 5) {
4254 /* Configure switch ID */
4255 ctxt.info.valid_sections |=
4256 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4257 ctxt.info.switch_id =
4258 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4261 /* Configure port/vlan */
4262 ctxt.info.valid_sections |=
4263 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4264 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4265 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4266 I40E_DEFAULT_TCMAP);
4267 if (ret != I40E_SUCCESS) {
4268 PMD_DRV_LOG(ERR, "Failed to configure "
4269 "TC queue mapping");
4270 goto fail_msix_alloc;
4272 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4273 ctxt.info.valid_sections |=
4274 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4276 * Since VSI is not created yet, only configure parameter,
4277 * will add vsi below.
4280 i40e_config_qinq(hw, vsi);
4281 } else if (type == I40E_VSI_VMDQ2) {
4282 memset(&ctxt, 0, sizeof(ctxt));
4284 * For other VSI, the uplink_seid equals to uplink VSI's
4285 * uplink_seid since they share same VEB
4287 vsi->uplink_seid = uplink_vsi->uplink_seid;
4288 ctxt.pf_num = hw->pf_id;
4290 ctxt.uplink_seid = vsi->uplink_seid;
4291 ctxt.connection_type = 0x1;
4292 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4294 ctxt.info.valid_sections |=
4295 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4296 /* user_param carries flag to enable loop back */
4298 ctxt.info.switch_id =
4299 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4300 ctxt.info.switch_id |=
4301 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4304 /* Configure port/vlan */
4305 ctxt.info.valid_sections |=
4306 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4307 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4308 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4309 I40E_DEFAULT_TCMAP);
4310 if (ret != I40E_SUCCESS) {
4311 PMD_DRV_LOG(ERR, "Failed to configure "
4312 "TC queue mapping");
4313 goto fail_msix_alloc;
4315 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4316 ctxt.info.valid_sections |=
4317 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4318 } else if (type == I40E_VSI_FDIR) {
4319 memset(&ctxt, 0, sizeof(ctxt));
4320 vsi->uplink_seid = uplink_vsi->uplink_seid;
4321 ctxt.pf_num = hw->pf_id;
4323 ctxt.uplink_seid = vsi->uplink_seid;
4324 ctxt.connection_type = 0x1; /* regular data port */
4325 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4326 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4327 I40E_DEFAULT_TCMAP);
4328 if (ret != I40E_SUCCESS) {
4329 PMD_DRV_LOG(ERR, "Failed to configure "
4330 "TC queue mapping.");
4331 goto fail_msix_alloc;
4333 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4334 ctxt.info.valid_sections |=
4335 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4337 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4338 goto fail_msix_alloc;
4341 if (vsi->type != I40E_VSI_MAIN) {
4342 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4343 if (ret != I40E_SUCCESS) {
4344 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4345 hw->aq.asq_last_status);
4346 goto fail_msix_alloc;
4348 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4349 vsi->info.valid_sections = 0;
4350 vsi->seid = ctxt.seid;
4351 vsi->vsi_id = ctxt.vsi_number;
4352 vsi->sib_vsi_list.vsi = vsi;
4353 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4354 &vsi->sib_vsi_list, list);
4357 /* MAC/VLAN configuration */
4358 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4359 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4361 ret = i40e_vsi_add_mac(vsi, &filter);
4362 if (ret != I40E_SUCCESS) {
4363 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4364 goto fail_msix_alloc;
4367 /* Get VSI BW information */
4368 i40e_vsi_get_bw_config(vsi);
4371 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4373 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4379 /* Configure vlan filter on or off */
4381 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4384 struct i40e_mac_filter *f;
4385 struct i40e_mac_filter_info *mac_filter;
4386 enum rte_mac_filter_type desired_filter;
4387 int ret = I40E_SUCCESS;
4390 /* Filter to match MAC and VLAN */
4391 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4393 /* Filter to match only MAC */
4394 desired_filter = RTE_MAC_PERFECT_MATCH;
4399 mac_filter = rte_zmalloc("mac_filter_info_data",
4400 num * sizeof(*mac_filter), 0);
4401 if (mac_filter == NULL) {
4402 PMD_DRV_LOG(ERR, "failed to allocate memory");
4403 return I40E_ERR_NO_MEMORY;
4408 /* Remove all existing mac */
4409 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4410 mac_filter[i] = f->mac_info;
4411 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4413 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4414 on ? "enable" : "disable");
4420 /* Override with new filter */
4421 for (i = 0; i < num; i++) {
4422 mac_filter[i].filter_type = desired_filter;
4423 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4425 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4426 on ? "enable" : "disable");
4432 rte_free(mac_filter);
4436 /* Configure vlan stripping on or off */
4438 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4440 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4441 struct i40e_vsi_context ctxt;
4443 int ret = I40E_SUCCESS;
4445 /* Check if it has been already on or off */
4446 if (vsi->info.valid_sections &
4447 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4449 if ((vsi->info.port_vlan_flags &
4450 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4451 return 0; /* already on */
4453 if ((vsi->info.port_vlan_flags &
4454 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4455 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4456 return 0; /* already off */
4461 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4463 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4464 vsi->info.valid_sections =
4465 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4466 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4467 vsi->info.port_vlan_flags |= vlan_flags;
4468 ctxt.seid = vsi->seid;
4469 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4470 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4472 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4473 on ? "enable" : "disable");
4479 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4481 struct rte_eth_dev_data *data = dev->data;
4485 /* Apply vlan offload setting */
4486 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4487 i40e_vlan_offload_set(dev, mask);
4489 /* Apply double-vlan setting, not implemented yet */
4491 /* Apply pvid setting */
4492 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4493 data->dev_conf.txmode.hw_vlan_insert_pvid);
4495 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4501 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4503 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4505 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4509 i40e_update_flow_control(struct i40e_hw *hw)
4511 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4512 struct i40e_link_status link_status;
4513 uint32_t rxfc = 0, txfc = 0, reg;
4517 memset(&link_status, 0, sizeof(link_status));
4518 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4519 if (ret != I40E_SUCCESS) {
4520 PMD_DRV_LOG(ERR, "Failed to get link status information");
4521 goto write_reg; /* Disable flow control */
4524 an_info = hw->phy.link_info.an_info;
4525 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4526 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4527 ret = I40E_ERR_NOT_READY;
4528 goto write_reg; /* Disable flow control */
4531 * If link auto negotiation is enabled, flow control needs to
4532 * be configured according to it
4534 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4535 case I40E_LINK_PAUSE_RXTX:
4538 hw->fc.current_mode = I40E_FC_FULL;
4540 case I40E_AQ_LINK_PAUSE_RX:
4542 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4544 case I40E_AQ_LINK_PAUSE_TX:
4546 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4549 hw->fc.current_mode = I40E_FC_NONE;
4554 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4555 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4556 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4557 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4558 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4559 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4566 i40e_pf_setup(struct i40e_pf *pf)
4568 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4569 struct i40e_filter_control_settings settings;
4570 struct i40e_vsi *vsi;
4573 /* Clear all stats counters */
4574 pf->offset_loaded = FALSE;
4575 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4576 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4578 ret = i40e_pf_get_switch_config(pf);
4579 if (ret != I40E_SUCCESS) {
4580 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4583 if (pf->flags & I40E_FLAG_FDIR) {
4584 /* make queue allocated first, let FDIR use queue pair 0*/
4585 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4586 if (ret != I40E_FDIR_QUEUE_ID) {
4587 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4589 pf->flags &= ~I40E_FLAG_FDIR;
4592 /* main VSI setup */
4593 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4595 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4596 return I40E_ERR_NOT_READY;
4600 /* Configure filter control */
4601 memset(&settings, 0, sizeof(settings));
4602 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4603 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4604 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4605 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4607 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4608 hw->func_caps.rss_table_size);
4609 return I40E_ERR_PARAM;
4611 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4612 "size: %u\n", hw->func_caps.rss_table_size);
4613 pf->hash_lut_size = hw->func_caps.rss_table_size;
4615 /* Enable ethtype and macvlan filters */
4616 settings.enable_ethtype = TRUE;
4617 settings.enable_macvlan = TRUE;
4618 ret = i40e_set_filter_control(hw, &settings);
4620 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4623 /* Update flow control according to the auto negotiation */
4624 i40e_update_flow_control(hw);
4626 return I40E_SUCCESS;
4630 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4636 * Set or clear TX Queue Disable flags,
4637 * which is required by hardware.
4639 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4640 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4642 /* Wait until the request is finished */
4643 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4644 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4645 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4646 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4647 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4653 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4654 return I40E_SUCCESS; /* already on, skip next steps */
4656 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4657 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4659 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4660 return I40E_SUCCESS; /* already off, skip next steps */
4661 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4663 /* Write the register */
4664 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4665 /* Check the result */
4666 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4667 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4668 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4670 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4671 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4674 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4675 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4679 /* Check if it is timeout */
4680 if (j >= I40E_CHK_Q_ENA_COUNT) {
4681 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4682 (on ? "enable" : "disable"), q_idx);
4683 return I40E_ERR_TIMEOUT;
4686 return I40E_SUCCESS;
4689 /* Swith on or off the tx queues */
4691 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4693 struct rte_eth_dev_data *dev_data = pf->dev_data;
4694 struct i40e_tx_queue *txq;
4695 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4699 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4700 txq = dev_data->tx_queues[i];
4701 /* Don't operate the queue if not configured or
4702 * if starting only per queue */
4703 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4706 ret = i40e_dev_tx_queue_start(dev, i);
4708 ret = i40e_dev_tx_queue_stop(dev, i);
4709 if ( ret != I40E_SUCCESS)
4713 return I40E_SUCCESS;
4717 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4722 /* Wait until the request is finished */
4723 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4724 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4725 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4726 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4727 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4732 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4733 return I40E_SUCCESS; /* Already on, skip next steps */
4734 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4736 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4737 return I40E_SUCCESS; /* Already off, skip next steps */
4738 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4741 /* Write the register */
4742 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4743 /* Check the result */
4744 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4745 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4746 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4748 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4749 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4752 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4753 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4758 /* Check if it is timeout */
4759 if (j >= I40E_CHK_Q_ENA_COUNT) {
4760 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4761 (on ? "enable" : "disable"), q_idx);
4762 return I40E_ERR_TIMEOUT;
4765 return I40E_SUCCESS;
4767 /* Switch on or off the rx queues */
4769 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4771 struct rte_eth_dev_data *dev_data = pf->dev_data;
4772 struct i40e_rx_queue *rxq;
4773 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4777 for (i = 0; i < dev_data->nb_rx_queues; i++) {
4778 rxq = dev_data->rx_queues[i];
4779 /* Don't operate the queue if not configured or
4780 * if starting only per queue */
4781 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4784 ret = i40e_dev_rx_queue_start(dev, i);
4786 ret = i40e_dev_rx_queue_stop(dev, i);
4787 if (ret != I40E_SUCCESS)
4791 return I40E_SUCCESS;
4794 /* Switch on or off all the rx/tx queues */
4796 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4801 /* enable rx queues before enabling tx queues */
4802 ret = i40e_dev_switch_rx_queues(pf, on);
4804 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4807 ret = i40e_dev_switch_tx_queues(pf, on);
4809 /* Stop tx queues before stopping rx queues */
4810 ret = i40e_dev_switch_tx_queues(pf, on);
4812 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4815 ret = i40e_dev_switch_rx_queues(pf, on);
4821 /* Initialize VSI for TX */
4823 i40e_dev_tx_init(struct i40e_pf *pf)
4825 struct rte_eth_dev_data *data = pf->dev_data;
4827 uint32_t ret = I40E_SUCCESS;
4828 struct i40e_tx_queue *txq;
4830 for (i = 0; i < data->nb_tx_queues; i++) {
4831 txq = data->tx_queues[i];
4832 if (!txq || !txq->q_set)
4834 ret = i40e_tx_queue_init(txq);
4835 if (ret != I40E_SUCCESS)
4838 if (ret == I40E_SUCCESS)
4839 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4845 /* Initialize VSI for RX */
4847 i40e_dev_rx_init(struct i40e_pf *pf)
4849 struct rte_eth_dev_data *data = pf->dev_data;
4850 int ret = I40E_SUCCESS;
4852 struct i40e_rx_queue *rxq;
4854 i40e_pf_config_mq_rx(pf);
4855 for (i = 0; i < data->nb_rx_queues; i++) {
4856 rxq = data->rx_queues[i];
4857 if (!rxq || !rxq->q_set)
4860 ret = i40e_rx_queue_init(rxq);
4861 if (ret != I40E_SUCCESS) {
4862 PMD_DRV_LOG(ERR, "Failed to do RX queue "
4867 if (ret == I40E_SUCCESS)
4868 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4875 i40e_dev_rxtx_init(struct i40e_pf *pf)
4879 err = i40e_dev_tx_init(pf);
4881 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4884 err = i40e_dev_rx_init(pf);
4886 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4894 i40e_vmdq_setup(struct rte_eth_dev *dev)
4896 struct rte_eth_conf *conf = &dev->data->dev_conf;
4897 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4898 int i, err, conf_vsis, j, loop;
4899 struct i40e_vsi *vsi;
4900 struct i40e_vmdq_info *vmdq_info;
4901 struct rte_eth_vmdq_rx_conf *vmdq_conf;
4902 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4905 * Disable interrupt to avoid message from VF. Furthermore, it will
4906 * avoid race condition in VSI creation/destroy.
4908 i40e_pf_disable_irq0(hw);
4910 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4911 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4915 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4916 if (conf_vsis > pf->max_nb_vmdq_vsi) {
4917 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4918 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4919 pf->max_nb_vmdq_vsi);
4923 if (pf->vmdq != NULL) {
4924 PMD_INIT_LOG(INFO, "VMDQ already configured");
4928 pf->vmdq = rte_zmalloc("vmdq_info_struct",
4929 sizeof(*vmdq_info) * conf_vsis, 0);
4931 if (pf->vmdq == NULL) {
4932 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4936 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4938 /* Create VMDQ VSI */
4939 for (i = 0; i < conf_vsis; i++) {
4940 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4941 vmdq_conf->enable_loop_back);
4943 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4947 vmdq_info = &pf->vmdq[i];
4949 vmdq_info->vsi = vsi;
4951 pf->nb_cfg_vmdq_vsi = conf_vsis;
4953 /* Configure Vlan */
4954 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4955 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4956 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4957 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4958 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4959 vmdq_conf->pool_map[i].vlan_id, j);
4961 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4962 vmdq_conf->pool_map[i].vlan_id);
4964 PMD_INIT_LOG(ERR, "Failed to add vlan");
4972 i40e_pf_enable_irq0(hw);
4977 for (i = 0; i < conf_vsis; i++)
4978 if (pf->vmdq[i].vsi == NULL)
4981 i40e_vsi_release(pf->vmdq[i].vsi);
4985 i40e_pf_enable_irq0(hw);
4990 i40e_stat_update_32(struct i40e_hw *hw,
4998 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5002 if (new_data >= *offset)
5003 *stat = (uint64_t)(new_data - *offset);
5005 *stat = (uint64_t)((new_data +
5006 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5010 i40e_stat_update_48(struct i40e_hw *hw,
5019 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5020 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5021 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5026 if (new_data >= *offset)
5027 *stat = new_data - *offset;
5029 *stat = (uint64_t)((new_data +
5030 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5032 *stat &= I40E_48_BIT_MASK;
5037 i40e_pf_disable_irq0(struct i40e_hw *hw)
5039 /* Disable all interrupt types */
5040 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5041 I40E_WRITE_FLUSH(hw);
5046 i40e_pf_enable_irq0(struct i40e_hw *hw)
5048 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5049 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5050 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5051 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5052 I40E_WRITE_FLUSH(hw);
5056 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5058 /* read pending request and disable first */
5059 i40e_pf_disable_irq0(hw);
5060 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5061 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5062 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5065 /* Link no queues with irq0 */
5066 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5067 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5071 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5073 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5074 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5077 uint32_t index, offset, val;
5082 * Try to find which VF trigger a reset, use absolute VF id to access
5083 * since the reg is global register.
5085 for (i = 0; i < pf->vf_num; i++) {
5086 abs_vf_id = hw->func_caps.vf_base_id + i;
5087 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5088 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5089 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5090 /* VFR event occured */
5091 if (val & (0x1 << offset)) {
5094 /* Clear the event first */
5095 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5097 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5099 * Only notify a VF reset event occured,
5100 * don't trigger another SW reset
5102 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5103 if (ret != I40E_SUCCESS)
5104 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5110 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5112 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5113 struct i40e_arq_event_info info;
5114 uint16_t pending, opcode;
5117 info.buf_len = I40E_AQ_BUF_SZ;
5118 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5119 if (!info.msg_buf) {
5120 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5126 ret = i40e_clean_arq_element(hw, &info, &pending);
5128 if (ret != I40E_SUCCESS) {
5129 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5130 "aq_err: %u", hw->aq.asq_last_status);
5133 opcode = rte_le_to_cpu_16(info.desc.opcode);
5136 case i40e_aqc_opc_send_msg_to_pf:
5137 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5138 i40e_pf_host_handle_vf_msg(dev,
5139 rte_le_to_cpu_16(info.desc.retval),
5140 rte_le_to_cpu_32(info.desc.cookie_high),
5141 rte_le_to_cpu_32(info.desc.cookie_low),
5146 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5151 rte_free(info.msg_buf);
5155 * Interrupt handler is registered as the alarm callback for handling LSC
5156 * interrupt in a definite of time, in order to wait the NIC into a stable
5157 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5158 * no need for link down interrupt.
5161 i40e_dev_interrupt_delayed_handler(void *param)
5163 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5164 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5167 /* read interrupt causes again */
5168 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5170 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5171 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5172 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5173 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5174 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5175 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5176 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5177 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5178 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5179 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5180 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5182 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5183 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5184 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5185 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5186 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5188 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5189 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5190 i40e_dev_handle_vfr_event(dev);
5192 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5193 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5194 i40e_dev_handle_aq_msg(dev);
5197 /* handle the link up interrupt in an alarm callback */
5198 i40e_dev_link_update(dev, 0);
5199 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5201 i40e_pf_enable_irq0(hw);
5202 rte_intr_enable(&(dev->pci_dev->intr_handle));
5206 * Interrupt handler triggered by NIC for handling
5207 * specific interrupt.
5210 * Pointer to interrupt handle.
5212 * The address of parameter (struct rte_eth_dev *) regsitered before.
5218 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5221 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5222 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5225 /* Disable interrupt */
5226 i40e_pf_disable_irq0(hw);
5228 /* read out interrupt causes */
5229 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5231 /* No interrupt event indicated */
5232 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5233 PMD_DRV_LOG(INFO, "No interrupt event");
5236 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5237 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5238 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5239 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5240 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5241 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5242 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5243 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5244 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5245 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5246 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5247 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5248 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5249 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5250 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5251 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5253 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5254 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5255 i40e_dev_handle_vfr_event(dev);
5257 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5258 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5259 i40e_dev_handle_aq_msg(dev);
5262 /* Link Status Change interrupt */
5263 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5264 #define I40E_US_PER_SECOND 1000000
5265 struct rte_eth_link link;
5267 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5268 memset(&link, 0, sizeof(link));
5269 rte_i40e_dev_atomic_read_link_status(dev, &link);
5270 i40e_dev_link_update(dev, 0);
5273 * For link up interrupt, it needs to wait 1 second to let the
5274 * hardware be a stable state. Otherwise several consecutive
5275 * interrupts can be observed.
5276 * For link down interrupt, no need to wait.
5278 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5279 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5282 _rte_eth_dev_callback_process(dev,
5283 RTE_ETH_EVENT_INTR_LSC);
5287 /* Enable interrupt */
5288 i40e_pf_enable_irq0(hw);
5289 rte_intr_enable(&(dev->pci_dev->intr_handle));
5293 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5294 struct i40e_macvlan_filter *filter,
5297 int ele_num, ele_buff_size;
5298 int num, actual_num, i;
5300 int ret = I40E_SUCCESS;
5301 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5302 struct i40e_aqc_add_macvlan_element_data *req_list;
5304 if (filter == NULL || total == 0)
5305 return I40E_ERR_PARAM;
5306 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5307 ele_buff_size = hw->aq.asq_buf_size;
5309 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5310 if (req_list == NULL) {
5311 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5312 return I40E_ERR_NO_MEMORY;
5317 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5318 memset(req_list, 0, ele_buff_size);
5320 for (i = 0; i < actual_num; i++) {
5321 (void)rte_memcpy(req_list[i].mac_addr,
5322 &filter[num + i].macaddr, ETH_ADDR_LEN);
5323 req_list[i].vlan_tag =
5324 rte_cpu_to_le_16(filter[num + i].vlan_id);
5326 switch (filter[num + i].filter_type) {
5327 case RTE_MAC_PERFECT_MATCH:
5328 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5329 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5331 case RTE_MACVLAN_PERFECT_MATCH:
5332 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5334 case RTE_MAC_HASH_MATCH:
5335 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5336 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5338 case RTE_MACVLAN_HASH_MATCH:
5339 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5342 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5343 ret = I40E_ERR_PARAM;
5347 req_list[i].queue_number = 0;
5349 req_list[i].flags = rte_cpu_to_le_16(flags);
5352 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5354 if (ret != I40E_SUCCESS) {
5355 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5359 } while (num < total);
5367 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5368 struct i40e_macvlan_filter *filter,
5371 int ele_num, ele_buff_size;
5372 int num, actual_num, i;
5374 int ret = I40E_SUCCESS;
5375 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5376 struct i40e_aqc_remove_macvlan_element_data *req_list;
5378 if (filter == NULL || total == 0)
5379 return I40E_ERR_PARAM;
5381 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5382 ele_buff_size = hw->aq.asq_buf_size;
5384 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5385 if (req_list == NULL) {
5386 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5387 return I40E_ERR_NO_MEMORY;
5392 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5393 memset(req_list, 0, ele_buff_size);
5395 for (i = 0; i < actual_num; i++) {
5396 (void)rte_memcpy(req_list[i].mac_addr,
5397 &filter[num + i].macaddr, ETH_ADDR_LEN);
5398 req_list[i].vlan_tag =
5399 rte_cpu_to_le_16(filter[num + i].vlan_id);
5401 switch (filter[num + i].filter_type) {
5402 case RTE_MAC_PERFECT_MATCH:
5403 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5404 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5406 case RTE_MACVLAN_PERFECT_MATCH:
5407 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5409 case RTE_MAC_HASH_MATCH:
5410 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5411 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5413 case RTE_MACVLAN_HASH_MATCH:
5414 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5417 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5418 ret = I40E_ERR_PARAM;
5421 req_list[i].flags = rte_cpu_to_le_16(flags);
5424 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5426 if (ret != I40E_SUCCESS) {
5427 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5431 } while (num < total);
5438 /* Find out specific MAC filter */
5439 static struct i40e_mac_filter *
5440 i40e_find_mac_filter(struct i40e_vsi *vsi,
5441 struct ether_addr *macaddr)
5443 struct i40e_mac_filter *f;
5445 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5446 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5454 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5457 uint32_t vid_idx, vid_bit;
5459 if (vlan_id > ETH_VLAN_ID_MAX)
5462 vid_idx = I40E_VFTA_IDX(vlan_id);
5463 vid_bit = I40E_VFTA_BIT(vlan_id);
5465 if (vsi->vfta[vid_idx] & vid_bit)
5472 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5473 uint16_t vlan_id, bool on)
5475 uint32_t vid_idx, vid_bit;
5477 if (vlan_id > ETH_VLAN_ID_MAX)
5480 vid_idx = I40E_VFTA_IDX(vlan_id);
5481 vid_bit = I40E_VFTA_BIT(vlan_id);
5484 vsi->vfta[vid_idx] |= vid_bit;
5486 vsi->vfta[vid_idx] &= ~vid_bit;
5490 * Find all vlan options for specific mac addr,
5491 * return with actual vlan found.
5494 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5495 struct i40e_macvlan_filter *mv_f,
5496 int num, struct ether_addr *addr)
5502 * Not to use i40e_find_vlan_filter to decrease the loop time,
5503 * although the code looks complex.
5505 if (num < vsi->vlan_num)
5506 return I40E_ERR_PARAM;
5509 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5511 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5512 if (vsi->vfta[j] & (1 << k)) {
5514 PMD_DRV_LOG(ERR, "vlan number "
5516 return I40E_ERR_PARAM;
5518 (void)rte_memcpy(&mv_f[i].macaddr,
5519 addr, ETH_ADDR_LEN);
5521 j * I40E_UINT32_BIT_SIZE + k;
5527 return I40E_SUCCESS;
5531 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5532 struct i40e_macvlan_filter *mv_f,
5537 struct i40e_mac_filter *f;
5539 if (num < vsi->mac_num)
5540 return I40E_ERR_PARAM;
5542 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5544 PMD_DRV_LOG(ERR, "buffer number not match");
5545 return I40E_ERR_PARAM;
5547 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5549 mv_f[i].vlan_id = vlan;
5550 mv_f[i].filter_type = f->mac_info.filter_type;
5554 return I40E_SUCCESS;
5558 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5561 struct i40e_mac_filter *f;
5562 struct i40e_macvlan_filter *mv_f;
5563 int ret = I40E_SUCCESS;
5565 if (vsi == NULL || vsi->mac_num == 0)
5566 return I40E_ERR_PARAM;
5568 /* Case that no vlan is set */
5569 if (vsi->vlan_num == 0)
5572 num = vsi->mac_num * vsi->vlan_num;
5574 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5576 PMD_DRV_LOG(ERR, "failed to allocate memory");
5577 return I40E_ERR_NO_MEMORY;
5581 if (vsi->vlan_num == 0) {
5582 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5583 (void)rte_memcpy(&mv_f[i].macaddr,
5584 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5585 mv_f[i].vlan_id = 0;
5589 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5590 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5591 vsi->vlan_num, &f->mac_info.mac_addr);
5592 if (ret != I40E_SUCCESS)
5598 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5606 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5608 struct i40e_macvlan_filter *mv_f;
5610 int ret = I40E_SUCCESS;
5612 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5613 return I40E_ERR_PARAM;
5615 /* If it's already set, just return */
5616 if (i40e_find_vlan_filter(vsi,vlan))
5617 return I40E_SUCCESS;
5619 mac_num = vsi->mac_num;
5622 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5623 return I40E_ERR_PARAM;
5626 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5629 PMD_DRV_LOG(ERR, "failed to allocate memory");
5630 return I40E_ERR_NO_MEMORY;
5633 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5635 if (ret != I40E_SUCCESS)
5638 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5640 if (ret != I40E_SUCCESS)
5643 i40e_set_vlan_filter(vsi, vlan, 1);
5653 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5655 struct i40e_macvlan_filter *mv_f;
5657 int ret = I40E_SUCCESS;
5660 * Vlan 0 is the generic filter for untagged packets
5661 * and can't be removed.
5663 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5664 return I40E_ERR_PARAM;
5666 /* If can't find it, just return */
5667 if (!i40e_find_vlan_filter(vsi, vlan))
5668 return I40E_ERR_PARAM;
5670 mac_num = vsi->mac_num;
5673 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5674 return I40E_ERR_PARAM;
5677 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5680 PMD_DRV_LOG(ERR, "failed to allocate memory");
5681 return I40E_ERR_NO_MEMORY;
5684 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5686 if (ret != I40E_SUCCESS)
5689 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5691 if (ret != I40E_SUCCESS)
5694 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5695 if (vsi->vlan_num == 1) {
5696 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5697 if (ret != I40E_SUCCESS)
5700 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5701 if (ret != I40E_SUCCESS)
5705 i40e_set_vlan_filter(vsi, vlan, 0);
5715 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5717 struct i40e_mac_filter *f;
5718 struct i40e_macvlan_filter *mv_f;
5719 int i, vlan_num = 0;
5720 int ret = I40E_SUCCESS;
5722 /* If it's add and we've config it, return */
5723 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5725 return I40E_SUCCESS;
5726 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5727 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5730 * If vlan_num is 0, that's the first time to add mac,
5731 * set mask for vlan_id 0.
5733 if (vsi->vlan_num == 0) {
5734 i40e_set_vlan_filter(vsi, 0, 1);
5737 vlan_num = vsi->vlan_num;
5738 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5739 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5742 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5744 PMD_DRV_LOG(ERR, "failed to allocate memory");
5745 return I40E_ERR_NO_MEMORY;
5748 for (i = 0; i < vlan_num; i++) {
5749 mv_f[i].filter_type = mac_filter->filter_type;
5750 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5754 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5755 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5756 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5757 &mac_filter->mac_addr);
5758 if (ret != I40E_SUCCESS)
5762 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5763 if (ret != I40E_SUCCESS)
5766 /* Add the mac addr into mac list */
5767 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5769 PMD_DRV_LOG(ERR, "failed to allocate memory");
5770 ret = I40E_ERR_NO_MEMORY;
5773 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5775 f->mac_info.filter_type = mac_filter->filter_type;
5776 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5787 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5789 struct i40e_mac_filter *f;
5790 struct i40e_macvlan_filter *mv_f;
5792 enum rte_mac_filter_type filter_type;
5793 int ret = I40E_SUCCESS;
5795 /* Can't find it, return an error */
5796 f = i40e_find_mac_filter(vsi, addr);
5798 return I40E_ERR_PARAM;
5800 vlan_num = vsi->vlan_num;
5801 filter_type = f->mac_info.filter_type;
5802 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5803 filter_type == RTE_MACVLAN_HASH_MATCH) {
5804 if (vlan_num == 0) {
5805 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5806 return I40E_ERR_PARAM;
5808 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5809 filter_type == RTE_MAC_HASH_MATCH)
5812 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5814 PMD_DRV_LOG(ERR, "failed to allocate memory");
5815 return I40E_ERR_NO_MEMORY;
5818 for (i = 0; i < vlan_num; i++) {
5819 mv_f[i].filter_type = filter_type;
5820 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5823 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5824 filter_type == RTE_MACVLAN_HASH_MATCH) {
5825 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5826 if (ret != I40E_SUCCESS)
5830 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5831 if (ret != I40E_SUCCESS)
5834 /* Remove the mac addr into mac list */
5835 TAILQ_REMOVE(&vsi->mac_list, f, next);
5845 /* Configure hash enable flags for RSS */
5847 i40e_config_hena(uint64_t flags)
5854 if (flags & ETH_RSS_FRAG_IPV4)
5855 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5856 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5857 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5858 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5859 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5860 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5861 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5862 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5863 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5864 if (flags & ETH_RSS_FRAG_IPV6)
5865 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5866 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5867 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5868 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5869 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5870 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5871 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5872 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5873 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5874 if (flags & ETH_RSS_L2_PAYLOAD)
5875 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5880 /* Parse the hash enable flags */
5882 i40e_parse_hena(uint64_t flags)
5884 uint64_t rss_hf = 0;
5888 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5889 rss_hf |= ETH_RSS_FRAG_IPV4;
5890 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5891 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5892 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5893 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5894 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5895 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5896 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5897 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5898 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5899 rss_hf |= ETH_RSS_FRAG_IPV6;
5900 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5901 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5902 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5903 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5904 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5905 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5906 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5907 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5908 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5909 rss_hf |= ETH_RSS_L2_PAYLOAD;
5916 i40e_pf_disable_rss(struct i40e_pf *pf)
5918 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5921 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5922 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5923 hena &= ~I40E_RSS_HENA_ALL;
5924 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5925 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5926 I40E_WRITE_FLUSH(hw);
5930 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5932 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5933 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5936 if (!key || key_len == 0) {
5937 PMD_DRV_LOG(DEBUG, "No key to be configured");
5939 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5941 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5945 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5946 struct i40e_aqc_get_set_rss_key_data *key_dw =
5947 (struct i40e_aqc_get_set_rss_key_data *)key;
5949 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5951 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5954 uint32_t *hash_key = (uint32_t *)key;
5957 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5958 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5959 I40E_WRITE_FLUSH(hw);
5966 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5968 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5969 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5972 if (!key || !key_len)
5975 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5976 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5977 (struct i40e_aqc_get_set_rss_key_data *)key);
5979 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5983 uint32_t *key_dw = (uint32_t *)key;
5986 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5987 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
5989 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5995 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5997 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6002 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6003 rss_conf->rss_key_len);
6007 rss_hf = rss_conf->rss_hf;
6008 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6009 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6010 hena &= ~I40E_RSS_HENA_ALL;
6011 hena |= i40e_config_hena(rss_hf);
6012 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6013 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6014 I40E_WRITE_FLUSH(hw);
6020 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6021 struct rte_eth_rss_conf *rss_conf)
6023 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6024 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6025 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6028 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6029 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6030 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6031 if (rss_hf != 0) /* Enable RSS */
6033 return 0; /* Nothing to do */
6036 if (rss_hf == 0) /* Disable RSS */
6039 return i40e_hw_rss_hash_set(pf, rss_conf);
6043 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6044 struct rte_eth_rss_conf *rss_conf)
6046 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6047 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6050 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6051 &rss_conf->rss_key_len);
6053 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6054 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6055 rss_conf->rss_hf = i40e_parse_hena(hena);
6061 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6063 switch (filter_type) {
6064 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6065 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6067 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6068 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6070 case RTE_TUNNEL_FILTER_IMAC_TENID:
6071 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6073 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6074 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6076 case ETH_TUNNEL_FILTER_IMAC:
6077 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6079 case ETH_TUNNEL_FILTER_OIP:
6080 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6082 case ETH_TUNNEL_FILTER_IIP:
6083 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6086 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6094 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6095 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6100 uint8_t i, tun_type = 0;
6101 /* internal varialbe to convert ipv6 byte order */
6102 uint32_t convert_ipv6[4];
6104 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6105 struct i40e_vsi *vsi = pf->main_vsi;
6106 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6107 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6109 cld_filter = rte_zmalloc("tunnel_filter",
6110 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6113 if (NULL == cld_filter) {
6114 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6117 pfilter = cld_filter;
6119 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6120 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6122 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6123 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6124 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6125 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6126 rte_memcpy(&pfilter->ipaddr.v4.data,
6127 &rte_cpu_to_le_32(ipv4_addr),
6128 sizeof(pfilter->ipaddr.v4.data));
6130 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6131 for (i = 0; i < 4; i++) {
6133 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6135 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6136 sizeof(pfilter->ipaddr.v6.data));
6139 /* check tunneled type */
6140 switch (tunnel_filter->tunnel_type) {
6141 case RTE_TUNNEL_TYPE_VXLAN:
6142 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6144 case RTE_TUNNEL_TYPE_NVGRE:
6145 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6147 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6148 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6151 /* Other tunnel types is not supported. */
6152 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6153 rte_free(cld_filter);
6157 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6160 rte_free(cld_filter);
6164 pfilter->flags |= rte_cpu_to_le_16(
6165 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6166 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6167 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6168 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6171 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6173 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6176 rte_free(cld_filter);
6181 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6185 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6186 if (pf->vxlan_ports[i] == port)
6194 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6198 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6200 idx = i40e_get_vxlan_port_idx(pf, port);
6202 /* Check if port already exists */
6204 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6208 /* Now check if there is space to add the new port */
6209 idx = i40e_get_vxlan_port_idx(pf, 0);
6211 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6212 "not adding port %d", port);
6216 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6219 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6223 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6226 /* New port: add it and mark its index in the bitmap */
6227 pf->vxlan_ports[idx] = port;
6228 pf->vxlan_bitmap |= (1 << idx);
6230 if (!(pf->flags & I40E_FLAG_VXLAN))
6231 pf->flags |= I40E_FLAG_VXLAN;
6237 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6240 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6242 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6243 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6247 idx = i40e_get_vxlan_port_idx(pf, port);
6250 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6254 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6255 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6259 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6262 pf->vxlan_ports[idx] = 0;
6263 pf->vxlan_bitmap &= ~(1 << idx);
6265 if (!pf->vxlan_bitmap)
6266 pf->flags &= ~I40E_FLAG_VXLAN;
6271 /* Add UDP tunneling port */
6273 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6274 struct rte_eth_udp_tunnel *udp_tunnel)
6277 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6279 if (udp_tunnel == NULL)
6282 switch (udp_tunnel->prot_type) {
6283 case RTE_TUNNEL_TYPE_VXLAN:
6284 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6287 case RTE_TUNNEL_TYPE_GENEVE:
6288 case RTE_TUNNEL_TYPE_TEREDO:
6289 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6294 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6302 /* Remove UDP tunneling port */
6304 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6305 struct rte_eth_udp_tunnel *udp_tunnel)
6308 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6310 if (udp_tunnel == NULL)
6313 switch (udp_tunnel->prot_type) {
6314 case RTE_TUNNEL_TYPE_VXLAN:
6315 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6317 case RTE_TUNNEL_TYPE_GENEVE:
6318 case RTE_TUNNEL_TYPE_TEREDO:
6319 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6323 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6331 /* Calculate the maximum number of contiguous PF queues that are configured */
6333 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6335 struct rte_eth_dev_data *data = pf->dev_data;
6337 struct i40e_rx_queue *rxq;
6340 for (i = 0; i < pf->lan_nb_qps; i++) {
6341 rxq = data->rx_queues[i];
6342 if (rxq && rxq->q_set)
6353 i40e_pf_config_rss(struct i40e_pf *pf)
6355 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6356 struct rte_eth_rss_conf rss_conf;
6357 uint32_t i, lut = 0;
6361 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6362 * It's necessary to calulate the actual PF queues that are configured.
6364 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6365 num = i40e_pf_calc_configured_queues_num(pf);
6367 num = pf->dev_data->nb_rx_queues;
6369 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6370 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6374 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6378 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6381 lut = (lut << 8) | (j & ((0x1 <<
6382 hw->func_caps.rss_table_entry_width) - 1));
6384 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6387 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6388 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6389 i40e_pf_disable_rss(pf);
6392 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6393 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6394 /* Random default keys */
6395 static uint32_t rss_key_default[] = {0x6b793944,
6396 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6397 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6398 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6400 rss_conf.rss_key = (uint8_t *)rss_key_default;
6401 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6405 return i40e_hw_rss_hash_set(pf, &rss_conf);
6409 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6410 struct rte_eth_tunnel_filter_conf *filter)
6412 if (pf == NULL || filter == NULL) {
6413 PMD_DRV_LOG(ERR, "Invalid parameter");
6417 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6418 PMD_DRV_LOG(ERR, "Invalid queue ID");
6422 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6423 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6427 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6428 (is_zero_ether_addr(&filter->outer_mac))) {
6429 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6433 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6434 (is_zero_ether_addr(&filter->inner_mac))) {
6435 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6442 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6443 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6445 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6450 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6451 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6454 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6455 } else if (len == 4) {
6456 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6458 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6463 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6470 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6471 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6477 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6484 switch (cfg->cfg_type) {
6485 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6486 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6489 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6497 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6498 enum rte_filter_op filter_op,
6501 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6502 int ret = I40E_ERR_PARAM;
6504 switch (filter_op) {
6505 case RTE_ETH_FILTER_SET:
6506 ret = i40e_dev_global_config_set(hw,
6507 (struct rte_eth_global_cfg *)arg);
6510 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6518 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6519 enum rte_filter_op filter_op,
6522 struct rte_eth_tunnel_filter_conf *filter;
6523 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6524 int ret = I40E_SUCCESS;
6526 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6528 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6529 return I40E_ERR_PARAM;
6531 switch (filter_op) {
6532 case RTE_ETH_FILTER_NOP:
6533 if (!(pf->flags & I40E_FLAG_VXLAN))
6534 ret = I40E_NOT_SUPPORTED;
6536 case RTE_ETH_FILTER_ADD:
6537 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6539 case RTE_ETH_FILTER_DELETE:
6540 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6543 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6544 ret = I40E_ERR_PARAM;
6552 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6555 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6558 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6559 ret = i40e_pf_config_rss(pf);
6561 i40e_pf_disable_rss(pf);
6566 /* Get the symmetric hash enable configurations per port */
6568 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6570 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6572 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6575 /* Set the symmetric hash enable configurations per port */
6577 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6579 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6582 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6583 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6587 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6589 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6590 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6594 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6596 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6597 I40E_WRITE_FLUSH(hw);
6601 * Get global configurations of hash function type and symmetric hash enable
6602 * per flow type (pctype). Note that global configuration means it affects all
6603 * the ports on the same NIC.
6606 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6607 struct rte_eth_hash_global_conf *g_cfg)
6609 uint32_t reg, mask = I40E_FLOW_TYPES;
6611 enum i40e_filter_pctype pctype;
6613 memset(g_cfg, 0, sizeof(*g_cfg));
6614 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6615 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6616 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6618 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6619 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6620 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6622 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6623 if (!(mask & (1UL << i)))
6625 mask &= ~(1UL << i);
6626 /* Bit set indicats the coresponding flow type is supported */
6627 g_cfg->valid_bit_mask[0] |= (1UL << i);
6628 pctype = i40e_flowtype_to_pctype(i);
6629 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6630 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6631 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6638 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6641 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6643 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6644 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6645 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6646 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6652 * As i40e supports less than 32 flow types, only first 32 bits need to
6655 mask0 = g_cfg->valid_bit_mask[0];
6656 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6658 /* Check if any unsupported flow type configured */
6659 if ((mask0 | i40e_mask) ^ i40e_mask)
6662 if (g_cfg->valid_bit_mask[i])
6670 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6676 * Set global configurations of hash function type and symmetric hash enable
6677 * per flow type (pctype). Note any modifying global configuration will affect
6678 * all the ports on the same NIC.
6681 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6682 struct rte_eth_hash_global_conf *g_cfg)
6687 uint32_t mask0 = g_cfg->valid_bit_mask[0];
6688 enum i40e_filter_pctype pctype;
6690 /* Check the input parameters */
6691 ret = i40e_hash_global_config_check(g_cfg);
6695 for (i = 0; mask0 && i < UINT32_BIT; i++) {
6696 if (!(mask0 & (1UL << i)))
6698 mask0 &= ~(1UL << i);
6699 pctype = i40e_flowtype_to_pctype(i);
6700 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6701 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6702 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6705 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6706 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6708 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6709 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6713 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6714 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6716 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6717 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6721 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6723 /* Use the default, and keep it as it is */
6726 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6729 I40E_WRITE_FLUSH(hw);
6735 * Valid input sets for hash and flow director filters per PCTYPE
6738 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6739 enum rte_filter_type filter)
6743 static const uint64_t valid_hash_inset_table[] = {
6744 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6745 I40E_INSET_DMAC | I40E_INSET_SMAC |
6746 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6747 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6748 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6749 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6750 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6751 I40E_INSET_FLEX_PAYLOAD,
6752 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6753 I40E_INSET_DMAC | I40E_INSET_SMAC |
6754 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6755 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6756 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6757 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6758 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6759 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6760 I40E_INSET_FLEX_PAYLOAD,
6761 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6762 I40E_INSET_DMAC | I40E_INSET_SMAC |
6763 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6764 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6765 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6766 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6767 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6768 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6769 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6770 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6771 I40E_INSET_DMAC | I40E_INSET_SMAC |
6772 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6773 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6774 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6775 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6776 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6777 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6778 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6779 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6780 I40E_INSET_DMAC | I40E_INSET_SMAC |
6781 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6782 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6783 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6784 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6785 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6786 I40E_INSET_FLEX_PAYLOAD,
6787 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6788 I40E_INSET_DMAC | I40E_INSET_SMAC |
6789 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6790 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6791 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6792 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6793 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6794 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6795 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6796 I40E_INSET_DMAC | I40E_INSET_SMAC |
6797 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6798 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6799 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6800 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6801 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6802 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6803 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6804 I40E_INSET_DMAC | I40E_INSET_SMAC |
6805 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6806 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6807 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6808 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6809 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6810 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6811 I40E_INSET_FLEX_PAYLOAD,
6812 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6813 I40E_INSET_DMAC | I40E_INSET_SMAC |
6814 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6815 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6816 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6817 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6818 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6819 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6820 I40E_INSET_FLEX_PAYLOAD,
6821 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6822 I40E_INSET_DMAC | I40E_INSET_SMAC |
6823 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6824 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6825 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6826 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6827 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6828 I40E_INSET_FLEX_PAYLOAD,
6829 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6830 I40E_INSET_DMAC | I40E_INSET_SMAC |
6831 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6832 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6833 I40E_INSET_FLEX_PAYLOAD,
6837 * Flow director supports only fields defined in
6838 * union rte_eth_fdir_flow.
6840 static const uint64_t valid_fdir_inset_table[] = {
6841 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6842 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6843 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6844 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6845 I40E_INSET_IPV4_TTL,
6846 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6847 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6848 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6849 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6850 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6851 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6852 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6853 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6854 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6855 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6856 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6857 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6858 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6859 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6860 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6862 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6863 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6864 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6865 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6866 I40E_INSET_IPV4_TTL,
6867 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6868 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6869 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6870 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6871 I40E_INSET_IPV6_HOP_LIMIT,
6872 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6873 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6874 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6875 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6876 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6877 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6878 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6879 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6880 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6881 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6882 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6883 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6884 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6885 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6886 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6888 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6889 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6890 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6891 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6892 I40E_INSET_IPV6_HOP_LIMIT,
6893 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6894 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6895 I40E_INSET_LAST_ETHER_TYPE,
6898 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6900 if (filter == RTE_ETH_FILTER_HASH)
6901 valid = valid_hash_inset_table[pctype];
6903 valid = valid_fdir_inset_table[pctype];
6909 * Validate if the input set is allowed for a specific PCTYPE
6912 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6913 enum rte_filter_type filter, uint64_t inset)
6917 valid = i40e_get_valid_input_set(pctype, filter);
6918 if (inset & (~valid))
6924 /* default input set fields combination per pctype */
6926 i40e_get_default_input_set(uint16_t pctype)
6928 static const uint64_t default_inset_table[] = {
6929 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6930 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6931 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6932 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6933 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6934 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6935 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6936 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6937 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6938 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6939 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6941 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6942 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6943 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6944 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6945 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6946 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6947 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6948 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6949 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6950 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6951 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6952 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6953 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6955 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6956 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6957 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6958 I40E_INSET_LAST_ETHER_TYPE,
6961 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6964 return default_inset_table[pctype];
6968 * Parse the input set from index to logical bit masks
6971 i40e_parse_input_set(uint64_t *inset,
6972 enum i40e_filter_pctype pctype,
6973 enum rte_eth_input_set_field *field,
6979 static const struct {
6980 enum rte_eth_input_set_field field;
6982 } inset_convert_table[] = {
6983 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6984 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6985 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6986 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6987 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6988 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6989 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6990 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6991 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6992 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6993 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
6994 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6995 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6996 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6997 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6998 I40E_INSET_IPV6_NEXT_HDR},
6999 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7000 I40E_INSET_IPV6_HOP_LIMIT},
7001 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7002 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7003 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7004 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7005 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7006 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7007 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7008 I40E_INSET_SCTP_VT},
7009 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7010 I40E_INSET_TUNNEL_DMAC},
7011 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7012 I40E_INSET_VLAN_TUNNEL},
7013 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7014 I40E_INSET_TUNNEL_ID},
7015 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7016 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7017 I40E_INSET_FLEX_PAYLOAD_W1},
7018 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7019 I40E_INSET_FLEX_PAYLOAD_W2},
7020 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7021 I40E_INSET_FLEX_PAYLOAD_W3},
7022 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7023 I40E_INSET_FLEX_PAYLOAD_W4},
7024 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7025 I40E_INSET_FLEX_PAYLOAD_W5},
7026 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7027 I40E_INSET_FLEX_PAYLOAD_W6},
7028 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7029 I40E_INSET_FLEX_PAYLOAD_W7},
7030 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7031 I40E_INSET_FLEX_PAYLOAD_W8},
7034 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7037 /* Only one item allowed for default or all */
7039 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7040 *inset = i40e_get_default_input_set(pctype);
7042 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7043 *inset = I40E_INSET_NONE;
7048 for (i = 0, *inset = 0; i < size; i++) {
7049 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7050 if (field[i] == inset_convert_table[j].field) {
7051 *inset |= inset_convert_table[j].inset;
7056 /* It contains unsupported input set, return immediately */
7057 if (j == RTE_DIM(inset_convert_table))
7065 * Translate the input set from bit masks to register aware bit masks
7069 i40e_translate_input_set_reg(uint64_t input)
7074 static const struct {
7078 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7079 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7080 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7081 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7082 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7083 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7084 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7085 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7086 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7087 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7088 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7089 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7090 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7091 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7092 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7093 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7094 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7095 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7096 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7097 {I40E_INSET_TUNNEL_DMAC,
7098 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7099 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7100 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7101 {I40E_INSET_TUNNEL_SRC_PORT,
7102 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7103 {I40E_INSET_TUNNEL_DST_PORT,
7104 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7105 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7106 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7107 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7108 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7109 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7110 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7111 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7112 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7113 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7119 /* Translate input set to register aware inset */
7120 for (i = 0; i < RTE_DIM(inset_map); i++) {
7121 if (input & inset_map[i].inset)
7122 val |= inset_map[i].inset_reg;
7129 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7132 uint64_t inset_need_mask = inset;
7134 static const struct {
7137 } inset_mask_map[] = {
7138 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7139 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7140 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7141 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7142 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7143 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7144 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7145 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7148 if (!inset || !mask || !nb_elem)
7151 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7152 /* Clear the inset bit, if no MASK is required,
7153 * for example proto + ttl
7155 if ((inset & inset_mask_map[i].inset) ==
7156 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7157 inset_need_mask &= ~inset_mask_map[i].inset;
7158 if (!inset_need_mask)
7161 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7162 if ((inset_need_mask & inset_mask_map[i].inset) ==
7163 inset_mask_map[i].inset) {
7164 if (idx >= nb_elem) {
7165 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7168 mask[idx] = inset_mask_map[i].mask;
7177 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7179 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7181 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7183 i40e_write_rx_ctl(hw, addr, val);
7184 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7185 (uint32_t)i40e_read_rx_ctl(hw, addr));
7189 i40e_filter_input_set_init(struct i40e_pf *pf)
7191 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7192 enum i40e_filter_pctype pctype;
7193 uint64_t input_set, inset_reg;
7194 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7197 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7198 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7199 if (!I40E_VALID_PCTYPE(pctype))
7201 input_set = i40e_get_default_input_set(pctype);
7203 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7204 I40E_INSET_MASK_NUM_REG);
7207 inset_reg = i40e_translate_input_set_reg(input_set);
7209 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7210 (uint32_t)(inset_reg & UINT32_MAX));
7211 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7212 (uint32_t)((inset_reg >>
7213 I40E_32_BIT_WIDTH) & UINT32_MAX));
7214 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7215 (uint32_t)(inset_reg & UINT32_MAX));
7216 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7217 (uint32_t)((inset_reg >>
7218 I40E_32_BIT_WIDTH) & UINT32_MAX));
7220 for (i = 0; i < num; i++) {
7221 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7223 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7226 /*clear unused mask registers of the pctype */
7227 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7228 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7230 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7233 I40E_WRITE_FLUSH(hw);
7235 /* store the default input set */
7236 pf->hash_input_set[pctype] = input_set;
7237 pf->fdir.input_set[pctype] = input_set;
7242 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7243 struct rte_eth_input_set_conf *conf)
7245 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7246 enum i40e_filter_pctype pctype;
7247 uint64_t input_set, inset_reg = 0;
7248 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7252 PMD_DRV_LOG(ERR, "Invalid pointer");
7255 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7256 conf->op != RTE_ETH_INPUT_SET_ADD) {
7257 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7261 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7262 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7263 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7268 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7271 PMD_DRV_LOG(ERR, "Failed to parse input set");
7274 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7276 PMD_DRV_LOG(ERR, "Invalid input set");
7279 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7280 /* get inset value in register */
7281 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7282 inset_reg <<= I40E_32_BIT_WIDTH;
7283 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7284 input_set |= pf->hash_input_set[pctype];
7286 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7287 I40E_INSET_MASK_NUM_REG);
7291 inset_reg |= i40e_translate_input_set_reg(input_set);
7293 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7294 (uint32_t)(inset_reg & UINT32_MAX));
7295 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7296 (uint32_t)((inset_reg >>
7297 I40E_32_BIT_WIDTH) & UINT32_MAX));
7299 for (i = 0; i < num; i++)
7300 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7302 /*clear unused mask registers of the pctype */
7303 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7304 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7306 I40E_WRITE_FLUSH(hw);
7308 pf->hash_input_set[pctype] = input_set;
7313 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7314 struct rte_eth_input_set_conf *conf)
7316 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7317 enum i40e_filter_pctype pctype;
7318 uint64_t input_set, inset_reg = 0;
7319 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7323 PMD_DRV_LOG(ERR, "Invalid pointer");
7326 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7327 conf->op != RTE_ETH_INPUT_SET_ADD) {
7328 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7332 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7333 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7334 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7338 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7341 PMD_DRV_LOG(ERR, "Failed to parse input set");
7344 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7346 PMD_DRV_LOG(ERR, "Invalid input set");
7350 /* get inset value in register */
7351 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7352 inset_reg <<= I40E_32_BIT_WIDTH;
7353 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7355 /* Can not change the inset reg for flex payload for fdir,
7356 * it is done by writing I40E_PRTQF_FD_FLXINSET
7357 * in i40e_set_flex_mask_on_pctype.
7359 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7360 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7362 input_set |= pf->fdir.input_set[pctype];
7363 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7364 I40E_INSET_MASK_NUM_REG);
7368 inset_reg |= i40e_translate_input_set_reg(input_set);
7370 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7371 (uint32_t)(inset_reg & UINT32_MAX));
7372 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7373 (uint32_t)((inset_reg >>
7374 I40E_32_BIT_WIDTH) & UINT32_MAX));
7376 for (i = 0; i < num; i++)
7377 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7379 /*clear unused mask registers of the pctype */
7380 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7381 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7383 I40E_WRITE_FLUSH(hw);
7385 pf->fdir.input_set[pctype] = input_set;
7390 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7395 PMD_DRV_LOG(ERR, "Invalid pointer");
7399 switch (info->info_type) {
7400 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7401 i40e_get_symmetric_hash_enable_per_port(hw,
7402 &(info->info.enable));
7404 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7405 ret = i40e_get_hash_filter_global_config(hw,
7406 &(info->info.global_conf));
7409 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7419 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7424 PMD_DRV_LOG(ERR, "Invalid pointer");
7428 switch (info->info_type) {
7429 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7430 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7432 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7433 ret = i40e_set_hash_filter_global_config(hw,
7434 &(info->info.global_conf));
7436 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7437 ret = i40e_hash_filter_inset_select(hw,
7438 &(info->info.input_set_conf));
7442 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7451 /* Operations for hash function */
7453 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7454 enum rte_filter_op filter_op,
7457 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7460 switch (filter_op) {
7461 case RTE_ETH_FILTER_NOP:
7463 case RTE_ETH_FILTER_GET:
7464 ret = i40e_hash_filter_get(hw,
7465 (struct rte_eth_hash_filter_info *)arg);
7467 case RTE_ETH_FILTER_SET:
7468 ret = i40e_hash_filter_set(hw,
7469 (struct rte_eth_hash_filter_info *)arg);
7472 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7482 * Configure ethertype filter, which can director packet by filtering
7483 * with mac address and ether_type or only ether_type
7486 i40e_ethertype_filter_set(struct i40e_pf *pf,
7487 struct rte_eth_ethertype_filter *filter,
7490 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7491 struct i40e_control_filter_stats stats;
7495 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7496 PMD_DRV_LOG(ERR, "Invalid queue ID");
7499 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7500 filter->ether_type == ETHER_TYPE_IPv6) {
7501 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7502 " control packet filter.", filter->ether_type);
7505 if (filter->ether_type == ETHER_TYPE_VLAN)
7506 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7509 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7510 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7511 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7512 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7513 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7515 memset(&stats, 0, sizeof(stats));
7516 ret = i40e_aq_add_rem_control_packet_filter(hw,
7517 filter->mac_addr.addr_bytes,
7518 filter->ether_type, flags,
7520 filter->queue, add, &stats, NULL);
7522 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7523 " mac_etype_used = %u, etype_used = %u,"
7524 " mac_etype_free = %u, etype_free = %u\n",
7525 ret, stats.mac_etype_used, stats.etype_used,
7526 stats.mac_etype_free, stats.etype_free);
7533 * Handle operations for ethertype filter.
7536 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7537 enum rte_filter_op filter_op,
7540 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7543 if (filter_op == RTE_ETH_FILTER_NOP)
7547 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7552 switch (filter_op) {
7553 case RTE_ETH_FILTER_ADD:
7554 ret = i40e_ethertype_filter_set(pf,
7555 (struct rte_eth_ethertype_filter *)arg,
7558 case RTE_ETH_FILTER_DELETE:
7559 ret = i40e_ethertype_filter_set(pf,
7560 (struct rte_eth_ethertype_filter *)arg,
7564 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7572 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7573 enum rte_filter_type filter_type,
7574 enum rte_filter_op filter_op,
7582 switch (filter_type) {
7583 case RTE_ETH_FILTER_NONE:
7584 /* For global configuration */
7585 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7587 case RTE_ETH_FILTER_HASH:
7588 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7590 case RTE_ETH_FILTER_MACVLAN:
7591 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7593 case RTE_ETH_FILTER_ETHERTYPE:
7594 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7596 case RTE_ETH_FILTER_TUNNEL:
7597 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7599 case RTE_ETH_FILTER_FDIR:
7600 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7603 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7613 * Check and enable Extended Tag.
7614 * Enabling Extended Tag is important for 40G performance.
7617 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7622 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7625 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7629 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7630 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7635 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7638 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7642 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7643 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7646 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7647 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7650 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7657 * As some registers wouldn't be reset unless a global hardware reset,
7658 * hardware initialization is needed to put those registers into an
7659 * expected initial state.
7662 i40e_hw_init(struct rte_eth_dev *dev)
7664 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7666 i40e_enable_extended_tag(dev);
7668 /* clear the PF Queue Filter control register */
7669 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7671 /* Disable symmetric hash per port */
7672 i40e_set_symmetric_hash_enable_per_port(hw, 0);
7675 enum i40e_filter_pctype
7676 i40e_flowtype_to_pctype(uint16_t flow_type)
7678 static const enum i40e_filter_pctype pctype_table[] = {
7679 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7680 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7681 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7682 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7683 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7684 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7685 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7686 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7687 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7688 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7689 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7690 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7691 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7692 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7693 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7694 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7695 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7696 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7697 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7700 return pctype_table[flow_type];
7704 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7706 static const uint16_t flowtype_table[] = {
7707 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7708 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7709 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7710 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7711 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7712 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7713 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7714 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7715 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7716 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7717 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7718 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7719 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7720 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7721 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7722 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7723 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7724 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7725 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7728 return flowtype_table[pctype];
7732 * On X710, performance number is far from the expectation on recent firmware
7733 * versions; on XL710, performance number is also far from the expectation on
7734 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7735 * mode is enabled and port MAC address is equal to the packet destination MAC
7736 * address. The fix for this issue may not be integrated in the following
7737 * firmware version. So the workaround in software driver is needed. It needs
7738 * to modify the initial values of 3 internal only registers for both X710 and
7739 * XL710. Note that the values for X710 or XL710 could be different, and the
7740 * workaround can be removed when it is fixed in firmware in the future.
7743 /* For both X710 and XL710 */
7744 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7745 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
7747 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7748 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
7751 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
7753 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
7754 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
7757 i40e_configure_registers(struct i40e_hw *hw)
7763 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7764 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7765 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7771 for (i = 0; i < RTE_DIM(reg_table); i++) {
7772 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7773 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7775 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7778 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7781 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7784 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7788 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7789 reg_table[i].addr, reg);
7790 if (reg == reg_table[i].val)
7793 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7794 reg_table[i].val, NULL);
7796 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7797 "address of 0x%"PRIx32, reg_table[i].val,
7801 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7802 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7806 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
7807 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
7808 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
7809 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7811 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7816 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7817 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7821 /* Configure for double VLAN RX stripping */
7822 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7823 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7824 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7825 ret = i40e_aq_debug_write_register(hw,
7826 I40E_VSI_TSR(vsi->vsi_id),
7829 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7831 return I40E_ERR_CONFIG;
7835 /* Configure for double VLAN TX insertion */
7836 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7837 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7838 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7839 ret = i40e_aq_debug_write_register(hw,
7840 I40E_VSI_L2TAGSTXVALID(
7841 vsi->vsi_id), reg, NULL);
7843 PMD_DRV_LOG(ERR, "Failed to update "
7844 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7845 return I40E_ERR_CONFIG;
7853 * i40e_aq_add_mirror_rule
7854 * @hw: pointer to the hardware structure
7855 * @seid: VEB seid to add mirror rule to
7856 * @dst_id: destination vsi seid
7857 * @entries: Buffer which contains the entities to be mirrored
7858 * @count: number of entities contained in the buffer
7859 * @rule_id:the rule_id of the rule to be added
7861 * Add a mirror rule for a given veb.
7864 static enum i40e_status_code
7865 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7866 uint16_t seid, uint16_t dst_id,
7867 uint16_t rule_type, uint16_t *entries,
7868 uint16_t count, uint16_t *rule_id)
7870 struct i40e_aq_desc desc;
7871 struct i40e_aqc_add_delete_mirror_rule cmd;
7872 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7873 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7876 enum i40e_status_code status;
7878 i40e_fill_default_direct_cmd_desc(&desc,
7879 i40e_aqc_opc_add_mirror_rule);
7880 memset(&cmd, 0, sizeof(cmd));
7882 buff_len = sizeof(uint16_t) * count;
7883 desc.datalen = rte_cpu_to_le_16(buff_len);
7885 desc.flags |= rte_cpu_to_le_16(
7886 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7887 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7888 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7889 cmd.num_entries = rte_cpu_to_le_16(count);
7890 cmd.seid = rte_cpu_to_le_16(seid);
7891 cmd.destination = rte_cpu_to_le_16(dst_id);
7893 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7894 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7895 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7897 " mirror_rules_used = %u, mirror_rules_free = %u,",
7898 hw->aq.asq_last_status, resp->rule_id,
7899 resp->mirror_rules_used, resp->mirror_rules_free);
7900 *rule_id = rte_le_to_cpu_16(resp->rule_id);
7906 * i40e_aq_del_mirror_rule
7907 * @hw: pointer to the hardware structure
7908 * @seid: VEB seid to add mirror rule to
7909 * @entries: Buffer which contains the entities to be mirrored
7910 * @count: number of entities contained in the buffer
7911 * @rule_id:the rule_id of the rule to be delete
7913 * Delete a mirror rule for a given veb.
7916 static enum i40e_status_code
7917 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7918 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7919 uint16_t count, uint16_t rule_id)
7921 struct i40e_aq_desc desc;
7922 struct i40e_aqc_add_delete_mirror_rule cmd;
7923 uint16_t buff_len = 0;
7924 enum i40e_status_code status;
7927 i40e_fill_default_direct_cmd_desc(&desc,
7928 i40e_aqc_opc_delete_mirror_rule);
7929 memset(&cmd, 0, sizeof(cmd));
7930 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7931 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7933 cmd.num_entries = count;
7934 buff_len = sizeof(uint16_t) * count;
7935 desc.datalen = rte_cpu_to_le_16(buff_len);
7936 buff = (void *)entries;
7938 /* rule id is filled in destination field for deleting mirror rule */
7939 cmd.destination = rte_cpu_to_le_16(rule_id);
7941 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7942 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7943 cmd.seid = rte_cpu_to_le_16(seid);
7945 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7946 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7952 * i40e_mirror_rule_set
7953 * @dev: pointer to the hardware structure
7954 * @mirror_conf: mirror rule info
7955 * @sw_id: mirror rule's sw_id
7956 * @on: enable/disable
7958 * set a mirror rule.
7962 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7963 struct rte_eth_mirror_conf *mirror_conf,
7964 uint8_t sw_id, uint8_t on)
7966 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7967 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7968 struct i40e_mirror_rule *it, *mirr_rule = NULL;
7969 struct i40e_mirror_rule *parent = NULL;
7970 uint16_t seid, dst_seid, rule_id;
7974 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7976 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7977 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7978 " without veb or vfs.");
7981 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7982 PMD_DRV_LOG(ERR, "mirror table is full.");
7985 if (mirror_conf->dst_pool > pf->vf_num) {
7986 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7987 mirror_conf->dst_pool);
7991 seid = pf->main_vsi->veb->seid;
7993 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7994 if (sw_id <= it->index) {
8000 if (mirr_rule && sw_id == mirr_rule->index) {
8002 PMD_DRV_LOG(ERR, "mirror rule exists.");
8005 ret = i40e_aq_del_mirror_rule(hw, seid,
8006 mirr_rule->rule_type,
8008 mirr_rule->num_entries, mirr_rule->id);
8010 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8011 " ret = %d, aq_err = %d.",
8012 ret, hw->aq.asq_last_status);
8015 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8016 rte_free(mirr_rule);
8017 pf->nb_mirror_rule--;
8021 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8025 mirr_rule = rte_zmalloc("i40e_mirror_rule",
8026 sizeof(struct i40e_mirror_rule) , 0);
8028 PMD_DRV_LOG(ERR, "failed to allocate memory");
8029 return I40E_ERR_NO_MEMORY;
8031 switch (mirror_conf->rule_type) {
8032 case ETH_MIRROR_VLAN:
8033 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8034 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8035 mirr_rule->entries[j] =
8036 mirror_conf->vlan.vlan_id[i];
8041 PMD_DRV_LOG(ERR, "vlan is not specified.");
8042 rte_free(mirr_rule);
8045 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8047 case ETH_MIRROR_VIRTUAL_POOL_UP:
8048 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8049 /* check if the specified pool bit is out of range */
8050 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8051 PMD_DRV_LOG(ERR, "pool mask is out of range.");
8052 rte_free(mirr_rule);
8055 for (i = 0, j = 0; i < pf->vf_num; i++) {
8056 if (mirror_conf->pool_mask & (1ULL << i)) {
8057 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8061 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8062 /* add pf vsi to entries */
8063 mirr_rule->entries[j] = pf->main_vsi_seid;
8067 PMD_DRV_LOG(ERR, "pool is not specified.");
8068 rte_free(mirr_rule);
8071 /* egress and ingress in aq commands means from switch but not port */
8072 mirr_rule->rule_type =
8073 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8074 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8075 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8077 case ETH_MIRROR_UPLINK_PORT:
8078 /* egress and ingress in aq commands means from switch but not port*/
8079 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8081 case ETH_MIRROR_DOWNLINK_PORT:
8082 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8085 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8086 mirror_conf->rule_type);
8087 rte_free(mirr_rule);
8091 /* If the dst_pool is equal to vf_num, consider it as PF */
8092 if (mirror_conf->dst_pool == pf->vf_num)
8093 dst_seid = pf->main_vsi_seid;
8095 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8097 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8098 mirr_rule->rule_type, mirr_rule->entries,
8101 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8102 " ret = %d, aq_err = %d.",
8103 ret, hw->aq.asq_last_status);
8104 rte_free(mirr_rule);
8108 mirr_rule->index = sw_id;
8109 mirr_rule->num_entries = j;
8110 mirr_rule->id = rule_id;
8111 mirr_rule->dst_vsi_seid = dst_seid;
8114 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8116 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8118 pf->nb_mirror_rule++;
8123 * i40e_mirror_rule_reset
8124 * @dev: pointer to the device
8125 * @sw_id: mirror rule's sw_id
8127 * reset a mirror rule.
8131 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8133 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8134 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8135 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8139 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8141 seid = pf->main_vsi->veb->seid;
8143 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8144 if (sw_id == it->index) {
8150 ret = i40e_aq_del_mirror_rule(hw, seid,
8151 mirr_rule->rule_type,
8153 mirr_rule->num_entries, mirr_rule->id);
8155 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8156 " status = %d, aq_err = %d.",
8157 ret, hw->aq.asq_last_status);
8160 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8161 rte_free(mirr_rule);
8162 pf->nb_mirror_rule--;
8164 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8171 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8173 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8174 uint64_t systim_cycles;
8176 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8177 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8180 return systim_cycles;
8184 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8186 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8189 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8190 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8197 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8199 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8202 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8203 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8210 i40e_start_timecounters(struct rte_eth_dev *dev)
8212 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8213 struct i40e_adapter *adapter =
8214 (struct i40e_adapter *)dev->data->dev_private;
8215 struct rte_eth_link link;
8216 uint32_t tsync_inc_l;
8217 uint32_t tsync_inc_h;
8219 /* Get current link speed. */
8220 memset(&link, 0, sizeof(link));
8221 i40e_dev_link_update(dev, 1);
8222 rte_i40e_dev_atomic_read_link_status(dev, &link);
8224 switch (link.link_speed) {
8225 case ETH_SPEED_NUM_40G:
8226 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8227 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8229 case ETH_SPEED_NUM_10G:
8230 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8231 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8233 case ETH_SPEED_NUM_1G:
8234 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8235 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8242 /* Set the timesync increment value. */
8243 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8244 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8246 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8247 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8248 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8250 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8251 adapter->systime_tc.cc_shift = 0;
8252 adapter->systime_tc.nsec_mask = 0;
8254 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8255 adapter->rx_tstamp_tc.cc_shift = 0;
8256 adapter->rx_tstamp_tc.nsec_mask = 0;
8258 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8259 adapter->tx_tstamp_tc.cc_shift = 0;
8260 adapter->tx_tstamp_tc.nsec_mask = 0;
8264 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8266 struct i40e_adapter *adapter =
8267 (struct i40e_adapter *)dev->data->dev_private;
8269 adapter->systime_tc.nsec += delta;
8270 adapter->rx_tstamp_tc.nsec += delta;
8271 adapter->tx_tstamp_tc.nsec += delta;
8277 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8280 struct i40e_adapter *adapter =
8281 (struct i40e_adapter *)dev->data->dev_private;
8283 ns = rte_timespec_to_ns(ts);
8285 /* Set the timecounters to a new value. */
8286 adapter->systime_tc.nsec = ns;
8287 adapter->rx_tstamp_tc.nsec = ns;
8288 adapter->tx_tstamp_tc.nsec = ns;
8294 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8296 uint64_t ns, systime_cycles;
8297 struct i40e_adapter *adapter =
8298 (struct i40e_adapter *)dev->data->dev_private;
8300 systime_cycles = i40e_read_systime_cyclecounter(dev);
8301 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8302 *ts = rte_ns_to_timespec(ns);
8308 i40e_timesync_enable(struct rte_eth_dev *dev)
8310 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8311 uint32_t tsync_ctl_l;
8312 uint32_t tsync_ctl_h;
8314 /* Stop the timesync system time. */
8315 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8316 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8317 /* Reset the timesync system time value. */
8318 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8319 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8321 i40e_start_timecounters(dev);
8323 /* Clear timesync registers. */
8324 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8325 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8326 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8327 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8328 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8329 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8331 /* Enable timestamping of PTP packets. */
8332 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8333 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8335 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8336 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8337 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8339 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8340 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8346 i40e_timesync_disable(struct rte_eth_dev *dev)
8348 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8349 uint32_t tsync_ctl_l;
8350 uint32_t tsync_ctl_h;
8352 /* Disable timestamping of transmitted PTP packets. */
8353 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8354 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8356 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8357 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8359 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8360 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8362 /* Reset the timesync increment value. */
8363 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8364 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8370 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8371 struct timespec *timestamp, uint32_t flags)
8373 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8374 struct i40e_adapter *adapter =
8375 (struct i40e_adapter *)dev->data->dev_private;
8377 uint32_t sync_status;
8378 uint32_t index = flags & 0x03;
8379 uint64_t rx_tstamp_cycles;
8382 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8383 if ((sync_status & (1 << index)) == 0)
8386 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8387 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8388 *timestamp = rte_ns_to_timespec(ns);
8394 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8395 struct timespec *timestamp)
8397 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8398 struct i40e_adapter *adapter =
8399 (struct i40e_adapter *)dev->data->dev_private;
8401 uint32_t sync_status;
8402 uint64_t tx_tstamp_cycles;
8405 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8406 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8409 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8410 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8411 *timestamp = rte_ns_to_timespec(ns);
8417 * i40e_parse_dcb_configure - parse dcb configure from user
8418 * @dev: the device being configured
8419 * @dcb_cfg: pointer of the result of parse
8420 * @*tc_map: bit map of enabled traffic classes
8422 * Returns 0 on success, negative value on failure
8425 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8426 struct i40e_dcbx_config *dcb_cfg,
8429 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8430 uint8_t i, tc_bw, bw_lf;
8432 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8434 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8435 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8436 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8440 /* assume each tc has the same bw */
8441 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8442 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8443 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8444 /* to ensure the sum of tcbw is equal to 100 */
8445 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8446 for (i = 0; i < bw_lf; i++)
8447 dcb_cfg->etscfg.tcbwtable[i]++;
8449 /* assume each tc has the same Transmission Selection Algorithm */
8450 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8451 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8453 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8454 dcb_cfg->etscfg.prioritytable[i] =
8455 dcb_rx_conf->dcb_tc[i];
8457 /* FW needs one App to configure HW */
8458 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8459 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8460 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8461 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8463 if (dcb_rx_conf->nb_tcs == 0)
8464 *tc_map = 1; /* tc0 only */
8466 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8468 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8469 dcb_cfg->pfc.willing = 0;
8470 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8471 dcb_cfg->pfc.pfcenable = *tc_map;
8477 static enum i40e_status_code
8478 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8479 struct i40e_aqc_vsi_properties_data *info,
8480 uint8_t enabled_tcmap)
8482 enum i40e_status_code ret;
8483 int i, total_tc = 0;
8484 uint16_t qpnum_per_tc, bsf, qp_idx;
8485 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8486 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8487 uint16_t used_queues;
8489 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8490 if (ret != I40E_SUCCESS)
8493 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8494 if (enabled_tcmap & (1 << i))
8499 vsi->enabled_tc = enabled_tcmap;
8501 /* different VSI has different queues assigned */
8502 if (vsi->type == I40E_VSI_MAIN)
8503 used_queues = dev_data->nb_rx_queues -
8504 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8505 else if (vsi->type == I40E_VSI_VMDQ2)
8506 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8508 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8509 return I40E_ERR_NO_AVAILABLE_VSI;
8512 qpnum_per_tc = used_queues / total_tc;
8513 /* Number of queues per enabled TC */
8514 if (qpnum_per_tc == 0) {
8515 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8516 return I40E_ERR_INVALID_QP_ID;
8518 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8520 bsf = rte_bsf32(qpnum_per_tc);
8523 * Configure TC and queue mapping parameters, for enabled TC,
8524 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8525 * default queue will serve it.
8528 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8529 if (vsi->enabled_tc & (1 << i)) {
8530 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8531 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8532 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8533 qp_idx += qpnum_per_tc;
8535 info->tc_mapping[i] = 0;
8538 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8539 if (vsi->type == I40E_VSI_SRIOV) {
8540 info->mapping_flags |=
8541 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8542 for (i = 0; i < vsi->nb_qps; i++)
8543 info->queue_mapping[i] =
8544 rte_cpu_to_le_16(vsi->base_queue + i);
8546 info->mapping_flags |=
8547 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8548 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8550 info->valid_sections |=
8551 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8553 return I40E_SUCCESS;
8557 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8558 * @veb: VEB to be configured
8559 * @tc_map: enabled TC bitmap
8561 * Returns 0 on success, negative value on failure
8563 static enum i40e_status_code
8564 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8566 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8567 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8568 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8569 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8570 enum i40e_status_code ret = I40E_SUCCESS;
8574 /* Check if enabled_tc is same as existing or new TCs */
8575 if (veb->enabled_tc == tc_map)
8578 /* configure tc bandwidth */
8579 memset(&veb_bw, 0, sizeof(veb_bw));
8580 veb_bw.tc_valid_bits = tc_map;
8581 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8582 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8583 if (tc_map & BIT_ULL(i))
8584 veb_bw.tc_bw_share_credits[i] = 1;
8586 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8589 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8590 " per TC failed = %d",
8591 hw->aq.asq_last_status);
8595 memset(&ets_query, 0, sizeof(ets_query));
8596 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8598 if (ret != I40E_SUCCESS) {
8599 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8600 " configuration %u", hw->aq.asq_last_status);
8603 memset(&bw_query, 0, sizeof(bw_query));
8604 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8606 if (ret != I40E_SUCCESS) {
8607 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8608 " configuration %u", hw->aq.asq_last_status);
8612 /* store and print out BW info */
8613 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8614 veb->bw_info.bw_max = ets_query.tc_bw_max;
8615 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8616 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8617 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8618 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8620 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8621 veb->bw_info.bw_ets_share_credits[i] =
8622 bw_query.tc_bw_share_credits[i];
8623 veb->bw_info.bw_ets_credits[i] =
8624 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8625 /* 4 bits per TC, 4th bit is reserved */
8626 veb->bw_info.bw_ets_max[i] =
8627 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8628 RTE_LEN2MASK(3, uint8_t));
8629 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8630 veb->bw_info.bw_ets_share_credits[i]);
8631 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8632 veb->bw_info.bw_ets_credits[i]);
8633 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8634 veb->bw_info.bw_ets_max[i]);
8637 veb->enabled_tc = tc_map;
8644 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8645 * @vsi: VSI to be configured
8646 * @tc_map: enabled TC bitmap
8648 * Returns 0 on success, negative value on failure
8650 static enum i40e_status_code
8651 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8653 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8654 struct i40e_vsi_context ctxt;
8655 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8656 enum i40e_status_code ret = I40E_SUCCESS;
8659 /* Check if enabled_tc is same as existing or new TCs */
8660 if (vsi->enabled_tc == tc_map)
8663 /* configure tc bandwidth */
8664 memset(&bw_data, 0, sizeof(bw_data));
8665 bw_data.tc_valid_bits = tc_map;
8666 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8667 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8668 if (tc_map & BIT_ULL(i))
8669 bw_data.tc_bw_credits[i] = 1;
8671 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8673 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8674 " per TC failed = %d",
8675 hw->aq.asq_last_status);
8678 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8679 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8681 /* Update Queue Pairs Mapping for currently enabled UPs */
8682 ctxt.seid = vsi->seid;
8683 ctxt.pf_num = hw->pf_id;
8685 ctxt.uplink_seid = vsi->uplink_seid;
8686 ctxt.info = vsi->info;
8688 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8692 /* Update the VSI after updating the VSI queue-mapping information */
8693 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8695 PMD_INIT_LOG(ERR, "Failed to configure "
8696 "TC queue mapping = %d",
8697 hw->aq.asq_last_status);
8700 /* update the local VSI info with updated queue map */
8701 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8702 sizeof(vsi->info.tc_mapping));
8703 (void)rte_memcpy(&vsi->info.queue_mapping,
8704 &ctxt.info.queue_mapping,
8705 sizeof(vsi->info.queue_mapping));
8706 vsi->info.mapping_flags = ctxt.info.mapping_flags;
8707 vsi->info.valid_sections = 0;
8709 /* query and update current VSI BW information */
8710 ret = i40e_vsi_get_bw_config(vsi);
8713 "Failed updating vsi bw info, err %s aq_err %s",
8714 i40e_stat_str(hw, ret),
8715 i40e_aq_str(hw, hw->aq.asq_last_status));
8719 vsi->enabled_tc = tc_map;
8726 * i40e_dcb_hw_configure - program the dcb setting to hw
8727 * @pf: pf the configuration is taken on
8728 * @new_cfg: new configuration
8729 * @tc_map: enabled TC bitmap
8731 * Returns 0 on success, negative value on failure
8733 static enum i40e_status_code
8734 i40e_dcb_hw_configure(struct i40e_pf *pf,
8735 struct i40e_dcbx_config *new_cfg,
8738 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8739 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8740 struct i40e_vsi *main_vsi = pf->main_vsi;
8741 struct i40e_vsi_list *vsi_list;
8742 enum i40e_status_code ret;
8746 /* Use the FW API if FW > v4.4*/
8747 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8748 (hw->aq.fw_maj_ver >= 5))) {
8749 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8750 " to configure DCB");
8751 return I40E_ERR_FIRMWARE_API_VERSION;
8754 /* Check if need reconfiguration */
8755 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8756 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8757 return I40E_SUCCESS;
8760 /* Copy the new config to the current config */
8761 *old_cfg = *new_cfg;
8762 old_cfg->etsrec = old_cfg->etscfg;
8763 ret = i40e_set_dcb_config(hw);
8766 "Set DCB Config failed, err %s aq_err %s\n",
8767 i40e_stat_str(hw, ret),
8768 i40e_aq_str(hw, hw->aq.asq_last_status));
8771 /* set receive Arbiter to RR mode and ETS scheme by default */
8772 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8773 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8774 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
8775 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8776 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8777 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8778 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8779 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8780 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8781 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8782 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8783 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8784 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8786 /* get local mib to check whether it is configured correctly */
8788 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8789 /* Get Local DCB Config */
8790 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8791 &hw->local_dcbx_config);
8793 /* if Veb is created, need to update TC of it at first */
8794 if (main_vsi->veb) {
8795 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8797 PMD_INIT_LOG(WARNING,
8798 "Failed configuring TC for VEB seid=%d\n",
8799 main_vsi->veb->seid);
8801 /* Update each VSI */
8802 i40e_vsi_config_tc(main_vsi, tc_map);
8803 if (main_vsi->veb) {
8804 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8805 /* Beside main VSI and VMDQ VSIs, only enable default
8808 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8809 ret = i40e_vsi_config_tc(vsi_list->vsi,
8812 ret = i40e_vsi_config_tc(vsi_list->vsi,
8813 I40E_DEFAULT_TCMAP);
8815 PMD_INIT_LOG(WARNING,
8816 "Failed configuring TC for VSI seid=%d\n",
8817 vsi_list->vsi->seid);
8821 return I40E_SUCCESS;
8825 * i40e_dcb_init_configure - initial dcb config
8826 * @dev: device being configured
8827 * @sw_dcb: indicate whether dcb is sw configured or hw offload
8829 * Returns 0 on success, negative value on failure
8832 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8834 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8835 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8838 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8839 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8843 /* DCB initialization:
8844 * Update DCB configuration from the Firmware and configure
8845 * LLDP MIB change event.
8847 if (sw_dcb == TRUE) {
8848 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8849 if (ret != I40E_SUCCESS)
8850 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8852 ret = i40e_init_dcb(hw);
8853 /* if sw_dcb, lldp agent is stopped, the return from
8854 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8857 if (ret != I40E_SUCCESS &&
8858 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8859 memset(&hw->local_dcbx_config, 0,
8860 sizeof(struct i40e_dcbx_config));
8861 /* set dcb default configuration */
8862 hw->local_dcbx_config.etscfg.willing = 0;
8863 hw->local_dcbx_config.etscfg.maxtcs = 0;
8864 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8865 hw->local_dcbx_config.etscfg.tsatable[0] =
8867 hw->local_dcbx_config.etsrec =
8868 hw->local_dcbx_config.etscfg;
8869 hw->local_dcbx_config.pfc.willing = 0;
8870 hw->local_dcbx_config.pfc.pfccap =
8871 I40E_MAX_TRAFFIC_CLASS;
8872 /* FW needs one App to configure HW */
8873 hw->local_dcbx_config.numapps = 1;
8874 hw->local_dcbx_config.app[0].selector =
8875 I40E_APP_SEL_ETHTYPE;
8876 hw->local_dcbx_config.app[0].priority = 3;
8877 hw->local_dcbx_config.app[0].protocolid =
8878 I40E_APP_PROTOID_FCOE;
8879 ret = i40e_set_dcb_config(hw);
8881 PMD_INIT_LOG(ERR, "default dcb config fails."
8882 " err = %d, aq_err = %d.", ret,
8883 hw->aq.asq_last_status);
8887 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8888 " aq_err = %d.", ret,
8889 hw->aq.asq_last_status);
8893 ret = i40e_aq_start_lldp(hw, NULL);
8894 if (ret != I40E_SUCCESS)
8895 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8897 ret = i40e_init_dcb(hw);
8899 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8900 PMD_INIT_LOG(ERR, "HW doesn't support"
8905 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8906 " aq_err = %d.", ret,
8907 hw->aq.asq_last_status);
8915 * i40e_dcb_setup - setup dcb related config
8916 * @dev: device being configured
8918 * Returns 0 on success, negative value on failure
8921 i40e_dcb_setup(struct rte_eth_dev *dev)
8923 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8924 struct i40e_dcbx_config dcb_cfg;
8928 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8929 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8933 if (pf->vf_num != 0)
8934 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8936 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8938 PMD_INIT_LOG(ERR, "invalid dcb config");
8941 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8943 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8951 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8952 struct rte_eth_dcb_info *dcb_info)
8954 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8955 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8956 struct i40e_vsi *vsi = pf->main_vsi;
8957 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8958 uint16_t bsf, tc_mapping;
8961 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8962 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8964 dcb_info->nb_tcs = 1;
8965 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8966 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8967 for (i = 0; i < dcb_info->nb_tcs; i++)
8968 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8970 /* get queue mapping if vmdq is disabled */
8971 if (!pf->nb_cfg_vmdq_vsi) {
8972 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8973 if (!(vsi->enabled_tc & (1 << i)))
8975 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8976 dcb_info->tc_queue.tc_rxq[j][i].base =
8977 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8978 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8979 dcb_info->tc_queue.tc_txq[j][i].base =
8980 dcb_info->tc_queue.tc_rxq[j][i].base;
8981 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8982 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8983 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8984 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8985 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8990 /* get queue mapping if vmdq is enabled */
8992 vsi = pf->vmdq[j].vsi;
8993 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8994 if (!(vsi->enabled_tc & (1 << i)))
8996 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8997 dcb_info->tc_queue.tc_rxq[j][i].base =
8998 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8999 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9000 dcb_info->tc_queue.tc_txq[j][i].base =
9001 dcb_info->tc_queue.tc_rxq[j][i].base;
9002 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9003 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9004 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9005 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9006 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9009 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9014 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9016 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9017 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9019 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9022 msix_intr = intr_handle->intr_vec[queue_id];
9023 if (msix_intr == I40E_MISC_VEC_ID)
9024 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9025 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9026 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9027 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9029 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9032 I40E_PFINT_DYN_CTLN(msix_intr -
9034 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9035 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9036 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9038 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9040 I40E_WRITE_FLUSH(hw);
9041 rte_intr_enable(&dev->pci_dev->intr_handle);
9047 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9049 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9050 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9053 msix_intr = intr_handle->intr_vec[queue_id];
9054 if (msix_intr == I40E_MISC_VEC_ID)
9055 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9058 I40E_PFINT_DYN_CTLN(msix_intr -
9061 I40E_WRITE_FLUSH(hw);
9066 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
9068 /* Highest base addr + 32-bit word */
9069 return I40E_GLGEN_STAT_CLEAR + 4;
9072 static int i40e_get_regs(struct rte_eth_dev *dev,
9073 struct rte_dev_reg_info *regs)
9075 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9076 uint32_t *ptr_data = regs->data;
9077 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9078 const struct i40e_reg_info *reg_info;
9080 /* The first few registers have to be read using AQ operations */
9082 while (i40e_regs_adminq[reg_idx].name) {
9083 reg_info = &i40e_regs_adminq[reg_idx++];
9084 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9086 arr_idx2 <= reg_info->count2;
9088 reg_offset = arr_idx * reg_info->stride1 +
9089 arr_idx2 * reg_info->stride2;
9090 reg_offset += reg_info->base_addr;
9091 ptr_data[reg_offset >> 2] =
9092 i40e_read_rx_ctl(hw, reg_offset);
9096 /* The remaining registers can be read using primitives */
9098 while (i40e_regs_others[reg_idx].name) {
9099 reg_info = &i40e_regs_others[reg_idx++];
9100 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9102 arr_idx2 <= reg_info->count2;
9104 reg_offset = arr_idx * reg_info->stride1 +
9105 arr_idx2 * reg_info->stride2;
9106 reg_offset += reg_info->base_addr;
9107 ptr_data[reg_offset >> 2] =
9108 I40E_READ_REG(hw, reg_offset);
9115 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9117 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9119 /* Convert word count to byte count */
9120 return hw->nvm.sr_size << 1;
9123 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9124 struct rte_dev_eeprom_info *eeprom)
9126 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9127 uint16_t *data = eeprom->data;
9128 uint16_t offset, length, cnt_words;
9131 offset = eeprom->offset >> 1;
9132 length = eeprom->length >> 1;
9135 if (offset > hw->nvm.sr_size ||
9136 offset + length > hw->nvm.sr_size) {
9137 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9141 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9143 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9144 if (ret_code != I40E_SUCCESS || cnt_words != length) {
9145 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9152 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9153 struct ether_addr *mac_addr)
9155 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9157 if (!is_valid_assigned_ether_addr(mac_addr)) {
9158 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9162 /* Flags: 0x3 updates port address */
9163 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);