4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memzone.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_alarm.h>
54 #include <rte_eth_ctrl.h>
55 #include <rte_tailq.h>
56 #include <rte_hash_crc.h>
58 #include "i40e_logs.h"
59 #include "base/i40e_prototype.h"
60 #include "base/i40e_adminq_cmd.h"
61 #include "base/i40e_type.h"
62 #include "base/i40e_register.h"
63 #include "base/i40e_dcb.h"
64 #include "i40e_ethdev.h"
65 #include "i40e_rxtx.h"
67 #include "i40e_regs.h"
69 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
70 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
72 #define I40E_CLEAR_PXE_WAIT_MS 200
74 /* Maximun number of capability elements */
75 #define I40E_MAX_CAP_ELE_NUM 128
77 /* Wait count and interval */
78 #define I40E_CHK_Q_ENA_COUNT 1000
79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
81 /* Maximun number of VSI */
82 #define I40E_MAX_NUM_VSIS (384UL)
84 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
86 /* Flow control default timer */
87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
89 /* Flow control default high water */
90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
92 /* Flow control default low water */
93 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
95 /* Flow control enable fwd bit */
96 #define I40E_PRTMAC_FWD_CTRL 0x00000001
98 /* Receive Packet Buffer size */
99 #define I40E_RXPBSIZE (968 * 1024)
101 /* Kilobytes shift */
102 #define I40E_KILOSHIFT 10
104 /* Receive Average Packet Size in Byte*/
105 #define I40E_PACKET_AVERAGE_SIZE 128
107 /* Mask of PF interrupt causes */
108 #define I40E_PFINT_ICR0_ENA_MASK ( \
109 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_GRST_MASK | \
112 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
113 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 /* Additional timesync values. */
133 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
134 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
135 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
136 #define I40E_PRTTSYN_TSYNENA 0x80000000
137 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
140 #define I40E_MAX_PERCENT 100
141 #define I40E_DEFAULT_DCB_APP_NUM 1
142 #define I40E_DEFAULT_DCB_APP_PRIO 3
145 * Below are values for writing un-exposed registers suggested
148 /* Destination MAC address */
149 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
150 /* Source MAC address */
151 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
153 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
155 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
156 /* Single VLAN tag in the inner L2 header */
157 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
158 /* Source IPv4 address */
159 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
160 /* Destination IPv4 address */
161 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
162 /* Source IPv4 address for X722 */
163 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
164 /* Destination IPv4 address for X722 */
165 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
166 /* IPv4 Protocol for X722 */
167 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
168 /* IPv4 Time to Live for X722 */
169 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
170 /* IPv4 Type of Service (TOS) */
171 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
173 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
174 /* IPv4 Time to Live */
175 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
176 /* Source IPv6 address */
177 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
178 /* Destination IPv6 address */
179 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
180 /* IPv6 Traffic Class (TC) */
181 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
182 /* IPv6 Next Header */
183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
187 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
188 /* Destination L4 port */
189 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
190 /* SCTP verification tag */
191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
194 /* Source port of tunneling UDP */
195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
196 /* Destination port of tunneling UDP */
197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
198 /* UDP Tunneling ID, NVGRE/GRE key */
199 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
200 /* Last ether type */
201 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
202 /* Tunneling outer destination IPv4 address */
203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
204 /* Tunneling outer destination IPv6 address */
205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
206 /* 1st word of flex payload */
207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
208 /* 2nd word of flex payload */
209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
210 /* 3rd word of flex payload */
211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
212 /* 4th word of flex payload */
213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
214 /* 5th word of flex payload */
215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
216 /* 6th word of flex payload */
217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
218 /* 7th word of flex payload */
219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
220 /* 8th word of flex payload */
221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
222 /* all 8 words flex payload */
223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
224 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
226 #define I40E_TRANSLATE_INSET 0
227 #define I40E_TRANSLATE_REG 1
229 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
230 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
231 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
232 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
234 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
236 /* PCI offset for querying capability */
237 #define PCI_DEV_CAP_REG 0xA4
238 /* PCI offset for enabling/disabling Extended Tag */
239 #define PCI_DEV_CTRL_REG 0xA8
240 /* Bit mask of Extended Tag capability */
241 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
242 /* Bit shift of Extended Tag enable/disable */
243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
244 /* Bit mask of Extended Tag enable/disable */
245 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int i40e_dev_configure(struct rte_eth_dev *dev);
250 static int i40e_dev_start(struct rte_eth_dev *dev);
251 static void i40e_dev_stop(struct rte_eth_dev *dev);
252 static void i40e_dev_close(struct rte_eth_dev *dev);
253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
260 struct rte_eth_stats *stats);
261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
262 struct rte_eth_xstat *xstats, unsigned n);
263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
264 struct rte_eth_xstat_name *xstats_names,
266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
272 char *fw_version, size_t fw_size);
273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
274 struct rte_eth_dev_info *dev_info);
275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
279 enum rte_vlan_type vlan_type,
281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
289 struct rte_eth_fc_conf *fc_conf);
290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
291 struct rte_eth_fc_conf *fc_conf);
292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
293 struct rte_eth_pfc_conf *pfc_conf);
294 static int i40e_macaddr_add(struct rte_eth_dev *dev,
295 struct ether_addr *mac_addr,
298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
300 struct rte_eth_rss_reta_entry64 *reta_conf,
302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
303 struct rte_eth_rss_reta_entry64 *reta_conf,
306 static int i40e_get_cap(struct i40e_hw *hw);
307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
308 static int i40e_pf_setup(struct i40e_pf *pf);
309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
314 bool offset_loaded, uint64_t *offset, uint64_t *stat);
315 static void i40e_stat_update_48(struct i40e_hw *hw,
321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
322 static void i40e_dev_interrupt_handler(void *param);
323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
324 uint32_t base, uint32_t num);
325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
331 static int i40e_veb_release(struct i40e_veb *veb);
332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
333 struct i40e_vsi *vsi);
334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
337 struct i40e_macvlan_filter *mv_f,
340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
342 struct rte_eth_rss_conf *rss_conf);
343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
344 struct rte_eth_rss_conf *rss_conf);
345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
346 struct rte_eth_udp_tunnel *udp_tunnel);
347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
348 struct rte_eth_udp_tunnel *udp_tunnel);
349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
351 enum rte_filter_op filter_op,
353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
354 enum rte_filter_type filter_type,
355 enum rte_filter_op filter_op,
357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
358 struct rte_eth_dcb_info *dcb_info);
359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
360 static void i40e_configure_registers(struct i40e_hw *hw);
361 static void i40e_hw_init(struct rte_eth_dev *dev);
362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
364 struct rte_eth_mirror_conf *mirror_conf,
365 uint8_t sw_id, uint8_t on);
366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
371 struct timespec *timestamp,
373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
374 struct timespec *timestamp);
375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
380 struct timespec *timestamp);
381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
382 const struct timespec *timestamp);
384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
389 static int i40e_get_regs(struct rte_eth_dev *dev,
390 struct rte_dev_reg_info *regs);
392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
395 struct rte_dev_eeprom_info *eeprom);
397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
398 struct ether_addr *mac_addr);
400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
402 static int i40e_ethertype_filter_convert(
403 const struct rte_eth_ethertype_filter *input,
404 struct i40e_ethertype_filter *filter);
405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
406 struct i40e_ethertype_filter *filter);
408 static int i40e_tunnel_filter_convert(
409 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
410 struct i40e_tunnel_filter *tunnel_filter);
411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
412 struct i40e_tunnel_filter *tunnel_filter);
413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
417 static void i40e_filter_restore(struct i40e_pf *pf);
418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
420 int i40e_logtype_init;
421 int i40e_logtype_driver;
423 static const struct rte_pci_id pci_id_i40e_map[] = {
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
444 { .vendor_id = 0, /* sentinel */ },
447 static const struct eth_dev_ops i40e_eth_dev_ops = {
448 .dev_configure = i40e_dev_configure,
449 .dev_start = i40e_dev_start,
450 .dev_stop = i40e_dev_stop,
451 .dev_close = i40e_dev_close,
452 .promiscuous_enable = i40e_dev_promiscuous_enable,
453 .promiscuous_disable = i40e_dev_promiscuous_disable,
454 .allmulticast_enable = i40e_dev_allmulticast_enable,
455 .allmulticast_disable = i40e_dev_allmulticast_disable,
456 .dev_set_link_up = i40e_dev_set_link_up,
457 .dev_set_link_down = i40e_dev_set_link_down,
458 .link_update = i40e_dev_link_update,
459 .stats_get = i40e_dev_stats_get,
460 .xstats_get = i40e_dev_xstats_get,
461 .xstats_get_names = i40e_dev_xstats_get_names,
462 .stats_reset = i40e_dev_stats_reset,
463 .xstats_reset = i40e_dev_stats_reset,
464 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
465 .fw_version_get = i40e_fw_version_get,
466 .dev_infos_get = i40e_dev_info_get,
467 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
468 .vlan_filter_set = i40e_vlan_filter_set,
469 .vlan_tpid_set = i40e_vlan_tpid_set,
470 .vlan_offload_set = i40e_vlan_offload_set,
471 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
472 .vlan_pvid_set = i40e_vlan_pvid_set,
473 .rx_queue_start = i40e_dev_rx_queue_start,
474 .rx_queue_stop = i40e_dev_rx_queue_stop,
475 .tx_queue_start = i40e_dev_tx_queue_start,
476 .tx_queue_stop = i40e_dev_tx_queue_stop,
477 .rx_queue_setup = i40e_dev_rx_queue_setup,
478 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
479 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
480 .rx_queue_release = i40e_dev_rx_queue_release,
481 .rx_queue_count = i40e_dev_rx_queue_count,
482 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
483 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
484 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
485 .tx_queue_setup = i40e_dev_tx_queue_setup,
486 .tx_queue_release = i40e_dev_tx_queue_release,
487 .dev_led_on = i40e_dev_led_on,
488 .dev_led_off = i40e_dev_led_off,
489 .flow_ctrl_get = i40e_flow_ctrl_get,
490 .flow_ctrl_set = i40e_flow_ctrl_set,
491 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
492 .mac_addr_add = i40e_macaddr_add,
493 .mac_addr_remove = i40e_macaddr_remove,
494 .reta_update = i40e_dev_rss_reta_update,
495 .reta_query = i40e_dev_rss_reta_query,
496 .rss_hash_update = i40e_dev_rss_hash_update,
497 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
498 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
499 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
500 .filter_ctrl = i40e_dev_filter_ctrl,
501 .rxq_info_get = i40e_rxq_info_get,
502 .txq_info_get = i40e_txq_info_get,
503 .mirror_rule_set = i40e_mirror_rule_set,
504 .mirror_rule_reset = i40e_mirror_rule_reset,
505 .timesync_enable = i40e_timesync_enable,
506 .timesync_disable = i40e_timesync_disable,
507 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
508 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
509 .get_dcb_info = i40e_dev_get_dcb_info,
510 .timesync_adjust_time = i40e_timesync_adjust_time,
511 .timesync_read_time = i40e_timesync_read_time,
512 .timesync_write_time = i40e_timesync_write_time,
513 .get_reg = i40e_get_regs,
514 .get_eeprom_length = i40e_get_eeprom_length,
515 .get_eeprom = i40e_get_eeprom,
516 .mac_addr_set = i40e_set_default_mac_addr,
517 .mtu_set = i40e_dev_mtu_set,
520 /* store statistics names and its offset in stats structure */
521 struct rte_i40e_xstats_name_off {
522 char name[RTE_ETH_XSTATS_NAME_SIZE];
526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
527 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
528 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
529 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
530 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
531 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
532 rx_unknown_protocol)},
533 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
534 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
535 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
536 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
539 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
540 sizeof(rte_i40e_stats_strings[0]))
542 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
543 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
544 tx_dropped_link_down)},
545 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
546 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
548 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
549 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
551 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
553 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
555 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
556 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
557 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
558 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
559 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
560 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
574 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
576 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
577 mac_short_packet_dropped)},
578 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
580 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
581 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
582 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
592 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
594 {"rx_flow_director_atr_match_packets",
595 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
596 {"rx_flow_director_sb_match_packets",
597 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
598 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
600 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
602 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
604 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
608 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
609 sizeof(rte_i40e_hw_port_strings[0]))
611 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
612 {"xon_packets", offsetof(struct i40e_hw_port_stats,
614 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
618 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
619 sizeof(rte_i40e_rxq_prio_strings[0]))
621 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
622 {"xon_packets", offsetof(struct i40e_hw_port_stats,
624 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
626 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
627 priority_xon_2_xoff)},
630 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
631 sizeof(rte_i40e_txq_prio_strings[0]))
633 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
634 struct rte_pci_device *pci_dev)
636 return rte_eth_dev_pci_generic_probe(pci_dev,
637 sizeof(struct i40e_adapter), eth_i40e_dev_init);
640 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
642 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
645 static struct rte_pci_driver rte_i40e_pmd = {
646 .id_table = pci_id_i40e_map,
647 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
648 .probe = eth_i40e_pci_probe,
649 .remove = eth_i40e_pci_remove,
653 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
654 struct rte_eth_link *link)
656 struct rte_eth_link *dst = link;
657 struct rte_eth_link *src = &(dev->data->dev_link);
659 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
660 *(uint64_t *)src) == 0)
667 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
668 struct rte_eth_link *link)
670 struct rte_eth_link *dst = &(dev->data->dev_link);
671 struct rte_eth_link *src = link;
673 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
674 *(uint64_t *)src) == 0)
680 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
681 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
682 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
684 #ifndef I40E_GLQF_ORT
685 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
687 #ifndef I40E_GLQF_PIT
688 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
690 #ifndef I40E_GLQF_L3_MAP
691 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
694 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
697 * Initialize registers for flexible payload, which should be set by NVM.
698 * This should be removed from code once it is fixed in NVM.
700 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
701 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
702 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
703 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
704 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
705 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
706 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
707 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
708 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
710 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
711 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
713 /* Initialize registers for parsing packet type of QinQ */
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
715 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
718 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
721 * Add a ethertype filter to drop all flow control frames transmitted
725 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
727 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
728 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
729 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
730 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
733 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
734 I40E_FLOW_CONTROL_ETHERTYPE, flags,
735 pf->main_vsi_seid, 0,
739 "Failed to add filter to drop flow control frames from VSIs.");
743 floating_veb_list_handler(__rte_unused const char *key,
744 const char *floating_veb_value,
748 unsigned int count = 0;
751 bool *vf_floating_veb = opaque;
753 while (isblank(*floating_veb_value))
754 floating_veb_value++;
756 /* Reset floating VEB configuration for VFs */
757 for (idx = 0; idx < I40E_MAX_VF; idx++)
758 vf_floating_veb[idx] = false;
762 while (isblank(*floating_veb_value))
763 floating_veb_value++;
764 if (*floating_veb_value == '\0')
767 idx = strtoul(floating_veb_value, &end, 10);
768 if (errno || end == NULL)
770 while (isblank(*end))
774 } else if ((*end == ';') || (*end == '\0')) {
776 if (min == I40E_MAX_VF)
778 if (max >= I40E_MAX_VF)
779 max = I40E_MAX_VF - 1;
780 for (idx = min; idx <= max; idx++) {
781 vf_floating_veb[idx] = true;
788 floating_veb_value = end + 1;
789 } while (*end != '\0');
798 config_vf_floating_veb(struct rte_devargs *devargs,
799 uint16_t floating_veb,
800 bool *vf_floating_veb)
802 struct rte_kvargs *kvlist;
804 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
808 /* All the VFs attach to the floating VEB by default
809 * when the floating VEB is enabled.
811 for (i = 0; i < I40E_MAX_VF; i++)
812 vf_floating_veb[i] = true;
817 kvlist = rte_kvargs_parse(devargs->args, NULL);
821 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
822 rte_kvargs_free(kvlist);
825 /* When the floating_veb_list parameter exists, all the VFs
826 * will attach to the legacy VEB firstly, then configure VFs
827 * to the floating VEB according to the floating_veb_list.
829 if (rte_kvargs_process(kvlist, floating_veb_list,
830 floating_veb_list_handler,
831 vf_floating_veb) < 0) {
832 rte_kvargs_free(kvlist);
835 rte_kvargs_free(kvlist);
839 i40e_check_floating_handler(__rte_unused const char *key,
841 __rte_unused void *opaque)
843 if (strcmp(value, "1"))
850 is_floating_veb_supported(struct rte_devargs *devargs)
852 struct rte_kvargs *kvlist;
853 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
858 kvlist = rte_kvargs_parse(devargs->args, NULL);
862 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
863 rte_kvargs_free(kvlist);
866 /* Floating VEB is enabled when there's key-value:
867 * enable_floating_veb=1
869 if (rte_kvargs_process(kvlist, floating_veb_key,
870 i40e_check_floating_handler, NULL) < 0) {
871 rte_kvargs_free(kvlist);
874 rte_kvargs_free(kvlist);
880 config_floating_veb(struct rte_eth_dev *dev)
882 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
883 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
884 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
886 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
888 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
890 is_floating_veb_supported(pci_dev->device.devargs);
891 config_vf_floating_veb(pci_dev->device.devargs,
893 pf->floating_veb_list);
895 pf->floating_veb = false;
899 #define I40E_L2_TAGS_S_TAG_SHIFT 1
900 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
903 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
905 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
906 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
907 char ethertype_hash_name[RTE_HASH_NAMESIZE];
910 struct rte_hash_parameters ethertype_hash_params = {
911 .name = ethertype_hash_name,
912 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
913 .key_len = sizeof(struct i40e_ethertype_filter_input),
914 .hash_func = rte_hash_crc,
915 .hash_func_init_val = 0,
916 .socket_id = rte_socket_id(),
919 /* Initialize ethertype filter rule list and hash */
920 TAILQ_INIT(ðertype_rule->ethertype_list);
921 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
922 "ethertype_%s", dev->data->name);
923 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
924 if (!ethertype_rule->hash_table) {
925 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
928 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
929 sizeof(struct i40e_ethertype_filter *) *
930 I40E_MAX_ETHERTYPE_FILTER_NUM,
932 if (!ethertype_rule->hash_map) {
934 "Failed to allocate memory for ethertype hash map!");
936 goto err_ethertype_hash_map_alloc;
941 err_ethertype_hash_map_alloc:
942 rte_hash_free(ethertype_rule->hash_table);
948 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
950 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
951 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
952 char tunnel_hash_name[RTE_HASH_NAMESIZE];
955 struct rte_hash_parameters tunnel_hash_params = {
956 .name = tunnel_hash_name,
957 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
958 .key_len = sizeof(struct i40e_tunnel_filter_input),
959 .hash_func = rte_hash_crc,
960 .hash_func_init_val = 0,
961 .socket_id = rte_socket_id(),
964 /* Initialize tunnel filter rule list and hash */
965 TAILQ_INIT(&tunnel_rule->tunnel_list);
966 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
967 "tunnel_%s", dev->data->name);
968 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
969 if (!tunnel_rule->hash_table) {
970 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
973 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
974 sizeof(struct i40e_tunnel_filter *) *
975 I40E_MAX_TUNNEL_FILTER_NUM,
977 if (!tunnel_rule->hash_map) {
979 "Failed to allocate memory for tunnel hash map!");
981 goto err_tunnel_hash_map_alloc;
986 err_tunnel_hash_map_alloc:
987 rte_hash_free(tunnel_rule->hash_table);
993 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
995 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
996 struct i40e_fdir_info *fdir_info = &pf->fdir;
997 char fdir_hash_name[RTE_HASH_NAMESIZE];
1000 struct rte_hash_parameters fdir_hash_params = {
1001 .name = fdir_hash_name,
1002 .entries = I40E_MAX_FDIR_FILTER_NUM,
1003 .key_len = sizeof(struct rte_eth_fdir_input),
1004 .hash_func = rte_hash_crc,
1005 .hash_func_init_val = 0,
1006 .socket_id = rte_socket_id(),
1009 /* Initialize flow director filter rule list and hash */
1010 TAILQ_INIT(&fdir_info->fdir_list);
1011 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1012 "fdir_%s", dev->data->name);
1013 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1014 if (!fdir_info->hash_table) {
1015 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1018 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1019 sizeof(struct i40e_fdir_filter *) *
1020 I40E_MAX_FDIR_FILTER_NUM,
1022 if (!fdir_info->hash_map) {
1024 "Failed to allocate memory for fdir hash map!");
1026 goto err_fdir_hash_map_alloc;
1030 err_fdir_hash_map_alloc:
1031 rte_hash_free(fdir_info->hash_table);
1037 eth_i40e_dev_init(struct rte_eth_dev *dev)
1039 struct rte_pci_device *pci_dev;
1040 struct rte_intr_handle *intr_handle;
1041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1042 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043 struct i40e_vsi *vsi;
1046 uint8_t aq_fail = 0;
1048 PMD_INIT_FUNC_TRACE();
1050 dev->dev_ops = &i40e_eth_dev_ops;
1051 dev->rx_pkt_burst = i40e_recv_pkts;
1052 dev->tx_pkt_burst = i40e_xmit_pkts;
1053 dev->tx_pkt_prepare = i40e_prep_pkts;
1055 /* for secondary processes, we don't initialise any further as primary
1056 * has already done this work. Only check we don't need a different
1058 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1059 i40e_set_rx_function(dev);
1060 i40e_set_tx_function(dev);
1063 i40e_set_default_ptype_table(dev);
1064 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1065 intr_handle = &pci_dev->intr_handle;
1067 rte_eth_copy_pci_info(dev, pci_dev);
1068 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1070 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1071 pf->adapter->eth_dev = dev;
1072 pf->dev_data = dev->data;
1074 hw->back = I40E_PF_TO_ADAPTER(pf);
1075 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1078 "Hardware is not available, as address is NULL");
1082 hw->vendor_id = pci_dev->id.vendor_id;
1083 hw->device_id = pci_dev->id.device_id;
1084 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1085 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1086 hw->bus.device = pci_dev->addr.devid;
1087 hw->bus.func = pci_dev->addr.function;
1088 hw->adapter_stopped = 0;
1090 /* Make sure all is clean before doing PF reset */
1093 /* Initialize the hardware */
1096 /* Reset here to make sure all is clean for each PF */
1097 ret = i40e_pf_reset(hw);
1099 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1103 /* Initialize the shared code (base driver) */
1104 ret = i40e_init_shared_code(hw);
1106 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1111 * To work around the NVM issue, initialize registers
1112 * for flexible payload and packet type of QinQ by
1113 * software. It should be removed once issues are fixed
1116 i40e_GLQF_reg_init(hw);
1118 /* Initialize the input set for filters (hash and fd) to default value */
1119 i40e_filter_input_set_init(pf);
1121 /* Initialize the parameters for adminq */
1122 i40e_init_adminq_parameter(hw);
1123 ret = i40e_init_adminq(hw);
1124 if (ret != I40E_SUCCESS) {
1125 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1128 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1129 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1130 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1131 ((hw->nvm.version >> 12) & 0xf),
1132 ((hw->nvm.version >> 4) & 0xff),
1133 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1135 /* initialise the L3_MAP register */
1136 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1139 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1141 /* Need the special FW version to support floating VEB */
1142 config_floating_veb(dev);
1143 /* Clear PXE mode */
1144 i40e_clear_pxe_mode(hw);
1145 ret = i40e_dev_sync_phy_type(hw);
1147 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1148 goto err_sync_phy_type;
1151 * On X710, performance number is far from the expectation on recent
1152 * firmware versions. The fix for this issue may not be integrated in
1153 * the following firmware version. So the workaround in software driver
1154 * is needed. It needs to modify the initial values of 3 internal only
1155 * registers. Note that the workaround can be removed when it is fixed
1156 * in firmware in the future.
1158 i40e_configure_registers(hw);
1160 /* Get hw capabilities */
1161 ret = i40e_get_cap(hw);
1162 if (ret != I40E_SUCCESS) {
1163 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1164 goto err_get_capabilities;
1167 /* Initialize parameters for PF */
1168 ret = i40e_pf_parameter_init(dev);
1170 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1171 goto err_parameter_init;
1174 /* Initialize the queue management */
1175 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1177 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1178 goto err_qp_pool_init;
1180 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1181 hw->func_caps.num_msix_vectors - 1);
1183 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1184 goto err_msix_pool_init;
1187 /* Initialize lan hmc */
1188 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1189 hw->func_caps.num_rx_qp, 0, 0);
1190 if (ret != I40E_SUCCESS) {
1191 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1192 goto err_init_lan_hmc;
1195 /* Configure lan hmc */
1196 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1197 if (ret != I40E_SUCCESS) {
1198 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1199 goto err_configure_lan_hmc;
1202 /* Get and check the mac address */
1203 i40e_get_mac_addr(hw, hw->mac.addr);
1204 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1205 PMD_INIT_LOG(ERR, "mac address is not valid");
1207 goto err_get_mac_addr;
1209 /* Copy the permanent MAC address */
1210 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1211 (struct ether_addr *) hw->mac.perm_addr);
1213 /* Disable flow control */
1214 hw->fc.requested_mode = I40E_FC_NONE;
1215 i40e_set_fc(hw, &aq_fail, TRUE);
1217 /* Set the global registers with default ether type value */
1218 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1219 if (ret != I40E_SUCCESS) {
1221 "Failed to set the default outer VLAN ether type");
1222 goto err_setup_pf_switch;
1225 /* PF setup, which includes VSI setup */
1226 ret = i40e_pf_setup(pf);
1228 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1229 goto err_setup_pf_switch;
1232 /* reset all stats of the device, including pf and main vsi */
1233 i40e_dev_stats_reset(dev);
1237 /* Disable double vlan by default */
1238 i40e_vsi_config_double_vlan(vsi, FALSE);
1240 /* Disable S-TAG identification when floating_veb is disabled */
1241 if (!pf->floating_veb) {
1242 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1243 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1244 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1245 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1249 if (!vsi->max_macaddrs)
1250 len = ETHER_ADDR_LEN;
1252 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1254 /* Should be after VSI initialized */
1255 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1256 if (!dev->data->mac_addrs) {
1258 "Failed to allocated memory for storing mac address");
1261 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1262 &dev->data->mac_addrs[0]);
1264 /* Init dcb to sw mode by default */
1265 ret = i40e_dcb_init_configure(dev, TRUE);
1266 if (ret != I40E_SUCCESS) {
1267 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1268 pf->flags &= ~I40E_FLAG_DCB;
1270 /* Update HW struct after DCB configuration */
1273 /* initialize pf host driver to setup SRIOV resource if applicable */
1274 i40e_pf_host_init(dev);
1276 /* register callback func to eal lib */
1277 rte_intr_callback_register(intr_handle,
1278 i40e_dev_interrupt_handler, dev);
1280 /* configure and enable device interrupt */
1281 i40e_pf_config_irq0(hw, TRUE);
1282 i40e_pf_enable_irq0(hw);
1284 /* enable uio intr after callback register */
1285 rte_intr_enable(intr_handle);
1287 * Add an ethertype filter to drop all flow control frames transmitted
1288 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1291 i40e_add_tx_flow_control_drop_filter(pf);
1293 /* Set the max frame size to 0x2600 by default,
1294 * in case other drivers changed the default value.
1296 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1298 /* initialize mirror rule list */
1299 TAILQ_INIT(&pf->mirror_list);
1301 ret = i40e_init_ethtype_filter_list(dev);
1303 goto err_init_ethtype_filter_list;
1304 ret = i40e_init_tunnel_filter_list(dev);
1306 goto err_init_tunnel_filter_list;
1307 ret = i40e_init_fdir_filter_list(dev);
1309 goto err_init_fdir_filter_list;
1313 err_init_fdir_filter_list:
1314 rte_free(pf->tunnel.hash_table);
1315 rte_free(pf->tunnel.hash_map);
1316 err_init_tunnel_filter_list:
1317 rte_free(pf->ethertype.hash_table);
1318 rte_free(pf->ethertype.hash_map);
1319 err_init_ethtype_filter_list:
1320 rte_free(dev->data->mac_addrs);
1322 i40e_vsi_release(pf->main_vsi);
1323 err_setup_pf_switch:
1325 err_configure_lan_hmc:
1326 (void)i40e_shutdown_lan_hmc(hw);
1328 i40e_res_pool_destroy(&pf->msix_pool);
1330 i40e_res_pool_destroy(&pf->qp_pool);
1333 err_get_capabilities:
1335 (void)i40e_shutdown_adminq(hw);
1341 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1343 struct i40e_ethertype_filter *p_ethertype;
1344 struct i40e_ethertype_rule *ethertype_rule;
1346 ethertype_rule = &pf->ethertype;
1347 /* Remove all ethertype filter rules and hash */
1348 if (ethertype_rule->hash_map)
1349 rte_free(ethertype_rule->hash_map);
1350 if (ethertype_rule->hash_table)
1351 rte_hash_free(ethertype_rule->hash_table);
1353 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1354 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1355 p_ethertype, rules);
1356 rte_free(p_ethertype);
1361 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1363 struct i40e_tunnel_filter *p_tunnel;
1364 struct i40e_tunnel_rule *tunnel_rule;
1366 tunnel_rule = &pf->tunnel;
1367 /* Remove all tunnel director rules and hash */
1368 if (tunnel_rule->hash_map)
1369 rte_free(tunnel_rule->hash_map);
1370 if (tunnel_rule->hash_table)
1371 rte_hash_free(tunnel_rule->hash_table);
1373 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1374 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1380 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1382 struct i40e_fdir_filter *p_fdir;
1383 struct i40e_fdir_info *fdir_info;
1385 fdir_info = &pf->fdir;
1386 /* Remove all flow director rules and hash */
1387 if (fdir_info->hash_map)
1388 rte_free(fdir_info->hash_map);
1389 if (fdir_info->hash_table)
1390 rte_hash_free(fdir_info->hash_table);
1392 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1393 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1399 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1402 struct rte_pci_device *pci_dev;
1403 struct rte_intr_handle *intr_handle;
1405 struct i40e_filter_control_settings settings;
1406 struct rte_flow *p_flow;
1408 uint8_t aq_fail = 0;
1410 PMD_INIT_FUNC_TRACE();
1412 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1415 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1418 intr_handle = &pci_dev->intr_handle;
1420 if (hw->adapter_stopped == 0)
1421 i40e_dev_close(dev);
1423 dev->dev_ops = NULL;
1424 dev->rx_pkt_burst = NULL;
1425 dev->tx_pkt_burst = NULL;
1427 /* Clear PXE mode */
1428 i40e_clear_pxe_mode(hw);
1430 /* Unconfigure filter control */
1431 memset(&settings, 0, sizeof(settings));
1432 ret = i40e_set_filter_control(hw, &settings);
1434 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1437 /* Disable flow control */
1438 hw->fc.requested_mode = I40E_FC_NONE;
1439 i40e_set_fc(hw, &aq_fail, TRUE);
1441 /* uninitialize pf host driver */
1442 i40e_pf_host_uninit(dev);
1444 rte_free(dev->data->mac_addrs);
1445 dev->data->mac_addrs = NULL;
1447 /* disable uio intr before callback unregister */
1448 rte_intr_disable(intr_handle);
1450 /* register callback func to eal lib */
1451 rte_intr_callback_unregister(intr_handle,
1452 i40e_dev_interrupt_handler, dev);
1454 i40e_rm_ethtype_filter_list(pf);
1455 i40e_rm_tunnel_filter_list(pf);
1456 i40e_rm_fdir_filter_list(pf);
1458 /* Remove all flows */
1459 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1460 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1468 i40e_dev_configure(struct rte_eth_dev *dev)
1470 struct i40e_adapter *ad =
1471 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1472 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1473 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1476 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1477 * bulk allocation or vector Rx preconditions we will reset it.
1479 ad->rx_bulk_alloc_allowed = true;
1480 ad->rx_vec_allowed = true;
1481 ad->tx_simple_allowed = true;
1482 ad->tx_vec_allowed = true;
1484 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1485 ret = i40e_fdir_setup(pf);
1486 if (ret != I40E_SUCCESS) {
1487 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1490 ret = i40e_fdir_configure(dev);
1492 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1496 i40e_fdir_teardown(pf);
1498 ret = i40e_dev_init_vlan(dev);
1503 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1504 * RSS setting have different requirements.
1505 * General PMD driver call sequence are NIC init, configure,
1506 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1507 * will try to lookup the VSI that specific queue belongs to if VMDQ
1508 * applicable. So, VMDQ setting has to be done before
1509 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1510 * For RSS setting, it will try to calculate actual configured RX queue
1511 * number, which will be available after rx_queue_setup(). dev_start()
1512 * function is good to place RSS setup.
1514 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1515 ret = i40e_vmdq_setup(dev);
1520 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1521 ret = i40e_dcb_setup(dev);
1523 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1528 TAILQ_INIT(&pf->flow_list);
1533 /* need to release vmdq resource if exists */
1534 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1535 i40e_vsi_release(pf->vmdq[i].vsi);
1536 pf->vmdq[i].vsi = NULL;
1541 /* need to release fdir resource if exists */
1542 i40e_fdir_teardown(pf);
1547 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1549 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1550 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1551 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1552 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1553 uint16_t msix_vect = vsi->msix_intr;
1556 for (i = 0; i < vsi->nb_qps; i++) {
1557 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1558 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1562 if (vsi->type != I40E_VSI_SRIOV) {
1563 if (!rte_intr_allow_others(intr_handle)) {
1564 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1565 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1567 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1570 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1571 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1573 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1578 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1579 vsi->user_param + (msix_vect - 1);
1581 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1582 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1584 I40E_WRITE_FLUSH(hw);
1588 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1589 int base_queue, int nb_queue)
1593 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1595 /* Bind all RX queues to allocated MSIX interrupt */
1596 for (i = 0; i < nb_queue; i++) {
1597 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1598 I40E_QINT_RQCTL_ITR_INDX_MASK |
1599 ((base_queue + i + 1) <<
1600 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1601 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1602 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1604 if (i == nb_queue - 1)
1605 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1606 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1609 /* Write first RX queue to Link list register as the head element */
1610 if (vsi->type != I40E_VSI_SRIOV) {
1612 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1614 if (msix_vect == I40E_MISC_VEC_ID) {
1615 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1617 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1619 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1621 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1624 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1626 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1628 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1630 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1637 if (msix_vect == I40E_MISC_VEC_ID) {
1639 I40E_VPINT_LNKLST0(vsi->user_param),
1641 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1643 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1645 /* num_msix_vectors_vf needs to minus irq0 */
1646 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1647 vsi->user_param + (msix_vect - 1);
1649 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1651 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1653 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1657 I40E_WRITE_FLUSH(hw);
1661 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1663 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1664 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1665 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1666 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1667 uint16_t msix_vect = vsi->msix_intr;
1668 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1669 uint16_t queue_idx = 0;
1674 for (i = 0; i < vsi->nb_qps; i++) {
1675 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1676 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1679 /* INTENA flag is not auto-cleared for interrupt */
1680 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1681 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1682 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1683 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1684 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1686 /* VF bind interrupt */
1687 if (vsi->type == I40E_VSI_SRIOV) {
1688 __vsi_queues_bind_intr(vsi, msix_vect,
1689 vsi->base_queue, vsi->nb_qps);
1693 /* PF & VMDq bind interrupt */
1694 if (rte_intr_dp_is_en(intr_handle)) {
1695 if (vsi->type == I40E_VSI_MAIN) {
1698 } else if (vsi->type == I40E_VSI_VMDQ2) {
1699 struct i40e_vsi *main_vsi =
1700 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1701 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1706 for (i = 0; i < vsi->nb_used_qps; i++) {
1708 if (!rte_intr_allow_others(intr_handle))
1709 /* allow to share MISC_VEC_ID */
1710 msix_vect = I40E_MISC_VEC_ID;
1712 /* no enough msix_vect, map all to one */
1713 __vsi_queues_bind_intr(vsi, msix_vect,
1714 vsi->base_queue + i,
1715 vsi->nb_used_qps - i);
1716 for (; !!record && i < vsi->nb_used_qps; i++)
1717 intr_handle->intr_vec[queue_idx + i] =
1721 /* 1:1 queue/msix_vect mapping */
1722 __vsi_queues_bind_intr(vsi, msix_vect,
1723 vsi->base_queue + i, 1);
1725 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1733 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1735 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1736 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1737 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1738 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1739 uint16_t interval = i40e_calc_itr_interval(\
1740 RTE_LIBRTE_I40E_ITR_INTERVAL);
1741 uint16_t msix_intr, i;
1743 if (rte_intr_allow_others(intr_handle))
1744 for (i = 0; i < vsi->nb_msix; i++) {
1745 msix_intr = vsi->msix_intr + i;
1746 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1747 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1748 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1749 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1751 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1754 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1755 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1756 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1757 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1759 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1761 I40E_WRITE_FLUSH(hw);
1765 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1767 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1768 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1769 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1770 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1771 uint16_t msix_intr, i;
1773 if (rte_intr_allow_others(intr_handle))
1774 for (i = 0; i < vsi->nb_msix; i++) {
1775 msix_intr = vsi->msix_intr + i;
1776 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1780 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1782 I40E_WRITE_FLUSH(hw);
1785 static inline uint8_t
1786 i40e_parse_link_speeds(uint16_t link_speeds)
1788 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1790 if (link_speeds & ETH_LINK_SPEED_40G)
1791 link_speed |= I40E_LINK_SPEED_40GB;
1792 if (link_speeds & ETH_LINK_SPEED_25G)
1793 link_speed |= I40E_LINK_SPEED_25GB;
1794 if (link_speeds & ETH_LINK_SPEED_20G)
1795 link_speed |= I40E_LINK_SPEED_20GB;
1796 if (link_speeds & ETH_LINK_SPEED_10G)
1797 link_speed |= I40E_LINK_SPEED_10GB;
1798 if (link_speeds & ETH_LINK_SPEED_1G)
1799 link_speed |= I40E_LINK_SPEED_1GB;
1800 if (link_speeds & ETH_LINK_SPEED_100M)
1801 link_speed |= I40E_LINK_SPEED_100MB;
1807 i40e_phy_conf_link(struct i40e_hw *hw,
1809 uint8_t force_speed)
1811 enum i40e_status_code status;
1812 struct i40e_aq_get_phy_abilities_resp phy_ab;
1813 struct i40e_aq_set_phy_config phy_conf;
1814 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1815 I40E_AQ_PHY_FLAG_PAUSE_RX |
1816 I40E_AQ_PHY_FLAG_PAUSE_RX |
1817 I40E_AQ_PHY_FLAG_LOW_POWER;
1818 const uint8_t advt = I40E_LINK_SPEED_40GB |
1819 I40E_LINK_SPEED_25GB |
1820 I40E_LINK_SPEED_10GB |
1821 I40E_LINK_SPEED_1GB |
1822 I40E_LINK_SPEED_100MB;
1826 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1831 memset(&phy_conf, 0, sizeof(phy_conf));
1833 /* bits 0-2 use the values from get_phy_abilities_resp */
1835 abilities |= phy_ab.abilities & mask;
1837 /* update ablities and speed */
1838 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1839 phy_conf.link_speed = advt;
1841 phy_conf.link_speed = force_speed;
1843 phy_conf.abilities = abilities;
1845 /* use get_phy_abilities_resp value for the rest */
1846 phy_conf.phy_type = phy_ab.phy_type;
1847 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1848 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1849 phy_conf.eee_capability = phy_ab.eee_capability;
1850 phy_conf.eeer = phy_ab.eeer_val;
1851 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1853 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1854 phy_ab.abilities, phy_ab.link_speed);
1855 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1856 phy_conf.abilities, phy_conf.link_speed);
1858 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1862 return I40E_SUCCESS;
1866 i40e_apply_link_speed(struct rte_eth_dev *dev)
1869 uint8_t abilities = 0;
1870 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871 struct rte_eth_conf *conf = &dev->data->dev_conf;
1873 speed = i40e_parse_link_speeds(conf->link_speeds);
1874 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1875 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1876 abilities |= I40E_AQ_PHY_AN_ENABLED;
1877 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1879 /* Skip changing speed on 40G interfaces, FW does not support */
1880 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1881 speed = I40E_LINK_SPEED_UNKNOWN;
1882 abilities |= I40E_AQ_PHY_AN_ENABLED;
1885 return i40e_phy_conf_link(hw, abilities, speed);
1889 i40e_dev_start(struct rte_eth_dev *dev)
1891 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1892 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1893 struct i40e_vsi *main_vsi = pf->main_vsi;
1895 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1896 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1897 uint32_t intr_vector = 0;
1898 struct i40e_vsi *vsi;
1900 hw->adapter_stopped = 0;
1902 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1903 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1904 dev->data->port_id);
1908 rte_intr_disable(intr_handle);
1910 if ((rte_intr_cap_multiple(intr_handle) ||
1911 !RTE_ETH_DEV_SRIOV(dev).active) &&
1912 dev->data->dev_conf.intr_conf.rxq != 0) {
1913 intr_vector = dev->data->nb_rx_queues;
1914 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1919 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1920 intr_handle->intr_vec =
1921 rte_zmalloc("intr_vec",
1922 dev->data->nb_rx_queues * sizeof(int),
1924 if (!intr_handle->intr_vec) {
1926 "Failed to allocate %d rx_queues intr_vec",
1927 dev->data->nb_rx_queues);
1932 /* Initialize VSI */
1933 ret = i40e_dev_rxtx_init(pf);
1934 if (ret != I40E_SUCCESS) {
1935 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1939 /* Map queues with MSIX interrupt */
1940 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1941 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1942 i40e_vsi_queues_bind_intr(main_vsi);
1943 i40e_vsi_enable_queues_intr(main_vsi);
1945 /* Map VMDQ VSI queues with MSIX interrupt */
1946 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1947 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1948 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1949 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1952 /* enable FDIR MSIX interrupt */
1953 if (pf->fdir.fdir_vsi) {
1954 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1955 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1958 /* Enable all queues which have been configured */
1959 ret = i40e_dev_switch_queues(pf, TRUE);
1960 if (ret != I40E_SUCCESS) {
1961 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1965 /* Enable receiving broadcast packets */
1966 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1967 if (ret != I40E_SUCCESS)
1968 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1970 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1971 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1973 if (ret != I40E_SUCCESS)
1974 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1977 /* Enable the VLAN promiscuous mode. */
1979 for (i = 0; i < pf->vf_num; i++) {
1980 vsi = pf->vfs[i].vsi;
1981 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1986 /* Apply link configure */
1987 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1988 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1989 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1990 ETH_LINK_SPEED_40G)) {
1991 PMD_DRV_LOG(ERR, "Invalid link setting");
1994 ret = i40e_apply_link_speed(dev);
1995 if (I40E_SUCCESS != ret) {
1996 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2000 if (!rte_intr_allow_others(intr_handle)) {
2001 rte_intr_callback_unregister(intr_handle,
2002 i40e_dev_interrupt_handler,
2004 /* configure and enable device interrupt */
2005 i40e_pf_config_irq0(hw, FALSE);
2006 i40e_pf_enable_irq0(hw);
2008 if (dev->data->dev_conf.intr_conf.lsc != 0)
2010 "lsc won't enable because of no intr multiplex");
2011 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2012 ret = i40e_aq_set_phy_int_mask(hw,
2013 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2014 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2015 I40E_AQ_EVENT_MEDIA_NA), NULL);
2016 if (ret != I40E_SUCCESS)
2017 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2019 /* Call get_link_info aq commond to enable LSE */
2020 i40e_dev_link_update(dev, 0);
2023 /* enable uio intr after callback register */
2024 rte_intr_enable(intr_handle);
2026 i40e_filter_restore(pf);
2028 return I40E_SUCCESS;
2031 i40e_dev_switch_queues(pf, FALSE);
2032 i40e_dev_clear_queues(dev);
2038 i40e_dev_stop(struct rte_eth_dev *dev)
2040 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2041 struct i40e_vsi *main_vsi = pf->main_vsi;
2042 struct i40e_mirror_rule *p_mirror;
2043 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2044 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2047 /* Disable all queues */
2048 i40e_dev_switch_queues(pf, FALSE);
2050 /* un-map queues with interrupt registers */
2051 i40e_vsi_disable_queues_intr(main_vsi);
2052 i40e_vsi_queues_unbind_intr(main_vsi);
2054 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2055 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2056 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2059 if (pf->fdir.fdir_vsi) {
2060 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2061 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2063 /* Clear all queues and release memory */
2064 i40e_dev_clear_queues(dev);
2067 i40e_dev_set_link_down(dev);
2069 /* Remove all mirror rules */
2070 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2071 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2074 pf->nb_mirror_rule = 0;
2076 if (!rte_intr_allow_others(intr_handle))
2077 /* resume to the default handler */
2078 rte_intr_callback_register(intr_handle,
2079 i40e_dev_interrupt_handler,
2082 /* Clean datapath event and queue/vec mapping */
2083 rte_intr_efd_disable(intr_handle);
2084 if (intr_handle->intr_vec) {
2085 rte_free(intr_handle->intr_vec);
2086 intr_handle->intr_vec = NULL;
2091 i40e_dev_close(struct rte_eth_dev *dev)
2093 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2094 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2096 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2100 PMD_INIT_FUNC_TRACE();
2103 hw->adapter_stopped = 1;
2104 i40e_dev_free_queues(dev);
2106 /* Disable interrupt */
2107 i40e_pf_disable_irq0(hw);
2108 rte_intr_disable(intr_handle);
2110 /* shutdown and destroy the HMC */
2111 i40e_shutdown_lan_hmc(hw);
2113 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2114 i40e_vsi_release(pf->vmdq[i].vsi);
2115 pf->vmdq[i].vsi = NULL;
2120 /* release all the existing VSIs and VEBs */
2121 i40e_fdir_teardown(pf);
2122 i40e_vsi_release(pf->main_vsi);
2124 /* shutdown the adminq */
2125 i40e_aq_queue_shutdown(hw, true);
2126 i40e_shutdown_adminq(hw);
2128 i40e_res_pool_destroy(&pf->qp_pool);
2129 i40e_res_pool_destroy(&pf->msix_pool);
2131 /* force a PF reset to clean anything leftover */
2132 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2133 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2134 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2135 I40E_WRITE_FLUSH(hw);
2139 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2142 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2143 struct i40e_vsi *vsi = pf->main_vsi;
2146 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2148 if (status != I40E_SUCCESS)
2149 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2151 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2153 if (status != I40E_SUCCESS)
2154 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2159 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2161 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2162 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163 struct i40e_vsi *vsi = pf->main_vsi;
2166 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2168 if (status != I40E_SUCCESS)
2169 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2171 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2173 if (status != I40E_SUCCESS)
2174 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2178 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2180 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2181 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182 struct i40e_vsi *vsi = pf->main_vsi;
2185 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2186 if (ret != I40E_SUCCESS)
2187 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2191 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2193 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2194 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195 struct i40e_vsi *vsi = pf->main_vsi;
2198 if (dev->data->promiscuous == 1)
2199 return; /* must remain in all_multicast mode */
2201 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2202 vsi->seid, FALSE, NULL);
2203 if (ret != I40E_SUCCESS)
2204 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2208 * Set device link up.
2211 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2213 /* re-apply link speed setting */
2214 return i40e_apply_link_speed(dev);
2218 * Set device link down.
2221 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2223 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2224 uint8_t abilities = 0;
2225 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2228 return i40e_phy_conf_link(hw, abilities, speed);
2232 i40e_dev_link_update(struct rte_eth_dev *dev,
2233 int wait_to_complete)
2235 #define CHECK_INTERVAL 100 /* 100ms */
2236 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2237 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238 struct i40e_link_status link_status;
2239 struct rte_eth_link link, old;
2241 unsigned rep_cnt = MAX_REPEAT_TIME;
2242 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2244 memset(&link, 0, sizeof(link));
2245 memset(&old, 0, sizeof(old));
2246 memset(&link_status, 0, sizeof(link_status));
2247 rte_i40e_dev_atomic_read_link_status(dev, &old);
2250 /* Get link status information from hardware */
2251 status = i40e_aq_get_link_info(hw, enable_lse,
2252 &link_status, NULL);
2253 if (status != I40E_SUCCESS) {
2254 link.link_speed = ETH_SPEED_NUM_100M;
2255 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2256 PMD_DRV_LOG(ERR, "Failed to get link info");
2260 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2261 if (!wait_to_complete || link.link_status)
2264 rte_delay_ms(CHECK_INTERVAL);
2265 } while (--rep_cnt);
2267 if (!link.link_status)
2270 /* i40e uses full duplex only */
2271 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2273 /* Parse the link status */
2274 switch (link_status.link_speed) {
2275 case I40E_LINK_SPEED_100MB:
2276 link.link_speed = ETH_SPEED_NUM_100M;
2278 case I40E_LINK_SPEED_1GB:
2279 link.link_speed = ETH_SPEED_NUM_1G;
2281 case I40E_LINK_SPEED_10GB:
2282 link.link_speed = ETH_SPEED_NUM_10G;
2284 case I40E_LINK_SPEED_20GB:
2285 link.link_speed = ETH_SPEED_NUM_20G;
2287 case I40E_LINK_SPEED_25GB:
2288 link.link_speed = ETH_SPEED_NUM_25G;
2290 case I40E_LINK_SPEED_40GB:
2291 link.link_speed = ETH_SPEED_NUM_40G;
2294 link.link_speed = ETH_SPEED_NUM_100M;
2298 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2299 ETH_LINK_SPEED_FIXED);
2302 rte_i40e_dev_atomic_write_link_status(dev, &link);
2303 if (link.link_status == old.link_status)
2306 i40e_notify_all_vfs_link_status(dev);
2311 /* Get all the statistics of a VSI */
2313 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2315 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2316 struct i40e_eth_stats *nes = &vsi->eth_stats;
2317 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2318 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2320 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2321 vsi->offset_loaded, &oes->rx_bytes,
2323 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2324 vsi->offset_loaded, &oes->rx_unicast,
2326 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2327 vsi->offset_loaded, &oes->rx_multicast,
2328 &nes->rx_multicast);
2329 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2330 vsi->offset_loaded, &oes->rx_broadcast,
2331 &nes->rx_broadcast);
2332 /* exclude CRC bytes */
2333 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2334 nes->rx_broadcast) * ETHER_CRC_LEN;
2336 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2337 &oes->rx_discards, &nes->rx_discards);
2338 /* GLV_REPC not supported */
2339 /* GLV_RMPC not supported */
2340 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2341 &oes->rx_unknown_protocol,
2342 &nes->rx_unknown_protocol);
2343 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2344 vsi->offset_loaded, &oes->tx_bytes,
2346 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2347 vsi->offset_loaded, &oes->tx_unicast,
2349 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2350 vsi->offset_loaded, &oes->tx_multicast,
2351 &nes->tx_multicast);
2352 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2353 vsi->offset_loaded, &oes->tx_broadcast,
2354 &nes->tx_broadcast);
2355 /* exclude CRC bytes */
2356 nes->tx_bytes -= (nes->tx_unicast + nes->tx_multicast +
2357 nes->tx_broadcast) * ETHER_CRC_LEN;
2358 /* GLV_TDPC not supported */
2359 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2360 &oes->tx_errors, &nes->tx_errors);
2361 vsi->offset_loaded = true;
2363 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2365 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2366 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2367 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2368 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2369 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2370 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2371 nes->rx_unknown_protocol);
2372 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2373 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2374 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2375 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2376 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2377 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2378 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2383 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2386 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2387 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2389 /* Get rx/tx bytes of internal transfer packets */
2390 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2391 I40E_GLV_GORCL(hw->port),
2393 &pf->internal_rx_bytes_offset,
2394 &pf->internal_rx_bytes);
2396 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2397 I40E_GLV_GOTCL(hw->port),
2399 &pf->internal_tx_bytes_offset,
2400 &pf->internal_tx_bytes);
2402 /* Get statistics of struct i40e_eth_stats */
2403 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2404 I40E_GLPRT_GORCL(hw->port),
2405 pf->offset_loaded, &os->eth.rx_bytes,
2407 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2408 I40E_GLPRT_UPRCL(hw->port),
2409 pf->offset_loaded, &os->eth.rx_unicast,
2410 &ns->eth.rx_unicast);
2411 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2412 I40E_GLPRT_MPRCL(hw->port),
2413 pf->offset_loaded, &os->eth.rx_multicast,
2414 &ns->eth.rx_multicast);
2415 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2416 I40E_GLPRT_BPRCL(hw->port),
2417 pf->offset_loaded, &os->eth.rx_broadcast,
2418 &ns->eth.rx_broadcast);
2419 /* Workaround: CRC size should not be included in byte statistics,
2420 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2422 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2423 ns->eth.rx_broadcast) * ETHER_CRC_LEN + pf->internal_rx_bytes;
2425 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2426 pf->offset_loaded, &os->eth.rx_discards,
2427 &ns->eth.rx_discards);
2428 /* GLPRT_REPC not supported */
2429 /* GLPRT_RMPC not supported */
2430 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2432 &os->eth.rx_unknown_protocol,
2433 &ns->eth.rx_unknown_protocol);
2434 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2435 I40E_GLPRT_GOTCL(hw->port),
2436 pf->offset_loaded, &os->eth.tx_bytes,
2438 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2439 I40E_GLPRT_UPTCL(hw->port),
2440 pf->offset_loaded, &os->eth.tx_unicast,
2441 &ns->eth.tx_unicast);
2442 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2443 I40E_GLPRT_MPTCL(hw->port),
2444 pf->offset_loaded, &os->eth.tx_multicast,
2445 &ns->eth.tx_multicast);
2446 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2447 I40E_GLPRT_BPTCL(hw->port),
2448 pf->offset_loaded, &os->eth.tx_broadcast,
2449 &ns->eth.tx_broadcast);
2450 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2451 ns->eth.tx_broadcast) * ETHER_CRC_LEN + pf->internal_tx_bytes;
2452 /* GLPRT_TEPC not supported */
2454 /* additional port specific stats */
2455 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2456 pf->offset_loaded, &os->tx_dropped_link_down,
2457 &ns->tx_dropped_link_down);
2458 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2459 pf->offset_loaded, &os->crc_errors,
2461 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2462 pf->offset_loaded, &os->illegal_bytes,
2463 &ns->illegal_bytes);
2464 /* GLPRT_ERRBC not supported */
2465 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2466 pf->offset_loaded, &os->mac_local_faults,
2467 &ns->mac_local_faults);
2468 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2469 pf->offset_loaded, &os->mac_remote_faults,
2470 &ns->mac_remote_faults);
2471 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2472 pf->offset_loaded, &os->rx_length_errors,
2473 &ns->rx_length_errors);
2474 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2475 pf->offset_loaded, &os->link_xon_rx,
2477 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2478 pf->offset_loaded, &os->link_xoff_rx,
2480 for (i = 0; i < 8; i++) {
2481 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2483 &os->priority_xon_rx[i],
2484 &ns->priority_xon_rx[i]);
2485 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2487 &os->priority_xoff_rx[i],
2488 &ns->priority_xoff_rx[i]);
2490 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2491 pf->offset_loaded, &os->link_xon_tx,
2493 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2494 pf->offset_loaded, &os->link_xoff_tx,
2496 for (i = 0; i < 8; i++) {
2497 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2499 &os->priority_xon_tx[i],
2500 &ns->priority_xon_tx[i]);
2501 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2503 &os->priority_xoff_tx[i],
2504 &ns->priority_xoff_tx[i]);
2505 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2507 &os->priority_xon_2_xoff[i],
2508 &ns->priority_xon_2_xoff[i]);
2510 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2511 I40E_GLPRT_PRC64L(hw->port),
2512 pf->offset_loaded, &os->rx_size_64,
2514 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2515 I40E_GLPRT_PRC127L(hw->port),
2516 pf->offset_loaded, &os->rx_size_127,
2518 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2519 I40E_GLPRT_PRC255L(hw->port),
2520 pf->offset_loaded, &os->rx_size_255,
2522 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2523 I40E_GLPRT_PRC511L(hw->port),
2524 pf->offset_loaded, &os->rx_size_511,
2526 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2527 I40E_GLPRT_PRC1023L(hw->port),
2528 pf->offset_loaded, &os->rx_size_1023,
2530 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2531 I40E_GLPRT_PRC1522L(hw->port),
2532 pf->offset_loaded, &os->rx_size_1522,
2534 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2535 I40E_GLPRT_PRC9522L(hw->port),
2536 pf->offset_loaded, &os->rx_size_big,
2538 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2539 pf->offset_loaded, &os->rx_undersize,
2541 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2542 pf->offset_loaded, &os->rx_fragments,
2544 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2545 pf->offset_loaded, &os->rx_oversize,
2547 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2548 pf->offset_loaded, &os->rx_jabber,
2550 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2551 I40E_GLPRT_PTC64L(hw->port),
2552 pf->offset_loaded, &os->tx_size_64,
2554 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2555 I40E_GLPRT_PTC127L(hw->port),
2556 pf->offset_loaded, &os->tx_size_127,
2558 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2559 I40E_GLPRT_PTC255L(hw->port),
2560 pf->offset_loaded, &os->tx_size_255,
2562 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2563 I40E_GLPRT_PTC511L(hw->port),
2564 pf->offset_loaded, &os->tx_size_511,
2566 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2567 I40E_GLPRT_PTC1023L(hw->port),
2568 pf->offset_loaded, &os->tx_size_1023,
2570 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2571 I40E_GLPRT_PTC1522L(hw->port),
2572 pf->offset_loaded, &os->tx_size_1522,
2574 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2575 I40E_GLPRT_PTC9522L(hw->port),
2576 pf->offset_loaded, &os->tx_size_big,
2578 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2580 &os->fd_sb_match, &ns->fd_sb_match);
2581 /* GLPRT_MSPDC not supported */
2582 /* GLPRT_XEC not supported */
2584 pf->offset_loaded = true;
2587 i40e_update_vsi_stats(pf->main_vsi);
2590 /* Get all statistics of a port */
2592 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2594 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2595 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2596 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2599 /* call read registers - updates values, now write them to struct */
2600 i40e_read_stats_registers(pf, hw);
2602 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2603 pf->main_vsi->eth_stats.rx_multicast +
2604 pf->main_vsi->eth_stats.rx_broadcast -
2605 pf->main_vsi->eth_stats.rx_discards;
2606 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2607 pf->main_vsi->eth_stats.tx_multicast +
2608 pf->main_vsi->eth_stats.tx_broadcast;
2609 stats->ibytes = ns->eth.rx_bytes;
2610 stats->obytes = ns->eth.tx_bytes;
2611 stats->oerrors = ns->eth.tx_errors +
2612 pf->main_vsi->eth_stats.tx_errors;
2615 stats->imissed = ns->eth.rx_discards +
2616 pf->main_vsi->eth_stats.rx_discards;
2617 stats->ierrors = ns->crc_errors +
2618 ns->rx_length_errors + ns->rx_undersize +
2619 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2621 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2622 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2623 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2624 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2625 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2626 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2627 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2628 ns->eth.rx_unknown_protocol);
2629 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2630 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2631 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2632 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2633 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2634 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2636 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2637 ns->tx_dropped_link_down);
2638 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2639 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2641 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2642 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2643 ns->mac_local_faults);
2644 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2645 ns->mac_remote_faults);
2646 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2647 ns->rx_length_errors);
2648 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2649 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2650 for (i = 0; i < 8; i++) {
2651 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2652 i, ns->priority_xon_rx[i]);
2653 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2654 i, ns->priority_xoff_rx[i]);
2656 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2657 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2658 for (i = 0; i < 8; i++) {
2659 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2660 i, ns->priority_xon_tx[i]);
2661 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2662 i, ns->priority_xoff_tx[i]);
2663 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2664 i, ns->priority_xon_2_xoff[i]);
2666 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2667 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2668 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2669 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2670 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2671 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2672 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2673 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2674 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2675 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2676 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2677 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2678 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2679 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2680 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2681 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2682 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2683 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2684 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2685 ns->mac_short_packet_dropped);
2686 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2687 ns->checksum_error);
2688 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2689 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2692 /* Reset the statistics */
2694 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2696 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2697 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2699 /* Mark PF and VSI stats to update the offset, aka "reset" */
2700 pf->offset_loaded = false;
2702 pf->main_vsi->offset_loaded = false;
2704 /* read the stats, reading current register values into offset */
2705 i40e_read_stats_registers(pf, hw);
2709 i40e_xstats_calc_num(void)
2711 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2712 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2713 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2716 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2717 struct rte_eth_xstat_name *xstats_names,
2718 __rte_unused unsigned limit)
2723 if (xstats_names == NULL)
2724 return i40e_xstats_calc_num();
2726 /* Note: limit checked in rte_eth_xstats_names() */
2728 /* Get stats from i40e_eth_stats struct */
2729 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2730 snprintf(xstats_names[count].name,
2731 sizeof(xstats_names[count].name),
2732 "%s", rte_i40e_stats_strings[i].name);
2736 /* Get individiual stats from i40e_hw_port struct */
2737 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2738 snprintf(xstats_names[count].name,
2739 sizeof(xstats_names[count].name),
2740 "%s", rte_i40e_hw_port_strings[i].name);
2744 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2745 for (prio = 0; prio < 8; prio++) {
2746 snprintf(xstats_names[count].name,
2747 sizeof(xstats_names[count].name),
2748 "rx_priority%u_%s", prio,
2749 rte_i40e_rxq_prio_strings[i].name);
2754 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2755 for (prio = 0; prio < 8; prio++) {
2756 snprintf(xstats_names[count].name,
2757 sizeof(xstats_names[count].name),
2758 "tx_priority%u_%s", prio,
2759 rte_i40e_txq_prio_strings[i].name);
2767 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2770 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2771 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2772 unsigned i, count, prio;
2773 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2775 count = i40e_xstats_calc_num();
2779 i40e_read_stats_registers(pf, hw);
2786 /* Get stats from i40e_eth_stats struct */
2787 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2788 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2789 rte_i40e_stats_strings[i].offset);
2790 xstats[count].id = count;
2794 /* Get individiual stats from i40e_hw_port struct */
2795 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2796 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2797 rte_i40e_hw_port_strings[i].offset);
2798 xstats[count].id = count;
2802 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2803 for (prio = 0; prio < 8; prio++) {
2804 xstats[count].value =
2805 *(uint64_t *)(((char *)hw_stats) +
2806 rte_i40e_rxq_prio_strings[i].offset +
2807 (sizeof(uint64_t) * prio));
2808 xstats[count].id = count;
2813 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2814 for (prio = 0; prio < 8; prio++) {
2815 xstats[count].value =
2816 *(uint64_t *)(((char *)hw_stats) +
2817 rte_i40e_txq_prio_strings[i].offset +
2818 (sizeof(uint64_t) * prio));
2819 xstats[count].id = count;
2828 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2829 __rte_unused uint16_t queue_id,
2830 __rte_unused uint8_t stat_idx,
2831 __rte_unused uint8_t is_rx)
2833 PMD_INIT_FUNC_TRACE();
2839 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2841 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2847 full_ver = hw->nvm.oem_ver;
2848 ver = (u8)(full_ver >> 24);
2849 build = (u16)((full_ver >> 8) & 0xffff);
2850 patch = (u8)(full_ver & 0xff);
2852 ret = snprintf(fw_version, fw_size,
2853 "%d.%d%d 0x%08x %d.%d.%d",
2854 ((hw->nvm.version >> 12) & 0xf),
2855 ((hw->nvm.version >> 4) & 0xff),
2856 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2859 ret += 1; /* add the size of '\0' */
2860 if (fw_size < (u32)ret)
2867 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2869 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2870 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871 struct i40e_vsi *vsi = pf->main_vsi;
2872 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2874 dev_info->pci_dev = pci_dev;
2875 dev_info->max_rx_queues = vsi->nb_qps;
2876 dev_info->max_tx_queues = vsi->nb_qps;
2877 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2878 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2879 dev_info->max_mac_addrs = vsi->max_macaddrs;
2880 dev_info->max_vfs = pci_dev->max_vfs;
2881 dev_info->rx_offload_capa =
2882 DEV_RX_OFFLOAD_VLAN_STRIP |
2883 DEV_RX_OFFLOAD_QINQ_STRIP |
2884 DEV_RX_OFFLOAD_IPV4_CKSUM |
2885 DEV_RX_OFFLOAD_UDP_CKSUM |
2886 DEV_RX_OFFLOAD_TCP_CKSUM;
2887 dev_info->tx_offload_capa =
2888 DEV_TX_OFFLOAD_VLAN_INSERT |
2889 DEV_TX_OFFLOAD_QINQ_INSERT |
2890 DEV_TX_OFFLOAD_IPV4_CKSUM |
2891 DEV_TX_OFFLOAD_UDP_CKSUM |
2892 DEV_TX_OFFLOAD_TCP_CKSUM |
2893 DEV_TX_OFFLOAD_SCTP_CKSUM |
2894 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2895 DEV_TX_OFFLOAD_TCP_TSO |
2896 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2897 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2898 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2899 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2900 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2902 dev_info->reta_size = pf->hash_lut_size;
2903 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2905 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2907 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2908 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2909 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2911 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2915 dev_info->default_txconf = (struct rte_eth_txconf) {
2917 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2918 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2919 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2921 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2922 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2923 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2924 ETH_TXQ_FLAGS_NOOFFLOADS,
2927 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2928 .nb_max = I40E_MAX_RING_DESC,
2929 .nb_min = I40E_MIN_RING_DESC,
2930 .nb_align = I40E_ALIGN_RING_DESC,
2933 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2934 .nb_max = I40E_MAX_RING_DESC,
2935 .nb_min = I40E_MIN_RING_DESC,
2936 .nb_align = I40E_ALIGN_RING_DESC,
2937 .nb_seg_max = I40E_TX_MAX_SEG,
2938 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2941 if (pf->flags & I40E_FLAG_VMDQ) {
2942 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2943 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2944 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2945 pf->max_nb_vmdq_vsi;
2946 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2947 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2948 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2951 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2953 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2954 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2956 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2959 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2963 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2965 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2966 struct i40e_vsi *vsi = pf->main_vsi;
2967 PMD_INIT_FUNC_TRACE();
2970 return i40e_vsi_add_vlan(vsi, vlan_id);
2972 return i40e_vsi_delete_vlan(vsi, vlan_id);
2976 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2977 enum rte_vlan_type vlan_type,
2980 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2981 uint64_t reg_r = 0, reg_w = 0;
2982 uint16_t reg_id = 0;
2984 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2986 switch (vlan_type) {
2987 case ETH_VLAN_TYPE_OUTER:
2993 case ETH_VLAN_TYPE_INNER:
2999 "Unsupported vlan type in single vlan.");
3005 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
3008 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3010 if (ret != I40E_SUCCESS) {
3012 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3018 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3021 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3022 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3023 if (reg_r == reg_w) {
3025 PMD_DRV_LOG(DEBUG, "No need to write");
3029 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3031 if (ret != I40E_SUCCESS) {
3034 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3039 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3046 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3048 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3049 struct i40e_vsi *vsi = pf->main_vsi;
3051 if (mask & ETH_VLAN_FILTER_MASK) {
3052 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3053 i40e_vsi_config_vlan_filter(vsi, TRUE);
3055 i40e_vsi_config_vlan_filter(vsi, FALSE);
3058 if (mask & ETH_VLAN_STRIP_MASK) {
3059 /* Enable or disable VLAN stripping */
3060 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3061 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3063 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3066 if (mask & ETH_VLAN_EXTEND_MASK) {
3067 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3068 i40e_vsi_config_double_vlan(vsi, TRUE);
3069 /* Set global registers with default ether type value */
3070 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3072 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3076 i40e_vsi_config_double_vlan(vsi, FALSE);
3081 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3082 __rte_unused uint16_t queue,
3083 __rte_unused int on)
3085 PMD_INIT_FUNC_TRACE();
3089 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3091 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3092 struct i40e_vsi *vsi = pf->main_vsi;
3093 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3094 struct i40e_vsi_vlan_pvid_info info;
3096 memset(&info, 0, sizeof(info));
3099 info.config.pvid = pvid;
3101 info.config.reject.tagged =
3102 data->dev_conf.txmode.hw_vlan_reject_tagged;
3103 info.config.reject.untagged =
3104 data->dev_conf.txmode.hw_vlan_reject_untagged;
3107 return i40e_vsi_vlan_pvid_set(vsi, &info);
3111 i40e_dev_led_on(struct rte_eth_dev *dev)
3113 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3114 uint32_t mode = i40e_led_get(hw);
3117 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3123 i40e_dev_led_off(struct rte_eth_dev *dev)
3125 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3126 uint32_t mode = i40e_led_get(hw);
3129 i40e_led_set(hw, 0, false);
3135 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3137 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3140 fc_conf->pause_time = pf->fc_conf.pause_time;
3141 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3142 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3144 /* Return current mode according to actual setting*/
3145 switch (hw->fc.current_mode) {
3147 fc_conf->mode = RTE_FC_FULL;
3149 case I40E_FC_TX_PAUSE:
3150 fc_conf->mode = RTE_FC_TX_PAUSE;
3152 case I40E_FC_RX_PAUSE:
3153 fc_conf->mode = RTE_FC_RX_PAUSE;
3157 fc_conf->mode = RTE_FC_NONE;
3164 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3166 uint32_t mflcn_reg, fctrl_reg, reg;
3167 uint32_t max_high_water;
3168 uint8_t i, aq_failure;
3172 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3173 [RTE_FC_NONE] = I40E_FC_NONE,
3174 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3175 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3176 [RTE_FC_FULL] = I40E_FC_FULL
3179 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3181 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3182 if ((fc_conf->high_water > max_high_water) ||
3183 (fc_conf->high_water < fc_conf->low_water)) {
3185 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3190 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3191 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3192 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3194 pf->fc_conf.pause_time = fc_conf->pause_time;
3195 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3196 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3198 PMD_INIT_FUNC_TRACE();
3200 /* All the link flow control related enable/disable register
3201 * configuration is handle by the F/W
3203 err = i40e_set_fc(hw, &aq_failure, true);
3207 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3208 /* Configure flow control refresh threshold,
3209 * the value for stat_tx_pause_refresh_timer[8]
3210 * is used for global pause operation.
3214 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3215 pf->fc_conf.pause_time);
3217 /* configure the timer value included in transmitted pause
3219 * the value for stat_tx_pause_quanta[8] is used for global
3222 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3223 pf->fc_conf.pause_time);
3225 fctrl_reg = I40E_READ_REG(hw,
3226 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3228 if (fc_conf->mac_ctrl_frame_fwd != 0)
3229 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3231 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3233 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3236 /* Configure pause time (2 TCs per register) */
3237 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3238 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3239 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3241 /* Configure flow control refresh threshold value */
3242 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3243 pf->fc_conf.pause_time / 2);
3245 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3247 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3248 *depending on configuration
3250 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3251 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3252 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3254 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3255 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3258 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3261 /* config the water marker both based on the packets and bytes */
3262 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3263 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3264 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3265 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3266 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3267 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3268 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3269 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3271 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3272 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3275 I40E_WRITE_FLUSH(hw);
3281 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3282 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3284 PMD_INIT_FUNC_TRACE();
3289 /* Add a MAC address, and update filters */
3291 i40e_macaddr_add(struct rte_eth_dev *dev,
3292 struct ether_addr *mac_addr,
3293 __rte_unused uint32_t index,
3296 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3297 struct i40e_mac_filter_info mac_filter;
3298 struct i40e_vsi *vsi;
3301 /* If VMDQ not enabled or configured, return */
3302 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3303 !pf->nb_cfg_vmdq_vsi)) {
3304 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3305 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3310 if (pool > pf->nb_cfg_vmdq_vsi) {
3311 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3312 pool, pf->nb_cfg_vmdq_vsi);
3316 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3317 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3318 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3320 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3325 vsi = pf->vmdq[pool - 1].vsi;
3327 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3328 if (ret != I40E_SUCCESS) {
3329 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3335 /* Remove a MAC address, and update filters */
3337 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3339 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3340 struct i40e_vsi *vsi;
3341 struct rte_eth_dev_data *data = dev->data;
3342 struct ether_addr *macaddr;
3347 macaddr = &(data->mac_addrs[index]);
3349 pool_sel = dev->data->mac_pool_sel[index];
3351 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3352 if (pool_sel & (1ULL << i)) {
3356 /* No VMDQ pool enabled or configured */
3357 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3358 (i > pf->nb_cfg_vmdq_vsi)) {
3360 "No VMDQ pool enabled/configured");
3363 vsi = pf->vmdq[i - 1].vsi;
3365 ret = i40e_vsi_delete_mac(vsi, macaddr);
3368 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3375 /* Set perfect match or hash match of MAC and VLAN for a VF */
3377 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3378 struct rte_eth_mac_filter *filter,
3382 struct i40e_mac_filter_info mac_filter;
3383 struct ether_addr old_mac;
3384 struct ether_addr *new_mac;
3385 struct i40e_pf_vf *vf = NULL;
3390 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3393 hw = I40E_PF_TO_HW(pf);
3395 if (filter == NULL) {
3396 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3400 new_mac = &filter->mac_addr;
3402 if (is_zero_ether_addr(new_mac)) {
3403 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3407 vf_id = filter->dst_id;
3409 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3410 PMD_DRV_LOG(ERR, "Invalid argument.");
3413 vf = &pf->vfs[vf_id];
3415 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3416 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3421 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3422 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3424 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3427 mac_filter.filter_type = filter->filter_type;
3428 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3429 if (ret != I40E_SUCCESS) {
3430 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3433 ether_addr_copy(new_mac, &pf->dev_addr);
3435 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3437 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3438 if (ret != I40E_SUCCESS) {
3439 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3443 /* Clear device address as it has been removed */
3444 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3445 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3451 /* MAC filter handle */
3453 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3456 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3457 struct rte_eth_mac_filter *filter;
3458 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3459 int ret = I40E_NOT_SUPPORTED;
3461 filter = (struct rte_eth_mac_filter *)(arg);
3463 switch (filter_op) {
3464 case RTE_ETH_FILTER_NOP:
3467 case RTE_ETH_FILTER_ADD:
3468 i40e_pf_disable_irq0(hw);
3470 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3471 i40e_pf_enable_irq0(hw);
3473 case RTE_ETH_FILTER_DELETE:
3474 i40e_pf_disable_irq0(hw);
3476 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3477 i40e_pf_enable_irq0(hw);
3480 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3481 ret = I40E_ERR_PARAM;
3489 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3491 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3492 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3498 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3499 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3502 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3506 uint32_t *lut_dw = (uint32_t *)lut;
3507 uint16_t i, lut_size_dw = lut_size / 4;
3509 for (i = 0; i < lut_size_dw; i++)
3510 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3517 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3526 pf = I40E_VSI_TO_PF(vsi);
3527 hw = I40E_VSI_TO_HW(vsi);
3529 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3530 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3533 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3537 uint32_t *lut_dw = (uint32_t *)lut;
3538 uint16_t i, lut_size_dw = lut_size / 4;
3540 for (i = 0; i < lut_size_dw; i++)
3541 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3542 I40E_WRITE_FLUSH(hw);
3549 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3550 struct rte_eth_rss_reta_entry64 *reta_conf,
3553 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3554 uint16_t i, lut_size = pf->hash_lut_size;
3555 uint16_t idx, shift;
3559 if (reta_size != lut_size ||
3560 reta_size > ETH_RSS_RETA_SIZE_512) {
3562 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3563 reta_size, lut_size);
3567 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3569 PMD_DRV_LOG(ERR, "No memory can be allocated");
3572 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3575 for (i = 0; i < reta_size; i++) {
3576 idx = i / RTE_RETA_GROUP_SIZE;
3577 shift = i % RTE_RETA_GROUP_SIZE;
3578 if (reta_conf[idx].mask & (1ULL << shift))
3579 lut[i] = reta_conf[idx].reta[shift];
3581 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3590 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3591 struct rte_eth_rss_reta_entry64 *reta_conf,
3594 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3595 uint16_t i, lut_size = pf->hash_lut_size;
3596 uint16_t idx, shift;
3600 if (reta_size != lut_size ||
3601 reta_size > ETH_RSS_RETA_SIZE_512) {
3603 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3604 reta_size, lut_size);
3608 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3610 PMD_DRV_LOG(ERR, "No memory can be allocated");
3614 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3617 for (i = 0; i < reta_size; i++) {
3618 idx = i / RTE_RETA_GROUP_SIZE;
3619 shift = i % RTE_RETA_GROUP_SIZE;
3620 if (reta_conf[idx].mask & (1ULL << shift))
3621 reta_conf[idx].reta[shift] = lut[i];
3631 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3632 * @hw: pointer to the HW structure
3633 * @mem: pointer to mem struct to fill out
3634 * @size: size of memory requested
3635 * @alignment: what to align the allocation to
3637 enum i40e_status_code
3638 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3639 struct i40e_dma_mem *mem,
3643 const struct rte_memzone *mz = NULL;
3644 char z_name[RTE_MEMZONE_NAMESIZE];
3647 return I40E_ERR_PARAM;
3649 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3650 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3651 alignment, RTE_PGSIZE_2M);
3653 return I40E_ERR_NO_MEMORY;
3657 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3658 mem->zone = (const void *)mz;
3660 "memzone %s allocated with physical address: %"PRIu64,
3663 return I40E_SUCCESS;
3667 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3668 * @hw: pointer to the HW structure
3669 * @mem: ptr to mem struct to free
3671 enum i40e_status_code
3672 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3673 struct i40e_dma_mem *mem)
3676 return I40E_ERR_PARAM;
3679 "memzone %s to be freed with physical address: %"PRIu64,
3680 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3681 rte_memzone_free((const struct rte_memzone *)mem->zone);
3686 return I40E_SUCCESS;
3690 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3691 * @hw: pointer to the HW structure
3692 * @mem: pointer to mem struct to fill out
3693 * @size: size of memory requested
3695 enum i40e_status_code
3696 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3697 struct i40e_virt_mem *mem,
3701 return I40E_ERR_PARAM;
3704 mem->va = rte_zmalloc("i40e", size, 0);
3707 return I40E_SUCCESS;
3709 return I40E_ERR_NO_MEMORY;
3713 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3714 * @hw: pointer to the HW structure
3715 * @mem: pointer to mem struct to free
3717 enum i40e_status_code
3718 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3719 struct i40e_virt_mem *mem)
3722 return I40E_ERR_PARAM;
3727 return I40E_SUCCESS;
3731 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3733 rte_spinlock_init(&sp->spinlock);
3737 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3739 rte_spinlock_lock(&sp->spinlock);
3743 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3745 rte_spinlock_unlock(&sp->spinlock);
3749 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3755 * Get the hardware capabilities, which will be parsed
3756 * and saved into struct i40e_hw.
3759 i40e_get_cap(struct i40e_hw *hw)
3761 struct i40e_aqc_list_capabilities_element_resp *buf;
3762 uint16_t len, size = 0;
3765 /* Calculate a huge enough buff for saving response data temporarily */
3766 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3767 I40E_MAX_CAP_ELE_NUM;
3768 buf = rte_zmalloc("i40e", len, 0);
3770 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3771 return I40E_ERR_NO_MEMORY;
3774 /* Get, parse the capabilities and save it to hw */
3775 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3776 i40e_aqc_opc_list_func_capabilities, NULL);
3777 if (ret != I40E_SUCCESS)
3778 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3780 /* Free the temporary buffer after being used */
3787 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3789 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3790 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3791 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3792 uint16_t qp_count = 0, vsi_count = 0;
3794 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3795 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3798 /* Add the parameter init for LFC */
3799 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3800 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3801 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3803 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3804 pf->max_num_vsi = hw->func_caps.num_vsis;
3805 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3806 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3807 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3809 /* FDir queue/VSI allocation */
3810 pf->fdir_qp_offset = 0;
3811 if (hw->func_caps.fd) {
3812 pf->flags |= I40E_FLAG_FDIR;
3813 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3815 pf->fdir_nb_qps = 0;
3817 qp_count += pf->fdir_nb_qps;
3820 /* LAN queue/VSI allocation */
3821 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3822 if (!hw->func_caps.rss) {
3825 pf->flags |= I40E_FLAG_RSS;
3826 if (hw->mac.type == I40E_MAC_X722)
3827 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3828 pf->lan_nb_qps = pf->lan_nb_qp_max;
3830 qp_count += pf->lan_nb_qps;
3833 /* VF queue/VSI allocation */
3834 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3835 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3836 pf->flags |= I40E_FLAG_SRIOV;
3837 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3838 pf->vf_num = pci_dev->max_vfs;
3840 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3841 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3846 qp_count += pf->vf_nb_qps * pf->vf_num;
3847 vsi_count += pf->vf_num;
3849 /* VMDq queue/VSI allocation */
3850 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3851 pf->vmdq_nb_qps = 0;
3852 pf->max_nb_vmdq_vsi = 0;
3853 if (hw->func_caps.vmdq) {
3854 if (qp_count < hw->func_caps.num_tx_qp &&
3855 vsi_count < hw->func_caps.num_vsis) {
3856 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3857 qp_count) / pf->vmdq_nb_qp_max;
3859 /* Limit the maximum number of VMDq vsi to the maximum
3860 * ethdev can support
3862 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3863 hw->func_caps.num_vsis - vsi_count);
3864 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3866 if (pf->max_nb_vmdq_vsi) {
3867 pf->flags |= I40E_FLAG_VMDQ;
3868 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3870 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3871 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3872 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3875 "No enough queues left for VMDq");
3878 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3881 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3882 vsi_count += pf->max_nb_vmdq_vsi;
3884 if (hw->func_caps.dcb)
3885 pf->flags |= I40E_FLAG_DCB;
3887 if (qp_count > hw->func_caps.num_tx_qp) {
3889 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3890 qp_count, hw->func_caps.num_tx_qp);
3893 if (vsi_count > hw->func_caps.num_vsis) {
3895 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3896 vsi_count, hw->func_caps.num_vsis);
3904 i40e_pf_get_switch_config(struct i40e_pf *pf)
3906 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3907 struct i40e_aqc_get_switch_config_resp *switch_config;
3908 struct i40e_aqc_switch_config_element_resp *element;
3909 uint16_t start_seid = 0, num_reported;
3912 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3913 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3914 if (!switch_config) {
3915 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3919 /* Get the switch configurations */
3920 ret = i40e_aq_get_switch_config(hw, switch_config,
3921 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3922 if (ret != I40E_SUCCESS) {
3923 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3926 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3927 if (num_reported != 1) { /* The number should be 1 */
3928 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3932 /* Parse the switch configuration elements */
3933 element = &(switch_config->element[0]);
3934 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3935 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3936 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3938 PMD_DRV_LOG(INFO, "Unknown element type");
3941 rte_free(switch_config);
3947 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3950 struct pool_entry *entry;
3952 if (pool == NULL || num == 0)
3955 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3956 if (entry == NULL) {
3957 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3961 /* queue heap initialize */
3962 pool->num_free = num;
3963 pool->num_alloc = 0;
3965 LIST_INIT(&pool->alloc_list);
3966 LIST_INIT(&pool->free_list);
3968 /* Initialize element */
3972 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3977 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3979 struct pool_entry *entry, *next_entry;
3984 for (entry = LIST_FIRST(&pool->alloc_list);
3985 entry && (next_entry = LIST_NEXT(entry, next), 1);
3986 entry = next_entry) {
3987 LIST_REMOVE(entry, next);
3991 for (entry = LIST_FIRST(&pool->free_list);
3992 entry && (next_entry = LIST_NEXT(entry, next), 1);
3993 entry = next_entry) {
3994 LIST_REMOVE(entry, next);
3999 pool->num_alloc = 0;
4001 LIST_INIT(&pool->alloc_list);
4002 LIST_INIT(&pool->free_list);
4006 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4009 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4010 uint32_t pool_offset;
4014 PMD_DRV_LOG(ERR, "Invalid parameter");
4018 pool_offset = base - pool->base;
4019 /* Lookup in alloc list */
4020 LIST_FOREACH(entry, &pool->alloc_list, next) {
4021 if (entry->base == pool_offset) {
4022 valid_entry = entry;
4023 LIST_REMOVE(entry, next);
4028 /* Not find, return */
4029 if (valid_entry == NULL) {
4030 PMD_DRV_LOG(ERR, "Failed to find entry");
4035 * Found it, move it to free list and try to merge.
4036 * In order to make merge easier, always sort it by qbase.
4037 * Find adjacent prev and last entries.
4040 LIST_FOREACH(entry, &pool->free_list, next) {
4041 if (entry->base > valid_entry->base) {
4049 /* Try to merge with next one*/
4051 /* Merge with next one */
4052 if (valid_entry->base + valid_entry->len == next->base) {
4053 next->base = valid_entry->base;
4054 next->len += valid_entry->len;
4055 rte_free(valid_entry);
4062 /* Merge with previous one */
4063 if (prev->base + prev->len == valid_entry->base) {
4064 prev->len += valid_entry->len;
4065 /* If it merge with next one, remove next node */
4067 LIST_REMOVE(valid_entry, next);
4068 rte_free(valid_entry);
4070 rte_free(valid_entry);
4076 /* Not find any entry to merge, insert */
4079 LIST_INSERT_AFTER(prev, valid_entry, next);
4080 else if (next != NULL)
4081 LIST_INSERT_BEFORE(next, valid_entry, next);
4082 else /* It's empty list, insert to head */
4083 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4086 pool->num_free += valid_entry->len;
4087 pool->num_alloc -= valid_entry->len;
4093 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4096 struct pool_entry *entry, *valid_entry;
4098 if (pool == NULL || num == 0) {
4099 PMD_DRV_LOG(ERR, "Invalid parameter");
4103 if (pool->num_free < num) {
4104 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4105 num, pool->num_free);
4110 /* Lookup in free list and find most fit one */
4111 LIST_FOREACH(entry, &pool->free_list, next) {
4112 if (entry->len >= num) {
4114 if (entry->len == num) {
4115 valid_entry = entry;
4118 if (valid_entry == NULL || valid_entry->len > entry->len)
4119 valid_entry = entry;
4123 /* Not find one to satisfy the request, return */
4124 if (valid_entry == NULL) {
4125 PMD_DRV_LOG(ERR, "No valid entry found");
4129 * The entry have equal queue number as requested,
4130 * remove it from alloc_list.
4132 if (valid_entry->len == num) {
4133 LIST_REMOVE(valid_entry, next);
4136 * The entry have more numbers than requested,
4137 * create a new entry for alloc_list and minus its
4138 * queue base and number in free_list.
4140 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4141 if (entry == NULL) {
4143 "Failed to allocate memory for resource pool");
4146 entry->base = valid_entry->base;
4148 valid_entry->base += num;
4149 valid_entry->len -= num;
4150 valid_entry = entry;
4153 /* Insert it into alloc list, not sorted */
4154 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4156 pool->num_free -= valid_entry->len;
4157 pool->num_alloc += valid_entry->len;
4159 return valid_entry->base + pool->base;
4163 * bitmap_is_subset - Check whether src2 is subset of src1
4166 bitmap_is_subset(uint8_t src1, uint8_t src2)
4168 return !((src1 ^ src2) & src2);
4171 static enum i40e_status_code
4172 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4174 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4176 /* If DCB is not supported, only default TC is supported */
4177 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4178 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4179 return I40E_NOT_SUPPORTED;
4182 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4184 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4185 hw->func_caps.enabled_tcmap, enabled_tcmap);
4186 return I40E_NOT_SUPPORTED;
4188 return I40E_SUCCESS;
4192 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4193 struct i40e_vsi_vlan_pvid_info *info)
4196 struct i40e_vsi_context ctxt;
4197 uint8_t vlan_flags = 0;
4200 if (vsi == NULL || info == NULL) {
4201 PMD_DRV_LOG(ERR, "invalid parameters");
4202 return I40E_ERR_PARAM;
4206 vsi->info.pvid = info->config.pvid;
4208 * If insert pvid is enabled, only tagged pkts are
4209 * allowed to be sent out.
4211 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4212 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4215 if (info->config.reject.tagged == 0)
4216 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4218 if (info->config.reject.untagged == 0)
4219 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4221 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4222 I40E_AQ_VSI_PVLAN_MODE_MASK);
4223 vsi->info.port_vlan_flags |= vlan_flags;
4224 vsi->info.valid_sections =
4225 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4226 memset(&ctxt, 0, sizeof(ctxt));
4227 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4228 ctxt.seid = vsi->seid;
4230 hw = I40E_VSI_TO_HW(vsi);
4231 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4232 if (ret != I40E_SUCCESS)
4233 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4239 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4241 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4243 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4245 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4246 if (ret != I40E_SUCCESS)
4250 PMD_DRV_LOG(ERR, "seid not valid");
4254 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4255 tc_bw_data.tc_valid_bits = enabled_tcmap;
4256 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4257 tc_bw_data.tc_bw_credits[i] =
4258 (enabled_tcmap & (1 << i)) ? 1 : 0;
4260 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4261 if (ret != I40E_SUCCESS) {
4262 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4266 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4267 sizeof(vsi->info.qs_handle));
4268 return I40E_SUCCESS;
4271 static enum i40e_status_code
4272 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4273 struct i40e_aqc_vsi_properties_data *info,
4274 uint8_t enabled_tcmap)
4276 enum i40e_status_code ret;
4277 int i, total_tc = 0;
4278 uint16_t qpnum_per_tc, bsf, qp_idx;
4280 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4281 if (ret != I40E_SUCCESS)
4284 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4285 if (enabled_tcmap & (1 << i))
4287 vsi->enabled_tc = enabled_tcmap;
4289 /* Number of queues per enabled TC */
4290 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4291 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4292 bsf = rte_bsf32(qpnum_per_tc);
4294 /* Adjust the queue number to actual queues that can be applied */
4295 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4296 vsi->nb_qps = qpnum_per_tc * total_tc;
4299 * Configure TC and queue mapping parameters, for enabled TC,
4300 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4301 * default queue will serve it.
4304 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4305 if (vsi->enabled_tc & (1 << i)) {
4306 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4307 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4308 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4309 qp_idx += qpnum_per_tc;
4311 info->tc_mapping[i] = 0;
4314 /* Associate queue number with VSI */
4315 if (vsi->type == I40E_VSI_SRIOV) {
4316 info->mapping_flags |=
4317 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4318 for (i = 0; i < vsi->nb_qps; i++)
4319 info->queue_mapping[i] =
4320 rte_cpu_to_le_16(vsi->base_queue + i);
4322 info->mapping_flags |=
4323 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4324 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4326 info->valid_sections |=
4327 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4329 return I40E_SUCCESS;
4333 i40e_veb_release(struct i40e_veb *veb)
4335 struct i40e_vsi *vsi;
4341 if (!TAILQ_EMPTY(&veb->head)) {
4342 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4345 /* associate_vsi field is NULL for floating VEB */
4346 if (veb->associate_vsi != NULL) {
4347 vsi = veb->associate_vsi;
4348 hw = I40E_VSI_TO_HW(vsi);
4350 vsi->uplink_seid = veb->uplink_seid;
4353 veb->associate_pf->main_vsi->floating_veb = NULL;
4354 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4357 i40e_aq_delete_element(hw, veb->seid, NULL);
4359 return I40E_SUCCESS;
4363 static struct i40e_veb *
4364 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4366 struct i40e_veb *veb;
4372 "veb setup failed, associated PF shouldn't null");
4375 hw = I40E_PF_TO_HW(pf);
4377 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4379 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4383 veb->associate_vsi = vsi;
4384 veb->associate_pf = pf;
4385 TAILQ_INIT(&veb->head);
4386 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4388 /* create floating veb if vsi is NULL */
4390 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4391 I40E_DEFAULT_TCMAP, false,
4392 &veb->seid, false, NULL);
4394 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4395 true, &veb->seid, false, NULL);
4398 if (ret != I40E_SUCCESS) {
4399 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4400 hw->aq.asq_last_status);
4403 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4405 /* get statistics index */
4406 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4407 &veb->stats_idx, NULL, NULL, NULL);
4408 if (ret != I40E_SUCCESS) {
4409 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4410 hw->aq.asq_last_status);
4413 /* Get VEB bandwidth, to be implemented */
4414 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4416 vsi->uplink_seid = veb->seid;
4425 i40e_vsi_release(struct i40e_vsi *vsi)
4429 struct i40e_vsi_list *vsi_list;
4432 struct i40e_mac_filter *f;
4433 uint16_t user_param;
4436 return I40E_SUCCESS;
4441 user_param = vsi->user_param;
4443 pf = I40E_VSI_TO_PF(vsi);
4444 hw = I40E_VSI_TO_HW(vsi);
4446 /* VSI has child to attach, release child first */
4448 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4449 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4452 i40e_veb_release(vsi->veb);
4455 if (vsi->floating_veb) {
4456 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4457 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4462 /* Remove all macvlan filters of the VSI */
4463 i40e_vsi_remove_all_macvlan_filter(vsi);
4464 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4467 if (vsi->type != I40E_VSI_MAIN &&
4468 ((vsi->type != I40E_VSI_SRIOV) ||
4469 !pf->floating_veb_list[user_param])) {
4470 /* Remove vsi from parent's sibling list */
4471 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4472 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4473 return I40E_ERR_PARAM;
4475 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4476 &vsi->sib_vsi_list, list);
4478 /* Remove all switch element of the VSI */
4479 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4480 if (ret != I40E_SUCCESS)
4481 PMD_DRV_LOG(ERR, "Failed to delete element");
4484 if ((vsi->type == I40E_VSI_SRIOV) &&
4485 pf->floating_veb_list[user_param]) {
4486 /* Remove vsi from parent's sibling list */
4487 if (vsi->parent_vsi == NULL ||
4488 vsi->parent_vsi->floating_veb == NULL) {
4489 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4490 return I40E_ERR_PARAM;
4492 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4493 &vsi->sib_vsi_list, list);
4495 /* Remove all switch element of the VSI */
4496 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4497 if (ret != I40E_SUCCESS)
4498 PMD_DRV_LOG(ERR, "Failed to delete element");
4501 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4503 if (vsi->type != I40E_VSI_SRIOV)
4504 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4507 return I40E_SUCCESS;
4511 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4513 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4514 struct i40e_aqc_remove_macvlan_element_data def_filter;
4515 struct i40e_mac_filter_info filter;
4518 if (vsi->type != I40E_VSI_MAIN)
4519 return I40E_ERR_CONFIG;
4520 memset(&def_filter, 0, sizeof(def_filter));
4521 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4523 def_filter.vlan_tag = 0;
4524 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4525 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4526 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4527 if (ret != I40E_SUCCESS) {
4528 struct i40e_mac_filter *f;
4529 struct ether_addr *mac;
4532 "Cannot remove the default macvlan filter");
4533 /* It needs to add the permanent mac into mac list */
4534 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4536 PMD_DRV_LOG(ERR, "failed to allocate memory");
4537 return I40E_ERR_NO_MEMORY;
4539 mac = &f->mac_info.mac_addr;
4540 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4542 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4543 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4548 (void)rte_memcpy(&filter.mac_addr,
4549 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4550 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4551 return i40e_vsi_add_mac(vsi, &filter);
4555 * i40e_vsi_get_bw_config - Query VSI BW Information
4556 * @vsi: the VSI to be queried
4558 * Returns 0 on success, negative value on failure
4560 static enum i40e_status_code
4561 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4563 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4564 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4565 struct i40e_hw *hw = &vsi->adapter->hw;
4570 memset(&bw_config, 0, sizeof(bw_config));
4571 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4572 if (ret != I40E_SUCCESS) {
4573 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4574 hw->aq.asq_last_status);
4578 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4579 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4580 &ets_sla_config, NULL);
4581 if (ret != I40E_SUCCESS) {
4583 "VSI failed to get TC bandwdith configuration %u",
4584 hw->aq.asq_last_status);
4588 /* store and print out BW info */
4589 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4590 vsi->bw_info.bw_max = bw_config.max_bw;
4591 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4592 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4593 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4594 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4596 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4597 vsi->bw_info.bw_ets_share_credits[i] =
4598 ets_sla_config.share_credits[i];
4599 vsi->bw_info.bw_ets_credits[i] =
4600 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4601 /* 4 bits per TC, 4th bit is reserved */
4602 vsi->bw_info.bw_ets_max[i] =
4603 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4604 RTE_LEN2MASK(3, uint8_t));
4605 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4606 vsi->bw_info.bw_ets_share_credits[i]);
4607 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4608 vsi->bw_info.bw_ets_credits[i]);
4609 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4610 vsi->bw_info.bw_ets_max[i]);
4613 return I40E_SUCCESS;
4616 /* i40e_enable_pf_lb
4617 * @pf: pointer to the pf structure
4619 * allow loopback on pf
4622 i40e_enable_pf_lb(struct i40e_pf *pf)
4624 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4625 struct i40e_vsi_context ctxt;
4628 /* Use the FW API if FW >= v5.0 */
4629 if (hw->aq.fw_maj_ver < 5) {
4630 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4634 memset(&ctxt, 0, sizeof(ctxt));
4635 ctxt.seid = pf->main_vsi_seid;
4636 ctxt.pf_num = hw->pf_id;
4637 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4639 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4640 ret, hw->aq.asq_last_status);
4643 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4644 ctxt.info.valid_sections =
4645 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4646 ctxt.info.switch_id |=
4647 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4649 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4651 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4652 hw->aq.asq_last_status);
4657 i40e_vsi_setup(struct i40e_pf *pf,
4658 enum i40e_vsi_type type,
4659 struct i40e_vsi *uplink_vsi,
4660 uint16_t user_param)
4662 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4663 struct i40e_vsi *vsi;
4664 struct i40e_mac_filter_info filter;
4666 struct i40e_vsi_context ctxt;
4667 struct ether_addr broadcast =
4668 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4670 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4671 uplink_vsi == NULL) {
4673 "VSI setup failed, VSI link shouldn't be NULL");
4677 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4679 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4684 * 1.type is not MAIN and uplink vsi is not NULL
4685 * If uplink vsi didn't setup VEB, create one first under veb field
4686 * 2.type is SRIOV and the uplink is NULL
4687 * If floating VEB is NULL, create one veb under floating veb field
4690 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4691 uplink_vsi->veb == NULL) {
4692 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4694 if (uplink_vsi->veb == NULL) {
4695 PMD_DRV_LOG(ERR, "VEB setup failed");
4698 /* set ALLOWLOOPBACk on pf, when veb is created */
4699 i40e_enable_pf_lb(pf);
4702 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4703 pf->main_vsi->floating_veb == NULL) {
4704 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4706 if (pf->main_vsi->floating_veb == NULL) {
4707 PMD_DRV_LOG(ERR, "VEB setup failed");
4712 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4714 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4717 TAILQ_INIT(&vsi->mac_list);
4719 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4720 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4721 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4722 vsi->user_param = user_param;
4723 vsi->vlan_anti_spoof_on = 0;
4724 vsi->vlan_filter_on = 0;
4725 /* Allocate queues */
4726 switch (vsi->type) {
4727 case I40E_VSI_MAIN :
4728 vsi->nb_qps = pf->lan_nb_qps;
4730 case I40E_VSI_SRIOV :
4731 vsi->nb_qps = pf->vf_nb_qps;
4733 case I40E_VSI_VMDQ2:
4734 vsi->nb_qps = pf->vmdq_nb_qps;
4737 vsi->nb_qps = pf->fdir_nb_qps;
4743 * The filter status descriptor is reported in rx queue 0,
4744 * while the tx queue for fdir filter programming has no
4745 * such constraints, can be non-zero queues.
4746 * To simplify it, choose FDIR vsi use queue 0 pair.
4747 * To make sure it will use queue 0 pair, queue allocation
4748 * need be done before this function is called
4750 if (type != I40E_VSI_FDIR) {
4751 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4753 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4757 vsi->base_queue = ret;
4759 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4761 /* VF has MSIX interrupt in VF range, don't allocate here */
4762 if (type == I40E_VSI_MAIN) {
4763 ret = i40e_res_pool_alloc(&pf->msix_pool,
4764 RTE_MIN(vsi->nb_qps,
4765 RTE_MAX_RXTX_INTR_VEC_ID));
4767 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4769 goto fail_queue_alloc;
4771 vsi->msix_intr = ret;
4772 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4773 } else if (type != I40E_VSI_SRIOV) {
4774 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4776 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4777 goto fail_queue_alloc;
4779 vsi->msix_intr = ret;
4787 if (type == I40E_VSI_MAIN) {
4788 /* For main VSI, no need to add since it's default one */
4789 vsi->uplink_seid = pf->mac_seid;
4790 vsi->seid = pf->main_vsi_seid;
4791 /* Bind queues with specific MSIX interrupt */
4793 * Needs 2 interrupt at least, one for misc cause which will
4794 * enabled from OS side, Another for queues binding the
4795 * interrupt from device side only.
4798 /* Get default VSI parameters from hardware */
4799 memset(&ctxt, 0, sizeof(ctxt));
4800 ctxt.seid = vsi->seid;
4801 ctxt.pf_num = hw->pf_id;
4802 ctxt.uplink_seid = vsi->uplink_seid;
4804 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4805 if (ret != I40E_SUCCESS) {
4806 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4807 goto fail_msix_alloc;
4809 (void)rte_memcpy(&vsi->info, &ctxt.info,
4810 sizeof(struct i40e_aqc_vsi_properties_data));
4811 vsi->vsi_id = ctxt.vsi_number;
4812 vsi->info.valid_sections = 0;
4814 /* Configure tc, enabled TC0 only */
4815 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4817 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4818 goto fail_msix_alloc;
4821 /* TC, queue mapping */
4822 memset(&ctxt, 0, sizeof(ctxt));
4823 vsi->info.valid_sections |=
4824 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4825 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4826 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4827 (void)rte_memcpy(&ctxt.info, &vsi->info,
4828 sizeof(struct i40e_aqc_vsi_properties_data));
4829 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4830 I40E_DEFAULT_TCMAP);
4831 if (ret != I40E_SUCCESS) {
4833 "Failed to configure TC queue mapping");
4834 goto fail_msix_alloc;
4836 ctxt.seid = vsi->seid;
4837 ctxt.pf_num = hw->pf_id;
4838 ctxt.uplink_seid = vsi->uplink_seid;
4841 /* Update VSI parameters */
4842 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4843 if (ret != I40E_SUCCESS) {
4844 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4845 goto fail_msix_alloc;
4848 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4849 sizeof(vsi->info.tc_mapping));
4850 (void)rte_memcpy(&vsi->info.queue_mapping,
4851 &ctxt.info.queue_mapping,
4852 sizeof(vsi->info.queue_mapping));
4853 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4854 vsi->info.valid_sections = 0;
4856 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4860 * Updating default filter settings are necessary to prevent
4861 * reception of tagged packets.
4862 * Some old firmware configurations load a default macvlan
4863 * filter which accepts both tagged and untagged packets.
4864 * The updating is to use a normal filter instead if needed.
4865 * For NVM 4.2.2 or after, the updating is not needed anymore.
4866 * The firmware with correct configurations load the default
4867 * macvlan filter which is expected and cannot be removed.
4869 i40e_update_default_filter_setting(vsi);
4870 i40e_config_qinq(hw, vsi);
4871 } else if (type == I40E_VSI_SRIOV) {
4872 memset(&ctxt, 0, sizeof(ctxt));
4874 * For other VSI, the uplink_seid equals to uplink VSI's
4875 * uplink_seid since they share same VEB
4877 if (uplink_vsi == NULL)
4878 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4880 vsi->uplink_seid = uplink_vsi->uplink_seid;
4881 ctxt.pf_num = hw->pf_id;
4882 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4883 ctxt.uplink_seid = vsi->uplink_seid;
4884 ctxt.connection_type = 0x1;
4885 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4887 /* Use the VEB configuration if FW >= v5.0 */
4888 if (hw->aq.fw_maj_ver >= 5) {
4889 /* Configure switch ID */
4890 ctxt.info.valid_sections |=
4891 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4892 ctxt.info.switch_id =
4893 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4896 /* Configure port/vlan */
4897 ctxt.info.valid_sections |=
4898 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4899 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4900 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4901 hw->func_caps.enabled_tcmap);
4902 if (ret != I40E_SUCCESS) {
4904 "Failed to configure TC queue mapping");
4905 goto fail_msix_alloc;
4908 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4909 ctxt.info.valid_sections |=
4910 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4912 * Since VSI is not created yet, only configure parameter,
4913 * will add vsi below.
4916 i40e_config_qinq(hw, vsi);
4917 } else if (type == I40E_VSI_VMDQ2) {
4918 memset(&ctxt, 0, sizeof(ctxt));
4920 * For other VSI, the uplink_seid equals to uplink VSI's
4921 * uplink_seid since they share same VEB
4923 vsi->uplink_seid = uplink_vsi->uplink_seid;
4924 ctxt.pf_num = hw->pf_id;
4926 ctxt.uplink_seid = vsi->uplink_seid;
4927 ctxt.connection_type = 0x1;
4928 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4930 ctxt.info.valid_sections |=
4931 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4932 /* user_param carries flag to enable loop back */
4934 ctxt.info.switch_id =
4935 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4936 ctxt.info.switch_id |=
4937 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4940 /* Configure port/vlan */
4941 ctxt.info.valid_sections |=
4942 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4943 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4944 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4945 I40E_DEFAULT_TCMAP);
4946 if (ret != I40E_SUCCESS) {
4948 "Failed to configure TC queue mapping");
4949 goto fail_msix_alloc;
4951 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4952 ctxt.info.valid_sections |=
4953 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4954 } else if (type == I40E_VSI_FDIR) {
4955 memset(&ctxt, 0, sizeof(ctxt));
4956 vsi->uplink_seid = uplink_vsi->uplink_seid;
4957 ctxt.pf_num = hw->pf_id;
4959 ctxt.uplink_seid = vsi->uplink_seid;
4960 ctxt.connection_type = 0x1; /* regular data port */
4961 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4962 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4963 I40E_DEFAULT_TCMAP);
4964 if (ret != I40E_SUCCESS) {
4966 "Failed to configure TC queue mapping.");
4967 goto fail_msix_alloc;
4969 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4970 ctxt.info.valid_sections |=
4971 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4973 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4974 goto fail_msix_alloc;
4977 if (vsi->type != I40E_VSI_MAIN) {
4978 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4979 if (ret != I40E_SUCCESS) {
4980 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4981 hw->aq.asq_last_status);
4982 goto fail_msix_alloc;
4984 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4985 vsi->info.valid_sections = 0;
4986 vsi->seid = ctxt.seid;
4987 vsi->vsi_id = ctxt.vsi_number;
4988 vsi->sib_vsi_list.vsi = vsi;
4989 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4990 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4991 &vsi->sib_vsi_list, list);
4993 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4994 &vsi->sib_vsi_list, list);
4998 /* MAC/VLAN configuration */
4999 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5000 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5002 ret = i40e_vsi_add_mac(vsi, &filter);
5003 if (ret != I40E_SUCCESS) {
5004 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5005 goto fail_msix_alloc;
5008 /* Get VSI BW information */
5009 i40e_vsi_get_bw_config(vsi);
5012 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5014 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5020 /* Configure vlan filter on or off */
5022 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5025 struct i40e_mac_filter *f;
5027 struct i40e_mac_filter_info *mac_filter;
5028 enum rte_mac_filter_type desired_filter;
5029 int ret = I40E_SUCCESS;
5032 /* Filter to match MAC and VLAN */
5033 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5035 /* Filter to match only MAC */
5036 desired_filter = RTE_MAC_PERFECT_MATCH;
5041 mac_filter = rte_zmalloc("mac_filter_info_data",
5042 num * sizeof(*mac_filter), 0);
5043 if (mac_filter == NULL) {
5044 PMD_DRV_LOG(ERR, "failed to allocate memory");
5045 return I40E_ERR_NO_MEMORY;
5050 /* Remove all existing mac */
5051 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5052 mac_filter[i] = f->mac_info;
5053 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5055 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5056 on ? "enable" : "disable");
5062 /* Override with new filter */
5063 for (i = 0; i < num; i++) {
5064 mac_filter[i].filter_type = desired_filter;
5065 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5067 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5068 on ? "enable" : "disable");
5074 rte_free(mac_filter);
5078 /* Configure vlan stripping on or off */
5080 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5082 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5083 struct i40e_vsi_context ctxt;
5085 int ret = I40E_SUCCESS;
5087 /* Check if it has been already on or off */
5088 if (vsi->info.valid_sections &
5089 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5091 if ((vsi->info.port_vlan_flags &
5092 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5093 return 0; /* already on */
5095 if ((vsi->info.port_vlan_flags &
5096 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5097 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5098 return 0; /* already off */
5103 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5105 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5106 vsi->info.valid_sections =
5107 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5108 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5109 vsi->info.port_vlan_flags |= vlan_flags;
5110 ctxt.seid = vsi->seid;
5111 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5112 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5114 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5115 on ? "enable" : "disable");
5121 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5123 struct rte_eth_dev_data *data = dev->data;
5127 /* Apply vlan offload setting */
5128 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5129 i40e_vlan_offload_set(dev, mask);
5131 /* Apply double-vlan setting, not implemented yet */
5133 /* Apply pvid setting */
5134 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5135 data->dev_conf.txmode.hw_vlan_insert_pvid);
5137 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5143 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5145 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5147 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5151 i40e_update_flow_control(struct i40e_hw *hw)
5153 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5154 struct i40e_link_status link_status;
5155 uint32_t rxfc = 0, txfc = 0, reg;
5159 memset(&link_status, 0, sizeof(link_status));
5160 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5161 if (ret != I40E_SUCCESS) {
5162 PMD_DRV_LOG(ERR, "Failed to get link status information");
5163 goto write_reg; /* Disable flow control */
5166 an_info = hw->phy.link_info.an_info;
5167 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5168 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5169 ret = I40E_ERR_NOT_READY;
5170 goto write_reg; /* Disable flow control */
5173 * If link auto negotiation is enabled, flow control needs to
5174 * be configured according to it
5176 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5177 case I40E_LINK_PAUSE_RXTX:
5180 hw->fc.current_mode = I40E_FC_FULL;
5182 case I40E_AQ_LINK_PAUSE_RX:
5184 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5186 case I40E_AQ_LINK_PAUSE_TX:
5188 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5191 hw->fc.current_mode = I40E_FC_NONE;
5196 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5197 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5198 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5199 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5200 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5201 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5208 i40e_pf_setup(struct i40e_pf *pf)
5210 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5211 struct i40e_filter_control_settings settings;
5212 struct i40e_vsi *vsi;
5215 /* Clear all stats counters */
5216 pf->offset_loaded = FALSE;
5217 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5218 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5219 pf->internal_rx_bytes = 0;
5220 pf->internal_tx_bytes = 0;
5221 pf->internal_rx_bytes_offset = 0;
5222 pf->internal_tx_bytes_offset = 0;
5224 ret = i40e_pf_get_switch_config(pf);
5225 if (ret != I40E_SUCCESS) {
5226 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5229 if (pf->flags & I40E_FLAG_FDIR) {
5230 /* make queue allocated first, let FDIR use queue pair 0*/
5231 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5232 if (ret != I40E_FDIR_QUEUE_ID) {
5234 "queue allocation fails for FDIR: ret =%d",
5236 pf->flags &= ~I40E_FLAG_FDIR;
5239 /* main VSI setup */
5240 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5242 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5243 return I40E_ERR_NOT_READY;
5247 /* Configure filter control */
5248 memset(&settings, 0, sizeof(settings));
5249 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5250 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5251 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5252 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5254 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5255 hw->func_caps.rss_table_size);
5256 return I40E_ERR_PARAM;
5258 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5259 hw->func_caps.rss_table_size);
5260 pf->hash_lut_size = hw->func_caps.rss_table_size;
5262 /* Enable ethtype and macvlan filters */
5263 settings.enable_ethtype = TRUE;
5264 settings.enable_macvlan = TRUE;
5265 ret = i40e_set_filter_control(hw, &settings);
5267 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5270 /* Update flow control according to the auto negotiation */
5271 i40e_update_flow_control(hw);
5273 return I40E_SUCCESS;
5277 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5283 * Set or clear TX Queue Disable flags,
5284 * which is required by hardware.
5286 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5287 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5289 /* Wait until the request is finished */
5290 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5291 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5292 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5293 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5294 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5300 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5301 return I40E_SUCCESS; /* already on, skip next steps */
5303 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5304 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5306 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5307 return I40E_SUCCESS; /* already off, skip next steps */
5308 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5310 /* Write the register */
5311 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5312 /* Check the result */
5313 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5314 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5315 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5317 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5318 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5321 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5322 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5326 /* Check if it is timeout */
5327 if (j >= I40E_CHK_Q_ENA_COUNT) {
5328 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5329 (on ? "enable" : "disable"), q_idx);
5330 return I40E_ERR_TIMEOUT;
5333 return I40E_SUCCESS;
5336 /* Swith on or off the tx queues */
5338 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5340 struct rte_eth_dev_data *dev_data = pf->dev_data;
5341 struct i40e_tx_queue *txq;
5342 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5346 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5347 txq = dev_data->tx_queues[i];
5348 /* Don't operate the queue if not configured or
5349 * if starting only per queue */
5350 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5353 ret = i40e_dev_tx_queue_start(dev, i);
5355 ret = i40e_dev_tx_queue_stop(dev, i);
5356 if ( ret != I40E_SUCCESS)
5360 return I40E_SUCCESS;
5364 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5369 /* Wait until the request is finished */
5370 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5371 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5372 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5373 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5374 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5379 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5380 return I40E_SUCCESS; /* Already on, skip next steps */
5381 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5383 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5384 return I40E_SUCCESS; /* Already off, skip next steps */
5385 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5388 /* Write the register */
5389 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5390 /* Check the result */
5391 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5392 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5393 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5395 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5396 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5399 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5400 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5405 /* Check if it is timeout */
5406 if (j >= I40E_CHK_Q_ENA_COUNT) {
5407 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5408 (on ? "enable" : "disable"), q_idx);
5409 return I40E_ERR_TIMEOUT;
5412 return I40E_SUCCESS;
5414 /* Switch on or off the rx queues */
5416 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5418 struct rte_eth_dev_data *dev_data = pf->dev_data;
5419 struct i40e_rx_queue *rxq;
5420 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5424 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5425 rxq = dev_data->rx_queues[i];
5426 /* Don't operate the queue if not configured or
5427 * if starting only per queue */
5428 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5431 ret = i40e_dev_rx_queue_start(dev, i);
5433 ret = i40e_dev_rx_queue_stop(dev, i);
5434 if (ret != I40E_SUCCESS)
5438 return I40E_SUCCESS;
5441 /* Switch on or off all the rx/tx queues */
5443 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5448 /* enable rx queues before enabling tx queues */
5449 ret = i40e_dev_switch_rx_queues(pf, on);
5451 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5454 ret = i40e_dev_switch_tx_queues(pf, on);
5456 /* Stop tx queues before stopping rx queues */
5457 ret = i40e_dev_switch_tx_queues(pf, on);
5459 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5462 ret = i40e_dev_switch_rx_queues(pf, on);
5468 /* Initialize VSI for TX */
5470 i40e_dev_tx_init(struct i40e_pf *pf)
5472 struct rte_eth_dev_data *data = pf->dev_data;
5474 uint32_t ret = I40E_SUCCESS;
5475 struct i40e_tx_queue *txq;
5477 for (i = 0; i < data->nb_tx_queues; i++) {
5478 txq = data->tx_queues[i];
5479 if (!txq || !txq->q_set)
5481 ret = i40e_tx_queue_init(txq);
5482 if (ret != I40E_SUCCESS)
5485 if (ret == I40E_SUCCESS)
5486 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5492 /* Initialize VSI for RX */
5494 i40e_dev_rx_init(struct i40e_pf *pf)
5496 struct rte_eth_dev_data *data = pf->dev_data;
5497 int ret = I40E_SUCCESS;
5499 struct i40e_rx_queue *rxq;
5501 i40e_pf_config_mq_rx(pf);
5502 for (i = 0; i < data->nb_rx_queues; i++) {
5503 rxq = data->rx_queues[i];
5504 if (!rxq || !rxq->q_set)
5507 ret = i40e_rx_queue_init(rxq);
5508 if (ret != I40E_SUCCESS) {
5510 "Failed to do RX queue initialization");
5514 if (ret == I40E_SUCCESS)
5515 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5522 i40e_dev_rxtx_init(struct i40e_pf *pf)
5526 err = i40e_dev_tx_init(pf);
5528 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5531 err = i40e_dev_rx_init(pf);
5533 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5541 i40e_vmdq_setup(struct rte_eth_dev *dev)
5543 struct rte_eth_conf *conf = &dev->data->dev_conf;
5544 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5545 int i, err, conf_vsis, j, loop;
5546 struct i40e_vsi *vsi;
5547 struct i40e_vmdq_info *vmdq_info;
5548 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5549 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5552 * Disable interrupt to avoid message from VF. Furthermore, it will
5553 * avoid race condition in VSI creation/destroy.
5555 i40e_pf_disable_irq0(hw);
5557 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5558 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5562 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5563 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5564 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5565 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5566 pf->max_nb_vmdq_vsi);
5570 if (pf->vmdq != NULL) {
5571 PMD_INIT_LOG(INFO, "VMDQ already configured");
5575 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5576 sizeof(*vmdq_info) * conf_vsis, 0);
5578 if (pf->vmdq == NULL) {
5579 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5583 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5585 /* Create VMDQ VSI */
5586 for (i = 0; i < conf_vsis; i++) {
5587 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5588 vmdq_conf->enable_loop_back);
5590 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5594 vmdq_info = &pf->vmdq[i];
5596 vmdq_info->vsi = vsi;
5598 pf->nb_cfg_vmdq_vsi = conf_vsis;
5600 /* Configure Vlan */
5601 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5602 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5603 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5604 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5605 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5606 vmdq_conf->pool_map[i].vlan_id, j);
5608 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5609 vmdq_conf->pool_map[i].vlan_id);
5611 PMD_INIT_LOG(ERR, "Failed to add vlan");
5619 i40e_pf_enable_irq0(hw);
5624 for (i = 0; i < conf_vsis; i++)
5625 if (pf->vmdq[i].vsi == NULL)
5628 i40e_vsi_release(pf->vmdq[i].vsi);
5632 i40e_pf_enable_irq0(hw);
5637 i40e_stat_update_32(struct i40e_hw *hw,
5645 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5649 if (new_data >= *offset)
5650 *stat = (uint64_t)(new_data - *offset);
5652 *stat = (uint64_t)((new_data +
5653 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5657 i40e_stat_update_48(struct i40e_hw *hw,
5666 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5667 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5668 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5673 if (new_data >= *offset)
5674 *stat = new_data - *offset;
5676 *stat = (uint64_t)((new_data +
5677 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5679 *stat &= I40E_48_BIT_MASK;
5684 i40e_pf_disable_irq0(struct i40e_hw *hw)
5686 /* Disable all interrupt types */
5687 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5688 I40E_WRITE_FLUSH(hw);
5693 i40e_pf_enable_irq0(struct i40e_hw *hw)
5695 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5696 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5697 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5698 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5699 I40E_WRITE_FLUSH(hw);
5703 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5705 /* read pending request and disable first */
5706 i40e_pf_disable_irq0(hw);
5707 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5708 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5709 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5712 /* Link no queues with irq0 */
5713 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5714 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5718 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5720 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5721 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5724 uint32_t index, offset, val;
5729 * Try to find which VF trigger a reset, use absolute VF id to access
5730 * since the reg is global register.
5732 for (i = 0; i < pf->vf_num; i++) {
5733 abs_vf_id = hw->func_caps.vf_base_id + i;
5734 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5735 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5736 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5737 /* VFR event occurred */
5738 if (val & (0x1 << offset)) {
5741 /* Clear the event first */
5742 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5744 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5746 * Only notify a VF reset event occurred,
5747 * don't trigger another SW reset
5749 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5750 if (ret != I40E_SUCCESS)
5751 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5757 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5759 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5762 for (i = 0; i < pf->vf_num; i++)
5763 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5767 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5769 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5770 struct i40e_arq_event_info info;
5771 uint16_t pending, opcode;
5774 info.buf_len = I40E_AQ_BUF_SZ;
5775 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5776 if (!info.msg_buf) {
5777 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5783 ret = i40e_clean_arq_element(hw, &info, &pending);
5785 if (ret != I40E_SUCCESS) {
5787 "Failed to read msg from AdminQ, aq_err: %u",
5788 hw->aq.asq_last_status);
5791 opcode = rte_le_to_cpu_16(info.desc.opcode);
5794 case i40e_aqc_opc_send_msg_to_pf:
5795 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5796 i40e_pf_host_handle_vf_msg(dev,
5797 rte_le_to_cpu_16(info.desc.retval),
5798 rte_le_to_cpu_32(info.desc.cookie_high),
5799 rte_le_to_cpu_32(info.desc.cookie_low),
5803 case i40e_aqc_opc_get_link_status:
5804 ret = i40e_dev_link_update(dev, 0);
5806 _rte_eth_dev_callback_process(dev,
5807 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5810 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5815 rte_free(info.msg_buf);
5819 * Interrupt handler triggered by NIC for handling
5820 * specific interrupt.
5823 * Pointer to interrupt handle.
5825 * The address of parameter (struct rte_eth_dev *) regsitered before.
5831 i40e_dev_interrupt_handler(void *param)
5833 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5834 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5837 /* Disable interrupt */
5838 i40e_pf_disable_irq0(hw);
5840 /* read out interrupt causes */
5841 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5843 /* No interrupt event indicated */
5844 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5845 PMD_DRV_LOG(INFO, "No interrupt event");
5848 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5849 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5850 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5851 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5852 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5853 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5854 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5855 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5856 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5857 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5858 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5859 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5860 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5861 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5863 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5864 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5865 i40e_dev_handle_vfr_event(dev);
5867 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5868 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5869 i40e_dev_handle_aq_msg(dev);
5873 /* Enable interrupt */
5874 i40e_pf_enable_irq0(hw);
5875 rte_intr_enable(dev->intr_handle);
5879 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5880 struct i40e_macvlan_filter *filter,
5883 int ele_num, ele_buff_size;
5884 int num, actual_num, i;
5886 int ret = I40E_SUCCESS;
5887 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5888 struct i40e_aqc_add_macvlan_element_data *req_list;
5890 if (filter == NULL || total == 0)
5891 return I40E_ERR_PARAM;
5892 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5893 ele_buff_size = hw->aq.asq_buf_size;
5895 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5896 if (req_list == NULL) {
5897 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5898 return I40E_ERR_NO_MEMORY;
5903 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5904 memset(req_list, 0, ele_buff_size);
5906 for (i = 0; i < actual_num; i++) {
5907 (void)rte_memcpy(req_list[i].mac_addr,
5908 &filter[num + i].macaddr, ETH_ADDR_LEN);
5909 req_list[i].vlan_tag =
5910 rte_cpu_to_le_16(filter[num + i].vlan_id);
5912 switch (filter[num + i].filter_type) {
5913 case RTE_MAC_PERFECT_MATCH:
5914 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5915 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5917 case RTE_MACVLAN_PERFECT_MATCH:
5918 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5920 case RTE_MAC_HASH_MATCH:
5921 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5922 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5924 case RTE_MACVLAN_HASH_MATCH:
5925 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5928 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5929 ret = I40E_ERR_PARAM;
5933 req_list[i].queue_number = 0;
5935 req_list[i].flags = rte_cpu_to_le_16(flags);
5938 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5940 if (ret != I40E_SUCCESS) {
5941 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5945 } while (num < total);
5953 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5954 struct i40e_macvlan_filter *filter,
5957 int ele_num, ele_buff_size;
5958 int num, actual_num, i;
5960 int ret = I40E_SUCCESS;
5961 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5962 struct i40e_aqc_remove_macvlan_element_data *req_list;
5964 if (filter == NULL || total == 0)
5965 return I40E_ERR_PARAM;
5967 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5968 ele_buff_size = hw->aq.asq_buf_size;
5970 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5971 if (req_list == NULL) {
5972 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5973 return I40E_ERR_NO_MEMORY;
5978 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5979 memset(req_list, 0, ele_buff_size);
5981 for (i = 0; i < actual_num; i++) {
5982 (void)rte_memcpy(req_list[i].mac_addr,
5983 &filter[num + i].macaddr, ETH_ADDR_LEN);
5984 req_list[i].vlan_tag =
5985 rte_cpu_to_le_16(filter[num + i].vlan_id);
5987 switch (filter[num + i].filter_type) {
5988 case RTE_MAC_PERFECT_MATCH:
5989 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5990 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5992 case RTE_MACVLAN_PERFECT_MATCH:
5993 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5995 case RTE_MAC_HASH_MATCH:
5996 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5997 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5999 case RTE_MACVLAN_HASH_MATCH:
6000 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6003 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6004 ret = I40E_ERR_PARAM;
6007 req_list[i].flags = rte_cpu_to_le_16(flags);
6010 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6012 if (ret != I40E_SUCCESS) {
6013 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6017 } while (num < total);
6024 /* Find out specific MAC filter */
6025 static struct i40e_mac_filter *
6026 i40e_find_mac_filter(struct i40e_vsi *vsi,
6027 struct ether_addr *macaddr)
6029 struct i40e_mac_filter *f;
6031 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6032 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6040 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6043 uint32_t vid_idx, vid_bit;
6045 if (vlan_id > ETH_VLAN_ID_MAX)
6048 vid_idx = I40E_VFTA_IDX(vlan_id);
6049 vid_bit = I40E_VFTA_BIT(vlan_id);
6051 if (vsi->vfta[vid_idx] & vid_bit)
6058 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6059 uint16_t vlan_id, bool on)
6061 uint32_t vid_idx, vid_bit;
6063 vid_idx = I40E_VFTA_IDX(vlan_id);
6064 vid_bit = I40E_VFTA_BIT(vlan_id);
6067 vsi->vfta[vid_idx] |= vid_bit;
6069 vsi->vfta[vid_idx] &= ~vid_bit;
6073 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6074 uint16_t vlan_id, bool on)
6076 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6077 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6080 if (vlan_id > ETH_VLAN_ID_MAX)
6083 i40e_store_vlan_filter(vsi, vlan_id, on);
6085 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6088 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6091 ret = i40e_aq_add_vlan(hw, vsi->seid,
6092 &vlan_data, 1, NULL);
6093 if (ret != I40E_SUCCESS)
6094 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6096 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6097 &vlan_data, 1, NULL);
6098 if (ret != I40E_SUCCESS)
6100 "Failed to remove vlan filter");
6105 * Find all vlan options for specific mac addr,
6106 * return with actual vlan found.
6109 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6110 struct i40e_macvlan_filter *mv_f,
6111 int num, struct ether_addr *addr)
6117 * Not to use i40e_find_vlan_filter to decrease the loop time,
6118 * although the code looks complex.
6120 if (num < vsi->vlan_num)
6121 return I40E_ERR_PARAM;
6124 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6126 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6127 if (vsi->vfta[j] & (1 << k)) {
6130 "vlan number doesn't match");
6131 return I40E_ERR_PARAM;
6133 (void)rte_memcpy(&mv_f[i].macaddr,
6134 addr, ETH_ADDR_LEN);
6136 j * I40E_UINT32_BIT_SIZE + k;
6142 return I40E_SUCCESS;
6146 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6147 struct i40e_macvlan_filter *mv_f,
6152 struct i40e_mac_filter *f;
6154 if (num < vsi->mac_num)
6155 return I40E_ERR_PARAM;
6157 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6159 PMD_DRV_LOG(ERR, "buffer number not match");
6160 return I40E_ERR_PARAM;
6162 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6164 mv_f[i].vlan_id = vlan;
6165 mv_f[i].filter_type = f->mac_info.filter_type;
6169 return I40E_SUCCESS;
6173 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6176 struct i40e_mac_filter *f;
6177 struct i40e_macvlan_filter *mv_f;
6178 int ret = I40E_SUCCESS;
6180 if (vsi == NULL || vsi->mac_num == 0)
6181 return I40E_ERR_PARAM;
6183 /* Case that no vlan is set */
6184 if (vsi->vlan_num == 0)
6187 num = vsi->mac_num * vsi->vlan_num;
6189 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6191 PMD_DRV_LOG(ERR, "failed to allocate memory");
6192 return I40E_ERR_NO_MEMORY;
6196 if (vsi->vlan_num == 0) {
6197 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6198 (void)rte_memcpy(&mv_f[i].macaddr,
6199 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6200 mv_f[i].filter_type = f->mac_info.filter_type;
6201 mv_f[i].vlan_id = 0;
6205 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6206 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6207 vsi->vlan_num, &f->mac_info.mac_addr);
6208 if (ret != I40E_SUCCESS)
6210 for (j = i; j < i + vsi->vlan_num; j++)
6211 mv_f[j].filter_type = f->mac_info.filter_type;
6216 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6224 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6226 struct i40e_macvlan_filter *mv_f;
6228 int ret = I40E_SUCCESS;
6230 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6231 return I40E_ERR_PARAM;
6233 /* If it's already set, just return */
6234 if (i40e_find_vlan_filter(vsi,vlan))
6235 return I40E_SUCCESS;
6237 mac_num = vsi->mac_num;
6240 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6241 return I40E_ERR_PARAM;
6244 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6247 PMD_DRV_LOG(ERR, "failed to allocate memory");
6248 return I40E_ERR_NO_MEMORY;
6251 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6253 if (ret != I40E_SUCCESS)
6256 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6258 if (ret != I40E_SUCCESS)
6261 i40e_set_vlan_filter(vsi, vlan, 1);
6271 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6273 struct i40e_macvlan_filter *mv_f;
6275 int ret = I40E_SUCCESS;
6278 * Vlan 0 is the generic filter for untagged packets
6279 * and can't be removed.
6281 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6282 return I40E_ERR_PARAM;
6284 /* If can't find it, just return */
6285 if (!i40e_find_vlan_filter(vsi, vlan))
6286 return I40E_ERR_PARAM;
6288 mac_num = vsi->mac_num;
6291 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6292 return I40E_ERR_PARAM;
6295 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6298 PMD_DRV_LOG(ERR, "failed to allocate memory");
6299 return I40E_ERR_NO_MEMORY;
6302 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6304 if (ret != I40E_SUCCESS)
6307 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6309 if (ret != I40E_SUCCESS)
6312 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6313 if (vsi->vlan_num == 1) {
6314 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6315 if (ret != I40E_SUCCESS)
6318 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6319 if (ret != I40E_SUCCESS)
6323 i40e_set_vlan_filter(vsi, vlan, 0);
6333 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6335 struct i40e_mac_filter *f;
6336 struct i40e_macvlan_filter *mv_f;
6337 int i, vlan_num = 0;
6338 int ret = I40E_SUCCESS;
6340 /* If it's add and we've config it, return */
6341 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6343 return I40E_SUCCESS;
6344 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6345 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6348 * If vlan_num is 0, that's the first time to add mac,
6349 * set mask for vlan_id 0.
6351 if (vsi->vlan_num == 0) {
6352 i40e_set_vlan_filter(vsi, 0, 1);
6355 vlan_num = vsi->vlan_num;
6356 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6357 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6360 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6362 PMD_DRV_LOG(ERR, "failed to allocate memory");
6363 return I40E_ERR_NO_MEMORY;
6366 for (i = 0; i < vlan_num; i++) {
6367 mv_f[i].filter_type = mac_filter->filter_type;
6368 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6372 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6373 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6374 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6375 &mac_filter->mac_addr);
6376 if (ret != I40E_SUCCESS)
6380 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6381 if (ret != I40E_SUCCESS)
6384 /* Add the mac addr into mac list */
6385 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6387 PMD_DRV_LOG(ERR, "failed to allocate memory");
6388 ret = I40E_ERR_NO_MEMORY;
6391 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6393 f->mac_info.filter_type = mac_filter->filter_type;
6394 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6405 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6407 struct i40e_mac_filter *f;
6408 struct i40e_macvlan_filter *mv_f;
6410 enum rte_mac_filter_type filter_type;
6411 int ret = I40E_SUCCESS;
6413 /* Can't find it, return an error */
6414 f = i40e_find_mac_filter(vsi, addr);
6416 return I40E_ERR_PARAM;
6418 vlan_num = vsi->vlan_num;
6419 filter_type = f->mac_info.filter_type;
6420 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6421 filter_type == RTE_MACVLAN_HASH_MATCH) {
6422 if (vlan_num == 0) {
6423 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6424 return I40E_ERR_PARAM;
6426 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6427 filter_type == RTE_MAC_HASH_MATCH)
6430 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6432 PMD_DRV_LOG(ERR, "failed to allocate memory");
6433 return I40E_ERR_NO_MEMORY;
6436 for (i = 0; i < vlan_num; i++) {
6437 mv_f[i].filter_type = filter_type;
6438 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6441 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6442 filter_type == RTE_MACVLAN_HASH_MATCH) {
6443 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6444 if (ret != I40E_SUCCESS)
6448 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6449 if (ret != I40E_SUCCESS)
6452 /* Remove the mac addr into mac list */
6453 TAILQ_REMOVE(&vsi->mac_list, f, next);
6463 /* Configure hash enable flags for RSS */
6465 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6472 if (flags & ETH_RSS_FRAG_IPV4)
6473 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6474 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6475 if (type == I40E_MAC_X722) {
6476 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6477 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6479 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6481 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6482 if (type == I40E_MAC_X722) {
6483 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6484 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6485 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6487 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6489 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6490 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6491 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6492 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6493 if (flags & ETH_RSS_FRAG_IPV6)
6494 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6495 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6496 if (type == I40E_MAC_X722) {
6497 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6498 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6500 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6502 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6503 if (type == I40E_MAC_X722) {
6504 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6505 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6506 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6508 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6510 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6511 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6512 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6513 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6514 if (flags & ETH_RSS_L2_PAYLOAD)
6515 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6520 /* Parse the hash enable flags */
6522 i40e_parse_hena(uint64_t flags)
6524 uint64_t rss_hf = 0;
6528 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6529 rss_hf |= ETH_RSS_FRAG_IPV4;
6530 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6531 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6532 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6533 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6534 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6535 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6536 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6537 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6538 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6539 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6540 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6541 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6542 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6543 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6544 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6545 rss_hf |= ETH_RSS_FRAG_IPV6;
6546 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6547 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6548 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6549 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6550 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6551 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6552 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6553 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6554 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6555 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6556 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6557 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6558 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6559 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6560 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6561 rss_hf |= ETH_RSS_L2_PAYLOAD;
6568 i40e_pf_disable_rss(struct i40e_pf *pf)
6570 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6573 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6574 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6575 if (hw->mac.type == I40E_MAC_X722)
6576 hena &= ~I40E_RSS_HENA_ALL_X722;
6578 hena &= ~I40E_RSS_HENA_ALL;
6579 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6580 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6581 I40E_WRITE_FLUSH(hw);
6585 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6587 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6588 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6591 if (!key || key_len == 0) {
6592 PMD_DRV_LOG(DEBUG, "No key to be configured");
6594 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6596 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6600 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6601 struct i40e_aqc_get_set_rss_key_data *key_dw =
6602 (struct i40e_aqc_get_set_rss_key_data *)key;
6604 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6606 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6608 uint32_t *hash_key = (uint32_t *)key;
6611 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6612 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6613 I40E_WRITE_FLUSH(hw);
6620 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6622 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6623 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6626 if (!key || !key_len)
6629 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6630 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6631 (struct i40e_aqc_get_set_rss_key_data *)key);
6633 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6637 uint32_t *key_dw = (uint32_t *)key;
6640 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6641 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6643 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6649 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6651 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6656 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6657 rss_conf->rss_key_len);
6661 rss_hf = rss_conf->rss_hf;
6662 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6663 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6664 if (hw->mac.type == I40E_MAC_X722)
6665 hena &= ~I40E_RSS_HENA_ALL_X722;
6667 hena &= ~I40E_RSS_HENA_ALL;
6668 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6669 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6670 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6671 I40E_WRITE_FLUSH(hw);
6677 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6678 struct rte_eth_rss_conf *rss_conf)
6680 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6681 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6682 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6685 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6686 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6687 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6688 ? I40E_RSS_HENA_ALL_X722
6689 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6690 if (rss_hf != 0) /* Enable RSS */
6692 return 0; /* Nothing to do */
6695 if (rss_hf == 0) /* Disable RSS */
6698 return i40e_hw_rss_hash_set(pf, rss_conf);
6702 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6703 struct rte_eth_rss_conf *rss_conf)
6705 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6706 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6709 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6710 &rss_conf->rss_key_len);
6712 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6713 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6714 rss_conf->rss_hf = i40e_parse_hena(hena);
6720 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6722 switch (filter_type) {
6723 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6724 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6726 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6727 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6729 case RTE_TUNNEL_FILTER_IMAC_TENID:
6730 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6732 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6733 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6735 case ETH_TUNNEL_FILTER_IMAC:
6736 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6738 case ETH_TUNNEL_FILTER_OIP:
6739 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6741 case ETH_TUNNEL_FILTER_IIP:
6742 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6745 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6752 /* Convert tunnel filter structure */
6754 i40e_tunnel_filter_convert(
6755 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6756 struct i40e_tunnel_filter *tunnel_filter)
6758 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6759 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6760 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6761 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6762 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6763 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6764 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6765 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6766 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6768 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6769 tunnel_filter->input.flags = cld_filter->element.flags;
6770 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6771 tunnel_filter->queue = cld_filter->element.queue_number;
6772 rte_memcpy(tunnel_filter->input.general_fields,
6773 cld_filter->general_fields,
6774 sizeof(cld_filter->general_fields));
6779 /* Check if there exists the tunnel filter */
6780 struct i40e_tunnel_filter *
6781 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6782 const struct i40e_tunnel_filter_input *input)
6786 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6790 return tunnel_rule->hash_map[ret];
6793 /* Add a tunnel filter into the SW list */
6795 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6796 struct i40e_tunnel_filter *tunnel_filter)
6798 struct i40e_tunnel_rule *rule = &pf->tunnel;
6801 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6804 "Failed to insert tunnel filter to hash table %d!",
6808 rule->hash_map[ret] = tunnel_filter;
6810 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6815 /* Delete a tunnel filter from the SW list */
6817 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6818 struct i40e_tunnel_filter_input *input)
6820 struct i40e_tunnel_rule *rule = &pf->tunnel;
6821 struct i40e_tunnel_filter *tunnel_filter;
6824 ret = rte_hash_del_key(rule->hash_table, input);
6827 "Failed to delete tunnel filter to hash table %d!",
6831 tunnel_filter = rule->hash_map[ret];
6832 rule->hash_map[ret] = NULL;
6834 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6835 rte_free(tunnel_filter);
6841 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6842 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6847 uint8_t i, tun_type = 0;
6848 /* internal varialbe to convert ipv6 byte order */
6849 uint32_t convert_ipv6[4];
6851 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6852 struct i40e_vsi *vsi = pf->main_vsi;
6853 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6854 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6855 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6856 struct i40e_tunnel_filter *tunnel, *node;
6857 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6859 cld_filter = rte_zmalloc("tunnel_filter",
6860 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6863 if (NULL == cld_filter) {
6864 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6867 pfilter = cld_filter;
6869 ether_addr_copy(&tunnel_filter->outer_mac,
6870 (struct ether_addr *)&pfilter->element.outer_mac);
6871 ether_addr_copy(&tunnel_filter->inner_mac,
6872 (struct ether_addr *)&pfilter->element.inner_mac);
6874 pfilter->element.inner_vlan =
6875 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6876 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6877 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6878 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6879 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6880 &rte_cpu_to_le_32(ipv4_addr),
6881 sizeof(pfilter->element.ipaddr.v4.data));
6883 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6884 for (i = 0; i < 4; i++) {
6886 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6888 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6890 sizeof(pfilter->element.ipaddr.v6.data));
6893 /* check tunneled type */
6894 switch (tunnel_filter->tunnel_type) {
6895 case RTE_TUNNEL_TYPE_VXLAN:
6896 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6898 case RTE_TUNNEL_TYPE_NVGRE:
6899 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6901 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6902 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6905 /* Other tunnel types is not supported. */
6906 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6907 rte_free(cld_filter);
6911 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6912 &pfilter->element.flags);
6914 rte_free(cld_filter);
6918 pfilter->element.flags |= rte_cpu_to_le_16(
6919 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6920 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6921 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6922 pfilter->element.queue_number =
6923 rte_cpu_to_le_16(tunnel_filter->queue_id);
6925 /* Check if there is the filter in SW list */
6926 memset(&check_filter, 0, sizeof(check_filter));
6927 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6928 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6930 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6934 if (!add && !node) {
6935 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6940 ret = i40e_aq_add_cloud_filters(hw,
6941 vsi->seid, &cld_filter->element, 1);
6943 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6946 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6947 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6948 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6950 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6951 &cld_filter->element, 1);
6953 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6956 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6959 rte_free(cld_filter);
6963 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6964 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
6965 #define I40E_TR_GENEVE_KEY_MASK 0x8
6966 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
6967 #define I40E_TR_GRE_KEY_MASK 0x400
6968 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
6969 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
6972 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6974 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
6975 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
6976 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6977 enum i40e_status_code status = I40E_SUCCESS;
6979 memset(&filter_replace, 0,
6980 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6981 memset(&filter_replace_buf, 0,
6982 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6984 /* create L1 filter */
6985 filter_replace.old_filter_type =
6986 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6987 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6988 filter_replace.tr_bit = 0;
6990 /* Prepare the buffer, 3 entries */
6991 filter_replace_buf.data[0] =
6992 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6993 filter_replace_buf.data[0] |=
6994 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6995 filter_replace_buf.data[2] = 0xFF;
6996 filter_replace_buf.data[3] = 0xFF;
6997 filter_replace_buf.data[4] =
6998 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6999 filter_replace_buf.data[4] |=
7000 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7001 filter_replace_buf.data[7] = 0xF0;
7002 filter_replace_buf.data[8]
7003 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7004 filter_replace_buf.data[8] |=
7005 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7006 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7007 I40E_TR_GENEVE_KEY_MASK |
7008 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7009 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7010 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7011 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7013 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7014 &filter_replace_buf);
7019 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7021 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7022 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7023 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7024 enum i40e_status_code status = I40E_SUCCESS;
7027 memset(&filter_replace, 0,
7028 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7029 memset(&filter_replace_buf, 0,
7030 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7031 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7032 I40E_AQC_MIRROR_CLOUD_FILTER;
7033 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7034 filter_replace.new_filter_type =
7035 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7036 /* Prepare the buffer, 2 entries */
7037 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7038 filter_replace_buf.data[0] |=
7039 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7040 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7041 filter_replace_buf.data[4] |=
7042 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7043 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7044 &filter_replace_buf);
7049 memset(&filter_replace, 0,
7050 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7051 memset(&filter_replace_buf, 0,
7052 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7054 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7055 I40E_AQC_MIRROR_CLOUD_FILTER;
7056 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7057 filter_replace.new_filter_type =
7058 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7059 /* Prepare the buffer, 2 entries */
7060 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7061 filter_replace_buf.data[0] |=
7062 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7063 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7064 filter_replace_buf.data[4] |=
7065 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7067 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7068 &filter_replace_buf);
7073 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7074 struct i40e_tunnel_filter_conf *tunnel_filter,
7079 uint8_t i, tun_type = 0;
7080 /* internal variable to convert ipv6 byte order */
7081 uint32_t convert_ipv6[4];
7083 struct i40e_pf_vf *vf = NULL;
7084 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7085 struct i40e_vsi *vsi;
7086 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7087 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7088 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7089 struct i40e_tunnel_filter *tunnel, *node;
7090 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7092 bool big_buffer = 0;
7094 cld_filter = rte_zmalloc("tunnel_filter",
7095 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7098 if (cld_filter == NULL) {
7099 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7102 pfilter = cld_filter;
7104 ether_addr_copy(&tunnel_filter->outer_mac,
7105 (struct ether_addr *)&pfilter->element.outer_mac);
7106 ether_addr_copy(&tunnel_filter->inner_mac,
7107 (struct ether_addr *)&pfilter->element.inner_mac);
7109 pfilter->element.inner_vlan =
7110 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7111 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7112 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7113 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7114 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7115 &rte_cpu_to_le_32(ipv4_addr),
7116 sizeof(pfilter->element.ipaddr.v4.data));
7118 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7119 for (i = 0; i < 4; i++) {
7121 rte_cpu_to_le_32(rte_be_to_cpu_32(
7122 tunnel_filter->ip_addr.ipv6_addr[i]));
7124 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7126 sizeof(pfilter->element.ipaddr.v6.data));
7129 /* check tunneled type */
7130 switch (tunnel_filter->tunnel_type) {
7131 case I40E_TUNNEL_TYPE_VXLAN:
7132 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7134 case I40E_TUNNEL_TYPE_NVGRE:
7135 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7137 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7138 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7140 case I40E_TUNNEL_TYPE_MPLSoUDP:
7141 if (!pf->mpls_replace_flag) {
7142 i40e_replace_mpls_l1_filter(pf);
7143 i40e_replace_mpls_cloud_filter(pf);
7144 pf->mpls_replace_flag = 1;
7146 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7147 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7149 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7150 (teid_le & 0xF) << 12;
7151 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7154 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7156 case I40E_TUNNEL_TYPE_MPLSoGRE:
7157 if (!pf->mpls_replace_flag) {
7158 i40e_replace_mpls_l1_filter(pf);
7159 i40e_replace_mpls_cloud_filter(pf);
7160 pf->mpls_replace_flag = 1;
7162 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7163 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7165 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7166 (teid_le & 0xF) << 12;
7167 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7170 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7172 case I40E_TUNNEL_TYPE_QINQ:
7173 if (!pf->qinq_replace_flag) {
7174 ret = i40e_cloud_filter_qinq_create(pf);
7177 "QinQ tunnel filter already created.");
7178 pf->qinq_replace_flag = 1;
7180 /* Add in the General fields the values of
7181 * the Outer and Inner VLAN
7182 * Big Buffer should be set, see changes in
7183 * i40e_aq_add_cloud_filters
7185 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7186 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7190 /* Other tunnel types is not supported. */
7191 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7192 rte_free(cld_filter);
7196 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7197 pfilter->element.flags =
7198 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7199 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7200 pfilter->element.flags =
7201 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7202 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7203 pfilter->element.flags |=
7204 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7206 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7207 &pfilter->element.flags);
7209 rte_free(cld_filter);
7214 pfilter->element.flags |= rte_cpu_to_le_16(
7215 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7216 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7217 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7218 pfilter->element.queue_number =
7219 rte_cpu_to_le_16(tunnel_filter->queue_id);
7221 if (!tunnel_filter->is_to_vf)
7224 if (tunnel_filter->vf_id >= pf->vf_num) {
7225 PMD_DRV_LOG(ERR, "Invalid argument.");
7228 vf = &pf->vfs[tunnel_filter->vf_id];
7232 /* Check if there is the filter in SW list */
7233 memset(&check_filter, 0, sizeof(check_filter));
7234 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7235 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7236 check_filter.vf_id = tunnel_filter->vf_id;
7237 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7239 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7243 if (!add && !node) {
7244 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7250 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7251 vsi->seid, cld_filter, 1);
7253 ret = i40e_aq_add_cloud_filters(hw,
7254 vsi->seid, &cld_filter->element, 1);
7256 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7259 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7260 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7261 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7264 ret = i40e_aq_remove_cloud_filters_big_buffer(
7265 hw, vsi->seid, cld_filter, 1);
7267 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7268 &cld_filter->element, 1);
7270 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7273 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7276 rte_free(cld_filter);
7281 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7285 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7286 if (pf->vxlan_ports[i] == port)
7294 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7298 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7300 idx = i40e_get_vxlan_port_idx(pf, port);
7302 /* Check if port already exists */
7304 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7308 /* Now check if there is space to add the new port */
7309 idx = i40e_get_vxlan_port_idx(pf, 0);
7312 "Maximum number of UDP ports reached, not adding port %d",
7317 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7320 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7324 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7327 /* New port: add it and mark its index in the bitmap */
7328 pf->vxlan_ports[idx] = port;
7329 pf->vxlan_bitmap |= (1 << idx);
7331 if (!(pf->flags & I40E_FLAG_VXLAN))
7332 pf->flags |= I40E_FLAG_VXLAN;
7338 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7341 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7343 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7344 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7348 idx = i40e_get_vxlan_port_idx(pf, port);
7351 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7355 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7356 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7360 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7363 pf->vxlan_ports[idx] = 0;
7364 pf->vxlan_bitmap &= ~(1 << idx);
7366 if (!pf->vxlan_bitmap)
7367 pf->flags &= ~I40E_FLAG_VXLAN;
7372 /* Add UDP tunneling port */
7374 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7375 struct rte_eth_udp_tunnel *udp_tunnel)
7378 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7380 if (udp_tunnel == NULL)
7383 switch (udp_tunnel->prot_type) {
7384 case RTE_TUNNEL_TYPE_VXLAN:
7385 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7388 case RTE_TUNNEL_TYPE_GENEVE:
7389 case RTE_TUNNEL_TYPE_TEREDO:
7390 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7395 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7403 /* Remove UDP tunneling port */
7405 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7406 struct rte_eth_udp_tunnel *udp_tunnel)
7409 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7411 if (udp_tunnel == NULL)
7414 switch (udp_tunnel->prot_type) {
7415 case RTE_TUNNEL_TYPE_VXLAN:
7416 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7418 case RTE_TUNNEL_TYPE_GENEVE:
7419 case RTE_TUNNEL_TYPE_TEREDO:
7420 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7424 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7432 /* Calculate the maximum number of contiguous PF queues that are configured */
7434 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7436 struct rte_eth_dev_data *data = pf->dev_data;
7438 struct i40e_rx_queue *rxq;
7441 for (i = 0; i < pf->lan_nb_qps; i++) {
7442 rxq = data->rx_queues[i];
7443 if (rxq && rxq->q_set)
7454 i40e_pf_config_rss(struct i40e_pf *pf)
7456 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7457 struct rte_eth_rss_conf rss_conf;
7458 uint32_t i, lut = 0;
7462 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7463 * It's necessary to calculate the actual PF queues that are configured.
7465 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7466 num = i40e_pf_calc_configured_queues_num(pf);
7468 num = pf->dev_data->nb_rx_queues;
7470 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7471 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7475 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7479 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7482 lut = (lut << 8) | (j & ((0x1 <<
7483 hw->func_caps.rss_table_entry_width) - 1));
7485 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7488 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7489 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7490 i40e_pf_disable_rss(pf);
7493 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7494 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7495 /* Random default keys */
7496 static uint32_t rss_key_default[] = {0x6b793944,
7497 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7498 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7499 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7501 rss_conf.rss_key = (uint8_t *)rss_key_default;
7502 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7506 return i40e_hw_rss_hash_set(pf, &rss_conf);
7510 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7511 struct rte_eth_tunnel_filter_conf *filter)
7513 if (pf == NULL || filter == NULL) {
7514 PMD_DRV_LOG(ERR, "Invalid parameter");
7518 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7519 PMD_DRV_LOG(ERR, "Invalid queue ID");
7523 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7524 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7528 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7529 (is_zero_ether_addr(&filter->outer_mac))) {
7530 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7534 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7535 (is_zero_ether_addr(&filter->inner_mac))) {
7536 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7543 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7544 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7546 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7551 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7552 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7555 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7556 } else if (len == 4) {
7557 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7559 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7564 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7571 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7572 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7578 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7585 switch (cfg->cfg_type) {
7586 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7587 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7590 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7598 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7599 enum rte_filter_op filter_op,
7602 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7603 int ret = I40E_ERR_PARAM;
7605 switch (filter_op) {
7606 case RTE_ETH_FILTER_SET:
7607 ret = i40e_dev_global_config_set(hw,
7608 (struct rte_eth_global_cfg *)arg);
7611 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7619 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7620 enum rte_filter_op filter_op,
7623 struct rte_eth_tunnel_filter_conf *filter;
7624 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7625 int ret = I40E_SUCCESS;
7627 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7629 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7630 return I40E_ERR_PARAM;
7632 switch (filter_op) {
7633 case RTE_ETH_FILTER_NOP:
7634 if (!(pf->flags & I40E_FLAG_VXLAN))
7635 ret = I40E_NOT_SUPPORTED;
7637 case RTE_ETH_FILTER_ADD:
7638 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7640 case RTE_ETH_FILTER_DELETE:
7641 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7644 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7645 ret = I40E_ERR_PARAM;
7653 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7656 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7659 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7660 ret = i40e_pf_config_rss(pf);
7662 i40e_pf_disable_rss(pf);
7667 /* Get the symmetric hash enable configurations per port */
7669 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7671 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7673 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7676 /* Set the symmetric hash enable configurations per port */
7678 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7680 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7683 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7685 "Symmetric hash has already been enabled");
7688 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7690 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7692 "Symmetric hash has already been disabled");
7695 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7697 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7698 I40E_WRITE_FLUSH(hw);
7702 * Get global configurations of hash function type and symmetric hash enable
7703 * per flow type (pctype). Note that global configuration means it affects all
7704 * the ports on the same NIC.
7707 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7708 struct rte_eth_hash_global_conf *g_cfg)
7710 uint32_t reg, mask = I40E_FLOW_TYPES;
7712 enum i40e_filter_pctype pctype;
7714 memset(g_cfg, 0, sizeof(*g_cfg));
7715 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7716 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7717 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7719 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7720 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7721 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7723 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7724 if (!(mask & (1UL << i)))
7726 mask &= ~(1UL << i);
7727 /* Bit set indicats the coresponding flow type is supported */
7728 g_cfg->valid_bit_mask[0] |= (1UL << i);
7729 /* if flowtype is invalid, continue */
7730 if (!I40E_VALID_FLOW(i))
7732 pctype = i40e_flowtype_to_pctype(i);
7733 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7734 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7735 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7742 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7745 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7747 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7748 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7749 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7750 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7756 * As i40e supports less than 32 flow types, only first 32 bits need to
7759 mask0 = g_cfg->valid_bit_mask[0];
7760 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7762 /* Check if any unsupported flow type configured */
7763 if ((mask0 | i40e_mask) ^ i40e_mask)
7766 if (g_cfg->valid_bit_mask[i])
7774 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7780 * Set global configurations of hash function type and symmetric hash enable
7781 * per flow type (pctype). Note any modifying global configuration will affect
7782 * all the ports on the same NIC.
7785 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7786 struct rte_eth_hash_global_conf *g_cfg)
7791 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7792 enum i40e_filter_pctype pctype;
7794 /* Check the input parameters */
7795 ret = i40e_hash_global_config_check(g_cfg);
7799 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7800 if (!(mask0 & (1UL << i)))
7802 mask0 &= ~(1UL << i);
7803 /* if flowtype is invalid, continue */
7804 if (!I40E_VALID_FLOW(i))
7806 pctype = i40e_flowtype_to_pctype(i);
7807 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7808 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7809 if (hw->mac.type == I40E_MAC_X722) {
7810 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7811 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7812 I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7813 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7814 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7816 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7817 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7819 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7820 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7821 I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7822 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7823 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7825 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7826 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7827 I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7828 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7829 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7831 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7832 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7834 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7835 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7836 I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7837 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7838 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7841 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7845 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7849 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7850 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7852 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7854 "Hash function already set to Toeplitz");
7857 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7858 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7860 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7862 "Hash function already set to Simple XOR");
7865 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7867 /* Use the default, and keep it as it is */
7870 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7873 I40E_WRITE_FLUSH(hw);
7879 * Valid input sets for hash and flow director filters per PCTYPE
7882 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7883 enum rte_filter_type filter)
7887 static const uint64_t valid_hash_inset_table[] = {
7888 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7889 I40E_INSET_DMAC | I40E_INSET_SMAC |
7890 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7891 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7892 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7893 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7894 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7895 I40E_INSET_FLEX_PAYLOAD,
7896 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7897 I40E_INSET_DMAC | I40E_INSET_SMAC |
7898 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7899 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7900 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7901 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7902 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7903 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7904 I40E_INSET_FLEX_PAYLOAD,
7905 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7906 I40E_INSET_DMAC | I40E_INSET_SMAC |
7907 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7908 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7909 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7910 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7911 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7912 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7913 I40E_INSET_FLEX_PAYLOAD,
7914 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7915 I40E_INSET_DMAC | I40E_INSET_SMAC |
7916 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7917 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7918 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7919 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7920 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7921 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7922 I40E_INSET_FLEX_PAYLOAD,
7923 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7924 I40E_INSET_DMAC | I40E_INSET_SMAC |
7925 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7926 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7927 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7928 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7929 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7930 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7931 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7932 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7933 I40E_INSET_DMAC | I40E_INSET_SMAC |
7934 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7935 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7936 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7937 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7938 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7939 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7940 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7941 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7942 I40E_INSET_DMAC | I40E_INSET_SMAC |
7943 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7944 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7945 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7946 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7947 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7948 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7949 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7950 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7951 I40E_INSET_DMAC | I40E_INSET_SMAC |
7952 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7953 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7954 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7955 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7956 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7957 I40E_INSET_FLEX_PAYLOAD,
7958 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7959 I40E_INSET_DMAC | I40E_INSET_SMAC |
7960 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7961 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7962 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7963 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7964 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7965 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7966 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7967 I40E_INSET_DMAC | I40E_INSET_SMAC |
7968 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7969 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7970 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7971 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7972 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7973 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7974 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7975 I40E_INSET_DMAC | I40E_INSET_SMAC |
7976 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7977 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7978 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7979 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7980 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7981 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7982 I40E_INSET_FLEX_PAYLOAD,
7983 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7984 I40E_INSET_DMAC | I40E_INSET_SMAC |
7985 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7986 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7987 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7988 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7989 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7990 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7991 I40E_INSET_FLEX_PAYLOAD,
7992 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7993 I40E_INSET_DMAC | I40E_INSET_SMAC |
7994 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7995 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7996 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7997 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7998 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7999 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8000 I40E_INSET_FLEX_PAYLOAD,
8001 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8002 I40E_INSET_DMAC | I40E_INSET_SMAC |
8003 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8004 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8005 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8006 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8007 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8008 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8009 I40E_INSET_FLEX_PAYLOAD,
8010 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8011 I40E_INSET_DMAC | I40E_INSET_SMAC |
8012 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8013 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8014 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8015 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8016 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8017 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8018 I40E_INSET_FLEX_PAYLOAD,
8019 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8020 I40E_INSET_DMAC | I40E_INSET_SMAC |
8021 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8022 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8023 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8024 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8025 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8026 I40E_INSET_FLEX_PAYLOAD,
8027 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8028 I40E_INSET_DMAC | I40E_INSET_SMAC |
8029 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8030 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8031 I40E_INSET_FLEX_PAYLOAD,
8035 * Flow director supports only fields defined in
8036 * union rte_eth_fdir_flow.
8038 static const uint64_t valid_fdir_inset_table[] = {
8039 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8040 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8041 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8042 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8043 I40E_INSET_IPV4_TTL,
8044 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8045 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8046 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8047 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8048 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8049 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8050 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8051 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8052 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8053 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8054 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8055 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8056 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8057 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8058 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8059 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8060 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8061 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8062 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8063 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8064 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8065 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8066 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8067 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8068 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8069 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8070 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8071 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8072 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8073 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8075 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8076 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8077 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8078 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8079 I40E_INSET_IPV4_TTL,
8080 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8081 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8082 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8083 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8084 I40E_INSET_IPV6_HOP_LIMIT,
8085 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8086 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8087 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8088 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8089 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8090 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8091 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8092 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8093 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8094 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8095 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8096 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8097 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8098 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8099 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8100 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8101 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8102 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8103 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8104 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8105 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8106 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8107 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8108 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8109 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8110 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8111 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8112 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8113 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8114 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8116 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8117 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8118 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8119 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8120 I40E_INSET_IPV6_HOP_LIMIT,
8121 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8122 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8123 I40E_INSET_LAST_ETHER_TYPE,
8126 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8128 if (filter == RTE_ETH_FILTER_HASH)
8129 valid = valid_hash_inset_table[pctype];
8131 valid = valid_fdir_inset_table[pctype];
8137 * Validate if the input set is allowed for a specific PCTYPE
8140 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8141 enum rte_filter_type filter, uint64_t inset)
8145 valid = i40e_get_valid_input_set(pctype, filter);
8146 if (inset & (~valid))
8152 /* default input set fields combination per pctype */
8154 i40e_get_default_input_set(uint16_t pctype)
8156 static const uint64_t default_inset_table[] = {
8157 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8158 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8159 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8160 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8161 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8162 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8163 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8164 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8165 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8166 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8167 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8168 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8169 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8170 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8171 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8172 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8173 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8174 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8175 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8176 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8178 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8179 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8180 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8181 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8182 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8183 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8184 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8185 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8186 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8187 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8188 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8189 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8190 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8191 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8192 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8193 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8194 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8195 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8196 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8197 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8198 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8199 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8201 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8202 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8203 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8204 I40E_INSET_LAST_ETHER_TYPE,
8207 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8210 return default_inset_table[pctype];
8214 * Parse the input set from index to logical bit masks
8217 i40e_parse_input_set(uint64_t *inset,
8218 enum i40e_filter_pctype pctype,
8219 enum rte_eth_input_set_field *field,
8225 static const struct {
8226 enum rte_eth_input_set_field field;
8228 } inset_convert_table[] = {
8229 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8230 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8231 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8232 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8233 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8234 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8235 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8236 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8237 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8238 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8239 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8240 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8241 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8242 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8243 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8244 I40E_INSET_IPV6_NEXT_HDR},
8245 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8246 I40E_INSET_IPV6_HOP_LIMIT},
8247 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8248 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8249 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8250 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8251 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8252 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8253 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8254 I40E_INSET_SCTP_VT},
8255 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8256 I40E_INSET_TUNNEL_DMAC},
8257 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8258 I40E_INSET_VLAN_TUNNEL},
8259 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8260 I40E_INSET_TUNNEL_ID},
8261 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8262 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8263 I40E_INSET_FLEX_PAYLOAD_W1},
8264 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8265 I40E_INSET_FLEX_PAYLOAD_W2},
8266 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8267 I40E_INSET_FLEX_PAYLOAD_W3},
8268 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8269 I40E_INSET_FLEX_PAYLOAD_W4},
8270 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8271 I40E_INSET_FLEX_PAYLOAD_W5},
8272 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8273 I40E_INSET_FLEX_PAYLOAD_W6},
8274 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8275 I40E_INSET_FLEX_PAYLOAD_W7},
8276 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8277 I40E_INSET_FLEX_PAYLOAD_W8},
8280 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8283 /* Only one item allowed for default or all */
8285 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8286 *inset = i40e_get_default_input_set(pctype);
8288 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8289 *inset = I40E_INSET_NONE;
8294 for (i = 0, *inset = 0; i < size; i++) {
8295 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8296 if (field[i] == inset_convert_table[j].field) {
8297 *inset |= inset_convert_table[j].inset;
8302 /* It contains unsupported input set, return immediately */
8303 if (j == RTE_DIM(inset_convert_table))
8311 * Translate the input set from bit masks to register aware bit masks
8315 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8325 static const struct inset_map inset_map_common[] = {
8326 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8327 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8328 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8329 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8330 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8331 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8332 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8333 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8334 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8335 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8336 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8337 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8338 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8339 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8340 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8341 {I40E_INSET_TUNNEL_DMAC,
8342 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8343 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8344 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8345 {I40E_INSET_TUNNEL_SRC_PORT,
8346 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8347 {I40E_INSET_TUNNEL_DST_PORT,
8348 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8349 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8350 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8351 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8352 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8353 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8354 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8355 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8356 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8357 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8360 /* some different registers map in x722*/
8361 static const struct inset_map inset_map_diff_x722[] = {
8362 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8363 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8364 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8365 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8368 static const struct inset_map inset_map_diff_not_x722[] = {
8369 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8370 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8371 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8372 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8378 /* Translate input set to register aware inset */
8379 if (type == I40E_MAC_X722) {
8380 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8381 if (input & inset_map_diff_x722[i].inset)
8382 val |= inset_map_diff_x722[i].inset_reg;
8385 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8386 if (input & inset_map_diff_not_x722[i].inset)
8387 val |= inset_map_diff_not_x722[i].inset_reg;
8391 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8392 if (input & inset_map_common[i].inset)
8393 val |= inset_map_common[i].inset_reg;
8400 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8403 uint64_t inset_need_mask = inset;
8405 static const struct {
8408 } inset_mask_map[] = {
8409 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8410 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8411 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8412 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8413 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8414 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8415 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8416 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8419 if (!inset || !mask || !nb_elem)
8422 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8423 /* Clear the inset bit, if no MASK is required,
8424 * for example proto + ttl
8426 if ((inset & inset_mask_map[i].inset) ==
8427 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8428 inset_need_mask &= ~inset_mask_map[i].inset;
8429 if (!inset_need_mask)
8432 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8433 if ((inset_need_mask & inset_mask_map[i].inset) ==
8434 inset_mask_map[i].inset) {
8435 if (idx >= nb_elem) {
8436 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8439 mask[idx] = inset_mask_map[i].mask;
8448 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8450 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8452 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8454 i40e_write_rx_ctl(hw, addr, val);
8455 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8456 (uint32_t)i40e_read_rx_ctl(hw, addr));
8460 i40e_filter_input_set_init(struct i40e_pf *pf)
8462 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8463 enum i40e_filter_pctype pctype;
8464 uint64_t input_set, inset_reg;
8465 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8468 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8469 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8470 if (hw->mac.type == I40E_MAC_X722) {
8471 if (!I40E_VALID_PCTYPE_X722(pctype))
8474 if (!I40E_VALID_PCTYPE(pctype))
8478 input_set = i40e_get_default_input_set(pctype);
8480 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8481 I40E_INSET_MASK_NUM_REG);
8484 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8487 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8488 (uint32_t)(inset_reg & UINT32_MAX));
8489 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8490 (uint32_t)((inset_reg >>
8491 I40E_32_BIT_WIDTH) & UINT32_MAX));
8492 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8493 (uint32_t)(inset_reg & UINT32_MAX));
8494 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8495 (uint32_t)((inset_reg >>
8496 I40E_32_BIT_WIDTH) & UINT32_MAX));
8498 for (i = 0; i < num; i++) {
8499 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8501 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8504 /*clear unused mask registers of the pctype */
8505 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8506 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8508 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8511 I40E_WRITE_FLUSH(hw);
8513 /* store the default input set */
8514 pf->hash_input_set[pctype] = input_set;
8515 pf->fdir.input_set[pctype] = input_set;
8520 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8521 struct rte_eth_input_set_conf *conf)
8523 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8524 enum i40e_filter_pctype pctype;
8525 uint64_t input_set, inset_reg = 0;
8526 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8530 PMD_DRV_LOG(ERR, "Invalid pointer");
8533 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8534 conf->op != RTE_ETH_INPUT_SET_ADD) {
8535 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8539 if (!I40E_VALID_FLOW(conf->flow_type)) {
8540 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8544 if (hw->mac.type == I40E_MAC_X722) {
8545 /* get translated pctype value in fd pctype register */
8546 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8547 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8550 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8552 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8555 PMD_DRV_LOG(ERR, "Failed to parse input set");
8558 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8560 PMD_DRV_LOG(ERR, "Invalid input set");
8563 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8564 /* get inset value in register */
8565 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8566 inset_reg <<= I40E_32_BIT_WIDTH;
8567 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8568 input_set |= pf->hash_input_set[pctype];
8570 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8571 I40E_INSET_MASK_NUM_REG);
8575 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8577 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8578 (uint32_t)(inset_reg & UINT32_MAX));
8579 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8580 (uint32_t)((inset_reg >>
8581 I40E_32_BIT_WIDTH) & UINT32_MAX));
8583 for (i = 0; i < num; i++)
8584 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8586 /*clear unused mask registers of the pctype */
8587 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8588 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8590 I40E_WRITE_FLUSH(hw);
8592 pf->hash_input_set[pctype] = input_set;
8597 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8598 struct rte_eth_input_set_conf *conf)
8600 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8601 enum i40e_filter_pctype pctype;
8602 uint64_t input_set, inset_reg = 0;
8603 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8607 PMD_DRV_LOG(ERR, "Invalid pointer");
8610 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8611 conf->op != RTE_ETH_INPUT_SET_ADD) {
8612 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8616 if (!I40E_VALID_FLOW(conf->flow_type)) {
8617 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8621 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8623 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8626 PMD_DRV_LOG(ERR, "Failed to parse input set");
8629 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8631 PMD_DRV_LOG(ERR, "Invalid input set");
8635 /* get inset value in register */
8636 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8637 inset_reg <<= I40E_32_BIT_WIDTH;
8638 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8640 /* Can not change the inset reg for flex payload for fdir,
8641 * it is done by writing I40E_PRTQF_FD_FLXINSET
8642 * in i40e_set_flex_mask_on_pctype.
8644 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8645 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8647 input_set |= pf->fdir.input_set[pctype];
8648 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8649 I40E_INSET_MASK_NUM_REG);
8653 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8655 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8656 (uint32_t)(inset_reg & UINT32_MAX));
8657 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8658 (uint32_t)((inset_reg >>
8659 I40E_32_BIT_WIDTH) & UINT32_MAX));
8661 for (i = 0; i < num; i++)
8662 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8664 /*clear unused mask registers of the pctype */
8665 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8666 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8668 I40E_WRITE_FLUSH(hw);
8670 pf->fdir.input_set[pctype] = input_set;
8675 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8680 PMD_DRV_LOG(ERR, "Invalid pointer");
8684 switch (info->info_type) {
8685 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8686 i40e_get_symmetric_hash_enable_per_port(hw,
8687 &(info->info.enable));
8689 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8690 ret = i40e_get_hash_filter_global_config(hw,
8691 &(info->info.global_conf));
8694 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8704 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8709 PMD_DRV_LOG(ERR, "Invalid pointer");
8713 switch (info->info_type) {
8714 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8715 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8717 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8718 ret = i40e_set_hash_filter_global_config(hw,
8719 &(info->info.global_conf));
8721 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8722 ret = i40e_hash_filter_inset_select(hw,
8723 &(info->info.input_set_conf));
8727 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8736 /* Operations for hash function */
8738 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8739 enum rte_filter_op filter_op,
8742 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8745 switch (filter_op) {
8746 case RTE_ETH_FILTER_NOP:
8748 case RTE_ETH_FILTER_GET:
8749 ret = i40e_hash_filter_get(hw,
8750 (struct rte_eth_hash_filter_info *)arg);
8752 case RTE_ETH_FILTER_SET:
8753 ret = i40e_hash_filter_set(hw,
8754 (struct rte_eth_hash_filter_info *)arg);
8757 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8766 /* Convert ethertype filter structure */
8768 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8769 struct i40e_ethertype_filter *filter)
8771 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8772 filter->input.ether_type = input->ether_type;
8773 filter->flags = input->flags;
8774 filter->queue = input->queue;
8779 /* Check if there exists the ehtertype filter */
8780 struct i40e_ethertype_filter *
8781 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8782 const struct i40e_ethertype_filter_input *input)
8786 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8790 return ethertype_rule->hash_map[ret];
8793 /* Add ethertype filter in SW list */
8795 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8796 struct i40e_ethertype_filter *filter)
8798 struct i40e_ethertype_rule *rule = &pf->ethertype;
8801 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8804 "Failed to insert ethertype filter"
8805 " to hash table %d!",
8809 rule->hash_map[ret] = filter;
8811 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8816 /* Delete ethertype filter in SW list */
8818 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8819 struct i40e_ethertype_filter_input *input)
8821 struct i40e_ethertype_rule *rule = &pf->ethertype;
8822 struct i40e_ethertype_filter *filter;
8825 ret = rte_hash_del_key(rule->hash_table, input);
8828 "Failed to delete ethertype filter"
8829 " to hash table %d!",
8833 filter = rule->hash_map[ret];
8834 rule->hash_map[ret] = NULL;
8836 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8843 * Configure ethertype filter, which can director packet by filtering
8844 * with mac address and ether_type or only ether_type
8847 i40e_ethertype_filter_set(struct i40e_pf *pf,
8848 struct rte_eth_ethertype_filter *filter,
8851 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8852 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8853 struct i40e_ethertype_filter *ethertype_filter, *node;
8854 struct i40e_ethertype_filter check_filter;
8855 struct i40e_control_filter_stats stats;
8859 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8860 PMD_DRV_LOG(ERR, "Invalid queue ID");
8863 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8864 filter->ether_type == ETHER_TYPE_IPv6) {
8866 "unsupported ether_type(0x%04x) in control packet filter.",
8867 filter->ether_type);
8870 if (filter->ether_type == ETHER_TYPE_VLAN)
8871 PMD_DRV_LOG(WARNING,
8872 "filter vlan ether_type in first tag is not supported.");
8874 /* Check if there is the filter in SW list */
8875 memset(&check_filter, 0, sizeof(check_filter));
8876 i40e_ethertype_filter_convert(filter, &check_filter);
8877 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8878 &check_filter.input);
8880 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8884 if (!add && !node) {
8885 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8889 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8890 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8891 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8892 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8893 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8895 memset(&stats, 0, sizeof(stats));
8896 ret = i40e_aq_add_rem_control_packet_filter(hw,
8897 filter->mac_addr.addr_bytes,
8898 filter->ether_type, flags,
8900 filter->queue, add, &stats, NULL);
8903 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8904 ret, stats.mac_etype_used, stats.etype_used,
8905 stats.mac_etype_free, stats.etype_free);
8909 /* Add or delete a filter in SW list */
8911 ethertype_filter = rte_zmalloc("ethertype_filter",
8912 sizeof(*ethertype_filter), 0);
8913 rte_memcpy(ethertype_filter, &check_filter,
8914 sizeof(check_filter));
8915 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8917 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8924 * Handle operations for ethertype filter.
8927 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8928 enum rte_filter_op filter_op,
8931 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8934 if (filter_op == RTE_ETH_FILTER_NOP)
8938 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8943 switch (filter_op) {
8944 case RTE_ETH_FILTER_ADD:
8945 ret = i40e_ethertype_filter_set(pf,
8946 (struct rte_eth_ethertype_filter *)arg,
8949 case RTE_ETH_FILTER_DELETE:
8950 ret = i40e_ethertype_filter_set(pf,
8951 (struct rte_eth_ethertype_filter *)arg,
8955 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8963 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8964 enum rte_filter_type filter_type,
8965 enum rte_filter_op filter_op,
8973 switch (filter_type) {
8974 case RTE_ETH_FILTER_NONE:
8975 /* For global configuration */
8976 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8978 case RTE_ETH_FILTER_HASH:
8979 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8981 case RTE_ETH_FILTER_MACVLAN:
8982 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8984 case RTE_ETH_FILTER_ETHERTYPE:
8985 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8987 case RTE_ETH_FILTER_TUNNEL:
8988 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8990 case RTE_ETH_FILTER_FDIR:
8991 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8993 case RTE_ETH_FILTER_GENERIC:
8994 if (filter_op != RTE_ETH_FILTER_GET)
8996 *(const void **)arg = &i40e_flow_ops;
8999 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9009 * Check and enable Extended Tag.
9010 * Enabling Extended Tag is important for 40G performance.
9013 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9015 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9019 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9022 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9026 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9027 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9032 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9035 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9039 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9040 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9043 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9044 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9047 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9054 * As some registers wouldn't be reset unless a global hardware reset,
9055 * hardware initialization is needed to put those registers into an
9056 * expected initial state.
9059 i40e_hw_init(struct rte_eth_dev *dev)
9061 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9063 i40e_enable_extended_tag(dev);
9065 /* clear the PF Queue Filter control register */
9066 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9068 /* Disable symmetric hash per port */
9069 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9072 enum i40e_filter_pctype
9073 i40e_flowtype_to_pctype(uint16_t flow_type)
9075 static const enum i40e_filter_pctype pctype_table[] = {
9076 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9077 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9078 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9079 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9080 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9081 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9082 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9083 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9084 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9085 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9086 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9087 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9088 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9089 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9090 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9091 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9092 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9093 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9094 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9097 return pctype_table[flow_type];
9101 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9103 static const uint16_t flowtype_table[] = {
9104 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9105 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9106 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9107 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9108 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9109 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9110 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9111 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9112 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9113 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9114 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9115 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9116 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9117 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9118 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9119 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9120 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9121 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9122 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9123 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9124 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9125 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9126 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9127 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9128 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9129 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9130 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9131 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9132 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9133 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9134 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9137 return flowtype_table[pctype];
9141 * On X710, performance number is far from the expectation on recent firmware
9142 * versions; on XL710, performance number is also far from the expectation on
9143 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9144 * mode is enabled and port MAC address is equal to the packet destination MAC
9145 * address. The fix for this issue may not be integrated in the following
9146 * firmware version. So the workaround in software driver is needed. It needs
9147 * to modify the initial values of 3 internal only registers for both X710 and
9148 * XL710. Note that the values for X710 or XL710 could be different, and the
9149 * workaround can be removed when it is fixed in firmware in the future.
9152 /* For both X710 and XL710 */
9153 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9154 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9156 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9157 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9160 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9161 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9164 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9166 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9167 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9170 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9172 enum i40e_status_code status;
9173 struct i40e_aq_get_phy_abilities_resp phy_ab;
9176 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9186 i40e_configure_registers(struct i40e_hw *hw)
9192 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9193 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9194 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9200 for (i = 0; i < RTE_DIM(reg_table); i++) {
9201 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9202 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9204 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9205 else /* For X710/XL710/XXV710 */
9207 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9210 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9211 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9213 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9214 else /* For X710/XL710/XXV710 */
9216 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9219 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9220 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9221 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9223 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9226 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9229 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9232 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9236 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9237 reg_table[i].addr, reg);
9238 if (reg == reg_table[i].val)
9241 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9242 reg_table[i].val, NULL);
9245 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9246 reg_table[i].val, reg_table[i].addr);
9249 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9250 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9254 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9255 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9256 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9257 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9259 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9264 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9265 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9269 /* Configure for double VLAN RX stripping */
9270 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9271 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9272 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9273 ret = i40e_aq_debug_write_register(hw,
9274 I40E_VSI_TSR(vsi->vsi_id),
9277 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9279 return I40E_ERR_CONFIG;
9283 /* Configure for double VLAN TX insertion */
9284 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9285 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9286 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9287 ret = i40e_aq_debug_write_register(hw,
9288 I40E_VSI_L2TAGSTXVALID(
9289 vsi->vsi_id), reg, NULL);
9292 "Failed to update VSI_L2TAGSTXVALID[%d]",
9294 return I40E_ERR_CONFIG;
9302 * i40e_aq_add_mirror_rule
9303 * @hw: pointer to the hardware structure
9304 * @seid: VEB seid to add mirror rule to
9305 * @dst_id: destination vsi seid
9306 * @entries: Buffer which contains the entities to be mirrored
9307 * @count: number of entities contained in the buffer
9308 * @rule_id:the rule_id of the rule to be added
9310 * Add a mirror rule for a given veb.
9313 static enum i40e_status_code
9314 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9315 uint16_t seid, uint16_t dst_id,
9316 uint16_t rule_type, uint16_t *entries,
9317 uint16_t count, uint16_t *rule_id)
9319 struct i40e_aq_desc desc;
9320 struct i40e_aqc_add_delete_mirror_rule cmd;
9321 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9322 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9325 enum i40e_status_code status;
9327 i40e_fill_default_direct_cmd_desc(&desc,
9328 i40e_aqc_opc_add_mirror_rule);
9329 memset(&cmd, 0, sizeof(cmd));
9331 buff_len = sizeof(uint16_t) * count;
9332 desc.datalen = rte_cpu_to_le_16(buff_len);
9334 desc.flags |= rte_cpu_to_le_16(
9335 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9336 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9337 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9338 cmd.num_entries = rte_cpu_to_le_16(count);
9339 cmd.seid = rte_cpu_to_le_16(seid);
9340 cmd.destination = rte_cpu_to_le_16(dst_id);
9342 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9343 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9345 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9346 hw->aq.asq_last_status, resp->rule_id,
9347 resp->mirror_rules_used, resp->mirror_rules_free);
9348 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9354 * i40e_aq_del_mirror_rule
9355 * @hw: pointer to the hardware structure
9356 * @seid: VEB seid to add mirror rule to
9357 * @entries: Buffer which contains the entities to be mirrored
9358 * @count: number of entities contained in the buffer
9359 * @rule_id:the rule_id of the rule to be delete
9361 * Delete a mirror rule for a given veb.
9364 static enum i40e_status_code
9365 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9366 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9367 uint16_t count, uint16_t rule_id)
9369 struct i40e_aq_desc desc;
9370 struct i40e_aqc_add_delete_mirror_rule cmd;
9371 uint16_t buff_len = 0;
9372 enum i40e_status_code status;
9375 i40e_fill_default_direct_cmd_desc(&desc,
9376 i40e_aqc_opc_delete_mirror_rule);
9377 memset(&cmd, 0, sizeof(cmd));
9378 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9379 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9381 cmd.num_entries = count;
9382 buff_len = sizeof(uint16_t) * count;
9383 desc.datalen = rte_cpu_to_le_16(buff_len);
9384 buff = (void *)entries;
9386 /* rule id is filled in destination field for deleting mirror rule */
9387 cmd.destination = rte_cpu_to_le_16(rule_id);
9389 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9390 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9391 cmd.seid = rte_cpu_to_le_16(seid);
9393 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9394 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9400 * i40e_mirror_rule_set
9401 * @dev: pointer to the hardware structure
9402 * @mirror_conf: mirror rule info
9403 * @sw_id: mirror rule's sw_id
9404 * @on: enable/disable
9406 * set a mirror rule.
9410 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9411 struct rte_eth_mirror_conf *mirror_conf,
9412 uint8_t sw_id, uint8_t on)
9414 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9415 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9416 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9417 struct i40e_mirror_rule *parent = NULL;
9418 uint16_t seid, dst_seid, rule_id;
9422 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9424 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9426 "mirror rule can not be configured without veb or vfs.");
9429 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9430 PMD_DRV_LOG(ERR, "mirror table is full.");
9433 if (mirror_conf->dst_pool > pf->vf_num) {
9434 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9435 mirror_conf->dst_pool);
9439 seid = pf->main_vsi->veb->seid;
9441 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9442 if (sw_id <= it->index) {
9448 if (mirr_rule && sw_id == mirr_rule->index) {
9450 PMD_DRV_LOG(ERR, "mirror rule exists.");
9453 ret = i40e_aq_del_mirror_rule(hw, seid,
9454 mirr_rule->rule_type,
9456 mirr_rule->num_entries, mirr_rule->id);
9459 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9460 ret, hw->aq.asq_last_status);
9463 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9464 rte_free(mirr_rule);
9465 pf->nb_mirror_rule--;
9469 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9473 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9474 sizeof(struct i40e_mirror_rule) , 0);
9476 PMD_DRV_LOG(ERR, "failed to allocate memory");
9477 return I40E_ERR_NO_MEMORY;
9479 switch (mirror_conf->rule_type) {
9480 case ETH_MIRROR_VLAN:
9481 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9482 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9483 mirr_rule->entries[j] =
9484 mirror_conf->vlan.vlan_id[i];
9489 PMD_DRV_LOG(ERR, "vlan is not specified.");
9490 rte_free(mirr_rule);
9493 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9495 case ETH_MIRROR_VIRTUAL_POOL_UP:
9496 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9497 /* check if the specified pool bit is out of range */
9498 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9499 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9500 rte_free(mirr_rule);
9503 for (i = 0, j = 0; i < pf->vf_num; i++) {
9504 if (mirror_conf->pool_mask & (1ULL << i)) {
9505 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9509 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9510 /* add pf vsi to entries */
9511 mirr_rule->entries[j] = pf->main_vsi_seid;
9515 PMD_DRV_LOG(ERR, "pool is not specified.");
9516 rte_free(mirr_rule);
9519 /* egress and ingress in aq commands means from switch but not port */
9520 mirr_rule->rule_type =
9521 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9522 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9523 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9525 case ETH_MIRROR_UPLINK_PORT:
9526 /* egress and ingress in aq commands means from switch but not port*/
9527 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9529 case ETH_MIRROR_DOWNLINK_PORT:
9530 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9533 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9534 mirror_conf->rule_type);
9535 rte_free(mirr_rule);
9539 /* If the dst_pool is equal to vf_num, consider it as PF */
9540 if (mirror_conf->dst_pool == pf->vf_num)
9541 dst_seid = pf->main_vsi_seid;
9543 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9545 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9546 mirr_rule->rule_type, mirr_rule->entries,
9550 "failed to add mirror rule: ret = %d, aq_err = %d.",
9551 ret, hw->aq.asq_last_status);
9552 rte_free(mirr_rule);
9556 mirr_rule->index = sw_id;
9557 mirr_rule->num_entries = j;
9558 mirr_rule->id = rule_id;
9559 mirr_rule->dst_vsi_seid = dst_seid;
9562 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9564 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9566 pf->nb_mirror_rule++;
9571 * i40e_mirror_rule_reset
9572 * @dev: pointer to the device
9573 * @sw_id: mirror rule's sw_id
9575 * reset a mirror rule.
9579 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9581 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9582 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9583 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9587 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9589 seid = pf->main_vsi->veb->seid;
9591 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9592 if (sw_id == it->index) {
9598 ret = i40e_aq_del_mirror_rule(hw, seid,
9599 mirr_rule->rule_type,
9601 mirr_rule->num_entries, mirr_rule->id);
9604 "failed to remove mirror rule: status = %d, aq_err = %d.",
9605 ret, hw->aq.asq_last_status);
9608 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9609 rte_free(mirr_rule);
9610 pf->nb_mirror_rule--;
9612 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9619 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9621 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9622 uint64_t systim_cycles;
9624 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9625 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9628 return systim_cycles;
9632 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9634 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9637 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9638 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9645 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9647 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9650 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9651 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9658 i40e_start_timecounters(struct rte_eth_dev *dev)
9660 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9661 struct i40e_adapter *adapter =
9662 (struct i40e_adapter *)dev->data->dev_private;
9663 struct rte_eth_link link;
9664 uint32_t tsync_inc_l;
9665 uint32_t tsync_inc_h;
9667 /* Get current link speed. */
9668 memset(&link, 0, sizeof(link));
9669 i40e_dev_link_update(dev, 1);
9670 rte_i40e_dev_atomic_read_link_status(dev, &link);
9672 switch (link.link_speed) {
9673 case ETH_SPEED_NUM_40G:
9674 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9675 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9677 case ETH_SPEED_NUM_10G:
9678 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9679 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9681 case ETH_SPEED_NUM_1G:
9682 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9683 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9690 /* Set the timesync increment value. */
9691 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9692 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9694 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9695 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9696 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9698 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9699 adapter->systime_tc.cc_shift = 0;
9700 adapter->systime_tc.nsec_mask = 0;
9702 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9703 adapter->rx_tstamp_tc.cc_shift = 0;
9704 adapter->rx_tstamp_tc.nsec_mask = 0;
9706 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9707 adapter->tx_tstamp_tc.cc_shift = 0;
9708 adapter->tx_tstamp_tc.nsec_mask = 0;
9712 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9714 struct i40e_adapter *adapter =
9715 (struct i40e_adapter *)dev->data->dev_private;
9717 adapter->systime_tc.nsec += delta;
9718 adapter->rx_tstamp_tc.nsec += delta;
9719 adapter->tx_tstamp_tc.nsec += delta;
9725 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9728 struct i40e_adapter *adapter =
9729 (struct i40e_adapter *)dev->data->dev_private;
9731 ns = rte_timespec_to_ns(ts);
9733 /* Set the timecounters to a new value. */
9734 adapter->systime_tc.nsec = ns;
9735 adapter->rx_tstamp_tc.nsec = ns;
9736 adapter->tx_tstamp_tc.nsec = ns;
9742 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9744 uint64_t ns, systime_cycles;
9745 struct i40e_adapter *adapter =
9746 (struct i40e_adapter *)dev->data->dev_private;
9748 systime_cycles = i40e_read_systime_cyclecounter(dev);
9749 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9750 *ts = rte_ns_to_timespec(ns);
9756 i40e_timesync_enable(struct rte_eth_dev *dev)
9758 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9759 uint32_t tsync_ctl_l;
9760 uint32_t tsync_ctl_h;
9762 /* Stop the timesync system time. */
9763 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9764 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9765 /* Reset the timesync system time value. */
9766 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9767 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9769 i40e_start_timecounters(dev);
9771 /* Clear timesync registers. */
9772 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9773 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9774 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9775 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9776 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9777 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9779 /* Enable timestamping of PTP packets. */
9780 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9781 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9783 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9784 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9785 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9787 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9788 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9794 i40e_timesync_disable(struct rte_eth_dev *dev)
9796 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9797 uint32_t tsync_ctl_l;
9798 uint32_t tsync_ctl_h;
9800 /* Disable timestamping of transmitted PTP packets. */
9801 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9802 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9804 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9805 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9807 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9808 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9810 /* Reset the timesync increment value. */
9811 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9812 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9818 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9819 struct timespec *timestamp, uint32_t flags)
9821 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9822 struct i40e_adapter *adapter =
9823 (struct i40e_adapter *)dev->data->dev_private;
9825 uint32_t sync_status;
9826 uint32_t index = flags & 0x03;
9827 uint64_t rx_tstamp_cycles;
9830 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9831 if ((sync_status & (1 << index)) == 0)
9834 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9835 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9836 *timestamp = rte_ns_to_timespec(ns);
9842 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9843 struct timespec *timestamp)
9845 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9846 struct i40e_adapter *adapter =
9847 (struct i40e_adapter *)dev->data->dev_private;
9849 uint32_t sync_status;
9850 uint64_t tx_tstamp_cycles;
9853 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9854 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9857 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9858 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9859 *timestamp = rte_ns_to_timespec(ns);
9865 * i40e_parse_dcb_configure - parse dcb configure from user
9866 * @dev: the device being configured
9867 * @dcb_cfg: pointer of the result of parse
9868 * @*tc_map: bit map of enabled traffic classes
9870 * Returns 0 on success, negative value on failure
9873 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9874 struct i40e_dcbx_config *dcb_cfg,
9877 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9878 uint8_t i, tc_bw, bw_lf;
9880 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9882 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9883 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9884 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9888 /* assume each tc has the same bw */
9889 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9890 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9891 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9892 /* to ensure the sum of tcbw is equal to 100 */
9893 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9894 for (i = 0; i < bw_lf; i++)
9895 dcb_cfg->etscfg.tcbwtable[i]++;
9897 /* assume each tc has the same Transmission Selection Algorithm */
9898 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9899 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9901 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9902 dcb_cfg->etscfg.prioritytable[i] =
9903 dcb_rx_conf->dcb_tc[i];
9905 /* FW needs one App to configure HW */
9906 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9907 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9908 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9909 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9911 if (dcb_rx_conf->nb_tcs == 0)
9912 *tc_map = 1; /* tc0 only */
9914 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9916 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9917 dcb_cfg->pfc.willing = 0;
9918 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9919 dcb_cfg->pfc.pfcenable = *tc_map;
9925 static enum i40e_status_code
9926 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9927 struct i40e_aqc_vsi_properties_data *info,
9928 uint8_t enabled_tcmap)
9930 enum i40e_status_code ret;
9931 int i, total_tc = 0;
9932 uint16_t qpnum_per_tc, bsf, qp_idx;
9933 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9934 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9935 uint16_t used_queues;
9937 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9938 if (ret != I40E_SUCCESS)
9941 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9942 if (enabled_tcmap & (1 << i))
9947 vsi->enabled_tc = enabled_tcmap;
9949 /* different VSI has different queues assigned */
9950 if (vsi->type == I40E_VSI_MAIN)
9951 used_queues = dev_data->nb_rx_queues -
9952 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9953 else if (vsi->type == I40E_VSI_VMDQ2)
9954 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9956 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9957 return I40E_ERR_NO_AVAILABLE_VSI;
9960 qpnum_per_tc = used_queues / total_tc;
9961 /* Number of queues per enabled TC */
9962 if (qpnum_per_tc == 0) {
9963 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9964 return I40E_ERR_INVALID_QP_ID;
9966 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9968 bsf = rte_bsf32(qpnum_per_tc);
9971 * Configure TC and queue mapping parameters, for enabled TC,
9972 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9973 * default queue will serve it.
9976 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9977 if (vsi->enabled_tc & (1 << i)) {
9978 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9979 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9980 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9981 qp_idx += qpnum_per_tc;
9983 info->tc_mapping[i] = 0;
9986 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9987 if (vsi->type == I40E_VSI_SRIOV) {
9988 info->mapping_flags |=
9989 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9990 for (i = 0; i < vsi->nb_qps; i++)
9991 info->queue_mapping[i] =
9992 rte_cpu_to_le_16(vsi->base_queue + i);
9994 info->mapping_flags |=
9995 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9996 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9998 info->valid_sections |=
9999 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10001 return I40E_SUCCESS;
10005 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10006 * @veb: VEB to be configured
10007 * @tc_map: enabled TC bitmap
10009 * Returns 0 on success, negative value on failure
10011 static enum i40e_status_code
10012 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10014 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10015 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10016 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10017 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10018 enum i40e_status_code ret = I40E_SUCCESS;
10022 /* Check if enabled_tc is same as existing or new TCs */
10023 if (veb->enabled_tc == tc_map)
10026 /* configure tc bandwidth */
10027 memset(&veb_bw, 0, sizeof(veb_bw));
10028 veb_bw.tc_valid_bits = tc_map;
10029 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10030 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10031 if (tc_map & BIT_ULL(i))
10032 veb_bw.tc_bw_share_credits[i] = 1;
10034 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10038 "AQ command Config switch_comp BW allocation per TC failed = %d",
10039 hw->aq.asq_last_status);
10043 memset(&ets_query, 0, sizeof(ets_query));
10044 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10046 if (ret != I40E_SUCCESS) {
10048 "Failed to get switch_comp ETS configuration %u",
10049 hw->aq.asq_last_status);
10052 memset(&bw_query, 0, sizeof(bw_query));
10053 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10055 if (ret != I40E_SUCCESS) {
10057 "Failed to get switch_comp bandwidth configuration %u",
10058 hw->aq.asq_last_status);
10062 /* store and print out BW info */
10063 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10064 veb->bw_info.bw_max = ets_query.tc_bw_max;
10065 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10066 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10067 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10068 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10069 I40E_16_BIT_WIDTH);
10070 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10071 veb->bw_info.bw_ets_share_credits[i] =
10072 bw_query.tc_bw_share_credits[i];
10073 veb->bw_info.bw_ets_credits[i] =
10074 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10075 /* 4 bits per TC, 4th bit is reserved */
10076 veb->bw_info.bw_ets_max[i] =
10077 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10078 RTE_LEN2MASK(3, uint8_t));
10079 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10080 veb->bw_info.bw_ets_share_credits[i]);
10081 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10082 veb->bw_info.bw_ets_credits[i]);
10083 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10084 veb->bw_info.bw_ets_max[i]);
10087 veb->enabled_tc = tc_map;
10094 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10095 * @vsi: VSI to be configured
10096 * @tc_map: enabled TC bitmap
10098 * Returns 0 on success, negative value on failure
10100 static enum i40e_status_code
10101 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10103 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10104 struct i40e_vsi_context ctxt;
10105 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10106 enum i40e_status_code ret = I40E_SUCCESS;
10109 /* Check if enabled_tc is same as existing or new TCs */
10110 if (vsi->enabled_tc == tc_map)
10113 /* configure tc bandwidth */
10114 memset(&bw_data, 0, sizeof(bw_data));
10115 bw_data.tc_valid_bits = tc_map;
10116 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10117 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10118 if (tc_map & BIT_ULL(i))
10119 bw_data.tc_bw_credits[i] = 1;
10121 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10124 "AQ command Config VSI BW allocation per TC failed = %d",
10125 hw->aq.asq_last_status);
10128 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10129 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10131 /* Update Queue Pairs Mapping for currently enabled UPs */
10132 ctxt.seid = vsi->seid;
10133 ctxt.pf_num = hw->pf_id;
10135 ctxt.uplink_seid = vsi->uplink_seid;
10136 ctxt.info = vsi->info;
10138 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10142 /* Update the VSI after updating the VSI queue-mapping information */
10143 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10145 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10146 hw->aq.asq_last_status);
10149 /* update the local VSI info with updated queue map */
10150 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10151 sizeof(vsi->info.tc_mapping));
10152 (void)rte_memcpy(&vsi->info.queue_mapping,
10153 &ctxt.info.queue_mapping,
10154 sizeof(vsi->info.queue_mapping));
10155 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10156 vsi->info.valid_sections = 0;
10158 /* query and update current VSI BW information */
10159 ret = i40e_vsi_get_bw_config(vsi);
10162 "Failed updating vsi bw info, err %s aq_err %s",
10163 i40e_stat_str(hw, ret),
10164 i40e_aq_str(hw, hw->aq.asq_last_status));
10168 vsi->enabled_tc = tc_map;
10175 * i40e_dcb_hw_configure - program the dcb setting to hw
10176 * @pf: pf the configuration is taken on
10177 * @new_cfg: new configuration
10178 * @tc_map: enabled TC bitmap
10180 * Returns 0 on success, negative value on failure
10182 static enum i40e_status_code
10183 i40e_dcb_hw_configure(struct i40e_pf *pf,
10184 struct i40e_dcbx_config *new_cfg,
10187 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10188 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10189 struct i40e_vsi *main_vsi = pf->main_vsi;
10190 struct i40e_vsi_list *vsi_list;
10191 enum i40e_status_code ret;
10195 /* Use the FW API if FW > v4.4*/
10196 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10197 (hw->aq.fw_maj_ver >= 5))) {
10199 "FW < v4.4, can not use FW LLDP API to configure DCB");
10200 return I40E_ERR_FIRMWARE_API_VERSION;
10203 /* Check if need reconfiguration */
10204 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10205 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10206 return I40E_SUCCESS;
10209 /* Copy the new config to the current config */
10210 *old_cfg = *new_cfg;
10211 old_cfg->etsrec = old_cfg->etscfg;
10212 ret = i40e_set_dcb_config(hw);
10214 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10215 i40e_stat_str(hw, ret),
10216 i40e_aq_str(hw, hw->aq.asq_last_status));
10219 /* set receive Arbiter to RR mode and ETS scheme by default */
10220 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10221 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10222 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10223 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10224 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10225 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10226 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10227 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10228 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10229 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10230 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10231 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10232 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10234 /* get local mib to check whether it is configured correctly */
10236 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10237 /* Get Local DCB Config */
10238 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10239 &hw->local_dcbx_config);
10241 /* if Veb is created, need to update TC of it at first */
10242 if (main_vsi->veb) {
10243 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10245 PMD_INIT_LOG(WARNING,
10246 "Failed configuring TC for VEB seid=%d",
10247 main_vsi->veb->seid);
10249 /* Update each VSI */
10250 i40e_vsi_config_tc(main_vsi, tc_map);
10251 if (main_vsi->veb) {
10252 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10253 /* Beside main VSI and VMDQ VSIs, only enable default
10254 * TC for other VSIs
10256 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10257 ret = i40e_vsi_config_tc(vsi_list->vsi,
10260 ret = i40e_vsi_config_tc(vsi_list->vsi,
10261 I40E_DEFAULT_TCMAP);
10263 PMD_INIT_LOG(WARNING,
10264 "Failed configuring TC for VSI seid=%d",
10265 vsi_list->vsi->seid);
10269 return I40E_SUCCESS;
10273 * i40e_dcb_init_configure - initial dcb config
10274 * @dev: device being configured
10275 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10277 * Returns 0 on success, negative value on failure
10280 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10282 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10283 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10286 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10287 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10291 /* DCB initialization:
10292 * Update DCB configuration from the Firmware and configure
10293 * LLDP MIB change event.
10295 if (sw_dcb == TRUE) {
10296 ret = i40e_init_dcb(hw);
10297 /* If lldp agent is stopped, the return value from
10298 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10299 * adminq status. Otherwise, it should return success.
10301 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10302 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10303 memset(&hw->local_dcbx_config, 0,
10304 sizeof(struct i40e_dcbx_config));
10305 /* set dcb default configuration */
10306 hw->local_dcbx_config.etscfg.willing = 0;
10307 hw->local_dcbx_config.etscfg.maxtcs = 0;
10308 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10309 hw->local_dcbx_config.etscfg.tsatable[0] =
10311 /* all UPs mapping to TC0 */
10312 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10313 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10314 hw->local_dcbx_config.etsrec =
10315 hw->local_dcbx_config.etscfg;
10316 hw->local_dcbx_config.pfc.willing = 0;
10317 hw->local_dcbx_config.pfc.pfccap =
10318 I40E_MAX_TRAFFIC_CLASS;
10319 /* FW needs one App to configure HW */
10320 hw->local_dcbx_config.numapps = 1;
10321 hw->local_dcbx_config.app[0].selector =
10322 I40E_APP_SEL_ETHTYPE;
10323 hw->local_dcbx_config.app[0].priority = 3;
10324 hw->local_dcbx_config.app[0].protocolid =
10325 I40E_APP_PROTOID_FCOE;
10326 ret = i40e_set_dcb_config(hw);
10329 "default dcb config fails. err = %d, aq_err = %d.",
10330 ret, hw->aq.asq_last_status);
10335 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10336 ret, hw->aq.asq_last_status);
10340 ret = i40e_aq_start_lldp(hw, NULL);
10341 if (ret != I40E_SUCCESS)
10342 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10344 ret = i40e_init_dcb(hw);
10346 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10348 "HW doesn't support DCBX offload.");
10353 "DCBX configuration failed, err = %d, aq_err = %d.",
10354 ret, hw->aq.asq_last_status);
10362 * i40e_dcb_setup - setup dcb related config
10363 * @dev: device being configured
10365 * Returns 0 on success, negative value on failure
10368 i40e_dcb_setup(struct rte_eth_dev *dev)
10370 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10371 struct i40e_dcbx_config dcb_cfg;
10372 uint8_t tc_map = 0;
10375 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10376 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10380 if (pf->vf_num != 0)
10381 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10383 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10385 PMD_INIT_LOG(ERR, "invalid dcb config");
10388 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10390 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10398 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10399 struct rte_eth_dcb_info *dcb_info)
10401 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10402 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10403 struct i40e_vsi *vsi = pf->main_vsi;
10404 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10405 uint16_t bsf, tc_mapping;
10408 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10409 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10411 dcb_info->nb_tcs = 1;
10412 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10413 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10414 for (i = 0; i < dcb_info->nb_tcs; i++)
10415 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10417 /* get queue mapping if vmdq is disabled */
10418 if (!pf->nb_cfg_vmdq_vsi) {
10419 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10420 if (!(vsi->enabled_tc & (1 << i)))
10422 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10423 dcb_info->tc_queue.tc_rxq[j][i].base =
10424 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10425 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10426 dcb_info->tc_queue.tc_txq[j][i].base =
10427 dcb_info->tc_queue.tc_rxq[j][i].base;
10428 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10429 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10430 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10431 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10432 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10437 /* get queue mapping if vmdq is enabled */
10439 vsi = pf->vmdq[j].vsi;
10440 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10441 if (!(vsi->enabled_tc & (1 << i)))
10443 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10444 dcb_info->tc_queue.tc_rxq[j][i].base =
10445 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10446 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10447 dcb_info->tc_queue.tc_txq[j][i].base =
10448 dcb_info->tc_queue.tc_rxq[j][i].base;
10449 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10450 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10451 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10452 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10453 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10456 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10461 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10463 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10464 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10465 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10466 uint16_t interval =
10467 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10468 uint16_t msix_intr;
10470 msix_intr = intr_handle->intr_vec[queue_id];
10471 if (msix_intr == I40E_MISC_VEC_ID)
10472 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10473 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10474 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10475 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10477 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10480 I40E_PFINT_DYN_CTLN(msix_intr -
10481 I40E_RX_VEC_START),
10482 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10483 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10484 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10486 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10488 I40E_WRITE_FLUSH(hw);
10489 rte_intr_enable(&pci_dev->intr_handle);
10495 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10497 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10498 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10499 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10500 uint16_t msix_intr;
10502 msix_intr = intr_handle->intr_vec[queue_id];
10503 if (msix_intr == I40E_MISC_VEC_ID)
10504 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10507 I40E_PFINT_DYN_CTLN(msix_intr -
10508 I40E_RX_VEC_START),
10510 I40E_WRITE_FLUSH(hw);
10515 static int i40e_get_regs(struct rte_eth_dev *dev,
10516 struct rte_dev_reg_info *regs)
10518 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10519 uint32_t *ptr_data = regs->data;
10520 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10521 const struct i40e_reg_info *reg_info;
10523 if (ptr_data == NULL) {
10524 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10525 regs->width = sizeof(uint32_t);
10529 /* The first few registers have to be read using AQ operations */
10531 while (i40e_regs_adminq[reg_idx].name) {
10532 reg_info = &i40e_regs_adminq[reg_idx++];
10533 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10535 arr_idx2 <= reg_info->count2;
10537 reg_offset = arr_idx * reg_info->stride1 +
10538 arr_idx2 * reg_info->stride2;
10539 reg_offset += reg_info->base_addr;
10540 ptr_data[reg_offset >> 2] =
10541 i40e_read_rx_ctl(hw, reg_offset);
10545 /* The remaining registers can be read using primitives */
10547 while (i40e_regs_others[reg_idx].name) {
10548 reg_info = &i40e_regs_others[reg_idx++];
10549 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10551 arr_idx2 <= reg_info->count2;
10553 reg_offset = arr_idx * reg_info->stride1 +
10554 arr_idx2 * reg_info->stride2;
10555 reg_offset += reg_info->base_addr;
10556 ptr_data[reg_offset >> 2] =
10557 I40E_READ_REG(hw, reg_offset);
10564 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10566 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10568 /* Convert word count to byte count */
10569 return hw->nvm.sr_size << 1;
10572 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10573 struct rte_dev_eeprom_info *eeprom)
10575 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10576 uint16_t *data = eeprom->data;
10577 uint16_t offset, length, cnt_words;
10580 offset = eeprom->offset >> 1;
10581 length = eeprom->length >> 1;
10582 cnt_words = length;
10584 if (offset > hw->nvm.sr_size ||
10585 offset + length > hw->nvm.sr_size) {
10586 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10590 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10592 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10593 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10594 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10601 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10602 struct ether_addr *mac_addr)
10604 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10606 if (!is_valid_assigned_ether_addr(mac_addr)) {
10607 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10611 /* Flags: 0x3 updates port address */
10612 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10616 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10618 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10619 struct rte_eth_dev_data *dev_data = pf->dev_data;
10620 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10623 /* check if mtu is within the allowed range */
10624 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10627 /* mtu setting is forbidden if port is start */
10628 if (dev_data->dev_started) {
10629 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10630 dev_data->port_id);
10634 if (frame_size > ETHER_MAX_LEN)
10635 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10637 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10639 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10644 /* Restore ethertype filter */
10646 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10648 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10649 struct i40e_ethertype_filter_list
10650 *ethertype_list = &pf->ethertype.ethertype_list;
10651 struct i40e_ethertype_filter *f;
10652 struct i40e_control_filter_stats stats;
10655 TAILQ_FOREACH(f, ethertype_list, rules) {
10657 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10658 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10659 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10660 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10661 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10663 memset(&stats, 0, sizeof(stats));
10664 i40e_aq_add_rem_control_packet_filter(hw,
10665 f->input.mac_addr.addr_bytes,
10666 f->input.ether_type,
10667 flags, pf->main_vsi->seid,
10668 f->queue, 1, &stats, NULL);
10670 PMD_DRV_LOG(INFO, "Ethertype filter:"
10671 " mac_etype_used = %u, etype_used = %u,"
10672 " mac_etype_free = %u, etype_free = %u",
10673 stats.mac_etype_used, stats.etype_used,
10674 stats.mac_etype_free, stats.etype_free);
10677 /* Restore tunnel filter */
10679 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10681 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10682 struct i40e_vsi *vsi;
10683 struct i40e_pf_vf *vf;
10684 struct i40e_tunnel_filter_list
10685 *tunnel_list = &pf->tunnel.tunnel_list;
10686 struct i40e_tunnel_filter *f;
10687 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10688 bool big_buffer = 0;
10690 TAILQ_FOREACH(f, tunnel_list, rules) {
10692 vsi = pf->main_vsi;
10694 vf = &pf->vfs[f->vf_id];
10697 memset(&cld_filter, 0, sizeof(cld_filter));
10698 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10699 (struct ether_addr *)&cld_filter.element.outer_mac);
10700 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10701 (struct ether_addr *)&cld_filter.element.inner_mac);
10702 cld_filter.element.inner_vlan = f->input.inner_vlan;
10703 cld_filter.element.flags = f->input.flags;
10704 cld_filter.element.tenant_id = f->input.tenant_id;
10705 cld_filter.element.queue_number = f->queue;
10706 rte_memcpy(cld_filter.general_fields,
10707 f->input.general_fields,
10708 sizeof(f->input.general_fields));
10710 if (((f->input.flags &
10711 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10712 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10714 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10715 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10717 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10718 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10722 i40e_aq_add_cloud_filters_big_buffer(hw,
10723 vsi->seid, &cld_filter, 1);
10725 i40e_aq_add_cloud_filters(hw, vsi->seid,
10726 &cld_filter.element, 1);
10731 i40e_filter_restore(struct i40e_pf *pf)
10733 i40e_ethertype_filter_restore(pf);
10734 i40e_tunnel_filter_restore(pf);
10735 i40e_fdir_filter_restore(pf);
10739 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10741 if (strcmp(dev->device->driver->name, drv->driver.name))
10748 is_i40e_supported(struct rte_eth_dev *dev)
10750 return is_device_supported(dev, &rte_i40e_pmd);
10753 /* Create a QinQ cloud filter
10755 * The Fortville NIC has limited resources for tunnel filters,
10756 * so we can only reuse existing filters.
10758 * In step 1 we define which Field Vector fields can be used for
10760 * As we do not have the inner tag defined as a field,
10761 * we have to define it first, by reusing one of L1 entries.
10763 * In step 2 we are replacing one of existing filter types with
10764 * a new one for QinQ.
10765 * As we reusing L1 and replacing L2, some of the default filter
10766 * types will disappear,which depends on L1 and L2 entries we reuse.
10768 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10770 * 1. Create L1 filter of outer vlan (12b) which will be in use
10771 * later when we define the cloud filter.
10772 * a. Valid_flags.replace_cloud = 0
10773 * b. Old_filter = 10 (Stag_Inner_Vlan)
10774 * c. New_filter = 0x10
10775 * d. TR bit = 0xff (optional, not used here)
10776 * e. Buffer – 2 entries:
10777 * i. Byte 0 = 8 (outer vlan FV index).
10779 * Byte 2-3 = 0x0fff
10780 * ii. Byte 0 = 37 (inner vlan FV index).
10782 * Byte 2-3 = 0x0fff
10785 * 2. Create cloud filter using two L1 filters entries: stag and
10786 * new filter(outer vlan+ inner vlan)
10787 * a. Valid_flags.replace_cloud = 1
10788 * b. Old_filter = 1 (instead of outer IP)
10789 * c. New_filter = 0x10
10790 * d. Buffer – 2 entries:
10791 * i. Byte 0 = 0x80 | 7 (valid | Stag).
10792 * Byte 1-3 = 0 (rsv)
10793 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10794 * Byte 9-11 = 0 (rsv)
10797 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10799 int ret = -ENOTSUP;
10800 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
10801 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
10802 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10805 memset(&filter_replace, 0,
10806 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10807 memset(&filter_replace_buf, 0,
10808 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10810 /* create L1 filter */
10811 filter_replace.old_filter_type =
10812 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10813 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10814 filter_replace.tr_bit = 0;
10816 /* Prepare the buffer, 2 entries */
10817 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10818 filter_replace_buf.data[0] |=
10819 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10820 /* Field Vector 12b mask */
10821 filter_replace_buf.data[2] = 0xff;
10822 filter_replace_buf.data[3] = 0x0f;
10823 filter_replace_buf.data[4] =
10824 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10825 filter_replace_buf.data[4] |=
10826 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10827 /* Field Vector 12b mask */
10828 filter_replace_buf.data[6] = 0xff;
10829 filter_replace_buf.data[7] = 0x0f;
10830 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10831 &filter_replace_buf);
10832 if (ret != I40E_SUCCESS)
10835 /* Apply the second L2 cloud filter */
10836 memset(&filter_replace, 0,
10837 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10838 memset(&filter_replace_buf, 0,
10839 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10841 /* create L2 filter, input for L2 filter will be L1 filter */
10842 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10843 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10844 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10846 /* Prepare the buffer, 2 entries */
10847 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10848 filter_replace_buf.data[0] |=
10849 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10850 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10851 filter_replace_buf.data[4] |=
10852 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10853 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10854 &filter_replace_buf);
10858 RTE_INIT(i40e_init_log);
10860 i40e_init_log(void)
10862 i40e_logtype_init = rte_log_register("pmd.i40e.init");
10863 if (i40e_logtype_init >= 0)
10864 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10865 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10866 if (i40e_logtype_driver >= 0)
10867 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);