1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_eth_ctrl.h>
28 #include <rte_tailq.h>
29 #include <rte_hash_crc.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
45 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
49 #define I40E_CLEAR_PXE_WAIT_MS 200
51 /* Maximun number of capability elements */
52 #define I40E_MAX_CAP_ELE_NUM 128
54 /* Wait count and interval */
55 #define I40E_CHK_Q_ENA_COUNT 1000
56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
58 /* Maximun number of VSI */
59 #define I40E_MAX_NUM_VSIS (384UL)
61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
63 /* Flow control default timer */
64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
66 /* Flow control enable fwd bit */
67 #define I40E_PRTMAC_FWD_CTRL 0x00000001
69 /* Receive Packet Buffer size */
70 #define I40E_RXPBSIZE (968 * 1024)
73 #define I40E_KILOSHIFT 10
75 /* Flow control default high water */
76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Flow control default low water */
79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Receive Average Packet Size in Byte*/
82 #define I40E_PACKET_AVERAGE_SIZE 128
84 /* Mask of PF interrupt causes */
85 #define I40E_PFINT_ICR0_ENA_MASK ( \
86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_GRST_MASK | \
89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 /* Additional timesync values. */
110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
113 #define I40E_PRTTSYN_TSYNENA 0x80000000
114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
118 * Below are values for writing un-exposed registers suggested
121 /* Destination MAC address */
122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
123 /* Source MAC address */
124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
129 /* Single VLAN tag in the inner L2 header */
130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
131 /* Source IPv4 address */
132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
133 /* Destination IPv4 address */
134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
135 /* Source IPv4 address for X722 */
136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
137 /* Destination IPv4 address for X722 */
138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
139 /* IPv4 Protocol for X722 */
140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
141 /* IPv4 Time to Live for X722 */
142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
143 /* IPv4 Type of Service (TOS) */
144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
147 /* IPv4 Time to Live */
148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
149 /* Source IPv6 address */
150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
151 /* Destination IPv6 address */
152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
153 /* IPv6 Traffic Class (TC) */
154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
155 /* IPv6 Next Header */
156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
161 /* Destination L4 port */
162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
163 /* SCTP verification tag */
164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
167 /* Source port of tunneling UDP */
168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
169 /* Destination port of tunneling UDP */
170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
171 /* UDP Tunneling ID, NVGRE/GRE key */
172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
173 /* Last ether type */
174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
175 /* Tunneling outer destination IPv4 address */
176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
177 /* Tunneling outer destination IPv6 address */
178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
179 /* 1st word of flex payload */
180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
181 /* 2nd word of flex payload */
182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
183 /* 3rd word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
185 /* 4th word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
187 /* 5th word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
189 /* 6th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
191 /* 7th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
193 /* 8th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
195 /* all 8 words flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
199 #define I40E_TRANSLATE_INSET 0
200 #define I40E_TRANSLATE_REG 1
202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
209 /* PCI offset for querying capability */
210 #define PCI_DEV_CAP_REG 0xA4
211 /* PCI offset for enabling/disabling Extended Tag */
212 #define PCI_DEV_CTRL_REG 0xA8
213 /* Bit mask of Extended Tag capability */
214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
215 /* Bit shift of Extended Tag enable/disable */
216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
217 /* Bit mask of Extended Tag enable/disable */
218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
222 static int i40e_dev_configure(struct rte_eth_dev *dev);
223 static int i40e_dev_start(struct rte_eth_dev *dev);
224 static void i40e_dev_stop(struct rte_eth_dev *dev);
225 static void i40e_dev_close(struct rte_eth_dev *dev);
226 static int i40e_dev_reset(struct rte_eth_dev *dev);
227 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
228 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
229 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
230 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
234 struct rte_eth_stats *stats);
235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
236 struct rte_eth_xstat *xstats, unsigned n);
237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
238 struct rte_eth_xstat_name *xstats_names,
240 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
241 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
245 static int i40e_fw_version_get(struct rte_eth_dev *dev,
246 char *fw_version, size_t fw_size);
247 static void i40e_dev_info_get(struct rte_eth_dev *dev,
248 struct rte_eth_dev_info *dev_info);
249 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
252 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
253 enum rte_vlan_type vlan_type,
255 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
256 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
259 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
260 static int i40e_dev_led_on(struct rte_eth_dev *dev);
261 static int i40e_dev_led_off(struct rte_eth_dev *dev);
262 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
263 struct rte_eth_fc_conf *fc_conf);
264 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
265 struct rte_eth_fc_conf *fc_conf);
266 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
267 struct rte_eth_pfc_conf *pfc_conf);
268 static int i40e_macaddr_add(struct rte_eth_dev *dev,
269 struct ether_addr *mac_addr,
272 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
273 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
276 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
277 struct rte_eth_rss_reta_entry64 *reta_conf,
280 static int i40e_get_cap(struct i40e_hw *hw);
281 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
282 static int i40e_pf_setup(struct i40e_pf *pf);
283 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
284 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
285 static int i40e_dcb_setup(struct rte_eth_dev *dev);
286 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
287 bool offset_loaded, uint64_t *offset, uint64_t *stat);
288 static void i40e_stat_update_48(struct i40e_hw *hw,
294 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
295 static void i40e_dev_interrupt_handler(void *param);
296 static void i40e_dev_alarm_handler(void *param);
297 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
298 uint32_t base, uint32_t num);
299 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
300 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
302 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
304 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
305 static int i40e_veb_release(struct i40e_veb *veb);
306 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
307 struct i40e_vsi *vsi);
308 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
309 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
310 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
311 struct i40e_macvlan_filter *mv_f,
314 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
315 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
316 struct rte_eth_rss_conf *rss_conf);
317 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
318 struct rte_eth_rss_conf *rss_conf);
319 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
320 struct rte_eth_udp_tunnel *udp_tunnel);
321 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
322 struct rte_eth_udp_tunnel *udp_tunnel);
323 static void i40e_filter_input_set_init(struct i40e_pf *pf);
324 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
328 enum rte_filter_type filter_type,
329 enum rte_filter_op filter_op,
331 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
332 struct rte_eth_dcb_info *dcb_info);
333 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
334 static void i40e_configure_registers(struct i40e_hw *hw);
335 static void i40e_hw_init(struct rte_eth_dev *dev);
336 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
337 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
343 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
344 struct rte_eth_mirror_conf *mirror_conf,
345 uint8_t sw_id, uint8_t on);
346 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
348 static int i40e_timesync_enable(struct rte_eth_dev *dev);
349 static int i40e_timesync_disable(struct rte_eth_dev *dev);
350 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
351 struct timespec *timestamp,
353 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
354 struct timespec *timestamp);
355 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
357 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
359 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
360 struct timespec *timestamp);
361 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
362 const struct timespec *timestamp);
364 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
366 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
369 static int i40e_get_regs(struct rte_eth_dev *dev,
370 struct rte_dev_reg_info *regs);
372 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
374 static int i40e_get_eeprom(struct rte_eth_dev *dev,
375 struct rte_dev_eeprom_info *eeprom);
377 static int i40e_get_module_info(struct rte_eth_dev *dev,
378 struct rte_eth_dev_module_info *modinfo);
379 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
380 struct rte_dev_eeprom_info *info);
382 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
383 struct ether_addr *mac_addr);
385 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
387 static int i40e_ethertype_filter_convert(
388 const struct rte_eth_ethertype_filter *input,
389 struct i40e_ethertype_filter *filter);
390 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
391 struct i40e_ethertype_filter *filter);
393 static int i40e_tunnel_filter_convert(
394 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
395 struct i40e_tunnel_filter *tunnel_filter);
396 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
397 struct i40e_tunnel_filter *tunnel_filter);
398 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
400 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
401 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
402 static void i40e_filter_restore(struct i40e_pf *pf);
403 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
405 int i40e_logtype_init;
406 int i40e_logtype_driver;
408 static const char *const valid_keys[] = {
409 ETH_I40E_FLOATING_VEB_ARG,
410 ETH_I40E_FLOATING_VEB_LIST_ARG,
411 ETH_I40E_SUPPORT_MULTI_DRIVER,
412 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
413 ETH_I40E_USE_LATEST_VEC,
416 static const struct rte_pci_id pci_id_i40e_map[] = {
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
437 { .vendor_id = 0, /* sentinel */ },
440 static const struct eth_dev_ops i40e_eth_dev_ops = {
441 .dev_configure = i40e_dev_configure,
442 .dev_start = i40e_dev_start,
443 .dev_stop = i40e_dev_stop,
444 .dev_close = i40e_dev_close,
445 .dev_reset = i40e_dev_reset,
446 .promiscuous_enable = i40e_dev_promiscuous_enable,
447 .promiscuous_disable = i40e_dev_promiscuous_disable,
448 .allmulticast_enable = i40e_dev_allmulticast_enable,
449 .allmulticast_disable = i40e_dev_allmulticast_disable,
450 .dev_set_link_up = i40e_dev_set_link_up,
451 .dev_set_link_down = i40e_dev_set_link_down,
452 .link_update = i40e_dev_link_update,
453 .stats_get = i40e_dev_stats_get,
454 .xstats_get = i40e_dev_xstats_get,
455 .xstats_get_names = i40e_dev_xstats_get_names,
456 .stats_reset = i40e_dev_stats_reset,
457 .xstats_reset = i40e_dev_stats_reset,
458 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
459 .fw_version_get = i40e_fw_version_get,
460 .dev_infos_get = i40e_dev_info_get,
461 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
462 .vlan_filter_set = i40e_vlan_filter_set,
463 .vlan_tpid_set = i40e_vlan_tpid_set,
464 .vlan_offload_set = i40e_vlan_offload_set,
465 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
466 .vlan_pvid_set = i40e_vlan_pvid_set,
467 .rx_queue_start = i40e_dev_rx_queue_start,
468 .rx_queue_stop = i40e_dev_rx_queue_stop,
469 .tx_queue_start = i40e_dev_tx_queue_start,
470 .tx_queue_stop = i40e_dev_tx_queue_stop,
471 .rx_queue_setup = i40e_dev_rx_queue_setup,
472 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
473 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
474 .rx_queue_release = i40e_dev_rx_queue_release,
475 .rx_queue_count = i40e_dev_rx_queue_count,
476 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
477 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
478 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
479 .tx_queue_setup = i40e_dev_tx_queue_setup,
480 .tx_queue_release = i40e_dev_tx_queue_release,
481 .dev_led_on = i40e_dev_led_on,
482 .dev_led_off = i40e_dev_led_off,
483 .flow_ctrl_get = i40e_flow_ctrl_get,
484 .flow_ctrl_set = i40e_flow_ctrl_set,
485 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
486 .mac_addr_add = i40e_macaddr_add,
487 .mac_addr_remove = i40e_macaddr_remove,
488 .reta_update = i40e_dev_rss_reta_update,
489 .reta_query = i40e_dev_rss_reta_query,
490 .rss_hash_update = i40e_dev_rss_hash_update,
491 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
492 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
493 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
494 .filter_ctrl = i40e_dev_filter_ctrl,
495 .rxq_info_get = i40e_rxq_info_get,
496 .txq_info_get = i40e_txq_info_get,
497 .mirror_rule_set = i40e_mirror_rule_set,
498 .mirror_rule_reset = i40e_mirror_rule_reset,
499 .timesync_enable = i40e_timesync_enable,
500 .timesync_disable = i40e_timesync_disable,
501 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
502 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
503 .get_dcb_info = i40e_dev_get_dcb_info,
504 .timesync_adjust_time = i40e_timesync_adjust_time,
505 .timesync_read_time = i40e_timesync_read_time,
506 .timesync_write_time = i40e_timesync_write_time,
507 .get_reg = i40e_get_regs,
508 .get_eeprom_length = i40e_get_eeprom_length,
509 .get_eeprom = i40e_get_eeprom,
510 .get_module_info = i40e_get_module_info,
511 .get_module_eeprom = i40e_get_module_eeprom,
512 .mac_addr_set = i40e_set_default_mac_addr,
513 .mtu_set = i40e_dev_mtu_set,
514 .tm_ops_get = i40e_tm_ops_get,
517 /* store statistics names and its offset in stats structure */
518 struct rte_i40e_xstats_name_off {
519 char name[RTE_ETH_XSTATS_NAME_SIZE];
523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
524 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
525 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
526 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
527 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
528 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
529 rx_unknown_protocol)},
530 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
531 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
532 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
533 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
537 sizeof(rte_i40e_stats_strings[0]))
539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
540 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
541 tx_dropped_link_down)},
542 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
543 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
545 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
546 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
548 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
550 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
552 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
553 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
554 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
555 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
556 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
557 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
559 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
571 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
573 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
574 mac_short_packet_dropped)},
575 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
577 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
578 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
579 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
581 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
583 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
591 {"rx_flow_director_atr_match_packets",
592 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
593 {"rx_flow_director_sb_match_packets",
594 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
595 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
597 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
599 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
601 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
606 sizeof(rte_i40e_hw_port_strings[0]))
608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
609 {"xon_packets", offsetof(struct i40e_hw_port_stats,
611 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
616 sizeof(rte_i40e_rxq_prio_strings[0]))
618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
619 {"xon_packets", offsetof(struct i40e_hw_port_stats,
621 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
623 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
624 priority_xon_2_xoff)},
627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
628 sizeof(rte_i40e_txq_prio_strings[0]))
631 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
632 struct rte_pci_device *pci_dev)
634 char name[RTE_ETH_NAME_MAX_LEN];
635 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
638 if (pci_dev->device.devargs) {
639 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
645 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
646 sizeof(struct i40e_adapter),
647 eth_dev_pci_specific_init, pci_dev,
648 eth_i40e_dev_init, NULL);
650 if (retval || eth_da.nb_representor_ports < 1)
653 /* probe VF representor ports */
654 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
655 pci_dev->device.name);
657 if (pf_ethdev == NULL)
660 for (i = 0; i < eth_da.nb_representor_ports; i++) {
661 struct i40e_vf_representor representor = {
662 .vf_id = eth_da.representor_ports[i],
663 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
664 pf_ethdev->data->dev_private)->switch_domain_id,
665 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
666 pf_ethdev->data->dev_private)
669 /* representor port net_bdf_port */
670 snprintf(name, sizeof(name), "net_%s_representor_%d",
671 pci_dev->device.name, eth_da.representor_ports[i]);
673 retval = rte_eth_dev_create(&pci_dev->device, name,
674 sizeof(struct i40e_vf_representor), NULL, NULL,
675 i40e_vf_representor_init, &representor);
678 PMD_DRV_LOG(ERR, "failed to create i40e vf "
679 "representor %s.", name);
685 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
687 struct rte_eth_dev *ethdev;
689 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
694 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
695 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
697 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
700 static struct rte_pci_driver rte_i40e_pmd = {
701 .id_table = pci_id_i40e_map,
702 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
703 RTE_PCI_DRV_IOVA_AS_VA,
704 .probe = eth_i40e_pci_probe,
705 .remove = eth_i40e_pci_remove,
709 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
712 uint32_t ori_reg_val;
713 struct rte_eth_dev *dev;
715 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
716 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
717 i40e_write_rx_ctl(hw, reg_addr, reg_val);
718 if (ori_reg_val != reg_val)
720 "i40e device %s changed global register [0x%08x]."
721 " original: 0x%08x, new: 0x%08x",
722 dev->device->name, reg_addr, ori_reg_val, reg_val);
725 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
726 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
727 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
729 #ifndef I40E_GLQF_ORT
730 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
732 #ifndef I40E_GLQF_PIT
733 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
735 #ifndef I40E_GLQF_L3_MAP
736 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
739 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
742 * Initialize registers for parsing packet type of QinQ
743 * This should be removed from code once proper
744 * configuration API is added to avoid configuration conflicts
745 * between ports of the same device.
747 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
748 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
751 static inline void i40e_config_automask(struct i40e_pf *pf)
753 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
756 /* INTENA flag is not auto-cleared for interrupt */
757 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
758 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
759 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
761 /* If support multi-driver, PF will use INT0. */
762 if (!pf->support_multi_driver)
763 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
765 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
768 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
771 * Add a ethertype filter to drop all flow control frames transmitted
775 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
777 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
778 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
779 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
780 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
783 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
784 I40E_FLOW_CONTROL_ETHERTYPE, flags,
785 pf->main_vsi_seid, 0,
789 "Failed to add filter to drop flow control frames from VSIs.");
793 floating_veb_list_handler(__rte_unused const char *key,
794 const char *floating_veb_value,
798 unsigned int count = 0;
801 bool *vf_floating_veb = opaque;
803 while (isblank(*floating_veb_value))
804 floating_veb_value++;
806 /* Reset floating VEB configuration for VFs */
807 for (idx = 0; idx < I40E_MAX_VF; idx++)
808 vf_floating_veb[idx] = false;
812 while (isblank(*floating_veb_value))
813 floating_veb_value++;
814 if (*floating_veb_value == '\0')
817 idx = strtoul(floating_veb_value, &end, 10);
818 if (errno || end == NULL)
820 while (isblank(*end))
824 } else if ((*end == ';') || (*end == '\0')) {
826 if (min == I40E_MAX_VF)
828 if (max >= I40E_MAX_VF)
829 max = I40E_MAX_VF - 1;
830 for (idx = min; idx <= max; idx++) {
831 vf_floating_veb[idx] = true;
838 floating_veb_value = end + 1;
839 } while (*end != '\0');
848 config_vf_floating_veb(struct rte_devargs *devargs,
849 uint16_t floating_veb,
850 bool *vf_floating_veb)
852 struct rte_kvargs *kvlist;
854 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
858 /* All the VFs attach to the floating VEB by default
859 * when the floating VEB is enabled.
861 for (i = 0; i < I40E_MAX_VF; i++)
862 vf_floating_veb[i] = true;
867 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
871 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
872 rte_kvargs_free(kvlist);
875 /* When the floating_veb_list parameter exists, all the VFs
876 * will attach to the legacy VEB firstly, then configure VFs
877 * to the floating VEB according to the floating_veb_list.
879 if (rte_kvargs_process(kvlist, floating_veb_list,
880 floating_veb_list_handler,
881 vf_floating_veb) < 0) {
882 rte_kvargs_free(kvlist);
885 rte_kvargs_free(kvlist);
889 i40e_check_floating_handler(__rte_unused const char *key,
891 __rte_unused void *opaque)
893 if (strcmp(value, "1"))
900 is_floating_veb_supported(struct rte_devargs *devargs)
902 struct rte_kvargs *kvlist;
903 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
908 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
912 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
913 rte_kvargs_free(kvlist);
916 /* Floating VEB is enabled when there's key-value:
917 * enable_floating_veb=1
919 if (rte_kvargs_process(kvlist, floating_veb_key,
920 i40e_check_floating_handler, NULL) < 0) {
921 rte_kvargs_free(kvlist);
924 rte_kvargs_free(kvlist);
930 config_floating_veb(struct rte_eth_dev *dev)
932 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
933 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
934 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
936 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
938 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
940 is_floating_veb_supported(pci_dev->device.devargs);
941 config_vf_floating_veb(pci_dev->device.devargs,
943 pf->floating_veb_list);
945 pf->floating_veb = false;
949 #define I40E_L2_TAGS_S_TAG_SHIFT 1
950 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
953 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
956 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
957 char ethertype_hash_name[RTE_HASH_NAMESIZE];
960 struct rte_hash_parameters ethertype_hash_params = {
961 .name = ethertype_hash_name,
962 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
963 .key_len = sizeof(struct i40e_ethertype_filter_input),
964 .hash_func = rte_hash_crc,
965 .hash_func_init_val = 0,
966 .socket_id = rte_socket_id(),
969 /* Initialize ethertype filter rule list and hash */
970 TAILQ_INIT(ðertype_rule->ethertype_list);
971 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
972 "ethertype_%s", dev->device->name);
973 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
974 if (!ethertype_rule->hash_table) {
975 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
978 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
979 sizeof(struct i40e_ethertype_filter *) *
980 I40E_MAX_ETHERTYPE_FILTER_NUM,
982 if (!ethertype_rule->hash_map) {
984 "Failed to allocate memory for ethertype hash map!");
986 goto err_ethertype_hash_map_alloc;
991 err_ethertype_hash_map_alloc:
992 rte_hash_free(ethertype_rule->hash_table);
998 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1000 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1002 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1005 struct rte_hash_parameters tunnel_hash_params = {
1006 .name = tunnel_hash_name,
1007 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1008 .key_len = sizeof(struct i40e_tunnel_filter_input),
1009 .hash_func = rte_hash_crc,
1010 .hash_func_init_val = 0,
1011 .socket_id = rte_socket_id(),
1014 /* Initialize tunnel filter rule list and hash */
1015 TAILQ_INIT(&tunnel_rule->tunnel_list);
1016 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1017 "tunnel_%s", dev->device->name);
1018 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1019 if (!tunnel_rule->hash_table) {
1020 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1023 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1024 sizeof(struct i40e_tunnel_filter *) *
1025 I40E_MAX_TUNNEL_FILTER_NUM,
1027 if (!tunnel_rule->hash_map) {
1029 "Failed to allocate memory for tunnel hash map!");
1031 goto err_tunnel_hash_map_alloc;
1036 err_tunnel_hash_map_alloc:
1037 rte_hash_free(tunnel_rule->hash_table);
1043 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1045 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1046 struct i40e_fdir_info *fdir_info = &pf->fdir;
1047 char fdir_hash_name[RTE_HASH_NAMESIZE];
1050 struct rte_hash_parameters fdir_hash_params = {
1051 .name = fdir_hash_name,
1052 .entries = I40E_MAX_FDIR_FILTER_NUM,
1053 .key_len = sizeof(struct i40e_fdir_input),
1054 .hash_func = rte_hash_crc,
1055 .hash_func_init_val = 0,
1056 .socket_id = rte_socket_id(),
1059 /* Initialize flow director filter rule list and hash */
1060 TAILQ_INIT(&fdir_info->fdir_list);
1061 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1062 "fdir_%s", dev->device->name);
1063 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1064 if (!fdir_info->hash_table) {
1065 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1068 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1069 sizeof(struct i40e_fdir_filter *) *
1070 I40E_MAX_FDIR_FILTER_NUM,
1072 if (!fdir_info->hash_map) {
1074 "Failed to allocate memory for fdir hash map!");
1076 goto err_fdir_hash_map_alloc;
1080 err_fdir_hash_map_alloc:
1081 rte_hash_free(fdir_info->hash_table);
1087 i40e_init_customized_info(struct i40e_pf *pf)
1091 /* Initialize customized pctype */
1092 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1093 pf->customized_pctype[i].index = i;
1094 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1095 pf->customized_pctype[i].valid = false;
1098 pf->gtp_support = false;
1102 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1104 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1105 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1106 struct i40e_queue_regions *info = &pf->queue_region;
1109 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1110 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1112 memset(info, 0, sizeof(struct i40e_queue_regions));
1116 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1121 unsigned long support_multi_driver;
1124 pf = (struct i40e_pf *)opaque;
1127 support_multi_driver = strtoul(value, &end, 10);
1128 if (errno != 0 || end == value || *end != 0) {
1129 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1133 if (support_multi_driver == 1 || support_multi_driver == 0)
1134 pf->support_multi_driver = (bool)support_multi_driver;
1136 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1137 "enable global configuration by default."
1138 ETH_I40E_SUPPORT_MULTI_DRIVER);
1143 i40e_support_multi_driver(struct rte_eth_dev *dev)
1145 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1146 struct rte_kvargs *kvlist;
1149 /* Enable global configuration by default */
1150 pf->support_multi_driver = false;
1152 if (!dev->device->devargs)
1155 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1159 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1160 if (!kvargs_count) {
1161 rte_kvargs_free(kvlist);
1165 if (kvargs_count > 1)
1166 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1167 "the first invalid or last valid one is used !",
1168 ETH_I40E_SUPPORT_MULTI_DRIVER);
1170 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1171 i40e_parse_multi_drv_handler, pf) < 0) {
1172 rte_kvargs_free(kvlist);
1176 rte_kvargs_free(kvlist);
1181 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1182 uint32_t reg_addr, uint64_t reg_val,
1183 struct i40e_asq_cmd_details *cmd_details)
1185 uint64_t ori_reg_val;
1186 struct rte_eth_dev *dev;
1189 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1190 if (ret != I40E_SUCCESS) {
1192 "Fail to debug read from 0x%08x",
1196 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1198 if (ori_reg_val != reg_val)
1199 PMD_DRV_LOG(WARNING,
1200 "i40e device %s changed global register [0x%08x]."
1201 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1202 dev->device->name, reg_addr, ori_reg_val, reg_val);
1204 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1208 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1212 struct i40e_adapter *ad;
1215 ad = (struct i40e_adapter *)opaque;
1217 use_latest_vec = atoi(value);
1219 if (use_latest_vec != 0 && use_latest_vec != 1)
1220 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1222 ad->use_latest_vec = (uint8_t)use_latest_vec;
1228 i40e_use_latest_vec(struct rte_eth_dev *dev)
1230 struct i40e_adapter *ad =
1231 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1232 struct rte_kvargs *kvlist;
1235 ad->use_latest_vec = false;
1237 if (!dev->device->devargs)
1240 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1244 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1245 if (!kvargs_count) {
1246 rte_kvargs_free(kvlist);
1250 if (kvargs_count > 1)
1251 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1252 "the first invalid or last valid one is used !",
1253 ETH_I40E_USE_LATEST_VEC);
1255 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1256 i40e_parse_latest_vec_handler, ad) < 0) {
1257 rte_kvargs_free(kvlist);
1261 rte_kvargs_free(kvlist);
1265 #define I40E_ALARM_INTERVAL 50000 /* us */
1268 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1270 struct rte_pci_device *pci_dev;
1271 struct rte_intr_handle *intr_handle;
1272 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1273 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274 struct i40e_vsi *vsi;
1277 uint8_t aq_fail = 0;
1279 PMD_INIT_FUNC_TRACE();
1281 dev->dev_ops = &i40e_eth_dev_ops;
1282 dev->rx_pkt_burst = i40e_recv_pkts;
1283 dev->tx_pkt_burst = i40e_xmit_pkts;
1284 dev->tx_pkt_prepare = i40e_prep_pkts;
1286 /* for secondary processes, we don't initialise any further as primary
1287 * has already done this work. Only check we don't need a different
1289 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1290 i40e_set_rx_function(dev);
1291 i40e_set_tx_function(dev);
1294 i40e_set_default_ptype_table(dev);
1295 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1296 intr_handle = &pci_dev->intr_handle;
1298 rte_eth_copy_pci_info(dev, pci_dev);
1300 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1301 pf->adapter->eth_dev = dev;
1302 pf->dev_data = dev->data;
1304 hw->back = I40E_PF_TO_ADAPTER(pf);
1305 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1308 "Hardware is not available, as address is NULL");
1312 hw->vendor_id = pci_dev->id.vendor_id;
1313 hw->device_id = pci_dev->id.device_id;
1314 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1315 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1316 hw->bus.device = pci_dev->addr.devid;
1317 hw->bus.func = pci_dev->addr.function;
1318 hw->adapter_stopped = 0;
1321 * Switch Tag value should not be identical to either the First Tag
1322 * or Second Tag values. So set something other than common Ethertype
1323 * for internal switching.
1325 hw->switch_tag = 0xffff;
1327 /* Check if need to support multi-driver */
1328 i40e_support_multi_driver(dev);
1329 /* Check if users want the latest supported vec path */
1330 i40e_use_latest_vec(dev);
1332 /* Make sure all is clean before doing PF reset */
1335 /* Reset here to make sure all is clean for each PF */
1336 ret = i40e_pf_reset(hw);
1338 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1342 /* Initialize the shared code (base driver) */
1343 ret = i40e_init_shared_code(hw);
1345 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1349 /* Initialize the parameters for adminq */
1350 i40e_init_adminq_parameter(hw);
1351 ret = i40e_init_adminq(hw);
1352 if (ret != I40E_SUCCESS) {
1353 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1356 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1357 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1358 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1359 ((hw->nvm.version >> 12) & 0xf),
1360 ((hw->nvm.version >> 4) & 0xff),
1361 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1363 /* Initialize the hardware */
1366 i40e_config_automask(pf);
1368 i40e_set_default_pctype_table(dev);
1371 * To work around the NVM issue, initialize registers
1372 * for packet type of QinQ by software.
1373 * It should be removed once issues are fixed in NVM.
1375 if (!pf->support_multi_driver)
1376 i40e_GLQF_reg_init(hw);
1378 /* Initialize the input set for filters (hash and fd) to default value */
1379 i40e_filter_input_set_init(pf);
1381 /* initialise the L3_MAP register */
1382 if (!pf->support_multi_driver) {
1383 ret = i40e_aq_debug_write_global_register(hw,
1384 I40E_GLQF_L3_MAP(40),
1387 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1390 "Global register 0x%08x is changed with 0x28",
1391 I40E_GLQF_L3_MAP(40));
1394 /* Need the special FW version to support floating VEB */
1395 config_floating_veb(dev);
1396 /* Clear PXE mode */
1397 i40e_clear_pxe_mode(hw);
1398 i40e_dev_sync_phy_type(hw);
1401 * On X710, performance number is far from the expectation on recent
1402 * firmware versions. The fix for this issue may not be integrated in
1403 * the following firmware version. So the workaround in software driver
1404 * is needed. It needs to modify the initial values of 3 internal only
1405 * registers. Note that the workaround can be removed when it is fixed
1406 * in firmware in the future.
1408 i40e_configure_registers(hw);
1410 /* Get hw capabilities */
1411 ret = i40e_get_cap(hw);
1412 if (ret != I40E_SUCCESS) {
1413 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1414 goto err_get_capabilities;
1417 /* Initialize parameters for PF */
1418 ret = i40e_pf_parameter_init(dev);
1420 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1421 goto err_parameter_init;
1424 /* Initialize the queue management */
1425 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1427 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1428 goto err_qp_pool_init;
1430 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1431 hw->func_caps.num_msix_vectors - 1);
1433 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1434 goto err_msix_pool_init;
1437 /* Initialize lan hmc */
1438 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1439 hw->func_caps.num_rx_qp, 0, 0);
1440 if (ret != I40E_SUCCESS) {
1441 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1442 goto err_init_lan_hmc;
1445 /* Configure lan hmc */
1446 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1447 if (ret != I40E_SUCCESS) {
1448 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1449 goto err_configure_lan_hmc;
1452 /* Get and check the mac address */
1453 i40e_get_mac_addr(hw, hw->mac.addr);
1454 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1455 PMD_INIT_LOG(ERR, "mac address is not valid");
1457 goto err_get_mac_addr;
1459 /* Copy the permanent MAC address */
1460 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1461 (struct ether_addr *) hw->mac.perm_addr);
1463 /* Disable flow control */
1464 hw->fc.requested_mode = I40E_FC_NONE;
1465 i40e_set_fc(hw, &aq_fail, TRUE);
1467 /* Set the global registers with default ether type value */
1468 if (!pf->support_multi_driver) {
1469 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1471 if (ret != I40E_SUCCESS) {
1473 "Failed to set the default outer "
1475 goto err_setup_pf_switch;
1479 /* PF setup, which includes VSI setup */
1480 ret = i40e_pf_setup(pf);
1482 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1483 goto err_setup_pf_switch;
1486 /* reset all stats of the device, including pf and main vsi */
1487 i40e_dev_stats_reset(dev);
1491 /* Disable double vlan by default */
1492 i40e_vsi_config_double_vlan(vsi, FALSE);
1494 /* Disable S-TAG identification when floating_veb is disabled */
1495 if (!pf->floating_veb) {
1496 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1497 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1498 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1499 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1503 if (!vsi->max_macaddrs)
1504 len = ETHER_ADDR_LEN;
1506 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1508 /* Should be after VSI initialized */
1509 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1510 if (!dev->data->mac_addrs) {
1512 "Failed to allocated memory for storing mac address");
1515 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1516 &dev->data->mac_addrs[0]);
1518 /* Init dcb to sw mode by default */
1519 ret = i40e_dcb_init_configure(dev, TRUE);
1520 if (ret != I40E_SUCCESS) {
1521 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1522 pf->flags &= ~I40E_FLAG_DCB;
1524 /* Update HW struct after DCB configuration */
1527 /* initialize pf host driver to setup SRIOV resource if applicable */
1528 i40e_pf_host_init(dev);
1530 /* register callback func to eal lib */
1531 rte_intr_callback_register(intr_handle,
1532 i40e_dev_interrupt_handler, dev);
1534 /* configure and enable device interrupt */
1535 i40e_pf_config_irq0(hw, TRUE);
1536 i40e_pf_enable_irq0(hw);
1538 /* enable uio intr after callback register */
1539 rte_intr_enable(intr_handle);
1541 /* By default disable flexible payload in global configuration */
1542 if (!pf->support_multi_driver)
1543 i40e_flex_payload_reg_set_default(hw);
1546 * Add an ethertype filter to drop all flow control frames transmitted
1547 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1550 i40e_add_tx_flow_control_drop_filter(pf);
1552 /* Set the max frame size to 0x2600 by default,
1553 * in case other drivers changed the default value.
1555 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1557 /* initialize mirror rule list */
1558 TAILQ_INIT(&pf->mirror_list);
1560 /* initialize Traffic Manager configuration */
1561 i40e_tm_conf_init(dev);
1563 /* Initialize customized information */
1564 i40e_init_customized_info(pf);
1566 ret = i40e_init_ethtype_filter_list(dev);
1568 goto err_init_ethtype_filter_list;
1569 ret = i40e_init_tunnel_filter_list(dev);
1571 goto err_init_tunnel_filter_list;
1572 ret = i40e_init_fdir_filter_list(dev);
1574 goto err_init_fdir_filter_list;
1576 /* initialize queue region configuration */
1577 i40e_init_queue_region_conf(dev);
1579 /* initialize rss configuration from rte_flow */
1580 memset(&pf->rss_info, 0,
1581 sizeof(struct i40e_rte_flow_rss_conf));
1585 err_init_fdir_filter_list:
1586 rte_free(pf->tunnel.hash_table);
1587 rte_free(pf->tunnel.hash_map);
1588 err_init_tunnel_filter_list:
1589 rte_free(pf->ethertype.hash_table);
1590 rte_free(pf->ethertype.hash_map);
1591 err_init_ethtype_filter_list:
1592 rte_free(dev->data->mac_addrs);
1594 i40e_vsi_release(pf->main_vsi);
1595 err_setup_pf_switch:
1597 err_configure_lan_hmc:
1598 (void)i40e_shutdown_lan_hmc(hw);
1600 i40e_res_pool_destroy(&pf->msix_pool);
1602 i40e_res_pool_destroy(&pf->qp_pool);
1605 err_get_capabilities:
1606 (void)i40e_shutdown_adminq(hw);
1612 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1614 struct i40e_ethertype_filter *p_ethertype;
1615 struct i40e_ethertype_rule *ethertype_rule;
1617 ethertype_rule = &pf->ethertype;
1618 /* Remove all ethertype filter rules and hash */
1619 if (ethertype_rule->hash_map)
1620 rte_free(ethertype_rule->hash_map);
1621 if (ethertype_rule->hash_table)
1622 rte_hash_free(ethertype_rule->hash_table);
1624 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1625 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1626 p_ethertype, rules);
1627 rte_free(p_ethertype);
1632 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1634 struct i40e_tunnel_filter *p_tunnel;
1635 struct i40e_tunnel_rule *tunnel_rule;
1637 tunnel_rule = &pf->tunnel;
1638 /* Remove all tunnel director rules and hash */
1639 if (tunnel_rule->hash_map)
1640 rte_free(tunnel_rule->hash_map);
1641 if (tunnel_rule->hash_table)
1642 rte_hash_free(tunnel_rule->hash_table);
1644 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1645 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1651 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1653 struct i40e_fdir_filter *p_fdir;
1654 struct i40e_fdir_info *fdir_info;
1656 fdir_info = &pf->fdir;
1657 /* Remove all flow director rules and hash */
1658 if (fdir_info->hash_map)
1659 rte_free(fdir_info->hash_map);
1660 if (fdir_info->hash_table)
1661 rte_hash_free(fdir_info->hash_table);
1663 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1664 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1669 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1672 * Disable by default flexible payload
1673 * for corresponding L2/L3/L4 layers.
1675 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1676 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1677 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1681 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1684 struct rte_pci_device *pci_dev;
1685 struct rte_intr_handle *intr_handle;
1687 struct i40e_filter_control_settings settings;
1688 struct rte_flow *p_flow;
1690 uint8_t aq_fail = 0;
1693 PMD_INIT_FUNC_TRACE();
1695 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1698 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1699 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1700 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1701 intr_handle = &pci_dev->intr_handle;
1703 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1705 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1707 if (hw->adapter_stopped == 0)
1708 i40e_dev_close(dev);
1710 dev->dev_ops = NULL;
1711 dev->rx_pkt_burst = NULL;
1712 dev->tx_pkt_burst = NULL;
1714 /* Clear PXE mode */
1715 i40e_clear_pxe_mode(hw);
1717 /* Unconfigure filter control */
1718 memset(&settings, 0, sizeof(settings));
1719 ret = i40e_set_filter_control(hw, &settings);
1721 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1724 /* Disable flow control */
1725 hw->fc.requested_mode = I40E_FC_NONE;
1726 i40e_set_fc(hw, &aq_fail, TRUE);
1728 /* uninitialize pf host driver */
1729 i40e_pf_host_uninit(dev);
1731 rte_free(dev->data->mac_addrs);
1732 dev->data->mac_addrs = NULL;
1734 /* disable uio intr before callback unregister */
1735 rte_intr_disable(intr_handle);
1737 /* unregister callback func to eal lib */
1739 ret = rte_intr_callback_unregister(intr_handle,
1740 i40e_dev_interrupt_handler, dev);
1743 } else if (ret != -EAGAIN) {
1745 "intr callback unregister failed: %d",
1749 i40e_msec_delay(500);
1750 } while (retries++ < 5);
1752 i40e_rm_ethtype_filter_list(pf);
1753 i40e_rm_tunnel_filter_list(pf);
1754 i40e_rm_fdir_filter_list(pf);
1756 /* Remove all flows */
1757 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1758 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1762 /* Remove all Traffic Manager configuration */
1763 i40e_tm_conf_uninit(dev);
1769 i40e_dev_configure(struct rte_eth_dev *dev)
1771 struct i40e_adapter *ad =
1772 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1773 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1774 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1778 ret = i40e_dev_sync_phy_type(hw);
1782 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1783 * bulk allocation or vector Rx preconditions we will reset it.
1785 ad->rx_bulk_alloc_allowed = true;
1786 ad->rx_vec_allowed = true;
1787 ad->tx_simple_allowed = true;
1788 ad->tx_vec_allowed = true;
1790 /* Only legacy filter API needs the following fdir config. So when the
1791 * legacy filter API is deprecated, the following codes should also be
1794 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1795 ret = i40e_fdir_setup(pf);
1796 if (ret != I40E_SUCCESS) {
1797 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1800 ret = i40e_fdir_configure(dev);
1802 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1806 i40e_fdir_teardown(pf);
1808 ret = i40e_dev_init_vlan(dev);
1813 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1814 * RSS setting have different requirements.
1815 * General PMD driver call sequence are NIC init, configure,
1816 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1817 * will try to lookup the VSI that specific queue belongs to if VMDQ
1818 * applicable. So, VMDQ setting has to be done before
1819 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1820 * For RSS setting, it will try to calculate actual configured RX queue
1821 * number, which will be available after rx_queue_setup(). dev_start()
1822 * function is good to place RSS setup.
1824 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1825 ret = i40e_vmdq_setup(dev);
1830 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1831 ret = i40e_dcb_setup(dev);
1833 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1838 TAILQ_INIT(&pf->flow_list);
1843 /* need to release vmdq resource if exists */
1844 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1845 i40e_vsi_release(pf->vmdq[i].vsi);
1846 pf->vmdq[i].vsi = NULL;
1851 /* Need to release fdir resource if exists.
1852 * Only legacy filter API needs the following fdir config. So when the
1853 * legacy filter API is deprecated, the following code should also be
1856 i40e_fdir_teardown(pf);
1861 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1863 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1864 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1865 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1866 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1867 uint16_t msix_vect = vsi->msix_intr;
1870 for (i = 0; i < vsi->nb_qps; i++) {
1871 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1872 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1876 if (vsi->type != I40E_VSI_SRIOV) {
1877 if (!rte_intr_allow_others(intr_handle)) {
1878 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1879 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1881 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1884 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1885 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1887 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1892 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1893 vsi->user_param + (msix_vect - 1);
1895 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1896 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1898 I40E_WRITE_FLUSH(hw);
1902 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1903 int base_queue, int nb_queue,
1908 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1909 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1911 /* Bind all RX queues to allocated MSIX interrupt */
1912 for (i = 0; i < nb_queue; i++) {
1913 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1914 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1915 ((base_queue + i + 1) <<
1916 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1917 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1918 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1920 if (i == nb_queue - 1)
1921 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1922 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1925 /* Write first RX queue to Link list register as the head element */
1926 if (vsi->type != I40E_VSI_SRIOV) {
1928 i40e_calc_itr_interval(1, pf->support_multi_driver);
1930 if (msix_vect == I40E_MISC_VEC_ID) {
1931 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1933 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1935 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1937 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1940 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1942 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1944 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1946 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1953 if (msix_vect == I40E_MISC_VEC_ID) {
1955 I40E_VPINT_LNKLST0(vsi->user_param),
1957 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1959 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1961 /* num_msix_vectors_vf needs to minus irq0 */
1962 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1963 vsi->user_param + (msix_vect - 1);
1965 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1967 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1969 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1973 I40E_WRITE_FLUSH(hw);
1977 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1979 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1980 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1981 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1982 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1983 uint16_t msix_vect = vsi->msix_intr;
1984 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1985 uint16_t queue_idx = 0;
1989 for (i = 0; i < vsi->nb_qps; i++) {
1990 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1991 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1994 /* VF bind interrupt */
1995 if (vsi->type == I40E_VSI_SRIOV) {
1996 __vsi_queues_bind_intr(vsi, msix_vect,
1997 vsi->base_queue, vsi->nb_qps,
2002 /* PF & VMDq bind interrupt */
2003 if (rte_intr_dp_is_en(intr_handle)) {
2004 if (vsi->type == I40E_VSI_MAIN) {
2007 } else if (vsi->type == I40E_VSI_VMDQ2) {
2008 struct i40e_vsi *main_vsi =
2009 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2010 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2015 for (i = 0; i < vsi->nb_used_qps; i++) {
2017 if (!rte_intr_allow_others(intr_handle))
2018 /* allow to share MISC_VEC_ID */
2019 msix_vect = I40E_MISC_VEC_ID;
2021 /* no enough msix_vect, map all to one */
2022 __vsi_queues_bind_intr(vsi, msix_vect,
2023 vsi->base_queue + i,
2024 vsi->nb_used_qps - i,
2026 for (; !!record && i < vsi->nb_used_qps; i++)
2027 intr_handle->intr_vec[queue_idx + i] =
2031 /* 1:1 queue/msix_vect mapping */
2032 __vsi_queues_bind_intr(vsi, msix_vect,
2033 vsi->base_queue + i, 1,
2036 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2044 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2046 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2047 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2048 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2049 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2050 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2051 uint16_t msix_intr, i;
2053 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2054 for (i = 0; i < vsi->nb_msix; i++) {
2055 msix_intr = vsi->msix_intr + i;
2056 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2057 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2058 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2059 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2062 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2063 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2064 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2065 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2067 I40E_WRITE_FLUSH(hw);
2071 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2073 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2074 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2075 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2076 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2077 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2078 uint16_t msix_intr, i;
2080 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2081 for (i = 0; i < vsi->nb_msix; i++) {
2082 msix_intr = vsi->msix_intr + i;
2083 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2084 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2087 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2088 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2090 I40E_WRITE_FLUSH(hw);
2093 static inline uint8_t
2094 i40e_parse_link_speeds(uint16_t link_speeds)
2096 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2098 if (link_speeds & ETH_LINK_SPEED_40G)
2099 link_speed |= I40E_LINK_SPEED_40GB;
2100 if (link_speeds & ETH_LINK_SPEED_25G)
2101 link_speed |= I40E_LINK_SPEED_25GB;
2102 if (link_speeds & ETH_LINK_SPEED_20G)
2103 link_speed |= I40E_LINK_SPEED_20GB;
2104 if (link_speeds & ETH_LINK_SPEED_10G)
2105 link_speed |= I40E_LINK_SPEED_10GB;
2106 if (link_speeds & ETH_LINK_SPEED_1G)
2107 link_speed |= I40E_LINK_SPEED_1GB;
2108 if (link_speeds & ETH_LINK_SPEED_100M)
2109 link_speed |= I40E_LINK_SPEED_100MB;
2115 i40e_phy_conf_link(struct i40e_hw *hw,
2117 uint8_t force_speed,
2120 enum i40e_status_code status;
2121 struct i40e_aq_get_phy_abilities_resp phy_ab;
2122 struct i40e_aq_set_phy_config phy_conf;
2123 enum i40e_aq_phy_type cnt;
2124 uint8_t avail_speed;
2125 uint32_t phy_type_mask = 0;
2127 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2128 I40E_AQ_PHY_FLAG_PAUSE_RX |
2129 I40E_AQ_PHY_FLAG_PAUSE_RX |
2130 I40E_AQ_PHY_FLAG_LOW_POWER;
2133 /* To get phy capabilities of available speeds. */
2134 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2137 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2141 avail_speed = phy_ab.link_speed;
2143 /* To get the current phy config. */
2144 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2147 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2152 /* If link needs to go up and it is in autoneg mode the speed is OK,
2153 * no need to set up again.
2155 if (is_up && phy_ab.phy_type != 0 &&
2156 abilities & I40E_AQ_PHY_AN_ENABLED &&
2157 phy_ab.link_speed != 0)
2158 return I40E_SUCCESS;
2160 memset(&phy_conf, 0, sizeof(phy_conf));
2162 /* bits 0-2 use the values from get_phy_abilities_resp */
2164 abilities |= phy_ab.abilities & mask;
2166 phy_conf.abilities = abilities;
2168 /* If link needs to go up, but the force speed is not supported,
2169 * Warn users and config the default available speeds.
2171 if (is_up && !(force_speed & avail_speed)) {
2172 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2173 phy_conf.link_speed = avail_speed;
2175 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2178 /* PHY type mask needs to include each type except PHY type extension */
2179 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2180 phy_type_mask |= 1 << cnt;
2182 /* use get_phy_abilities_resp value for the rest */
2183 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2184 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2185 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2186 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2187 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2188 phy_conf.eee_capability = phy_ab.eee_capability;
2189 phy_conf.eeer = phy_ab.eeer_val;
2190 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2192 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2193 phy_ab.abilities, phy_ab.link_speed);
2194 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2195 phy_conf.abilities, phy_conf.link_speed);
2197 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2201 return I40E_SUCCESS;
2205 i40e_apply_link_speed(struct rte_eth_dev *dev)
2208 uint8_t abilities = 0;
2209 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2210 struct rte_eth_conf *conf = &dev->data->dev_conf;
2212 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2213 conf->link_speeds = ETH_LINK_SPEED_40G |
2214 ETH_LINK_SPEED_25G |
2215 ETH_LINK_SPEED_20G |
2216 ETH_LINK_SPEED_10G |
2218 ETH_LINK_SPEED_100M;
2220 speed = i40e_parse_link_speeds(conf->link_speeds);
2221 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2222 I40E_AQ_PHY_AN_ENABLED |
2223 I40E_AQ_PHY_LINK_ENABLED;
2225 return i40e_phy_conf_link(hw, abilities, speed, true);
2229 i40e_dev_start(struct rte_eth_dev *dev)
2231 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2232 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2233 struct i40e_vsi *main_vsi = pf->main_vsi;
2235 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2236 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2237 uint32_t intr_vector = 0;
2238 struct i40e_vsi *vsi;
2240 hw->adapter_stopped = 0;
2242 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2244 "Invalid link_speeds for port %u, autonegotiation disabled",
2245 dev->data->port_id);
2249 rte_intr_disable(intr_handle);
2251 if ((rte_intr_cap_multiple(intr_handle) ||
2252 !RTE_ETH_DEV_SRIOV(dev).active) &&
2253 dev->data->dev_conf.intr_conf.rxq != 0) {
2254 intr_vector = dev->data->nb_rx_queues;
2255 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2260 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2261 intr_handle->intr_vec =
2262 rte_zmalloc("intr_vec",
2263 dev->data->nb_rx_queues * sizeof(int),
2265 if (!intr_handle->intr_vec) {
2267 "Failed to allocate %d rx_queues intr_vec",
2268 dev->data->nb_rx_queues);
2273 /* Initialize VSI */
2274 ret = i40e_dev_rxtx_init(pf);
2275 if (ret != I40E_SUCCESS) {
2276 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2280 /* Map queues with MSIX interrupt */
2281 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2282 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2283 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2284 i40e_vsi_enable_queues_intr(main_vsi);
2286 /* Map VMDQ VSI queues with MSIX interrupt */
2287 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2288 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2289 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2290 I40E_ITR_INDEX_DEFAULT);
2291 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2294 /* enable FDIR MSIX interrupt */
2295 if (pf->fdir.fdir_vsi) {
2296 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2297 I40E_ITR_INDEX_NONE);
2298 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2301 /* Enable all queues which have been configured */
2302 ret = i40e_dev_switch_queues(pf, TRUE);
2303 if (ret != I40E_SUCCESS) {
2304 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2308 /* Enable receiving broadcast packets */
2309 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2310 if (ret != I40E_SUCCESS)
2311 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2313 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2314 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2316 if (ret != I40E_SUCCESS)
2317 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2320 /* Enable the VLAN promiscuous mode. */
2322 for (i = 0; i < pf->vf_num; i++) {
2323 vsi = pf->vfs[i].vsi;
2324 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2329 /* Enable mac loopback mode */
2330 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2331 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2332 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2333 if (ret != I40E_SUCCESS) {
2334 PMD_DRV_LOG(ERR, "fail to set loopback link");
2339 /* Apply link configure */
2340 ret = i40e_apply_link_speed(dev);
2341 if (I40E_SUCCESS != ret) {
2342 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2346 if (!rte_intr_allow_others(intr_handle)) {
2347 rte_intr_callback_unregister(intr_handle,
2348 i40e_dev_interrupt_handler,
2350 /* configure and enable device interrupt */
2351 i40e_pf_config_irq0(hw, FALSE);
2352 i40e_pf_enable_irq0(hw);
2354 if (dev->data->dev_conf.intr_conf.lsc != 0)
2356 "lsc won't enable because of no intr multiplex");
2358 ret = i40e_aq_set_phy_int_mask(hw,
2359 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2360 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2361 I40E_AQ_EVENT_MEDIA_NA), NULL);
2362 if (ret != I40E_SUCCESS)
2363 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2365 /* Call get_link_info aq commond to enable/disable LSE */
2366 i40e_dev_link_update(dev, 0);
2369 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2370 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2371 i40e_dev_alarm_handler, dev);
2373 /* enable uio intr after callback register */
2374 rte_intr_enable(intr_handle);
2377 i40e_filter_restore(pf);
2379 if (pf->tm_conf.root && !pf->tm_conf.committed)
2380 PMD_DRV_LOG(WARNING,
2381 "please call hierarchy_commit() "
2382 "before starting the port");
2384 return I40E_SUCCESS;
2387 i40e_dev_switch_queues(pf, FALSE);
2388 i40e_dev_clear_queues(dev);
2394 i40e_dev_stop(struct rte_eth_dev *dev)
2396 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2397 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398 struct i40e_vsi *main_vsi = pf->main_vsi;
2399 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2400 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2403 if (hw->adapter_stopped == 1)
2406 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2407 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2408 rte_intr_enable(intr_handle);
2411 /* Disable all queues */
2412 i40e_dev_switch_queues(pf, FALSE);
2414 /* un-map queues with interrupt registers */
2415 i40e_vsi_disable_queues_intr(main_vsi);
2416 i40e_vsi_queues_unbind_intr(main_vsi);
2418 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2419 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2420 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2423 if (pf->fdir.fdir_vsi) {
2424 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2425 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2427 /* Clear all queues and release memory */
2428 i40e_dev_clear_queues(dev);
2431 i40e_dev_set_link_down(dev);
2433 if (!rte_intr_allow_others(intr_handle))
2434 /* resume to the default handler */
2435 rte_intr_callback_register(intr_handle,
2436 i40e_dev_interrupt_handler,
2439 /* Clean datapath event and queue/vec mapping */
2440 rte_intr_efd_disable(intr_handle);
2441 if (intr_handle->intr_vec) {
2442 rte_free(intr_handle->intr_vec);
2443 intr_handle->intr_vec = NULL;
2446 /* reset hierarchy commit */
2447 pf->tm_conf.committed = false;
2449 hw->adapter_stopped = 1;
2453 i40e_dev_close(struct rte_eth_dev *dev)
2455 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2456 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2458 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2459 struct i40e_mirror_rule *p_mirror;
2464 PMD_INIT_FUNC_TRACE();
2468 /* Remove all mirror rules */
2469 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2470 ret = i40e_aq_del_mirror_rule(hw,
2471 pf->main_vsi->veb->seid,
2472 p_mirror->rule_type,
2474 p_mirror->num_entries,
2477 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2478 "status = %d, aq_err = %d.", ret,
2479 hw->aq.asq_last_status);
2481 /* remove mirror software resource anyway */
2482 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2484 pf->nb_mirror_rule--;
2487 i40e_dev_free_queues(dev);
2489 /* Disable interrupt */
2490 i40e_pf_disable_irq0(hw);
2491 rte_intr_disable(intr_handle);
2494 * Only legacy filter API needs the following fdir config. So when the
2495 * legacy filter API is deprecated, the following code should also be
2498 i40e_fdir_teardown(pf);
2500 /* shutdown and destroy the HMC */
2501 i40e_shutdown_lan_hmc(hw);
2503 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2504 i40e_vsi_release(pf->vmdq[i].vsi);
2505 pf->vmdq[i].vsi = NULL;
2510 /* release all the existing VSIs and VEBs */
2511 i40e_vsi_release(pf->main_vsi);
2513 /* shutdown the adminq */
2514 i40e_aq_queue_shutdown(hw, true);
2515 i40e_shutdown_adminq(hw);
2517 i40e_res_pool_destroy(&pf->qp_pool);
2518 i40e_res_pool_destroy(&pf->msix_pool);
2520 /* Disable flexible payload in global configuration */
2521 if (!pf->support_multi_driver)
2522 i40e_flex_payload_reg_set_default(hw);
2524 /* force a PF reset to clean anything leftover */
2525 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2526 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2527 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2528 I40E_WRITE_FLUSH(hw);
2532 * Reset PF device only to re-initialize resources in PMD layer
2535 i40e_dev_reset(struct rte_eth_dev *dev)
2539 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2540 * its VF to make them align with it. The detailed notification
2541 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2542 * To avoid unexpected behavior in VF, currently reset of PF with
2543 * SR-IOV activation is not supported. It might be supported later.
2545 if (dev->data->sriov.active)
2548 ret = eth_i40e_dev_uninit(dev);
2552 ret = eth_i40e_dev_init(dev, NULL);
2558 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2560 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2561 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2562 struct i40e_vsi *vsi = pf->main_vsi;
2565 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2567 if (status != I40E_SUCCESS)
2568 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2570 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2572 if (status != I40E_SUCCESS)
2573 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2578 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2580 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2581 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2582 struct i40e_vsi *vsi = pf->main_vsi;
2585 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2587 if (status != I40E_SUCCESS)
2588 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2590 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2592 if (status != I40E_SUCCESS)
2593 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2597 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2599 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2600 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2601 struct i40e_vsi *vsi = pf->main_vsi;
2604 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2605 if (ret != I40E_SUCCESS)
2606 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2610 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2612 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2613 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2614 struct i40e_vsi *vsi = pf->main_vsi;
2617 if (dev->data->promiscuous == 1)
2618 return; /* must remain in all_multicast mode */
2620 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2621 vsi->seid, FALSE, NULL);
2622 if (ret != I40E_SUCCESS)
2623 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2627 * Set device link up.
2630 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2632 /* re-apply link speed setting */
2633 return i40e_apply_link_speed(dev);
2637 * Set device link down.
2640 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2642 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2643 uint8_t abilities = 0;
2644 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2646 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2647 return i40e_phy_conf_link(hw, abilities, speed, false);
2650 static __rte_always_inline void
2651 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2653 /* Link status registers and values*/
2654 #define I40E_PRTMAC_LINKSTA 0x001E2420
2655 #define I40E_REG_LINK_UP 0x40000080
2656 #define I40E_PRTMAC_MACC 0x001E24E0
2657 #define I40E_REG_MACC_25GB 0x00020000
2658 #define I40E_REG_SPEED_MASK 0x38000000
2659 #define I40E_REG_SPEED_100MB 0x00000000
2660 #define I40E_REG_SPEED_1GB 0x08000000
2661 #define I40E_REG_SPEED_10GB 0x10000000
2662 #define I40E_REG_SPEED_20GB 0x20000000
2663 #define I40E_REG_SPEED_25_40GB 0x18000000
2664 uint32_t link_speed;
2667 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2668 link_speed = reg_val & I40E_REG_SPEED_MASK;
2669 reg_val &= I40E_REG_LINK_UP;
2670 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2672 if (unlikely(link->link_status == 0))
2675 /* Parse the link status */
2676 switch (link_speed) {
2677 case I40E_REG_SPEED_100MB:
2678 link->link_speed = ETH_SPEED_NUM_100M;
2680 case I40E_REG_SPEED_1GB:
2681 link->link_speed = ETH_SPEED_NUM_1G;
2683 case I40E_REG_SPEED_10GB:
2684 link->link_speed = ETH_SPEED_NUM_10G;
2686 case I40E_REG_SPEED_20GB:
2687 link->link_speed = ETH_SPEED_NUM_20G;
2689 case I40E_REG_SPEED_25_40GB:
2690 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2692 if (reg_val & I40E_REG_MACC_25GB)
2693 link->link_speed = ETH_SPEED_NUM_25G;
2695 link->link_speed = ETH_SPEED_NUM_40G;
2699 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2704 static __rte_always_inline void
2705 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2706 bool enable_lse, int wait_to_complete)
2708 #define CHECK_INTERVAL 100 /* 100ms */
2709 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2710 uint32_t rep_cnt = MAX_REPEAT_TIME;
2711 struct i40e_link_status link_status;
2714 memset(&link_status, 0, sizeof(link_status));
2717 memset(&link_status, 0, sizeof(link_status));
2719 /* Get link status information from hardware */
2720 status = i40e_aq_get_link_info(hw, enable_lse,
2721 &link_status, NULL);
2722 if (unlikely(status != I40E_SUCCESS)) {
2723 link->link_speed = ETH_SPEED_NUM_100M;
2724 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2725 PMD_DRV_LOG(ERR, "Failed to get link info");
2729 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2730 if (!wait_to_complete || link->link_status)
2733 rte_delay_ms(CHECK_INTERVAL);
2734 } while (--rep_cnt);
2736 /* Parse the link status */
2737 switch (link_status.link_speed) {
2738 case I40E_LINK_SPEED_100MB:
2739 link->link_speed = ETH_SPEED_NUM_100M;
2741 case I40E_LINK_SPEED_1GB:
2742 link->link_speed = ETH_SPEED_NUM_1G;
2744 case I40E_LINK_SPEED_10GB:
2745 link->link_speed = ETH_SPEED_NUM_10G;
2747 case I40E_LINK_SPEED_20GB:
2748 link->link_speed = ETH_SPEED_NUM_20G;
2750 case I40E_LINK_SPEED_25GB:
2751 link->link_speed = ETH_SPEED_NUM_25G;
2753 case I40E_LINK_SPEED_40GB:
2754 link->link_speed = ETH_SPEED_NUM_40G;
2757 link->link_speed = ETH_SPEED_NUM_100M;
2763 i40e_dev_link_update(struct rte_eth_dev *dev,
2764 int wait_to_complete)
2766 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2767 struct rte_eth_link link;
2768 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2771 memset(&link, 0, sizeof(link));
2773 /* i40e uses full duplex only */
2774 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2775 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2776 ETH_LINK_SPEED_FIXED);
2778 if (!wait_to_complete && !enable_lse)
2779 update_link_reg(hw, &link);
2781 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2783 ret = rte_eth_linkstatus_set(dev, &link);
2784 i40e_notify_all_vfs_link_status(dev);
2789 /* Get all the statistics of a VSI */
2791 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2793 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2794 struct i40e_eth_stats *nes = &vsi->eth_stats;
2795 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2796 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2798 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2799 vsi->offset_loaded, &oes->rx_bytes,
2801 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2802 vsi->offset_loaded, &oes->rx_unicast,
2804 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2805 vsi->offset_loaded, &oes->rx_multicast,
2806 &nes->rx_multicast);
2807 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2808 vsi->offset_loaded, &oes->rx_broadcast,
2809 &nes->rx_broadcast);
2810 /* exclude CRC bytes */
2811 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2812 nes->rx_broadcast) * ETHER_CRC_LEN;
2814 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2815 &oes->rx_discards, &nes->rx_discards);
2816 /* GLV_REPC not supported */
2817 /* GLV_RMPC not supported */
2818 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2819 &oes->rx_unknown_protocol,
2820 &nes->rx_unknown_protocol);
2821 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2822 vsi->offset_loaded, &oes->tx_bytes,
2824 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2825 vsi->offset_loaded, &oes->tx_unicast,
2827 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2828 vsi->offset_loaded, &oes->tx_multicast,
2829 &nes->tx_multicast);
2830 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2831 vsi->offset_loaded, &oes->tx_broadcast,
2832 &nes->tx_broadcast);
2833 /* GLV_TDPC not supported */
2834 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2835 &oes->tx_errors, &nes->tx_errors);
2836 vsi->offset_loaded = true;
2838 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2840 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2841 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2842 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2843 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2844 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2845 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2846 nes->rx_unknown_protocol);
2847 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2848 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2849 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2850 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2851 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2852 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2853 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2858 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2861 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2862 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2864 /* Get rx/tx bytes of internal transfer packets */
2865 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2866 I40E_GLV_GORCL(hw->port),
2868 &pf->internal_stats_offset.rx_bytes,
2869 &pf->internal_stats.rx_bytes);
2871 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2872 I40E_GLV_GOTCL(hw->port),
2874 &pf->internal_stats_offset.tx_bytes,
2875 &pf->internal_stats.tx_bytes);
2876 /* Get total internal rx packet count */
2877 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2878 I40E_GLV_UPRCL(hw->port),
2880 &pf->internal_stats_offset.rx_unicast,
2881 &pf->internal_stats.rx_unicast);
2882 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2883 I40E_GLV_MPRCL(hw->port),
2885 &pf->internal_stats_offset.rx_multicast,
2886 &pf->internal_stats.rx_multicast);
2887 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2888 I40E_GLV_BPRCL(hw->port),
2890 &pf->internal_stats_offset.rx_broadcast,
2891 &pf->internal_stats.rx_broadcast);
2892 /* Get total internal tx packet count */
2893 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2894 I40E_GLV_UPTCL(hw->port),
2896 &pf->internal_stats_offset.tx_unicast,
2897 &pf->internal_stats.tx_unicast);
2898 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2899 I40E_GLV_MPTCL(hw->port),
2901 &pf->internal_stats_offset.tx_multicast,
2902 &pf->internal_stats.tx_multicast);
2903 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2904 I40E_GLV_BPTCL(hw->port),
2906 &pf->internal_stats_offset.tx_broadcast,
2907 &pf->internal_stats.tx_broadcast);
2909 /* exclude CRC size */
2910 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2911 pf->internal_stats.rx_multicast +
2912 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2914 /* Get statistics of struct i40e_eth_stats */
2915 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2916 I40E_GLPRT_GORCL(hw->port),
2917 pf->offset_loaded, &os->eth.rx_bytes,
2919 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2920 I40E_GLPRT_UPRCL(hw->port),
2921 pf->offset_loaded, &os->eth.rx_unicast,
2922 &ns->eth.rx_unicast);
2923 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2924 I40E_GLPRT_MPRCL(hw->port),
2925 pf->offset_loaded, &os->eth.rx_multicast,
2926 &ns->eth.rx_multicast);
2927 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2928 I40E_GLPRT_BPRCL(hw->port),
2929 pf->offset_loaded, &os->eth.rx_broadcast,
2930 &ns->eth.rx_broadcast);
2931 /* Workaround: CRC size should not be included in byte statistics,
2932 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2934 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2935 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2937 /* exclude internal rx bytes
2938 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2939 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2941 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2943 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2944 ns->eth.rx_bytes = 0;
2946 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2948 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2949 ns->eth.rx_unicast = 0;
2951 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2953 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2954 ns->eth.rx_multicast = 0;
2956 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2958 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2959 ns->eth.rx_broadcast = 0;
2961 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2963 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2964 pf->offset_loaded, &os->eth.rx_discards,
2965 &ns->eth.rx_discards);
2966 /* GLPRT_REPC not supported */
2967 /* GLPRT_RMPC not supported */
2968 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2970 &os->eth.rx_unknown_protocol,
2971 &ns->eth.rx_unknown_protocol);
2972 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2973 I40E_GLPRT_GOTCL(hw->port),
2974 pf->offset_loaded, &os->eth.tx_bytes,
2976 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2977 I40E_GLPRT_UPTCL(hw->port),
2978 pf->offset_loaded, &os->eth.tx_unicast,
2979 &ns->eth.tx_unicast);
2980 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2981 I40E_GLPRT_MPTCL(hw->port),
2982 pf->offset_loaded, &os->eth.tx_multicast,
2983 &ns->eth.tx_multicast);
2984 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2985 I40E_GLPRT_BPTCL(hw->port),
2986 pf->offset_loaded, &os->eth.tx_broadcast,
2987 &ns->eth.tx_broadcast);
2988 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2989 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2991 /* exclude internal tx bytes
2992 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2993 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2995 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2997 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2998 ns->eth.tx_bytes = 0;
3000 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3002 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3003 ns->eth.tx_unicast = 0;
3005 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3007 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3008 ns->eth.tx_multicast = 0;
3010 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3012 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3013 ns->eth.tx_broadcast = 0;
3015 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3017 /* GLPRT_TEPC not supported */
3019 /* additional port specific stats */
3020 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3021 pf->offset_loaded, &os->tx_dropped_link_down,
3022 &ns->tx_dropped_link_down);
3023 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3024 pf->offset_loaded, &os->crc_errors,
3026 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3027 pf->offset_loaded, &os->illegal_bytes,
3028 &ns->illegal_bytes);
3029 /* GLPRT_ERRBC not supported */
3030 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3031 pf->offset_loaded, &os->mac_local_faults,
3032 &ns->mac_local_faults);
3033 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3034 pf->offset_loaded, &os->mac_remote_faults,
3035 &ns->mac_remote_faults);
3036 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3037 pf->offset_loaded, &os->rx_length_errors,
3038 &ns->rx_length_errors);
3039 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3040 pf->offset_loaded, &os->link_xon_rx,
3042 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3043 pf->offset_loaded, &os->link_xoff_rx,
3045 for (i = 0; i < 8; i++) {
3046 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3048 &os->priority_xon_rx[i],
3049 &ns->priority_xon_rx[i]);
3050 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3052 &os->priority_xoff_rx[i],
3053 &ns->priority_xoff_rx[i]);
3055 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3056 pf->offset_loaded, &os->link_xon_tx,
3058 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3059 pf->offset_loaded, &os->link_xoff_tx,
3061 for (i = 0; i < 8; i++) {
3062 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3064 &os->priority_xon_tx[i],
3065 &ns->priority_xon_tx[i]);
3066 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3068 &os->priority_xoff_tx[i],
3069 &ns->priority_xoff_tx[i]);
3070 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3072 &os->priority_xon_2_xoff[i],
3073 &ns->priority_xon_2_xoff[i]);
3075 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3076 I40E_GLPRT_PRC64L(hw->port),
3077 pf->offset_loaded, &os->rx_size_64,
3079 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3080 I40E_GLPRT_PRC127L(hw->port),
3081 pf->offset_loaded, &os->rx_size_127,
3083 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3084 I40E_GLPRT_PRC255L(hw->port),
3085 pf->offset_loaded, &os->rx_size_255,
3087 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3088 I40E_GLPRT_PRC511L(hw->port),
3089 pf->offset_loaded, &os->rx_size_511,
3091 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3092 I40E_GLPRT_PRC1023L(hw->port),
3093 pf->offset_loaded, &os->rx_size_1023,
3095 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3096 I40E_GLPRT_PRC1522L(hw->port),
3097 pf->offset_loaded, &os->rx_size_1522,
3099 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3100 I40E_GLPRT_PRC9522L(hw->port),
3101 pf->offset_loaded, &os->rx_size_big,
3103 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3104 pf->offset_loaded, &os->rx_undersize,
3106 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3107 pf->offset_loaded, &os->rx_fragments,
3109 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3110 pf->offset_loaded, &os->rx_oversize,
3112 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3113 pf->offset_loaded, &os->rx_jabber,
3115 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3116 I40E_GLPRT_PTC64L(hw->port),
3117 pf->offset_loaded, &os->tx_size_64,
3119 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3120 I40E_GLPRT_PTC127L(hw->port),
3121 pf->offset_loaded, &os->tx_size_127,
3123 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3124 I40E_GLPRT_PTC255L(hw->port),
3125 pf->offset_loaded, &os->tx_size_255,
3127 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3128 I40E_GLPRT_PTC511L(hw->port),
3129 pf->offset_loaded, &os->tx_size_511,
3131 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3132 I40E_GLPRT_PTC1023L(hw->port),
3133 pf->offset_loaded, &os->tx_size_1023,
3135 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3136 I40E_GLPRT_PTC1522L(hw->port),
3137 pf->offset_loaded, &os->tx_size_1522,
3139 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3140 I40E_GLPRT_PTC9522L(hw->port),
3141 pf->offset_loaded, &os->tx_size_big,
3143 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3145 &os->fd_sb_match, &ns->fd_sb_match);
3146 /* GLPRT_MSPDC not supported */
3147 /* GLPRT_XEC not supported */
3149 pf->offset_loaded = true;
3152 i40e_update_vsi_stats(pf->main_vsi);
3155 /* Get all statistics of a port */
3157 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3159 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3160 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3161 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3164 /* call read registers - updates values, now write them to struct */
3165 i40e_read_stats_registers(pf, hw);
3167 stats->ipackets = ns->eth.rx_unicast +
3168 ns->eth.rx_multicast +
3169 ns->eth.rx_broadcast -
3170 ns->eth.rx_discards -
3171 pf->main_vsi->eth_stats.rx_discards;
3172 stats->opackets = ns->eth.tx_unicast +
3173 ns->eth.tx_multicast +
3174 ns->eth.tx_broadcast;
3175 stats->ibytes = ns->eth.rx_bytes;
3176 stats->obytes = ns->eth.tx_bytes;
3177 stats->oerrors = ns->eth.tx_errors +
3178 pf->main_vsi->eth_stats.tx_errors;
3181 stats->imissed = ns->eth.rx_discards +
3182 pf->main_vsi->eth_stats.rx_discards;
3183 stats->ierrors = ns->crc_errors +
3184 ns->rx_length_errors + ns->rx_undersize +
3185 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3187 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3188 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3189 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3190 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3191 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3192 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3193 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3194 ns->eth.rx_unknown_protocol);
3195 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3196 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3197 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3198 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3199 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3200 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3202 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3203 ns->tx_dropped_link_down);
3204 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3205 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3207 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3208 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3209 ns->mac_local_faults);
3210 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3211 ns->mac_remote_faults);
3212 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3213 ns->rx_length_errors);
3214 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3215 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3216 for (i = 0; i < 8; i++) {
3217 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3218 i, ns->priority_xon_rx[i]);
3219 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3220 i, ns->priority_xoff_rx[i]);
3222 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3223 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3224 for (i = 0; i < 8; i++) {
3225 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3226 i, ns->priority_xon_tx[i]);
3227 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3228 i, ns->priority_xoff_tx[i]);
3229 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3230 i, ns->priority_xon_2_xoff[i]);
3232 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3233 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3234 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3235 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3236 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3237 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3238 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3239 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3240 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3241 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3242 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3243 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3244 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3245 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3246 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3247 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3248 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3249 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3250 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3251 ns->mac_short_packet_dropped);
3252 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3253 ns->checksum_error);
3254 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3255 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3259 /* Reset the statistics */
3261 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3263 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3264 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3266 /* Mark PF and VSI stats to update the offset, aka "reset" */
3267 pf->offset_loaded = false;
3269 pf->main_vsi->offset_loaded = false;
3271 /* read the stats, reading current register values into offset */
3272 i40e_read_stats_registers(pf, hw);
3276 i40e_xstats_calc_num(void)
3278 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3279 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3280 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3283 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3284 struct rte_eth_xstat_name *xstats_names,
3285 __rte_unused unsigned limit)
3290 if (xstats_names == NULL)
3291 return i40e_xstats_calc_num();
3293 /* Note: limit checked in rte_eth_xstats_names() */
3295 /* Get stats from i40e_eth_stats struct */
3296 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3297 snprintf(xstats_names[count].name,
3298 sizeof(xstats_names[count].name),
3299 "%s", rte_i40e_stats_strings[i].name);
3303 /* Get individiual stats from i40e_hw_port struct */
3304 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3305 snprintf(xstats_names[count].name,
3306 sizeof(xstats_names[count].name),
3307 "%s", rte_i40e_hw_port_strings[i].name);
3311 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3312 for (prio = 0; prio < 8; prio++) {
3313 snprintf(xstats_names[count].name,
3314 sizeof(xstats_names[count].name),
3315 "rx_priority%u_%s", prio,
3316 rte_i40e_rxq_prio_strings[i].name);
3321 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3322 for (prio = 0; prio < 8; prio++) {
3323 snprintf(xstats_names[count].name,
3324 sizeof(xstats_names[count].name),
3325 "tx_priority%u_%s", prio,
3326 rte_i40e_txq_prio_strings[i].name);
3334 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3337 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3338 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3339 unsigned i, count, prio;
3340 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3342 count = i40e_xstats_calc_num();
3346 i40e_read_stats_registers(pf, hw);
3353 /* Get stats from i40e_eth_stats struct */
3354 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3355 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3356 rte_i40e_stats_strings[i].offset);
3357 xstats[count].id = count;
3361 /* Get individiual stats from i40e_hw_port struct */
3362 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3363 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3364 rte_i40e_hw_port_strings[i].offset);
3365 xstats[count].id = count;
3369 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3370 for (prio = 0; prio < 8; prio++) {
3371 xstats[count].value =
3372 *(uint64_t *)(((char *)hw_stats) +
3373 rte_i40e_rxq_prio_strings[i].offset +
3374 (sizeof(uint64_t) * prio));
3375 xstats[count].id = count;
3380 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3381 for (prio = 0; prio < 8; prio++) {
3382 xstats[count].value =
3383 *(uint64_t *)(((char *)hw_stats) +
3384 rte_i40e_txq_prio_strings[i].offset +
3385 (sizeof(uint64_t) * prio));
3386 xstats[count].id = count;
3395 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3396 __rte_unused uint16_t queue_id,
3397 __rte_unused uint8_t stat_idx,
3398 __rte_unused uint8_t is_rx)
3400 PMD_INIT_FUNC_TRACE();
3406 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3408 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3414 full_ver = hw->nvm.oem_ver;
3415 ver = (u8)(full_ver >> 24);
3416 build = (u16)((full_ver >> 8) & 0xffff);
3417 patch = (u8)(full_ver & 0xff);
3419 ret = snprintf(fw_version, fw_size,
3420 "%d.%d%d 0x%08x %d.%d.%d",
3421 ((hw->nvm.version >> 12) & 0xf),
3422 ((hw->nvm.version >> 4) & 0xff),
3423 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3426 ret += 1; /* add the size of '\0' */
3427 if (fw_size < (u32)ret)
3434 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3436 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3437 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3438 struct i40e_vsi *vsi = pf->main_vsi;
3439 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3441 dev_info->max_rx_queues = vsi->nb_qps;
3442 dev_info->max_tx_queues = vsi->nb_qps;
3443 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3444 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3445 dev_info->max_mac_addrs = vsi->max_macaddrs;
3446 dev_info->max_vfs = pci_dev->max_vfs;
3447 dev_info->rx_queue_offload_capa = 0;
3448 dev_info->rx_offload_capa =
3449 DEV_RX_OFFLOAD_VLAN_STRIP |
3450 DEV_RX_OFFLOAD_QINQ_STRIP |
3451 DEV_RX_OFFLOAD_IPV4_CKSUM |
3452 DEV_RX_OFFLOAD_UDP_CKSUM |
3453 DEV_RX_OFFLOAD_TCP_CKSUM |
3454 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3455 DEV_RX_OFFLOAD_KEEP_CRC |
3456 DEV_RX_OFFLOAD_SCATTER |
3457 DEV_RX_OFFLOAD_VLAN_EXTEND |
3458 DEV_RX_OFFLOAD_VLAN_FILTER |
3459 DEV_RX_OFFLOAD_JUMBO_FRAME;
3461 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3462 dev_info->tx_offload_capa =
3463 DEV_TX_OFFLOAD_VLAN_INSERT |
3464 DEV_TX_OFFLOAD_QINQ_INSERT |
3465 DEV_TX_OFFLOAD_IPV4_CKSUM |
3466 DEV_TX_OFFLOAD_UDP_CKSUM |
3467 DEV_TX_OFFLOAD_TCP_CKSUM |
3468 DEV_TX_OFFLOAD_SCTP_CKSUM |
3469 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3470 DEV_TX_OFFLOAD_TCP_TSO |
3471 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3472 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3473 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3474 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3475 DEV_TX_OFFLOAD_MULTI_SEGS |
3476 dev_info->tx_queue_offload_capa;
3477 dev_info->dev_capa =
3478 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3479 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3481 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3483 dev_info->reta_size = pf->hash_lut_size;
3484 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3486 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3488 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3489 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3490 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3492 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3497 dev_info->default_txconf = (struct rte_eth_txconf) {
3499 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3500 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3501 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3503 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3504 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3508 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3509 .nb_max = I40E_MAX_RING_DESC,
3510 .nb_min = I40E_MIN_RING_DESC,
3511 .nb_align = I40E_ALIGN_RING_DESC,
3514 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3515 .nb_max = I40E_MAX_RING_DESC,
3516 .nb_min = I40E_MIN_RING_DESC,
3517 .nb_align = I40E_ALIGN_RING_DESC,
3518 .nb_seg_max = I40E_TX_MAX_SEG,
3519 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3522 if (pf->flags & I40E_FLAG_VMDQ) {
3523 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3524 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3525 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3526 pf->max_nb_vmdq_vsi;
3527 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3528 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3529 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3532 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3534 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3535 dev_info->default_rxportconf.nb_queues = 2;
3536 dev_info->default_txportconf.nb_queues = 2;
3537 if (dev->data->nb_rx_queues == 1)
3538 dev_info->default_rxportconf.ring_size = 2048;
3540 dev_info->default_rxportconf.ring_size = 1024;
3541 if (dev->data->nb_tx_queues == 1)
3542 dev_info->default_txportconf.ring_size = 1024;
3544 dev_info->default_txportconf.ring_size = 512;
3546 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3548 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3549 dev_info->default_rxportconf.nb_queues = 1;
3550 dev_info->default_txportconf.nb_queues = 1;
3551 dev_info->default_rxportconf.ring_size = 256;
3552 dev_info->default_txportconf.ring_size = 256;
3555 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3556 dev_info->default_rxportconf.nb_queues = 1;
3557 dev_info->default_txportconf.nb_queues = 1;
3558 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3559 dev_info->default_rxportconf.ring_size = 512;
3560 dev_info->default_txportconf.ring_size = 256;
3562 dev_info->default_rxportconf.ring_size = 256;
3563 dev_info->default_txportconf.ring_size = 256;
3566 dev_info->default_rxportconf.burst_size = 32;
3567 dev_info->default_txportconf.burst_size = 32;
3571 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3573 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3574 struct i40e_vsi *vsi = pf->main_vsi;
3575 PMD_INIT_FUNC_TRACE();
3578 return i40e_vsi_add_vlan(vsi, vlan_id);
3580 return i40e_vsi_delete_vlan(vsi, vlan_id);
3584 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3585 enum rte_vlan_type vlan_type,
3586 uint16_t tpid, int qinq)
3588 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3591 uint16_t reg_id = 3;
3595 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3599 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3601 if (ret != I40E_SUCCESS) {
3603 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3608 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3611 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3612 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3613 if (reg_r == reg_w) {
3614 PMD_DRV_LOG(DEBUG, "No need to write");
3618 ret = i40e_aq_debug_write_global_register(hw,
3619 I40E_GL_SWT_L2TAGCTRL(reg_id),
3621 if (ret != I40E_SUCCESS) {
3623 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3628 "Global register 0x%08x is changed with value 0x%08x",
3629 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3635 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3636 enum rte_vlan_type vlan_type,
3639 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3640 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3641 int qinq = dev->data->dev_conf.rxmode.offloads &
3642 DEV_RX_OFFLOAD_VLAN_EXTEND;
3645 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3646 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3647 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3649 "Unsupported vlan type.");
3653 if (pf->support_multi_driver) {
3654 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3658 /* 802.1ad frames ability is added in NVM API 1.7*/
3659 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3661 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3662 hw->first_tag = rte_cpu_to_le_16(tpid);
3663 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3664 hw->second_tag = rte_cpu_to_le_16(tpid);
3666 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3667 hw->second_tag = rte_cpu_to_le_16(tpid);
3669 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3670 if (ret != I40E_SUCCESS) {
3672 "Set switch config failed aq_err: %d",
3673 hw->aq.asq_last_status);
3677 /* If NVM API < 1.7, keep the register setting */
3678 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3685 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3687 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3688 struct i40e_vsi *vsi = pf->main_vsi;
3689 struct rte_eth_rxmode *rxmode;
3691 rxmode = &dev->data->dev_conf.rxmode;
3692 if (mask & ETH_VLAN_FILTER_MASK) {
3693 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3694 i40e_vsi_config_vlan_filter(vsi, TRUE);
3696 i40e_vsi_config_vlan_filter(vsi, FALSE);
3699 if (mask & ETH_VLAN_STRIP_MASK) {
3700 /* Enable or disable VLAN stripping */
3701 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3702 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3704 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3707 if (mask & ETH_VLAN_EXTEND_MASK) {
3708 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3709 i40e_vsi_config_double_vlan(vsi, TRUE);
3710 /* Set global registers with default ethertype. */
3711 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3713 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3717 i40e_vsi_config_double_vlan(vsi, FALSE);
3724 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3725 __rte_unused uint16_t queue,
3726 __rte_unused int on)
3728 PMD_INIT_FUNC_TRACE();
3732 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3734 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3735 struct i40e_vsi *vsi = pf->main_vsi;
3736 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3737 struct i40e_vsi_vlan_pvid_info info;
3739 memset(&info, 0, sizeof(info));
3742 info.config.pvid = pvid;
3744 info.config.reject.tagged =
3745 data->dev_conf.txmode.hw_vlan_reject_tagged;
3746 info.config.reject.untagged =
3747 data->dev_conf.txmode.hw_vlan_reject_untagged;
3750 return i40e_vsi_vlan_pvid_set(vsi, &info);
3754 i40e_dev_led_on(struct rte_eth_dev *dev)
3756 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3757 uint32_t mode = i40e_led_get(hw);
3760 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3766 i40e_dev_led_off(struct rte_eth_dev *dev)
3768 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3769 uint32_t mode = i40e_led_get(hw);
3772 i40e_led_set(hw, 0, false);
3778 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3780 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3781 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3783 fc_conf->pause_time = pf->fc_conf.pause_time;
3785 /* read out from register, in case they are modified by other port */
3786 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3787 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3788 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3789 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3791 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3792 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3794 /* Return current mode according to actual setting*/
3795 switch (hw->fc.current_mode) {
3797 fc_conf->mode = RTE_FC_FULL;
3799 case I40E_FC_TX_PAUSE:
3800 fc_conf->mode = RTE_FC_TX_PAUSE;
3802 case I40E_FC_RX_PAUSE:
3803 fc_conf->mode = RTE_FC_RX_PAUSE;
3807 fc_conf->mode = RTE_FC_NONE;
3814 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3816 uint32_t mflcn_reg, fctrl_reg, reg;
3817 uint32_t max_high_water;
3818 uint8_t i, aq_failure;
3822 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3823 [RTE_FC_NONE] = I40E_FC_NONE,
3824 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3825 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3826 [RTE_FC_FULL] = I40E_FC_FULL
3829 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3831 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3832 if ((fc_conf->high_water > max_high_water) ||
3833 (fc_conf->high_water < fc_conf->low_water)) {
3835 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3840 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3841 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3842 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3844 pf->fc_conf.pause_time = fc_conf->pause_time;
3845 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3846 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3848 PMD_INIT_FUNC_TRACE();
3850 /* All the link flow control related enable/disable register
3851 * configuration is handle by the F/W
3853 err = i40e_set_fc(hw, &aq_failure, true);
3857 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3858 /* Configure flow control refresh threshold,
3859 * the value for stat_tx_pause_refresh_timer[8]
3860 * is used for global pause operation.
3864 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3865 pf->fc_conf.pause_time);
3867 /* configure the timer value included in transmitted pause
3869 * the value for stat_tx_pause_quanta[8] is used for global
3872 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3873 pf->fc_conf.pause_time);
3875 fctrl_reg = I40E_READ_REG(hw,
3876 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3878 if (fc_conf->mac_ctrl_frame_fwd != 0)
3879 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3881 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3883 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3886 /* Configure pause time (2 TCs per register) */
3887 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3888 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3889 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3891 /* Configure flow control refresh threshold value */
3892 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3893 pf->fc_conf.pause_time / 2);
3895 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3897 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3898 *depending on configuration
3900 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3901 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3902 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3904 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3905 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3908 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3911 if (!pf->support_multi_driver) {
3912 /* config water marker both based on the packets and bytes */
3913 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3914 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3915 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3916 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3917 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3918 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3919 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3920 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3922 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3923 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3927 "Water marker configuration is not supported.");
3930 I40E_WRITE_FLUSH(hw);
3936 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3937 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3939 PMD_INIT_FUNC_TRACE();
3944 /* Add a MAC address, and update filters */
3946 i40e_macaddr_add(struct rte_eth_dev *dev,
3947 struct ether_addr *mac_addr,
3948 __rte_unused uint32_t index,
3951 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3952 struct i40e_mac_filter_info mac_filter;
3953 struct i40e_vsi *vsi;
3954 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3957 /* If VMDQ not enabled or configured, return */
3958 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3959 !pf->nb_cfg_vmdq_vsi)) {
3960 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3961 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3966 if (pool > pf->nb_cfg_vmdq_vsi) {
3967 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3968 pool, pf->nb_cfg_vmdq_vsi);
3972 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3973 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3974 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3976 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3981 vsi = pf->vmdq[pool - 1].vsi;
3983 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3984 if (ret != I40E_SUCCESS) {
3985 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3991 /* Remove a MAC address, and update filters */
3993 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3995 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3996 struct i40e_vsi *vsi;
3997 struct rte_eth_dev_data *data = dev->data;
3998 struct ether_addr *macaddr;
4003 macaddr = &(data->mac_addrs[index]);
4005 pool_sel = dev->data->mac_pool_sel[index];
4007 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4008 if (pool_sel & (1ULL << i)) {
4012 /* No VMDQ pool enabled or configured */
4013 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4014 (i > pf->nb_cfg_vmdq_vsi)) {
4016 "No VMDQ pool enabled/configured");
4019 vsi = pf->vmdq[i - 1].vsi;
4021 ret = i40e_vsi_delete_mac(vsi, macaddr);
4024 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4031 /* Set perfect match or hash match of MAC and VLAN for a VF */
4033 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4034 struct rte_eth_mac_filter *filter,
4038 struct i40e_mac_filter_info mac_filter;
4039 struct ether_addr old_mac;
4040 struct ether_addr *new_mac;
4041 struct i40e_pf_vf *vf = NULL;
4046 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4049 hw = I40E_PF_TO_HW(pf);
4051 if (filter == NULL) {
4052 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4056 new_mac = &filter->mac_addr;
4058 if (is_zero_ether_addr(new_mac)) {
4059 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4063 vf_id = filter->dst_id;
4065 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4066 PMD_DRV_LOG(ERR, "Invalid argument.");
4069 vf = &pf->vfs[vf_id];
4071 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
4072 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4077 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
4078 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4080 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4083 mac_filter.filter_type = filter->filter_type;
4084 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4085 if (ret != I40E_SUCCESS) {
4086 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4089 ether_addr_copy(new_mac, &pf->dev_addr);
4091 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4093 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4094 if (ret != I40E_SUCCESS) {
4095 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4099 /* Clear device address as it has been removed */
4100 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4101 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
4107 /* MAC filter handle */
4109 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4112 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4113 struct rte_eth_mac_filter *filter;
4114 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4115 int ret = I40E_NOT_SUPPORTED;
4117 filter = (struct rte_eth_mac_filter *)(arg);
4119 switch (filter_op) {
4120 case RTE_ETH_FILTER_NOP:
4123 case RTE_ETH_FILTER_ADD:
4124 i40e_pf_disable_irq0(hw);
4126 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4127 i40e_pf_enable_irq0(hw);
4129 case RTE_ETH_FILTER_DELETE:
4130 i40e_pf_disable_irq0(hw);
4132 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4133 i40e_pf_enable_irq0(hw);
4136 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4137 ret = I40E_ERR_PARAM;
4145 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4147 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4148 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4155 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4156 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4159 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4163 uint32_t *lut_dw = (uint32_t *)lut;
4164 uint16_t i, lut_size_dw = lut_size / 4;
4166 if (vsi->type == I40E_VSI_SRIOV) {
4167 for (i = 0; i <= lut_size_dw; i++) {
4168 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4169 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4172 for (i = 0; i < lut_size_dw; i++)
4173 lut_dw[i] = I40E_READ_REG(hw,
4182 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4191 pf = I40E_VSI_TO_PF(vsi);
4192 hw = I40E_VSI_TO_HW(vsi);
4194 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4195 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4198 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4202 uint32_t *lut_dw = (uint32_t *)lut;
4203 uint16_t i, lut_size_dw = lut_size / 4;
4205 if (vsi->type == I40E_VSI_SRIOV) {
4206 for (i = 0; i < lut_size_dw; i++)
4209 I40E_VFQF_HLUT1(i, vsi->user_param),
4212 for (i = 0; i < lut_size_dw; i++)
4213 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4216 I40E_WRITE_FLUSH(hw);
4223 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4224 struct rte_eth_rss_reta_entry64 *reta_conf,
4227 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4228 uint16_t i, lut_size = pf->hash_lut_size;
4229 uint16_t idx, shift;
4233 if (reta_size != lut_size ||
4234 reta_size > ETH_RSS_RETA_SIZE_512) {
4236 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4237 reta_size, lut_size);
4241 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4243 PMD_DRV_LOG(ERR, "No memory can be allocated");
4246 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4249 for (i = 0; i < reta_size; i++) {
4250 idx = i / RTE_RETA_GROUP_SIZE;
4251 shift = i % RTE_RETA_GROUP_SIZE;
4252 if (reta_conf[idx].mask & (1ULL << shift))
4253 lut[i] = reta_conf[idx].reta[shift];
4255 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4264 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4265 struct rte_eth_rss_reta_entry64 *reta_conf,
4268 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4269 uint16_t i, lut_size = pf->hash_lut_size;
4270 uint16_t idx, shift;
4274 if (reta_size != lut_size ||
4275 reta_size > ETH_RSS_RETA_SIZE_512) {
4277 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4278 reta_size, lut_size);
4282 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4284 PMD_DRV_LOG(ERR, "No memory can be allocated");
4288 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4291 for (i = 0; i < reta_size; i++) {
4292 idx = i / RTE_RETA_GROUP_SIZE;
4293 shift = i % RTE_RETA_GROUP_SIZE;
4294 if (reta_conf[idx].mask & (1ULL << shift))
4295 reta_conf[idx].reta[shift] = lut[i];
4305 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4306 * @hw: pointer to the HW structure
4307 * @mem: pointer to mem struct to fill out
4308 * @size: size of memory requested
4309 * @alignment: what to align the allocation to
4311 enum i40e_status_code
4312 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4313 struct i40e_dma_mem *mem,
4317 const struct rte_memzone *mz = NULL;
4318 char z_name[RTE_MEMZONE_NAMESIZE];
4321 return I40E_ERR_PARAM;
4323 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4324 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4325 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4327 return I40E_ERR_NO_MEMORY;
4332 mem->zone = (const void *)mz;
4334 "memzone %s allocated with physical address: %"PRIu64,
4337 return I40E_SUCCESS;
4341 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4342 * @hw: pointer to the HW structure
4343 * @mem: ptr to mem struct to free
4345 enum i40e_status_code
4346 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4347 struct i40e_dma_mem *mem)
4350 return I40E_ERR_PARAM;
4353 "memzone %s to be freed with physical address: %"PRIu64,
4354 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4355 rte_memzone_free((const struct rte_memzone *)mem->zone);
4360 return I40E_SUCCESS;
4364 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4365 * @hw: pointer to the HW structure
4366 * @mem: pointer to mem struct to fill out
4367 * @size: size of memory requested
4369 enum i40e_status_code
4370 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4371 struct i40e_virt_mem *mem,
4375 return I40E_ERR_PARAM;
4378 mem->va = rte_zmalloc("i40e", size, 0);
4381 return I40E_SUCCESS;
4383 return I40E_ERR_NO_MEMORY;
4387 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4388 * @hw: pointer to the HW structure
4389 * @mem: pointer to mem struct to free
4391 enum i40e_status_code
4392 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4393 struct i40e_virt_mem *mem)
4396 return I40E_ERR_PARAM;
4401 return I40E_SUCCESS;
4405 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4407 rte_spinlock_init(&sp->spinlock);
4411 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4413 rte_spinlock_lock(&sp->spinlock);
4417 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4419 rte_spinlock_unlock(&sp->spinlock);
4423 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4429 * Get the hardware capabilities, which will be parsed
4430 * and saved into struct i40e_hw.
4433 i40e_get_cap(struct i40e_hw *hw)
4435 struct i40e_aqc_list_capabilities_element_resp *buf;
4436 uint16_t len, size = 0;
4439 /* Calculate a huge enough buff for saving response data temporarily */
4440 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4441 I40E_MAX_CAP_ELE_NUM;
4442 buf = rte_zmalloc("i40e", len, 0);
4444 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4445 return I40E_ERR_NO_MEMORY;
4448 /* Get, parse the capabilities and save it to hw */
4449 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4450 i40e_aqc_opc_list_func_capabilities, NULL);
4451 if (ret != I40E_SUCCESS)
4452 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4454 /* Free the temporary buffer after being used */
4460 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4462 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4470 pf = (struct i40e_pf *)opaque;
4474 num = strtoul(value, &end, 0);
4475 if (errno != 0 || end == value || *end != 0) {
4476 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4477 "kept the value = %hu", value, pf->vf_nb_qp_max);
4481 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4482 pf->vf_nb_qp_max = (uint16_t)num;
4484 /* here return 0 to make next valid same argument work */
4485 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4486 "power of 2 and equal or less than 16 !, Now it is "
4487 "kept the value = %hu", num, pf->vf_nb_qp_max);
4492 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4494 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4495 struct rte_kvargs *kvlist;
4498 /* set default queue number per VF as 4 */
4499 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4501 if (dev->device->devargs == NULL)
4504 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4508 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4509 if (!kvargs_count) {
4510 rte_kvargs_free(kvlist);
4514 if (kvargs_count > 1)
4515 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4516 "the first invalid or last valid one is used !",
4517 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4519 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4520 i40e_pf_parse_vf_queue_number_handler, pf);
4522 rte_kvargs_free(kvlist);
4528 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4530 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4531 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4532 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4533 uint16_t qp_count = 0, vsi_count = 0;
4535 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4536 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4540 i40e_pf_config_vf_rxq_number(dev);
4542 /* Add the parameter init for LFC */
4543 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4544 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4545 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4547 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4548 pf->max_num_vsi = hw->func_caps.num_vsis;
4549 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4550 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4552 /* FDir queue/VSI allocation */
4553 pf->fdir_qp_offset = 0;
4554 if (hw->func_caps.fd) {
4555 pf->flags |= I40E_FLAG_FDIR;
4556 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4558 pf->fdir_nb_qps = 0;
4560 qp_count += pf->fdir_nb_qps;
4563 /* LAN queue/VSI allocation */
4564 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4565 if (!hw->func_caps.rss) {
4568 pf->flags |= I40E_FLAG_RSS;
4569 if (hw->mac.type == I40E_MAC_X722)
4570 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4571 pf->lan_nb_qps = pf->lan_nb_qp_max;
4573 qp_count += pf->lan_nb_qps;
4576 /* VF queue/VSI allocation */
4577 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4578 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4579 pf->flags |= I40E_FLAG_SRIOV;
4580 pf->vf_nb_qps = pf->vf_nb_qp_max;
4581 pf->vf_num = pci_dev->max_vfs;
4583 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4584 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4589 qp_count += pf->vf_nb_qps * pf->vf_num;
4590 vsi_count += pf->vf_num;
4592 /* VMDq queue/VSI allocation */
4593 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4594 pf->vmdq_nb_qps = 0;
4595 pf->max_nb_vmdq_vsi = 0;
4596 if (hw->func_caps.vmdq) {
4597 if (qp_count < hw->func_caps.num_tx_qp &&
4598 vsi_count < hw->func_caps.num_vsis) {
4599 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4600 qp_count) / pf->vmdq_nb_qp_max;
4602 /* Limit the maximum number of VMDq vsi to the maximum
4603 * ethdev can support
4605 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4606 hw->func_caps.num_vsis - vsi_count);
4607 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4609 if (pf->max_nb_vmdq_vsi) {
4610 pf->flags |= I40E_FLAG_VMDQ;
4611 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4613 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4614 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4615 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4618 "No enough queues left for VMDq");
4621 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4624 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4625 vsi_count += pf->max_nb_vmdq_vsi;
4627 if (hw->func_caps.dcb)
4628 pf->flags |= I40E_FLAG_DCB;
4630 if (qp_count > hw->func_caps.num_tx_qp) {
4632 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4633 qp_count, hw->func_caps.num_tx_qp);
4636 if (vsi_count > hw->func_caps.num_vsis) {
4638 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4639 vsi_count, hw->func_caps.num_vsis);
4647 i40e_pf_get_switch_config(struct i40e_pf *pf)
4649 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4650 struct i40e_aqc_get_switch_config_resp *switch_config;
4651 struct i40e_aqc_switch_config_element_resp *element;
4652 uint16_t start_seid = 0, num_reported;
4655 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4656 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4657 if (!switch_config) {
4658 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4662 /* Get the switch configurations */
4663 ret = i40e_aq_get_switch_config(hw, switch_config,
4664 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4665 if (ret != I40E_SUCCESS) {
4666 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4669 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4670 if (num_reported != 1) { /* The number should be 1 */
4671 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4675 /* Parse the switch configuration elements */
4676 element = &(switch_config->element[0]);
4677 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4678 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4679 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4681 PMD_DRV_LOG(INFO, "Unknown element type");
4684 rte_free(switch_config);
4690 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4693 struct pool_entry *entry;
4695 if (pool == NULL || num == 0)
4698 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4699 if (entry == NULL) {
4700 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4704 /* queue heap initialize */
4705 pool->num_free = num;
4706 pool->num_alloc = 0;
4708 LIST_INIT(&pool->alloc_list);
4709 LIST_INIT(&pool->free_list);
4711 /* Initialize element */
4715 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4720 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4722 struct pool_entry *entry, *next_entry;
4727 for (entry = LIST_FIRST(&pool->alloc_list);
4728 entry && (next_entry = LIST_NEXT(entry, next), 1);
4729 entry = next_entry) {
4730 LIST_REMOVE(entry, next);
4734 for (entry = LIST_FIRST(&pool->free_list);
4735 entry && (next_entry = LIST_NEXT(entry, next), 1);
4736 entry = next_entry) {
4737 LIST_REMOVE(entry, next);
4742 pool->num_alloc = 0;
4744 LIST_INIT(&pool->alloc_list);
4745 LIST_INIT(&pool->free_list);
4749 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4752 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4753 uint32_t pool_offset;
4757 PMD_DRV_LOG(ERR, "Invalid parameter");
4761 pool_offset = base - pool->base;
4762 /* Lookup in alloc list */
4763 LIST_FOREACH(entry, &pool->alloc_list, next) {
4764 if (entry->base == pool_offset) {
4765 valid_entry = entry;
4766 LIST_REMOVE(entry, next);
4771 /* Not find, return */
4772 if (valid_entry == NULL) {
4773 PMD_DRV_LOG(ERR, "Failed to find entry");
4778 * Found it, move it to free list and try to merge.
4779 * In order to make merge easier, always sort it by qbase.
4780 * Find adjacent prev and last entries.
4783 LIST_FOREACH(entry, &pool->free_list, next) {
4784 if (entry->base > valid_entry->base) {
4792 /* Try to merge with next one*/
4794 /* Merge with next one */
4795 if (valid_entry->base + valid_entry->len == next->base) {
4796 next->base = valid_entry->base;
4797 next->len += valid_entry->len;
4798 rte_free(valid_entry);
4805 /* Merge with previous one */
4806 if (prev->base + prev->len == valid_entry->base) {
4807 prev->len += valid_entry->len;
4808 /* If it merge with next one, remove next node */
4810 LIST_REMOVE(valid_entry, next);
4811 rte_free(valid_entry);
4813 rte_free(valid_entry);
4819 /* Not find any entry to merge, insert */
4822 LIST_INSERT_AFTER(prev, valid_entry, next);
4823 else if (next != NULL)
4824 LIST_INSERT_BEFORE(next, valid_entry, next);
4825 else /* It's empty list, insert to head */
4826 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4829 pool->num_free += valid_entry->len;
4830 pool->num_alloc -= valid_entry->len;
4836 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4839 struct pool_entry *entry, *valid_entry;
4841 if (pool == NULL || num == 0) {
4842 PMD_DRV_LOG(ERR, "Invalid parameter");
4846 if (pool->num_free < num) {
4847 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4848 num, pool->num_free);
4853 /* Lookup in free list and find most fit one */
4854 LIST_FOREACH(entry, &pool->free_list, next) {
4855 if (entry->len >= num) {
4857 if (entry->len == num) {
4858 valid_entry = entry;
4861 if (valid_entry == NULL || valid_entry->len > entry->len)
4862 valid_entry = entry;
4866 /* Not find one to satisfy the request, return */
4867 if (valid_entry == NULL) {
4868 PMD_DRV_LOG(ERR, "No valid entry found");
4872 * The entry have equal queue number as requested,
4873 * remove it from alloc_list.
4875 if (valid_entry->len == num) {
4876 LIST_REMOVE(valid_entry, next);
4879 * The entry have more numbers than requested,
4880 * create a new entry for alloc_list and minus its
4881 * queue base and number in free_list.
4883 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4884 if (entry == NULL) {
4886 "Failed to allocate memory for resource pool");
4889 entry->base = valid_entry->base;
4891 valid_entry->base += num;
4892 valid_entry->len -= num;
4893 valid_entry = entry;
4896 /* Insert it into alloc list, not sorted */
4897 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4899 pool->num_free -= valid_entry->len;
4900 pool->num_alloc += valid_entry->len;
4902 return valid_entry->base + pool->base;
4906 * bitmap_is_subset - Check whether src2 is subset of src1
4909 bitmap_is_subset(uint8_t src1, uint8_t src2)
4911 return !((src1 ^ src2) & src2);
4914 static enum i40e_status_code
4915 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4917 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4919 /* If DCB is not supported, only default TC is supported */
4920 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4921 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4922 return I40E_NOT_SUPPORTED;
4925 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4927 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4928 hw->func_caps.enabled_tcmap, enabled_tcmap);
4929 return I40E_NOT_SUPPORTED;
4931 return I40E_SUCCESS;
4935 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4936 struct i40e_vsi_vlan_pvid_info *info)
4939 struct i40e_vsi_context ctxt;
4940 uint8_t vlan_flags = 0;
4943 if (vsi == NULL || info == NULL) {
4944 PMD_DRV_LOG(ERR, "invalid parameters");
4945 return I40E_ERR_PARAM;
4949 vsi->info.pvid = info->config.pvid;
4951 * If insert pvid is enabled, only tagged pkts are
4952 * allowed to be sent out.
4954 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4955 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4958 if (info->config.reject.tagged == 0)
4959 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4961 if (info->config.reject.untagged == 0)
4962 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4964 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4965 I40E_AQ_VSI_PVLAN_MODE_MASK);
4966 vsi->info.port_vlan_flags |= vlan_flags;
4967 vsi->info.valid_sections =
4968 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4969 memset(&ctxt, 0, sizeof(ctxt));
4970 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4971 ctxt.seid = vsi->seid;
4973 hw = I40E_VSI_TO_HW(vsi);
4974 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4975 if (ret != I40E_SUCCESS)
4976 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4982 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4984 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4986 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4988 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4989 if (ret != I40E_SUCCESS)
4993 PMD_DRV_LOG(ERR, "seid not valid");
4997 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4998 tc_bw_data.tc_valid_bits = enabled_tcmap;
4999 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5000 tc_bw_data.tc_bw_credits[i] =
5001 (enabled_tcmap & (1 << i)) ? 1 : 0;
5003 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5004 if (ret != I40E_SUCCESS) {
5005 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5009 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5010 sizeof(vsi->info.qs_handle));
5011 return I40E_SUCCESS;
5014 static enum i40e_status_code
5015 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5016 struct i40e_aqc_vsi_properties_data *info,
5017 uint8_t enabled_tcmap)
5019 enum i40e_status_code ret;
5020 int i, total_tc = 0;
5021 uint16_t qpnum_per_tc, bsf, qp_idx;
5023 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5024 if (ret != I40E_SUCCESS)
5027 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5028 if (enabled_tcmap & (1 << i))
5032 vsi->enabled_tc = enabled_tcmap;
5034 /* Number of queues per enabled TC */
5035 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5036 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5037 bsf = rte_bsf32(qpnum_per_tc);
5039 /* Adjust the queue number to actual queues that can be applied */
5040 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5041 vsi->nb_qps = qpnum_per_tc * total_tc;
5044 * Configure TC and queue mapping parameters, for enabled TC,
5045 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5046 * default queue will serve it.
5049 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5050 if (vsi->enabled_tc & (1 << i)) {
5051 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5052 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5053 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5054 qp_idx += qpnum_per_tc;
5056 info->tc_mapping[i] = 0;
5059 /* Associate queue number with VSI */
5060 if (vsi->type == I40E_VSI_SRIOV) {
5061 info->mapping_flags |=
5062 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5063 for (i = 0; i < vsi->nb_qps; i++)
5064 info->queue_mapping[i] =
5065 rte_cpu_to_le_16(vsi->base_queue + i);
5067 info->mapping_flags |=
5068 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5069 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5071 info->valid_sections |=
5072 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5074 return I40E_SUCCESS;
5078 i40e_veb_release(struct i40e_veb *veb)
5080 struct i40e_vsi *vsi;
5086 if (!TAILQ_EMPTY(&veb->head)) {
5087 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5090 /* associate_vsi field is NULL for floating VEB */
5091 if (veb->associate_vsi != NULL) {
5092 vsi = veb->associate_vsi;
5093 hw = I40E_VSI_TO_HW(vsi);
5095 vsi->uplink_seid = veb->uplink_seid;
5098 veb->associate_pf->main_vsi->floating_veb = NULL;
5099 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5102 i40e_aq_delete_element(hw, veb->seid, NULL);
5104 return I40E_SUCCESS;
5108 static struct i40e_veb *
5109 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5111 struct i40e_veb *veb;
5117 "veb setup failed, associated PF shouldn't null");
5120 hw = I40E_PF_TO_HW(pf);
5122 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5124 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5128 veb->associate_vsi = vsi;
5129 veb->associate_pf = pf;
5130 TAILQ_INIT(&veb->head);
5131 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5133 /* create floating veb if vsi is NULL */
5135 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5136 I40E_DEFAULT_TCMAP, false,
5137 &veb->seid, false, NULL);
5139 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5140 true, &veb->seid, false, NULL);
5143 if (ret != I40E_SUCCESS) {
5144 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5145 hw->aq.asq_last_status);
5148 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5150 /* get statistics index */
5151 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5152 &veb->stats_idx, NULL, NULL, NULL);
5153 if (ret != I40E_SUCCESS) {
5154 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5155 hw->aq.asq_last_status);
5158 /* Get VEB bandwidth, to be implemented */
5159 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5161 vsi->uplink_seid = veb->seid;
5170 i40e_vsi_release(struct i40e_vsi *vsi)
5174 struct i40e_vsi_list *vsi_list;
5177 struct i40e_mac_filter *f;
5178 uint16_t user_param;
5181 return I40E_SUCCESS;
5186 user_param = vsi->user_param;
5188 pf = I40E_VSI_TO_PF(vsi);
5189 hw = I40E_VSI_TO_HW(vsi);
5191 /* VSI has child to attach, release child first */
5193 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5194 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5197 i40e_veb_release(vsi->veb);
5200 if (vsi->floating_veb) {
5201 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5202 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5207 /* Remove all macvlan filters of the VSI */
5208 i40e_vsi_remove_all_macvlan_filter(vsi);
5209 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5212 if (vsi->type != I40E_VSI_MAIN &&
5213 ((vsi->type != I40E_VSI_SRIOV) ||
5214 !pf->floating_veb_list[user_param])) {
5215 /* Remove vsi from parent's sibling list */
5216 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5217 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5218 return I40E_ERR_PARAM;
5220 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5221 &vsi->sib_vsi_list, list);
5223 /* Remove all switch element of the VSI */
5224 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5225 if (ret != I40E_SUCCESS)
5226 PMD_DRV_LOG(ERR, "Failed to delete element");
5229 if ((vsi->type == I40E_VSI_SRIOV) &&
5230 pf->floating_veb_list[user_param]) {
5231 /* Remove vsi from parent's sibling list */
5232 if (vsi->parent_vsi == NULL ||
5233 vsi->parent_vsi->floating_veb == NULL) {
5234 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5235 return I40E_ERR_PARAM;
5237 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5238 &vsi->sib_vsi_list, list);
5240 /* Remove all switch element of the VSI */
5241 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5242 if (ret != I40E_SUCCESS)
5243 PMD_DRV_LOG(ERR, "Failed to delete element");
5246 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5248 if (vsi->type != I40E_VSI_SRIOV)
5249 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5252 return I40E_SUCCESS;
5256 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5258 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5259 struct i40e_aqc_remove_macvlan_element_data def_filter;
5260 struct i40e_mac_filter_info filter;
5263 if (vsi->type != I40E_VSI_MAIN)
5264 return I40E_ERR_CONFIG;
5265 memset(&def_filter, 0, sizeof(def_filter));
5266 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5268 def_filter.vlan_tag = 0;
5269 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5270 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5271 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5272 if (ret != I40E_SUCCESS) {
5273 struct i40e_mac_filter *f;
5274 struct ether_addr *mac;
5277 "Cannot remove the default macvlan filter");
5278 /* It needs to add the permanent mac into mac list */
5279 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5281 PMD_DRV_LOG(ERR, "failed to allocate memory");
5282 return I40E_ERR_NO_MEMORY;
5284 mac = &f->mac_info.mac_addr;
5285 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5287 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5288 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5293 rte_memcpy(&filter.mac_addr,
5294 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5295 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5296 return i40e_vsi_add_mac(vsi, &filter);
5300 * i40e_vsi_get_bw_config - Query VSI BW Information
5301 * @vsi: the VSI to be queried
5303 * Returns 0 on success, negative value on failure
5305 static enum i40e_status_code
5306 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5308 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5309 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5310 struct i40e_hw *hw = &vsi->adapter->hw;
5315 memset(&bw_config, 0, sizeof(bw_config));
5316 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5317 if (ret != I40E_SUCCESS) {
5318 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5319 hw->aq.asq_last_status);
5323 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5324 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5325 &ets_sla_config, NULL);
5326 if (ret != I40E_SUCCESS) {
5328 "VSI failed to get TC bandwdith configuration %u",
5329 hw->aq.asq_last_status);
5333 /* store and print out BW info */
5334 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5335 vsi->bw_info.bw_max = bw_config.max_bw;
5336 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5337 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5338 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5339 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5341 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5342 vsi->bw_info.bw_ets_share_credits[i] =
5343 ets_sla_config.share_credits[i];
5344 vsi->bw_info.bw_ets_credits[i] =
5345 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5346 /* 4 bits per TC, 4th bit is reserved */
5347 vsi->bw_info.bw_ets_max[i] =
5348 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5349 RTE_LEN2MASK(3, uint8_t));
5350 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5351 vsi->bw_info.bw_ets_share_credits[i]);
5352 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5353 vsi->bw_info.bw_ets_credits[i]);
5354 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5355 vsi->bw_info.bw_ets_max[i]);
5358 return I40E_SUCCESS;
5361 /* i40e_enable_pf_lb
5362 * @pf: pointer to the pf structure
5364 * allow loopback on pf
5367 i40e_enable_pf_lb(struct i40e_pf *pf)
5369 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5370 struct i40e_vsi_context ctxt;
5373 /* Use the FW API if FW >= v5.0 */
5374 if (hw->aq.fw_maj_ver < 5) {
5375 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5379 memset(&ctxt, 0, sizeof(ctxt));
5380 ctxt.seid = pf->main_vsi_seid;
5381 ctxt.pf_num = hw->pf_id;
5382 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5384 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5385 ret, hw->aq.asq_last_status);
5388 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5389 ctxt.info.valid_sections =
5390 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5391 ctxt.info.switch_id |=
5392 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5394 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5396 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5397 hw->aq.asq_last_status);
5402 i40e_vsi_setup(struct i40e_pf *pf,
5403 enum i40e_vsi_type type,
5404 struct i40e_vsi *uplink_vsi,
5405 uint16_t user_param)
5407 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5408 struct i40e_vsi *vsi;
5409 struct i40e_mac_filter_info filter;
5411 struct i40e_vsi_context ctxt;
5412 struct ether_addr broadcast =
5413 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5415 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5416 uplink_vsi == NULL) {
5418 "VSI setup failed, VSI link shouldn't be NULL");
5422 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5424 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5429 * 1.type is not MAIN and uplink vsi is not NULL
5430 * If uplink vsi didn't setup VEB, create one first under veb field
5431 * 2.type is SRIOV and the uplink is NULL
5432 * If floating VEB is NULL, create one veb under floating veb field
5435 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5436 uplink_vsi->veb == NULL) {
5437 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5439 if (uplink_vsi->veb == NULL) {
5440 PMD_DRV_LOG(ERR, "VEB setup failed");
5443 /* set ALLOWLOOPBACk on pf, when veb is created */
5444 i40e_enable_pf_lb(pf);
5447 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5448 pf->main_vsi->floating_veb == NULL) {
5449 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5451 if (pf->main_vsi->floating_veb == NULL) {
5452 PMD_DRV_LOG(ERR, "VEB setup failed");
5457 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5459 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5462 TAILQ_INIT(&vsi->mac_list);
5464 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5465 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5466 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5467 vsi->user_param = user_param;
5468 vsi->vlan_anti_spoof_on = 0;
5469 vsi->vlan_filter_on = 0;
5470 /* Allocate queues */
5471 switch (vsi->type) {
5472 case I40E_VSI_MAIN :
5473 vsi->nb_qps = pf->lan_nb_qps;
5475 case I40E_VSI_SRIOV :
5476 vsi->nb_qps = pf->vf_nb_qps;
5478 case I40E_VSI_VMDQ2:
5479 vsi->nb_qps = pf->vmdq_nb_qps;
5482 vsi->nb_qps = pf->fdir_nb_qps;
5488 * The filter status descriptor is reported in rx queue 0,
5489 * while the tx queue for fdir filter programming has no
5490 * such constraints, can be non-zero queues.
5491 * To simplify it, choose FDIR vsi use queue 0 pair.
5492 * To make sure it will use queue 0 pair, queue allocation
5493 * need be done before this function is called
5495 if (type != I40E_VSI_FDIR) {
5496 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5498 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5502 vsi->base_queue = ret;
5504 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5506 /* VF has MSIX interrupt in VF range, don't allocate here */
5507 if (type == I40E_VSI_MAIN) {
5508 if (pf->support_multi_driver) {
5509 /* If support multi-driver, need to use INT0 instead of
5510 * allocating from msix pool. The Msix pool is init from
5511 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5512 * to 1 without calling i40e_res_pool_alloc.
5517 ret = i40e_res_pool_alloc(&pf->msix_pool,
5518 RTE_MIN(vsi->nb_qps,
5519 RTE_MAX_RXTX_INTR_VEC_ID));
5522 "VSI MAIN %d get heap failed %d",
5524 goto fail_queue_alloc;
5526 vsi->msix_intr = ret;
5527 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5528 RTE_MAX_RXTX_INTR_VEC_ID);
5530 } else if (type != I40E_VSI_SRIOV) {
5531 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5533 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5534 goto fail_queue_alloc;
5536 vsi->msix_intr = ret;
5544 if (type == I40E_VSI_MAIN) {
5545 /* For main VSI, no need to add since it's default one */
5546 vsi->uplink_seid = pf->mac_seid;
5547 vsi->seid = pf->main_vsi_seid;
5548 /* Bind queues with specific MSIX interrupt */
5550 * Needs 2 interrupt at least, one for misc cause which will
5551 * enabled from OS side, Another for queues binding the
5552 * interrupt from device side only.
5555 /* Get default VSI parameters from hardware */
5556 memset(&ctxt, 0, sizeof(ctxt));
5557 ctxt.seid = vsi->seid;
5558 ctxt.pf_num = hw->pf_id;
5559 ctxt.uplink_seid = vsi->uplink_seid;
5561 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5562 if (ret != I40E_SUCCESS) {
5563 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5564 goto fail_msix_alloc;
5566 rte_memcpy(&vsi->info, &ctxt.info,
5567 sizeof(struct i40e_aqc_vsi_properties_data));
5568 vsi->vsi_id = ctxt.vsi_number;
5569 vsi->info.valid_sections = 0;
5571 /* Configure tc, enabled TC0 only */
5572 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5574 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5575 goto fail_msix_alloc;
5578 /* TC, queue mapping */
5579 memset(&ctxt, 0, sizeof(ctxt));
5580 vsi->info.valid_sections |=
5581 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5582 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5583 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5584 rte_memcpy(&ctxt.info, &vsi->info,
5585 sizeof(struct i40e_aqc_vsi_properties_data));
5586 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5587 I40E_DEFAULT_TCMAP);
5588 if (ret != I40E_SUCCESS) {
5590 "Failed to configure TC queue mapping");
5591 goto fail_msix_alloc;
5593 ctxt.seid = vsi->seid;
5594 ctxt.pf_num = hw->pf_id;
5595 ctxt.uplink_seid = vsi->uplink_seid;
5598 /* Update VSI parameters */
5599 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5600 if (ret != I40E_SUCCESS) {
5601 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5602 goto fail_msix_alloc;
5605 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5606 sizeof(vsi->info.tc_mapping));
5607 rte_memcpy(&vsi->info.queue_mapping,
5608 &ctxt.info.queue_mapping,
5609 sizeof(vsi->info.queue_mapping));
5610 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5611 vsi->info.valid_sections = 0;
5613 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5617 * Updating default filter settings are necessary to prevent
5618 * reception of tagged packets.
5619 * Some old firmware configurations load a default macvlan
5620 * filter which accepts both tagged and untagged packets.
5621 * The updating is to use a normal filter instead if needed.
5622 * For NVM 4.2.2 or after, the updating is not needed anymore.
5623 * The firmware with correct configurations load the default
5624 * macvlan filter which is expected and cannot be removed.
5626 i40e_update_default_filter_setting(vsi);
5627 i40e_config_qinq(hw, vsi);
5628 } else if (type == I40E_VSI_SRIOV) {
5629 memset(&ctxt, 0, sizeof(ctxt));
5631 * For other VSI, the uplink_seid equals to uplink VSI's
5632 * uplink_seid since they share same VEB
5634 if (uplink_vsi == NULL)
5635 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5637 vsi->uplink_seid = uplink_vsi->uplink_seid;
5638 ctxt.pf_num = hw->pf_id;
5639 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5640 ctxt.uplink_seid = vsi->uplink_seid;
5641 ctxt.connection_type = 0x1;
5642 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5644 /* Use the VEB configuration if FW >= v5.0 */
5645 if (hw->aq.fw_maj_ver >= 5) {
5646 /* Configure switch ID */
5647 ctxt.info.valid_sections |=
5648 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5649 ctxt.info.switch_id =
5650 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5653 /* Configure port/vlan */
5654 ctxt.info.valid_sections |=
5655 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5656 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5657 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5658 hw->func_caps.enabled_tcmap);
5659 if (ret != I40E_SUCCESS) {
5661 "Failed to configure TC queue mapping");
5662 goto fail_msix_alloc;
5665 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5666 ctxt.info.valid_sections |=
5667 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5669 * Since VSI is not created yet, only configure parameter,
5670 * will add vsi below.
5673 i40e_config_qinq(hw, vsi);
5674 } else if (type == I40E_VSI_VMDQ2) {
5675 memset(&ctxt, 0, sizeof(ctxt));
5677 * For other VSI, the uplink_seid equals to uplink VSI's
5678 * uplink_seid since they share same VEB
5680 vsi->uplink_seid = uplink_vsi->uplink_seid;
5681 ctxt.pf_num = hw->pf_id;
5683 ctxt.uplink_seid = vsi->uplink_seid;
5684 ctxt.connection_type = 0x1;
5685 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5687 ctxt.info.valid_sections |=
5688 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5689 /* user_param carries flag to enable loop back */
5691 ctxt.info.switch_id =
5692 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5693 ctxt.info.switch_id |=
5694 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5697 /* Configure port/vlan */
5698 ctxt.info.valid_sections |=
5699 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5700 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5701 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5702 I40E_DEFAULT_TCMAP);
5703 if (ret != I40E_SUCCESS) {
5705 "Failed to configure TC queue mapping");
5706 goto fail_msix_alloc;
5708 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5709 ctxt.info.valid_sections |=
5710 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5711 } else if (type == I40E_VSI_FDIR) {
5712 memset(&ctxt, 0, sizeof(ctxt));
5713 vsi->uplink_seid = uplink_vsi->uplink_seid;
5714 ctxt.pf_num = hw->pf_id;
5716 ctxt.uplink_seid = vsi->uplink_seid;
5717 ctxt.connection_type = 0x1; /* regular data port */
5718 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5719 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5720 I40E_DEFAULT_TCMAP);
5721 if (ret != I40E_SUCCESS) {
5723 "Failed to configure TC queue mapping.");
5724 goto fail_msix_alloc;
5726 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5727 ctxt.info.valid_sections |=
5728 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5730 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5731 goto fail_msix_alloc;
5734 if (vsi->type != I40E_VSI_MAIN) {
5735 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5736 if (ret != I40E_SUCCESS) {
5737 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5738 hw->aq.asq_last_status);
5739 goto fail_msix_alloc;
5741 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5742 vsi->info.valid_sections = 0;
5743 vsi->seid = ctxt.seid;
5744 vsi->vsi_id = ctxt.vsi_number;
5745 vsi->sib_vsi_list.vsi = vsi;
5746 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5747 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5748 &vsi->sib_vsi_list, list);
5750 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5751 &vsi->sib_vsi_list, list);
5755 /* MAC/VLAN configuration */
5756 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5757 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5759 ret = i40e_vsi_add_mac(vsi, &filter);
5760 if (ret != I40E_SUCCESS) {
5761 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5762 goto fail_msix_alloc;
5765 /* Get VSI BW information */
5766 i40e_vsi_get_bw_config(vsi);
5769 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5771 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5777 /* Configure vlan filter on or off */
5779 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5782 struct i40e_mac_filter *f;
5784 struct i40e_mac_filter_info *mac_filter;
5785 enum rte_mac_filter_type desired_filter;
5786 int ret = I40E_SUCCESS;
5789 /* Filter to match MAC and VLAN */
5790 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5792 /* Filter to match only MAC */
5793 desired_filter = RTE_MAC_PERFECT_MATCH;
5798 mac_filter = rte_zmalloc("mac_filter_info_data",
5799 num * sizeof(*mac_filter), 0);
5800 if (mac_filter == NULL) {
5801 PMD_DRV_LOG(ERR, "failed to allocate memory");
5802 return I40E_ERR_NO_MEMORY;
5807 /* Remove all existing mac */
5808 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5809 mac_filter[i] = f->mac_info;
5810 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5812 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5813 on ? "enable" : "disable");
5819 /* Override with new filter */
5820 for (i = 0; i < num; i++) {
5821 mac_filter[i].filter_type = desired_filter;
5822 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5824 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5825 on ? "enable" : "disable");
5831 rte_free(mac_filter);
5835 /* Configure vlan stripping on or off */
5837 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5839 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5840 struct i40e_vsi_context ctxt;
5842 int ret = I40E_SUCCESS;
5844 /* Check if it has been already on or off */
5845 if (vsi->info.valid_sections &
5846 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5848 if ((vsi->info.port_vlan_flags &
5849 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5850 return 0; /* already on */
5852 if ((vsi->info.port_vlan_flags &
5853 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5854 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5855 return 0; /* already off */
5860 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5862 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5863 vsi->info.valid_sections =
5864 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5865 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5866 vsi->info.port_vlan_flags |= vlan_flags;
5867 ctxt.seid = vsi->seid;
5868 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5869 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5871 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5872 on ? "enable" : "disable");
5878 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5880 struct rte_eth_dev_data *data = dev->data;
5884 /* Apply vlan offload setting */
5885 mask = ETH_VLAN_STRIP_MASK |
5886 ETH_VLAN_FILTER_MASK |
5887 ETH_VLAN_EXTEND_MASK;
5888 ret = i40e_vlan_offload_set(dev, mask);
5890 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5894 /* Apply pvid setting */
5895 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5896 data->dev_conf.txmode.hw_vlan_insert_pvid);
5898 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5904 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5906 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5908 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5912 i40e_update_flow_control(struct i40e_hw *hw)
5914 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5915 struct i40e_link_status link_status;
5916 uint32_t rxfc = 0, txfc = 0, reg;
5920 memset(&link_status, 0, sizeof(link_status));
5921 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5922 if (ret != I40E_SUCCESS) {
5923 PMD_DRV_LOG(ERR, "Failed to get link status information");
5924 goto write_reg; /* Disable flow control */
5927 an_info = hw->phy.link_info.an_info;
5928 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5929 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5930 ret = I40E_ERR_NOT_READY;
5931 goto write_reg; /* Disable flow control */
5934 * If link auto negotiation is enabled, flow control needs to
5935 * be configured according to it
5937 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5938 case I40E_LINK_PAUSE_RXTX:
5941 hw->fc.current_mode = I40E_FC_FULL;
5943 case I40E_AQ_LINK_PAUSE_RX:
5945 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5947 case I40E_AQ_LINK_PAUSE_TX:
5949 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5952 hw->fc.current_mode = I40E_FC_NONE;
5957 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5958 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5959 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5960 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5961 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5962 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5969 i40e_pf_setup(struct i40e_pf *pf)
5971 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5972 struct i40e_filter_control_settings settings;
5973 struct i40e_vsi *vsi;
5976 /* Clear all stats counters */
5977 pf->offset_loaded = FALSE;
5978 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5979 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5980 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5981 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5983 ret = i40e_pf_get_switch_config(pf);
5984 if (ret != I40E_SUCCESS) {
5985 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5989 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5991 PMD_INIT_LOG(WARNING,
5992 "failed to allocate switch domain for device %d", ret);
5994 if (pf->flags & I40E_FLAG_FDIR) {
5995 /* make queue allocated first, let FDIR use queue pair 0*/
5996 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5997 if (ret != I40E_FDIR_QUEUE_ID) {
5999 "queue allocation fails for FDIR: ret =%d",
6001 pf->flags &= ~I40E_FLAG_FDIR;
6004 /* main VSI setup */
6005 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6007 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6008 return I40E_ERR_NOT_READY;
6012 /* Configure filter control */
6013 memset(&settings, 0, sizeof(settings));
6014 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6015 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6016 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6017 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6019 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6020 hw->func_caps.rss_table_size);
6021 return I40E_ERR_PARAM;
6023 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6024 hw->func_caps.rss_table_size);
6025 pf->hash_lut_size = hw->func_caps.rss_table_size;
6027 /* Enable ethtype and macvlan filters */
6028 settings.enable_ethtype = TRUE;
6029 settings.enable_macvlan = TRUE;
6030 ret = i40e_set_filter_control(hw, &settings);
6032 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6035 /* Update flow control according to the auto negotiation */
6036 i40e_update_flow_control(hw);
6038 return I40E_SUCCESS;
6042 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6048 * Set or clear TX Queue Disable flags,
6049 * which is required by hardware.
6051 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6052 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6054 /* Wait until the request is finished */
6055 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6056 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6057 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6058 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6059 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6065 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6066 return I40E_SUCCESS; /* already on, skip next steps */
6068 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6069 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6071 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6072 return I40E_SUCCESS; /* already off, skip next steps */
6073 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6075 /* Write the register */
6076 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6077 /* Check the result */
6078 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6079 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6080 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6082 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6083 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6086 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6087 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6091 /* Check if it is timeout */
6092 if (j >= I40E_CHK_Q_ENA_COUNT) {
6093 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6094 (on ? "enable" : "disable"), q_idx);
6095 return I40E_ERR_TIMEOUT;
6098 return I40E_SUCCESS;
6101 /* Swith on or off the tx queues */
6103 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6105 struct rte_eth_dev_data *dev_data = pf->dev_data;
6106 struct i40e_tx_queue *txq;
6107 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6111 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6112 txq = dev_data->tx_queues[i];
6113 /* Don't operate the queue if not configured or
6114 * if starting only per queue */
6115 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6118 ret = i40e_dev_tx_queue_start(dev, i);
6120 ret = i40e_dev_tx_queue_stop(dev, i);
6121 if ( ret != I40E_SUCCESS)
6125 return I40E_SUCCESS;
6129 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6134 /* Wait until the request is finished */
6135 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6136 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6137 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6138 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6139 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6144 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6145 return I40E_SUCCESS; /* Already on, skip next steps */
6146 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6148 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6149 return I40E_SUCCESS; /* Already off, skip next steps */
6150 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6153 /* Write the register */
6154 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6155 /* Check the result */
6156 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6157 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6158 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6160 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6161 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6164 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6165 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6170 /* Check if it is timeout */
6171 if (j >= I40E_CHK_Q_ENA_COUNT) {
6172 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6173 (on ? "enable" : "disable"), q_idx);
6174 return I40E_ERR_TIMEOUT;
6177 return I40E_SUCCESS;
6179 /* Switch on or off the rx queues */
6181 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6183 struct rte_eth_dev_data *dev_data = pf->dev_data;
6184 struct i40e_rx_queue *rxq;
6185 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6189 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6190 rxq = dev_data->rx_queues[i];
6191 /* Don't operate the queue if not configured or
6192 * if starting only per queue */
6193 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6196 ret = i40e_dev_rx_queue_start(dev, i);
6198 ret = i40e_dev_rx_queue_stop(dev, i);
6199 if (ret != I40E_SUCCESS)
6203 return I40E_SUCCESS;
6206 /* Switch on or off all the rx/tx queues */
6208 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6213 /* enable rx queues before enabling tx queues */
6214 ret = i40e_dev_switch_rx_queues(pf, on);
6216 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6219 ret = i40e_dev_switch_tx_queues(pf, on);
6221 /* Stop tx queues before stopping rx queues */
6222 ret = i40e_dev_switch_tx_queues(pf, on);
6224 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6227 ret = i40e_dev_switch_rx_queues(pf, on);
6233 /* Initialize VSI for TX */
6235 i40e_dev_tx_init(struct i40e_pf *pf)
6237 struct rte_eth_dev_data *data = pf->dev_data;
6239 uint32_t ret = I40E_SUCCESS;
6240 struct i40e_tx_queue *txq;
6242 for (i = 0; i < data->nb_tx_queues; i++) {
6243 txq = data->tx_queues[i];
6244 if (!txq || !txq->q_set)
6246 ret = i40e_tx_queue_init(txq);
6247 if (ret != I40E_SUCCESS)
6250 if (ret == I40E_SUCCESS)
6251 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6257 /* Initialize VSI for RX */
6259 i40e_dev_rx_init(struct i40e_pf *pf)
6261 struct rte_eth_dev_data *data = pf->dev_data;
6262 int ret = I40E_SUCCESS;
6264 struct i40e_rx_queue *rxq;
6266 i40e_pf_config_mq_rx(pf);
6267 for (i = 0; i < data->nb_rx_queues; i++) {
6268 rxq = data->rx_queues[i];
6269 if (!rxq || !rxq->q_set)
6272 ret = i40e_rx_queue_init(rxq);
6273 if (ret != I40E_SUCCESS) {
6275 "Failed to do RX queue initialization");
6279 if (ret == I40E_SUCCESS)
6280 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6287 i40e_dev_rxtx_init(struct i40e_pf *pf)
6291 err = i40e_dev_tx_init(pf);
6293 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6296 err = i40e_dev_rx_init(pf);
6298 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6306 i40e_vmdq_setup(struct rte_eth_dev *dev)
6308 struct rte_eth_conf *conf = &dev->data->dev_conf;
6309 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6310 int i, err, conf_vsis, j, loop;
6311 struct i40e_vsi *vsi;
6312 struct i40e_vmdq_info *vmdq_info;
6313 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6314 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6317 * Disable interrupt to avoid message from VF. Furthermore, it will
6318 * avoid race condition in VSI creation/destroy.
6320 i40e_pf_disable_irq0(hw);
6322 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6323 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6327 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6328 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6329 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6330 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6331 pf->max_nb_vmdq_vsi);
6335 if (pf->vmdq != NULL) {
6336 PMD_INIT_LOG(INFO, "VMDQ already configured");
6340 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6341 sizeof(*vmdq_info) * conf_vsis, 0);
6343 if (pf->vmdq == NULL) {
6344 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6348 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6350 /* Create VMDQ VSI */
6351 for (i = 0; i < conf_vsis; i++) {
6352 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6353 vmdq_conf->enable_loop_back);
6355 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6359 vmdq_info = &pf->vmdq[i];
6361 vmdq_info->vsi = vsi;
6363 pf->nb_cfg_vmdq_vsi = conf_vsis;
6365 /* Configure Vlan */
6366 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6367 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6368 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6369 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6370 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6371 vmdq_conf->pool_map[i].vlan_id, j);
6373 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6374 vmdq_conf->pool_map[i].vlan_id);
6376 PMD_INIT_LOG(ERR, "Failed to add vlan");
6384 i40e_pf_enable_irq0(hw);
6389 for (i = 0; i < conf_vsis; i++)
6390 if (pf->vmdq[i].vsi == NULL)
6393 i40e_vsi_release(pf->vmdq[i].vsi);
6397 i40e_pf_enable_irq0(hw);
6402 i40e_stat_update_32(struct i40e_hw *hw,
6410 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6414 if (new_data >= *offset)
6415 *stat = (uint64_t)(new_data - *offset);
6417 *stat = (uint64_t)((new_data +
6418 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6422 i40e_stat_update_48(struct i40e_hw *hw,
6431 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6432 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6433 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6438 if (new_data >= *offset)
6439 *stat = new_data - *offset;
6441 *stat = (uint64_t)((new_data +
6442 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6444 *stat &= I40E_48_BIT_MASK;
6449 i40e_pf_disable_irq0(struct i40e_hw *hw)
6451 /* Disable all interrupt types */
6452 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6453 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6454 I40E_WRITE_FLUSH(hw);
6459 i40e_pf_enable_irq0(struct i40e_hw *hw)
6461 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6462 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6463 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6464 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6465 I40E_WRITE_FLUSH(hw);
6469 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6471 /* read pending request and disable first */
6472 i40e_pf_disable_irq0(hw);
6473 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6474 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6475 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6478 /* Link no queues with irq0 */
6479 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6480 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6484 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6486 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6487 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6490 uint32_t index, offset, val;
6495 * Try to find which VF trigger a reset, use absolute VF id to access
6496 * since the reg is global register.
6498 for (i = 0; i < pf->vf_num; i++) {
6499 abs_vf_id = hw->func_caps.vf_base_id + i;
6500 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6501 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6502 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6503 /* VFR event occurred */
6504 if (val & (0x1 << offset)) {
6507 /* Clear the event first */
6508 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6510 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6512 * Only notify a VF reset event occurred,
6513 * don't trigger another SW reset
6515 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6516 if (ret != I40E_SUCCESS)
6517 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6523 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6525 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6528 for (i = 0; i < pf->vf_num; i++)
6529 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6533 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6535 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6536 struct i40e_arq_event_info info;
6537 uint16_t pending, opcode;
6540 info.buf_len = I40E_AQ_BUF_SZ;
6541 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6542 if (!info.msg_buf) {
6543 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6549 ret = i40e_clean_arq_element(hw, &info, &pending);
6551 if (ret != I40E_SUCCESS) {
6553 "Failed to read msg from AdminQ, aq_err: %u",
6554 hw->aq.asq_last_status);
6557 opcode = rte_le_to_cpu_16(info.desc.opcode);
6560 case i40e_aqc_opc_send_msg_to_pf:
6561 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6562 i40e_pf_host_handle_vf_msg(dev,
6563 rte_le_to_cpu_16(info.desc.retval),
6564 rte_le_to_cpu_32(info.desc.cookie_high),
6565 rte_le_to_cpu_32(info.desc.cookie_low),
6569 case i40e_aqc_opc_get_link_status:
6570 ret = i40e_dev_link_update(dev, 0);
6572 _rte_eth_dev_callback_process(dev,
6573 RTE_ETH_EVENT_INTR_LSC, NULL);
6576 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6581 rte_free(info.msg_buf);
6585 * Interrupt handler triggered by NIC for handling
6586 * specific interrupt.
6589 * Pointer to interrupt handle.
6591 * The address of parameter (struct rte_eth_dev *) regsitered before.
6597 i40e_dev_interrupt_handler(void *param)
6599 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6600 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6603 /* Disable interrupt */
6604 i40e_pf_disable_irq0(hw);
6606 /* read out interrupt causes */
6607 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6609 /* No interrupt event indicated */
6610 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6611 PMD_DRV_LOG(INFO, "No interrupt event");
6614 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6615 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6616 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6617 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6618 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6619 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6620 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6621 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6622 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6623 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6624 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6625 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6626 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6627 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6629 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6630 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6631 i40e_dev_handle_vfr_event(dev);
6633 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6634 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6635 i40e_dev_handle_aq_msg(dev);
6639 /* Enable interrupt */
6640 i40e_pf_enable_irq0(hw);
6644 i40e_dev_alarm_handler(void *param)
6646 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6647 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6650 /* Disable interrupt */
6651 i40e_pf_disable_irq0(hw);
6653 /* read out interrupt causes */
6654 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6656 /* No interrupt event indicated */
6657 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6659 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6660 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6661 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6662 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6663 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6664 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6665 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6666 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6667 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6668 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6669 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6670 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6671 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6672 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6674 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6675 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6676 i40e_dev_handle_vfr_event(dev);
6678 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6679 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6680 i40e_dev_handle_aq_msg(dev);
6684 /* Enable interrupt */
6685 i40e_pf_enable_irq0(hw);
6686 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6687 i40e_dev_alarm_handler, dev);
6691 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6692 struct i40e_macvlan_filter *filter,
6695 int ele_num, ele_buff_size;
6696 int num, actual_num, i;
6698 int ret = I40E_SUCCESS;
6699 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6700 struct i40e_aqc_add_macvlan_element_data *req_list;
6702 if (filter == NULL || total == 0)
6703 return I40E_ERR_PARAM;
6704 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6705 ele_buff_size = hw->aq.asq_buf_size;
6707 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6708 if (req_list == NULL) {
6709 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6710 return I40E_ERR_NO_MEMORY;
6715 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6716 memset(req_list, 0, ele_buff_size);
6718 for (i = 0; i < actual_num; i++) {
6719 rte_memcpy(req_list[i].mac_addr,
6720 &filter[num + i].macaddr, ETH_ADDR_LEN);
6721 req_list[i].vlan_tag =
6722 rte_cpu_to_le_16(filter[num + i].vlan_id);
6724 switch (filter[num + i].filter_type) {
6725 case RTE_MAC_PERFECT_MATCH:
6726 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6727 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6729 case RTE_MACVLAN_PERFECT_MATCH:
6730 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6732 case RTE_MAC_HASH_MATCH:
6733 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6734 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6736 case RTE_MACVLAN_HASH_MATCH:
6737 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6740 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6741 ret = I40E_ERR_PARAM;
6745 req_list[i].queue_number = 0;
6747 req_list[i].flags = rte_cpu_to_le_16(flags);
6750 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6752 if (ret != I40E_SUCCESS) {
6753 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6757 } while (num < total);
6765 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6766 struct i40e_macvlan_filter *filter,
6769 int ele_num, ele_buff_size;
6770 int num, actual_num, i;
6772 int ret = I40E_SUCCESS;
6773 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6774 struct i40e_aqc_remove_macvlan_element_data *req_list;
6776 if (filter == NULL || total == 0)
6777 return I40E_ERR_PARAM;
6779 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6780 ele_buff_size = hw->aq.asq_buf_size;
6782 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6783 if (req_list == NULL) {
6784 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6785 return I40E_ERR_NO_MEMORY;
6790 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6791 memset(req_list, 0, ele_buff_size);
6793 for (i = 0; i < actual_num; i++) {
6794 rte_memcpy(req_list[i].mac_addr,
6795 &filter[num + i].macaddr, ETH_ADDR_LEN);
6796 req_list[i].vlan_tag =
6797 rte_cpu_to_le_16(filter[num + i].vlan_id);
6799 switch (filter[num + i].filter_type) {
6800 case RTE_MAC_PERFECT_MATCH:
6801 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6802 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6804 case RTE_MACVLAN_PERFECT_MATCH:
6805 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6807 case RTE_MAC_HASH_MATCH:
6808 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6809 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6811 case RTE_MACVLAN_HASH_MATCH:
6812 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6815 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6816 ret = I40E_ERR_PARAM;
6819 req_list[i].flags = rte_cpu_to_le_16(flags);
6822 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6824 if (ret != I40E_SUCCESS) {
6825 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6829 } while (num < total);
6836 /* Find out specific MAC filter */
6837 static struct i40e_mac_filter *
6838 i40e_find_mac_filter(struct i40e_vsi *vsi,
6839 struct ether_addr *macaddr)
6841 struct i40e_mac_filter *f;
6843 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6844 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6852 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6855 uint32_t vid_idx, vid_bit;
6857 if (vlan_id > ETH_VLAN_ID_MAX)
6860 vid_idx = I40E_VFTA_IDX(vlan_id);
6861 vid_bit = I40E_VFTA_BIT(vlan_id);
6863 if (vsi->vfta[vid_idx] & vid_bit)
6870 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6871 uint16_t vlan_id, bool on)
6873 uint32_t vid_idx, vid_bit;
6875 vid_idx = I40E_VFTA_IDX(vlan_id);
6876 vid_bit = I40E_VFTA_BIT(vlan_id);
6879 vsi->vfta[vid_idx] |= vid_bit;
6881 vsi->vfta[vid_idx] &= ~vid_bit;
6885 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6886 uint16_t vlan_id, bool on)
6888 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6889 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6892 if (vlan_id > ETH_VLAN_ID_MAX)
6895 i40e_store_vlan_filter(vsi, vlan_id, on);
6897 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6900 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6903 ret = i40e_aq_add_vlan(hw, vsi->seid,
6904 &vlan_data, 1, NULL);
6905 if (ret != I40E_SUCCESS)
6906 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6908 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6909 &vlan_data, 1, NULL);
6910 if (ret != I40E_SUCCESS)
6912 "Failed to remove vlan filter");
6917 * Find all vlan options for specific mac addr,
6918 * return with actual vlan found.
6921 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6922 struct i40e_macvlan_filter *mv_f,
6923 int num, struct ether_addr *addr)
6929 * Not to use i40e_find_vlan_filter to decrease the loop time,
6930 * although the code looks complex.
6932 if (num < vsi->vlan_num)
6933 return I40E_ERR_PARAM;
6936 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6938 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6939 if (vsi->vfta[j] & (1 << k)) {
6942 "vlan number doesn't match");
6943 return I40E_ERR_PARAM;
6945 rte_memcpy(&mv_f[i].macaddr,
6946 addr, ETH_ADDR_LEN);
6948 j * I40E_UINT32_BIT_SIZE + k;
6954 return I40E_SUCCESS;
6958 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6959 struct i40e_macvlan_filter *mv_f,
6964 struct i40e_mac_filter *f;
6966 if (num < vsi->mac_num)
6967 return I40E_ERR_PARAM;
6969 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6971 PMD_DRV_LOG(ERR, "buffer number not match");
6972 return I40E_ERR_PARAM;
6974 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6976 mv_f[i].vlan_id = vlan;
6977 mv_f[i].filter_type = f->mac_info.filter_type;
6981 return I40E_SUCCESS;
6985 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6988 struct i40e_mac_filter *f;
6989 struct i40e_macvlan_filter *mv_f;
6990 int ret = I40E_SUCCESS;
6992 if (vsi == NULL || vsi->mac_num == 0)
6993 return I40E_ERR_PARAM;
6995 /* Case that no vlan is set */
6996 if (vsi->vlan_num == 0)
6999 num = vsi->mac_num * vsi->vlan_num;
7001 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7003 PMD_DRV_LOG(ERR, "failed to allocate memory");
7004 return I40E_ERR_NO_MEMORY;
7008 if (vsi->vlan_num == 0) {
7009 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7010 rte_memcpy(&mv_f[i].macaddr,
7011 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7012 mv_f[i].filter_type = f->mac_info.filter_type;
7013 mv_f[i].vlan_id = 0;
7017 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7018 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7019 vsi->vlan_num, &f->mac_info.mac_addr);
7020 if (ret != I40E_SUCCESS)
7022 for (j = i; j < i + vsi->vlan_num; j++)
7023 mv_f[j].filter_type = f->mac_info.filter_type;
7028 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7036 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7038 struct i40e_macvlan_filter *mv_f;
7040 int ret = I40E_SUCCESS;
7042 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
7043 return I40E_ERR_PARAM;
7045 /* If it's already set, just return */
7046 if (i40e_find_vlan_filter(vsi,vlan))
7047 return I40E_SUCCESS;
7049 mac_num = vsi->mac_num;
7052 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7053 return I40E_ERR_PARAM;
7056 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7059 PMD_DRV_LOG(ERR, "failed to allocate memory");
7060 return I40E_ERR_NO_MEMORY;
7063 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7065 if (ret != I40E_SUCCESS)
7068 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7070 if (ret != I40E_SUCCESS)
7073 i40e_set_vlan_filter(vsi, vlan, 1);
7083 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7085 struct i40e_macvlan_filter *mv_f;
7087 int ret = I40E_SUCCESS;
7090 * Vlan 0 is the generic filter for untagged packets
7091 * and can't be removed.
7093 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
7094 return I40E_ERR_PARAM;
7096 /* If can't find it, just return */
7097 if (!i40e_find_vlan_filter(vsi, vlan))
7098 return I40E_ERR_PARAM;
7100 mac_num = vsi->mac_num;
7103 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7104 return I40E_ERR_PARAM;
7107 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7110 PMD_DRV_LOG(ERR, "failed to allocate memory");
7111 return I40E_ERR_NO_MEMORY;
7114 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7116 if (ret != I40E_SUCCESS)
7119 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7121 if (ret != I40E_SUCCESS)
7124 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7125 if (vsi->vlan_num == 1) {
7126 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7127 if (ret != I40E_SUCCESS)
7130 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7131 if (ret != I40E_SUCCESS)
7135 i40e_set_vlan_filter(vsi, vlan, 0);
7145 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7147 struct i40e_mac_filter *f;
7148 struct i40e_macvlan_filter *mv_f;
7149 int i, vlan_num = 0;
7150 int ret = I40E_SUCCESS;
7152 /* If it's add and we've config it, return */
7153 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7155 return I40E_SUCCESS;
7156 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7157 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7160 * If vlan_num is 0, that's the first time to add mac,
7161 * set mask for vlan_id 0.
7163 if (vsi->vlan_num == 0) {
7164 i40e_set_vlan_filter(vsi, 0, 1);
7167 vlan_num = vsi->vlan_num;
7168 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7169 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7172 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7174 PMD_DRV_LOG(ERR, "failed to allocate memory");
7175 return I40E_ERR_NO_MEMORY;
7178 for (i = 0; i < vlan_num; i++) {
7179 mv_f[i].filter_type = mac_filter->filter_type;
7180 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7184 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7185 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7186 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7187 &mac_filter->mac_addr);
7188 if (ret != I40E_SUCCESS)
7192 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7193 if (ret != I40E_SUCCESS)
7196 /* Add the mac addr into mac list */
7197 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7199 PMD_DRV_LOG(ERR, "failed to allocate memory");
7200 ret = I40E_ERR_NO_MEMORY;
7203 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7205 f->mac_info.filter_type = mac_filter->filter_type;
7206 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7217 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7219 struct i40e_mac_filter *f;
7220 struct i40e_macvlan_filter *mv_f;
7222 enum rte_mac_filter_type filter_type;
7223 int ret = I40E_SUCCESS;
7225 /* Can't find it, return an error */
7226 f = i40e_find_mac_filter(vsi, addr);
7228 return I40E_ERR_PARAM;
7230 vlan_num = vsi->vlan_num;
7231 filter_type = f->mac_info.filter_type;
7232 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7233 filter_type == RTE_MACVLAN_HASH_MATCH) {
7234 if (vlan_num == 0) {
7235 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7236 return I40E_ERR_PARAM;
7238 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7239 filter_type == RTE_MAC_HASH_MATCH)
7242 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7244 PMD_DRV_LOG(ERR, "failed to allocate memory");
7245 return I40E_ERR_NO_MEMORY;
7248 for (i = 0; i < vlan_num; i++) {
7249 mv_f[i].filter_type = filter_type;
7250 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7253 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7254 filter_type == RTE_MACVLAN_HASH_MATCH) {
7255 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7256 if (ret != I40E_SUCCESS)
7260 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7261 if (ret != I40E_SUCCESS)
7264 /* Remove the mac addr into mac list */
7265 TAILQ_REMOVE(&vsi->mac_list, f, next);
7275 /* Configure hash enable flags for RSS */
7277 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7285 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7286 if (flags & (1ULL << i))
7287 hena |= adapter->pctypes_tbl[i];
7293 /* Parse the hash enable flags */
7295 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7297 uint64_t rss_hf = 0;
7303 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7304 if (flags & adapter->pctypes_tbl[i])
7305 rss_hf |= (1ULL << i);
7312 i40e_pf_disable_rss(struct i40e_pf *pf)
7314 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7316 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7317 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7318 I40E_WRITE_FLUSH(hw);
7322 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7324 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7325 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7326 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7327 I40E_VFQF_HKEY_MAX_INDEX :
7328 I40E_PFQF_HKEY_MAX_INDEX;
7331 if (!key || key_len == 0) {
7332 PMD_DRV_LOG(DEBUG, "No key to be configured");
7334 } else if (key_len != (key_idx + 1) *
7336 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7340 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7341 struct i40e_aqc_get_set_rss_key_data *key_dw =
7342 (struct i40e_aqc_get_set_rss_key_data *)key;
7344 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7346 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7348 uint32_t *hash_key = (uint32_t *)key;
7351 if (vsi->type == I40E_VSI_SRIOV) {
7352 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7355 I40E_VFQF_HKEY1(i, vsi->user_param),
7359 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7360 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7363 I40E_WRITE_FLUSH(hw);
7370 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7372 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7373 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7377 if (!key || !key_len)
7380 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7381 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7382 (struct i40e_aqc_get_set_rss_key_data *)key);
7384 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7388 uint32_t *key_dw = (uint32_t *)key;
7391 if (vsi->type == I40E_VSI_SRIOV) {
7392 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7393 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7394 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7396 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7399 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7400 reg = I40E_PFQF_HKEY(i);
7401 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7403 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7411 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7413 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7417 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7418 rss_conf->rss_key_len);
7422 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7423 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7424 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7425 I40E_WRITE_FLUSH(hw);
7431 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7432 struct rte_eth_rss_conf *rss_conf)
7434 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7435 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7436 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7439 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7440 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7442 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7443 if (rss_hf != 0) /* Enable RSS */
7445 return 0; /* Nothing to do */
7448 if (rss_hf == 0) /* Disable RSS */
7451 return i40e_hw_rss_hash_set(pf, rss_conf);
7455 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7456 struct rte_eth_rss_conf *rss_conf)
7458 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7459 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7462 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7463 &rss_conf->rss_key_len);
7465 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7466 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7467 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7473 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7475 switch (filter_type) {
7476 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7477 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7479 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7480 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7482 case RTE_TUNNEL_FILTER_IMAC_TENID:
7483 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7485 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7486 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7488 case ETH_TUNNEL_FILTER_IMAC:
7489 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7491 case ETH_TUNNEL_FILTER_OIP:
7492 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7494 case ETH_TUNNEL_FILTER_IIP:
7495 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7498 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7505 /* Convert tunnel filter structure */
7507 i40e_tunnel_filter_convert(
7508 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7509 struct i40e_tunnel_filter *tunnel_filter)
7511 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7512 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7513 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7514 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7515 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7516 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7517 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7518 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7519 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7521 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7522 tunnel_filter->input.flags = cld_filter->element.flags;
7523 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7524 tunnel_filter->queue = cld_filter->element.queue_number;
7525 rte_memcpy(tunnel_filter->input.general_fields,
7526 cld_filter->general_fields,
7527 sizeof(cld_filter->general_fields));
7532 /* Check if there exists the tunnel filter */
7533 struct i40e_tunnel_filter *
7534 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7535 const struct i40e_tunnel_filter_input *input)
7539 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7543 return tunnel_rule->hash_map[ret];
7546 /* Add a tunnel filter into the SW list */
7548 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7549 struct i40e_tunnel_filter *tunnel_filter)
7551 struct i40e_tunnel_rule *rule = &pf->tunnel;
7554 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7557 "Failed to insert tunnel filter to hash table %d!",
7561 rule->hash_map[ret] = tunnel_filter;
7563 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7568 /* Delete a tunnel filter from the SW list */
7570 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7571 struct i40e_tunnel_filter_input *input)
7573 struct i40e_tunnel_rule *rule = &pf->tunnel;
7574 struct i40e_tunnel_filter *tunnel_filter;
7577 ret = rte_hash_del_key(rule->hash_table, input);
7580 "Failed to delete tunnel filter to hash table %d!",
7584 tunnel_filter = rule->hash_map[ret];
7585 rule->hash_map[ret] = NULL;
7587 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7588 rte_free(tunnel_filter);
7594 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7595 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7599 uint32_t ipv4_addr, ipv4_addr_le;
7600 uint8_t i, tun_type = 0;
7601 /* internal varialbe to convert ipv6 byte order */
7602 uint32_t convert_ipv6[4];
7604 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7605 struct i40e_vsi *vsi = pf->main_vsi;
7606 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7607 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7608 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7609 struct i40e_tunnel_filter *tunnel, *node;
7610 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7612 cld_filter = rte_zmalloc("tunnel_filter",
7613 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7616 if (NULL == cld_filter) {
7617 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7620 pfilter = cld_filter;
7622 ether_addr_copy(&tunnel_filter->outer_mac,
7623 (struct ether_addr *)&pfilter->element.outer_mac);
7624 ether_addr_copy(&tunnel_filter->inner_mac,
7625 (struct ether_addr *)&pfilter->element.inner_mac);
7627 pfilter->element.inner_vlan =
7628 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7629 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7630 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7631 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7632 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7633 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7635 sizeof(pfilter->element.ipaddr.v4.data));
7637 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7638 for (i = 0; i < 4; i++) {
7640 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7642 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7644 sizeof(pfilter->element.ipaddr.v6.data));
7647 /* check tunneled type */
7648 switch (tunnel_filter->tunnel_type) {
7649 case RTE_TUNNEL_TYPE_VXLAN:
7650 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7652 case RTE_TUNNEL_TYPE_NVGRE:
7653 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7655 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7656 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7659 /* Other tunnel types is not supported. */
7660 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7661 rte_free(cld_filter);
7665 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7666 &pfilter->element.flags);
7668 rte_free(cld_filter);
7672 pfilter->element.flags |= rte_cpu_to_le_16(
7673 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7674 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7675 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7676 pfilter->element.queue_number =
7677 rte_cpu_to_le_16(tunnel_filter->queue_id);
7679 /* Check if there is the filter in SW list */
7680 memset(&check_filter, 0, sizeof(check_filter));
7681 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7682 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7684 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7685 rte_free(cld_filter);
7689 if (!add && !node) {
7690 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7691 rte_free(cld_filter);
7696 ret = i40e_aq_add_cloud_filters(hw,
7697 vsi->seid, &cld_filter->element, 1);
7699 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7700 rte_free(cld_filter);
7703 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7704 if (tunnel == NULL) {
7705 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7706 rte_free(cld_filter);
7710 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7711 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7715 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7716 &cld_filter->element, 1);
7718 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7719 rte_free(cld_filter);
7722 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7725 rte_free(cld_filter);
7729 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7730 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7731 #define I40E_TR_GENEVE_KEY_MASK 0x8
7732 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7733 #define I40E_TR_GRE_KEY_MASK 0x400
7734 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7735 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7738 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7740 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7741 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7742 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7743 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7744 enum i40e_status_code status = I40E_SUCCESS;
7746 if (pf->support_multi_driver) {
7747 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7748 return I40E_NOT_SUPPORTED;
7751 memset(&filter_replace, 0,
7752 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7753 memset(&filter_replace_buf, 0,
7754 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7756 /* create L1 filter */
7757 filter_replace.old_filter_type =
7758 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7759 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7760 filter_replace.tr_bit = 0;
7762 /* Prepare the buffer, 3 entries */
7763 filter_replace_buf.data[0] =
7764 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7765 filter_replace_buf.data[0] |=
7766 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7767 filter_replace_buf.data[2] = 0xFF;
7768 filter_replace_buf.data[3] = 0xFF;
7769 filter_replace_buf.data[4] =
7770 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7771 filter_replace_buf.data[4] |=
7772 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7773 filter_replace_buf.data[7] = 0xF0;
7774 filter_replace_buf.data[8]
7775 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7776 filter_replace_buf.data[8] |=
7777 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7778 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7779 I40E_TR_GENEVE_KEY_MASK |
7780 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7781 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7782 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7783 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7785 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7786 &filter_replace_buf);
7787 if (!status && (filter_replace.old_filter_type !=
7788 filter_replace.new_filter_type))
7789 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7790 " original: 0x%x, new: 0x%x",
7792 filter_replace.old_filter_type,
7793 filter_replace.new_filter_type);
7799 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7801 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7802 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7803 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7804 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7805 enum i40e_status_code status = I40E_SUCCESS;
7807 if (pf->support_multi_driver) {
7808 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7809 return I40E_NOT_SUPPORTED;
7813 memset(&filter_replace, 0,
7814 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7815 memset(&filter_replace_buf, 0,
7816 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7817 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7818 I40E_AQC_MIRROR_CLOUD_FILTER;
7819 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7820 filter_replace.new_filter_type =
7821 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7822 /* Prepare the buffer, 2 entries */
7823 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7824 filter_replace_buf.data[0] |=
7825 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7826 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7827 filter_replace_buf.data[4] |=
7828 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7829 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7830 &filter_replace_buf);
7833 if (filter_replace.old_filter_type !=
7834 filter_replace.new_filter_type)
7835 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7836 " original: 0x%x, new: 0x%x",
7838 filter_replace.old_filter_type,
7839 filter_replace.new_filter_type);
7842 memset(&filter_replace, 0,
7843 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7844 memset(&filter_replace_buf, 0,
7845 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7847 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7848 I40E_AQC_MIRROR_CLOUD_FILTER;
7849 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7850 filter_replace.new_filter_type =
7851 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7852 /* Prepare the buffer, 2 entries */
7853 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7854 filter_replace_buf.data[0] |=
7855 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7856 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7857 filter_replace_buf.data[4] |=
7858 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7860 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7861 &filter_replace_buf);
7862 if (!status && (filter_replace.old_filter_type !=
7863 filter_replace.new_filter_type))
7864 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7865 " original: 0x%x, new: 0x%x",
7867 filter_replace.old_filter_type,
7868 filter_replace.new_filter_type);
7873 static enum i40e_status_code
7874 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7876 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7877 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7878 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7879 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7880 enum i40e_status_code status = I40E_SUCCESS;
7882 if (pf->support_multi_driver) {
7883 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7884 return I40E_NOT_SUPPORTED;
7888 memset(&filter_replace, 0,
7889 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7890 memset(&filter_replace_buf, 0,
7891 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7892 /* create L1 filter */
7893 filter_replace.old_filter_type =
7894 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7895 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7896 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7897 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7898 /* Prepare the buffer, 2 entries */
7899 filter_replace_buf.data[0] =
7900 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7901 filter_replace_buf.data[0] |=
7902 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7903 filter_replace_buf.data[2] = 0xFF;
7904 filter_replace_buf.data[3] = 0xFF;
7905 filter_replace_buf.data[4] =
7906 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7907 filter_replace_buf.data[4] |=
7908 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7909 filter_replace_buf.data[6] = 0xFF;
7910 filter_replace_buf.data[7] = 0xFF;
7911 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7912 &filter_replace_buf);
7915 if (filter_replace.old_filter_type !=
7916 filter_replace.new_filter_type)
7917 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7918 " original: 0x%x, new: 0x%x",
7920 filter_replace.old_filter_type,
7921 filter_replace.new_filter_type);
7924 memset(&filter_replace, 0,
7925 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7926 memset(&filter_replace_buf, 0,
7927 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7928 /* create L1 filter */
7929 filter_replace.old_filter_type =
7930 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7931 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7932 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7933 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7934 /* Prepare the buffer, 2 entries */
7935 filter_replace_buf.data[0] =
7936 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7937 filter_replace_buf.data[0] |=
7938 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7939 filter_replace_buf.data[2] = 0xFF;
7940 filter_replace_buf.data[3] = 0xFF;
7941 filter_replace_buf.data[4] =
7942 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7943 filter_replace_buf.data[4] |=
7944 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7945 filter_replace_buf.data[6] = 0xFF;
7946 filter_replace_buf.data[7] = 0xFF;
7948 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7949 &filter_replace_buf);
7950 if (!status && (filter_replace.old_filter_type !=
7951 filter_replace.new_filter_type))
7952 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7953 " original: 0x%x, new: 0x%x",
7955 filter_replace.old_filter_type,
7956 filter_replace.new_filter_type);
7962 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7964 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7965 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7966 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7967 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7968 enum i40e_status_code status = I40E_SUCCESS;
7970 if (pf->support_multi_driver) {
7971 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7972 return I40E_NOT_SUPPORTED;
7976 memset(&filter_replace, 0,
7977 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7978 memset(&filter_replace_buf, 0,
7979 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7980 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7981 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7982 filter_replace.new_filter_type =
7983 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7984 /* Prepare the buffer, 2 entries */
7985 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7986 filter_replace_buf.data[0] |=
7987 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7988 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7989 filter_replace_buf.data[4] |=
7990 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7991 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7992 &filter_replace_buf);
7995 if (filter_replace.old_filter_type !=
7996 filter_replace.new_filter_type)
7997 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7998 " original: 0x%x, new: 0x%x",
8000 filter_replace.old_filter_type,
8001 filter_replace.new_filter_type);
8004 memset(&filter_replace, 0,
8005 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8006 memset(&filter_replace_buf, 0,
8007 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8008 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8009 filter_replace.old_filter_type =
8010 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8011 filter_replace.new_filter_type =
8012 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8013 /* Prepare the buffer, 2 entries */
8014 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8015 filter_replace_buf.data[0] |=
8016 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8017 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8018 filter_replace_buf.data[4] |=
8019 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8021 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8022 &filter_replace_buf);
8023 if (!status && (filter_replace.old_filter_type !=
8024 filter_replace.new_filter_type))
8025 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8026 " original: 0x%x, new: 0x%x",
8028 filter_replace.old_filter_type,
8029 filter_replace.new_filter_type);
8035 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8036 struct i40e_tunnel_filter_conf *tunnel_filter,
8040 uint32_t ipv4_addr, ipv4_addr_le;
8041 uint8_t i, tun_type = 0;
8042 /* internal variable to convert ipv6 byte order */
8043 uint32_t convert_ipv6[4];
8045 struct i40e_pf_vf *vf = NULL;
8046 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8047 struct i40e_vsi *vsi;
8048 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8049 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8050 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8051 struct i40e_tunnel_filter *tunnel, *node;
8052 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8054 bool big_buffer = 0;
8056 cld_filter = rte_zmalloc("tunnel_filter",
8057 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8060 if (cld_filter == NULL) {
8061 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8064 pfilter = cld_filter;
8066 ether_addr_copy(&tunnel_filter->outer_mac,
8067 (struct ether_addr *)&pfilter->element.outer_mac);
8068 ether_addr_copy(&tunnel_filter->inner_mac,
8069 (struct ether_addr *)&pfilter->element.inner_mac);
8071 pfilter->element.inner_vlan =
8072 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8073 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8074 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8075 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8076 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8077 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8079 sizeof(pfilter->element.ipaddr.v4.data));
8081 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8082 for (i = 0; i < 4; i++) {
8084 rte_cpu_to_le_32(rte_be_to_cpu_32(
8085 tunnel_filter->ip_addr.ipv6_addr[i]));
8087 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8089 sizeof(pfilter->element.ipaddr.v6.data));
8092 /* check tunneled type */
8093 switch (tunnel_filter->tunnel_type) {
8094 case I40E_TUNNEL_TYPE_VXLAN:
8095 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8097 case I40E_TUNNEL_TYPE_NVGRE:
8098 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8100 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8101 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8103 case I40E_TUNNEL_TYPE_MPLSoUDP:
8104 if (!pf->mpls_replace_flag) {
8105 i40e_replace_mpls_l1_filter(pf);
8106 i40e_replace_mpls_cloud_filter(pf);
8107 pf->mpls_replace_flag = 1;
8109 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8110 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8112 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8113 (teid_le & 0xF) << 12;
8114 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8117 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8119 case I40E_TUNNEL_TYPE_MPLSoGRE:
8120 if (!pf->mpls_replace_flag) {
8121 i40e_replace_mpls_l1_filter(pf);
8122 i40e_replace_mpls_cloud_filter(pf);
8123 pf->mpls_replace_flag = 1;
8125 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8126 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8128 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8129 (teid_le & 0xF) << 12;
8130 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8133 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8135 case I40E_TUNNEL_TYPE_GTPC:
8136 if (!pf->gtp_replace_flag) {
8137 i40e_replace_gtp_l1_filter(pf);
8138 i40e_replace_gtp_cloud_filter(pf);
8139 pf->gtp_replace_flag = 1;
8141 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8142 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8143 (teid_le >> 16) & 0xFFFF;
8144 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8146 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8150 case I40E_TUNNEL_TYPE_GTPU:
8151 if (!pf->gtp_replace_flag) {
8152 i40e_replace_gtp_l1_filter(pf);
8153 i40e_replace_gtp_cloud_filter(pf);
8154 pf->gtp_replace_flag = 1;
8156 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8157 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8158 (teid_le >> 16) & 0xFFFF;
8159 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8161 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8165 case I40E_TUNNEL_TYPE_QINQ:
8166 if (!pf->qinq_replace_flag) {
8167 ret = i40e_cloud_filter_qinq_create(pf);
8170 "QinQ tunnel filter already created.");
8171 pf->qinq_replace_flag = 1;
8173 /* Add in the General fields the values of
8174 * the Outer and Inner VLAN
8175 * Big Buffer should be set, see changes in
8176 * i40e_aq_add_cloud_filters
8178 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8179 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8183 /* Other tunnel types is not supported. */
8184 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8185 rte_free(cld_filter);
8189 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8190 pfilter->element.flags =
8191 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8192 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8193 pfilter->element.flags =
8194 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8195 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8196 pfilter->element.flags =
8197 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8198 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8199 pfilter->element.flags =
8200 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8201 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8202 pfilter->element.flags |=
8203 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8205 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8206 &pfilter->element.flags);
8208 rte_free(cld_filter);
8213 pfilter->element.flags |= rte_cpu_to_le_16(
8214 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8215 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8216 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8217 pfilter->element.queue_number =
8218 rte_cpu_to_le_16(tunnel_filter->queue_id);
8220 if (!tunnel_filter->is_to_vf)
8223 if (tunnel_filter->vf_id >= pf->vf_num) {
8224 PMD_DRV_LOG(ERR, "Invalid argument.");
8225 rte_free(cld_filter);
8228 vf = &pf->vfs[tunnel_filter->vf_id];
8232 /* Check if there is the filter in SW list */
8233 memset(&check_filter, 0, sizeof(check_filter));
8234 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8235 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8236 check_filter.vf_id = tunnel_filter->vf_id;
8237 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8239 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8240 rte_free(cld_filter);
8244 if (!add && !node) {
8245 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8246 rte_free(cld_filter);
8252 ret = i40e_aq_add_cloud_filters_bb(hw,
8253 vsi->seid, cld_filter, 1);
8255 ret = i40e_aq_add_cloud_filters(hw,
8256 vsi->seid, &cld_filter->element, 1);
8258 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8259 rte_free(cld_filter);
8262 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8263 if (tunnel == NULL) {
8264 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8265 rte_free(cld_filter);
8269 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8270 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8275 ret = i40e_aq_rem_cloud_filters_bb(
8276 hw, vsi->seid, cld_filter, 1);
8278 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8279 &cld_filter->element, 1);
8281 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8282 rte_free(cld_filter);
8285 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8288 rte_free(cld_filter);
8293 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8297 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8298 if (pf->vxlan_ports[i] == port)
8306 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8310 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8312 idx = i40e_get_vxlan_port_idx(pf, port);
8314 /* Check if port already exists */
8316 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8320 /* Now check if there is space to add the new port */
8321 idx = i40e_get_vxlan_port_idx(pf, 0);
8324 "Maximum number of UDP ports reached, not adding port %d",
8329 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8332 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8336 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8339 /* New port: add it and mark its index in the bitmap */
8340 pf->vxlan_ports[idx] = port;
8341 pf->vxlan_bitmap |= (1 << idx);
8343 if (!(pf->flags & I40E_FLAG_VXLAN))
8344 pf->flags |= I40E_FLAG_VXLAN;
8350 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8353 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8355 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8356 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8360 idx = i40e_get_vxlan_port_idx(pf, port);
8363 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8367 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8368 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8372 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8375 pf->vxlan_ports[idx] = 0;
8376 pf->vxlan_bitmap &= ~(1 << idx);
8378 if (!pf->vxlan_bitmap)
8379 pf->flags &= ~I40E_FLAG_VXLAN;
8384 /* Add UDP tunneling port */
8386 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8387 struct rte_eth_udp_tunnel *udp_tunnel)
8390 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8392 if (udp_tunnel == NULL)
8395 switch (udp_tunnel->prot_type) {
8396 case RTE_TUNNEL_TYPE_VXLAN:
8397 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8400 case RTE_TUNNEL_TYPE_GENEVE:
8401 case RTE_TUNNEL_TYPE_TEREDO:
8402 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8407 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8415 /* Remove UDP tunneling port */
8417 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8418 struct rte_eth_udp_tunnel *udp_tunnel)
8421 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8423 if (udp_tunnel == NULL)
8426 switch (udp_tunnel->prot_type) {
8427 case RTE_TUNNEL_TYPE_VXLAN:
8428 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8430 case RTE_TUNNEL_TYPE_GENEVE:
8431 case RTE_TUNNEL_TYPE_TEREDO:
8432 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8436 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8444 /* Calculate the maximum number of contiguous PF queues that are configured */
8446 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8448 struct rte_eth_dev_data *data = pf->dev_data;
8450 struct i40e_rx_queue *rxq;
8453 for (i = 0; i < pf->lan_nb_qps; i++) {
8454 rxq = data->rx_queues[i];
8455 if (rxq && rxq->q_set)
8466 i40e_pf_config_rss(struct i40e_pf *pf)
8468 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8469 struct rte_eth_rss_conf rss_conf;
8470 uint32_t i, lut = 0;
8474 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8475 * It's necessary to calculate the actual PF queues that are configured.
8477 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8478 num = i40e_pf_calc_configured_queues_num(pf);
8480 num = pf->dev_data->nb_rx_queues;
8482 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8483 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8487 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8491 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8494 lut = (lut << 8) | (j & ((0x1 <<
8495 hw->func_caps.rss_table_entry_width) - 1));
8497 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8500 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8501 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8502 i40e_pf_disable_rss(pf);
8505 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8506 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8507 /* Random default keys */
8508 static uint32_t rss_key_default[] = {0x6b793944,
8509 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8510 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8511 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8513 rss_conf.rss_key = (uint8_t *)rss_key_default;
8514 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8518 return i40e_hw_rss_hash_set(pf, &rss_conf);
8522 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8523 struct rte_eth_tunnel_filter_conf *filter)
8525 if (pf == NULL || filter == NULL) {
8526 PMD_DRV_LOG(ERR, "Invalid parameter");
8530 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8531 PMD_DRV_LOG(ERR, "Invalid queue ID");
8535 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8536 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8540 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8541 (is_zero_ether_addr(&filter->outer_mac))) {
8542 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8546 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8547 (is_zero_ether_addr(&filter->inner_mac))) {
8548 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8555 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8556 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8558 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8560 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8564 if (pf->support_multi_driver) {
8565 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8569 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8570 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8573 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8574 } else if (len == 4) {
8575 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8577 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8582 ret = i40e_aq_debug_write_global_register(hw,
8583 I40E_GL_PRS_FVBM(2),
8587 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8588 "with value 0x%08x",
8589 I40E_GL_PRS_FVBM(2), reg);
8593 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8594 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8600 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8607 switch (cfg->cfg_type) {
8608 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8609 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8612 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8620 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8621 enum rte_filter_op filter_op,
8624 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8625 int ret = I40E_ERR_PARAM;
8627 switch (filter_op) {
8628 case RTE_ETH_FILTER_SET:
8629 ret = i40e_dev_global_config_set(hw,
8630 (struct rte_eth_global_cfg *)arg);
8633 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8641 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8642 enum rte_filter_op filter_op,
8645 struct rte_eth_tunnel_filter_conf *filter;
8646 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8647 int ret = I40E_SUCCESS;
8649 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8651 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8652 return I40E_ERR_PARAM;
8654 switch (filter_op) {
8655 case RTE_ETH_FILTER_NOP:
8656 if (!(pf->flags & I40E_FLAG_VXLAN))
8657 ret = I40E_NOT_SUPPORTED;
8659 case RTE_ETH_FILTER_ADD:
8660 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8662 case RTE_ETH_FILTER_DELETE:
8663 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8666 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8667 ret = I40E_ERR_PARAM;
8675 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8678 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8681 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8682 ret = i40e_pf_config_rss(pf);
8684 i40e_pf_disable_rss(pf);
8689 /* Get the symmetric hash enable configurations per port */
8691 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8693 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8695 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8698 /* Set the symmetric hash enable configurations per port */
8700 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8702 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8705 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8707 "Symmetric hash has already been enabled");
8710 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8712 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8714 "Symmetric hash has already been disabled");
8717 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8719 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8720 I40E_WRITE_FLUSH(hw);
8724 * Get global configurations of hash function type and symmetric hash enable
8725 * per flow type (pctype). Note that global configuration means it affects all
8726 * the ports on the same NIC.
8729 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8730 struct rte_eth_hash_global_conf *g_cfg)
8732 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8736 memset(g_cfg, 0, sizeof(*g_cfg));
8737 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8738 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8739 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8741 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8742 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8743 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8746 * As i40e supports less than 64 flow types, only first 64 bits need to
8749 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8750 g_cfg->valid_bit_mask[i] = 0ULL;
8751 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8754 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8756 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8757 if (!adapter->pctypes_tbl[i])
8759 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8760 j < I40E_FILTER_PCTYPE_MAX; j++) {
8761 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8762 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8763 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8764 g_cfg->sym_hash_enable_mask[0] |=
8775 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8776 const struct rte_eth_hash_global_conf *g_cfg)
8779 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8781 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8782 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8783 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8784 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8790 * As i40e supports less than 64 flow types, only first 64 bits need to
8793 mask0 = g_cfg->valid_bit_mask[0];
8794 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8796 /* Check if any unsupported flow type configured */
8797 if ((mask0 | i40e_mask) ^ i40e_mask)
8800 if (g_cfg->valid_bit_mask[i])
8808 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8814 * Set global configurations of hash function type and symmetric hash enable
8815 * per flow type (pctype). Note any modifying global configuration will affect
8816 * all the ports on the same NIC.
8819 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8820 struct rte_eth_hash_global_conf *g_cfg)
8822 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8823 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8827 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8829 if (pf->support_multi_driver) {
8830 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8834 /* Check the input parameters */
8835 ret = i40e_hash_global_config_check(adapter, g_cfg);
8840 * As i40e supports less than 64 flow types, only first 64 bits need to
8843 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8844 if (mask0 & (1UL << i)) {
8845 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8846 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8848 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8849 j < I40E_FILTER_PCTYPE_MAX; j++) {
8850 if (adapter->pctypes_tbl[i] & (1ULL << j))
8851 i40e_write_global_rx_ctl(hw,
8858 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8859 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8861 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8863 "Hash function already set to Toeplitz");
8866 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8867 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8869 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8871 "Hash function already set to Simple XOR");
8874 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8876 /* Use the default, and keep it as it is */
8879 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8882 I40E_WRITE_FLUSH(hw);
8888 * Valid input sets for hash and flow director filters per PCTYPE
8891 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8892 enum rte_filter_type filter)
8896 static const uint64_t valid_hash_inset_table[] = {
8897 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8898 I40E_INSET_DMAC | I40E_INSET_SMAC |
8899 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8900 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8901 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8902 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8903 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8904 I40E_INSET_FLEX_PAYLOAD,
8905 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8906 I40E_INSET_DMAC | I40E_INSET_SMAC |
8907 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8908 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8909 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8910 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8911 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8912 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8913 I40E_INSET_FLEX_PAYLOAD,
8914 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8915 I40E_INSET_DMAC | I40E_INSET_SMAC |
8916 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8917 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8918 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8919 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8920 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8921 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8922 I40E_INSET_FLEX_PAYLOAD,
8923 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8924 I40E_INSET_DMAC | I40E_INSET_SMAC |
8925 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8926 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8927 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8928 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8929 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8930 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8931 I40E_INSET_FLEX_PAYLOAD,
8932 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8933 I40E_INSET_DMAC | I40E_INSET_SMAC |
8934 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8935 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8936 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8937 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8938 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8939 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8940 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8941 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8942 I40E_INSET_DMAC | I40E_INSET_SMAC |
8943 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8944 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8945 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8946 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8947 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8948 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8949 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8950 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8951 I40E_INSET_DMAC | I40E_INSET_SMAC |
8952 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8953 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8954 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8955 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8956 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8957 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8958 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8959 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8960 I40E_INSET_DMAC | I40E_INSET_SMAC |
8961 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8962 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8963 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8964 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8965 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8966 I40E_INSET_FLEX_PAYLOAD,
8967 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8968 I40E_INSET_DMAC | I40E_INSET_SMAC |
8969 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8970 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8971 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8972 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8973 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8974 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8975 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8976 I40E_INSET_DMAC | I40E_INSET_SMAC |
8977 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8978 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8979 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8980 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8981 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8982 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8983 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8984 I40E_INSET_DMAC | I40E_INSET_SMAC |
8985 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8986 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8987 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8988 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8989 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8990 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8991 I40E_INSET_FLEX_PAYLOAD,
8992 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8993 I40E_INSET_DMAC | I40E_INSET_SMAC |
8994 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8995 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8996 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8997 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8998 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8999 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9000 I40E_INSET_FLEX_PAYLOAD,
9001 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9002 I40E_INSET_DMAC | I40E_INSET_SMAC |
9003 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9004 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9005 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9006 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9007 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9008 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9009 I40E_INSET_FLEX_PAYLOAD,
9010 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9011 I40E_INSET_DMAC | I40E_INSET_SMAC |
9012 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9013 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9014 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9015 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9016 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9017 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9018 I40E_INSET_FLEX_PAYLOAD,
9019 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9020 I40E_INSET_DMAC | I40E_INSET_SMAC |
9021 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9022 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9023 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9024 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9025 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9026 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9027 I40E_INSET_FLEX_PAYLOAD,
9028 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9029 I40E_INSET_DMAC | I40E_INSET_SMAC |
9030 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9031 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9032 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9033 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9034 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9035 I40E_INSET_FLEX_PAYLOAD,
9036 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9037 I40E_INSET_DMAC | I40E_INSET_SMAC |
9038 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9039 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9040 I40E_INSET_FLEX_PAYLOAD,
9044 * Flow director supports only fields defined in
9045 * union rte_eth_fdir_flow.
9047 static const uint64_t valid_fdir_inset_table[] = {
9048 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9049 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9050 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9051 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9052 I40E_INSET_IPV4_TTL,
9053 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9054 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9055 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9056 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9057 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9058 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9059 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9060 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9061 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9062 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9063 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9064 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9065 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9066 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9067 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9068 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9069 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9070 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9071 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9072 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9073 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9074 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9075 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9076 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9077 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9078 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9079 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9080 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9081 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9082 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9084 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9085 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9086 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9087 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9088 I40E_INSET_IPV4_TTL,
9089 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9090 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9091 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9092 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9093 I40E_INSET_IPV6_HOP_LIMIT,
9094 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9095 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9096 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9097 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9098 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9099 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9100 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9101 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9102 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9103 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9104 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9105 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9106 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9107 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9108 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9109 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9110 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9111 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9112 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9113 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9114 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9115 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9116 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9117 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9118 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9119 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9120 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9121 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9122 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9123 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9125 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9126 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9127 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9128 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9129 I40E_INSET_IPV6_HOP_LIMIT,
9130 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9131 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9132 I40E_INSET_LAST_ETHER_TYPE,
9135 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9137 if (filter == RTE_ETH_FILTER_HASH)
9138 valid = valid_hash_inset_table[pctype];
9140 valid = valid_fdir_inset_table[pctype];
9146 * Validate if the input set is allowed for a specific PCTYPE
9149 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9150 enum rte_filter_type filter, uint64_t inset)
9154 valid = i40e_get_valid_input_set(pctype, filter);
9155 if (inset & (~valid))
9161 /* default input set fields combination per pctype */
9163 i40e_get_default_input_set(uint16_t pctype)
9165 static const uint64_t default_inset_table[] = {
9166 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9167 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9168 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9169 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9170 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9171 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9172 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9173 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9174 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9175 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9176 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9177 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9178 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9179 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9180 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9181 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9182 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9183 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9184 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9185 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9187 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9188 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9189 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9190 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9191 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9192 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9193 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9194 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9195 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9196 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9197 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9198 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9199 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9200 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9201 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9202 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9203 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9204 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9205 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9206 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9207 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9208 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9210 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9211 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9212 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9213 I40E_INSET_LAST_ETHER_TYPE,
9216 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9219 return default_inset_table[pctype];
9223 * Parse the input set from index to logical bit masks
9226 i40e_parse_input_set(uint64_t *inset,
9227 enum i40e_filter_pctype pctype,
9228 enum rte_eth_input_set_field *field,
9234 static const struct {
9235 enum rte_eth_input_set_field field;
9237 } inset_convert_table[] = {
9238 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9239 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9240 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9241 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9242 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9243 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9244 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9245 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9246 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9247 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9248 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9249 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9250 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9251 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9252 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9253 I40E_INSET_IPV6_NEXT_HDR},
9254 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9255 I40E_INSET_IPV6_HOP_LIMIT},
9256 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9257 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9258 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9259 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9260 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9261 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9262 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9263 I40E_INSET_SCTP_VT},
9264 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9265 I40E_INSET_TUNNEL_DMAC},
9266 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9267 I40E_INSET_VLAN_TUNNEL},
9268 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9269 I40E_INSET_TUNNEL_ID},
9270 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9271 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9272 I40E_INSET_FLEX_PAYLOAD_W1},
9273 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9274 I40E_INSET_FLEX_PAYLOAD_W2},
9275 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9276 I40E_INSET_FLEX_PAYLOAD_W3},
9277 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9278 I40E_INSET_FLEX_PAYLOAD_W4},
9279 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9280 I40E_INSET_FLEX_PAYLOAD_W5},
9281 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9282 I40E_INSET_FLEX_PAYLOAD_W6},
9283 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9284 I40E_INSET_FLEX_PAYLOAD_W7},
9285 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9286 I40E_INSET_FLEX_PAYLOAD_W8},
9289 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9292 /* Only one item allowed for default or all */
9294 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9295 *inset = i40e_get_default_input_set(pctype);
9297 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9298 *inset = I40E_INSET_NONE;
9303 for (i = 0, *inset = 0; i < size; i++) {
9304 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9305 if (field[i] == inset_convert_table[j].field) {
9306 *inset |= inset_convert_table[j].inset;
9311 /* It contains unsupported input set, return immediately */
9312 if (j == RTE_DIM(inset_convert_table))
9320 * Translate the input set from bit masks to register aware bit masks
9324 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9334 static const struct inset_map inset_map_common[] = {
9335 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9336 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9337 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9338 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9339 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9340 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9341 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9342 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9343 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9344 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9345 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9346 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9347 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9348 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9349 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9350 {I40E_INSET_TUNNEL_DMAC,
9351 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9352 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9353 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9354 {I40E_INSET_TUNNEL_SRC_PORT,
9355 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9356 {I40E_INSET_TUNNEL_DST_PORT,
9357 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9358 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9359 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9360 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9361 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9362 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9363 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9364 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9365 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9366 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9369 /* some different registers map in x722*/
9370 static const struct inset_map inset_map_diff_x722[] = {
9371 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9372 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9373 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9374 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9377 static const struct inset_map inset_map_diff_not_x722[] = {
9378 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9379 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9380 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9381 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9387 /* Translate input set to register aware inset */
9388 if (type == I40E_MAC_X722) {
9389 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9390 if (input & inset_map_diff_x722[i].inset)
9391 val |= inset_map_diff_x722[i].inset_reg;
9394 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9395 if (input & inset_map_diff_not_x722[i].inset)
9396 val |= inset_map_diff_not_x722[i].inset_reg;
9400 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9401 if (input & inset_map_common[i].inset)
9402 val |= inset_map_common[i].inset_reg;
9409 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9412 uint64_t inset_need_mask = inset;
9414 static const struct {
9417 } inset_mask_map[] = {
9418 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9419 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9420 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9421 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9422 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9423 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9424 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9425 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9428 if (!inset || !mask || !nb_elem)
9431 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9432 /* Clear the inset bit, if no MASK is required,
9433 * for example proto + ttl
9435 if ((inset & inset_mask_map[i].inset) ==
9436 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9437 inset_need_mask &= ~inset_mask_map[i].inset;
9438 if (!inset_need_mask)
9441 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9442 if ((inset_need_mask & inset_mask_map[i].inset) ==
9443 inset_mask_map[i].inset) {
9444 if (idx >= nb_elem) {
9445 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9448 mask[idx] = inset_mask_map[i].mask;
9457 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9459 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9461 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9463 i40e_write_rx_ctl(hw, addr, val);
9464 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9465 (uint32_t)i40e_read_rx_ctl(hw, addr));
9469 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9471 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9472 struct rte_eth_dev *dev;
9474 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9476 i40e_write_rx_ctl(hw, addr, val);
9477 PMD_DRV_LOG(WARNING,
9478 "i40e device %s changed global register [0x%08x]."
9479 " original: 0x%08x, new: 0x%08x",
9480 dev->device->name, addr, reg,
9481 (uint32_t)i40e_read_rx_ctl(hw, addr));
9486 i40e_filter_input_set_init(struct i40e_pf *pf)
9488 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9489 enum i40e_filter_pctype pctype;
9490 uint64_t input_set, inset_reg;
9491 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9495 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9496 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9497 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9499 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9502 input_set = i40e_get_default_input_set(pctype);
9504 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9505 I40E_INSET_MASK_NUM_REG);
9508 if (pf->support_multi_driver && num > 0) {
9509 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9512 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9515 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9516 (uint32_t)(inset_reg & UINT32_MAX));
9517 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9518 (uint32_t)((inset_reg >>
9519 I40E_32_BIT_WIDTH) & UINT32_MAX));
9520 if (!pf->support_multi_driver) {
9521 i40e_check_write_global_reg(hw,
9522 I40E_GLQF_HASH_INSET(0, pctype),
9523 (uint32_t)(inset_reg & UINT32_MAX));
9524 i40e_check_write_global_reg(hw,
9525 I40E_GLQF_HASH_INSET(1, pctype),
9526 (uint32_t)((inset_reg >>
9527 I40E_32_BIT_WIDTH) & UINT32_MAX));
9529 for (i = 0; i < num; i++) {
9530 i40e_check_write_global_reg(hw,
9531 I40E_GLQF_FD_MSK(i, pctype),
9533 i40e_check_write_global_reg(hw,
9534 I40E_GLQF_HASH_MSK(i, pctype),
9537 /*clear unused mask registers of the pctype */
9538 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9539 i40e_check_write_global_reg(hw,
9540 I40E_GLQF_FD_MSK(i, pctype),
9542 i40e_check_write_global_reg(hw,
9543 I40E_GLQF_HASH_MSK(i, pctype),
9547 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9549 I40E_WRITE_FLUSH(hw);
9551 /* store the default input set */
9552 if (!pf->support_multi_driver)
9553 pf->hash_input_set[pctype] = input_set;
9554 pf->fdir.input_set[pctype] = input_set;
9559 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9560 struct rte_eth_input_set_conf *conf)
9562 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9563 enum i40e_filter_pctype pctype;
9564 uint64_t input_set, inset_reg = 0;
9565 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9569 PMD_DRV_LOG(ERR, "Invalid pointer");
9572 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9573 conf->op != RTE_ETH_INPUT_SET_ADD) {
9574 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9578 if (pf->support_multi_driver) {
9579 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9583 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9584 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9585 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9589 if (hw->mac.type == I40E_MAC_X722) {
9590 /* get translated pctype value in fd pctype register */
9591 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9592 I40E_GLQF_FD_PCTYPES((int)pctype));
9595 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9598 PMD_DRV_LOG(ERR, "Failed to parse input set");
9602 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9603 /* get inset value in register */
9604 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9605 inset_reg <<= I40E_32_BIT_WIDTH;
9606 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9607 input_set |= pf->hash_input_set[pctype];
9609 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9610 I40E_INSET_MASK_NUM_REG);
9614 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9616 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9617 (uint32_t)(inset_reg & UINT32_MAX));
9618 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9619 (uint32_t)((inset_reg >>
9620 I40E_32_BIT_WIDTH) & UINT32_MAX));
9622 for (i = 0; i < num; i++)
9623 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9625 /*clear unused mask registers of the pctype */
9626 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9627 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9629 I40E_WRITE_FLUSH(hw);
9631 pf->hash_input_set[pctype] = input_set;
9636 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9637 struct rte_eth_input_set_conf *conf)
9639 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9640 enum i40e_filter_pctype pctype;
9641 uint64_t input_set, inset_reg = 0;
9642 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9646 PMD_DRV_LOG(ERR, "Invalid pointer");
9649 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9650 conf->op != RTE_ETH_INPUT_SET_ADD) {
9651 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9655 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9657 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9658 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9662 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9665 PMD_DRV_LOG(ERR, "Failed to parse input set");
9669 /* get inset value in register */
9670 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9671 inset_reg <<= I40E_32_BIT_WIDTH;
9672 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9674 /* Can not change the inset reg for flex payload for fdir,
9675 * it is done by writing I40E_PRTQF_FD_FLXINSET
9676 * in i40e_set_flex_mask_on_pctype.
9678 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9679 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9681 input_set |= pf->fdir.input_set[pctype];
9682 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9683 I40E_INSET_MASK_NUM_REG);
9686 if (pf->support_multi_driver && num > 0) {
9687 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9691 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9693 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9694 (uint32_t)(inset_reg & UINT32_MAX));
9695 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9696 (uint32_t)((inset_reg >>
9697 I40E_32_BIT_WIDTH) & UINT32_MAX));
9699 if (!pf->support_multi_driver) {
9700 for (i = 0; i < num; i++)
9701 i40e_check_write_global_reg(hw,
9702 I40E_GLQF_FD_MSK(i, pctype),
9704 /*clear unused mask registers of the pctype */
9705 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9706 i40e_check_write_global_reg(hw,
9707 I40E_GLQF_FD_MSK(i, pctype),
9710 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9712 I40E_WRITE_FLUSH(hw);
9714 pf->fdir.input_set[pctype] = input_set;
9719 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9724 PMD_DRV_LOG(ERR, "Invalid pointer");
9728 switch (info->info_type) {
9729 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9730 i40e_get_symmetric_hash_enable_per_port(hw,
9731 &(info->info.enable));
9733 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9734 ret = i40e_get_hash_filter_global_config(hw,
9735 &(info->info.global_conf));
9738 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9748 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9753 PMD_DRV_LOG(ERR, "Invalid pointer");
9757 switch (info->info_type) {
9758 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9759 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9761 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9762 ret = i40e_set_hash_filter_global_config(hw,
9763 &(info->info.global_conf));
9765 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9766 ret = i40e_hash_filter_inset_select(hw,
9767 &(info->info.input_set_conf));
9771 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9780 /* Operations for hash function */
9782 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9783 enum rte_filter_op filter_op,
9786 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9789 switch (filter_op) {
9790 case RTE_ETH_FILTER_NOP:
9792 case RTE_ETH_FILTER_GET:
9793 ret = i40e_hash_filter_get(hw,
9794 (struct rte_eth_hash_filter_info *)arg);
9796 case RTE_ETH_FILTER_SET:
9797 ret = i40e_hash_filter_set(hw,
9798 (struct rte_eth_hash_filter_info *)arg);
9801 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9810 /* Convert ethertype filter structure */
9812 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9813 struct i40e_ethertype_filter *filter)
9815 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9816 filter->input.ether_type = input->ether_type;
9817 filter->flags = input->flags;
9818 filter->queue = input->queue;
9823 /* Check if there exists the ehtertype filter */
9824 struct i40e_ethertype_filter *
9825 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9826 const struct i40e_ethertype_filter_input *input)
9830 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9834 return ethertype_rule->hash_map[ret];
9837 /* Add ethertype filter in SW list */
9839 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9840 struct i40e_ethertype_filter *filter)
9842 struct i40e_ethertype_rule *rule = &pf->ethertype;
9845 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9848 "Failed to insert ethertype filter"
9849 " to hash table %d!",
9853 rule->hash_map[ret] = filter;
9855 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9860 /* Delete ethertype filter in SW list */
9862 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9863 struct i40e_ethertype_filter_input *input)
9865 struct i40e_ethertype_rule *rule = &pf->ethertype;
9866 struct i40e_ethertype_filter *filter;
9869 ret = rte_hash_del_key(rule->hash_table, input);
9872 "Failed to delete ethertype filter"
9873 " to hash table %d!",
9877 filter = rule->hash_map[ret];
9878 rule->hash_map[ret] = NULL;
9880 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9887 * Configure ethertype filter, which can director packet by filtering
9888 * with mac address and ether_type or only ether_type
9891 i40e_ethertype_filter_set(struct i40e_pf *pf,
9892 struct rte_eth_ethertype_filter *filter,
9895 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9896 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9897 struct i40e_ethertype_filter *ethertype_filter, *node;
9898 struct i40e_ethertype_filter check_filter;
9899 struct i40e_control_filter_stats stats;
9903 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9904 PMD_DRV_LOG(ERR, "Invalid queue ID");
9907 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9908 filter->ether_type == ETHER_TYPE_IPv6) {
9910 "unsupported ether_type(0x%04x) in control packet filter.",
9911 filter->ether_type);
9914 if (filter->ether_type == ETHER_TYPE_VLAN)
9915 PMD_DRV_LOG(WARNING,
9916 "filter vlan ether_type in first tag is not supported.");
9918 /* Check if there is the filter in SW list */
9919 memset(&check_filter, 0, sizeof(check_filter));
9920 i40e_ethertype_filter_convert(filter, &check_filter);
9921 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9922 &check_filter.input);
9924 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9928 if (!add && !node) {
9929 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9933 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9934 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9935 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9936 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9937 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9939 memset(&stats, 0, sizeof(stats));
9940 ret = i40e_aq_add_rem_control_packet_filter(hw,
9941 filter->mac_addr.addr_bytes,
9942 filter->ether_type, flags,
9944 filter->queue, add, &stats, NULL);
9947 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9948 ret, stats.mac_etype_used, stats.etype_used,
9949 stats.mac_etype_free, stats.etype_free);
9953 /* Add or delete a filter in SW list */
9955 ethertype_filter = rte_zmalloc("ethertype_filter",
9956 sizeof(*ethertype_filter), 0);
9957 if (ethertype_filter == NULL) {
9958 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9962 rte_memcpy(ethertype_filter, &check_filter,
9963 sizeof(check_filter));
9964 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9966 rte_free(ethertype_filter);
9968 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9975 * Handle operations for ethertype filter.
9978 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9979 enum rte_filter_op filter_op,
9982 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9985 if (filter_op == RTE_ETH_FILTER_NOP)
9989 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9994 switch (filter_op) {
9995 case RTE_ETH_FILTER_ADD:
9996 ret = i40e_ethertype_filter_set(pf,
9997 (struct rte_eth_ethertype_filter *)arg,
10000 case RTE_ETH_FILTER_DELETE:
10001 ret = i40e_ethertype_filter_set(pf,
10002 (struct rte_eth_ethertype_filter *)arg,
10006 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10014 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10015 enum rte_filter_type filter_type,
10016 enum rte_filter_op filter_op,
10024 switch (filter_type) {
10025 case RTE_ETH_FILTER_NONE:
10026 /* For global configuration */
10027 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10029 case RTE_ETH_FILTER_HASH:
10030 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10032 case RTE_ETH_FILTER_MACVLAN:
10033 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10035 case RTE_ETH_FILTER_ETHERTYPE:
10036 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10038 case RTE_ETH_FILTER_TUNNEL:
10039 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10041 case RTE_ETH_FILTER_FDIR:
10042 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10044 case RTE_ETH_FILTER_GENERIC:
10045 if (filter_op != RTE_ETH_FILTER_GET)
10047 *(const void **)arg = &i40e_flow_ops;
10050 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10060 * Check and enable Extended Tag.
10061 * Enabling Extended Tag is important for 40G performance.
10064 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10066 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10070 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10073 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10077 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10078 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10083 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10086 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10090 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10091 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10094 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10095 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10098 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10105 * As some registers wouldn't be reset unless a global hardware reset,
10106 * hardware initialization is needed to put those registers into an
10107 * expected initial state.
10110 i40e_hw_init(struct rte_eth_dev *dev)
10112 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10114 i40e_enable_extended_tag(dev);
10116 /* clear the PF Queue Filter control register */
10117 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10119 /* Disable symmetric hash per port */
10120 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10124 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10125 * however this function will return only one highest pctype index,
10126 * which is not quite correct. This is known problem of i40e driver
10127 * and needs to be fixed later.
10129 enum i40e_filter_pctype
10130 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10133 uint64_t pctype_mask;
10135 if (flow_type < I40E_FLOW_TYPE_MAX) {
10136 pctype_mask = adapter->pctypes_tbl[flow_type];
10137 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10138 if (pctype_mask & (1ULL << i))
10139 return (enum i40e_filter_pctype)i;
10142 return I40E_FILTER_PCTYPE_INVALID;
10146 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10147 enum i40e_filter_pctype pctype)
10150 uint64_t pctype_mask = 1ULL << pctype;
10152 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10154 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10158 return RTE_ETH_FLOW_UNKNOWN;
10162 * On X710, performance number is far from the expectation on recent firmware
10163 * versions; on XL710, performance number is also far from the expectation on
10164 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10165 * mode is enabled and port MAC address is equal to the packet destination MAC
10166 * address. The fix for this issue may not be integrated in the following
10167 * firmware version. So the workaround in software driver is needed. It needs
10168 * to modify the initial values of 3 internal only registers for both X710 and
10169 * XL710. Note that the values for X710 or XL710 could be different, and the
10170 * workaround can be removed when it is fixed in firmware in the future.
10173 /* For both X710 and XL710 */
10174 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10175 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10176 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10178 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10179 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10182 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10183 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10186 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10188 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10189 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10192 * GL_SWR_PM_UP_THR:
10193 * The value is not impacted from the link speed, its value is set according
10194 * to the total number of ports for a better pipe-monitor configuration.
10197 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10199 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10200 .device_id = (dev), \
10201 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10203 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10204 .device_id = (dev), \
10205 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10207 static const struct {
10208 uint16_t device_id;
10210 } swr_pm_table[] = {
10211 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10212 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10213 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10214 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10216 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10217 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10218 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10219 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10220 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10221 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10222 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10226 if (value == NULL) {
10227 PMD_DRV_LOG(ERR, "value is NULL");
10231 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10232 if (hw->device_id == swr_pm_table[i].device_id) {
10233 *value = swr_pm_table[i].val;
10235 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10237 hw->device_id, *value);
10246 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10248 enum i40e_status_code status;
10249 struct i40e_aq_get_phy_abilities_resp phy_ab;
10250 int ret = -ENOTSUP;
10253 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10257 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10260 rte_delay_us(100000);
10262 status = i40e_aq_get_phy_capabilities(hw, false,
10263 true, &phy_ab, NULL);
10271 i40e_configure_registers(struct i40e_hw *hw)
10277 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10278 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10279 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10285 for (i = 0; i < RTE_DIM(reg_table); i++) {
10286 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10287 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10289 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10290 else /* For X710/XL710/XXV710 */
10291 if (hw->aq.fw_maj_ver < 6)
10293 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10296 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10299 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10300 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10302 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10303 else /* For X710/XL710/XXV710 */
10305 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10308 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10311 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10312 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10313 "GL_SWR_PM_UP_THR value fixup",
10318 reg_table[i].val = cfg_val;
10321 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10324 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10325 reg_table[i].addr);
10328 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10329 reg_table[i].addr, reg);
10330 if (reg == reg_table[i].val)
10333 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10334 reg_table[i].val, NULL);
10337 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10338 reg_table[i].val, reg_table[i].addr);
10341 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10342 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10346 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10347 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10348 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10349 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10351 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10356 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10357 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10361 /* Configure for double VLAN RX stripping */
10362 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10363 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10364 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10365 ret = i40e_aq_debug_write_register(hw,
10366 I40E_VSI_TSR(vsi->vsi_id),
10369 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10371 return I40E_ERR_CONFIG;
10375 /* Configure for double VLAN TX insertion */
10376 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10377 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10378 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10379 ret = i40e_aq_debug_write_register(hw,
10380 I40E_VSI_L2TAGSTXVALID(
10381 vsi->vsi_id), reg, NULL);
10384 "Failed to update VSI_L2TAGSTXVALID[%d]",
10386 return I40E_ERR_CONFIG;
10394 * i40e_aq_add_mirror_rule
10395 * @hw: pointer to the hardware structure
10396 * @seid: VEB seid to add mirror rule to
10397 * @dst_id: destination vsi seid
10398 * @entries: Buffer which contains the entities to be mirrored
10399 * @count: number of entities contained in the buffer
10400 * @rule_id:the rule_id of the rule to be added
10402 * Add a mirror rule for a given veb.
10405 static enum i40e_status_code
10406 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10407 uint16_t seid, uint16_t dst_id,
10408 uint16_t rule_type, uint16_t *entries,
10409 uint16_t count, uint16_t *rule_id)
10411 struct i40e_aq_desc desc;
10412 struct i40e_aqc_add_delete_mirror_rule cmd;
10413 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10414 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10417 enum i40e_status_code status;
10419 i40e_fill_default_direct_cmd_desc(&desc,
10420 i40e_aqc_opc_add_mirror_rule);
10421 memset(&cmd, 0, sizeof(cmd));
10423 buff_len = sizeof(uint16_t) * count;
10424 desc.datalen = rte_cpu_to_le_16(buff_len);
10426 desc.flags |= rte_cpu_to_le_16(
10427 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10428 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10429 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10430 cmd.num_entries = rte_cpu_to_le_16(count);
10431 cmd.seid = rte_cpu_to_le_16(seid);
10432 cmd.destination = rte_cpu_to_le_16(dst_id);
10434 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10435 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10437 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10438 hw->aq.asq_last_status, resp->rule_id,
10439 resp->mirror_rules_used, resp->mirror_rules_free);
10440 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10446 * i40e_aq_del_mirror_rule
10447 * @hw: pointer to the hardware structure
10448 * @seid: VEB seid to add mirror rule to
10449 * @entries: Buffer which contains the entities to be mirrored
10450 * @count: number of entities contained in the buffer
10451 * @rule_id:the rule_id of the rule to be delete
10453 * Delete a mirror rule for a given veb.
10456 static enum i40e_status_code
10457 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10458 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10459 uint16_t count, uint16_t rule_id)
10461 struct i40e_aq_desc desc;
10462 struct i40e_aqc_add_delete_mirror_rule cmd;
10463 uint16_t buff_len = 0;
10464 enum i40e_status_code status;
10467 i40e_fill_default_direct_cmd_desc(&desc,
10468 i40e_aqc_opc_delete_mirror_rule);
10469 memset(&cmd, 0, sizeof(cmd));
10470 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10471 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10473 cmd.num_entries = count;
10474 buff_len = sizeof(uint16_t) * count;
10475 desc.datalen = rte_cpu_to_le_16(buff_len);
10476 buff = (void *)entries;
10478 /* rule id is filled in destination field for deleting mirror rule */
10479 cmd.destination = rte_cpu_to_le_16(rule_id);
10481 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10482 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10483 cmd.seid = rte_cpu_to_le_16(seid);
10485 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10486 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10492 * i40e_mirror_rule_set
10493 * @dev: pointer to the hardware structure
10494 * @mirror_conf: mirror rule info
10495 * @sw_id: mirror rule's sw_id
10496 * @on: enable/disable
10498 * set a mirror rule.
10502 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10503 struct rte_eth_mirror_conf *mirror_conf,
10504 uint8_t sw_id, uint8_t on)
10506 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10507 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10508 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10509 struct i40e_mirror_rule *parent = NULL;
10510 uint16_t seid, dst_seid, rule_id;
10514 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10516 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10518 "mirror rule can not be configured without veb or vfs.");
10521 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10522 PMD_DRV_LOG(ERR, "mirror table is full.");
10525 if (mirror_conf->dst_pool > pf->vf_num) {
10526 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10527 mirror_conf->dst_pool);
10531 seid = pf->main_vsi->veb->seid;
10533 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10534 if (sw_id <= it->index) {
10540 if (mirr_rule && sw_id == mirr_rule->index) {
10542 PMD_DRV_LOG(ERR, "mirror rule exists.");
10545 ret = i40e_aq_del_mirror_rule(hw, seid,
10546 mirr_rule->rule_type,
10547 mirr_rule->entries,
10548 mirr_rule->num_entries, mirr_rule->id);
10551 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10552 ret, hw->aq.asq_last_status);
10555 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10556 rte_free(mirr_rule);
10557 pf->nb_mirror_rule--;
10561 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10565 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10566 sizeof(struct i40e_mirror_rule) , 0);
10568 PMD_DRV_LOG(ERR, "failed to allocate memory");
10569 return I40E_ERR_NO_MEMORY;
10571 switch (mirror_conf->rule_type) {
10572 case ETH_MIRROR_VLAN:
10573 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10574 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10575 mirr_rule->entries[j] =
10576 mirror_conf->vlan.vlan_id[i];
10581 PMD_DRV_LOG(ERR, "vlan is not specified.");
10582 rte_free(mirr_rule);
10585 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10587 case ETH_MIRROR_VIRTUAL_POOL_UP:
10588 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10589 /* check if the specified pool bit is out of range */
10590 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10591 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10592 rte_free(mirr_rule);
10595 for (i = 0, j = 0; i < pf->vf_num; i++) {
10596 if (mirror_conf->pool_mask & (1ULL << i)) {
10597 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10601 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10602 /* add pf vsi to entries */
10603 mirr_rule->entries[j] = pf->main_vsi_seid;
10607 PMD_DRV_LOG(ERR, "pool is not specified.");
10608 rte_free(mirr_rule);
10611 /* egress and ingress in aq commands means from switch but not port */
10612 mirr_rule->rule_type =
10613 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10614 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10615 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10617 case ETH_MIRROR_UPLINK_PORT:
10618 /* egress and ingress in aq commands means from switch but not port*/
10619 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10621 case ETH_MIRROR_DOWNLINK_PORT:
10622 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10625 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10626 mirror_conf->rule_type);
10627 rte_free(mirr_rule);
10631 /* If the dst_pool is equal to vf_num, consider it as PF */
10632 if (mirror_conf->dst_pool == pf->vf_num)
10633 dst_seid = pf->main_vsi_seid;
10635 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10637 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10638 mirr_rule->rule_type, mirr_rule->entries,
10642 "failed to add mirror rule: ret = %d, aq_err = %d.",
10643 ret, hw->aq.asq_last_status);
10644 rte_free(mirr_rule);
10648 mirr_rule->index = sw_id;
10649 mirr_rule->num_entries = j;
10650 mirr_rule->id = rule_id;
10651 mirr_rule->dst_vsi_seid = dst_seid;
10654 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10656 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10658 pf->nb_mirror_rule++;
10663 * i40e_mirror_rule_reset
10664 * @dev: pointer to the device
10665 * @sw_id: mirror rule's sw_id
10667 * reset a mirror rule.
10671 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10673 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10674 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10675 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10679 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10681 seid = pf->main_vsi->veb->seid;
10683 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10684 if (sw_id == it->index) {
10690 ret = i40e_aq_del_mirror_rule(hw, seid,
10691 mirr_rule->rule_type,
10692 mirr_rule->entries,
10693 mirr_rule->num_entries, mirr_rule->id);
10696 "failed to remove mirror rule: status = %d, aq_err = %d.",
10697 ret, hw->aq.asq_last_status);
10700 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10701 rte_free(mirr_rule);
10702 pf->nb_mirror_rule--;
10704 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10711 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10713 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10714 uint64_t systim_cycles;
10716 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10717 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10720 return systim_cycles;
10724 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10726 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10727 uint64_t rx_tstamp;
10729 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10730 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10737 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10739 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10740 uint64_t tx_tstamp;
10742 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10743 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10750 i40e_start_timecounters(struct rte_eth_dev *dev)
10752 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10753 struct i40e_adapter *adapter =
10754 (struct i40e_adapter *)dev->data->dev_private;
10755 struct rte_eth_link link;
10756 uint32_t tsync_inc_l;
10757 uint32_t tsync_inc_h;
10759 /* Get current link speed. */
10760 i40e_dev_link_update(dev, 1);
10761 rte_eth_linkstatus_get(dev, &link);
10763 switch (link.link_speed) {
10764 case ETH_SPEED_NUM_40G:
10765 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10766 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10768 case ETH_SPEED_NUM_10G:
10769 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10770 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10772 case ETH_SPEED_NUM_1G:
10773 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10774 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10781 /* Set the timesync increment value. */
10782 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10783 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10785 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10786 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10787 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10789 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10790 adapter->systime_tc.cc_shift = 0;
10791 adapter->systime_tc.nsec_mask = 0;
10793 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10794 adapter->rx_tstamp_tc.cc_shift = 0;
10795 adapter->rx_tstamp_tc.nsec_mask = 0;
10797 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10798 adapter->tx_tstamp_tc.cc_shift = 0;
10799 adapter->tx_tstamp_tc.nsec_mask = 0;
10803 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10805 struct i40e_adapter *adapter =
10806 (struct i40e_adapter *)dev->data->dev_private;
10808 adapter->systime_tc.nsec += delta;
10809 adapter->rx_tstamp_tc.nsec += delta;
10810 adapter->tx_tstamp_tc.nsec += delta;
10816 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10819 struct i40e_adapter *adapter =
10820 (struct i40e_adapter *)dev->data->dev_private;
10822 ns = rte_timespec_to_ns(ts);
10824 /* Set the timecounters to a new value. */
10825 adapter->systime_tc.nsec = ns;
10826 adapter->rx_tstamp_tc.nsec = ns;
10827 adapter->tx_tstamp_tc.nsec = ns;
10833 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10835 uint64_t ns, systime_cycles;
10836 struct i40e_adapter *adapter =
10837 (struct i40e_adapter *)dev->data->dev_private;
10839 systime_cycles = i40e_read_systime_cyclecounter(dev);
10840 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10841 *ts = rte_ns_to_timespec(ns);
10847 i40e_timesync_enable(struct rte_eth_dev *dev)
10849 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10850 uint32_t tsync_ctl_l;
10851 uint32_t tsync_ctl_h;
10853 /* Stop the timesync system time. */
10854 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10855 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10856 /* Reset the timesync system time value. */
10857 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10858 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10860 i40e_start_timecounters(dev);
10862 /* Clear timesync registers. */
10863 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10864 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10865 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10866 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10867 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10868 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10870 /* Enable timestamping of PTP packets. */
10871 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10872 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10874 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10875 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10876 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10878 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10879 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10885 i40e_timesync_disable(struct rte_eth_dev *dev)
10887 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10888 uint32_t tsync_ctl_l;
10889 uint32_t tsync_ctl_h;
10891 /* Disable timestamping of transmitted PTP packets. */
10892 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10893 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10895 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10896 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10898 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10899 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10901 /* Reset the timesync increment value. */
10902 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10903 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10909 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10910 struct timespec *timestamp, uint32_t flags)
10912 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10913 struct i40e_adapter *adapter =
10914 (struct i40e_adapter *)dev->data->dev_private;
10916 uint32_t sync_status;
10917 uint32_t index = flags & 0x03;
10918 uint64_t rx_tstamp_cycles;
10921 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10922 if ((sync_status & (1 << index)) == 0)
10925 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10926 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10927 *timestamp = rte_ns_to_timespec(ns);
10933 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10934 struct timespec *timestamp)
10936 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10937 struct i40e_adapter *adapter =
10938 (struct i40e_adapter *)dev->data->dev_private;
10940 uint32_t sync_status;
10941 uint64_t tx_tstamp_cycles;
10944 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10945 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10948 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10949 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10950 *timestamp = rte_ns_to_timespec(ns);
10956 * i40e_parse_dcb_configure - parse dcb configure from user
10957 * @dev: the device being configured
10958 * @dcb_cfg: pointer of the result of parse
10959 * @*tc_map: bit map of enabled traffic classes
10961 * Returns 0 on success, negative value on failure
10964 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10965 struct i40e_dcbx_config *dcb_cfg,
10968 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10969 uint8_t i, tc_bw, bw_lf;
10971 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10973 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10974 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10975 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10979 /* assume each tc has the same bw */
10980 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10981 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10982 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10983 /* to ensure the sum of tcbw is equal to 100 */
10984 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10985 for (i = 0; i < bw_lf; i++)
10986 dcb_cfg->etscfg.tcbwtable[i]++;
10988 /* assume each tc has the same Transmission Selection Algorithm */
10989 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10990 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10992 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10993 dcb_cfg->etscfg.prioritytable[i] =
10994 dcb_rx_conf->dcb_tc[i];
10996 /* FW needs one App to configure HW */
10997 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10998 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10999 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11000 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11002 if (dcb_rx_conf->nb_tcs == 0)
11003 *tc_map = 1; /* tc0 only */
11005 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11007 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11008 dcb_cfg->pfc.willing = 0;
11009 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11010 dcb_cfg->pfc.pfcenable = *tc_map;
11016 static enum i40e_status_code
11017 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11018 struct i40e_aqc_vsi_properties_data *info,
11019 uint8_t enabled_tcmap)
11021 enum i40e_status_code ret;
11022 int i, total_tc = 0;
11023 uint16_t qpnum_per_tc, bsf, qp_idx;
11024 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11025 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11026 uint16_t used_queues;
11028 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11029 if (ret != I40E_SUCCESS)
11032 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11033 if (enabled_tcmap & (1 << i))
11038 vsi->enabled_tc = enabled_tcmap;
11040 /* different VSI has different queues assigned */
11041 if (vsi->type == I40E_VSI_MAIN)
11042 used_queues = dev_data->nb_rx_queues -
11043 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11044 else if (vsi->type == I40E_VSI_VMDQ2)
11045 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11047 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11048 return I40E_ERR_NO_AVAILABLE_VSI;
11051 qpnum_per_tc = used_queues / total_tc;
11052 /* Number of queues per enabled TC */
11053 if (qpnum_per_tc == 0) {
11054 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11055 return I40E_ERR_INVALID_QP_ID;
11057 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11058 I40E_MAX_Q_PER_TC);
11059 bsf = rte_bsf32(qpnum_per_tc);
11062 * Configure TC and queue mapping parameters, for enabled TC,
11063 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11064 * default queue will serve it.
11067 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11068 if (vsi->enabled_tc & (1 << i)) {
11069 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11070 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11071 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11072 qp_idx += qpnum_per_tc;
11074 info->tc_mapping[i] = 0;
11077 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11078 if (vsi->type == I40E_VSI_SRIOV) {
11079 info->mapping_flags |=
11080 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11081 for (i = 0; i < vsi->nb_qps; i++)
11082 info->queue_mapping[i] =
11083 rte_cpu_to_le_16(vsi->base_queue + i);
11085 info->mapping_flags |=
11086 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11087 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11089 info->valid_sections |=
11090 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11092 return I40E_SUCCESS;
11096 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11097 * @veb: VEB to be configured
11098 * @tc_map: enabled TC bitmap
11100 * Returns 0 on success, negative value on failure
11102 static enum i40e_status_code
11103 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11105 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11106 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11107 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11108 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11109 enum i40e_status_code ret = I40E_SUCCESS;
11113 /* Check if enabled_tc is same as existing or new TCs */
11114 if (veb->enabled_tc == tc_map)
11117 /* configure tc bandwidth */
11118 memset(&veb_bw, 0, sizeof(veb_bw));
11119 veb_bw.tc_valid_bits = tc_map;
11120 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11121 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11122 if (tc_map & BIT_ULL(i))
11123 veb_bw.tc_bw_share_credits[i] = 1;
11125 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11129 "AQ command Config switch_comp BW allocation per TC failed = %d",
11130 hw->aq.asq_last_status);
11134 memset(&ets_query, 0, sizeof(ets_query));
11135 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11137 if (ret != I40E_SUCCESS) {
11139 "Failed to get switch_comp ETS configuration %u",
11140 hw->aq.asq_last_status);
11143 memset(&bw_query, 0, sizeof(bw_query));
11144 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11146 if (ret != I40E_SUCCESS) {
11148 "Failed to get switch_comp bandwidth configuration %u",
11149 hw->aq.asq_last_status);
11153 /* store and print out BW info */
11154 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11155 veb->bw_info.bw_max = ets_query.tc_bw_max;
11156 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11157 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11158 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11159 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11160 I40E_16_BIT_WIDTH);
11161 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11162 veb->bw_info.bw_ets_share_credits[i] =
11163 bw_query.tc_bw_share_credits[i];
11164 veb->bw_info.bw_ets_credits[i] =
11165 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11166 /* 4 bits per TC, 4th bit is reserved */
11167 veb->bw_info.bw_ets_max[i] =
11168 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11169 RTE_LEN2MASK(3, uint8_t));
11170 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11171 veb->bw_info.bw_ets_share_credits[i]);
11172 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11173 veb->bw_info.bw_ets_credits[i]);
11174 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11175 veb->bw_info.bw_ets_max[i]);
11178 veb->enabled_tc = tc_map;
11185 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11186 * @vsi: VSI to be configured
11187 * @tc_map: enabled TC bitmap
11189 * Returns 0 on success, negative value on failure
11191 static enum i40e_status_code
11192 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11194 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11195 struct i40e_vsi_context ctxt;
11196 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11197 enum i40e_status_code ret = I40E_SUCCESS;
11200 /* Check if enabled_tc is same as existing or new TCs */
11201 if (vsi->enabled_tc == tc_map)
11204 /* configure tc bandwidth */
11205 memset(&bw_data, 0, sizeof(bw_data));
11206 bw_data.tc_valid_bits = tc_map;
11207 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11208 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11209 if (tc_map & BIT_ULL(i))
11210 bw_data.tc_bw_credits[i] = 1;
11212 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11215 "AQ command Config VSI BW allocation per TC failed = %d",
11216 hw->aq.asq_last_status);
11219 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11220 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11222 /* Update Queue Pairs Mapping for currently enabled UPs */
11223 ctxt.seid = vsi->seid;
11224 ctxt.pf_num = hw->pf_id;
11226 ctxt.uplink_seid = vsi->uplink_seid;
11227 ctxt.info = vsi->info;
11229 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11233 /* Update the VSI after updating the VSI queue-mapping information */
11234 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11236 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11237 hw->aq.asq_last_status);
11240 /* update the local VSI info with updated queue map */
11241 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11242 sizeof(vsi->info.tc_mapping));
11243 rte_memcpy(&vsi->info.queue_mapping,
11244 &ctxt.info.queue_mapping,
11245 sizeof(vsi->info.queue_mapping));
11246 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11247 vsi->info.valid_sections = 0;
11249 /* query and update current VSI BW information */
11250 ret = i40e_vsi_get_bw_config(vsi);
11253 "Failed updating vsi bw info, err %s aq_err %s",
11254 i40e_stat_str(hw, ret),
11255 i40e_aq_str(hw, hw->aq.asq_last_status));
11259 vsi->enabled_tc = tc_map;
11266 * i40e_dcb_hw_configure - program the dcb setting to hw
11267 * @pf: pf the configuration is taken on
11268 * @new_cfg: new configuration
11269 * @tc_map: enabled TC bitmap
11271 * Returns 0 on success, negative value on failure
11273 static enum i40e_status_code
11274 i40e_dcb_hw_configure(struct i40e_pf *pf,
11275 struct i40e_dcbx_config *new_cfg,
11278 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11279 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11280 struct i40e_vsi *main_vsi = pf->main_vsi;
11281 struct i40e_vsi_list *vsi_list;
11282 enum i40e_status_code ret;
11286 /* Use the FW API if FW > v4.4*/
11287 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11288 (hw->aq.fw_maj_ver >= 5))) {
11290 "FW < v4.4, can not use FW LLDP API to configure DCB");
11291 return I40E_ERR_FIRMWARE_API_VERSION;
11294 /* Check if need reconfiguration */
11295 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11296 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11297 return I40E_SUCCESS;
11300 /* Copy the new config to the current config */
11301 *old_cfg = *new_cfg;
11302 old_cfg->etsrec = old_cfg->etscfg;
11303 ret = i40e_set_dcb_config(hw);
11305 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11306 i40e_stat_str(hw, ret),
11307 i40e_aq_str(hw, hw->aq.asq_last_status));
11310 /* set receive Arbiter to RR mode and ETS scheme by default */
11311 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11312 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11313 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11314 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11315 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11316 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11317 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11318 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11319 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11320 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11321 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11322 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11323 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11325 /* get local mib to check whether it is configured correctly */
11327 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11328 /* Get Local DCB Config */
11329 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11330 &hw->local_dcbx_config);
11332 /* if Veb is created, need to update TC of it at first */
11333 if (main_vsi->veb) {
11334 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11336 PMD_INIT_LOG(WARNING,
11337 "Failed configuring TC for VEB seid=%d",
11338 main_vsi->veb->seid);
11340 /* Update each VSI */
11341 i40e_vsi_config_tc(main_vsi, tc_map);
11342 if (main_vsi->veb) {
11343 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11344 /* Beside main VSI and VMDQ VSIs, only enable default
11345 * TC for other VSIs
11347 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11348 ret = i40e_vsi_config_tc(vsi_list->vsi,
11351 ret = i40e_vsi_config_tc(vsi_list->vsi,
11352 I40E_DEFAULT_TCMAP);
11354 PMD_INIT_LOG(WARNING,
11355 "Failed configuring TC for VSI seid=%d",
11356 vsi_list->vsi->seid);
11360 return I40E_SUCCESS;
11364 * i40e_dcb_init_configure - initial dcb config
11365 * @dev: device being configured
11366 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11368 * Returns 0 on success, negative value on failure
11371 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11373 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11374 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11377 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11378 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11382 /* DCB initialization:
11383 * Update DCB configuration from the Firmware and configure
11384 * LLDP MIB change event.
11386 if (sw_dcb == TRUE) {
11387 /* When using NVM 6.01 or later, the RX data path does
11388 * not hang if the FW LLDP is stopped.
11390 if (((hw->nvm.version >> 12) & 0xf) >= 6 &&
11391 ((hw->nvm.version >> 4) & 0xff) >= 1) {
11392 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11393 if (ret != I40E_SUCCESS)
11394 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11397 ret = i40e_init_dcb(hw);
11398 /* If lldp agent is stopped, the return value from
11399 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11400 * adminq status. Otherwise, it should return success.
11402 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11403 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11404 memset(&hw->local_dcbx_config, 0,
11405 sizeof(struct i40e_dcbx_config));
11406 /* set dcb default configuration */
11407 hw->local_dcbx_config.etscfg.willing = 0;
11408 hw->local_dcbx_config.etscfg.maxtcs = 0;
11409 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11410 hw->local_dcbx_config.etscfg.tsatable[0] =
11412 /* all UPs mapping to TC0 */
11413 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11414 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11415 hw->local_dcbx_config.etsrec =
11416 hw->local_dcbx_config.etscfg;
11417 hw->local_dcbx_config.pfc.willing = 0;
11418 hw->local_dcbx_config.pfc.pfccap =
11419 I40E_MAX_TRAFFIC_CLASS;
11420 /* FW needs one App to configure HW */
11421 hw->local_dcbx_config.numapps = 1;
11422 hw->local_dcbx_config.app[0].selector =
11423 I40E_APP_SEL_ETHTYPE;
11424 hw->local_dcbx_config.app[0].priority = 3;
11425 hw->local_dcbx_config.app[0].protocolid =
11426 I40E_APP_PROTOID_FCOE;
11427 ret = i40e_set_dcb_config(hw);
11430 "default dcb config fails. err = %d, aq_err = %d.",
11431 ret, hw->aq.asq_last_status);
11436 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11437 ret, hw->aq.asq_last_status);
11441 ret = i40e_aq_start_lldp(hw, NULL);
11442 if (ret != I40E_SUCCESS)
11443 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11445 ret = i40e_init_dcb(hw);
11447 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11449 "HW doesn't support DCBX offload.");
11454 "DCBX configuration failed, err = %d, aq_err = %d.",
11455 ret, hw->aq.asq_last_status);
11463 * i40e_dcb_setup - setup dcb related config
11464 * @dev: device being configured
11466 * Returns 0 on success, negative value on failure
11469 i40e_dcb_setup(struct rte_eth_dev *dev)
11471 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11472 struct i40e_dcbx_config dcb_cfg;
11473 uint8_t tc_map = 0;
11476 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11477 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11481 if (pf->vf_num != 0)
11482 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11484 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11486 PMD_INIT_LOG(ERR, "invalid dcb config");
11489 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11491 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11499 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11500 struct rte_eth_dcb_info *dcb_info)
11502 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11503 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11504 struct i40e_vsi *vsi = pf->main_vsi;
11505 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11506 uint16_t bsf, tc_mapping;
11509 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11510 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11512 dcb_info->nb_tcs = 1;
11513 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11514 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11515 for (i = 0; i < dcb_info->nb_tcs; i++)
11516 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11518 /* get queue mapping if vmdq is disabled */
11519 if (!pf->nb_cfg_vmdq_vsi) {
11520 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11521 if (!(vsi->enabled_tc & (1 << i)))
11523 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11524 dcb_info->tc_queue.tc_rxq[j][i].base =
11525 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11526 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11527 dcb_info->tc_queue.tc_txq[j][i].base =
11528 dcb_info->tc_queue.tc_rxq[j][i].base;
11529 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11530 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11531 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11532 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11533 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11538 /* get queue mapping if vmdq is enabled */
11540 vsi = pf->vmdq[j].vsi;
11541 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11542 if (!(vsi->enabled_tc & (1 << i)))
11544 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11545 dcb_info->tc_queue.tc_rxq[j][i].base =
11546 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11547 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11548 dcb_info->tc_queue.tc_txq[j][i].base =
11549 dcb_info->tc_queue.tc_rxq[j][i].base;
11550 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11551 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11552 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11553 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11554 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11557 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11562 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11564 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11565 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11566 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11567 uint16_t msix_intr;
11569 msix_intr = intr_handle->intr_vec[queue_id];
11570 if (msix_intr == I40E_MISC_VEC_ID)
11571 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11572 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11573 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11574 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11577 I40E_PFINT_DYN_CTLN(msix_intr -
11578 I40E_RX_VEC_START),
11579 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11580 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11581 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11583 I40E_WRITE_FLUSH(hw);
11584 rte_intr_enable(&pci_dev->intr_handle);
11590 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11592 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11593 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11594 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11595 uint16_t msix_intr;
11597 msix_intr = intr_handle->intr_vec[queue_id];
11598 if (msix_intr == I40E_MISC_VEC_ID)
11599 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11600 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11603 I40E_PFINT_DYN_CTLN(msix_intr -
11604 I40E_RX_VEC_START),
11605 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11606 I40E_WRITE_FLUSH(hw);
11611 static int i40e_get_regs(struct rte_eth_dev *dev,
11612 struct rte_dev_reg_info *regs)
11614 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11615 uint32_t *ptr_data = regs->data;
11616 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11617 const struct i40e_reg_info *reg_info;
11619 if (ptr_data == NULL) {
11620 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11621 regs->width = sizeof(uint32_t);
11625 /* The first few registers have to be read using AQ operations */
11627 while (i40e_regs_adminq[reg_idx].name) {
11628 reg_info = &i40e_regs_adminq[reg_idx++];
11629 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11631 arr_idx2 <= reg_info->count2;
11633 reg_offset = arr_idx * reg_info->stride1 +
11634 arr_idx2 * reg_info->stride2;
11635 reg_offset += reg_info->base_addr;
11636 ptr_data[reg_offset >> 2] =
11637 i40e_read_rx_ctl(hw, reg_offset);
11641 /* The remaining registers can be read using primitives */
11643 while (i40e_regs_others[reg_idx].name) {
11644 reg_info = &i40e_regs_others[reg_idx++];
11645 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11647 arr_idx2 <= reg_info->count2;
11649 reg_offset = arr_idx * reg_info->stride1 +
11650 arr_idx2 * reg_info->stride2;
11651 reg_offset += reg_info->base_addr;
11652 ptr_data[reg_offset >> 2] =
11653 I40E_READ_REG(hw, reg_offset);
11660 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11662 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11664 /* Convert word count to byte count */
11665 return hw->nvm.sr_size << 1;
11668 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11669 struct rte_dev_eeprom_info *eeprom)
11671 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11672 uint16_t *data = eeprom->data;
11673 uint16_t offset, length, cnt_words;
11676 offset = eeprom->offset >> 1;
11677 length = eeprom->length >> 1;
11678 cnt_words = length;
11680 if (offset > hw->nvm.sr_size ||
11681 offset + length > hw->nvm.sr_size) {
11682 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11686 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11688 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11689 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11690 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11697 static int i40e_get_module_info(struct rte_eth_dev *dev,
11698 struct rte_eth_dev_module_info *modinfo)
11700 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11701 uint32_t sff8472_comp = 0;
11702 uint32_t sff8472_swap = 0;
11703 uint32_t sff8636_rev = 0;
11704 i40e_status status;
11707 /* Check if firmware supports reading module EEPROM. */
11708 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11710 "Module EEPROM memory read not supported. "
11711 "Please update the NVM image.\n");
11715 status = i40e_update_link_info(hw);
11719 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11721 "Cannot read module EEPROM memory. "
11722 "No module connected.\n");
11726 type = hw->phy.link_info.module_type[0];
11729 case I40E_MODULE_TYPE_SFP:
11730 status = i40e_aq_get_phy_register(hw,
11731 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11732 I40E_I2C_EEPROM_DEV_ADDR, 1,
11733 I40E_MODULE_SFF_8472_COMP,
11734 &sff8472_comp, NULL);
11738 status = i40e_aq_get_phy_register(hw,
11739 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11740 I40E_I2C_EEPROM_DEV_ADDR, 1,
11741 I40E_MODULE_SFF_8472_SWAP,
11742 &sff8472_swap, NULL);
11746 /* Check if the module requires address swap to access
11747 * the other EEPROM memory page.
11749 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11750 PMD_DRV_LOG(WARNING,
11751 "Module address swap to access "
11752 "page 0xA2 is not supported.\n");
11753 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11754 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11755 } else if (sff8472_comp == 0x00) {
11756 /* Module is not SFF-8472 compliant */
11757 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11758 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11760 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11761 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11764 case I40E_MODULE_TYPE_QSFP_PLUS:
11765 /* Read from memory page 0. */
11766 status = i40e_aq_get_phy_register(hw,
11767 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11769 I40E_MODULE_REVISION_ADDR,
11770 &sff8636_rev, NULL);
11773 /* Determine revision compliance byte */
11774 if (sff8636_rev > 0x02) {
11775 /* Module is SFF-8636 compliant */
11776 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11777 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11779 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11780 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11783 case I40E_MODULE_TYPE_QSFP28:
11784 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11785 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11788 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11794 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11795 struct rte_dev_eeprom_info *info)
11797 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11798 bool is_sfp = false;
11799 i40e_status status;
11800 uint8_t *data = info->data;
11801 uint32_t value = 0;
11804 if (!info || !info->length || !data)
11807 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11810 for (i = 0; i < info->length; i++) {
11811 u32 offset = i + info->offset;
11812 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11814 /* Check if we need to access the other memory page */
11816 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11817 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11818 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11821 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11822 /* Compute memory page number and offset. */
11823 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11827 status = i40e_aq_get_phy_register(hw,
11828 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11829 addr, offset, 1, &value, NULL);
11832 data[i] = (uint8_t)value;
11837 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11838 struct ether_addr *mac_addr)
11840 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11841 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11842 struct i40e_vsi *vsi = pf->main_vsi;
11843 struct i40e_mac_filter_info mac_filter;
11844 struct i40e_mac_filter *f;
11847 if (!is_valid_assigned_ether_addr(mac_addr)) {
11848 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11852 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11853 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11858 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11862 mac_filter = f->mac_info;
11863 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11864 if (ret != I40E_SUCCESS) {
11865 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11868 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11869 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11870 if (ret != I40E_SUCCESS) {
11871 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11874 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11876 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11877 mac_addr->addr_bytes, NULL);
11878 if (ret != I40E_SUCCESS) {
11879 PMD_DRV_LOG(ERR, "Failed to change mac");
11887 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11889 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11890 struct rte_eth_dev_data *dev_data = pf->dev_data;
11891 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11894 /* check if mtu is within the allowed range */
11895 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11898 /* mtu setting is forbidden if port is start */
11899 if (dev_data->dev_started) {
11900 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11901 dev_data->port_id);
11905 if (frame_size > ETHER_MAX_LEN)
11906 dev_data->dev_conf.rxmode.offloads |=
11907 DEV_RX_OFFLOAD_JUMBO_FRAME;
11909 dev_data->dev_conf.rxmode.offloads &=
11910 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11912 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11917 /* Restore ethertype filter */
11919 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11921 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11922 struct i40e_ethertype_filter_list
11923 *ethertype_list = &pf->ethertype.ethertype_list;
11924 struct i40e_ethertype_filter *f;
11925 struct i40e_control_filter_stats stats;
11928 TAILQ_FOREACH(f, ethertype_list, rules) {
11930 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11931 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11932 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11933 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11934 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11936 memset(&stats, 0, sizeof(stats));
11937 i40e_aq_add_rem_control_packet_filter(hw,
11938 f->input.mac_addr.addr_bytes,
11939 f->input.ether_type,
11940 flags, pf->main_vsi->seid,
11941 f->queue, 1, &stats, NULL);
11943 PMD_DRV_LOG(INFO, "Ethertype filter:"
11944 " mac_etype_used = %u, etype_used = %u,"
11945 " mac_etype_free = %u, etype_free = %u",
11946 stats.mac_etype_used, stats.etype_used,
11947 stats.mac_etype_free, stats.etype_free);
11950 /* Restore tunnel filter */
11952 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11954 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11955 struct i40e_vsi *vsi;
11956 struct i40e_pf_vf *vf;
11957 struct i40e_tunnel_filter_list
11958 *tunnel_list = &pf->tunnel.tunnel_list;
11959 struct i40e_tunnel_filter *f;
11960 struct i40e_aqc_cloud_filters_element_bb cld_filter;
11961 bool big_buffer = 0;
11963 TAILQ_FOREACH(f, tunnel_list, rules) {
11965 vsi = pf->main_vsi;
11967 vf = &pf->vfs[f->vf_id];
11970 memset(&cld_filter, 0, sizeof(cld_filter));
11971 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11972 (struct ether_addr *)&cld_filter.element.outer_mac);
11973 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11974 (struct ether_addr *)&cld_filter.element.inner_mac);
11975 cld_filter.element.inner_vlan = f->input.inner_vlan;
11976 cld_filter.element.flags = f->input.flags;
11977 cld_filter.element.tenant_id = f->input.tenant_id;
11978 cld_filter.element.queue_number = f->queue;
11979 rte_memcpy(cld_filter.general_fields,
11980 f->input.general_fields,
11981 sizeof(f->input.general_fields));
11983 if (((f->input.flags &
11984 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11985 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11987 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11988 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11990 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11991 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11995 i40e_aq_add_cloud_filters_bb(hw,
11996 vsi->seid, &cld_filter, 1);
11998 i40e_aq_add_cloud_filters(hw, vsi->seid,
11999 &cld_filter.element, 1);
12003 /* Restore rss filter */
12005 i40e_rss_filter_restore(struct i40e_pf *pf)
12007 struct i40e_rte_flow_rss_conf *conf =
12009 if (conf->conf.queue_num)
12010 i40e_config_rss_filter(pf, conf, TRUE);
12014 i40e_filter_restore(struct i40e_pf *pf)
12016 i40e_ethertype_filter_restore(pf);
12017 i40e_tunnel_filter_restore(pf);
12018 i40e_fdir_filter_restore(pf);
12019 i40e_rss_filter_restore(pf);
12023 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12025 if (strcmp(dev->device->driver->name, drv->driver.name))
12032 is_i40e_supported(struct rte_eth_dev *dev)
12034 return is_device_supported(dev, &rte_i40e_pmd);
12037 struct i40e_customized_pctype*
12038 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12042 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12043 if (pf->customized_pctype[i].index == index)
12044 return &pf->customized_pctype[i];
12050 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12051 uint32_t pkg_size, uint32_t proto_num,
12052 struct rte_pmd_i40e_proto_info *proto,
12053 enum rte_pmd_i40e_package_op op)
12055 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12056 uint32_t pctype_num;
12057 struct rte_pmd_i40e_ptype_info *pctype;
12058 uint32_t buff_size;
12059 struct i40e_customized_pctype *new_pctype = NULL;
12061 uint8_t pctype_value;
12066 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12067 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12068 PMD_DRV_LOG(ERR, "Unsupported operation.");
12072 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12073 (uint8_t *)&pctype_num, sizeof(pctype_num),
12074 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12076 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12080 PMD_DRV_LOG(INFO, "No new pctype added");
12084 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12085 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12087 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12090 /* get information about new pctype list */
12091 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12092 (uint8_t *)pctype, buff_size,
12093 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12095 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12100 /* Update customized pctype. */
12101 for (i = 0; i < pctype_num; i++) {
12102 pctype_value = pctype[i].ptype_id;
12103 memset(name, 0, sizeof(name));
12104 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12105 proto_id = pctype[i].protocols[j];
12106 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12108 for (n = 0; n < proto_num; n++) {
12109 if (proto[n].proto_id != proto_id)
12111 strcat(name, proto[n].name);
12116 name[strlen(name) - 1] = '\0';
12117 if (!strcmp(name, "GTPC"))
12119 i40e_find_customized_pctype(pf,
12120 I40E_CUSTOMIZED_GTPC);
12121 else if (!strcmp(name, "GTPU_IPV4"))
12123 i40e_find_customized_pctype(pf,
12124 I40E_CUSTOMIZED_GTPU_IPV4);
12125 else if (!strcmp(name, "GTPU_IPV6"))
12127 i40e_find_customized_pctype(pf,
12128 I40E_CUSTOMIZED_GTPU_IPV6);
12129 else if (!strcmp(name, "GTPU"))
12131 i40e_find_customized_pctype(pf,
12132 I40E_CUSTOMIZED_GTPU);
12134 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12135 new_pctype->pctype = pctype_value;
12136 new_pctype->valid = true;
12138 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12139 new_pctype->valid = false;
12149 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12150 uint32_t pkg_size, uint32_t proto_num,
12151 struct rte_pmd_i40e_proto_info *proto,
12152 enum rte_pmd_i40e_package_op op)
12154 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12155 uint16_t port_id = dev->data->port_id;
12156 uint32_t ptype_num;
12157 struct rte_pmd_i40e_ptype_info *ptype;
12158 uint32_t buff_size;
12160 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12165 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12166 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12167 PMD_DRV_LOG(ERR, "Unsupported operation.");
12171 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12172 rte_pmd_i40e_ptype_mapping_reset(port_id);
12176 /* get information about new ptype num */
12177 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12178 (uint8_t *)&ptype_num, sizeof(ptype_num),
12179 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12181 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12185 PMD_DRV_LOG(INFO, "No new ptype added");
12189 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12190 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12192 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12196 /* get information about new ptype list */
12197 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12198 (uint8_t *)ptype, buff_size,
12199 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12201 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12206 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12207 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12208 if (!ptype_mapping) {
12209 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12214 /* Update ptype mapping table. */
12215 for (i = 0; i < ptype_num; i++) {
12216 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12217 ptype_mapping[i].sw_ptype = 0;
12219 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12220 proto_id = ptype[i].protocols[j];
12221 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12223 for (n = 0; n < proto_num; n++) {
12224 if (proto[n].proto_id != proto_id)
12226 memset(name, 0, sizeof(name));
12227 strcpy(name, proto[n].name);
12228 if (!strncasecmp(name, "PPPOE", 5))
12229 ptype_mapping[i].sw_ptype |=
12230 RTE_PTYPE_L2_ETHER_PPPOE;
12231 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12233 ptype_mapping[i].sw_ptype |=
12234 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12235 ptype_mapping[i].sw_ptype |=
12237 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12239 ptype_mapping[i].sw_ptype |=
12240 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12241 ptype_mapping[i].sw_ptype |=
12242 RTE_PTYPE_INNER_L4_FRAG;
12243 } else if (!strncasecmp(name, "OIPV4", 5)) {
12244 ptype_mapping[i].sw_ptype |=
12245 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12247 } else if (!strncasecmp(name, "IPV4", 4) &&
12249 ptype_mapping[i].sw_ptype |=
12250 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12251 else if (!strncasecmp(name, "IPV4", 4) &&
12253 ptype_mapping[i].sw_ptype |=
12254 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12255 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12257 ptype_mapping[i].sw_ptype |=
12258 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12259 ptype_mapping[i].sw_ptype |=
12261 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12263 ptype_mapping[i].sw_ptype |=
12264 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12265 ptype_mapping[i].sw_ptype |=
12266 RTE_PTYPE_INNER_L4_FRAG;
12267 } else if (!strncasecmp(name, "OIPV6", 5)) {
12268 ptype_mapping[i].sw_ptype |=
12269 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12271 } else if (!strncasecmp(name, "IPV6", 4) &&
12273 ptype_mapping[i].sw_ptype |=
12274 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12275 else if (!strncasecmp(name, "IPV6", 4) &&
12277 ptype_mapping[i].sw_ptype |=
12278 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12279 else if (!strncasecmp(name, "UDP", 3) &&
12281 ptype_mapping[i].sw_ptype |=
12283 else if (!strncasecmp(name, "UDP", 3) &&
12285 ptype_mapping[i].sw_ptype |=
12286 RTE_PTYPE_INNER_L4_UDP;
12287 else if (!strncasecmp(name, "TCP", 3) &&
12289 ptype_mapping[i].sw_ptype |=
12291 else if (!strncasecmp(name, "TCP", 3) &&
12293 ptype_mapping[i].sw_ptype |=
12294 RTE_PTYPE_INNER_L4_TCP;
12295 else if (!strncasecmp(name, "SCTP", 4) &&
12297 ptype_mapping[i].sw_ptype |=
12299 else if (!strncasecmp(name, "SCTP", 4) &&
12301 ptype_mapping[i].sw_ptype |=
12302 RTE_PTYPE_INNER_L4_SCTP;
12303 else if ((!strncasecmp(name, "ICMP", 4) ||
12304 !strncasecmp(name, "ICMPV6", 6)) &&
12306 ptype_mapping[i].sw_ptype |=
12308 else if ((!strncasecmp(name, "ICMP", 4) ||
12309 !strncasecmp(name, "ICMPV6", 6)) &&
12311 ptype_mapping[i].sw_ptype |=
12312 RTE_PTYPE_INNER_L4_ICMP;
12313 else if (!strncasecmp(name, "GTPC", 4)) {
12314 ptype_mapping[i].sw_ptype |=
12315 RTE_PTYPE_TUNNEL_GTPC;
12317 } else if (!strncasecmp(name, "GTPU", 4)) {
12318 ptype_mapping[i].sw_ptype |=
12319 RTE_PTYPE_TUNNEL_GTPU;
12321 } else if (!strncasecmp(name, "GRENAT", 6)) {
12322 ptype_mapping[i].sw_ptype |=
12323 RTE_PTYPE_TUNNEL_GRENAT;
12325 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12326 !strncasecmp(name, "L2TPV2", 6)) {
12327 ptype_mapping[i].sw_ptype |=
12328 RTE_PTYPE_TUNNEL_L2TP;
12337 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12340 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12342 rte_free(ptype_mapping);
12348 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12349 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12351 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12352 uint32_t proto_num;
12353 struct rte_pmd_i40e_proto_info *proto;
12354 uint32_t buff_size;
12358 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12359 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12360 PMD_DRV_LOG(ERR, "Unsupported operation.");
12364 /* get information about protocol number */
12365 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12366 (uint8_t *)&proto_num, sizeof(proto_num),
12367 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12369 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12373 PMD_DRV_LOG(INFO, "No new protocol added");
12377 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12378 proto = rte_zmalloc("new_proto", buff_size, 0);
12380 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12384 /* get information about protocol list */
12385 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12386 (uint8_t *)proto, buff_size,
12387 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12389 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12394 /* Check if GTP is supported. */
12395 for (i = 0; i < proto_num; i++) {
12396 if (!strncmp(proto[i].name, "GTP", 3)) {
12397 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12398 pf->gtp_support = true;
12400 pf->gtp_support = false;
12405 /* Update customized pctype info */
12406 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12407 proto_num, proto, op);
12409 PMD_DRV_LOG(INFO, "No pctype is updated.");
12411 /* Update customized ptype info */
12412 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12413 proto_num, proto, op);
12415 PMD_DRV_LOG(INFO, "No ptype is updated.");
12420 /* Create a QinQ cloud filter
12422 * The Fortville NIC has limited resources for tunnel filters,
12423 * so we can only reuse existing filters.
12425 * In step 1 we define which Field Vector fields can be used for
12427 * As we do not have the inner tag defined as a field,
12428 * we have to define it first, by reusing one of L1 entries.
12430 * In step 2 we are replacing one of existing filter types with
12431 * a new one for QinQ.
12432 * As we reusing L1 and replacing L2, some of the default filter
12433 * types will disappear,which depends on L1 and L2 entries we reuse.
12435 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12437 * 1. Create L1 filter of outer vlan (12b) which will be in use
12438 * later when we define the cloud filter.
12439 * a. Valid_flags.replace_cloud = 0
12440 * b. Old_filter = 10 (Stag_Inner_Vlan)
12441 * c. New_filter = 0x10
12442 * d. TR bit = 0xff (optional, not used here)
12443 * e. Buffer – 2 entries:
12444 * i. Byte 0 = 8 (outer vlan FV index).
12446 * Byte 2-3 = 0x0fff
12447 * ii. Byte 0 = 37 (inner vlan FV index).
12449 * Byte 2-3 = 0x0fff
12452 * 2. Create cloud filter using two L1 filters entries: stag and
12453 * new filter(outer vlan+ inner vlan)
12454 * a. Valid_flags.replace_cloud = 1
12455 * b. Old_filter = 1 (instead of outer IP)
12456 * c. New_filter = 0x10
12457 * d. Buffer – 2 entries:
12458 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12459 * Byte 1-3 = 0 (rsv)
12460 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12461 * Byte 9-11 = 0 (rsv)
12464 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12466 int ret = -ENOTSUP;
12467 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12468 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12469 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12470 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12472 if (pf->support_multi_driver) {
12473 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12478 memset(&filter_replace, 0,
12479 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12480 memset(&filter_replace_buf, 0,
12481 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12483 /* create L1 filter */
12484 filter_replace.old_filter_type =
12485 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12486 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12487 filter_replace.tr_bit = 0;
12489 /* Prepare the buffer, 2 entries */
12490 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12491 filter_replace_buf.data[0] |=
12492 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12493 /* Field Vector 12b mask */
12494 filter_replace_buf.data[2] = 0xff;
12495 filter_replace_buf.data[3] = 0x0f;
12496 filter_replace_buf.data[4] =
12497 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12498 filter_replace_buf.data[4] |=
12499 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12500 /* Field Vector 12b mask */
12501 filter_replace_buf.data[6] = 0xff;
12502 filter_replace_buf.data[7] = 0x0f;
12503 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12504 &filter_replace_buf);
12505 if (ret != I40E_SUCCESS)
12508 if (filter_replace.old_filter_type !=
12509 filter_replace.new_filter_type)
12510 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12511 " original: 0x%x, new: 0x%x",
12513 filter_replace.old_filter_type,
12514 filter_replace.new_filter_type);
12516 /* Apply the second L2 cloud filter */
12517 memset(&filter_replace, 0,
12518 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12519 memset(&filter_replace_buf, 0,
12520 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12522 /* create L2 filter, input for L2 filter will be L1 filter */
12523 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12524 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12525 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12527 /* Prepare the buffer, 2 entries */
12528 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12529 filter_replace_buf.data[0] |=
12530 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12531 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12532 filter_replace_buf.data[4] |=
12533 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12534 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12535 &filter_replace_buf);
12536 if (!ret && (filter_replace.old_filter_type !=
12537 filter_replace.new_filter_type))
12538 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12539 " original: 0x%x, new: 0x%x",
12541 filter_replace.old_filter_type,
12542 filter_replace.new_filter_type);
12548 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12549 const struct rte_flow_action_rss *in)
12551 if (in->key_len > RTE_DIM(out->key) ||
12552 in->queue_num > RTE_DIM(out->queue))
12554 out->conf = (struct rte_flow_action_rss){
12556 .level = in->level,
12557 .types = in->types,
12558 .key_len = in->key_len,
12559 .queue_num = in->queue_num,
12560 .key = memcpy(out->key, in->key, in->key_len),
12561 .queue = memcpy(out->queue, in->queue,
12562 sizeof(*in->queue) * in->queue_num),
12568 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12569 const struct rte_flow_action_rss *with)
12571 return (comp->func == with->func &&
12572 comp->level == with->level &&
12573 comp->types == with->types &&
12574 comp->key_len == with->key_len &&
12575 comp->queue_num == with->queue_num &&
12576 !memcmp(comp->key, with->key, with->key_len) &&
12577 !memcmp(comp->queue, with->queue,
12578 sizeof(*with->queue) * with->queue_num));
12582 i40e_config_rss_filter(struct i40e_pf *pf,
12583 struct i40e_rte_flow_rss_conf *conf, bool add)
12585 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12586 uint32_t i, lut = 0;
12588 struct rte_eth_rss_conf rss_conf = {
12589 .rss_key = conf->conf.key_len ?
12590 (void *)(uintptr_t)conf->conf.key : NULL,
12591 .rss_key_len = conf->conf.key_len,
12592 .rss_hf = conf->conf.types,
12594 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12597 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12598 i40e_pf_disable_rss(pf);
12599 memset(rss_info, 0,
12600 sizeof(struct i40e_rte_flow_rss_conf));
12606 if (rss_info->conf.queue_num)
12609 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12610 * It's necessary to calculate the actual PF queues that are configured.
12612 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12613 num = i40e_pf_calc_configured_queues_num(pf);
12615 num = pf->dev_data->nb_rx_queues;
12617 num = RTE_MIN(num, conf->conf.queue_num);
12618 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12622 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12626 /* Fill in redirection table */
12627 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12630 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12631 hw->func_caps.rss_table_entry_width) - 1));
12633 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12636 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12637 i40e_pf_disable_rss(pf);
12640 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12641 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12642 /* Random default keys */
12643 static uint32_t rss_key_default[] = {0x6b793944,
12644 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12645 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12646 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12648 rss_conf.rss_key = (uint8_t *)rss_key_default;
12649 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12653 i40e_hw_rss_hash_set(pf, &rss_conf);
12655 if (i40e_rss_conf_init(rss_info, &conf->conf))
12661 RTE_INIT(i40e_init_log)
12663 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12664 if (i40e_logtype_init >= 0)
12665 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12666 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12667 if (i40e_logtype_driver >= 0)
12668 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12671 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12672 ETH_I40E_FLOATING_VEB_ARG "=1"
12673 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12674 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12675 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12676 ETH_I40E_USE_LATEST_VEC "=0|1");