1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
5 #ifndef _I40E_ETHDEV_H_
6 #define _I40E_ETHDEV_H_
11 #include <rte_kvargs.h>
14 #include <rte_flow_driver.h>
15 #include <rte_tm_driver.h>
16 #include "rte_pmd_i40e.h"
18 #include "base/i40e_register.h"
20 #define I40E_VLAN_TAG_SIZE 4
22 #define I40E_AQ_LEN 32
23 #define I40E_AQ_BUF_SZ 4096
24 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
25 #define I40E_MAX_Q_PER_TC 64
26 #define I40E_NUM_DESC_DEFAULT 512
27 #define I40E_NUM_DESC_ALIGN 32
28 #define I40E_BUF_SIZE_MIN 1024
29 #define I40E_FRAME_SIZE_MAX 9728
30 #define I40E_TSO_FRAME_SIZE_MAX 262144
31 #define I40E_QUEUE_BASE_ADDR_UNIT 128
32 /* number of VSIs and queue default setting */
33 #define I40E_MAX_QP_NUM_PER_VF 16
34 #define I40E_DEFAULT_QP_NUM_FDIR 1
35 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
36 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
37 /* Maximun number of MAC addresses */
38 #define I40E_NUM_MACADDR_MAX 64
39 /* Maximum number of VFs */
40 #define I40E_MAX_VF 128
41 /*flag of no loopback*/
42 #define I40E_AQ_LB_MODE_NONE 0x0
44 * vlan_id is a 12 bit number.
45 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
46 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
47 * The higher 7 bit val specifies VFTA array index.
49 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
50 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
52 /* Default TC traffic in case DCB is not enabled */
53 #define I40E_DEFAULT_TCMAP 0x1
54 #define I40E_FDIR_QUEUE_ID 0
56 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
57 #define I40E_VMDQ_POOL_BASE 1
59 #define I40E_DEFAULT_RX_FREE_THRESH 32
60 #define I40E_DEFAULT_RX_PTHRESH 8
61 #define I40E_DEFAULT_RX_HTHRESH 8
62 #define I40E_DEFAULT_RX_WTHRESH 0
64 #define I40E_DEFAULT_TX_FREE_THRESH 32
65 #define I40E_DEFAULT_TX_PTHRESH 32
66 #define I40E_DEFAULT_TX_HTHRESH 0
67 #define I40E_DEFAULT_TX_WTHRESH 0
68 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
70 /* Bit shift and mask */
71 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
72 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
73 #define I40E_8_BIT_WIDTH CHAR_BIT
74 #define I40E_8_BIT_MASK UINT8_MAX
75 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
76 #define I40E_16_BIT_MASK UINT16_MAX
77 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
78 #define I40E_32_BIT_MASK UINT32_MAX
79 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
80 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
82 /* Linux PF host with virtchnl version 1.1 */
83 #define PF_IS_V11(vf) \
84 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
85 ((vf)->version_minor == 1))
87 #define I40E_WRITE_GLB_REG(hw, reg, value) \
90 struct rte_eth_dev *dev; \
91 ori_val = I40E_READ_REG((hw), (reg)); \
92 dev = ((struct i40e_adapter *)hw->back)->eth_dev; \
93 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \
95 if (ori_val != value) \
96 PMD_DRV_LOG(WARNING, \
97 "i40e device %s changed global " \
98 "register [0x%08x]. original: 0x%08x, " \
100 (dev->device->name), (reg), \
101 (ori_val), (value)); \
104 /* index flex payload per layer */
105 enum i40e_flxpld_layer_idx {
106 I40E_FLXPLD_L2_IDX = 0,
107 I40E_FLXPLD_L3_IDX = 1,
108 I40E_FLXPLD_L4_IDX = 2,
109 I40E_MAX_FLXPLD_LAYER = 3,
111 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
112 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
113 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
114 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
115 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
118 #define I40E_FLAG_RSS (1ULL << 0)
119 #define I40E_FLAG_DCB (1ULL << 1)
120 #define I40E_FLAG_VMDQ (1ULL << 2)
121 #define I40E_FLAG_SRIOV (1ULL << 3)
122 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
123 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
124 #define I40E_FLAG_FDIR (1ULL << 6)
125 #define I40E_FLAG_VXLAN (1ULL << 7)
126 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
127 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
128 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
132 I40E_FLAG_HEADER_SPLIT_DISABLED | \
133 I40E_FLAG_HEADER_SPLIT_ENABLED | \
136 I40E_FLAG_RSS_AQ_CAPABLE | \
137 I40E_FLAG_VF_MAC_BY_PF)
139 #define I40E_RSS_OFFLOAD_ALL ( \
140 ETH_RSS_FRAG_IPV4 | \
141 ETH_RSS_NONFRAG_IPV4_TCP | \
142 ETH_RSS_NONFRAG_IPV4_UDP | \
143 ETH_RSS_NONFRAG_IPV4_SCTP | \
144 ETH_RSS_NONFRAG_IPV4_OTHER | \
145 ETH_RSS_FRAG_IPV6 | \
146 ETH_RSS_NONFRAG_IPV6_TCP | \
147 ETH_RSS_NONFRAG_IPV6_UDP | \
148 ETH_RSS_NONFRAG_IPV6_SCTP | \
149 ETH_RSS_NONFRAG_IPV6_OTHER | \
152 /* All bits of RSS hash enable for X722*/
153 #define I40E_RSS_HENA_ALL_X722 ( \
154 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
155 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
156 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
157 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
158 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
159 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
162 /* All bits of RSS hash enable */
163 #define I40E_RSS_HENA_ALL ( \
164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
165 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
166 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
168 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
173 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
174 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
175 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
176 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
177 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
179 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
180 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
182 /* Default queue interrupt throttling time in microseconds */
183 #define I40E_ITR_INDEX_DEFAULT 0
184 #define I40E_ITR_INDEX_NONE 3
185 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
186 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
187 #define I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
188 /* Special FW support this floating VEB feature */
189 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
190 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
192 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
193 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
194 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
195 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
197 #define I40E_INSET_NONE 0x00000000000000000ULL
200 #define I40E_INSET_DMAC 0x0000000000000001ULL
201 #define I40E_INSET_SMAC 0x0000000000000002ULL
202 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
203 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
204 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
207 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
208 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
209 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
210 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
211 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
212 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
213 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
215 /* bit 16 ~ bit 31 */
216 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
217 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
218 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
219 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
220 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
221 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
222 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
223 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
225 /* bit 32 ~ bit 47, tunnel fields */
226 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
227 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
228 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
229 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
230 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
231 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
233 /* bit 48 ~ bit 55 */
234 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
236 /* bit 56 ~ bit 63, Flex Payload */
237 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
238 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
239 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
240 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
241 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
242 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
243 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
244 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
245 #define I40E_INSET_FLEX_PAYLOAD \
246 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
247 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
248 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
249 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
251 /* The max bandwidth of i40e is 40Gbps. */
252 #define I40E_QOS_BW_MAX 40000
253 /* The bandwidth should be the multiple of 50Mbps. */
254 #define I40E_QOS_BW_GRANULARITY 50
255 /* The min bandwidth weight is 1. */
256 #define I40E_QOS_BW_WEIGHT_MIN 1
257 /* The max bandwidth weight is 127. */
258 #define I40E_QOS_BW_WEIGHT_MAX 127
259 /* The max queue region index is 7. */
260 #define I40E_REGION_MAX_INDEX 7
262 #define I40E_MAX_PERCENT 100
263 #define I40E_DEFAULT_DCB_APP_NUM 1
264 #define I40E_DEFAULT_DCB_APP_PRIO 3
267 * The overhead from MTU to max frame size.
268 * Considering QinQ packet, the VLAN tag needs to be counted twice.
270 #define I40E_ETH_OVERHEAD \
271 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
274 struct rte_pci_driver;
277 * MAC filter structure
279 struct i40e_mac_filter_info {
280 enum rte_mac_filter_type filter_type;
281 struct rte_ether_addr mac_addr;
284 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
286 /* MAC filter list structure */
287 struct i40e_mac_filter {
288 TAILQ_ENTRY(i40e_mac_filter) next;
289 struct i40e_mac_filter_info mac_info;
292 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
296 /* VSI list structure */
297 struct i40e_vsi_list {
298 TAILQ_ENTRY(i40e_vsi_list) list;
299 struct i40e_vsi *vsi;
302 struct i40e_rx_queue;
303 struct i40e_tx_queue;
305 /* Bandwidth limit information */
306 struct i40e_bw_info {
307 uint16_t bw_limit; /* BW Limit (0 = disabled) */
308 uint8_t bw_max; /* Max BW limit if enabled */
310 /* Relative credits within same TC with respect to other VSIs or Comps */
311 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
312 /* Bandwidth limit per TC */
313 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
314 /* Max bandwidth limit per TC */
315 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
318 /* Structure that defines a VEB */
320 struct i40e_vsi_list_head head;
321 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
322 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
323 uint16_t seid; /* The seid of VEB itself */
324 uint16_t uplink_seid; /* The uplink seid of this VEB */
326 struct i40e_eth_stats stats;
327 uint8_t enabled_tc; /* The traffic class enabled */
328 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
329 struct i40e_bw_info bw_info; /* VEB bandwidth information */
332 /* i40e MACVLAN filter structure */
333 struct i40e_macvlan_filter {
334 struct rte_ether_addr macaddr;
335 enum rte_mac_filter_type filter_type;
340 * Structure that defines a VSI, associated with a adapter.
343 struct i40e_adapter *adapter; /* Backreference to associated adapter */
344 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
346 struct i40e_eth_stats eth_stats_offset;
347 struct i40e_eth_stats eth_stats;
349 * When drivers loaded, only a default main VSI exists. In case new VSI
350 * needs to add, HW needs to know the layout that VSIs are organized.
351 * Besides that, VSI isan element and can't switch packets, which needs
352 * to add new component VEB to perform switching. So, a new VSI needs
353 * to specify the uplink VSI (Parent VSI) before created. The
354 * uplink VSI will check whether it had a VEB to switch packets. If no,
355 * it will try to create one. Then, uplink VSI will move the new VSI
356 * into its' sib_vsi_list to manage all the downlink VSI.
357 * sib_vsi_list: the VSI list that shared the same uplink VSI.
358 * parent_vsi : the uplink VSI. It's NULL for main VSI.
359 * veb : the VEB associates with the VSI.
361 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
362 struct i40e_vsi *parent_vsi;
363 struct i40e_veb *veb; /* Associated veb, could be null */
364 struct i40e_veb *floating_veb; /* Associated floating veb */
366 enum i40e_vsi_type type; /* VSI types */
367 uint16_t vlan_num; /* Total VLAN number */
368 uint16_t mac_num; /* Total mac number */
369 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
370 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
371 /* specific VSI-defined parameters, SRIOV stored the vf_id */
373 uint16_t seid; /* The seid of VSI itself */
374 uint16_t uplink_seid; /* The uplink seid of this VSI */
375 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
376 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
377 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
378 uint16_t base_queue; /* The first queue index of this VSI */
380 * The offset to visit VSI related register, assigned by HW when
384 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
385 uint16_t nb_msix; /* The max number of msix vector */
386 uint8_t enabled_tc; /* The traffic class enabled */
387 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
388 uint8_t vlan_filter_on; /* The VLAN filter enabled */
389 struct i40e_bw_info bw_info; /* VSI bandwidth information */
393 LIST_ENTRY(pool_entry) next;
398 LIST_HEAD(res_list, pool_entry);
400 struct i40e_res_pool_info {
401 uint32_t base; /* Resource start index */
402 uint32_t num_alloc; /* Allocated resource number */
403 uint32_t num_free; /* Total available resource number */
404 struct res_list alloc_list; /* Allocated resource list */
405 struct res_list free_list; /* Available resource list */
409 I40E_VF_INACTIVE = 0,
416 * Structure to store private data for PF host.
420 struct i40e_vsi *vsi;
421 enum I40E_VF_STATE state; /* The number of queue pairs available */
422 uint16_t vf_idx; /* VF index in pf->vfs */
423 uint16_t lan_nb_qps; /* Actual queues allocated */
424 uint16_t reset_cnt; /* Total vf reset times */
425 struct rte_ether_addr mac_addr; /* Default MAC address */
426 /* version of the virtchnl from VF */
427 struct virtchnl_version_info version;
428 uint32_t request_caps; /* offload caps requested from VF */
431 * Variables for store the arrival timestamp of VF messages.
432 * If the timestamp of latest message stored at
433 * `msg_timestamps[index % max]` then the timestamp of
434 * earliest message stored at `msg_time[(index + 1) % max]`.
435 * When a new message come, the timestamp of this message
436 * will be stored at `msg_timestamps[(index + 1) % max]` and the
437 * earliest message timestamp is at
438 * `msg_timestamps[(index + 2) % max]` now...
441 uint64_t *msg_timestamps;
443 /* cycle of stop ignoring VF message */
444 uint64_t ignore_end_cycle;
448 * Structure to store private data for flow control.
450 struct i40e_fc_conf {
451 uint16_t pause_time; /* Flow control pause timer */
452 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
453 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
454 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
455 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
459 * Structure to store private data for VMDQ instance
461 struct i40e_vmdq_info {
463 struct i40e_vsi *vsi;
466 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
467 #define I40E_MAX_FLX_SOURCE_OFF 480
468 #define NONUSE_FLX_PIT_DEST_OFF 63
469 #define NONUSE_FLX_PIT_FSIZE 1
470 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
471 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
472 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
473 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
474 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
475 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
476 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
477 NONUSE_FLX_PIT_DEST_OFF : \
478 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
479 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
480 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
481 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
482 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
483 #define I40E_FDIR_IPv6_TC_OFFSET 20
485 /* A structure used to define the input for GTP flow */
486 struct i40e_gtp_flow {
487 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
488 uint8_t msg_type; /* Message type. */
489 uint32_t teid; /* TEID in big endian. */
492 /* A structure used to define the input for GTP IPV4 flow */
493 struct i40e_gtp_ipv4_flow {
494 struct i40e_gtp_flow gtp;
495 struct rte_eth_ipv4_flow ip4;
498 /* A structure used to define the input for GTP IPV6 flow */
499 struct i40e_gtp_ipv6_flow {
500 struct i40e_gtp_flow gtp;
501 struct rte_eth_ipv6_flow ip6;
504 /* A structure used to define the input for raw type flow */
505 struct i40e_raw_flow {
511 /* A structure used to define the input for L2TPv3 over IPv4 flow */
512 struct i40e_ipv4_l2tpv3oip_flow {
513 struct rte_eth_ipv4_flow ip4;
514 uint32_t session_id; /* Session ID in big endian. */
517 /* A structure used to define the input for L2TPv3 over IPv6 flow */
518 struct i40e_ipv6_l2tpv3oip_flow {
519 struct rte_eth_ipv6_flow ip6;
520 uint32_t session_id; /* Session ID in big endian. */
524 * A union contains the inputs for all types of flow
525 * items in flows need to be in big endian
527 union i40e_fdir_flow {
528 struct rte_eth_l2_flow l2_flow;
529 struct rte_eth_udpv4_flow udp4_flow;
530 struct rte_eth_tcpv4_flow tcp4_flow;
531 struct rte_eth_sctpv4_flow sctp4_flow;
532 struct rte_eth_ipv4_flow ip4_flow;
533 struct rte_eth_udpv6_flow udp6_flow;
534 struct rte_eth_tcpv6_flow tcp6_flow;
535 struct rte_eth_sctpv6_flow sctp6_flow;
536 struct rte_eth_ipv6_flow ipv6_flow;
537 struct i40e_gtp_flow gtp_flow;
538 struct i40e_gtp_ipv4_flow gtp_ipv4_flow;
539 struct i40e_gtp_ipv6_flow gtp_ipv6_flow;
540 struct i40e_raw_flow raw_flow;
541 struct i40e_ipv4_l2tpv3oip_flow ip4_l2tpv3oip_flow;
542 struct i40e_ipv6_l2tpv3oip_flow ip6_l2tpv3oip_flow;
545 enum i40e_fdir_ip_type {
546 I40E_FDIR_IPTYPE_IPV4,
547 I40E_FDIR_IPTYPE_IPV6,
550 /* A structure used to contain extend input of flow */
551 struct i40e_fdir_flow_ext {
553 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
554 /* It is filled by the flexible payload to match. */
555 uint8_t is_vf; /* 1 for VF, 0 for port dev */
556 uint16_t dst_id; /* VF ID, available when is_vf is 1*/
557 bool inner_ip; /* If there is inner ip */
558 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
559 enum i40e_fdir_ip_type oip_type; /* ip type for outer ip */
560 bool customized_pctype; /* If customized pctype is used */
561 bool pkt_template; /* If raw packet template is used */
564 /* A structure used to define the input for a flow director filter entry */
565 struct i40e_fdir_input {
566 enum i40e_filter_pctype pctype;
567 union i40e_fdir_flow flow;
568 /* Flow fields to match, dependent on flow_type */
569 struct i40e_fdir_flow_ext flow_ext;
570 /* Additional fields to match */
573 /* Behavior will be taken if FDIR match */
574 enum i40e_fdir_behavior {
575 I40E_FDIR_ACCEPT = 0,
580 /* Flow director report status
581 * It defines what will be reported if FDIR entry is matched.
583 enum i40e_fdir_status {
584 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */
585 I40E_FDIR_REPORT_ID, /* Only report FD ID. */
586 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */
587 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */
590 /* A structure used to define an action when match FDIR packet filter. */
591 struct i40e_fdir_action {
592 uint16_t rx_queue; /* Queue assigned to if FDIR match. */
593 enum i40e_fdir_behavior behavior; /* Behavior will be taken */
594 enum i40e_fdir_status report_status; /* Status report option */
595 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or
596 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported
597 * flex bytes start from in flexible payload.
602 /* A structure used to define the flow director filter entry by filter_ctrl API
603 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and
604 * RTE_ETH_FILTER_DELETE operations.
606 struct i40e_fdir_filter_conf {
608 /* ID, an unique value is required when deal with FDIR entry */
609 struct i40e_fdir_input input; /* Input set */
610 struct i40e_fdir_action action; /* Action taken when match */
614 * Structure to store flex pit for flow diretor.
616 struct i40e_fdir_flex_pit {
617 uint8_t src_offset; /* offset in words from the beginning of payload */
618 uint8_t size; /* size in words */
619 uint8_t dst_offset; /* offset in words of flexible payload */
622 struct i40e_fdir_flex_mask {
623 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
628 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
631 #define I40E_FILTER_PCTYPE_INVALID 0
632 #define I40E_FILTER_PCTYPE_MAX 64
633 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
635 struct i40e_fdir_filter {
636 TAILQ_ENTRY(i40e_fdir_filter) rules;
637 struct i40e_fdir_filter_conf fdir;
640 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
642 * A structure used to define fields of a FDIR related info.
644 struct i40e_fdir_info {
645 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
646 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
647 struct i40e_tx_queue *txq;
648 struct i40e_rx_queue *rxq;
649 void *prg_pkt; /* memory for fdir program packet */
650 uint64_t dma_addr; /* physic address of packet memory*/
651 /* input set bits for each pctype */
652 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
654 * the rule how bytes stream is extracted as flexible payload
655 * for each payload layer, the setting can up to three elements
657 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
658 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
660 struct i40e_fdir_filter_list fdir_list;
661 struct i40e_fdir_filter **hash_map;
662 struct rte_hash *hash_table;
664 /* Mark if flex pit and mask is set */
665 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
666 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
668 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
671 /* Ethertype filter number HW supports */
672 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
674 /* Ethertype filter struct */
675 struct i40e_ethertype_filter_input {
676 struct rte_ether_addr mac_addr; /* Mac address to match */
677 uint16_t ether_type; /* Ether type to match */
680 struct i40e_ethertype_filter {
681 TAILQ_ENTRY(i40e_ethertype_filter) rules;
682 struct i40e_ethertype_filter_input input;
683 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
684 uint16_t queue; /* Queue assigned to when match */
687 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
689 struct i40e_ethertype_rule {
690 struct i40e_ethertype_filter_list ethertype_list;
691 struct i40e_ethertype_filter **hash_map;
692 struct rte_hash *hash_table;
695 /* queue region info */
696 struct i40e_queue_region_info {
697 /* the region id for this configuration */
699 /* the start queue index for this region */
700 uint8_t queue_start_index;
701 /* the total queue number of this queue region */
703 /* the total number of user priority for this region */
704 uint8_t user_priority_num;
705 /* the packet's user priority for this region */
706 uint8_t user_priority[I40E_MAX_USER_PRIORITY];
707 /* the total number of flowtype for this region */
708 uint8_t flowtype_num;
710 * the pctype or hardware flowtype of packet,
711 * the specific index for each type has been defined
712 * in file i40e_type.h as enum i40e_filter_pctype.
714 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];
717 struct i40e_queue_regions {
718 /* the total number of queue region for this port */
719 uint16_t queue_region_number;
720 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1];
723 /* Tunnel filter number HW supports */
724 #define I40E_MAX_TUNNEL_FILTER_NUM 400
726 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
727 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
728 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8
729 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9
730 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10
731 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11
732 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12
733 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11
734 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12
735 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13
736 #define I40E_AQC_NEW_TR_21 21
737 #define I40E_AQC_NEW_TR_22 22
739 enum i40e_tunnel_iptype {
740 I40E_TUNNEL_IPTYPE_IPV4,
741 I40E_TUNNEL_IPTYPE_IPV6,
744 /* Tunnel filter struct */
745 struct i40e_tunnel_filter_input {
746 uint8_t outer_mac[6]; /* Outer mac address to match */
747 uint8_t inner_mac[6]; /* Inner mac address to match */
748 uint16_t inner_vlan; /* Inner vlan address to match */
749 enum i40e_tunnel_iptype ip_type;
750 uint16_t flags; /* Filter type flag */
751 uint32_t tenant_id; /* Tenant id to match */
752 uint16_t general_fields[32]; /* Big buffer */
755 struct i40e_tunnel_filter {
756 TAILQ_ENTRY(i40e_tunnel_filter) rules;
757 struct i40e_tunnel_filter_input input;
758 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
759 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
760 uint16_t queue; /* Queue assigned to when match */
763 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
765 struct i40e_tunnel_rule {
766 struct i40e_tunnel_filter_list tunnel_list;
767 struct i40e_tunnel_filter **hash_map;
768 struct rte_hash *hash_table;
774 enum i40e_tunnel_type {
775 I40E_TUNNEL_TYPE_NONE = 0,
776 I40E_TUNNEL_TYPE_VXLAN,
777 I40E_TUNNEL_TYPE_GENEVE,
778 I40E_TUNNEL_TYPE_TEREDO,
779 I40E_TUNNEL_TYPE_NVGRE,
780 I40E_TUNNEL_TYPE_IP_IN_GRE,
781 I40E_L2_TUNNEL_TYPE_E_TAG,
782 I40E_TUNNEL_TYPE_MPLSoUDP,
783 I40E_TUNNEL_TYPE_MPLSoGRE,
784 I40E_TUNNEL_TYPE_QINQ,
785 I40E_TUNNEL_TYPE_GTPC,
786 I40E_TUNNEL_TYPE_GTPU,
787 I40E_TUNNEL_TYPE_MAX,
791 * Tunneling Packet filter configuration.
793 struct i40e_tunnel_filter_conf {
794 struct rte_ether_addr outer_mac; /**< Outer MAC address to match. */
795 struct rte_ether_addr inner_mac; /**< Inner MAC address to match. */
796 uint16_t inner_vlan; /**< Inner VLAN to match. */
797 uint32_t outer_vlan; /**< Outer VLAN to match */
798 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
800 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
801 * is set in filter_type, or inner destination IP address to match
802 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
805 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
806 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
808 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
809 uint16_t filter_type;
810 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
811 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
812 uint16_t queue_id; /**< Queue assigned to if match. */
813 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
814 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
817 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
818 #define I40E_MAX_MIRROR_RULES 64
820 * Mirror rule structure
822 struct i40e_mirror_rule {
823 TAILQ_ENTRY(i40e_mirror_rule) rules;
825 uint16_t index; /* the sw index of mirror rule */
826 uint16_t id; /* the rule id assigned by firmware */
827 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
828 uint16_t num_entries;
829 /* the info stores depend on the rule type.
830 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
831 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
833 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
836 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
839 * Struct to store flow created.
842 TAILQ_ENTRY(rte_flow) node;
843 enum rte_filter_type filter_type;
847 TAILQ_HEAD(i40e_flow_list, rte_flow);
849 /* Struct to store Traffic Manager shaper profile. */
850 struct i40e_tm_shaper_profile {
851 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
852 uint32_t shaper_profile_id;
853 uint32_t reference_count;
854 struct rte_tm_shaper_params profile;
857 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
859 /* node type of Traffic Manager */
860 enum i40e_tm_node_type {
861 I40E_TM_NODE_TYPE_PORT,
862 I40E_TM_NODE_TYPE_TC,
863 I40E_TM_NODE_TYPE_QUEUE,
864 I40E_TM_NODE_TYPE_MAX,
867 /* Struct to store Traffic Manager node configuration. */
868 struct i40e_tm_node {
869 TAILQ_ENTRY(i40e_tm_node) node;
873 uint32_t reference_count;
874 struct i40e_tm_node *parent;
875 struct i40e_tm_shaper_profile *shaper_profile;
876 struct rte_tm_node_params params;
879 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
881 /* Struct to store all the Traffic Manager configuration. */
882 struct i40e_tm_conf {
883 struct i40e_shaper_profile_list shaper_profile_list;
884 struct i40e_tm_node *root; /* root node - port */
885 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
886 struct i40e_tm_node_list queue_list; /* node list for all the queues */
888 * The number of added TC nodes.
889 * It should be no more than the TC number of this port.
893 * The number of added queue nodes.
894 * It should be no more than the queue number of this port.
896 uint32_t nb_queue_node;
898 * This flag is used to check if APP can change the TM node
900 * When it's true, means the configuration is applied to HW,
901 * APP should not change the configuration.
902 * As we don't support on-the-fly configuration, when starting
903 * the port, APP should call the hierarchy_commit API to set this
904 * flag to true. When stopping the port, this flag should be set
910 enum i40e_new_pctype {
911 I40E_CUSTOMIZED_GTPC = 0,
912 I40E_CUSTOMIZED_GTPU_IPV4,
913 I40E_CUSTOMIZED_GTPU_IPV6,
914 I40E_CUSTOMIZED_GTPU,
915 I40E_CUSTOMIZED_IPV4_L2TPV3,
916 I40E_CUSTOMIZED_IPV6_L2TPV3,
920 #define I40E_FILTER_PCTYPE_INVALID 0
921 struct i40e_customized_pctype {
922 enum i40e_new_pctype index; /* Indicate which customized pctype */
923 uint8_t pctype; /* New pctype value */
924 bool valid; /* Check if it's valid */
927 struct i40e_rte_flow_rss_conf {
928 struct rte_flow_action_rss conf; /**< RSS parameters. */
929 uint16_t queue_region_conf; /**< Queue region config flag */
930 uint8_t key[(I40E_VFQF_HKEY_MAX_INDEX > I40E_PFQF_HKEY_MAX_INDEX ?
931 I40E_VFQF_HKEY_MAX_INDEX : I40E_PFQF_HKEY_MAX_INDEX + 1) *
932 sizeof(uint32_t)]; /* Hash key. */
933 uint16_t queue[I40E_MAX_Q_PER_TC]; /**< Queues indices to use. */
936 struct i40e_vf_msg_cfg {
937 /* maximal VF message during a statistic period */
940 /* statistic period, in second */
943 * If message statistics from a VF exceed the maximal limitation,
944 * the PF will ignore any new message from that VF for
945 * 'ignor_second' time.
947 uint32_t ignore_second;
951 * Structure to store private data specific for PF instance.
954 struct i40e_adapter *adapter; /* The adapter this PF associate to */
955 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
956 uint16_t mac_seid; /* The seid of the MAC of this PF */
957 uint16_t main_vsi_seid; /* The seid of the main VSI */
958 uint16_t max_num_vsi;
959 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
960 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
962 struct i40e_hw_port_stats stats_offset;
963 struct i40e_hw_port_stats stats;
964 /* internal packet statistics, it should be excluded from the total */
965 struct i40e_eth_stats internal_stats_offset;
966 struct i40e_eth_stats internal_stats;
969 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
970 struct rte_ether_addr dev_addr; /* PF device mac address */
971 uint64_t flags; /* PF feature flags */
972 /* All kinds of queue pair setting for different VSIs */
973 struct i40e_pf_vf *vfs;
975 /* Each of below queue pairs should be power of 2 since it's the
976 precondition after TC configuration applied */
977 uint16_t lan_nb_qp_max;
978 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
979 uint16_t lan_qp_offset;
980 uint16_t vmdq_nb_qp_max;
981 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
982 uint16_t vmdq_qp_offset;
983 uint16_t vf_nb_qp_max;
984 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
985 uint16_t vf_qp_offset;
986 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
987 uint16_t fdir_qp_offset;
989 uint16_t hash_lut_size; /* The size of hash lookup table */
990 /* input set bits for each pctype */
991 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
992 /* store VXLAN UDP ports */
993 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
994 uint16_t vxlan_bitmap; /* Vxlan bit mask */
996 /* VMDQ related info */
997 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
998 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
999 struct i40e_vmdq_info *vmdq;
1001 struct i40e_fdir_info fdir; /* flow director info */
1002 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
1003 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
1004 struct i40e_rte_flow_rss_conf rss_info; /* rss info */
1005 struct i40e_queue_regions queue_region; /* queue region info */
1006 struct i40e_fc_conf fc_conf; /* Flow control conf */
1007 struct i40e_mirror_rule_list mirror_list;
1008 uint16_t nb_mirror_rule; /* The number of mirror rules */
1009 bool floating_veb; /* The flag to use the floating VEB */
1010 /* The floating enable flag for the specific VF */
1011 bool floating_veb_list[I40E_MAX_VF];
1012 struct i40e_flow_list flow_list;
1013 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
1014 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */
1015 bool qinq_replace_flag; /* QINQ filter replace is done */
1016 struct i40e_tm_conf tm_conf;
1017 bool support_multi_driver; /* 1 - support multiple driver */
1019 /* Dynamic Device Personalization */
1020 bool gtp_support; /* 1 - support GTP-C and GTP-U */
1021 /* customer customized pctype */
1022 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];
1023 /* Switch Domain Id */
1024 uint16_t switch_domain_id;
1026 struct i40e_vf_msg_cfg vf_msg_cfg;
1030 PFMSG_LINK_CHANGE = 0x1,
1031 PFMSG_RESET_IMPENDING = 0x2,
1032 PFMSG_DRIVER_CLOSE = 0x4,
1035 struct i40e_vsi_vlan_pvid_info {
1036 uint16_t on; /* Enable or disable pvid */
1038 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
1040 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
1041 * while 'untagged' will reject untagged packets.
1049 struct i40e_vf_rx_queues {
1050 uint64_t rx_dma_addr;
1051 uint32_t rx_ring_len;
1055 struct i40e_vf_tx_queues {
1056 uint64_t tx_dma_addr;
1057 uint32_t tx_ring_len;
1061 * Structure to store private data specific for VF instance.
1064 struct i40e_adapter *adapter; /* The adapter this VF associate to */
1065 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
1066 uint16_t num_queue_pairs;
1067 uint16_t max_pkt_len; /* Maximum packet length */
1068 bool promisc_unicast_enabled;
1069 bool promisc_multicast_enabled;
1071 uint32_t version_major; /* Major version number */
1072 uint32_t version_minor; /* Minor version number */
1073 uint16_t promisc_flags; /* Promiscuous setting */
1074 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
1076 /* Multicast addrs */
1077 struct rte_ether_addr mc_addrs[I40E_NUM_MACADDR_MAX];
1078 uint16_t mc_addrs_num; /* Multicast mac addresses number */
1083 enum virtchnl_link_speed link_speed;
1085 volatile uint32_t pend_cmd; /* pending command not finished yet */
1086 int32_t cmd_retval; /* return value of the cmd response from PF */
1087 u16 pend_msg; /* flags indicates events from pf not handled yet */
1088 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
1091 struct virtchnl_vf_resource *vf_res; /* All VSIs */
1092 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
1093 struct i40e_vsi vsi;
1097 #define I40E_MAX_PKT_TYPE 256
1098 #define I40E_FLOW_TYPE_MAX 64
1101 * Structure to store private data for each PF/VF instance.
1103 struct i40e_adapter {
1104 /* Common for both PF and VF */
1106 struct rte_eth_dev *eth_dev;
1108 /* Specific for PF or VF */
1114 /* For vector PMD */
1115 bool rx_bulk_alloc_allowed;
1116 bool rx_vec_allowed;
1117 bool tx_simple_allowed;
1118 bool tx_vec_allowed;
1121 struct rte_timecounter systime_tc;
1122 struct rte_timecounter rx_tstamp_tc;
1123 struct rte_timecounter tx_tstamp_tc;
1125 /* ptype mapping table */
1126 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
1127 /* flow type to pctype mapping table */
1128 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
1129 uint64_t flow_types_mask;
1130 uint64_t pctypes_mask;
1133 uint8_t use_latest_vec;
1135 /* For RSS reta table update */
1136 uint8_t rss_reta_updated;
1140 * Strucute to store private data for each VF representor instance
1142 struct i40e_vf_representor {
1143 uint16_t switch_domain_id;
1144 /**< Virtual Function ID */
1146 /**< Virtual Function ID */
1147 struct i40e_adapter *adapter;
1148 /**< Private data store of assocaiated physical function */
1149 struct i40e_eth_stats stats_offset;
1150 /**< Zero-point of VF statistics*/
1153 extern const struct rte_flow_ops i40e_flow_ops;
1155 union i40e_filter_t {
1156 struct rte_eth_ethertype_filter ethertype_filter;
1157 struct i40e_fdir_filter_conf fdir_filter;
1158 struct rte_eth_tunnel_filter_conf tunnel_filter;
1159 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
1160 struct i40e_rte_flow_rss_conf rss_conf;
1163 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
1164 const struct rte_flow_attr *attr,
1165 const struct rte_flow_item pattern[],
1166 const struct rte_flow_action actions[],
1167 struct rte_flow_error *error,
1168 union i40e_filter_t *filter);
1169 struct i40e_valid_pattern {
1170 enum rte_flow_item_type *items;
1171 parse_filter_t parse_filter;
1174 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
1175 int i40e_vsi_release(struct i40e_vsi *vsi);
1176 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
1177 enum i40e_vsi_type type,
1178 struct i40e_vsi *uplink_vsi,
1179 uint16_t user_param);
1180 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1181 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1182 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1183 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1184 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
1185 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr);
1186 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
1187 void i40e_pf_disable_irq0(struct i40e_hw *hw);
1188 void i40e_pf_enable_irq0(struct i40e_hw *hw);
1189 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1190 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
1191 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
1192 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
1193 struct i40e_vsi_vlan_pvid_info *info);
1194 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
1195 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
1196 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags);
1197 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags);
1198 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
1199 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
1200 int i40e_fdir_setup(struct i40e_pf *pf);
1201 const struct rte_memzone *i40e_memzone_reserve(const char *name,
1204 int i40e_fdir_configure(struct rte_eth_dev *dev);
1205 void i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on);
1206 void i40e_fdir_teardown(struct i40e_pf *pf);
1207 enum i40e_filter_pctype
1208 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter,
1209 uint16_t flow_type);
1210 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
1211 enum i40e_filter_pctype pctype);
1212 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1213 enum rte_filter_op filter_op,
1215 int i40e_select_filter_input_set(struct i40e_hw *hw,
1216 struct rte_eth_input_set_conf *conf,
1217 enum rte_filter_type filter);
1218 void i40e_fdir_filter_restore(struct i40e_pf *pf);
1219 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
1220 struct rte_eth_input_set_conf *conf);
1221 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
1222 struct rte_eth_input_set_conf *conf);
1223 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
1224 uint32_t retval, uint8_t *msg,
1226 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1227 struct rte_eth_rxq_info *qinfo);
1228 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1229 struct rte_eth_txq_info *qinfo);
1230 int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
1231 struct rte_eth_burst_mode *mode);
1232 int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
1233 struct rte_eth_burst_mode *mode);
1234 struct i40e_ethertype_filter *
1235 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
1236 const struct i40e_ethertype_filter_input *input);
1237 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
1238 struct i40e_ethertype_filter_input *input);
1239 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
1240 struct i40e_fdir_input *input);
1241 struct i40e_tunnel_filter *
1242 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
1243 const struct i40e_tunnel_filter_input *input);
1244 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
1245 struct i40e_tunnel_filter_input *input);
1246 uint64_t i40e_get_default_input_set(uint16_t pctype);
1247 int i40e_ethertype_filter_set(struct i40e_pf *pf,
1248 struct rte_eth_ethertype_filter *filter,
1250 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1251 const struct rte_eth_fdir_filter *filter,
1253 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1254 const struct i40e_fdir_filter_conf *filter,
1256 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
1257 struct rte_eth_tunnel_filter_conf *tunnel_filter,
1259 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
1260 struct i40e_tunnel_filter_conf *tunnel_filter,
1262 int i40e_fdir_flush(struct rte_eth_dev *dev);
1263 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
1264 struct i40e_macvlan_filter *mv_f,
1265 int num, struct rte_ether_addr *addr);
1266 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
1267 struct i40e_macvlan_filter *filter,
1269 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
1270 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
1271 struct i40e_macvlan_filter *filter,
1273 bool is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv);
1274 bool is_i40e_supported(struct rte_eth_dev *dev);
1275 bool is_i40evf_supported(struct rte_eth_dev *dev);
1277 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
1278 enum rte_filter_type filter, uint64_t inset);
1279 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1281 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1282 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1283 void i40e_check_write_global_reg(struct i40e_hw *hw,
1284 uint32_t addr, uint32_t val);
1286 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1287 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1288 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1289 struct i40e_customized_pctype*
1290 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);
1291 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
1293 enum rte_pmd_i40e_package_op op);
1294 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
1295 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
1296 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on);
1297 void i40e_init_queue_region_conf(struct rte_eth_dev *dev);
1298 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw);
1299 int i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len);
1300 int i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size);
1301 int i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
1302 const struct rte_flow_action_rss *in);
1303 int i40e_action_rss_same(const struct rte_flow_action_rss *comp,
1304 const struct rte_flow_action_rss *with);
1305 int i40e_config_rss_filter(struct i40e_pf *pf,
1306 struct i40e_rte_flow_rss_conf *conf, bool add);
1307 int i40e_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params);
1308 int i40e_vf_representor_uninit(struct rte_eth_dev *ethdev);
1310 #define I40E_DEV_TO_PCI(eth_dev) \
1311 RTE_DEV_TO_PCI((eth_dev)->device)
1313 /* I40E_DEV_PRIVATE_TO */
1314 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1315 (&((struct i40e_adapter *)adapter)->pf)
1316 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1317 (&((struct i40e_adapter *)adapter)->hw)
1318 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1319 ((struct i40e_adapter *)adapter)
1321 /* I40EVF_DEV_PRIVATE_TO */
1322 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1323 (&((struct i40e_adapter *)adapter)->vf)
1325 static inline struct i40e_vsi *
1326 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1333 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1334 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1335 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1338 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1339 return pf->main_vsi;
1342 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1343 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1346 #define I40E_VSI_TO_HW(vsi) \
1347 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1348 #define I40E_VSI_TO_PF(vsi) \
1349 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1350 #define I40E_VSI_TO_VF(vsi) \
1351 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1352 #define I40E_VSI_TO_DEV_DATA(vsi) \
1353 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1354 #define I40E_VSI_TO_ETH_DEV(vsi) \
1355 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1358 #define I40E_PF_TO_HW(pf) \
1359 (&(((struct i40e_pf *)pf)->adapter->hw))
1360 #define I40E_PF_TO_ADAPTER(pf) \
1361 ((struct i40e_adapter *)pf->adapter)
1364 #define I40E_VF_TO_HW(vf) \
1365 (&(((struct i40e_vf *)vf)->adapter->hw))
1368 i40e_init_adminq_parameter(struct i40e_hw *hw)
1370 hw->aq.num_arq_entries = I40E_AQ_LEN;
1371 hw->aq.num_asq_entries = I40E_AQ_LEN;
1372 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1373 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1377 i40e_align_floor(int n)
1381 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1384 static inline uint16_t
1385 i40e_calc_itr_interval(bool is_pf, bool is_multi_drv)
1387 uint16_t interval = 0;
1390 interval = I40E_QUEUE_ITR_INTERVAL_MAX;
1393 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1395 interval = I40E_VF_QUEUE_ITR_INTERVAL_DEFAULT;
1398 /* Convert to hardware count, as writing each 1 represents 2 us */
1399 return interval / 2;
1402 #define I40E_VALID_FLOW(flow_type) \
1403 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1404 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1405 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1406 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1407 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1408 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1409 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1410 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1411 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1412 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1413 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1415 #define I40E_VALID_PCTYPE_X722(pctype) \
1416 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1417 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1418 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1419 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1420 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1421 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1422 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1423 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1424 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1425 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1426 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1427 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1428 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1429 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1430 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1431 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1432 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1434 #define I40E_VALID_PCTYPE(pctype) \
1435 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1436 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1437 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1438 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1439 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1440 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1441 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1442 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1443 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1444 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1445 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1447 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1448 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1449 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1450 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1451 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1452 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1453 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1455 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1456 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1457 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1458 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1459 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR) || \
1460 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_AOC) || \
1461 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_ACC))
1463 #endif /* _I40E_ETHDEV_H_ */