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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #include <rte_kvargs.h>
41 #include <rte_flow_driver.h>
43 #define I40E_VLAN_TAG_SIZE 4
45 #define I40E_AQ_LEN 32
46 #define I40E_AQ_BUF_SZ 4096
47 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
48 #define I40E_MAX_Q_PER_TC 64
49 #define I40E_NUM_DESC_DEFAULT 512
50 #define I40E_NUM_DESC_ALIGN 32
51 #define I40E_BUF_SIZE_MIN 1024
52 #define I40E_FRAME_SIZE_MAX 9728
53 #define I40E_QUEUE_BASE_ADDR_UNIT 128
54 /* number of VSIs and queue default setting */
55 #define I40E_MAX_QP_NUM_PER_VF 16
56 #define I40E_DEFAULT_QP_NUM_FDIR 1
57 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
58 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
59 /* Maximun number of MAC addresses */
60 #define I40E_NUM_MACADDR_MAX 64
61 /* Maximum number of VFs */
62 #define I40E_MAX_VF 128
65 * vlan_id is a 12 bit number.
66 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
67 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
68 * The higher 7 bit val specifies VFTA array index.
70 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
71 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
73 /* Default TC traffic in case DCB is not enabled */
74 #define I40E_DEFAULT_TCMAP 0x1
75 #define I40E_FDIR_QUEUE_ID 0
77 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
78 #define I40E_VMDQ_POOL_BASE 1
80 #define I40E_DEFAULT_RX_FREE_THRESH 32
81 #define I40E_DEFAULT_RX_PTHRESH 8
82 #define I40E_DEFAULT_RX_HTHRESH 8
83 #define I40E_DEFAULT_RX_WTHRESH 0
85 #define I40E_DEFAULT_TX_FREE_THRESH 32
86 #define I40E_DEFAULT_TX_PTHRESH 32
87 #define I40E_DEFAULT_TX_HTHRESH 0
88 #define I40E_DEFAULT_TX_WTHRESH 0
89 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
91 /* Bit shift and mask */
92 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
93 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
94 #define I40E_8_BIT_WIDTH CHAR_BIT
95 #define I40E_8_BIT_MASK UINT8_MAX
96 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
97 #define I40E_16_BIT_MASK UINT16_MAX
98 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
99 #define I40E_32_BIT_MASK UINT32_MAX
100 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
101 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
103 /* Linux PF host with virtchnl version 1.1 */
104 #define PF_IS_V11(vf) \
105 (((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \
106 ((vf)->version_minor == 1))
108 /* index flex payload per layer */
109 enum i40e_flxpld_layer_idx {
110 I40E_FLXPLD_L2_IDX = 0,
111 I40E_FLXPLD_L3_IDX = 1,
112 I40E_FLXPLD_L4_IDX = 2,
113 I40E_MAX_FLXPLD_LAYER = 3,
115 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
116 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
117 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
118 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
119 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
122 #define I40E_FLAG_RSS (1ULL << 0)
123 #define I40E_FLAG_DCB (1ULL << 1)
124 #define I40E_FLAG_VMDQ (1ULL << 2)
125 #define I40E_FLAG_SRIOV (1ULL << 3)
126 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
127 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
128 #define I40E_FLAG_FDIR (1ULL << 6)
129 #define I40E_FLAG_VXLAN (1ULL << 7)
130 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
131 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
135 I40E_FLAG_HEADER_SPLIT_DISABLED | \
136 I40E_FLAG_HEADER_SPLIT_ENABLED | \
139 I40E_FLAG_RSS_AQ_CAPABLE)
141 #define I40E_RSS_OFFLOAD_ALL ( \
142 ETH_RSS_FRAG_IPV4 | \
143 ETH_RSS_NONFRAG_IPV4_TCP | \
144 ETH_RSS_NONFRAG_IPV4_UDP | \
145 ETH_RSS_NONFRAG_IPV4_SCTP | \
146 ETH_RSS_NONFRAG_IPV4_OTHER | \
147 ETH_RSS_FRAG_IPV6 | \
148 ETH_RSS_NONFRAG_IPV6_TCP | \
149 ETH_RSS_NONFRAG_IPV6_UDP | \
150 ETH_RSS_NONFRAG_IPV6_SCTP | \
151 ETH_RSS_NONFRAG_IPV6_OTHER | \
154 /* All bits of RSS hash enable for X722*/
155 #define I40E_RSS_HENA_ALL_X722 ( \
156 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
157 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
158 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
159 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
160 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
161 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
164 /* All bits of RSS hash enable */
165 #define I40E_RSS_HENA_ALL ( \
166 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
168 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
169 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
170 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
173 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
174 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
175 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
176 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
177 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
178 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
179 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
181 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
182 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
184 /* Default queue interrupt throttling time in microseconds */
185 #define I40E_ITR_INDEX_DEFAULT 0
186 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
187 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
189 /* Special FW support this floating VEB feature */
190 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
191 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
193 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
194 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
195 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
196 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
198 #define I40E_INSET_NONE 0x00000000000000000ULL
201 #define I40E_INSET_DMAC 0x0000000000000001ULL
202 #define I40E_INSET_SMAC 0x0000000000000002ULL
203 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
204 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
205 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
208 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
209 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
210 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
211 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
212 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
213 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
214 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
216 /* bit 16 ~ bit 31 */
217 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
218 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
219 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
220 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
221 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
222 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
223 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
224 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
226 /* bit 32 ~ bit 47, tunnel fields */
227 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
228 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
229 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
230 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
231 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
232 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
234 /* bit 48 ~ bit 55 */
235 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
237 /* bit 56 ~ bit 63, Flex Payload */
238 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
239 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
240 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
241 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
242 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
243 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
244 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
245 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
246 #define I40E_INSET_FLEX_PAYLOAD \
247 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
248 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
249 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
250 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
255 * MAC filter structure
257 struct i40e_mac_filter_info {
258 enum rte_mac_filter_type filter_type;
259 struct ether_addr mac_addr;
262 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
264 /* MAC filter list structure */
265 struct i40e_mac_filter {
266 TAILQ_ENTRY(i40e_mac_filter) next;
267 struct i40e_mac_filter_info mac_info;
270 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
274 /* VSI list structure */
275 struct i40e_vsi_list {
276 TAILQ_ENTRY(i40e_vsi_list) list;
277 struct i40e_vsi *vsi;
280 struct i40e_rx_queue;
281 struct i40e_tx_queue;
283 /* Bandwidth limit information */
284 struct i40e_bw_info {
285 uint16_t bw_limit; /* BW Limit (0 = disabled) */
286 uint8_t bw_max; /* Max BW limit if enabled */
288 /* Relative credits within same TC with respect to other VSIs or Comps */
289 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
290 /* Bandwidth limit per TC */
291 uint8_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
292 /* Max bandwidth limit per TC */
293 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
296 /* Structure that defines a VEB */
298 struct i40e_vsi_list_head head;
299 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
300 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
301 uint16_t seid; /* The seid of VEB itself */
302 uint16_t uplink_seid; /* The uplink seid of this VEB */
304 struct i40e_eth_stats stats;
305 uint8_t enabled_tc; /* The traffic class enabled */
306 struct i40e_bw_info bw_info; /* VEB bandwidth information */
309 /* i40e MACVLAN filter structure */
310 struct i40e_macvlan_filter {
311 struct ether_addr macaddr;
312 enum rte_mac_filter_type filter_type;
317 * Structure that defines a VSI, associated with a adapter.
320 struct i40e_adapter *adapter; /* Backreference to associated adapter */
321 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
323 struct i40e_eth_stats eth_stats_offset;
324 struct i40e_eth_stats eth_stats;
326 * When drivers loaded, only a default main VSI exists. In case new VSI
327 * needs to add, HW needs to know the layout that VSIs are organized.
328 * Besides that, VSI isan element and can't switch packets, which needs
329 * to add new component VEB to perform switching. So, a new VSI needs
330 * to specify the the uplink VSI (Parent VSI) before created. The
331 * uplink VSI will check whether it had a VEB to switch packets. If no,
332 * it will try to create one. Then, uplink VSI will move the new VSI
333 * into its' sib_vsi_list to manage all the downlink VSI.
334 * sib_vsi_list: the VSI list that shared the same uplink VSI.
335 * parent_vsi : the uplink VSI. It's NULL for main VSI.
336 * veb : the VEB associates with the VSI.
338 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
339 struct i40e_vsi *parent_vsi;
340 struct i40e_veb *veb; /* Associated veb, could be null */
341 struct i40e_veb *floating_veb; /* Associated floating veb */
343 enum i40e_vsi_type type; /* VSI types */
344 uint16_t vlan_num; /* Total VLAN number */
345 uint16_t mac_num; /* Total mac number */
346 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
347 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
348 /* specific VSI-defined parameters, SRIOV stored the vf_id */
350 uint16_t seid; /* The seid of VSI itself */
351 uint16_t uplink_seid; /* The uplink seid of this VSI */
352 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
353 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
354 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
355 uint16_t base_queue; /* The first queue index of this VSI */
357 * The offset to visit VSI related register, assigned by HW when
361 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
362 uint16_t nb_msix; /* The max number of msix vector */
363 uint8_t enabled_tc; /* The traffic class enabled */
364 struct i40e_bw_info bw_info; /* VSI bandwidth information */
368 LIST_ENTRY(pool_entry) next;
373 LIST_HEAD(res_list, pool_entry);
375 struct i40e_res_pool_info {
376 uint32_t base; /* Resource start index */
377 uint32_t num_alloc; /* Allocated resource number */
378 uint32_t num_free; /* Total available resource number */
379 struct res_list alloc_list; /* Allocated resource list */
380 struct res_list free_list; /* Available resource list */
384 I40E_VF_INACTIVE = 0,
391 * Structure to store private data for PF host.
395 struct i40e_vsi *vsi;
396 enum I40E_VF_STATE state; /* The number of queue pairs availiable */
397 uint16_t vf_idx; /* VF index in pf->vfs */
398 uint16_t lan_nb_qps; /* Actual queues allocated */
399 uint16_t reset_cnt; /* Total vf reset times */
400 struct ether_addr mac_addr; /* Default MAC address */
404 * Structure to store private data for flow control.
406 struct i40e_fc_conf {
407 uint16_t pause_time; /* Flow control pause timer */
408 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
409 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
410 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
411 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
415 * Structure to store private data for VMDQ instance
417 struct i40e_vmdq_info {
419 struct i40e_vsi *vsi;
423 * Structure to store flex pit for flow diretor.
425 struct i40e_fdir_flex_pit {
426 uint8_t src_offset; /* offset in words from the beginning of payload */
427 uint8_t size; /* size in words */
428 uint8_t dst_offset; /* offset in words of flexible payload */
431 struct i40e_fdir_flex_mask {
432 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
436 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
439 #define I40E_FILTER_PCTYPE_MAX 64
440 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
442 struct i40e_fdir_filter {
443 TAILQ_ENTRY(i40e_fdir_filter) rules;
444 struct rte_eth_fdir_filter fdir;
447 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
449 * A structure used to define fields of a FDIR related info.
451 struct i40e_fdir_info {
452 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
453 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
454 struct i40e_tx_queue *txq;
455 struct i40e_rx_queue *rxq;
456 void *prg_pkt; /* memory for fdir program packet */
457 uint64_t dma_addr; /* physic address of packet memory*/
458 /* input set bits for each pctype */
459 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
461 * the rule how bytes stream is extracted as flexible payload
462 * for each payload layer, the setting can up to three elements
464 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
465 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
467 struct i40e_fdir_filter_list fdir_list;
468 struct i40e_fdir_filter **hash_map;
469 struct rte_hash *hash_table;
472 /* Ethertype filter number HW supports */
473 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
475 /* Ethertype filter struct */
476 struct i40e_ethertype_filter_input {
477 struct ether_addr mac_addr; /* Mac address to match */
478 uint16_t ether_type; /* Ether type to match */
481 struct i40e_ethertype_filter {
482 TAILQ_ENTRY(i40e_ethertype_filter) rules;
483 struct i40e_ethertype_filter_input input;
484 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
485 uint16_t queue; /* Queue assigned to when match */
488 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
490 struct i40e_ethertype_rule {
491 struct i40e_ethertype_filter_list ethertype_list;
492 struct i40e_ethertype_filter **hash_map;
493 struct rte_hash *hash_table;
496 /* Tunnel filter number HW supports */
497 #define I40E_MAX_TUNNEL_FILTER_NUM 400
499 /* Tunnel filter struct */
500 struct i40e_tunnel_filter_input {
501 uint8_t outer_mac[6]; /* Outer mac address to match */
502 uint8_t inner_mac[6]; /* Inner mac address to match */
503 uint16_t inner_vlan; /* Inner vlan address to match */
504 uint16_t flags; /* Filter type flag */
505 uint32_t tenant_id; /* Tenant id to match */
508 struct i40e_tunnel_filter {
509 TAILQ_ENTRY(i40e_tunnel_filter) rules;
510 struct i40e_tunnel_filter_input input;
511 uint16_t queue; /* Queue assigned to when match */
514 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
516 struct i40e_tunnel_rule {
517 struct i40e_tunnel_filter_list tunnel_list;
518 struct i40e_tunnel_filter **hash_map;
519 struct rte_hash *hash_table;
522 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
523 #define I40E_MAX_MIRROR_RULES 64
525 * Mirror rule structure
527 struct i40e_mirror_rule {
528 TAILQ_ENTRY(i40e_mirror_rule) rules;
530 uint16_t index; /* the sw index of mirror rule */
531 uint16_t id; /* the rule id assigned by firmware */
532 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
533 uint16_t num_entries;
534 /* the info stores depend on the rule type.
535 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
536 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
538 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
541 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
544 * Struct to store flow created.
547 TAILQ_ENTRY(rte_flow) node;
548 enum rte_filter_type filter_type;
552 TAILQ_HEAD(i40e_flow_list, rte_flow);
555 * Structure to store private data specific for PF instance.
558 struct i40e_adapter *adapter; /* The adapter this PF associate to */
559 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
560 uint16_t mac_seid; /* The seid of the MAC of this PF */
561 uint16_t main_vsi_seid; /* The seid of the main VSI */
562 uint16_t max_num_vsi;
563 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
564 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
566 struct i40e_hw_port_stats stats_offset;
567 struct i40e_hw_port_stats stats;
570 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
571 struct ether_addr dev_addr; /* PF device mac address */
572 uint64_t flags; /* PF feature flags */
573 /* All kinds of queue pair setting for different VSIs */
574 struct i40e_pf_vf *vfs;
576 /* Each of below queue pairs should be power of 2 since it's the
577 precondition after TC configuration applied */
578 uint16_t lan_nb_qp_max;
579 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
580 uint16_t lan_qp_offset;
581 uint16_t vmdq_nb_qp_max;
582 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
583 uint16_t vmdq_qp_offset;
584 uint16_t vf_nb_qp_max;
585 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
586 uint16_t vf_qp_offset;
587 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
588 uint16_t fdir_qp_offset;
590 uint16_t hash_lut_size; /* The size of hash lookup table */
591 /* input set bits for each pctype */
592 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
593 /* store VXLAN UDP ports */
594 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
595 uint16_t vxlan_bitmap; /* Vxlan bit mask */
597 /* VMDQ related info */
598 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
599 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
600 struct i40e_vmdq_info *vmdq;
602 struct i40e_fdir_info fdir; /* flow director info */
603 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
604 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
605 struct i40e_fc_conf fc_conf; /* Flow control conf */
606 struct i40e_mirror_rule_list mirror_list;
607 uint16_t nb_mirror_rule; /* The number of mirror rules */
608 bool floating_veb; /* The flag to use the floating VEB */
609 /* The floating enable flag for the specific VF */
610 bool floating_veb_list[I40E_MAX_VF];
611 struct i40e_flow_list flow_list;
615 PFMSG_LINK_CHANGE = 0x1,
616 PFMSG_RESET_IMPENDING = 0x2,
617 PFMSG_DRIVER_CLOSE = 0x4,
620 struct i40e_vsi_vlan_pvid_info {
621 uint16_t on; /* Enable or disable pvid */
623 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
625 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
626 * while 'untagged' will reject untagged packets.
634 struct i40e_vf_rx_queues {
635 uint64_t rx_dma_addr;
636 uint32_t rx_ring_len;
640 struct i40e_vf_tx_queues {
641 uint64_t tx_dma_addr;
642 uint32_t tx_ring_len;
646 * Structure to store private data specific for VF instance.
649 struct i40e_adapter *adapter; /* The adapter this VF associate to */
650 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
651 uint16_t num_queue_pairs;
652 uint16_t max_pkt_len; /* Maximum packet length */
653 bool promisc_unicast_enabled;
654 bool promisc_multicast_enabled;
656 uint32_t version_major; /* Major version number */
657 uint32_t version_minor; /* Minor version number */
658 uint16_t promisc_flags; /* Promiscuous setting */
659 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
664 enum i40e_aq_link_speed link_speed;
666 volatile uint32_t pend_cmd; /* pending command not finished yet */
667 int32_t cmd_retval; /* return value of the cmd response from PF */
668 u16 pend_msg; /* flags indicates events from pf not handled yet */
669 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
672 struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */
673 struct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */
679 * Structure to store private data for each PF/VF instance.
681 struct i40e_adapter {
682 /* Common for both PF and VF */
684 struct rte_eth_dev *eth_dev;
686 /* Specific for PF or VF */
693 bool rx_bulk_alloc_allowed;
695 bool tx_simple_allowed;
699 struct rte_timecounter systime_tc;
700 struct rte_timecounter rx_tstamp_tc;
701 struct rte_timecounter tx_tstamp_tc;
704 extern const struct rte_flow_ops i40e_flow_ops;
706 union i40e_filter_t {
707 struct rte_eth_ethertype_filter ethertype_filter;
708 struct rte_eth_fdir_filter fdir_filter;
709 struct rte_eth_tunnel_filter_conf tunnel_filter;
712 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
713 const struct rte_flow_attr *attr,
714 const struct rte_flow_item pattern[],
715 const struct rte_flow_action actions[],
716 struct rte_flow_error *error,
717 union i40e_filter_t *filter);
718 struct i40e_valid_pattern {
719 enum rte_flow_item_type *items;
720 parse_filter_t parse_filter;
723 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
724 int i40e_vsi_release(struct i40e_vsi *vsi);
725 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
726 enum i40e_vsi_type type,
727 struct i40e_vsi *uplink_vsi,
728 uint16_t user_param);
729 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
730 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
731 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
732 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
733 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
734 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
735 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
736 void i40e_pf_disable_irq0(struct i40e_hw *hw);
737 void i40e_pf_enable_irq0(struct i40e_hw *hw);
738 int i40e_dev_link_update(struct rte_eth_dev *dev,
739 __rte_unused int wait_to_complete);
740 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi);
741 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
742 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
743 struct i40e_vsi_vlan_pvid_info *info);
744 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
745 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
746 uint64_t i40e_config_hena(uint64_t flags, enum i40e_mac_type type);
747 uint64_t i40e_parse_hena(uint64_t flags);
748 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
749 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
750 int i40e_fdir_setup(struct i40e_pf *pf);
751 const struct rte_memzone *i40e_memzone_reserve(const char *name,
754 int i40e_fdir_configure(struct rte_eth_dev *dev);
755 void i40e_fdir_teardown(struct i40e_pf *pf);
756 enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type);
757 uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);
758 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
759 enum rte_filter_op filter_op,
761 int i40e_select_filter_input_set(struct i40e_hw *hw,
762 struct rte_eth_input_set_conf *conf,
763 enum rte_filter_type filter);
764 void i40e_fdir_filter_restore(struct i40e_pf *pf);
765 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
766 struct rte_eth_input_set_conf *conf);
767 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
768 struct rte_eth_input_set_conf *conf);
769 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
770 uint32_t retval, uint8_t *msg,
772 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
773 struct rte_eth_rxq_info *qinfo);
774 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
775 struct rte_eth_txq_info *qinfo);
776 struct i40e_ethertype_filter *
777 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
778 const struct i40e_ethertype_filter_input *input);
779 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
780 struct i40e_ethertype_filter_input *input);
781 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
782 struct rte_eth_fdir_input *input);
783 struct i40e_tunnel_filter *
784 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
785 const struct i40e_tunnel_filter_input *input);
786 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
787 struct i40e_tunnel_filter_input *input);
788 uint64_t i40e_get_default_input_set(uint16_t pctype);
789 int i40e_ethertype_filter_set(struct i40e_pf *pf,
790 struct rte_eth_ethertype_filter *filter,
792 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
793 const struct rte_eth_fdir_filter *filter,
795 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
796 struct rte_eth_tunnel_filter_conf *tunnel_filter,
798 int i40e_fdir_flush(struct rte_eth_dev *dev);
800 #define I40E_DEV_TO_PCI(eth_dev) \
801 RTE_DEV_TO_PCI((eth_dev)->device)
803 /* I40E_DEV_PRIVATE_TO */
804 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
805 (&((struct i40e_adapter *)adapter)->pf)
806 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
807 (&((struct i40e_adapter *)adapter)->hw)
808 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
809 ((struct i40e_adapter *)adapter)
811 /* I40EVF_DEV_PRIVATE_TO */
812 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
813 (&((struct i40e_adapter *)adapter)->vf)
815 static inline struct i40e_vsi *
816 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
823 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
824 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
825 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
828 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
832 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
833 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
836 #define I40E_VSI_TO_HW(vsi) \
837 (&(((struct i40e_vsi *)vsi)->adapter->hw))
838 #define I40E_VSI_TO_PF(vsi) \
839 (&(((struct i40e_vsi *)vsi)->adapter->pf))
840 #define I40E_VSI_TO_VF(vsi) \
841 (&(((struct i40e_vsi *)vsi)->adapter->vf))
842 #define I40E_VSI_TO_DEV_DATA(vsi) \
843 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
844 #define I40E_VSI_TO_ETH_DEV(vsi) \
845 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
848 #define I40E_PF_TO_HW(pf) \
849 (&(((struct i40e_pf *)pf)->adapter->hw))
850 #define I40E_PF_TO_ADAPTER(pf) \
851 ((struct i40e_adapter *)pf->adapter)
854 #define I40E_VF_TO_HW(vf) \
855 (&(((struct i40e_vf *)vf)->adapter->hw))
858 i40e_init_adminq_parameter(struct i40e_hw *hw)
860 hw->aq.num_arq_entries = I40E_AQ_LEN;
861 hw->aq.num_asq_entries = I40E_AQ_LEN;
862 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
863 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
867 i40e_align_floor(int n)
871 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
874 static inline uint16_t
875 i40e_calc_itr_interval(int16_t interval)
877 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
878 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
880 /* Convert to hardware count, as writing each 1 represents 2 us */
884 #define I40E_VALID_FLOW(flow_type) \
885 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
886 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
887 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
888 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
889 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
890 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
891 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
892 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
893 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
894 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
895 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
897 #define I40E_VALID_PCTYPE_X722(pctype) \
898 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
899 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
900 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
901 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
902 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
903 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
904 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
905 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
906 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
907 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
908 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
909 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
910 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
911 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
912 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
913 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
914 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
916 #define I40E_VALID_PCTYPE(pctype) \
917 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
918 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
919 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
920 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
921 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
922 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
923 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
924 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
925 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
926 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
927 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
929 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
930 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
931 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
932 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
933 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
934 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
935 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
937 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
938 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
939 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
940 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
941 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
943 #endif /* _I40E_ETHDEV_H_ */