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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
55 #include <rte_alarm.h>
56 #include <rte_ether.h>
57 #include <rte_ethdev.h>
58 #include <rte_atomic.h>
59 #include <rte_malloc.h>
62 #include "i40e_logs.h"
63 #include "base/i40e_prototype.h"
64 #include "base/i40e_adminq_cmd.h"
65 #include "base/i40e_type.h"
67 #include "i40e_rxtx.h"
68 #include "i40e_ethdev.h"
70 #define I40EVF_VSI_DEFAULT_MSIX_INTR 1
72 /* busy wait delay in msec */
73 #define I40EVF_BUSY_WAIT_DELAY 10
74 #define I40EVF_BUSY_WAIT_COUNT 50
75 #define MAX_RESET_WAIT_CNT 20
77 struct i40evf_arq_msg_info {
78 enum i40e_virtchnl_ops ops;
79 enum i40e_status_code result;
86 enum i40e_virtchnl_ops ops;
88 uint32_t in_args_size;
90 /* Input & output type. pass in buffer size and pass out
91 * actual return result
96 enum i40evf_aq_result {
97 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
98 I40EVF_MSG_NON, /* Read nothing from admin queue */
99 I40EVF_MSG_SYS, /* Read system msg from admin queue */
100 I40EVF_MSG_CMD, /* Read async command result */
103 /* A share buffer to store the command result from PF driver */
104 static uint8_t cmd_result_buffer[I40E_AQ_BUF_SZ];
106 static int i40evf_dev_configure(struct rte_eth_dev *dev);
107 static int i40evf_dev_start(struct rte_eth_dev *dev);
108 static void i40evf_dev_stop(struct rte_eth_dev *dev);
109 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
110 struct rte_eth_dev_info *dev_info);
111 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
112 __rte_unused int wait_to_complete);
113 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
114 struct rte_eth_stats *stats);
115 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
116 uint16_t vlan_id, int on);
117 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
118 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
120 static void i40evf_dev_close(struct rte_eth_dev *dev);
121 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
122 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
123 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
124 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
125 static int i40evf_get_link_status(struct rte_eth_dev *dev,
126 struct rte_eth_link *link);
127 static int i40evf_init_vlan(struct rte_eth_dev *dev);
128 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
129 uint16_t rx_queue_id);
130 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
131 uint16_t rx_queue_id);
132 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
133 uint16_t tx_queue_id);
134 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
135 uint16_t tx_queue_id);
136 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
137 struct rte_eth_rss_reta_entry64 *reta_conf,
139 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
140 struct rte_eth_rss_reta_entry64 *reta_conf,
142 static int i40evf_config_rss(struct i40e_vf *vf);
143 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
144 struct rte_eth_rss_conf *rss_conf);
145 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
146 struct rte_eth_rss_conf *rss_conf);
148 /* Default hash key buffer for RSS */
149 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
151 static const struct eth_dev_ops i40evf_eth_dev_ops = {
152 .dev_configure = i40evf_dev_configure,
153 .dev_start = i40evf_dev_start,
154 .dev_stop = i40evf_dev_stop,
155 .promiscuous_enable = i40evf_dev_promiscuous_enable,
156 .promiscuous_disable = i40evf_dev_promiscuous_disable,
157 .allmulticast_enable = i40evf_dev_allmulticast_enable,
158 .allmulticast_disable = i40evf_dev_allmulticast_disable,
159 .link_update = i40evf_dev_link_update,
160 .stats_get = i40evf_dev_stats_get,
161 .dev_close = i40evf_dev_close,
162 .dev_infos_get = i40evf_dev_info_get,
163 .vlan_filter_set = i40evf_vlan_filter_set,
164 .vlan_offload_set = i40evf_vlan_offload_set,
165 .vlan_pvid_set = i40evf_vlan_pvid_set,
166 .rx_queue_start = i40evf_dev_rx_queue_start,
167 .rx_queue_stop = i40evf_dev_rx_queue_stop,
168 .tx_queue_start = i40evf_dev_tx_queue_start,
169 .tx_queue_stop = i40evf_dev_tx_queue_stop,
170 .rx_queue_setup = i40e_dev_rx_queue_setup,
171 .rx_queue_release = i40e_dev_rx_queue_release,
172 .tx_queue_setup = i40e_dev_tx_queue_setup,
173 .tx_queue_release = i40e_dev_tx_queue_release,
174 .reta_update = i40evf_dev_rss_reta_update,
175 .reta_query = i40evf_dev_rss_reta_query,
176 .rss_hash_update = i40evf_dev_rss_hash_update,
177 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
181 i40evf_set_mac_type(struct i40e_hw *hw)
183 int status = I40E_ERR_DEVICE_NOT_SUPPORTED;
185 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
186 switch (hw->device_id) {
188 case I40E_DEV_ID_VF_HV:
189 hw->mac.type = I40E_MAC_VF;
190 status = I40E_SUCCESS;
201 * Parse admin queue message.
206 * > 0: read cmd result
208 static enum i40evf_aq_result
209 i40evf_parse_pfmsg(struct i40e_vf *vf,
210 struct i40e_arq_event_info *event,
211 struct i40evf_arq_msg_info *data)
213 enum i40e_virtchnl_ops opcode = (enum i40e_virtchnl_ops)\
214 rte_le_to_cpu_32(event->desc.cookie_high);
215 enum i40e_status_code retval = (enum i40e_status_code)\
216 rte_le_to_cpu_32(event->desc.cookie_low);
217 enum i40evf_aq_result ret = I40EVF_MSG_CMD;
220 if (opcode == I40E_VIRTCHNL_OP_EVENT) {
221 struct i40e_virtchnl_pf_event *vpe =
222 (struct i40e_virtchnl_pf_event *)event->msg_buf;
224 /* Initialize ret to sys event */
225 ret = I40EVF_MSG_SYS;
226 switch (vpe->event) {
227 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
229 vpe->event_data.link_event.link_status;
230 vf->pend_msg |= PFMSG_LINK_CHANGE;
231 PMD_DRV_LOG(INFO, "Link status update:%s",
232 vf->link_up ? "up" : "down");
234 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
236 vf->pend_msg |= PFMSG_RESET_IMPENDING;
237 PMD_DRV_LOG(INFO, "vf is reseting");
239 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
240 vf->dev_closed = true;
241 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
242 PMD_DRV_LOG(INFO, "PF driver closed");
245 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
246 __func__, vpe->event);
249 /* async reply msg on command issued by vf previously */
250 ret = I40EVF_MSG_CMD;
251 /* Actual data length read from PF */
252 data->msg_len = event->msg_len;
254 /* fill the ops and result to notify VF */
255 data->result = retval;
262 * Read data in admin queue to get msg from pf driver
264 static enum i40evf_aq_result
265 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
267 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
268 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
269 struct i40e_arq_event_info event;
271 enum i40evf_aq_result result = I40EVF_MSG_NON;
273 event.buf_len = data->buf_len;
274 event.msg_buf = data->msg;
275 ret = i40e_clean_arq_element(hw, &event, NULL);
276 /* Can't read any msg from adminQ */
278 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
279 result = I40EVF_MSG_NON;
281 result = I40EVF_MSG_ERR;
285 /* Parse the event */
286 result = i40evf_parse_pfmsg(vf, &event, data);
292 * Polling read until command result return from pf driver or meet error.
295 i40evf_wait_cmd_done(struct rte_eth_dev *dev,
296 struct i40evf_arq_msg_info *data)
299 enum i40evf_aq_result ret;
301 #define MAX_TRY_TIMES 10
302 #define ASQ_DELAY_MS 50
304 /* Delay some time first */
305 rte_delay_ms(ASQ_DELAY_MS);
306 ret = i40evf_read_pfmsg(dev, data);
307 if (ret == I40EVF_MSG_CMD)
309 else if (ret == I40EVF_MSG_ERR)
312 /* If don't read msg or read sys event, continue */
313 } while(i++ < MAX_TRY_TIMES);
319 * clear current command. Only call in case execute
320 * _atomic_set_cmd successfully.
323 _clear_cmd(struct i40e_vf *vf)
326 vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
330 * Check there is pending cmd in execution. If none, set new command.
333 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
335 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
336 I40E_VIRTCHNL_OP_UNKNOWN, ops);
339 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
345 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
347 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
348 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
350 struct i40evf_arq_msg_info info;
352 if (_atomic_set_cmd(vf, args->ops))
355 info.msg = args->out_buffer;
356 info.buf_len = args->out_size;
357 info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
358 info.result = I40E_SUCCESS;
360 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
361 args->in_args, args->in_args_size, NULL);
363 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
367 err = i40evf_wait_cmd_done(dev, &info);
368 /* read message and it's expected one */
369 if (!err && args->ops == info.ops)
372 PMD_DRV_LOG(ERR, "Failed to read message from AdminQ");
373 else if (args->ops != info.ops)
374 PMD_DRV_LOG(ERR, "command mismatch, expect %u, get %u",
375 args->ops, info.ops);
377 return (err | info.result);
381 * Check API version with sync wait until version read or fail from admin queue
384 i40evf_check_api_version(struct rte_eth_dev *dev)
386 struct i40e_virtchnl_version_info version, *pver;
388 struct vf_cmd_info args;
389 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
391 version.major = I40E_VIRTCHNL_VERSION_MAJOR;
392 version.minor = I40E_VIRTCHNL_VERSION_MINOR;
394 args.ops = I40E_VIRTCHNL_OP_VERSION;
395 args.in_args = (uint8_t *)&version;
396 args.in_args_size = sizeof(version);
397 args.out_buffer = cmd_result_buffer;
398 args.out_size = I40E_AQ_BUF_SZ;
400 err = i40evf_execute_vf_cmd(dev, &args);
402 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
406 pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
407 vf->version_major = pver->major;
408 vf->version_minor = pver->minor;
409 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
410 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
411 else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
412 (vf->version_minor == I40E_VIRTCHNL_VERSION_MINOR))
413 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
415 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
416 vf->version_major, vf->version_minor,
417 I40E_VIRTCHNL_VERSION_MAJOR,
418 I40E_VIRTCHNL_VERSION_MINOR);
426 i40evf_get_vf_resource(struct rte_eth_dev *dev)
428 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
429 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
431 struct vf_cmd_info args;
434 args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
436 args.in_args_size = 0;
437 args.out_buffer = cmd_result_buffer;
438 args.out_size = I40E_AQ_BUF_SZ;
440 err = i40evf_execute_vf_cmd(dev, &args);
443 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
447 len = sizeof(struct i40e_virtchnl_vf_resource) +
448 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
450 (void)rte_memcpy(vf->vf_res, args.out_buffer,
451 RTE_MIN(args.out_size, len));
452 i40e_vf_parse_hw_config(hw, vf->vf_res);
458 i40evf_config_promisc(struct rte_eth_dev *dev,
460 bool enable_multicast)
462 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
464 struct vf_cmd_info args;
465 struct i40e_virtchnl_promisc_info promisc;
468 promisc.vsi_id = vf->vsi_res->vsi_id;
471 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
473 if (enable_multicast)
474 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
476 args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
477 args.in_args = (uint8_t *)&promisc;
478 args.in_args_size = sizeof(promisc);
479 args.out_buffer = cmd_result_buffer;
480 args.out_size = I40E_AQ_BUF_SZ;
482 err = i40evf_execute_vf_cmd(dev, &args);
485 PMD_DRV_LOG(ERR, "fail to execute command "
486 "CONFIG_PROMISCUOUS_MODE");
490 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
492 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
493 bool enable_vlan_strip)
495 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
497 struct vf_cmd_info args;
498 struct i40e_virtchnl_vlan_offload_info offload;
500 offload.vsi_id = vf->vsi_res->vsi_id;
501 offload.enable_vlan_strip = enable_vlan_strip;
503 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
504 args.in_args = (uint8_t *)&offload;
505 args.in_args_size = sizeof(offload);
506 args.out_buffer = cmd_result_buffer;
507 args.out_size = I40E_AQ_BUF_SZ;
509 err = i40evf_execute_vf_cmd(dev, &args);
511 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
517 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
518 struct i40e_vsi_vlan_pvid_info *info)
520 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
522 struct vf_cmd_info args;
523 struct i40e_virtchnl_pvid_info tpid_info;
525 if (dev == NULL || info == NULL) {
526 PMD_DRV_LOG(ERR, "invalid parameters");
527 return I40E_ERR_PARAM;
530 memset(&tpid_info, 0, sizeof(tpid_info));
531 tpid_info.vsi_id = vf->vsi_res->vsi_id;
532 (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
534 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
535 args.in_args = (uint8_t *)&tpid_info;
536 args.in_args_size = sizeof(tpid_info);
537 args.out_buffer = cmd_result_buffer;
538 args.out_size = I40E_AQ_BUF_SZ;
540 err = i40evf_execute_vf_cmd(dev, &args);
542 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
548 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
552 struct i40e_tx_queue *txq)
554 txq_info->vsi_id = vsi_id;
555 txq_info->queue_id = queue_id;
556 if (queue_id < nb_txq) {
557 txq_info->ring_len = txq->nb_tx_desc;
558 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
563 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
567 uint32_t max_pkt_size,
568 struct i40e_rx_queue *rxq)
570 rxq_info->vsi_id = vsi_id;
571 rxq_info->queue_id = queue_id;
572 rxq_info->max_pkt_size = max_pkt_size;
573 if (queue_id < nb_rxq) {
574 rxq_info->ring_len = rxq->nb_rx_desc;
575 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
576 rxq_info->databuffer_size =
577 (rte_pktmbuf_data_room_size(rxq->mp) -
578 RTE_PKTMBUF_HEADROOM);
582 /* It configures VSI queues to co-work with Linux PF host */
584 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
586 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
587 struct i40e_rx_queue **rxq =
588 (struct i40e_rx_queue **)dev->data->rx_queues;
589 struct i40e_tx_queue **txq =
590 (struct i40e_tx_queue **)dev->data->tx_queues;
591 struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
592 struct i40e_virtchnl_queue_pair_info *vc_qpi;
593 struct vf_cmd_info args;
594 uint16_t i, nb_qp = vf->num_queue_pairs;
595 const uint32_t size =
596 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
600 memset(buff, 0, sizeof(buff));
601 vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
602 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
603 vc_vqci->num_queue_pairs = nb_qp;
605 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
606 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
607 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
608 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
609 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
610 vf->max_pkt_len, rxq[i]);
612 memset(&args, 0, sizeof(args));
613 args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
614 args.in_args = (uint8_t *)vc_vqci;
615 args.in_args_size = size;
616 args.out_buffer = cmd_result_buffer;
617 args.out_size = I40E_AQ_BUF_SZ;
618 ret = i40evf_execute_vf_cmd(dev, &args);
620 PMD_DRV_LOG(ERR, "Failed to execute command of "
621 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
626 /* It configures VSI queues to co-work with DPDK PF host */
628 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
630 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
631 struct i40e_rx_queue **rxq =
632 (struct i40e_rx_queue **)dev->data->rx_queues;
633 struct i40e_tx_queue **txq =
634 (struct i40e_tx_queue **)dev->data->tx_queues;
635 struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
636 struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
637 struct vf_cmd_info args;
638 uint16_t i, nb_qp = vf->num_queue_pairs;
639 const uint32_t size =
640 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
644 memset(buff, 0, sizeof(buff));
645 vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
646 vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
647 vc_vqcei->num_queue_pairs = nb_qp;
648 vc_qpei = vc_vqcei->qpair;
649 for (i = 0; i < nb_qp; i++, vc_qpei++) {
650 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
651 vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
652 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
653 vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
654 vf->max_pkt_len, rxq[i]);
655 if (i < dev->data->nb_rx_queues)
657 * It adds extra info for configuring VSI queues, which
658 * is needed to enable the configurable crc stripping
661 vc_qpei->rxq_ext.crcstrip =
662 dev->data->dev_conf.rxmode.hw_strip_crc;
664 memset(&args, 0, sizeof(args));
666 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
667 args.in_args = (uint8_t *)vc_vqcei;
668 args.in_args_size = size;
669 args.out_buffer = cmd_result_buffer;
670 args.out_size = I40E_AQ_BUF_SZ;
671 ret = i40evf_execute_vf_cmd(dev, &args);
673 PMD_DRV_LOG(ERR, "Failed to execute command of "
674 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
680 i40evf_configure_queues(struct rte_eth_dev *dev)
682 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
684 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
685 /* To support DPDK PF host */
686 return i40evf_configure_vsi_queues_ext(dev);
688 /* To support Linux PF host */
689 return i40evf_configure_vsi_queues(dev);
693 i40evf_config_irq_map(struct rte_eth_dev *dev)
695 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
696 struct vf_cmd_info args;
697 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
698 sizeof(struct i40e_virtchnl_vector_map)];
699 struct i40e_virtchnl_irq_map_info *map_info;
701 map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
702 map_info->num_vectors = 1;
703 map_info->vecmap[0].rxitr_idx = RTE_LIBRTE_I40E_ITR_INTERVAL / 2;
704 map_info->vecmap[0].txitr_idx = RTE_LIBRTE_I40E_ITR_INTERVAL / 2;
705 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
706 /* Alway use default dynamic MSIX interrupt */
707 map_info->vecmap[0].vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
708 /* Don't map any tx queue */
709 map_info->vecmap[0].txq_map = 0;
710 map_info->vecmap[0].rxq_map = 0;
711 for (i = 0; i < dev->data->nb_rx_queues; i++)
712 map_info->vecmap[0].rxq_map |= 1 << i;
714 args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
715 args.in_args = (u8 *)cmd_buffer;
716 args.in_args_size = sizeof(cmd_buffer);
717 args.out_buffer = cmd_result_buffer;
718 args.out_size = I40E_AQ_BUF_SZ;
719 err = i40evf_execute_vf_cmd(dev, &args);
721 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
727 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
730 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
731 struct i40e_virtchnl_queue_select queue_select;
733 struct vf_cmd_info args;
734 memset(&queue_select, 0, sizeof(queue_select));
735 queue_select.vsi_id = vf->vsi_res->vsi_id;
738 queue_select.rx_queues |= 1 << qid;
740 queue_select.tx_queues |= 1 << qid;
743 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
745 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
746 args.in_args = (u8 *)&queue_select;
747 args.in_args_size = sizeof(queue_select);
748 args.out_buffer = cmd_result_buffer;
749 args.out_size = I40E_AQ_BUF_SZ;
750 err = i40evf_execute_vf_cmd(dev, &args);
752 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
753 isrx ? "RX" : "TX", qid, on ? "on" : "off");
759 i40evf_start_queues(struct rte_eth_dev *dev)
761 struct rte_eth_dev_data *dev_data = dev->data;
763 struct i40e_rx_queue *rxq;
764 struct i40e_tx_queue *txq;
766 for (i = 0; i < dev->data->nb_rx_queues; i++) {
767 rxq = dev_data->rx_queues[i];
768 if (rxq->rx_deferred_start)
770 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
771 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
776 for (i = 0; i < dev->data->nb_tx_queues; i++) {
777 txq = dev_data->tx_queues[i];
778 if (txq->tx_deferred_start)
780 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
781 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
790 i40evf_stop_queues(struct rte_eth_dev *dev)
794 /* Stop TX queues first */
795 for (i = 0; i < dev->data->nb_tx_queues; i++) {
796 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
797 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
802 /* Then stop RX queues */
803 for (i = 0; i < dev->data->nb_rx_queues; i++) {
804 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
805 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
814 i40evf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
816 struct i40e_virtchnl_ether_addr_list *list;
817 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
818 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
819 sizeof(struct i40e_virtchnl_ether_addr)];
821 struct vf_cmd_info args;
823 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
824 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
825 addr->addr_bytes[0], addr->addr_bytes[1],
826 addr->addr_bytes[2], addr->addr_bytes[3],
827 addr->addr_bytes[4], addr->addr_bytes[5]);
831 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
832 list->vsi_id = vf->vsi_res->vsi_id;
833 list->num_elements = 1;
834 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
835 sizeof(addr->addr_bytes));
837 args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
838 args.in_args = cmd_buffer;
839 args.in_args_size = sizeof(cmd_buffer);
840 args.out_buffer = cmd_result_buffer;
841 args.out_size = I40E_AQ_BUF_SZ;
842 err = i40evf_execute_vf_cmd(dev, &args);
844 PMD_DRV_LOG(ERR, "fail to execute command "
845 "OP_ADD_ETHER_ADDRESS");
851 i40evf_del_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
853 struct i40e_virtchnl_ether_addr_list *list;
854 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
855 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
856 sizeof(struct i40e_virtchnl_ether_addr)];
858 struct vf_cmd_info args;
860 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
861 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
862 addr->addr_bytes[0], addr->addr_bytes[1],
863 addr->addr_bytes[2], addr->addr_bytes[3],
864 addr->addr_bytes[4], addr->addr_bytes[5]);
868 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
869 list->vsi_id = vf->vsi_res->vsi_id;
870 list->num_elements = 1;
871 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
872 sizeof(addr->addr_bytes));
874 args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
875 args.in_args = cmd_buffer;
876 args.in_args_size = sizeof(cmd_buffer);
877 args.out_buffer = cmd_result_buffer;
878 args.out_size = I40E_AQ_BUF_SZ;
879 err = i40evf_execute_vf_cmd(dev, &args);
881 PMD_DRV_LOG(ERR, "fail to execute command "
882 "OP_DEL_ETHER_ADDRESS");
888 i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
890 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
891 struct i40e_virtchnl_queue_select q_stats;
892 struct i40e_eth_stats *pstats;
894 struct vf_cmd_info args;
896 memset(&q_stats, 0, sizeof(q_stats));
897 q_stats.vsi_id = vf->vsi_res->vsi_id;
898 args.ops = I40E_VIRTCHNL_OP_GET_STATS;
899 args.in_args = (u8 *)&q_stats;
900 args.in_args_size = sizeof(q_stats);
901 args.out_buffer = cmd_result_buffer;
902 args.out_size = I40E_AQ_BUF_SZ;
904 err = i40evf_execute_vf_cmd(dev, &args);
906 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
909 pstats = (struct i40e_eth_stats *)args.out_buffer;
910 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
911 pstats->rx_broadcast;
912 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
914 stats->ierrors = pstats->rx_discards;
915 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
916 stats->ibytes = pstats->rx_bytes;
917 stats->obytes = pstats->tx_bytes;
923 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
925 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
926 struct i40e_virtchnl_vlan_filter_list *vlan_list;
927 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
930 struct vf_cmd_info args;
932 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
933 vlan_list->vsi_id = vf->vsi_res->vsi_id;
934 vlan_list->num_elements = 1;
935 vlan_list->vlan_id[0] = vlanid;
937 args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
938 args.in_args = (u8 *)&cmd_buffer;
939 args.in_args_size = sizeof(cmd_buffer);
940 args.out_buffer = cmd_result_buffer;
941 args.out_size = I40E_AQ_BUF_SZ;
942 err = i40evf_execute_vf_cmd(dev, &args);
944 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
950 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
952 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
953 struct i40e_virtchnl_vlan_filter_list *vlan_list;
954 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
957 struct vf_cmd_info args;
959 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
960 vlan_list->vsi_id = vf->vsi_res->vsi_id;
961 vlan_list->num_elements = 1;
962 vlan_list->vlan_id[0] = vlanid;
964 args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
965 args.in_args = (u8 *)&cmd_buffer;
966 args.in_args_size = sizeof(cmd_buffer);
967 args.out_buffer = cmd_result_buffer;
968 args.out_size = I40E_AQ_BUF_SZ;
969 err = i40evf_execute_vf_cmd(dev, &args);
971 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
977 i40evf_get_link_status(struct rte_eth_dev *dev, struct rte_eth_link *link)
980 struct vf_cmd_info args;
981 struct rte_eth_link *new_link;
983 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_GET_LINK_STAT;
985 args.in_args_size = 0;
986 args.out_buffer = cmd_result_buffer;
987 args.out_size = I40E_AQ_BUF_SZ;
988 err = i40evf_execute_vf_cmd(dev, &args);
990 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_LINK_STAT");
994 new_link = (struct rte_eth_link *)args.out_buffer;
995 (void)rte_memcpy(link, new_link, sizeof(*link));
1000 static const struct rte_pci_id pci_id_i40evf_map[] = {
1001 #define RTE_PCI_DEV_ID_DECL_I40EVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
1002 #include "rte_pci_dev_ids.h"
1003 { .vendor_id = 0, /* sentinel */ },
1007 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1008 struct rte_eth_link *link)
1010 struct rte_eth_link *dst = &(dev->data->dev_link);
1011 struct rte_eth_link *src = link;
1013 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1014 *(uint64_t *)src) == 0)
1021 i40evf_reset_vf(struct i40e_hw *hw)
1025 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1026 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1030 * After issuing vf reset command to pf, pf won't necessarily
1031 * reset vf, it depends on what state it exactly is. If it's not
1032 * initialized yet, it won't have vf reset since it's in a certain
1033 * state. If not, it will try to reset. Even vf is reset, pf will
1034 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1035 * it to ACTIVE. In this duration, vf may not catch the moment that
1036 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1040 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1041 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1042 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1043 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1044 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1050 if (i >= MAX_RESET_WAIT_CNT) {
1051 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1059 i40evf_init_vf(struct rte_eth_dev *dev)
1062 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1063 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1065 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1066 vf->dev_data = dev->data;
1067 err = i40evf_set_mac_type(hw);
1069 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1073 i40e_init_adminq_parameter(hw);
1074 err = i40e_init_adminq(hw);
1076 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1081 /* Reset VF and wait until it's complete */
1082 if (i40evf_reset_vf(hw)) {
1083 PMD_INIT_LOG(ERR, "reset NIC failed");
1087 /* VF reset, shutdown admin queue and initialize again */
1088 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1089 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1093 i40e_init_adminq_parameter(hw);
1094 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1095 PMD_INIT_LOG(ERR, "init_adminq failed");
1098 if (i40evf_check_api_version(dev) != 0) {
1099 PMD_INIT_LOG(ERR, "check_api version failed");
1102 bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1103 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1104 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1106 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1110 if (i40evf_get_vf_resource(dev) != 0) {
1111 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1115 /* got VF config message back from PF, now we can parse it */
1116 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1117 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1118 vf->vsi_res = &vf->vf_res->vsi_res[i];
1122 PMD_INIT_LOG(ERR, "no LAN VSI found");
1126 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1127 vf->vsi.type = vf->vsi_res->vsi_type;
1128 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1130 /* check mac addr, if it's not valid, genrate one */
1131 if (I40E_SUCCESS != i40e_validate_mac_addr(\
1132 vf->vsi_res->default_mac_addr))
1133 eth_random_addr(vf->vsi_res->default_mac_addr);
1135 ether_addr_copy((struct ether_addr *)vf->vsi_res->default_mac_addr,
1136 (struct ether_addr *)hw->mac.addr);
1141 rte_free(vf->vf_res);
1143 i40e_shutdown_adminq(hw); /* ignore error */
1149 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1151 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(\
1152 eth_dev->data->dev_private);
1154 PMD_INIT_FUNC_TRACE();
1156 /* assign ops func pointer */
1157 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1158 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1159 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1162 * For secondary processes, we don't initialise any further as primary
1163 * has already done this work.
1165 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1166 if (eth_dev->data->scattered_rx)
1167 eth_dev->rx_pkt_burst = i40e_recv_scattered_pkts;
1171 hw->vendor_id = eth_dev->pci_dev->id.vendor_id;
1172 hw->device_id = eth_dev->pci_dev->id.device_id;
1173 hw->subsystem_vendor_id = eth_dev->pci_dev->id.subsystem_vendor_id;
1174 hw->subsystem_device_id = eth_dev->pci_dev->id.subsystem_device_id;
1175 hw->bus.device = eth_dev->pci_dev->addr.devid;
1176 hw->bus.func = eth_dev->pci_dev->addr.function;
1177 hw->hw_addr = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1179 if(i40evf_init_vf(eth_dev) != 0) {
1180 PMD_INIT_LOG(ERR, "Init vf failed");
1185 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1187 if (eth_dev->data->mac_addrs == NULL) {
1188 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
1189 "store MAC addresses", ETHER_ADDR_LEN);
1192 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1193 (struct ether_addr *)eth_dev->data->mac_addrs);
1199 * virtual function driver struct
1201 static struct eth_driver rte_i40evf_pmd = {
1203 .name = "rte_i40evf_pmd",
1204 .id_table = pci_id_i40evf_map,
1205 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1207 .eth_dev_init = i40evf_dev_init,
1208 .dev_private_size = sizeof(struct i40e_vf),
1212 * VF Driver initialization routine.
1213 * Invoked one at EAL init time.
1214 * Register itself as the [Virtual Poll Mode] Driver of PCI Fortville devices.
1217 rte_i40evf_pmd_init(const char *name __rte_unused,
1218 const char *params __rte_unused)
1220 PMD_INIT_FUNC_TRACE();
1222 rte_eth_driver_register(&rte_i40evf_pmd);
1227 static struct rte_driver rte_i40evf_driver = {
1229 .init = rte_i40evf_pmd_init,
1232 PMD_REGISTER_DRIVER(rte_i40evf_driver);
1235 i40evf_dev_configure(struct rte_eth_dev *dev)
1237 return i40evf_init_vlan(dev);
1241 i40evf_init_vlan(struct rte_eth_dev *dev)
1243 struct rte_eth_dev_data *data = dev->data;
1246 /* Apply vlan offload setting */
1247 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1249 /* Apply pvid setting */
1250 ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1251 data->dev_conf.txmode.hw_vlan_insert_pvid);
1256 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1258 bool enable_vlan_strip = 0;
1259 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1260 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1262 /* Linux pf host doesn't support vlan offload yet */
1263 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1264 /* Vlan stripping setting */
1265 if (mask & ETH_VLAN_STRIP_MASK) {
1266 /* Enable or disable VLAN stripping */
1267 if (dev_conf->rxmode.hw_vlan_strip)
1268 enable_vlan_strip = 1;
1270 enable_vlan_strip = 0;
1272 i40evf_config_vlan_offload(dev, enable_vlan_strip);
1278 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1280 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1281 struct i40e_vsi_vlan_pvid_info info;
1282 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1284 memset(&info, 0, sizeof(info));
1287 /* Linux pf host don't support vlan offload yet */
1288 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1290 info.config.pvid = pvid;
1292 info.config.reject.tagged =
1293 dev_conf->txmode.hw_vlan_reject_tagged;
1294 info.config.reject.untagged =
1295 dev_conf->txmode.hw_vlan_reject_untagged;
1297 return i40evf_config_vlan_pvid(dev, &info);
1304 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1306 struct i40e_rx_queue *rxq;
1308 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1310 PMD_INIT_FUNC_TRACE();
1312 if (rx_queue_id < dev->data->nb_rx_queues) {
1313 rxq = dev->data->rx_queues[rx_queue_id];
1315 err = i40e_alloc_rx_queue_mbufs(rxq);
1317 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1323 /* Init the RX tail register. */
1324 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1325 I40EVF_WRITE_FLUSH(hw);
1327 /* Ready to switch the queue on */
1328 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1331 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1339 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1341 struct i40e_rx_queue *rxq;
1344 if (rx_queue_id < dev->data->nb_rx_queues) {
1345 rxq = dev->data->rx_queues[rx_queue_id];
1347 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1350 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1355 i40e_rx_queue_release_mbufs(rxq);
1356 i40e_reset_rx_queue(rxq);
1363 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1367 PMD_INIT_FUNC_TRACE();
1369 if (tx_queue_id < dev->data->nb_tx_queues) {
1371 /* Ready to switch the queue on */
1372 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1375 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1383 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1385 struct i40e_tx_queue *txq;
1388 if (tx_queue_id < dev->data->nb_tx_queues) {
1389 txq = dev->data->tx_queues[tx_queue_id];
1391 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1394 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1399 i40e_tx_queue_release_mbufs(txq);
1400 i40e_reset_tx_queue(txq);
1407 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1412 ret = i40evf_add_vlan(dev, vlan_id);
1414 ret = i40evf_del_vlan(dev,vlan_id);
1420 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1422 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1423 struct rte_eth_dev_data *dev_data = dev->data;
1424 struct rte_pktmbuf_pool_private *mbp_priv;
1425 uint16_t buf_size, len;
1427 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1428 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1429 I40EVF_WRITE_FLUSH(hw);
1431 /* Calculate the maximum packet length allowed */
1432 mbp_priv = rte_mempool_get_priv(rxq->mp);
1433 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1434 RTE_PKTMBUF_HEADROOM);
1435 rxq->hs_mode = i40e_header_split_none;
1436 rxq->rx_hdr_len = 0;
1437 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1438 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1439 rxq->max_pkt_len = RTE_MIN(len,
1440 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1443 * Check if the jumbo frame and maximum packet length are set correctly
1445 if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1446 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1447 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1448 PMD_DRV_LOG(ERR, "maximum packet length must be "
1449 "larger than %u and smaller than %u, as jumbo "
1450 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1451 (uint32_t)I40E_FRAME_SIZE_MAX);
1452 return I40E_ERR_CONFIG;
1455 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1456 rxq->max_pkt_len > ETHER_MAX_LEN) {
1457 PMD_DRV_LOG(ERR, "maximum packet length must be "
1458 "larger than %u and smaller than %u, as jumbo "
1459 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1460 (uint32_t)ETHER_MAX_LEN);
1461 return I40E_ERR_CONFIG;
1465 if (dev_data->dev_conf.rxmode.enable_scatter ||
1466 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1467 dev_data->scattered_rx = 1;
1468 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
1475 i40evf_rx_init(struct rte_eth_dev *dev)
1477 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1479 struct i40e_rx_queue **rxq =
1480 (struct i40e_rx_queue **)dev->data->rx_queues;
1482 i40evf_config_rss(vf);
1483 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1484 if (i40evf_rxq_init(dev, rxq[i]) < 0)
1492 i40evf_tx_init(struct rte_eth_dev *dev)
1495 struct i40e_tx_queue **txq =
1496 (struct i40e_tx_queue **)dev->data->tx_queues;
1497 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1499 for (i = 0; i < dev->data->nb_tx_queues; i++)
1500 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1504 i40evf_enable_queues_intr(struct i40e_hw *hw)
1506 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1507 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1508 I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1512 i40evf_disable_queues_intr(struct i40e_hw *hw)
1514 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1519 i40evf_dev_start(struct rte_eth_dev *dev)
1521 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1522 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1523 struct ether_addr mac_addr;
1525 PMD_INIT_FUNC_TRACE();
1527 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1528 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1529 dev->data->nb_tx_queues);
1531 if (i40evf_rx_init(dev) != 0){
1532 PMD_DRV_LOG(ERR, "failed to do RX init");
1536 i40evf_tx_init(dev);
1538 if (i40evf_configure_queues(dev) != 0) {
1539 PMD_DRV_LOG(ERR, "configure queues failed");
1542 if (i40evf_config_irq_map(dev)) {
1543 PMD_DRV_LOG(ERR, "config_irq_map failed");
1548 (void)rte_memcpy(mac_addr.addr_bytes, hw->mac.addr,
1549 sizeof(mac_addr.addr_bytes));
1550 if (i40evf_add_mac_addr(dev, &mac_addr)) {
1551 PMD_DRV_LOG(ERR, "Failed to add mac addr");
1555 if (i40evf_start_queues(dev) != 0) {
1556 PMD_DRV_LOG(ERR, "enable queues failed");
1560 i40evf_enable_queues_intr(hw);
1564 i40evf_del_mac_addr(dev, &mac_addr);
1570 i40evf_dev_stop(struct rte_eth_dev *dev)
1572 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1574 PMD_INIT_FUNC_TRACE();
1576 i40evf_disable_queues_intr(hw);
1577 i40evf_stop_queues(dev);
1581 i40evf_dev_link_update(struct rte_eth_dev *dev,
1582 __rte_unused int wait_to_complete)
1584 struct rte_eth_link new_link;
1585 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1587 * DPDK pf host provide interfacet to acquire link status
1588 * while Linux driver does not
1590 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1591 i40evf_get_link_status(dev, &new_link);
1593 /* Always assume it's up, for Linux driver PF host */
1594 new_link.link_duplex = ETH_LINK_AUTONEG_DUPLEX;
1595 new_link.link_speed = ETH_LINK_SPEED_10000;
1596 new_link.link_status = 1;
1598 i40evf_dev_atomic_write_link_status(dev, &new_link);
1604 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
1606 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1609 /* If enabled, just return */
1610 if (vf->promisc_unicast_enabled)
1613 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
1615 vf->promisc_unicast_enabled = TRUE;
1619 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
1621 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1624 /* If disabled, just return */
1625 if (!vf->promisc_unicast_enabled)
1628 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
1630 vf->promisc_unicast_enabled = FALSE;
1634 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
1636 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1639 /* If enabled, just return */
1640 if (vf->promisc_multicast_enabled)
1643 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
1645 vf->promisc_multicast_enabled = TRUE;
1649 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
1651 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1654 /* If enabled, just return */
1655 if (!vf->promisc_multicast_enabled)
1658 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
1660 vf->promisc_multicast_enabled = FALSE;
1664 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1666 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1668 memset(dev_info, 0, sizeof(*dev_info));
1669 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
1670 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
1671 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1672 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1673 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
1674 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1675 dev_info->rx_offload_capa =
1676 DEV_RX_OFFLOAD_VLAN_STRIP |
1677 DEV_RX_OFFLOAD_QINQ_STRIP |
1678 DEV_RX_OFFLOAD_IPV4_CKSUM |
1679 DEV_RX_OFFLOAD_UDP_CKSUM |
1680 DEV_RX_OFFLOAD_TCP_CKSUM;
1681 dev_info->tx_offload_capa =
1682 DEV_TX_OFFLOAD_VLAN_INSERT |
1683 DEV_TX_OFFLOAD_QINQ_INSERT |
1684 DEV_TX_OFFLOAD_IPV4_CKSUM |
1685 DEV_TX_OFFLOAD_UDP_CKSUM |
1686 DEV_TX_OFFLOAD_TCP_CKSUM |
1687 DEV_TX_OFFLOAD_SCTP_CKSUM;
1689 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1691 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1692 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1693 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1695 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1699 dev_info->default_txconf = (struct rte_eth_txconf) {
1701 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1702 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1703 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1705 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1706 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1707 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1708 ETH_TXQ_FLAGS_NOOFFLOADS,
1713 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1715 if (i40evf_get_statics(dev, stats))
1716 PMD_DRV_LOG(ERR, "Get statics failed");
1720 i40evf_dev_close(struct rte_eth_dev *dev)
1722 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1724 i40evf_dev_stop(dev);
1725 i40evf_reset_vf(hw);
1726 i40e_shutdown_adminq(hw);
1730 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
1731 struct rte_eth_rss_reta_entry64 *reta_conf,
1734 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737 uint16_t idx, shift;
1740 if (reta_size != ETH_RSS_RETA_SIZE_64) {
1741 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1742 "(%d) doesn't match the number of hardware can "
1743 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
1747 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1748 idx = i / RTE_RETA_GROUP_SIZE;
1749 shift = i % RTE_RETA_GROUP_SIZE;
1750 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1754 if (mask == I40E_4_BIT_MASK)
1757 l = I40E_READ_REG(hw, I40E_VFQF_HLUT(i >> 2));
1759 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1760 if (mask & (0x1 << j))
1761 lut |= reta_conf[idx].reta[shift + j] <<
1764 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1766 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
1773 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
1774 struct rte_eth_rss_reta_entry64 *reta_conf,
1777 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1780 uint16_t idx, shift;
1783 if (reta_size != ETH_RSS_RETA_SIZE_64) {
1784 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1785 "(%d) doesn't match the number of hardware can "
1786 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
1790 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1791 idx = i / RTE_RETA_GROUP_SIZE;
1792 shift = i % RTE_RETA_GROUP_SIZE;
1793 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1798 lut = I40E_READ_REG(hw, I40E_VFQF_HLUT(i >> 2));
1799 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1800 if (mask & (0x1 << j))
1801 reta_conf[idx].reta[shift + j] =
1802 ((lut >> (CHAR_BIT * j)) &
1811 i40evf_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
1814 uint8_t hash_key_len;
1815 uint64_t rss_hf, hena;
1817 hash_key = (uint32_t *)(rss_conf->rss_key);
1818 hash_key_len = rss_conf->rss_key_len;
1819 if (hash_key != NULL && hash_key_len >=
1820 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
1823 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
1824 I40E_WRITE_REG(hw, I40E_VFQF_HKEY(i), hash_key[i]);
1827 rss_hf = rss_conf->rss_hf;
1828 hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));
1829 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;
1830 hena &= ~I40E_RSS_HENA_ALL;
1831 hena |= i40e_config_hena(rss_hf);
1832 I40E_WRITE_REG(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
1833 I40E_WRITE_REG(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
1834 I40EVF_WRITE_FLUSH(hw);
1840 i40evf_disable_rss(struct i40e_vf *vf)
1842 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
1845 hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));
1846 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;
1847 hena &= ~I40E_RSS_HENA_ALL;
1848 I40E_WRITE_REG(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
1849 I40E_WRITE_REG(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
1850 I40EVF_WRITE_FLUSH(hw);
1854 i40evf_config_rss(struct i40e_vf *vf)
1856 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
1857 struct rte_eth_rss_conf rss_conf;
1858 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
1860 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
1861 i40evf_disable_rss(vf);
1862 PMD_DRV_LOG(DEBUG, "RSS not configured\n");
1866 /* Fill out the look up table */
1867 for (i = 0, j = 0; i < nb_q; i++, j++) {
1868 if (j >= vf->num_queue_pairs)
1870 lut = (lut << 8) | j;
1872 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
1875 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
1876 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
1877 i40evf_disable_rss(vf);
1878 PMD_DRV_LOG(DEBUG, "No hash flag is set\n");
1882 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len < nb_q) {
1883 /* Calculate the default hash key */
1884 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
1885 rss_key_default[i] = (uint32_t)rte_rand();
1886 rss_conf.rss_key = (uint8_t *)rss_key_default;
1887 rss_conf.rss_key_len = nb_q;
1890 return i40evf_hw_rss_hash_set(hw, &rss_conf);
1894 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
1895 struct rte_eth_rss_conf *rss_conf)
1897 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1898 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
1901 hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));
1902 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;
1903 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
1904 if (rss_hf != 0) /* Enable RSS */
1910 if (rss_hf == 0) /* Disable RSS */
1913 return i40evf_hw_rss_hash_set(hw, rss_conf);
1917 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1918 struct rte_eth_rss_conf *rss_conf)
1920 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1921 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
1926 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
1927 hash_key[i] = I40E_READ_REG(hw, I40E_VFQF_HKEY(i));
1928 rss_conf->rss_key_len = i * sizeof(uint32_t);
1930 hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));
1931 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;
1932 rss_conf->rss_hf = i40e_parse_hena(hena);