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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
55 #include <rte_alarm.h>
56 #include <rte_ether.h>
57 #include <rte_ethdev.h>
58 #include <rte_ethdev_pci.h>
59 #include <rte_malloc.h>
62 #include "i40e_logs.h"
63 #include "base/i40e_prototype.h"
64 #include "base/i40e_adminq_cmd.h"
65 #include "base/i40e_type.h"
67 #include "i40e_rxtx.h"
68 #include "i40e_ethdev.h"
70 #define I40EVF_VSI_DEFAULT_MSIX_INTR 1
71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
73 /* busy wait delay in msec */
74 #define I40EVF_BUSY_WAIT_DELAY 10
75 #define I40EVF_BUSY_WAIT_COUNT 50
76 #define MAX_RESET_WAIT_CNT 20
78 struct i40evf_arq_msg_info {
79 enum virtchnl_ops ops;
80 enum i40e_status_code result;
87 enum virtchnl_ops ops;
89 uint32_t in_args_size;
91 /* Input & output type. pass in buffer size and pass out
92 * actual return result
97 enum i40evf_aq_result {
98 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
99 I40EVF_MSG_NON, /* Read nothing from admin queue */
100 I40EVF_MSG_SYS, /* Read system msg from admin queue */
101 I40EVF_MSG_CMD, /* Read async command result */
104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
105 static int i40evf_dev_start(struct rte_eth_dev *dev);
106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
108 struct rte_eth_dev_info *dev_info);
109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
110 int wait_to_complete);
111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
112 struct rte_eth_stats *stats);
113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
114 struct rte_eth_xstat *xstats, unsigned n);
115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
116 struct rte_eth_xstat_name *xstats_names,
118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
120 uint16_t vlan_id, int on);
121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
122 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
124 static void i40evf_dev_close(struct rte_eth_dev *dev);
125 static int i40evf_dev_reset(struct rte_eth_dev *dev);
126 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
127 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
128 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
129 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
130 static int i40evf_init_vlan(struct rte_eth_dev *dev);
131 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
132 uint16_t rx_queue_id);
133 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
134 uint16_t rx_queue_id);
135 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
136 uint16_t tx_queue_id);
137 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
138 uint16_t tx_queue_id);
139 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
140 struct ether_addr *addr,
143 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
144 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
145 struct rte_eth_rss_reta_entry64 *reta_conf,
147 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
148 struct rte_eth_rss_reta_entry64 *reta_conf,
150 static int i40evf_config_rss(struct i40e_vf *vf);
151 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
152 struct rte_eth_rss_conf *rss_conf);
153 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
154 struct rte_eth_rss_conf *rss_conf);
155 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
156 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
157 struct ether_addr *mac_addr);
159 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
161 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
162 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
166 /* Default hash key buffer for RSS */
167 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
169 struct rte_i40evf_xstats_name_off {
170 char name[RTE_ETH_XSTATS_NAME_SIZE];
174 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
175 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
176 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
177 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
178 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
179 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
180 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
181 rx_unknown_protocol)},
182 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
183 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
184 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
185 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
186 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
187 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
190 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
191 sizeof(rte_i40evf_stats_strings[0]))
193 static const struct eth_dev_ops i40evf_eth_dev_ops = {
194 .dev_configure = i40evf_dev_configure,
195 .dev_start = i40evf_dev_start,
196 .dev_stop = i40evf_dev_stop,
197 .promiscuous_enable = i40evf_dev_promiscuous_enable,
198 .promiscuous_disable = i40evf_dev_promiscuous_disable,
199 .allmulticast_enable = i40evf_dev_allmulticast_enable,
200 .allmulticast_disable = i40evf_dev_allmulticast_disable,
201 .link_update = i40evf_dev_link_update,
202 .stats_get = i40evf_dev_stats_get,
203 .xstats_get = i40evf_dev_xstats_get,
204 .xstats_get_names = i40evf_dev_xstats_get_names,
205 .xstats_reset = i40evf_dev_xstats_reset,
206 .dev_close = i40evf_dev_close,
207 .dev_reset = i40evf_dev_reset,
208 .dev_infos_get = i40evf_dev_info_get,
209 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
210 .vlan_filter_set = i40evf_vlan_filter_set,
211 .vlan_offload_set = i40evf_vlan_offload_set,
212 .vlan_pvid_set = i40evf_vlan_pvid_set,
213 .rx_queue_start = i40evf_dev_rx_queue_start,
214 .rx_queue_stop = i40evf_dev_rx_queue_stop,
215 .tx_queue_start = i40evf_dev_tx_queue_start,
216 .tx_queue_stop = i40evf_dev_tx_queue_stop,
217 .rx_queue_setup = i40e_dev_rx_queue_setup,
218 .rx_queue_release = i40e_dev_rx_queue_release,
219 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
220 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
221 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
222 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
223 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
224 .tx_queue_setup = i40e_dev_tx_queue_setup,
225 .tx_queue_release = i40e_dev_tx_queue_release,
226 .rx_queue_count = i40e_dev_rx_queue_count,
227 .rxq_info_get = i40e_rxq_info_get,
228 .txq_info_get = i40e_txq_info_get,
229 .mac_addr_add = i40evf_add_mac_addr,
230 .mac_addr_remove = i40evf_del_mac_addr,
231 .reta_update = i40evf_dev_rss_reta_update,
232 .reta_query = i40evf_dev_rss_reta_query,
233 .rss_hash_update = i40evf_dev_rss_hash_update,
234 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
235 .mtu_set = i40evf_dev_mtu_set,
236 .mac_addr_set = i40evf_set_default_mac_addr,
240 * Read data in admin queue to get msg from pf driver
242 static enum i40evf_aq_result
243 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
245 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
246 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
247 struct i40e_arq_event_info event;
248 enum virtchnl_ops opcode;
249 enum i40e_status_code retval;
251 enum i40evf_aq_result result = I40EVF_MSG_NON;
253 event.buf_len = data->buf_len;
254 event.msg_buf = data->msg;
255 ret = i40e_clean_arq_element(hw, &event, NULL);
256 /* Can't read any msg from adminQ */
258 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
259 result = I40EVF_MSG_ERR;
263 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
264 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
266 if (opcode == VIRTCHNL_OP_EVENT) {
267 struct virtchnl_pf_event *vpe =
268 (struct virtchnl_pf_event *)event.msg_buf;
270 result = I40EVF_MSG_SYS;
271 switch (vpe->event) {
272 case VIRTCHNL_EVENT_LINK_CHANGE:
274 vpe->event_data.link_event.link_status;
276 vpe->event_data.link_event.link_speed;
277 vf->pend_msg |= PFMSG_LINK_CHANGE;
278 PMD_DRV_LOG(INFO, "Link status update:%s",
279 vf->link_up ? "up" : "down");
281 case VIRTCHNL_EVENT_RESET_IMPENDING:
283 vf->pend_msg |= PFMSG_RESET_IMPENDING;
284 PMD_DRV_LOG(INFO, "vf is reseting");
286 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
287 vf->dev_closed = true;
288 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
289 PMD_DRV_LOG(INFO, "PF driver closed");
292 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
293 __func__, vpe->event);
296 /* async reply msg on command issued by vf previously */
297 result = I40EVF_MSG_CMD;
298 /* Actual data length read from PF */
299 data->msg_len = event.msg_len;
302 data->result = retval;
309 * clear current command. Only call in case execute
310 * _atomic_set_cmd successfully.
313 _clear_cmd(struct i40e_vf *vf)
316 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
320 * Check there is pending cmd in execution. If none, set new command.
323 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
325 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
326 VIRTCHNL_OP_UNKNOWN, ops);
329 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
334 #define MAX_TRY_TIMES 200
335 #define ASQ_DELAY_MS 10
338 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
340 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
341 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
342 struct i40evf_arq_msg_info info;
343 enum i40evf_aq_result ret;
346 if (_atomic_set_cmd(vf, args->ops))
349 info.msg = args->out_buffer;
350 info.buf_len = args->out_size;
351 info.ops = VIRTCHNL_OP_UNKNOWN;
352 info.result = I40E_SUCCESS;
354 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
355 args->in_args, args->in_args_size, NULL);
357 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
363 case VIRTCHNL_OP_RESET_VF:
364 /*no need to process in this function */
367 case VIRTCHNL_OP_VERSION:
368 case VIRTCHNL_OP_GET_VF_RESOURCES:
369 /* for init adminq commands, need to poll the response */
372 ret = i40evf_read_pfmsg(dev, &info);
373 vf->cmd_retval = info.result;
374 if (ret == I40EVF_MSG_CMD) {
377 } else if (ret == I40EVF_MSG_ERR)
379 rte_delay_ms(ASQ_DELAY_MS);
380 /* If don't read msg or read sys event, continue */
381 } while (i++ < MAX_TRY_TIMES);
386 /* for other adminq in running time, waiting the cmd done flag */
389 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
393 rte_delay_ms(ASQ_DELAY_MS);
394 /* If don't read msg or read sys event, continue */
395 } while (i++ < MAX_TRY_TIMES);
396 /* If there's no response is received, clear command */
397 if (i >= MAX_TRY_TIMES) {
398 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
404 return err | vf->cmd_retval;
408 * Check API version with sync wait until version read or fail from admin queue
411 i40evf_check_api_version(struct rte_eth_dev *dev)
413 struct virtchnl_version_info version, *pver;
415 struct vf_cmd_info args;
416 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
418 version.major = VIRTCHNL_VERSION_MAJOR;
419 version.minor = VIRTCHNL_VERSION_MINOR;
421 args.ops = VIRTCHNL_OP_VERSION;
422 args.in_args = (uint8_t *)&version;
423 args.in_args_size = sizeof(version);
424 args.out_buffer = vf->aq_resp;
425 args.out_size = I40E_AQ_BUF_SZ;
427 err = i40evf_execute_vf_cmd(dev, &args);
429 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
433 pver = (struct virtchnl_version_info *)args.out_buffer;
434 vf->version_major = pver->major;
435 vf->version_minor = pver->minor;
436 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
437 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
438 else if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
439 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
440 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
442 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
443 vf->version_major, vf->version_minor,
444 VIRTCHNL_VERSION_MAJOR,
445 VIRTCHNL_VERSION_MINOR);
453 i40evf_get_vf_resource(struct rte_eth_dev *dev)
455 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
456 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
458 struct vf_cmd_info args;
461 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
462 args.out_buffer = vf->aq_resp;
463 args.out_size = I40E_AQ_BUF_SZ;
465 caps = VIRTCHNL_VF_OFFLOAD_L2 |
466 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
467 VIRTCHNL_VF_OFFLOAD_RSS_REG |
468 VIRTCHNL_VF_OFFLOAD_VLAN |
469 VIRTCHNL_VF_OFFLOAD_RX_POLLING;
470 args.in_args = (uint8_t *)∩︀
471 args.in_args_size = sizeof(caps);
474 args.in_args_size = 0;
476 err = i40evf_execute_vf_cmd(dev, &args);
479 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
483 len = sizeof(struct virtchnl_vf_resource) +
484 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
486 (void)rte_memcpy(vf->vf_res, args.out_buffer,
487 RTE_MIN(args.out_size, len));
488 i40e_vf_parse_hw_config(hw, vf->vf_res);
494 i40evf_config_promisc(struct rte_eth_dev *dev,
496 bool enable_multicast)
498 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
500 struct vf_cmd_info args;
501 struct virtchnl_promisc_info promisc;
504 promisc.vsi_id = vf->vsi_res->vsi_id;
507 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
509 if (enable_multicast)
510 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
512 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
513 args.in_args = (uint8_t *)&promisc;
514 args.in_args_size = sizeof(promisc);
515 args.out_buffer = vf->aq_resp;
516 args.out_size = I40E_AQ_BUF_SZ;
518 err = i40evf_execute_vf_cmd(dev, &args);
521 PMD_DRV_LOG(ERR, "fail to execute command "
522 "CONFIG_PROMISCUOUS_MODE");
527 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
529 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
530 struct vf_cmd_info args;
533 memset(&args, 0, sizeof(args));
534 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
536 args.in_args_size = 0;
537 args.out_buffer = vf->aq_resp;
538 args.out_size = I40E_AQ_BUF_SZ;
539 ret = i40evf_execute_vf_cmd(dev, &args);
541 PMD_DRV_LOG(ERR, "Failed to execute command of "
542 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
548 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
550 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
551 struct vf_cmd_info args;
554 memset(&args, 0, sizeof(args));
555 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
557 args.in_args_size = 0;
558 args.out_buffer = vf->aq_resp;
559 args.out_size = I40E_AQ_BUF_SZ;
560 ret = i40evf_execute_vf_cmd(dev, &args);
562 PMD_DRV_LOG(ERR, "Failed to execute command of "
563 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
569 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
570 struct i40e_vsi_vlan_pvid_info *info)
572 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
574 struct vf_cmd_info args;
575 struct virtchnl_pvid_info tpid_info;
578 PMD_DRV_LOG(ERR, "invalid parameters");
579 return I40E_ERR_PARAM;
582 memset(&tpid_info, 0, sizeof(tpid_info));
583 tpid_info.vsi_id = vf->vsi_res->vsi_id;
584 (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
586 args.ops = (enum virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
587 args.in_args = (uint8_t *)&tpid_info;
588 args.in_args_size = sizeof(tpid_info);
589 args.out_buffer = vf->aq_resp;
590 args.out_size = I40E_AQ_BUF_SZ;
592 err = i40evf_execute_vf_cmd(dev, &args);
594 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
600 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
604 struct i40e_tx_queue *txq)
606 txq_info->vsi_id = vsi_id;
607 txq_info->queue_id = queue_id;
608 if (queue_id < nb_txq) {
609 txq_info->ring_len = txq->nb_tx_desc;
610 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
615 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
619 uint32_t max_pkt_size,
620 struct i40e_rx_queue *rxq)
622 rxq_info->vsi_id = vsi_id;
623 rxq_info->queue_id = queue_id;
624 rxq_info->max_pkt_size = max_pkt_size;
625 if (queue_id < nb_rxq) {
626 rxq_info->ring_len = rxq->nb_rx_desc;
627 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
628 rxq_info->databuffer_size =
629 (rte_pktmbuf_data_room_size(rxq->mp) -
630 RTE_PKTMBUF_HEADROOM);
634 /* It configures VSI queues to co-work with Linux PF host */
636 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
638 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
639 struct i40e_rx_queue **rxq =
640 (struct i40e_rx_queue **)dev->data->rx_queues;
641 struct i40e_tx_queue **txq =
642 (struct i40e_tx_queue **)dev->data->tx_queues;
643 struct virtchnl_vsi_queue_config_info *vc_vqci;
644 struct virtchnl_queue_pair_info *vc_qpi;
645 struct vf_cmd_info args;
646 uint16_t i, nb_qp = vf->num_queue_pairs;
647 const uint32_t size =
648 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
652 memset(buff, 0, sizeof(buff));
653 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
654 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
655 vc_vqci->num_queue_pairs = nb_qp;
657 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
658 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
659 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
660 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
661 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
662 vf->max_pkt_len, rxq[i]);
664 memset(&args, 0, sizeof(args));
665 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
666 args.in_args = (uint8_t *)vc_vqci;
667 args.in_args_size = size;
668 args.out_buffer = vf->aq_resp;
669 args.out_size = I40E_AQ_BUF_SZ;
670 ret = i40evf_execute_vf_cmd(dev, &args);
672 PMD_DRV_LOG(ERR, "Failed to execute command of "
673 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
678 /* It configures VSI queues to co-work with DPDK PF host */
680 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
682 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
683 struct i40e_rx_queue **rxq =
684 (struct i40e_rx_queue **)dev->data->rx_queues;
685 struct i40e_tx_queue **txq =
686 (struct i40e_tx_queue **)dev->data->tx_queues;
687 struct virtchnl_vsi_queue_config_ext_info *vc_vqcei;
688 struct virtchnl_queue_pair_ext_info *vc_qpei;
689 struct vf_cmd_info args;
690 uint16_t i, nb_qp = vf->num_queue_pairs;
691 const uint32_t size =
692 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
696 memset(buff, 0, sizeof(buff));
697 vc_vqcei = (struct virtchnl_vsi_queue_config_ext_info *)buff;
698 vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
699 vc_vqcei->num_queue_pairs = nb_qp;
700 vc_qpei = vc_vqcei->qpair;
701 for (i = 0; i < nb_qp; i++, vc_qpei++) {
702 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
703 vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
704 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
705 vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
706 vf->max_pkt_len, rxq[i]);
707 if (i < dev->data->nb_rx_queues)
709 * It adds extra info for configuring VSI queues, which
710 * is needed to enable the configurable crc stripping
713 vc_qpei->rxq_ext.crcstrip =
714 dev->data->dev_conf.rxmode.hw_strip_crc;
716 memset(&args, 0, sizeof(args));
718 (enum virtchnl_ops)VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
719 args.in_args = (uint8_t *)vc_vqcei;
720 args.in_args_size = size;
721 args.out_buffer = vf->aq_resp;
722 args.out_size = I40E_AQ_BUF_SZ;
723 ret = i40evf_execute_vf_cmd(dev, &args);
725 PMD_DRV_LOG(ERR, "Failed to execute command of "
726 "VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT");
732 i40evf_configure_queues(struct rte_eth_dev *dev)
734 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
736 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
737 /* To support DPDK PF host */
738 return i40evf_configure_vsi_queues_ext(dev);
740 /* To support Linux PF host */
741 return i40evf_configure_vsi_queues(dev);
745 i40evf_config_irq_map(struct rte_eth_dev *dev)
747 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
748 struct vf_cmd_info args;
749 uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
750 sizeof(struct virtchnl_vector_map)];
751 struct virtchnl_irq_map_info *map_info;
752 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
753 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
757 if (rte_intr_allow_others(intr_handle)) {
758 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
759 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
761 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
763 vector_id = I40E_MISC_VEC_ID;
766 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
767 map_info->num_vectors = 1;
768 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
769 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
770 /* Alway use default dynamic MSIX interrupt */
771 map_info->vecmap[0].vector_id = vector_id;
772 /* Don't map any tx queue */
773 map_info->vecmap[0].txq_map = 0;
774 map_info->vecmap[0].rxq_map = 0;
775 for (i = 0; i < dev->data->nb_rx_queues; i++) {
776 map_info->vecmap[0].rxq_map |= 1 << i;
777 if (rte_intr_dp_is_en(intr_handle))
778 intr_handle->intr_vec[i] = vector_id;
781 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
782 args.in_args = (u8 *)cmd_buffer;
783 args.in_args_size = sizeof(cmd_buffer);
784 args.out_buffer = vf->aq_resp;
785 args.out_size = I40E_AQ_BUF_SZ;
786 err = i40evf_execute_vf_cmd(dev, &args);
788 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
794 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
797 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
798 struct virtchnl_queue_select queue_select;
800 struct vf_cmd_info args;
801 memset(&queue_select, 0, sizeof(queue_select));
802 queue_select.vsi_id = vf->vsi_res->vsi_id;
805 queue_select.rx_queues |= 1 << qid;
807 queue_select.tx_queues |= 1 << qid;
810 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
812 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
813 args.in_args = (u8 *)&queue_select;
814 args.in_args_size = sizeof(queue_select);
815 args.out_buffer = vf->aq_resp;
816 args.out_size = I40E_AQ_BUF_SZ;
817 err = i40evf_execute_vf_cmd(dev, &args);
819 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
820 isrx ? "RX" : "TX", qid, on ? "on" : "off");
826 i40evf_start_queues(struct rte_eth_dev *dev)
828 struct rte_eth_dev_data *dev_data = dev->data;
830 struct i40e_rx_queue *rxq;
831 struct i40e_tx_queue *txq;
833 for (i = 0; i < dev->data->nb_rx_queues; i++) {
834 rxq = dev_data->rx_queues[i];
835 if (rxq->rx_deferred_start)
837 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
838 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
843 for (i = 0; i < dev->data->nb_tx_queues; i++) {
844 txq = dev_data->tx_queues[i];
845 if (txq->tx_deferred_start)
847 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
848 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
857 i40evf_stop_queues(struct rte_eth_dev *dev)
861 /* Stop TX queues first */
862 for (i = 0; i < dev->data->nb_tx_queues; i++) {
863 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
864 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
869 /* Then stop RX queues */
870 for (i = 0; i < dev->data->nb_rx_queues; i++) {
871 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
872 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
881 i40evf_add_mac_addr(struct rte_eth_dev *dev,
882 struct ether_addr *addr,
883 __rte_unused uint32_t index,
884 __rte_unused uint32_t pool)
886 struct virtchnl_ether_addr_list *list;
887 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
888 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
889 sizeof(struct virtchnl_ether_addr)];
891 struct vf_cmd_info args;
893 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
894 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
895 addr->addr_bytes[0], addr->addr_bytes[1],
896 addr->addr_bytes[2], addr->addr_bytes[3],
897 addr->addr_bytes[4], addr->addr_bytes[5]);
898 return I40E_ERR_INVALID_MAC_ADDR;
901 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
902 list->vsi_id = vf->vsi_res->vsi_id;
903 list->num_elements = 1;
904 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
905 sizeof(addr->addr_bytes));
907 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
908 args.in_args = cmd_buffer;
909 args.in_args_size = sizeof(cmd_buffer);
910 args.out_buffer = vf->aq_resp;
911 args.out_size = I40E_AQ_BUF_SZ;
912 err = i40evf_execute_vf_cmd(dev, &args);
914 PMD_DRV_LOG(ERR, "fail to execute command "
915 "OP_ADD_ETHER_ADDRESS");
923 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
924 struct ether_addr *addr)
926 struct virtchnl_ether_addr_list *list;
927 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
928 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
929 sizeof(struct virtchnl_ether_addr)];
931 struct vf_cmd_info args;
933 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
934 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
935 addr->addr_bytes[0], addr->addr_bytes[1],
936 addr->addr_bytes[2], addr->addr_bytes[3],
937 addr->addr_bytes[4], addr->addr_bytes[5]);
941 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
942 list->vsi_id = vf->vsi_res->vsi_id;
943 list->num_elements = 1;
944 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
945 sizeof(addr->addr_bytes));
947 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
948 args.in_args = cmd_buffer;
949 args.in_args_size = sizeof(cmd_buffer);
950 args.out_buffer = vf->aq_resp;
951 args.out_size = I40E_AQ_BUF_SZ;
952 err = i40evf_execute_vf_cmd(dev, &args);
954 PMD_DRV_LOG(ERR, "fail to execute command "
955 "OP_DEL_ETHER_ADDRESS");
962 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
964 struct rte_eth_dev_data *data = dev->data;
965 struct ether_addr *addr;
967 addr = &data->mac_addrs[index];
969 i40evf_del_mac_addr_by_addr(dev, addr);
973 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
975 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
976 struct virtchnl_queue_select q_stats;
978 struct vf_cmd_info args;
980 memset(&q_stats, 0, sizeof(q_stats));
981 q_stats.vsi_id = vf->vsi_res->vsi_id;
982 args.ops = VIRTCHNL_OP_GET_STATS;
983 args.in_args = (u8 *)&q_stats;
984 args.in_args_size = sizeof(q_stats);
985 args.out_buffer = vf->aq_resp;
986 args.out_size = I40E_AQ_BUF_SZ;
988 err = i40evf_execute_vf_cmd(dev, &args);
990 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
994 *pstats = (struct i40e_eth_stats *)args.out_buffer;
999 i40evf_get_statistics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1002 struct i40e_eth_stats *pstats = NULL;
1004 ret = i40evf_update_stats(dev, &pstats);
1008 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
1009 pstats->rx_broadcast;
1010 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
1012 stats->imissed = pstats->rx_discards;
1013 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
1014 stats->ibytes = pstats->rx_bytes;
1015 stats->obytes = pstats->tx_bytes;
1021 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
1023 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1024 struct i40e_eth_stats *pstats = NULL;
1026 /* read stat values to clear hardware registers */
1027 i40evf_update_stats(dev, &pstats);
1029 /* set stats offset base on current values */
1030 vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
1033 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1034 struct rte_eth_xstat_name *xstats_names,
1035 __rte_unused unsigned limit)
1039 if (xstats_names != NULL)
1040 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1041 snprintf(xstats_names[i].name,
1042 sizeof(xstats_names[i].name),
1043 "%s", rte_i40evf_stats_strings[i].name);
1045 return I40EVF_NB_XSTATS;
1048 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1049 struct rte_eth_xstat *xstats, unsigned n)
1053 struct i40e_eth_stats *pstats = NULL;
1055 if (n < I40EVF_NB_XSTATS)
1056 return I40EVF_NB_XSTATS;
1058 ret = i40evf_update_stats(dev, &pstats);
1065 /* loop over xstats array and values from pstats */
1066 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1068 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1069 rte_i40evf_stats_strings[i].offset);
1072 return I40EVF_NB_XSTATS;
1076 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1078 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1079 struct virtchnl_vlan_filter_list *vlan_list;
1080 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1083 struct vf_cmd_info args;
1085 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1086 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1087 vlan_list->num_elements = 1;
1088 vlan_list->vlan_id[0] = vlanid;
1090 args.ops = VIRTCHNL_OP_ADD_VLAN;
1091 args.in_args = (u8 *)&cmd_buffer;
1092 args.in_args_size = sizeof(cmd_buffer);
1093 args.out_buffer = vf->aq_resp;
1094 args.out_size = I40E_AQ_BUF_SZ;
1095 err = i40evf_execute_vf_cmd(dev, &args);
1097 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1103 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1105 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1106 struct virtchnl_vlan_filter_list *vlan_list;
1107 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1110 struct vf_cmd_info args;
1112 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1113 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1114 vlan_list->num_elements = 1;
1115 vlan_list->vlan_id[0] = vlanid;
1117 args.ops = VIRTCHNL_OP_DEL_VLAN;
1118 args.in_args = (u8 *)&cmd_buffer;
1119 args.in_args_size = sizeof(cmd_buffer);
1120 args.out_buffer = vf->aq_resp;
1121 args.out_size = I40E_AQ_BUF_SZ;
1122 err = i40evf_execute_vf_cmd(dev, &args);
1124 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1129 static const struct rte_pci_id pci_id_i40evf_map[] = {
1130 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1131 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1132 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1133 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1134 { .vendor_id = 0, /* sentinel */ },
1138 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1139 struct rte_eth_link *link)
1141 struct rte_eth_link *dst = &(dev->data->dev_link);
1142 struct rte_eth_link *src = link;
1144 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1145 *(uint64_t *)src) == 0)
1153 i40evf_disable_irq0(struct i40e_hw *hw)
1155 /* Disable all interrupt types */
1156 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1157 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1158 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1159 I40EVF_WRITE_FLUSH(hw);
1164 i40evf_enable_irq0(struct i40e_hw *hw)
1166 /* Enable admin queue interrupt trigger */
1169 i40evf_disable_irq0(hw);
1170 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1171 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1172 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1173 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1175 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1176 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1177 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1178 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1180 I40EVF_WRITE_FLUSH(hw);
1184 i40evf_reset_vf(struct i40e_hw *hw)
1188 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1189 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1193 * After issuing vf reset command to pf, pf won't necessarily
1194 * reset vf, it depends on what state it exactly is. If it's not
1195 * initialized yet, it won't have vf reset since it's in a certain
1196 * state. If not, it will try to reset. Even vf is reset, pf will
1197 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1198 * it to ACTIVE. In this duration, vf may not catch the moment that
1199 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1203 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1204 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1205 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1206 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1207 if (VIRTCHNL_VFR_COMPLETED == reset || VIRTCHNL_VFR_VFACTIVE == reset)
1213 if (i >= MAX_RESET_WAIT_CNT) {
1214 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1222 i40evf_init_vf(struct rte_eth_dev *dev)
1225 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1226 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1228 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1230 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1231 vf->dev_data = dev->data;
1232 err = i40e_set_mac_type(hw);
1234 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1238 i40e_init_adminq_parameter(hw);
1239 err = i40e_init_adminq(hw);
1241 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1245 /* Reset VF and wait until it's complete */
1246 if (i40evf_reset_vf(hw)) {
1247 PMD_INIT_LOG(ERR, "reset NIC failed");
1251 /* VF reset, shutdown admin queue and initialize again */
1252 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1253 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1257 i40e_init_adminq_parameter(hw);
1258 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1259 PMD_INIT_LOG(ERR, "init_adminq failed");
1262 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1264 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1267 if (i40evf_check_api_version(dev) != 0) {
1268 PMD_INIT_LOG(ERR, "check_api version failed");
1271 bufsz = sizeof(struct virtchnl_vf_resource) +
1272 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1273 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1275 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1279 if (i40evf_get_vf_resource(dev) != 0) {
1280 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1284 /* got VF config message back from PF, now we can parse it */
1285 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1286 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1287 vf->vsi_res = &vf->vf_res->vsi_res[i];
1291 PMD_INIT_LOG(ERR, "no LAN VSI found");
1295 if (hw->mac.type == I40E_MAC_X722_VF)
1296 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1297 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1298 vf->vsi.type = (enum i40e_vsi_type)vf->vsi_res->vsi_type;
1299 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1300 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1302 /* Store the MAC address configured by host, or generate random one */
1303 if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1304 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1306 eth_random_addr(hw->mac.addr); /* Generate a random one */
1308 /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1309 if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1310 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1311 (I40E_ITR_INDEX_DEFAULT <<
1312 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1314 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1315 I40EVF_WRITE_FLUSH(hw);
1321 rte_free(vf->vf_res);
1323 i40e_shutdown_adminq(hw); /* ignore error */
1329 i40evf_uninit_vf(struct rte_eth_dev *dev)
1331 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1332 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1334 PMD_INIT_FUNC_TRACE();
1336 if (hw->adapter_stopped == 0)
1337 i40evf_dev_close(dev);
1338 rte_free(vf->vf_res);
1340 rte_free(vf->aq_resp);
1347 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1348 __rte_unused uint16_t msglen)
1350 struct virtchnl_pf_event *pf_msg =
1351 (struct virtchnl_pf_event *)msg;
1352 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1354 switch (pf_msg->event) {
1355 case VIRTCHNL_EVENT_RESET_IMPENDING:
1356 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1357 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1360 case VIRTCHNL_EVENT_LINK_CHANGE:
1361 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1362 vf->link_up = pf_msg->event_data.link_event.link_status;
1363 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1365 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1366 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1369 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1375 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1377 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1379 struct i40e_arq_event_info info;
1380 uint16_t pending, aq_opc;
1381 enum virtchnl_ops msg_opc;
1382 enum i40e_status_code msg_ret;
1385 info.buf_len = I40E_AQ_BUF_SZ;
1387 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1390 info.msg_buf = vf->aq_resp;
1394 ret = i40e_clean_arq_element(hw, &info, &pending);
1396 if (ret != I40E_SUCCESS) {
1397 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1401 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1402 /* For the message sent from pf to vf, opcode is stored in
1403 * cookie_high of struct i40e_aq_desc, while return error code
1404 * are stored in cookie_low, Which is done by
1405 * i40e_aq_send_msg_to_vf in PF driver.*/
1406 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1407 info.desc.cookie_high);
1408 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1409 info.desc.cookie_low);
1411 case i40e_aqc_opc_send_msg_to_vf:
1412 if (msg_opc == VIRTCHNL_OP_EVENT)
1414 i40evf_handle_pf_event(dev, info.msg_buf,
1417 /* read message and it's expected one */
1418 if (msg_opc == vf->pend_cmd) {
1419 vf->cmd_retval = msg_ret;
1420 /* prevent compiler reordering */
1421 rte_compiler_barrier();
1424 PMD_DRV_LOG(ERR, "command mismatch,"
1425 "expect %u, get %u",
1426 vf->pend_cmd, msg_opc);
1427 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1428 " opcode = %d", msg_opc);
1432 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1440 * Interrupt handler triggered by NIC for handling
1441 * specific interrupt. Only adminq interrupt is processed in VF.
1444 * Pointer to interrupt handle.
1446 * The address of parameter (struct rte_eth_dev *) regsitered before.
1452 i40evf_dev_interrupt_handler(void *param)
1454 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1455 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1458 i40evf_disable_irq0(hw);
1460 /* read out interrupt causes */
1461 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1463 /* No interrupt event indicated */
1464 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1465 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1469 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1470 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1471 i40evf_handle_aq_msg(dev);
1474 /* Link Status Change interrupt */
1475 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1476 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1480 i40evf_enable_irq0(hw);
1481 rte_intr_enable(dev->intr_handle);
1485 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1488 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1489 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1491 PMD_INIT_FUNC_TRACE();
1493 /* assign ops func pointer */
1494 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1495 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1496 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1499 * For secondary processes, we don't initialise any further as primary
1500 * has already done this work.
1502 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1503 i40e_set_rx_function(eth_dev);
1504 i40e_set_tx_function(eth_dev);
1507 i40e_set_default_ptype_table(eth_dev);
1508 rte_eth_copy_pci_info(eth_dev, pci_dev);
1509 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1511 hw->vendor_id = pci_dev->id.vendor_id;
1512 hw->device_id = pci_dev->id.device_id;
1513 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1514 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1515 hw->bus.device = pci_dev->addr.devid;
1516 hw->bus.func = pci_dev->addr.function;
1517 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1518 hw->adapter_stopped = 0;
1520 if(i40evf_init_vf(eth_dev) != 0) {
1521 PMD_INIT_LOG(ERR, "Init vf failed");
1525 /* register callback func to eal lib */
1526 rte_intr_callback_register(&pci_dev->intr_handle,
1527 i40evf_dev_interrupt_handler, (void *)eth_dev);
1529 /* enable uio intr after callback register */
1530 rte_intr_enable(&pci_dev->intr_handle);
1532 /* configure and enable device interrupt */
1533 i40evf_enable_irq0(hw);
1536 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1537 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1539 if (eth_dev->data->mac_addrs == NULL) {
1540 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1541 " store MAC addresses",
1542 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1545 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1546 ð_dev->data->mac_addrs[0]);
1552 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1554 PMD_INIT_FUNC_TRACE();
1556 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1559 eth_dev->dev_ops = NULL;
1560 eth_dev->rx_pkt_burst = NULL;
1561 eth_dev->tx_pkt_burst = NULL;
1563 if (i40evf_uninit_vf(eth_dev) != 0) {
1564 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1568 rte_free(eth_dev->data->mac_addrs);
1569 eth_dev->data->mac_addrs = NULL;
1574 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1575 struct rte_pci_device *pci_dev)
1577 return rte_eth_dev_pci_generic_probe(pci_dev,
1578 sizeof(struct i40e_adapter), i40evf_dev_init);
1581 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1583 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1587 * virtual function driver struct
1589 static struct rte_pci_driver rte_i40evf_pmd = {
1590 .id_table = pci_id_i40evf_map,
1591 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1592 .probe = eth_i40evf_pci_probe,
1593 .remove = eth_i40evf_pci_remove,
1596 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1597 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1598 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1601 i40evf_dev_configure(struct rte_eth_dev *dev)
1603 struct i40e_adapter *ad =
1604 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1605 struct rte_eth_conf *conf = &dev->data->dev_conf;
1608 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1609 * allocation or vector Rx preconditions we will reset it.
1611 ad->rx_bulk_alloc_allowed = true;
1612 ad->rx_vec_allowed = true;
1613 ad->tx_simple_allowed = true;
1614 ad->tx_vec_allowed = true;
1616 /* For non-DPDK PF drivers, VF has no ability to disable HW
1617 * CRC strip, and is implicitly enabled by the PF.
1619 if (!conf->rxmode.hw_strip_crc) {
1620 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1621 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
1622 (vf->version_minor <= VIRTCHNL_VERSION_MINOR)) {
1623 /* Peer is running non-DPDK PF driver. */
1624 PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1629 return i40evf_init_vlan(dev);
1633 i40evf_init_vlan(struct rte_eth_dev *dev)
1635 struct rte_eth_dev_data *data = dev->data;
1638 /* Apply vlan offload setting */
1639 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1641 /* Apply pvid setting */
1642 ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1643 data->dev_conf.txmode.hw_vlan_insert_pvid);
1648 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1650 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1652 /* Vlan stripping setting */
1653 if (mask & ETH_VLAN_STRIP_MASK) {
1654 /* Enable or disable VLAN stripping */
1655 if (dev_conf->rxmode.hw_vlan_strip)
1656 i40evf_enable_vlan_strip(dev);
1658 i40evf_disable_vlan_strip(dev);
1663 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1665 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1666 struct i40e_vsi_vlan_pvid_info info;
1667 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1669 memset(&info, 0, sizeof(info));
1672 /* Linux pf host don't support vlan offload yet */
1673 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1675 info.config.pvid = pvid;
1677 info.config.reject.tagged =
1678 dev_conf->txmode.hw_vlan_reject_tagged;
1679 info.config.reject.untagged =
1680 dev_conf->txmode.hw_vlan_reject_untagged;
1682 return i40evf_config_vlan_pvid(dev, &info);
1689 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1691 struct i40e_rx_queue *rxq;
1693 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1695 PMD_INIT_FUNC_TRACE();
1697 if (rx_queue_id < dev->data->nb_rx_queues) {
1698 rxq = dev->data->rx_queues[rx_queue_id];
1700 err = i40e_alloc_rx_queue_mbufs(rxq);
1702 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1708 /* Init the RX tail register. */
1709 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1710 I40EVF_WRITE_FLUSH(hw);
1712 /* Ready to switch the queue on */
1713 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1716 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1719 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1726 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1728 struct i40e_rx_queue *rxq;
1731 if (rx_queue_id < dev->data->nb_rx_queues) {
1732 rxq = dev->data->rx_queues[rx_queue_id];
1734 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1737 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1742 i40e_rx_queue_release_mbufs(rxq);
1743 i40e_reset_rx_queue(rxq);
1744 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1751 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1755 PMD_INIT_FUNC_TRACE();
1757 if (tx_queue_id < dev->data->nb_tx_queues) {
1759 /* Ready to switch the queue on */
1760 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1763 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1766 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1773 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1775 struct i40e_tx_queue *txq;
1778 if (tx_queue_id < dev->data->nb_tx_queues) {
1779 txq = dev->data->tx_queues[tx_queue_id];
1781 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1784 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1789 i40e_tx_queue_release_mbufs(txq);
1790 i40e_reset_tx_queue(txq);
1791 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1798 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1803 ret = i40evf_add_vlan(dev, vlan_id);
1805 ret = i40evf_del_vlan(dev,vlan_id);
1811 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1813 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1814 struct rte_eth_dev_data *dev_data = dev->data;
1815 struct rte_pktmbuf_pool_private *mbp_priv;
1816 uint16_t buf_size, len;
1818 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1819 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1820 I40EVF_WRITE_FLUSH(hw);
1822 /* Calculate the maximum packet length allowed */
1823 mbp_priv = rte_mempool_get_priv(rxq->mp);
1824 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1825 RTE_PKTMBUF_HEADROOM);
1826 rxq->hs_mode = i40e_header_split_none;
1827 rxq->rx_hdr_len = 0;
1828 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1829 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1830 rxq->max_pkt_len = RTE_MIN(len,
1831 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1834 * Check if the jumbo frame and maximum packet length are set correctly
1836 if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1837 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1838 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1839 PMD_DRV_LOG(ERR, "maximum packet length must be "
1840 "larger than %u and smaller than %u, as jumbo "
1841 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1842 (uint32_t)I40E_FRAME_SIZE_MAX);
1843 return I40E_ERR_CONFIG;
1846 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1847 rxq->max_pkt_len > ETHER_MAX_LEN) {
1848 PMD_DRV_LOG(ERR, "maximum packet length must be "
1849 "larger than %u and smaller than %u, as jumbo "
1850 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1851 (uint32_t)ETHER_MAX_LEN);
1852 return I40E_ERR_CONFIG;
1856 if (dev_data->dev_conf.rxmode.enable_scatter ||
1857 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1858 dev_data->scattered_rx = 1;
1865 i40evf_rx_init(struct rte_eth_dev *dev)
1867 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1869 int ret = I40E_SUCCESS;
1870 struct i40e_rx_queue **rxq =
1871 (struct i40e_rx_queue **)dev->data->rx_queues;
1873 i40evf_config_rss(vf);
1874 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1875 if (!rxq[i] || !rxq[i]->q_set)
1877 ret = i40evf_rxq_init(dev, rxq[i]);
1878 if (ret != I40E_SUCCESS)
1881 if (ret == I40E_SUCCESS)
1882 i40e_set_rx_function(dev);
1888 i40evf_tx_init(struct rte_eth_dev *dev)
1891 struct i40e_tx_queue **txq =
1892 (struct i40e_tx_queue **)dev->data->tx_queues;
1893 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1895 for (i = 0; i < dev->data->nb_tx_queues; i++)
1896 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1898 i40e_set_tx_function(dev);
1902 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1904 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1905 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1906 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1907 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1909 if (!rte_intr_allow_others(intr_handle)) {
1911 I40E_VFINT_DYN_CTL01,
1912 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1913 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1914 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1915 I40EVF_WRITE_FLUSH(hw);
1919 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1920 /* To support DPDK PF host */
1922 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1923 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1924 I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1925 /* If host driver is kernel driver, do nothing.
1926 * Interrupt 0 is used for rx packets, but don't set
1927 * I40E_VFINT_DYN_CTL01,
1928 * because it is already done in i40evf_enable_irq0.
1931 I40EVF_WRITE_FLUSH(hw);
1935 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1937 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1938 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1940 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1942 if (!rte_intr_allow_others(intr_handle)) {
1943 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1944 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1945 I40EVF_WRITE_FLUSH(hw);
1949 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1951 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1954 /* If host driver is kernel driver, do nothing.
1955 * Interrupt 0 is used for rx packets, but don't zero
1956 * I40E_VFINT_DYN_CTL01,
1957 * because interrupt 0 is also used for adminq processing.
1960 I40EVF_WRITE_FLUSH(hw);
1964 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1966 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1967 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1968 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1970 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1973 msix_intr = intr_handle->intr_vec[queue_id];
1974 if (msix_intr == I40E_MISC_VEC_ID)
1975 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1976 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1977 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1978 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1980 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1983 I40E_VFINT_DYN_CTLN1(msix_intr -
1985 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1986 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1987 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1989 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1991 I40EVF_WRITE_FLUSH(hw);
1993 rte_intr_enable(&pci_dev->intr_handle);
1999 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2001 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2002 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2003 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006 msix_intr = intr_handle->intr_vec[queue_id];
2007 if (msix_intr == I40E_MISC_VEC_ID)
2008 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
2011 I40E_VFINT_DYN_CTLN1(msix_intr -
2015 I40EVF_WRITE_FLUSH(hw);
2021 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
2023 struct virtchnl_ether_addr_list *list;
2024 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2029 struct ether_addr *addr;
2030 struct vf_cmd_info args;
2034 len = sizeof(struct virtchnl_ether_addr_list);
2035 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
2036 if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
2038 len += sizeof(struct virtchnl_ether_addr);
2039 if (len >= I40E_AQ_BUF_SZ) {
2045 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2047 PMD_DRV_LOG(ERR, "fail to allocate memory");
2051 for (i = begin; i < next_begin; i++) {
2052 addr = &dev->data->mac_addrs[i];
2053 if (is_zero_ether_addr(addr))
2055 (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
2056 sizeof(addr->addr_bytes));
2057 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2058 addr->addr_bytes[0], addr->addr_bytes[1],
2059 addr->addr_bytes[2], addr->addr_bytes[3],
2060 addr->addr_bytes[4], addr->addr_bytes[5]);
2063 list->vsi_id = vf->vsi_res->vsi_id;
2064 list->num_elements = j;
2065 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
2066 VIRTCHNL_OP_DEL_ETH_ADDR;
2067 args.in_args = (uint8_t *)list;
2068 args.in_args_size = len;
2069 args.out_buffer = vf->aq_resp;
2070 args.out_size = I40E_AQ_BUF_SZ;
2071 err = i40evf_execute_vf_cmd(dev, &args);
2073 PMD_DRV_LOG(ERR, "fail to execute command %s",
2074 add ? "OP_ADD_ETHER_ADDRESS" :
2075 "OP_DEL_ETHER_ADDRESS");
2084 } while (begin < I40E_NUM_MACADDR_MAX);
2088 i40evf_dev_start(struct rte_eth_dev *dev)
2090 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2091 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2092 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2093 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2094 uint32_t intr_vector = 0;
2096 PMD_INIT_FUNC_TRACE();
2098 hw->adapter_stopped = 0;
2100 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2101 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2102 dev->data->nb_tx_queues);
2104 /* check and configure queue intr-vector mapping */
2105 if (dev->data->dev_conf.intr_conf.rxq != 0) {
2106 intr_vector = dev->data->nb_rx_queues;
2107 if (rte_intr_efd_enable(intr_handle, intr_vector))
2111 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2112 intr_handle->intr_vec =
2113 rte_zmalloc("intr_vec",
2114 dev->data->nb_rx_queues * sizeof(int), 0);
2115 if (!intr_handle->intr_vec) {
2116 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2117 " intr_vec", dev->data->nb_rx_queues);
2122 if (i40evf_rx_init(dev) != 0){
2123 PMD_DRV_LOG(ERR, "failed to do RX init");
2127 i40evf_tx_init(dev);
2129 if (i40evf_configure_queues(dev) != 0) {
2130 PMD_DRV_LOG(ERR, "configure queues failed");
2133 if (i40evf_config_irq_map(dev)) {
2134 PMD_DRV_LOG(ERR, "config_irq_map failed");
2138 /* Set all mac addrs */
2139 i40evf_add_del_all_mac_addr(dev, TRUE);
2141 if (i40evf_start_queues(dev) != 0) {
2142 PMD_DRV_LOG(ERR, "enable queues failed");
2146 i40evf_enable_queues_intr(dev);
2150 i40evf_add_del_all_mac_addr(dev, FALSE);
2156 i40evf_dev_stop(struct rte_eth_dev *dev)
2158 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2159 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2160 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev);
2162 PMD_INIT_FUNC_TRACE();
2164 if (hw->adapter_stopped == 1)
2166 i40evf_stop_queues(dev);
2167 i40evf_disable_queues_intr(dev);
2168 i40e_dev_clear_queues(dev);
2170 /* Clean datapath event and queue/vec mapping */
2171 rte_intr_efd_disable(intr_handle);
2172 if (intr_handle->intr_vec) {
2173 rte_free(intr_handle->intr_vec);
2174 intr_handle->intr_vec = NULL;
2176 /* remove all mac addrs */
2177 i40evf_add_del_all_mac_addr(dev, FALSE);
2178 hw->adapter_stopped = 1;
2183 i40evf_dev_link_update(struct rte_eth_dev *dev,
2184 __rte_unused int wait_to_complete)
2186 struct rte_eth_link new_link;
2187 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2189 * DPDK pf host provide interfacet to acquire link status
2190 * while Linux driver does not
2193 /* Linux driver PF host */
2194 switch (vf->link_speed) {
2195 case I40E_LINK_SPEED_100MB:
2196 new_link.link_speed = ETH_SPEED_NUM_100M;
2198 case I40E_LINK_SPEED_1GB:
2199 new_link.link_speed = ETH_SPEED_NUM_1G;
2201 case I40E_LINK_SPEED_10GB:
2202 new_link.link_speed = ETH_SPEED_NUM_10G;
2204 case I40E_LINK_SPEED_20GB:
2205 new_link.link_speed = ETH_SPEED_NUM_20G;
2207 case I40E_LINK_SPEED_25GB:
2208 new_link.link_speed = ETH_SPEED_NUM_25G;
2210 case I40E_LINK_SPEED_40GB:
2211 new_link.link_speed = ETH_SPEED_NUM_40G;
2214 new_link.link_speed = ETH_SPEED_NUM_100M;
2217 /* full duplex only */
2218 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2219 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2222 i40evf_dev_atomic_write_link_status(dev, &new_link);
2228 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2230 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2233 /* If enabled, just return */
2234 if (vf->promisc_unicast_enabled)
2237 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2239 vf->promisc_unicast_enabled = TRUE;
2243 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2245 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2248 /* If disabled, just return */
2249 if (!vf->promisc_unicast_enabled)
2252 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2254 vf->promisc_unicast_enabled = FALSE;
2258 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2260 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2263 /* If enabled, just return */
2264 if (vf->promisc_multicast_enabled)
2267 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2269 vf->promisc_multicast_enabled = TRUE;
2273 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2275 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2278 /* If enabled, just return */
2279 if (!vf->promisc_multicast_enabled)
2282 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2284 vf->promisc_multicast_enabled = FALSE;
2288 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2290 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2292 memset(dev_info, 0, sizeof(*dev_info));
2293 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2294 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2295 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2296 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2297 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2298 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2299 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2300 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2301 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2302 dev_info->rx_offload_capa =
2303 DEV_RX_OFFLOAD_VLAN_STRIP |
2304 DEV_RX_OFFLOAD_QINQ_STRIP |
2305 DEV_RX_OFFLOAD_IPV4_CKSUM |
2306 DEV_RX_OFFLOAD_UDP_CKSUM |
2307 DEV_RX_OFFLOAD_TCP_CKSUM;
2308 dev_info->tx_offload_capa =
2309 DEV_TX_OFFLOAD_VLAN_INSERT |
2310 DEV_TX_OFFLOAD_QINQ_INSERT |
2311 DEV_TX_OFFLOAD_IPV4_CKSUM |
2312 DEV_TX_OFFLOAD_UDP_CKSUM |
2313 DEV_TX_OFFLOAD_TCP_CKSUM |
2314 DEV_TX_OFFLOAD_SCTP_CKSUM;
2316 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2318 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2319 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2320 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2322 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2326 dev_info->default_txconf = (struct rte_eth_txconf) {
2328 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2329 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2330 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2332 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2333 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2334 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2335 ETH_TXQ_FLAGS_NOOFFLOADS,
2338 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2339 .nb_max = I40E_MAX_RING_DESC,
2340 .nb_min = I40E_MIN_RING_DESC,
2341 .nb_align = I40E_ALIGN_RING_DESC,
2344 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2345 .nb_max = I40E_MAX_RING_DESC,
2346 .nb_min = I40E_MIN_RING_DESC,
2347 .nb_align = I40E_ALIGN_RING_DESC,
2352 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2354 if (i40evf_get_statistics(dev, stats))
2355 PMD_DRV_LOG(ERR, "Get statistics failed");
2359 i40evf_dev_close(struct rte_eth_dev *dev)
2361 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2362 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2363 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2365 i40evf_dev_stop(dev);
2366 i40e_dev_free_queues(dev);
2367 i40evf_reset_vf(hw);
2368 i40e_shutdown_adminq(hw);
2369 /* disable uio intr before callback unregister */
2370 rte_intr_disable(intr_handle);
2372 /* unregister callback func from eal lib */
2373 rte_intr_callback_unregister(intr_handle,
2374 i40evf_dev_interrupt_handler, dev);
2375 i40evf_disable_irq0(hw);
2379 * Reset VF device only to re-initialize resources in PMD layer
2382 i40evf_dev_reset(struct rte_eth_dev *dev)
2386 ret = i40evf_dev_uninit(dev);
2390 ret = i40evf_dev_init(dev);
2396 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2398 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2399 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2405 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2406 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2409 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2413 uint32_t *lut_dw = (uint32_t *)lut;
2414 uint16_t i, lut_size_dw = lut_size / 4;
2416 for (i = 0; i < lut_size_dw; i++)
2417 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2424 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2433 vf = I40E_VSI_TO_VF(vsi);
2434 hw = I40E_VSI_TO_HW(vsi);
2436 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2437 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2440 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2444 uint32_t *lut_dw = (uint32_t *)lut;
2445 uint16_t i, lut_size_dw = lut_size / 4;
2447 for (i = 0; i < lut_size_dw; i++)
2448 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2449 I40EVF_WRITE_FLUSH(hw);
2456 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2457 struct rte_eth_rss_reta_entry64 *reta_conf,
2460 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2462 uint16_t i, idx, shift;
2465 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2466 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2467 "(%d) doesn't match the number of hardware can "
2468 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2472 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2474 PMD_DRV_LOG(ERR, "No memory can be allocated");
2477 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2480 for (i = 0; i < reta_size; i++) {
2481 idx = i / RTE_RETA_GROUP_SIZE;
2482 shift = i % RTE_RETA_GROUP_SIZE;
2483 if (reta_conf[idx].mask & (1ULL << shift))
2484 lut[i] = reta_conf[idx].reta[shift];
2486 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2495 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2496 struct rte_eth_rss_reta_entry64 *reta_conf,
2499 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2500 uint16_t i, idx, shift;
2504 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2505 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2506 "(%d) doesn't match the number of hardware can "
2507 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2511 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2513 PMD_DRV_LOG(ERR, "No memory can be allocated");
2517 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2520 for (i = 0; i < reta_size; i++) {
2521 idx = i / RTE_RETA_GROUP_SIZE;
2522 shift = i % RTE_RETA_GROUP_SIZE;
2523 if (reta_conf[idx].mask & (1ULL << shift))
2524 reta_conf[idx].reta[shift] = lut[i];
2534 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2536 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2537 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2540 if (!key || key_len == 0) {
2541 PMD_DRV_LOG(DEBUG, "No key to be configured");
2543 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2545 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2549 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2550 struct i40e_aqc_get_set_rss_key_data *key_dw =
2551 (struct i40e_aqc_get_set_rss_key_data *)key;
2553 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2555 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2558 uint32_t *hash_key = (uint32_t *)key;
2561 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2562 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2563 I40EVF_WRITE_FLUSH(hw);
2570 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2572 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2573 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2576 if (!key || !key_len)
2579 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2580 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2581 (struct i40e_aqc_get_set_rss_key_data *)key);
2583 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2587 uint32_t *key_dw = (uint32_t *)key;
2590 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2591 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2593 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2599 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2601 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2602 uint64_t rss_hf, hena;
2605 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2606 rss_conf->rss_key_len);
2610 rss_hf = rss_conf->rss_hf;
2611 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2612 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2613 if (hw->mac.type == I40E_MAC_X722)
2614 hena &= ~I40E_RSS_HENA_ALL_X722;
2616 hena &= ~I40E_RSS_HENA_ALL;
2617 hena |= i40e_config_hena(rss_hf, hw->mac.type);
2618 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2619 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2620 I40EVF_WRITE_FLUSH(hw);
2626 i40evf_disable_rss(struct i40e_vf *vf)
2628 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2631 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2632 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2633 if (hw->mac.type == I40E_MAC_X722)
2634 hena &= ~I40E_RSS_HENA_ALL_X722;
2636 hena &= ~I40E_RSS_HENA_ALL;
2637 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2638 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2639 I40EVF_WRITE_FLUSH(hw);
2643 i40evf_config_rss(struct i40e_vf *vf)
2645 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2646 struct rte_eth_rss_conf rss_conf;
2647 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2650 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2651 i40evf_disable_rss(vf);
2652 PMD_DRV_LOG(DEBUG, "RSS not configured");
2656 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2657 /* Fill out the look up table */
2658 for (i = 0, j = 0; i < nb_q; i++, j++) {
2661 lut = (lut << 8) | j;
2663 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2666 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2667 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2668 i40evf_disable_rss(vf);
2669 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2673 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2674 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2675 /* Calculate the default hash key */
2676 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2677 rss_key_default[i] = (uint32_t)rte_rand();
2678 rss_conf.rss_key = (uint8_t *)rss_key_default;
2679 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2683 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2687 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2688 struct rte_eth_rss_conf *rss_conf)
2690 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2691 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2692 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2695 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2696 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2697 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2698 ? I40E_RSS_HENA_ALL_X722
2699 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2700 if (rss_hf != 0) /* Enable RSS */
2706 if (rss_hf == 0) /* Disable RSS */
2709 return i40evf_hw_rss_hash_set(vf, rss_conf);
2713 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2714 struct rte_eth_rss_conf *rss_conf)
2716 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2717 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2720 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2721 &rss_conf->rss_key_len);
2723 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2724 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2725 rss_conf->rss_hf = i40e_parse_hena(hena);
2731 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2733 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2734 struct rte_eth_dev_data *dev_data = vf->dev_data;
2735 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2738 /* check if mtu is within the allowed range */
2739 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2742 /* mtu setting is forbidden if port is start */
2743 if (dev_data->dev_started) {
2744 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2749 if (frame_size > ETHER_MAX_LEN)
2750 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2752 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2754 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2760 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2761 struct ether_addr *mac_addr)
2763 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2765 if (!is_valid_assigned_ether_addr(mac_addr)) {
2766 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2770 if (is_same_ether_addr(mac_addr, dev->data->mac_addrs))
2773 if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2776 i40evf_del_mac_addr_by_addr(dev, dev->data->mac_addrs);
2778 i40evf_add_mac_addr(dev, mac_addr, 0, 0);