4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "base/i40e_prototype.h"
39 #include "base/i40e_type.h"
40 #include "i40e_ethdev.h"
41 #include "i40e_rxtx.h"
43 #include <tmmintrin.h>
45 #ifndef __INTEL_COMPILER
46 #pragma GCC diagnostic ignored "-Wcast-qual"
50 i40e_rxq_rearm(struct i40e_rx_queue *rxq)
54 volatile union i40e_rx_desc *rxdp;
55 struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
56 struct rte_mbuf *mb0, *mb1;
57 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
58 RTE_PKTMBUF_HEADROOM);
59 __m128i dma_addr0, dma_addr1;
61 rxdp = rxq->rx_ring + rxq->rxrearm_start;
63 /* Pull 'n' more MBUFs into the software ring */
64 if (rte_mempool_get_bulk(rxq->mp,
66 RTE_I40E_RXQ_REARM_THRESH) < 0) {
67 if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
69 dma_addr0 = _mm_setzero_si128();
70 for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
71 rxep[i].mbuf = &rxq->fake_mbuf;
72 _mm_store_si128((__m128i *)&rxdp[i].read,
76 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
77 RTE_I40E_RXQ_REARM_THRESH;
81 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
82 for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
83 __m128i vaddr0, vaddr1;
89 /* Flush mbuf with pkt template.
90 * Data to be rearmed is 6 bytes long.
91 * Though, RX will overwrite ol_flags that are coming next
92 * anyway. So overwrite whole 8 bytes with one load:
93 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
95 p0 = (uintptr_t)&mb0->rearm_data;
96 *(uint64_t *)p0 = rxq->mbuf_initializer;
97 p1 = (uintptr_t)&mb1->rearm_data;
98 *(uint64_t *)p1 = rxq->mbuf_initializer;
100 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
101 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
102 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
104 /* convert pa to dma_addr hdr/data */
105 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
106 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
108 /* add headroom to pa values */
109 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
110 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
112 /* flush desc with pa dma_addr */
113 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
114 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
117 rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
118 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
119 rxq->rxrearm_start = 0;
121 rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
123 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
124 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
126 /* Update the tail pointer on the NIC */
127 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
130 /* Handling the offload flags (olflags) field takes computation
131 * time when receiving packets. Therefore we provide a flag to disable
132 * the processing of the olflags field when they are not needed. This
133 * gives improved performance, at the cost of losing the offload info
134 * in the received packet
136 #ifdef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE
139 desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
141 __m128i vlan0, vlan1, rss;
147 /* mask everything except RSS, flow director and VLAN flags
148 * bit2 is for VLAN tag, bit11 for flow director indication
149 * bit13:12 for RSS indication.
151 const __m128i rss_vlan_msk = _mm_set_epi16(
152 0x0000, 0x0000, 0x0000, 0x0000,
153 0x3804, 0x3804, 0x3804, 0x3804);
155 /* map rss and vlan type to rss hash and vlan flag */
156 const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,
158 0, 0, 0, PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
161 const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
163 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
164 0, 0, PKT_RX_FDIR, 0);
166 vlan0 = _mm_unpackhi_epi16(descs[0], descs[1]);
167 vlan1 = _mm_unpackhi_epi16(descs[2], descs[3]);
168 vlan0 = _mm_unpacklo_epi32(vlan0, vlan1);
170 vlan1 = _mm_and_si128(vlan0, rss_vlan_msk);
171 vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);
173 rss = _mm_srli_epi16(vlan1, 11);
174 rss = _mm_shuffle_epi8(rss_flags, rss);
176 vlan0 = _mm_or_si128(vlan0, rss);
177 vol.dword = _mm_cvtsi128_si64(vlan0);
179 rx_pkts[0]->ol_flags = vol.e[0];
180 rx_pkts[1]->ol_flags = vol.e[1];
181 rx_pkts[2]->ol_flags = vol.e[2];
182 rx_pkts[3]->ol_flags = vol.e[3];
185 #define desc_to_olflags_v(desc, rx_pkts) do {} while (0)
188 #define PKTLEN_SHIFT 10
192 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
193 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
196 static inline uint16_t
197 _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
198 uint16_t nb_pkts, uint8_t *split_packet)
200 volatile union i40e_rx_desc *rxdp;
201 struct i40e_rx_entry *sw_ring;
202 uint16_t nb_pkts_recd;
207 __m128i crc_adjust = _mm_set_epi16(
208 0, 0, 0, /* ignore non-length fields */
209 -rxq->crc_len, /* sub crc on data_len */
210 0, /* ignore high-16bits of pkt_len */
211 -rxq->crc_len, /* sub crc on pkt_len */
212 0, 0 /* ignore pkt_type field */
214 __m128i dd_check, eop_check;
216 /* nb_pkts shall be less equal than RTE_I40E_MAX_RX_BURST */
217 nb_pkts = RTE_MIN(nb_pkts, RTE_I40E_MAX_RX_BURST);
219 /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
220 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
222 /* Just the act of getting into the function from the application is
223 * going to cost about 7 cycles
225 rxdp = rxq->rx_ring + rxq->rx_tail;
229 /* See if we need to rearm the RX queue - gives the prefetch a bit
232 if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
235 /* Before we start moving massive data around, check to see if
236 * there is actually a packet available
238 if (!(rxdp->wb.qword1.status_error_len &
239 rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
242 /* 4 packets DD mask */
243 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
245 /* 4 packets EOP mask */
246 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
248 /* mask to shuffle from desc. to mbuf */
249 shuf_msk = _mm_set_epi8(
250 7, 6, 5, 4, /* octet 4~7, 32bits rss */
251 3, 2, /* octet 2~3, low 16 bits vlan_macip */
252 15, 14, /* octet 15~14, 16 bits data_len */
253 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
254 15, 14, /* octet 15~14, low 16 bits pkt_len */
255 0xFF, 0xFF, /* pkt_type set as unknown */
256 0xFF, 0xFF /*pkt_type set as unknown */
259 /* Cache is empty -> need to scan the buffer rings, but first move
260 * the next 'n' mbufs into the cache
262 sw_ring = &rxq->sw_ring[rxq->rx_tail];
264 /* A. load 4 packet in one loop
265 * [A*. mask out 4 unused dirty field in desc]
266 * B. copy 4 mbuf point from swring to rx_pkts
267 * C. calc the number of DD bits among the 4 packets
268 * [C*. extract the end-of-packet bit, if requested]
269 * D. fill info. from desc to mbuf
272 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
273 pos += RTE_I40E_DESCS_PER_LOOP,
274 rxdp += RTE_I40E_DESCS_PER_LOOP) {
275 __m128i descs[RTE_I40E_DESCS_PER_LOOP];
276 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
277 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
278 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
280 /* B.1 load 1 mbuf point */
281 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
282 /* Read desc statuses backwards to avoid race condition */
283 /* A.1 load 4 pkts desc */
284 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
286 /* B.2 copy 2 mbuf point into rx_pkts */
287 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
289 /* B.1 load 1 mbuf point */
290 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
292 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
293 /* B.1 load 2 mbuf point */
294 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
295 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
297 /* B.2 copy 2 mbuf point into rx_pkts */
298 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
301 rte_mbuf_prefetch_part2(rx_pkts[pos]);
302 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
303 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
304 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
307 /* avoid compiler reorder optimization */
308 rte_compiler_barrier();
310 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
311 const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);
312 const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);
314 /* merge the now-aligned packet length fields back in */
315 descs[3] = _mm_blend_epi16(descs[3], len3, 0x80);
316 descs[2] = _mm_blend_epi16(descs[2], len2, 0x80);
318 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
319 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
320 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
322 /* C.1 4=>2 filter staterr info only */
323 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
324 /* C.1 4=>2 filter staterr info only */
325 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
327 desc_to_olflags_v(descs, &rx_pkts[pos]);
329 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
330 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
331 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
333 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
334 const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);
335 const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);
337 /* merge the now-aligned packet length fields back in */
338 descs[1] = _mm_blend_epi16(descs[1], len1, 0x80);
339 descs[0] = _mm_blend_epi16(descs[0], len0, 0x80);
341 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
342 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
343 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
345 /* C.2 get 4 pkts staterr value */
346 zero = _mm_xor_si128(dd_check, dd_check);
347 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
349 /* D.3 copy final 3,4 data to rx_pkts */
350 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
352 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
355 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
356 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
357 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
359 /* C* extract and record EOP bit */
361 __m128i eop_shuf_mask = _mm_set_epi8(
362 0xFF, 0xFF, 0xFF, 0xFF,
363 0xFF, 0xFF, 0xFF, 0xFF,
364 0xFF, 0xFF, 0xFF, 0xFF,
365 0x04, 0x0C, 0x00, 0x08
368 /* and with mask to extract bits, flipping 1-0 */
369 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
370 /* the staterr values are not in order, as the count
371 * count of dd bits doesn't care. However, for end of
372 * packet tracking, we do care, so shuffle. This also
373 * compresses the 32-bit values to 8-bit
375 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
376 /* store the resulting 32-bit value */
377 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
378 split_packet += RTE_I40E_DESCS_PER_LOOP;
380 /* zero-out next pointers */
381 rx_pkts[pos]->next = NULL;
382 rx_pkts[pos + 1]->next = NULL;
383 rx_pkts[pos + 2]->next = NULL;
384 rx_pkts[pos + 3]->next = NULL;
387 /* C.3 calc available number of desc */
388 staterr = _mm_and_si128(staterr, dd_check);
389 staterr = _mm_packs_epi32(staterr, zero);
391 /* D.3 copy final 1,2 data to rx_pkts */
392 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
394 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
396 /* C.4 calc avaialbe number of desc */
397 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
399 if (likely(var != RTE_I40E_DESCS_PER_LOOP))
403 /* Update our internal tail pointer */
404 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
405 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
406 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
413 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
414 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
418 i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
421 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
424 static inline uint16_t
425 reassemble_packets(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_bufs,
426 uint16_t nb_bufs, uint8_t *split_flags)
428 struct rte_mbuf *pkts[RTE_I40E_VPMD_RX_BURST]; /*finished pkts*/
429 struct rte_mbuf *start = rxq->pkt_first_seg;
430 struct rte_mbuf *end = rxq->pkt_last_seg;
431 unsigned pkt_idx, buf_idx;
433 for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
435 /* processing a split packet */
436 end->next = rx_bufs[buf_idx];
437 rx_bufs[buf_idx]->data_len += rxq->crc_len;
440 start->pkt_len += rx_bufs[buf_idx]->data_len;
443 if (!split_flags[buf_idx]) {
444 /* it's the last packet of the set */
445 start->hash = end->hash;
446 start->ol_flags = end->ol_flags;
447 /* we need to strip crc for the whole packet */
448 start->pkt_len -= rxq->crc_len;
449 if (end->data_len > rxq->crc_len) {
450 end->data_len -= rxq->crc_len;
452 /* free up last mbuf */
453 struct rte_mbuf *secondlast = start;
455 while (secondlast->next != end)
456 secondlast = secondlast->next;
457 secondlast->data_len -= (rxq->crc_len -
459 secondlast->next = NULL;
460 rte_pktmbuf_free_seg(end);
463 pkts[pkt_idx++] = start;
467 /* not processing a split packet */
468 if (!split_flags[buf_idx]) {
469 /* not a split packet, save and skip */
470 pkts[pkt_idx++] = rx_bufs[buf_idx];
473 end = start = rx_bufs[buf_idx];
474 rx_bufs[buf_idx]->data_len += rxq->crc_len;
475 rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
479 /* save the partial packet for next time */
480 rxq->pkt_first_seg = start;
481 rxq->pkt_last_seg = end;
482 memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
486 /* vPMD receive routine that reassembles scattered packets
488 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
489 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
493 i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
497 struct i40e_rx_queue *rxq = rx_queue;
498 uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
500 /* get some new buffers */
501 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
506 /* happy day case, full burst + no packets to be joined */
507 const uint64_t *split_fl64 = (uint64_t *)split_flags;
509 if (rxq->pkt_first_seg == NULL &&
510 split_fl64[0] == 0 && split_fl64[1] == 0 &&
511 split_fl64[2] == 0 && split_fl64[3] == 0)
514 /* reassemble any packets that need reassembly*/
517 if (rxq->pkt_first_seg == NULL) {
518 /* find the first split flag, and only reassemble then*/
519 while (i < nb_bufs && !split_flags[i])
524 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
529 vtx1(volatile struct i40e_tx_desc *txdp,
530 struct rte_mbuf *pkt, uint64_t flags)
532 uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
533 ((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) |
534 ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
536 __m128i descriptor = _mm_set_epi64x(high_qw,
537 pkt->buf_physaddr + pkt->data_off);
538 _mm_store_si128((__m128i *)txdp, descriptor);
542 vtx(volatile struct i40e_tx_desc *txdp,
543 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
547 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
548 vtx1(txdp, *pkt, flags);
551 static inline int __attribute__((always_inline))
552 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
554 struct i40e_tx_entry *txep;
558 struct rte_mbuf *m, *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];
560 /* check DD bits on threshold descriptor */
561 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
562 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
563 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
566 n = txq->tx_rs_thresh;
568 /* first buffer to free from S/W ring is at index
569 * tx_next_dd - (tx_rs_thresh-1)
571 txep = &txq->sw_ring[txq->tx_next_dd - (n - 1)];
572 m = __rte_pktmbuf_prefree_seg(txep[0].mbuf);
573 if (likely(m != NULL)) {
576 for (i = 1; i < n; i++) {
577 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
578 if (likely(m != NULL)) {
579 if (likely(m->pool == free[0]->pool)) {
582 rte_mempool_put_bulk(free[0]->pool,
590 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
592 for (i = 1; i < n; i++) {
593 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
595 rte_mempool_put(m->pool, m);
599 /* buffers were freed, update counters */
600 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
601 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
602 if (txq->tx_next_dd >= txq->nb_tx_desc)
603 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
605 return txq->tx_rs_thresh;
608 static inline void __attribute__((always_inline))
609 tx_backlog_entry(struct i40e_tx_entry *txep,
610 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
614 for (i = 0; i < (int)nb_pkts; ++i)
615 txep[i].mbuf = tx_pkts[i];
619 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
622 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
623 volatile struct i40e_tx_desc *txdp;
624 struct i40e_tx_entry *txep;
625 uint16_t n, nb_commit, tx_id;
626 uint64_t flags = I40E_TD_CMD;
627 uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
630 /* cross rx_thresh boundary is not allowed */
631 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
633 if (txq->nb_tx_free < txq->tx_free_thresh)
634 i40e_tx_free_bufs(txq);
636 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
637 if (unlikely(nb_pkts == 0))
640 tx_id = txq->tx_tail;
641 txdp = &txq->tx_ring[tx_id];
642 txep = &txq->sw_ring[tx_id];
644 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
646 n = (uint16_t)(txq->nb_tx_desc - tx_id);
647 if (nb_commit >= n) {
648 tx_backlog_entry(txep, tx_pkts, n);
650 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
651 vtx1(txdp, *tx_pkts, flags);
653 vtx1(txdp, *tx_pkts++, rs);
655 nb_commit = (uint16_t)(nb_commit - n);
658 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
660 /* avoid reach the end of ring */
661 txdp = &txq->tx_ring[tx_id];
662 txep = &txq->sw_ring[tx_id];
665 tx_backlog_entry(txep, tx_pkts, nb_commit);
667 vtx(txdp, tx_pkts, nb_commit, flags);
669 tx_id = (uint16_t)(tx_id + nb_commit);
670 if (tx_id > txq->tx_next_rs) {
671 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
672 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
673 I40E_TXD_QW1_CMD_SHIFT);
675 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
678 txq->tx_tail = tx_id;
680 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
685 void __attribute__((cold))
686 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
688 const unsigned mask = rxq->nb_rx_desc - 1;
691 if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_rx_desc)
694 /* free all mbufs that are valid in the ring */
695 if (rxq->rxrearm_nb == 0) {
696 for (i = 0; i < rxq->nb_rx_desc; i++) {
697 if (rxq->sw_ring[i].mbuf != NULL)
698 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
701 for (i = rxq->rx_tail;
702 i != rxq->rxrearm_start;
703 i = (i + 1) & mask) {
704 if (rxq->sw_ring[i].mbuf != NULL)
705 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
709 rxq->rxrearm_nb = rxq->nb_rx_desc;
711 /* set all entries to NULL */
712 memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);
715 int __attribute__((cold))
716 i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
719 struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
722 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
723 mb_def.port = rxq->port_id;
724 rte_mbuf_refcnt_set(&mb_def, 1);
726 /* prevent compiler reordering: rearm_data covers previous fields */
727 rte_compiler_barrier();
728 p = (uintptr_t)&mb_def.rearm_data;
729 rxq->mbuf_initializer = *(uint64_t *)p;
733 int __attribute__((cold))
734 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
739 int __attribute__((cold))
740 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
742 #ifndef RTE_LIBRTE_IEEE1588
743 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
744 struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
746 /* need SSE4.1 support */
747 if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
750 #ifndef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE
751 /* whithout rx ol_flags, no VP flag report */
752 if (rxmode->hw_vlan_strip != 0 ||
753 rxmode->hw_vlan_extend != 0)
757 /* no fdir support */
758 if (fconf->mode != RTE_FDIR_MODE_NONE)
761 /* - no csum error report support
762 * - no header split support
764 if (rxmode->hw_ip_checksum == 1 ||
765 rxmode->header_split == 1)