1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #ifndef _ICE_ADMINQ_CMD_H_
6 #define _ICE_ADMINQ_CMD_H_
8 /* This header file defines the Admin Queue commands, error codes and
9 * descriptor format. It is shared between Firmware and Software.
13 #define ICE_MAX_VSI 768
14 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
15 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
18 struct ice_aqc_generic {
26 /* Get version (direct 0x0001) */
27 struct ice_aqc_get_ver {
41 /* Send driver version (indirect 0x0002) */
42 struct ice_aqc_driver_ver {
53 /* Queue Shutdown (direct 0x0003) */
54 struct ice_aqc_q_shutdown {
55 __le32 driver_unloading;
56 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
63 /* Request resource ownership (direct 0x0008)
64 * Release resource ownership (direct 0x0009)
66 struct ice_aqc_req_res {
68 #define ICE_AQC_RES_ID_NVM 1
69 #define ICE_AQC_RES_ID_SDP 2
70 #define ICE_AQC_RES_ID_CHNG_LOCK 3
71 #define ICE_AQC_RES_ID_GLBL_LOCK 4
73 #define ICE_AQC_RES_ACCESS_READ 1
74 #define ICE_AQC_RES_ACCESS_WRITE 2
76 /* Upon successful completion, FW writes this value and driver is
77 * expected to release resource before timeout. This value is provided
81 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
82 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
83 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
84 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
85 /* For SDP: pin ID of the SDP */
87 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
89 #define ICE_AQ_RES_GLBL_SUCCESS 0
90 #define ICE_AQ_RES_GLBL_IN_PROG 1
91 #define ICE_AQ_RES_GLBL_DONE 2
96 /* Get function capabilities (indirect 0x000A)
97 * Get device capabilities (indirect 0x000B)
99 struct ice_aqc_list_caps {
109 /* Device/Function buffer entry, repeated per reported capability */
110 struct ice_aqc_list_caps_elem {
112 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
113 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8
114 #define ICE_AQC_CAPS_VSI 0x0017
115 #define ICE_AQC_CAPS_DCB 0x0018
116 #define ICE_AQC_CAPS_RSS 0x0040
117 #define ICE_AQC_CAPS_RXQS 0x0041
118 #define ICE_AQC_CAPS_TXQS 0x0042
119 #define ICE_AQC_CAPS_MSIX 0x0043
120 #define ICE_AQC_CAPS_FD 0x0045
121 #define ICE_AQC_CAPS_MAX_MTU 0x0047
125 /* Number of resources described by this capability */
127 /* Only meaningful for some types of resources */
129 /* Only meaningful for some types of resources */
136 /* Manage MAC address, read command - indirect (0x0107)
137 * This struct is also used for the response
139 struct ice_aqc_manage_mac_read {
140 __le16 flags; /* Zeroed by device driver */
141 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
142 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
143 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
144 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
145 #define ICE_AQC_MAN_MAC_READ_S 4
146 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
148 u8 num_addr; /* Used in response */
155 /* Response buffer format for manage MAC read command */
156 struct ice_aqc_manage_mac_read_resp {
159 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
160 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
161 u8 mac_addr[ETH_ALEN];
165 /* Manage MAC address, write command - direct (0x0108) */
166 struct ice_aqc_manage_mac_write {
169 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
170 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
171 #define ICE_AQC_MAN_MAC_WR_S 6
172 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S)
173 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
174 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S)
175 /* High 16 bits of MAC address in big endian order */
177 /* Low 32 bits of MAC address in big endian order */
184 /* Clear PXE Command and response (direct 0x0110) */
185 struct ice_aqc_clear_pxe {
187 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
192 /* Configure No-Drop Policy Command (direct 0x0112) */
193 struct ice_aqc_config_no_drop_policy {
195 #define ICE_AQC_FORCE_NO_DROP BIT(0)
199 /* Get switch configuration (0x0200) */
200 struct ice_aqc_get_sw_cfg {
201 /* Reserved for command and copy of request flags for response */
203 /* First desc in case of command and next_elem in case of response
204 * In case of response, if it is not zero, means all the configuration
205 * was not returned and new command shall be sent with this value in
206 * the 'first desc' field
209 /* Reserved for command, only used for response */
217 /* Each entry in the response buffer is of the following type: */
218 struct ice_aqc_get_sw_cfg_resp_elem {
219 /* VSI/Port Number */
221 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
222 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
223 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
224 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
225 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
226 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
227 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
228 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
230 /* SWID VSI/Port belongs to */
233 /* Bit 14..0 : PF/VF number VSI belongs to
234 * Bit 15 : VF indication bit
237 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
238 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
239 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
240 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
244 /* The response buffer is as follows. Note that the length of the
245 * elements array varies with the length of the command response.
247 struct ice_aqc_get_sw_cfg_resp {
248 struct ice_aqc_get_sw_cfg_resp_elem elements[1];
253 /* These resource type defines are used for all switch resource
254 * commands where a resource type is required, such as:
255 * Get Resource Allocation command (indirect 0x0204)
256 * Allocate Resources command (indirect 0x0208)
257 * Free Resources command (indirect 0x0209)
258 * Get Allocated Resource Descriptors Command (indirect 0x020A)
260 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00
261 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01
262 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02
263 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
264 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
265 #define ICE_AQC_RES_TYPE_RECIPE 0x05
266 #define ICE_AQC_RES_TYPE_PROFILE 0x06
267 #define ICE_AQC_RES_TYPE_SWID 0x07
268 #define ICE_AQC_RES_TYPE_VSI 0x08
269 #define ICE_AQC_RES_TYPE_FLU 0x09
270 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A
271 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B
272 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C
273 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20
274 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
275 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
276 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
277 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30
278 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48
279 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49
280 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50
281 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51
282 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
283 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
284 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
285 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
286 /* Resource types 0x62-67 are reserved for Hash profile builder */
287 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68
288 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69
290 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
291 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
292 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
294 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
296 #define ICE_AQC_RES_TYPE_S 0
297 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
299 /* Get Resource Allocation command (indirect 0x0204) */
300 struct ice_aqc_get_res_alloc {
301 __le16 resp_elem_num; /* Used in response, reserved in command */
307 /* Get Resource Allocation Response Buffer per response */
308 struct ice_aqc_get_res_resp_elem {
309 __le16 res_type; /* Types defined above cmd 0x0204 */
310 __le16 total_capacity; /* Resources available to all PF's */
311 __le16 total_function; /* Resources allocated for a PF */
312 __le16 total_shared; /* Resources allocated as shared */
313 __le16 total_free; /* Resources un-allocated/not reserved by any PF */
316 /* Buffer for Get Resource command */
317 struct ice_aqc_get_res_resp {
318 /* Number of resource entries to be calculated using
319 * datalen/sizeof(struct ice_aqc_cmd_resp)).
320 * Value of 'datalen' gets updated as part of response.
322 struct ice_aqc_get_res_resp_elem elem[1];
326 /* Allocate Resources command (indirect 0x0208)
327 * Free Resources command (indirect 0x0209)
329 struct ice_aqc_alloc_free_res_cmd {
330 __le16 num_entries; /* Number of Resource entries */
337 /* Resource descriptor */
338 struct ice_aqc_res_elem {
346 /* Buffer for Allocate/Free Resources commands */
347 struct ice_aqc_alloc_free_res_elem {
348 __le16 res_type; /* Types defined above cmd 0x0204 */
349 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
350 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
351 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
353 struct ice_aqc_res_elem elem[1];
357 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */
358 struct ice_aqc_get_allocd_res_desc {
361 __le16 res; /* Types defined above cmd 0x0204 */
376 struct ice_aqc_get_allocd_res_desc_resp {
377 struct ice_aqc_res_elem elem[1];
381 /* Add VSI (indirect 0x0210)
382 * Update VSI (indirect 0x0211)
383 * Get VSI (indirect 0x0212)
384 * Free VSI (indirect 0x0213)
386 struct ice_aqc_add_get_update_free_vsi {
388 #define ICE_AQ_VSI_NUM_S 0
389 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
390 #define ICE_AQ_VSI_IS_VALID BIT(15)
392 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
396 #define ICE_AQ_VSI_TYPE_S 0
397 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
398 #define ICE_AQ_VSI_TYPE_VF 0x0
399 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
400 #define ICE_AQ_VSI_TYPE_PF 0x2
401 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
407 /* Response descriptor for:
408 * Add VSI (indirect 0x0210)
409 * Update VSI (indirect 0x0211)
410 * Free VSI (indirect 0x0213)
412 struct ice_aqc_add_update_free_vsi_resp {
422 struct ice_aqc_get_vsi_resp {
425 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values.
426 * These are found above in struct ice_aqc_add_get_update_free_vsi.
436 struct ice_aqc_vsi_props {
437 __le16 valid_sections;
438 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
439 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
440 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
441 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
442 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
443 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
444 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
445 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
446 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
447 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
448 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
452 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
453 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
454 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
456 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
457 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
458 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
459 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
460 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
462 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
463 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
464 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
465 /* security section */
467 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
468 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
469 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
470 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
471 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
474 __le16 pvid; /* VLANS include priority bits */
475 u8 pvlan_reserved[2];
477 #define ICE_AQ_VSI_VLAN_MODE_S 0
478 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
479 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
480 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
481 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
482 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
483 #define ICE_AQ_VSI_VLAN_EMOD_S 3
484 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
485 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
486 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
487 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
488 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
489 u8 pvlan_reserved2[3];
490 /* ingress egress up sections */
491 __le32 ingress_table; /* bitmap, 3 bits per up */
492 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
493 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
494 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
495 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
496 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
497 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
498 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
499 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
500 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
501 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
502 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
503 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
504 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
505 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
506 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
507 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
508 __le32 egress_table; /* same defines as for ingress table */
509 /* outer tags section */
512 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
513 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
514 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
515 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
516 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
517 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
518 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
519 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
520 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
521 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
522 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
523 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
524 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
525 u8 outer_tag_reserved;
526 /* queue mapping section */
527 __le16 mapping_flags;
528 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
529 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
530 __le16 q_mapping[16];
531 #define ICE_AQ_VSI_Q_S 0
532 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
533 __le16 tc_mapping[8];
534 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
535 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
536 #define ICE_AQ_VSI_TC_Q_NUM_S 11
537 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
538 /* queueing option section */
540 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
541 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
542 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
543 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
544 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
545 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
546 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
547 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
548 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
549 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
550 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
551 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
552 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
554 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
555 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
556 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
558 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
559 u8 q_opt_reserved[3];
560 /* outer up section */
561 __le32 outer_up_table; /* same structure and defines as ingress tbl */
563 __le16 sect_10_reserved;
564 /* flow director section */
566 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
567 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
568 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
569 __le16 max_fd_fltr_dedicated;
570 __le16 max_fd_fltr_shared;
572 #define ICE_AQ_VSI_FD_DEF_Q_S 0
573 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
574 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
575 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
576 __le16 fd_report_opt;
577 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
578 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
579 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
580 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
581 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
584 #define ICE_AQ_VSI_PASID_ID_S 0
585 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
586 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
591 /* Add/update mirror rule - direct (0x0260) */
592 #define ICE_AQC_RULE_ID_VALID_S 7
593 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S)
594 #define ICE_AQC_RULE_ID_S 0
595 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S)
597 /* Following defines to be used while processing caller specified mirror list
600 /* Action: Byte.bit (1.7)
601 * 0 = Remove VSI from mirror rule
602 * 1 = Add VSI to mirror rule
604 #define ICE_AQC_RULE_ACT_S 15
605 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S)
606 /* Action: 1.2:0.0 = Mirrored VSI */
607 #define ICE_AQC_RULE_MIRRORED_VSI_S 0
608 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S)
610 /* This is to be used by add/update mirror rule Admin Queue command.
611 * In case of add mirror rule - if rule ID is specified as
612 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool.
613 * If specified rule_id is valid, then it is used. If specified rule_id
614 * is in use then new mirroring rule is added.
616 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF
618 struct ice_aqc_add_update_mir_rule {
622 #define ICE_AQC_RULE_TYPE_S 0
623 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S)
624 /* VPORT ingress/egress */
625 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1
626 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2
627 /* Physical port ingress mirroring.
628 * All traffic received by this port
630 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6
631 /* Physical port egress mirroring. All traffic sent by this port */
632 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7
634 /* Number of mirrored entries.
635 * The values are in the command buffer
639 /* Destination VSI */
645 /* Delete mirror rule - direct(0x0261) */
646 struct ice_aqc_delete_mir_rule {
650 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of
651 * the PF allocated resources, otherwise it is returned to the
654 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0
655 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S)
661 /* Set/Get storm config - (direct 0x0280, 0x0281) */
662 /* This structure holds get storm configuration response and same structure
663 * is used to perform set_storm_cfg
665 struct ice_aqc_storm_cfg {
666 __le32 bcast_thresh_size;
667 __le32 mcast_thresh_size;
668 /* Bit 18:0 - Traffic upper threshold size
669 * Bit 31:19 - Reserved
671 #define ICE_AQ_THRESHOLD_S 0
672 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S)
674 __le32 storm_ctrl_ctrl;
675 /* Bit 0: MDIPW - Drop Multicast packets in previous window
676 * Bit 1: MDICW - Drop multicast packets in current window
677 * Bit 2: BDIPW - Drop broadcast packets in previous window
678 * Bit 3: BDICW - Drop broadcast packets in current window
680 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0)
681 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1)
682 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2)
683 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3)
684 /* Bit 7:5 : Reserved */
685 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The
686 * interval size for applying ingress broadcast or multicast storm
689 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8
690 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \
691 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S)
696 #define ICE_MAX_NUM_RECIPES 64
698 /* Add/Get Recipe (indirect 0x0290/0x0292)*/
699 struct ice_aqc_add_get_recipe {
700 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */
701 __le16 return_index; /* Input, used for Get cmd only */
707 struct ice_aqc_recipe_content {
709 #define ICE_AQ_RECIPE_ID_S 0
710 #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S)
711 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7)
712 #define ICE_AQ_SW_ID_LKUP_IDX 0
714 #define ICE_AQ_RECIPE_LKUP_DATA_S 0
715 #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)
716 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7)
717 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF
720 #define ICE_AQ_RECIPE_RESULT_DATA_S 0
721 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S)
722 #define ICE_AQ_RECIPE_RESULT_EN BIT(7)
724 u8 act_ctrl_join_priority;
725 u8 act_ctrl_fwd_priority;
726 #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0
727 #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S)
729 #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0)
730 #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1)
731 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2)
732 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4
733 #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S)
736 #define ICE_AQ_RECIPE_DFLT_ACT_S 0
737 #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S)
738 #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31)
741 struct ice_aqc_recipe_data_elem {
744 #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0)
748 struct ice_aqc_recipe_content content;
752 /* This struct contains a number of entries as per the
753 * num_sub_recipes in the command
755 struct ice_aqc_add_get_recipe_data {
756 struct ice_aqc_recipe_data_elem recipe[1];
759 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */
760 struct ice_aqc_recipe_to_profile {
763 ice_declare_bitmap(recipe_assoc, ICE_MAX_NUM_RECIPES);
766 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
768 struct ice_aqc_sw_rules {
769 /* ops: add switch rules, referring the number of rules.
770 * ops: update switch rules, referring the number of filters
771 * ops: remove switch rules, referring the entry index.
772 * ops: get switch rules, referring to the number of filters.
774 __le16 num_rules_fltr_entry_index;
782 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
783 * This structures describes the lookup rules and associated actions. "index"
784 * is returned as part of a response to a successful Add command, and can be
785 * used to identify the rule for Update/Get/Remove commands.
787 struct ice_sw_rule_lkup_rx_tx {
789 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
790 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
794 /* Bit 0:1 - Action type */
795 #define ICE_SINGLE_ACT_TYPE_S 0x00
796 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
798 /* Bit 2 - Loop back enable
801 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
802 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
804 /* Action type = 0 - Forward to VSI or VSI list */
805 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
807 #define ICE_SINGLE_ACT_VSI_ID_S 4
808 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
809 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
810 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
811 /* This bit needs to be set if action is forward to VSI list */
812 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
813 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
814 #define ICE_SINGLE_ACT_DROP BIT(18)
816 /* Action type = 1 - Forward to Queue of Queue group */
817 #define ICE_SINGLE_ACT_TO_Q 0x1
818 #define ICE_SINGLE_ACT_Q_INDEX_S 4
819 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
820 #define ICE_SINGLE_ACT_Q_REGION_S 15
821 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
822 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
824 /* Action type = 2 - Prune */
825 #define ICE_SINGLE_ACT_PRUNE 0x2
826 #define ICE_SINGLE_ACT_EGRESS BIT(15)
827 #define ICE_SINGLE_ACT_INGRESS BIT(16)
828 #define ICE_SINGLE_ACT_PRUNET BIT(17)
829 /* Bit 18 should be set to 0 for this action */
831 /* Action type = 2 - Pointer */
832 #define ICE_SINGLE_ACT_PTR 0x2
833 #define ICE_SINGLE_ACT_PTR_VAL_S 4
834 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
835 /* Bit 18 should be set to 1 */
836 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
838 /* Action type = 3 - Other actions. Last two bits
839 * are other action identifier
841 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
842 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
843 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
844 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
846 /* Bit 17:18 - Defines other actions */
847 /* Other action = 0 - Mirror VSI */
848 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
849 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
850 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
851 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
853 /* Other action = 3 - Set Stat count */
854 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
855 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
856 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
857 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
859 __le16 index; /* The index of the rule in the lookup table */
860 /* Length and values of the header to be matched per recipe or
869 /* Add/Update/Remove large action command/response entry
870 * "index" is returned as part of a response to a successful Add command, and
871 * can be used to identify the action for Update/Get/Remove commands.
873 struct ice_sw_rule_lg_act {
874 __le16 index; /* Index in large action table */
876 __le32 act[1]; /* array of size for actions */
877 /* Max number of large actions */
878 #define ICE_MAX_LG_ACT 4
879 /* Bit 0:1 - Action type */
880 #define ICE_LG_ACT_TYPE_S 0
881 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
883 /* Action type = 0 - Forward to VSI or VSI list */
884 #define ICE_LG_ACT_VSI_FORWARDING 0
885 #define ICE_LG_ACT_VSI_ID_S 3
886 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
887 #define ICE_LG_ACT_VSI_LIST_ID_S 3
888 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
889 /* This bit needs to be set if action is forward to VSI list */
890 #define ICE_LG_ACT_VSI_LIST BIT(13)
892 #define ICE_LG_ACT_VALID_BIT BIT(16)
894 /* Action type = 1 - Forward to Queue of Queue group */
895 #define ICE_LG_ACT_TO_Q 0x1
896 #define ICE_LG_ACT_Q_INDEX_S 3
897 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
898 #define ICE_LG_ACT_Q_REGION_S 14
899 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
900 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
902 /* Action type = 2 - Prune */
903 #define ICE_LG_ACT_PRUNE 0x2
904 #define ICE_LG_ACT_EGRESS BIT(14)
905 #define ICE_LG_ACT_INGRESS BIT(15)
906 #define ICE_LG_ACT_PRUNET BIT(16)
908 /* Action type = 3 - Mirror VSI */
909 #define ICE_LG_OTHER_ACT_MIRROR 0x3
910 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
911 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
913 /* Action type = 5 - Generic Value */
914 #define ICE_LG_ACT_GENERIC 0x5
915 #define ICE_LG_ACT_GENERIC_VALUE_S 3
916 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
917 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
918 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
919 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
920 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
921 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
923 /* Action = 7 - Set Stat count */
924 #define ICE_LG_ACT_STAT_COUNT 0x7
925 #define ICE_LG_ACT_STAT_COUNT_S 3
926 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
930 /* Add/Update/Remove VSI list command/response entry
931 * "index" is returned as part of a response to a successful Add command, and
932 * can be used to identify the VSI list for Update/Get/Remove commands.
934 struct ice_sw_rule_vsi_list {
935 __le16 index; /* Index of VSI/Prune list */
937 __le16 vsi[1]; /* Array of number_vsi VSI numbers */
942 /* Query VSI list command/response entry */
943 struct ice_sw_rule_vsi_list_query {
945 ice_declare_bitmap(vsi_list, ICE_MAX_VSI);
951 /* Add switch rule response:
952 * Content of return buffer is same as the input buffer. The status field and
953 * LUT index are updated as part of the response
955 struct ice_aqc_sw_rules_elem {
956 __le16 type; /* Switch rule type, one of T_... */
957 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
958 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
959 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
960 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
961 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
962 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
963 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
966 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
967 struct ice_sw_rule_lg_act lg_act;
968 struct ice_sw_rule_vsi_list vsi_list;
969 struct ice_sw_rule_vsi_list_query vsi_list_query;
976 /* PFC Ignore (direct 0x0301)
977 * The command and response use the same descriptor structure
979 struct ice_aqc_pfc_ignore {
981 u8 cmd_flags; /* unused in response */
982 #define ICE_AQC_PFC_IGNORE_SET BIT(7)
983 #define ICE_AQC_PFC_IGNORE_CLEAR 0
987 /* Set PFC Mode (direct 0x0303)
988 * Query PFC Mode (direct 0x0302)
990 struct ice_aqc_set_query_pfc_mode {
992 /* For Set Command response, reserved in all other cases */
993 #define ICE_AQC_PFC_NOT_CONFIGURED 0
994 /* For Query Command response, reserved in all other cases */
995 #define ICE_AQC_DCB_DIS 0
996 #define ICE_AQC_PFC_VLAN_BASED_PFC 1
997 #define ICE_AQC_PFC_DSCP_BASED_PFC 2
1001 /* Set DCB Parameters (direct 0x0306) */
1002 struct ice_aqc_set_dcb_params {
1003 u8 cmd_flags; /* unused in response */
1004 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0)
1005 u8 valid_flags; /* unused in response */
1006 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0)
1011 /* Get Default Topology (indirect 0x0400) */
1012 struct ice_aqc_get_topo {
1022 /* Update TSE (indirect 0x0403)
1023 * Get TSE (indirect 0x0404)
1024 * Add TSE (indirect 0x0401)
1025 * Delete TSE (indirect 0x040F)
1026 * Move TSE (indirect 0x0408)
1027 * Suspend Nodes (indirect 0x0409)
1028 * Resume Nodes (indirect 0x040A)
1030 struct ice_aqc_sched_elem_cmd {
1031 __le16 num_elem_req; /* Used by commands */
1032 __le16 num_elem_resp; /* Used by responses */
1039 /* This is the buffer for:
1040 * Suspend Nodes (indirect 0x0409)
1041 * Resume Nodes (indirect 0x040A)
1043 struct ice_aqc_suspend_resume_elem {
1048 struct ice_aqc_txsched_move_grp_info_hdr {
1049 __le32 src_parent_teid;
1050 __le32 dest_parent_teid;
1056 struct ice_aqc_move_elem {
1057 struct ice_aqc_txsched_move_grp_info_hdr hdr;
1062 struct ice_aqc_elem_info_bw {
1063 __le16 bw_profile_idx;
1068 struct ice_aqc_txsched_elem {
1069 u8 elem_type; /* Special field, reserved for some aq calls */
1070 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
1071 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
1072 #define ICE_AQC_ELEM_TYPE_TC 0x2
1073 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
1074 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
1075 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
1076 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
1078 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
1079 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
1080 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
1081 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
1083 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
1084 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
1085 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
1086 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
1087 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
1088 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
1089 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
1090 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
1091 u8 flags; /* Special field, reserved for some aq calls */
1092 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
1093 struct ice_aqc_elem_info_bw cir_bw;
1094 struct ice_aqc_elem_info_bw eir_bw;
1100 struct ice_aqc_txsched_elem_data {
1103 struct ice_aqc_txsched_elem data;
1107 struct ice_aqc_txsched_topo_grp_info_hdr {
1114 struct ice_aqc_add_elem {
1115 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1116 struct ice_aqc_txsched_elem_data generic[1];
1120 struct ice_aqc_conf_elem {
1121 struct ice_aqc_txsched_elem_data generic[1];
1125 struct ice_aqc_get_elem {
1126 struct ice_aqc_txsched_elem_data generic[1];
1130 struct ice_aqc_get_topo_elem {
1131 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1132 struct ice_aqc_txsched_elem_data
1133 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1137 struct ice_aqc_delete_elem {
1138 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1143 /* Query Port ETS (indirect 0x040E)
1145 * This indirect command is used to query port TC node configuration.
1147 struct ice_aqc_query_port_ets {
1154 struct ice_aqc_port_ets_elem {
1157 /* 3 bits for UP per TC 0-7, 4th byte reserved */
1160 __le32 port_eir_prof_id;
1161 __le32 port_cir_prof_id;
1162 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
1163 __le32 tc_node_prio;
1164 #define ICE_TC_NODE_PRIO_S 0x4
1166 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
1170 /* Rate limiting profile for
1171 * Add RL profile (indirect 0x0410)
1172 * Query RL profile (indirect 0x0411)
1173 * Remove RL profile (indirect 0x0415)
1174 * These indirect commands acts on single or multiple
1175 * RL profiles with specified data.
1177 struct ice_aqc_rl_profile {
1178 __le16 num_profiles;
1179 __le16 num_processed; /* Only for response. Reserved in Command. */
1186 struct ice_aqc_rl_profile_elem {
1189 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
1190 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
1191 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
1192 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
1193 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
1194 /* The following flag is used for Query RL Profile Data */
1195 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
1196 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
1199 __le16 max_burst_size;
1201 __le16 wake_up_calc;
1206 struct ice_aqc_rl_profile_generic_elem {
1207 struct ice_aqc_rl_profile_elem generic[1];
1212 /* Configure L2 Node CGD (indirect 0x0414)
1213 * This indirect command allows configuring a congestion domain for given L2
1214 * node TEIDs in the scheduler topology.
1216 struct ice_aqc_cfg_l2_node_cgd {
1217 __le16 num_l2_nodes;
1224 struct ice_aqc_cfg_l2_node_cgd_elem {
1231 struct ice_aqc_cfg_l2_node_cgd_data {
1232 struct ice_aqc_cfg_l2_node_cgd_elem elem[1];
1236 /* Query Scheduler Resource Allocation (indirect 0x0412)
1237 * This indirect command retrieves the scheduler resources allocated by
1238 * EMP Firmware to the given PF.
1240 struct ice_aqc_query_txsched_res {
1247 struct ice_aqc_generic_sched_props {
1249 __le16 logical_levels;
1250 u8 flattening_bitmap;
1259 struct ice_aqc_layer_props {
1262 __le16 max_device_nodes;
1263 __le16 max_pf_nodes;
1265 __le16 max_sibl_grp_sz;
1266 __le16 max_cir_rl_profiles;
1267 __le16 max_eir_rl_profiles;
1268 __le16 max_srl_profiles;
1273 struct ice_aqc_query_txsched_res_resp {
1274 struct ice_aqc_generic_sched_props sched_props;
1275 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1279 /* Query Node to Root Topology (indirect 0x0413)
1280 * This command uses ice_aqc_get_elem as its data buffer.
1282 struct ice_aqc_query_node_to_root {
1284 __le32 num_nodes; /* Response only */
1290 /* Get PHY capabilities (indirect 0x0600) */
1291 struct ice_aqc_get_phy_caps {
1295 /* 18.0 - Report qualified modules */
1296 #define ICE_AQC_GET_PHY_RQM BIT(0)
1297 /* 18.1 - 18.2 : Report mode
1298 * 00b - Report NVM capabilities
1299 * 01b - Report topology capabilities
1300 * 10b - Report SW configured
1302 #define ICE_AQC_REPORT_MODE_S 1
1303 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
1304 #define ICE_AQC_REPORT_NVM_CAP 0
1305 #define ICE_AQC_REPORT_TOPO_CAP BIT(1)
1306 #define ICE_AQC_REPORT_SW_CFG BIT(2)
1313 /* This is #define of PHY type (Extended):
1314 * The first set of defines is for phy_type_low.
1316 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1317 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1318 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1319 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
1320 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
1321 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
1322 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1323 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1324 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1325 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
1326 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1327 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1328 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1329 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
1330 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
1331 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
1332 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
1333 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
1334 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
1335 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
1336 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
1337 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
1338 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1339 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1340 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1341 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1342 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1343 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1344 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1345 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1346 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1347 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1348 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1349 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1350 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1351 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1352 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1353 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1354 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1355 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1356 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1357 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1358 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1359 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1360 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1361 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1362 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1363 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1364 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1365 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1366 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1367 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1368 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1369 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1370 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1371 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1372 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1373 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1374 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1375 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1376 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1377 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1378 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1379 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1380 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1381 /* The second set of defines is for phy_type_high. */
1382 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1383 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1384 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1385 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1386 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1387 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19
1389 struct ice_aqc_get_phy_caps_data {
1390 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1391 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1393 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1394 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1395 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1396 #define ICE_AQC_PHY_EN_LINK BIT(3)
1397 #define ICE_AQC_PHY_AN_MODE BIT(4)
1398 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5)
1399 #define ICE_AQC_PHY_EN_LESM BIT(6)
1400 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1401 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0)
1403 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1405 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1406 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1407 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1408 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1409 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1410 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1411 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1412 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7)
1413 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8)
1414 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9)
1415 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10)
1417 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1419 u8 link_fec_options;
1420 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1421 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1422 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1423 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1424 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1425 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1426 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1427 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
1428 u8 rsvd1; /* Byte 35 reserved */
1429 u8 extended_compliance_code;
1430 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1431 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1432 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1433 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1434 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1435 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1436 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1437 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1438 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1439 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1440 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1441 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1442 u8 qualified_module_count;
1443 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1444 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1451 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1455 /* Set PHY capabilities (direct 0x0601)
1456 * NOTE: This command must be followed by setup link and restart auto-neg
1458 struct ice_aqc_set_phy_cfg {
1466 /* Set PHY config command data structure */
1467 struct ice_aqc_set_phy_cfg_data {
1468 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1469 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1471 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0)
1472 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1473 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1474 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1475 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1476 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1477 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1478 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1480 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1482 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1487 /* Set MAC Config command data structure (direct 0x0603) */
1488 struct ice_aqc_set_mac_cfg {
1489 __le16 max_frame_size;
1491 #define ICE_AQ_SET_MAC_PACE_S 3
1492 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1493 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1494 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1495 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1497 __le16 tx_tmr_value;
1498 __le16 fc_refresh_threshold;
1500 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1501 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1502 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1507 /* Restart AN command data structure (direct 0x0605)
1508 * Also used for response, with only the lport_num field present.
1510 struct ice_aqc_restart_an {
1514 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1515 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1520 /* Get link status (indirect 0x0607), also used for Link Status Event */
1521 struct ice_aqc_get_link_status {
1525 #define ICE_AQ_LSE_M 0x3
1526 #define ICE_AQ_LSE_NOP 0x0
1527 #define ICE_AQ_LSE_DIS 0x2
1528 #define ICE_AQ_LSE_ENA 0x3
1529 /* only response uses this flag */
1530 #define ICE_AQ_LSE_IS_ENABLED 0x1
1537 /* Get link status response data structure, also used for Link Status Event */
1538 struct ice_aqc_get_link_status_data {
1539 u8 topo_media_conflict;
1540 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1541 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1542 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1543 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1544 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1545 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1546 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1548 #define ICE_AQ_LINK_CFG_ERR BIT(0)
1550 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1551 #define ICE_AQ_LINK_FAULT BIT(1)
1552 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1553 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1554 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1555 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1556 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1557 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1559 #define ICE_AQ_AN_COMPLETED BIT(0)
1560 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1561 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1562 #define ICE_AQ_FEC_EN BIT(3)
1563 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1564 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1565 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1566 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1568 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1569 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1570 /* Port Tx Suspended */
1571 #define ICE_AQ_LINK_TX_S 2
1572 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1573 #define ICE_AQ_LINK_TX_ACTIVE 0
1574 #define ICE_AQ_LINK_TX_DRAINED 1
1575 #define ICE_AQ_LINK_TX_FLUSHED 3
1577 __le16 max_frame_size;
1579 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1580 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1581 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1582 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
1584 #define ICE_AQ_CFG_PACING_S 3
1585 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1586 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1587 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1588 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1589 /* External Device Power Ability */
1591 #define ICE_AQ_PWR_CLASS_M 0x3
1592 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1593 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1594 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1595 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1596 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1597 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1599 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1600 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1601 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1602 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1603 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1604 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1605 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1606 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1607 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1608 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1609 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1610 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1611 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1612 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1613 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1617 /* Set event mask command (direct 0x0613) */
1618 struct ice_aqc_set_event_mask {
1622 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1623 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1624 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1625 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1626 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1627 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1628 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1629 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1630 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1636 /* Set MAC Loopback command (direct 0x0620) */
1637 struct ice_aqc_set_mac_lb {
1639 #define ICE_AQ_MAC_LB_EN BIT(0)
1640 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1648 /* Set Port Identification LED (direct, 0x06E9) */
1649 struct ice_aqc_set_port_id_led {
1652 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0)
1654 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1655 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1661 /* NVM Read command (indirect 0x0701)
1662 * NVM Erase commands (direct 0x0702)
1663 * NVM Update commands (indirect 0x0703)
1665 struct ice_aqc_nvm {
1669 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1670 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1671 #define ICE_AQC_NVM_PRESERVATION_S 1
1672 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1673 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1674 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1675 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1676 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1677 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1678 __le16 module_typeid;
1680 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1686 /* Used for 0x0704 as well as for 0x0705 commands */
1687 struct ice_aqc_nvm_cfg {
1689 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
1690 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
1691 #define ICE_AQC_ANVM_NEW_CFG BIT(2)
1701 struct ice_aqc_nvm_cfg_data {
1703 __le16 field_options;
1708 /* NVM Checksum Command (direct, 0x0706) */
1709 struct ice_aqc_nvm_checksum {
1711 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1712 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1714 __le16 checksum; /* Used only by response */
1715 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1722 /* Get LLDP MIB (indirect 0x0A00)
1723 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1724 * as the format is the same.
1726 struct ice_aqc_lldp_get_mib {
1728 #define ICE_AQ_LLDP_MIB_TYPE_S 0
1729 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1730 #define ICE_AQ_LLDP_MIB_LOCAL 0
1731 #define ICE_AQ_LLDP_MIB_REMOTE 1
1732 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1733 #define ICE_AQ_LLDP_BRID_TYPE_S 2
1734 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1735 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1736 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1737 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1738 #define ICE_AQ_LLDP_TX_S 0x4
1739 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1740 #define ICE_AQ_LLDP_TX_ACTIVE 0
1741 #define ICE_AQ_LLDP_TX_SUSPENDED 1
1742 #define ICE_AQ_LLDP_TX_FLUSHED 3
1743 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1744 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1745 * Get LLDP MIB (0x0A00) response only.
1755 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1756 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1757 struct ice_aqc_lldp_set_mib_change {
1759 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1760 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1764 /* Add LLDP TLV (indirect 0x0A02)
1765 * Delete LLDP TLV (indirect 0x0A04)
1767 struct ice_aqc_lldp_add_delete_tlv {
1768 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1776 /* Update LLDP TLV (indirect 0x0A03) */
1777 struct ice_aqc_lldp_update_tlv {
1778 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1787 /* Stop LLDP (direct 0x0A05) */
1788 struct ice_aqc_lldp_stop {
1790 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1791 #define ICE_AQ_LLDP_AGENT_STOP 0x0
1792 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1793 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1797 /* Start LLDP (direct 0x0A06) */
1798 struct ice_aqc_lldp_start {
1800 #define ICE_AQ_LLDP_AGENT_START BIT(0)
1801 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1805 /* Get CEE DCBX Oper Config (0x0A07)
1806 * The command uses the generic descriptor struct and
1807 * returns the struct below as an indirect response.
1809 struct ice_aqc_get_cee_dcb_cfg_resp {
1814 __le16 oper_app_prio;
1815 #define ICE_AQC_CEE_APP_FCOE_S 0
1816 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1817 #define ICE_AQC_CEE_APP_ISCSI_S 3
1818 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1819 #define ICE_AQC_CEE_APP_FIP_S 8
1820 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1822 #define ICE_AQC_CEE_PG_STATUS_S 0
1823 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1824 #define ICE_AQC_CEE_PFC_STATUS_S 3
1825 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1826 #define ICE_AQC_CEE_FCOE_STATUS_S 8
1827 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1828 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
1829 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1830 #define ICE_AQC_CEE_FIP_STATUS_S 16
1831 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1835 /* Set Local LLDP MIB (indirect 0x0A08)
1836 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1838 struct ice_aqc_lldp_set_local_mib {
1840 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1841 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1842 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1843 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1844 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1852 struct ice_aqc_lldp_set_local_mib_resp {
1854 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0)
1855 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0
1856 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M
1860 /* Stop/Start LLDP Agent (direct 0x0A09)
1861 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1862 * The same structure is used for the response, with the command field
1863 * being used as the status field.
1865 struct ice_aqc_lldp_stop_start_specific_agent {
1867 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
1868 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1869 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1874 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1875 struct ice_aqc_get_set_rss_key {
1876 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1877 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1878 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1886 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1887 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1888 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1889 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1890 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1893 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer
1894 * @standard_rss_key: 40 most significant bytes of hash key
1895 * @extended_hash_key: 12 least significant bytes of hash key
1897 * Set/Get 40 byte hash key using standard_rss_key field, and set
1898 * extended_hash_key field to zero. Set/Get 52 byte hash key using
1899 * standard_rss_key field for 40 most significant bytes and the
1900 * extended_hash_key field for the 12 least significant bytes of hash key.
1902 struct ice_aqc_get_set_rss_keys {
1903 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1904 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1908 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1909 struct ice_aqc_get_set_rss_lut {
1910 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1911 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1912 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1914 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1915 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1916 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1918 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1919 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1920 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1922 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1923 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1924 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1926 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1927 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1928 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1929 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1930 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1931 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1933 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1934 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1935 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1944 /* Clear FD Table Command (direct, 0x0B06) */
1945 struct ice_aqc_clear_fd_table {
1947 #define CL_FD_VM_VF_TYPE_VSI_IDX 1
1948 #define CL_FD_VM_VF_TYPE_PF_IDX 2
1957 /* Add Tx LAN Queues (indirect 0x0C30) */
1958 struct ice_aqc_add_txqs {
1967 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
1968 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1970 struct ice_aqc_add_txqs_perq {
1976 struct ice_aqc_txsched_elem info;
1980 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1981 * is an array of the following structs. Please note that the length of
1982 * each struct ice_aqc_add_tx_qgrp is variable due
1983 * to the variable number of queues in each group!
1985 struct ice_aqc_add_tx_qgrp {
1989 struct ice_aqc_add_txqs_perq txqs[1];
1993 /* Disable Tx LAN Queues (indirect 0x0C31) */
1994 struct ice_aqc_dis_txqs {
1996 #define ICE_AQC_Q_DIS_CMD_S 0
1997 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1998 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1999 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
2000 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
2001 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
2002 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
2003 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
2005 __le16 vmvf_and_timeout;
2006 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
2007 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
2008 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
2009 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
2010 __le32 blocked_cgds;
2016 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
2017 * contains the following structures, arrayed one after the
2019 * Note: Since the q_id is 16 bits wide, if the
2020 * number of queues is even, then 2 bytes of alignment MUST be
2021 * added before the start of the next group, to allow correct
2022 * alignment of the parent_teid field.
2024 struct ice_aqc_dis_txq_item {
2028 /* The length of the q_id array varies according to num_qs */
2030 /* This only applies from F8 onward */
2031 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
2032 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
2033 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2034 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
2035 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2039 struct ice_aqc_dis_txq {
2040 struct ice_aqc_dis_txq_item qgrps[1];
2044 /* Tx LAN Queues Cleanup Event (0x0C31) */
2045 struct ice_aqc_txqs_cleanup {
2052 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */
2053 struct ice_aqc_move_txqs {
2055 #define ICE_AQC_Q_CMD_TYPE_S 0
2056 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S)
2057 #define ICE_AQC_Q_CMD_TYPE_MOVE 1
2058 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2
2059 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3
2060 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2)
2061 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3)
2065 #define ICE_AQC_Q_CMD_TIMEOUT_S 2
2066 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
2067 __le32 blocked_cgds;
2073 /* This is the descriptor of each queue entry for the move Tx LAN Queues
2076 struct ice_aqc_move_txqs_elem {
2084 struct ice_aqc_move_txqs_data {
2087 struct ice_aqc_move_txqs_elem txqs[1];
2092 /* Download Package (indirect 0x0C40) */
2093 /* Also used for Update Package (indirect 0x0C42) */
2094 struct ice_aqc_download_pkg {
2096 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
2103 struct ice_aqc_download_pkg_resp {
2104 __le32 error_offset;
2110 /* Get Package Info List (indirect 0x0C43) */
2111 struct ice_aqc_get_pkg_info_list {
2118 /* Version format for packages */
2119 struct ice_pkg_ver {
2126 #define ICE_PKG_NAME_SIZE 32
2128 struct ice_aqc_get_pkg_info {
2129 struct ice_pkg_ver ver;
2130 char name[ICE_PKG_NAME_SIZE];
2133 u8 is_active_at_boot;
2137 /* Get Package Info List response buffer format (0x0C43) */
2138 struct ice_aqc_get_pkg_info_resp {
2140 struct ice_aqc_get_pkg_info pkg_info[1];
2146 /* Lan Queue Overflow Event (direct, 0x1001) */
2147 struct ice_aqc_event_lan_overflow {
2148 __le32 prtdcb_ruptq;
2155 /* Configure Firmware Logging Command (indirect 0xFF09)
2156 * Logging Information Read Response (indirect 0xFF10)
2157 * Note: The 0xFF10 command has no input parameters.
2159 struct ice_aqc_fw_logging {
2161 #define ICE_AQC_FW_LOG_AQ_EN BIT(0)
2162 #define ICE_AQC_FW_LOG_UART_EN BIT(1)
2164 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
2165 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
2166 #define ICE_AQC_FW_LOG_UART_VALID BIT(1)
2173 enum ice_aqc_fw_logging_mod {
2174 ICE_AQC_FW_LOG_ID_GENERAL = 0,
2175 ICE_AQC_FW_LOG_ID_CTRL,
2176 ICE_AQC_FW_LOG_ID_LINK,
2177 ICE_AQC_FW_LOG_ID_LINK_TOPO,
2178 ICE_AQC_FW_LOG_ID_DNL,
2179 ICE_AQC_FW_LOG_ID_I2C,
2180 ICE_AQC_FW_LOG_ID_SDP,
2181 ICE_AQC_FW_LOG_ID_MDIO,
2182 ICE_AQC_FW_LOG_ID_ADMINQ,
2183 ICE_AQC_FW_LOG_ID_HDMA,
2184 ICE_AQC_FW_LOG_ID_LLDP,
2185 ICE_AQC_FW_LOG_ID_DCBX,
2186 ICE_AQC_FW_LOG_ID_DCB,
2187 ICE_AQC_FW_LOG_ID_NETPROXY,
2188 ICE_AQC_FW_LOG_ID_NVM,
2189 ICE_AQC_FW_LOG_ID_AUTH,
2190 ICE_AQC_FW_LOG_ID_VPD,
2191 ICE_AQC_FW_LOG_ID_IOSF,
2192 ICE_AQC_FW_LOG_ID_PARSER,
2193 ICE_AQC_FW_LOG_ID_SW,
2194 ICE_AQC_FW_LOG_ID_SCHEDULER,
2195 ICE_AQC_FW_LOG_ID_TXQ,
2196 ICE_AQC_FW_LOG_ID_RSVD,
2197 ICE_AQC_FW_LOG_ID_POST,
2198 ICE_AQC_FW_LOG_ID_WATCHDOG,
2199 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
2200 ICE_AQC_FW_LOG_ID_MNG,
2201 ICE_AQC_FW_LOG_ID_SYNCE,
2202 ICE_AQC_FW_LOG_ID_MAX,
2205 /* This is the buffer for both of the logging commands.
2206 * The entry array size depends on the datalen parameter in the descriptor.
2207 * There will be a total of datalen / 2 entries.
2209 struct ice_aqc_fw_logging_data {
2211 #define ICE_AQC_FW_LOG_ID_S 0
2212 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
2214 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
2215 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
2217 #define ICE_AQC_FW_LOG_EN_S 12
2218 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
2219 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
2220 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
2221 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
2222 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
2226 /* Get/Clear FW Log (indirect 0xFF11) */
2227 struct ice_aqc_get_clear_fw_log {
2229 #define ICE_AQC_FW_LOG_CLEAR BIT(0)
2230 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
2238 * struct ice_aq_desc - Admin Queue (AQ) descriptor
2239 * @flags: ICE_AQ_FLAG_* flags
2240 * @opcode: AQ command opcode
2241 * @datalen: length in bytes of indirect/external data buffer
2242 * @retval: return value from firmware
2243 * @cookie_h: opaque data high-half
2244 * @cookie_l: opaque data low-half
2245 * @params: command-specific parameters
2247 * Descriptor format for commands the driver posts on the Admin Transmit Queue
2248 * (ATQ). The firmware writes back onto the command descriptor and returns
2249 * the result of the command. Asynchronous events that are not an immediate
2250 * result of the command are written to the Admin Receive Queue (ARQ) using
2251 * the same descriptor format. Descriptors are in little-endian notation with
2254 struct ice_aq_desc {
2263 struct ice_aqc_generic generic;
2264 struct ice_aqc_get_ver get_ver;
2265 struct ice_aqc_driver_ver driver_ver;
2266 struct ice_aqc_q_shutdown q_shutdown;
2267 struct ice_aqc_req_res res_owner;
2268 struct ice_aqc_manage_mac_read mac_read;
2269 struct ice_aqc_manage_mac_write mac_write;
2270 struct ice_aqc_clear_pxe clear_pxe;
2271 struct ice_aqc_config_no_drop_policy no_drop;
2272 struct ice_aqc_add_update_mir_rule add_update_rule;
2273 struct ice_aqc_delete_mir_rule del_rule;
2274 struct ice_aqc_list_caps get_cap;
2275 struct ice_aqc_get_phy_caps get_phy;
2276 struct ice_aqc_set_phy_cfg set_phy;
2277 struct ice_aqc_restart_an restart_an;
2278 struct ice_aqc_set_port_id_led set_port_id_led;
2279 struct ice_aqc_get_sw_cfg get_sw_conf;
2280 struct ice_aqc_sw_rules sw_rules;
2281 struct ice_aqc_storm_cfg storm_conf;
2282 struct ice_aqc_add_get_recipe add_get_recipe;
2283 struct ice_aqc_recipe_to_profile recipe_to_profile;
2284 struct ice_aqc_get_topo get_topo;
2285 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2286 struct ice_aqc_query_txsched_res query_sched_res;
2287 struct ice_aqc_query_node_to_root query_node_to_root;
2288 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
2289 struct ice_aqc_query_port_ets port_ets;
2290 struct ice_aqc_rl_profile rl_profile;
2291 struct ice_aqc_nvm nvm;
2292 struct ice_aqc_nvm_cfg nvm_cfg;
2293 struct ice_aqc_nvm_checksum nvm_checksum;
2294 struct ice_aqc_pfc_ignore pfc_ignore;
2295 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2296 struct ice_aqc_set_dcb_params set_dcb_params;
2297 struct ice_aqc_lldp_get_mib lldp_get_mib;
2298 struct ice_aqc_lldp_set_mib_change lldp_set_event;
2299 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv;
2300 struct ice_aqc_lldp_update_tlv lldp_update_tlv;
2301 struct ice_aqc_lldp_stop lldp_stop;
2302 struct ice_aqc_lldp_start lldp_start;
2303 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2304 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2305 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2306 struct ice_aqc_get_set_rss_key get_set_rss_key;
2307 struct ice_aqc_clear_fd_table clear_fd_table;
2308 struct ice_aqc_add_txqs add_txqs;
2309 struct ice_aqc_dis_txqs dis_txqs;
2310 struct ice_aqc_txqs_cleanup txqs_cleanup;
2311 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2312 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2313 struct ice_aqc_get_vsi_resp get_vsi_resp;
2314 struct ice_aqc_download_pkg download_pkg;
2315 struct ice_aqc_get_pkg_info_list get_pkg_info_list;
2316 struct ice_aqc_fw_logging fw_logging;
2317 struct ice_aqc_get_clear_fw_log get_clear_fw_log;
2318 struct ice_aqc_set_mac_lb set_mac_lb;
2319 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2320 struct ice_aqc_get_res_alloc get_res;
2321 struct ice_aqc_get_allocd_res_desc get_res_desc;
2322 struct ice_aqc_set_mac_cfg set_mac_cfg;
2323 struct ice_aqc_set_event_mask set_event_mask;
2324 struct ice_aqc_get_link_status get_link_status;
2329 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
2330 #define ICE_AQ_LG_BUF 512
2332 /* Flags sub-structure
2333 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
2334 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
2337 /* command flags and offsets */
2338 #define ICE_AQ_FLAG_DD_S 0
2339 #define ICE_AQ_FLAG_CMP_S 1
2340 #define ICE_AQ_FLAG_ERR_S 2
2341 #define ICE_AQ_FLAG_VFE_S 3
2342 #define ICE_AQ_FLAG_LB_S 9
2343 #define ICE_AQ_FLAG_RD_S 10
2344 #define ICE_AQ_FLAG_VFC_S 11
2345 #define ICE_AQ_FLAG_BUF_S 12
2346 #define ICE_AQ_FLAG_SI_S 13
2347 #define ICE_AQ_FLAG_EI_S 14
2348 #define ICE_AQ_FLAG_FE_S 15
2350 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */
2351 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */
2352 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
2353 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */
2354 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
2355 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
2356 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */
2357 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
2358 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
2359 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */
2360 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */
2364 ICE_AQ_RC_OK = 0, /* Success */
2365 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
2366 ICE_AQ_RC_ENOENT = 2, /* No such element */
2367 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */
2368 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */
2369 ICE_AQ_RC_EIO = 5, /* I/O error */
2370 ICE_AQ_RC_ENXIO = 6, /* No such resource */
2371 ICE_AQ_RC_E2BIG = 7, /* Arg too long */
2372 ICE_AQ_RC_EAGAIN = 8, /* Try again */
2373 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
2374 ICE_AQ_RC_EACCES = 10, /* Permission denied */
2375 ICE_AQ_RC_EFAULT = 11, /* Bad address */
2376 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
2377 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
2378 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
2379 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */
2380 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
2381 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
2382 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */
2383 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
2384 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
2385 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
2386 ICE_AQ_RC_EFBIG = 22, /* File too big */
2387 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */
2388 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
2389 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
2390 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
2391 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
2392 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
2395 /* Admin Queue command opcodes */
2396 enum ice_adminq_opc {
2398 ice_aqc_opc_get_ver = 0x0001,
2399 ice_aqc_opc_driver_ver = 0x0002,
2400 ice_aqc_opc_q_shutdown = 0x0003,
2401 ice_aqc_opc_get_exp_err = 0x0005,
2403 /* resource ownership */
2404 ice_aqc_opc_req_res = 0x0008,
2405 ice_aqc_opc_release_res = 0x0009,
2407 /* device/function capabilities */
2408 ice_aqc_opc_list_func_caps = 0x000A,
2409 ice_aqc_opc_list_dev_caps = 0x000B,
2411 /* manage MAC address */
2412 ice_aqc_opc_manage_mac_read = 0x0107,
2413 ice_aqc_opc_manage_mac_write = 0x0108,
2416 ice_aqc_opc_clear_pxe_mode = 0x0110,
2418 ice_aqc_opc_config_no_drop_policy = 0x0112,
2420 /* internal switch commands */
2421 ice_aqc_opc_get_sw_cfg = 0x0200,
2423 /* Alloc/Free/Get Resources */
2424 ice_aqc_opc_get_res_alloc = 0x0204,
2425 ice_aqc_opc_alloc_res = 0x0208,
2426 ice_aqc_opc_free_res = 0x0209,
2427 ice_aqc_opc_get_allocd_res_desc = 0x020A,
2430 ice_aqc_opc_add_vsi = 0x0210,
2431 ice_aqc_opc_update_vsi = 0x0211,
2432 ice_aqc_opc_get_vsi_params = 0x0212,
2433 ice_aqc_opc_free_vsi = 0x0213,
2435 /* Mirroring rules - add/update, delete */
2436 ice_aqc_opc_add_update_mir_rule = 0x0260,
2437 ice_aqc_opc_del_mir_rule = 0x0261,
2439 /* storm configuration */
2440 ice_aqc_opc_set_storm_cfg = 0x0280,
2441 ice_aqc_opc_get_storm_cfg = 0x0281,
2443 /* recipe commands */
2444 ice_aqc_opc_add_recipe = 0x0290,
2445 ice_aqc_opc_recipe_to_profile = 0x0291,
2446 ice_aqc_opc_get_recipe = 0x0292,
2447 ice_aqc_opc_get_recipe_to_profile = 0x0293,
2449 /* switch rules population commands */
2450 ice_aqc_opc_add_sw_rules = 0x02A0,
2451 ice_aqc_opc_update_sw_rules = 0x02A1,
2452 ice_aqc_opc_remove_sw_rules = 0x02A2,
2453 ice_aqc_opc_get_sw_rules = 0x02A3,
2454 ice_aqc_opc_clear_pf_cfg = 0x02A4,
2457 ice_aqc_opc_pfc_ignore = 0x0301,
2458 ice_aqc_opc_query_pfc_mode = 0x0302,
2459 ice_aqc_opc_set_pfc_mode = 0x0303,
2460 ice_aqc_opc_set_dcb_params = 0x0306,
2462 /* transmit scheduler commands */
2463 ice_aqc_opc_get_dflt_topo = 0x0400,
2464 ice_aqc_opc_add_sched_elems = 0x0401,
2465 ice_aqc_opc_cfg_sched_elems = 0x0403,
2466 ice_aqc_opc_get_sched_elems = 0x0404,
2467 ice_aqc_opc_move_sched_elems = 0x0408,
2468 ice_aqc_opc_suspend_sched_elems = 0x0409,
2469 ice_aqc_opc_resume_sched_elems = 0x040A,
2470 ice_aqc_opc_query_port_ets = 0x040E,
2471 ice_aqc_opc_delete_sched_elems = 0x040F,
2472 ice_aqc_opc_add_rl_profiles = 0x0410,
2473 ice_aqc_opc_query_rl_profiles = 0x0411,
2474 ice_aqc_opc_query_sched_res = 0x0412,
2475 ice_aqc_opc_query_node_to_root = 0x0413,
2476 ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
2477 ice_aqc_opc_remove_rl_profiles = 0x0415,
2480 ice_aqc_opc_get_phy_caps = 0x0600,
2481 ice_aqc_opc_set_phy_cfg = 0x0601,
2482 ice_aqc_opc_set_mac_cfg = 0x0603,
2483 ice_aqc_opc_restart_an = 0x0605,
2484 ice_aqc_opc_get_link_status = 0x0607,
2485 ice_aqc_opc_set_event_mask = 0x0613,
2486 ice_aqc_opc_set_mac_lb = 0x0620,
2487 ice_aqc_opc_set_port_id_led = 0x06E9,
2488 ice_aqc_opc_get_port_options = 0x06EA,
2489 ice_aqc_opc_set_port_option = 0x06EB,
2490 ice_aqc_opc_set_gpio = 0x06EC,
2491 ice_aqc_opc_get_gpio = 0x06ED,
2494 ice_aqc_opc_nvm_read = 0x0701,
2495 ice_aqc_opc_nvm_erase = 0x0702,
2496 ice_aqc_opc_nvm_update = 0x0703,
2497 ice_aqc_opc_nvm_cfg_read = 0x0704,
2498 ice_aqc_opc_nvm_cfg_write = 0x0705,
2499 ice_aqc_opc_nvm_checksum = 0x0706,
2502 ice_aqc_opc_lldp_get_mib = 0x0A00,
2503 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
2504 ice_aqc_opc_lldp_add_tlv = 0x0A02,
2505 ice_aqc_opc_lldp_update_tlv = 0x0A03,
2506 ice_aqc_opc_lldp_delete_tlv = 0x0A04,
2507 ice_aqc_opc_lldp_stop = 0x0A05,
2508 ice_aqc_opc_lldp_start = 0x0A06,
2509 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
2510 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
2511 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
2514 ice_aqc_opc_set_rss_key = 0x0B02,
2515 ice_aqc_opc_set_rss_lut = 0x0B03,
2516 ice_aqc_opc_get_rss_key = 0x0B04,
2517 ice_aqc_opc_get_rss_lut = 0x0B05,
2518 ice_aqc_opc_clear_fd_table = 0x0B06,
2520 /* Tx queue handling commands/events */
2521 ice_aqc_opc_add_txqs = 0x0C30,
2522 ice_aqc_opc_dis_txqs = 0x0C31,
2523 ice_aqc_opc_txqs_cleanup = 0x0C31,
2524 ice_aqc_opc_move_recfg_txqs = 0x0C32,
2526 /* package commands */
2527 ice_aqc_opc_download_pkg = 0x0C40,
2528 ice_aqc_opc_upload_section = 0x0C41,
2529 ice_aqc_opc_update_pkg = 0x0C42,
2530 ice_aqc_opc_get_pkg_info_list = 0x0C43,
2534 /* Standalone Commands/Events */
2535 ice_aqc_opc_event_lan_overflow = 0x1001,
2537 /* debug commands */
2538 ice_aqc_opc_fw_logging = 0xFF09,
2539 ice_aqc_opc_fw_logging_info = 0xFF10,
2540 ice_aqc_opc_get_clear_fw_log = 0xFF11
2543 #endif /* _ICE_ADMINQ_CMD_H_ */