1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 200
15 * ice_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
18 * This function sets the MAC type of the adapter based on the
19 * vendor ID and device ID stored in the HW structure.
21 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
23 enum ice_status status = ICE_SUCCESS;
25 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
27 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) {
28 switch (hw->device_id) {
30 hw->mac_type = ICE_MAC_GENERIC;
34 status = ICE_ERR_DEVICE_NOT_SUPPORTED;
37 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n",
38 hw->mac_type, status);
44 * ice_clear_pf_cfg - Clear PF configuration
45 * @hw: pointer to the hardware structure
47 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
48 * configuration, flow director filters, etc.).
50 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
52 struct ice_aq_desc desc;
54 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
56 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
60 * ice_aq_manage_mac_read - manage MAC address read command
61 * @hw: pointer to the HW struct
62 * @buf: a virtual buffer to hold the manage MAC read response
63 * @buf_size: Size of the virtual buffer
64 * @cd: pointer to command details structure or NULL
66 * This function is used to return per PF station MAC address (0x0107).
67 * NOTE: Upon successful completion of this command, MAC address information
68 * is returned in user specified buffer. Please interpret user specified
69 * buffer as "manage_mac_read" response.
70 * Response such as various MAC addresses are stored in HW struct (port.mac)
71 * ice_aq_discover_caps is expected to be called before this function is called.
73 static enum ice_status
74 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
77 struct ice_aqc_manage_mac_read_resp *resp;
78 struct ice_aqc_manage_mac_read *cmd;
79 struct ice_aq_desc desc;
80 enum ice_status status;
84 cmd = &desc.params.mac_read;
86 if (buf_size < sizeof(*resp))
87 return ICE_ERR_BUF_TOO_SHORT;
89 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
91 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
95 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
96 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
98 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
99 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
103 /* A single port can report up to two (LAN and WoL) addresses */
104 for (i = 0; i < cmd->num_addr; i++)
105 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
106 ice_memcpy(hw->port_info->mac.lan_addr,
107 resp[i].mac_addr, ETH_ALEN,
109 ice_memcpy(hw->port_info->mac.perm_addr,
111 ETH_ALEN, ICE_DMA_TO_NONDMA);
118 * ice_aq_get_phy_caps - returns PHY capabilities
119 * @pi: port information structure
120 * @qual_mods: report qualified modules
121 * @report_mode: report mode capabilities
122 * @pcaps: structure for PHY capabilities to be filled
123 * @cd: pointer to command details structure or NULL
125 * Returns the various PHY capabilities supported on the Port (0x0600)
128 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
129 struct ice_aqc_get_phy_caps_data *pcaps,
130 struct ice_sq_cd *cd)
132 struct ice_aqc_get_phy_caps *cmd;
133 u16 pcaps_size = sizeof(*pcaps);
134 struct ice_aq_desc desc;
135 enum ice_status status;
137 cmd = &desc.params.get_phy;
139 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
140 return ICE_ERR_PARAM;
142 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
145 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
147 cmd->param0 |= CPU_TO_LE16(report_mode);
148 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
150 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
151 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
152 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
159 * ice_aq_get_link_topo_handle - get link topology node return status
160 * @pi: port information structure
161 * @node_type: requested node type
162 * @cd: pointer to command details structure or NULL
164 * Get link topology node return status for specified node type (0x06E0)
166 * Node type cage can be used to determine if cage is present. If AQC
167 * returns error (ENOENT), then no cage present. If no cage present, then
168 * connection type is backplane or BASE-T.
170 static enum ice_status
171 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
172 struct ice_sq_cd *cd)
174 struct ice_aqc_get_link_topo *cmd;
175 struct ice_aq_desc desc;
177 cmd = &desc.params.get_link_topo;
180 return ICE_ERR_PARAM;
182 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
184 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
185 ICE_AQC_LINK_TOPO_NODE_CTX_S);
188 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
190 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
194 * ice_is_media_cage_present
195 * @pi: port information structure
197 * Returns true if media cage is present, else false. If no cage, then
198 * media type is backplane or BASE-T.
200 static bool ice_is_media_cage_present(struct ice_port_info *pi)
202 /* Node type cage can be used to determine if cage is present. If AQC
203 * returns error (ENOENT), then no cage present. If no cage present then
204 * connection type is backplane or BASE-T.
206 return !ice_aq_get_link_topo_handle(pi,
207 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
212 * ice_get_media_type - Gets media type
213 * @pi: port information structure
215 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
217 struct ice_link_status *hw_link_info;
220 return ICE_MEDIA_UNKNOWN;
222 hw_link_info = &pi->phy.link_info;
223 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
224 /* If more than one media type is selected, report unknown */
225 return ICE_MEDIA_UNKNOWN;
227 if (hw_link_info->phy_type_low) {
228 switch (hw_link_info->phy_type_low) {
229 case ICE_PHY_TYPE_LOW_1000BASE_SX:
230 case ICE_PHY_TYPE_LOW_1000BASE_LX:
231 case ICE_PHY_TYPE_LOW_10GBASE_SR:
232 case ICE_PHY_TYPE_LOW_10GBASE_LR:
233 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
234 case ICE_PHY_TYPE_LOW_25GBASE_SR:
235 case ICE_PHY_TYPE_LOW_25GBASE_LR:
236 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
237 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
238 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
239 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
240 case ICE_PHY_TYPE_LOW_50GBASE_SR:
241 case ICE_PHY_TYPE_LOW_50GBASE_FR:
242 case ICE_PHY_TYPE_LOW_50GBASE_LR:
243 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
244 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
245 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
246 case ICE_PHY_TYPE_LOW_100GBASE_DR:
247 return ICE_MEDIA_FIBER;
248 case ICE_PHY_TYPE_LOW_100BASE_TX:
249 case ICE_PHY_TYPE_LOW_1000BASE_T:
250 case ICE_PHY_TYPE_LOW_2500BASE_T:
251 case ICE_PHY_TYPE_LOW_5GBASE_T:
252 case ICE_PHY_TYPE_LOW_10GBASE_T:
253 case ICE_PHY_TYPE_LOW_25GBASE_T:
254 return ICE_MEDIA_BASET;
255 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
256 case ICE_PHY_TYPE_LOW_25GBASE_CR:
257 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
258 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
259 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
260 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
261 case ICE_PHY_TYPE_LOW_50GBASE_CP:
262 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
263 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
264 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
266 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
267 case ICE_PHY_TYPE_LOW_40G_XLAUI:
268 case ICE_PHY_TYPE_LOW_50G_LAUI2:
269 case ICE_PHY_TYPE_LOW_50G_AUI2:
270 case ICE_PHY_TYPE_LOW_50G_AUI1:
271 case ICE_PHY_TYPE_LOW_100G_AUI4:
272 case ICE_PHY_TYPE_LOW_100G_CAUI4:
273 if (ice_is_media_cage_present(pi))
276 case ICE_PHY_TYPE_LOW_1000BASE_KX:
277 case ICE_PHY_TYPE_LOW_2500BASE_KX:
278 case ICE_PHY_TYPE_LOW_2500BASE_X:
279 case ICE_PHY_TYPE_LOW_5GBASE_KR:
280 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
281 case ICE_PHY_TYPE_LOW_25GBASE_KR:
282 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
283 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
284 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
285 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
286 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
287 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
288 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
289 return ICE_MEDIA_BACKPLANE;
292 switch (hw_link_info->phy_type_high) {
293 case ICE_PHY_TYPE_HIGH_100G_AUI2:
294 if (ice_is_media_cage_present(pi))
297 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
298 return ICE_MEDIA_BACKPLANE;
301 return ICE_MEDIA_UNKNOWN;
305 * ice_aq_get_link_info
306 * @pi: port information structure
307 * @ena_lse: enable/disable LinkStatusEvent reporting
308 * @link: pointer to link status structure - optional
309 * @cd: pointer to command details structure or NULL
311 * Get Link Status (0x607). Returns the link status of the adapter.
314 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
315 struct ice_link_status *link, struct ice_sq_cd *cd)
317 struct ice_aqc_get_link_status_data link_data = { 0 };
318 struct ice_aqc_get_link_status *resp;
319 struct ice_link_status *li_old, *li;
320 enum ice_media_type *hw_media_type;
321 struct ice_fc_info *hw_fc_info;
322 bool tx_pause, rx_pause;
323 struct ice_aq_desc desc;
324 enum ice_status status;
329 return ICE_ERR_PARAM;
331 li_old = &pi->phy.link_info_old;
332 hw_media_type = &pi->phy.media_type;
333 li = &pi->phy.link_info;
334 hw_fc_info = &pi->fc;
336 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
337 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
338 resp = &desc.params.get_link_status;
339 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
340 resp->lport_num = pi->lport;
342 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
344 if (status != ICE_SUCCESS)
347 /* save off old link status information */
350 /* update current link status information */
351 li->link_speed = LE16_TO_CPU(link_data.link_speed);
352 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
353 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
354 *hw_media_type = ice_get_media_type(pi);
355 li->link_info = link_data.link_info;
356 li->an_info = link_data.an_info;
357 li->ext_info = link_data.ext_info;
358 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
359 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
360 li->topo_media_conflict = link_data.topo_media_conflict;
361 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
362 ICE_AQ_CFG_PACING_TYPE_M);
365 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
366 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
367 if (tx_pause && rx_pause)
368 hw_fc_info->current_mode = ICE_FC_FULL;
370 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
372 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
374 hw_fc_info->current_mode = ICE_FC_NONE;
376 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
378 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
379 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
380 (unsigned long long)li->phy_type_low);
381 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
382 (unsigned long long)li->phy_type_high);
383 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
384 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
385 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
386 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
387 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
388 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
389 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
391 /* save link status information */
395 /* flag cleared so calling functions don't call AQ again */
396 pi->phy.get_link_info = false;
403 * @hw: pointer to the HW struct
404 * @max_frame_size: Maximum Frame Size to be supported
405 * @cd: pointer to command details structure or NULL
407 * Set MAC configuration (0x0603)
410 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
412 u16 fc_threshold_val, tx_timer_val;
413 struct ice_aqc_set_mac_cfg *cmd;
414 struct ice_aq_desc desc;
417 cmd = &desc.params.set_mac_cfg;
419 if (max_frame_size == 0)
420 return ICE_ERR_PARAM;
422 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
424 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
426 /* We read back the transmit timer and fc threshold value of
427 * LFC. Thus, we will use index =
428 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
430 * Also, because we are opearating on transmit timer and fc
431 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
433 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
435 /* Retrieve the transmit timer */
437 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
438 tx_timer_val = reg_val &
439 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
440 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
442 /* Retrieve the fc threshold */
444 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
445 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);
446 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);
448 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
452 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
453 * @hw: pointer to the HW struct
455 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
457 struct ice_switch_info *sw;
459 hw->switch_info = (struct ice_switch_info *)
460 ice_malloc(hw, sizeof(*hw->switch_info));
461 sw = hw->switch_info;
464 return ICE_ERR_NO_MEMORY;
466 INIT_LIST_HEAD(&sw->vsi_list_map_head);
468 return ice_init_def_sw_recp(hw);
472 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
473 * @hw: pointer to the HW struct
475 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
477 struct ice_switch_info *sw = hw->switch_info;
478 struct ice_vsi_list_map_info *v_pos_map;
479 struct ice_vsi_list_map_info *v_tmp_map;
480 struct ice_sw_recipe *recps;
483 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
484 ice_vsi_list_map_info, list_entry) {
485 LIST_DEL(&v_pos_map->list_entry);
486 ice_free(hw, v_pos_map);
488 recps = hw->switch_info->recp_list;
489 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
490 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
492 recps[i].root_rid = i;
493 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
494 &recps[i].rg_list, ice_recp_grp_entry,
496 LIST_DEL(&rg_entry->l_entry);
497 ice_free(hw, rg_entry);
500 if (recps[i].adv_rule) {
501 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
502 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
504 ice_destroy_lock(&recps[i].filt_rule_lock);
505 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
506 &recps[i].filt_rules,
507 ice_adv_fltr_mgmt_list_entry,
509 LIST_DEL(&lst_itr->list_entry);
510 ice_free(hw, lst_itr->lkups);
511 ice_free(hw, lst_itr);
514 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
516 ice_destroy_lock(&recps[i].filt_rule_lock);
517 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
518 &recps[i].filt_rules,
519 ice_fltr_mgmt_list_entry,
521 LIST_DEL(&lst_itr->list_entry);
522 ice_free(hw, lst_itr);
525 if (recps[i].root_buf)
526 ice_free(hw, recps[i].root_buf);
528 ice_rm_all_sw_replay_rule_info(hw);
529 ice_free(hw, sw->recp_list);
534 * ice_get_itr_intrl_gran
535 * @hw: pointer to the HW struct
537 * Determines the ITR/INTRL granularities based on the maximum aggregate
538 * bandwidth according to the device's configuration during power-on.
540 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
542 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
543 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
544 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
546 switch (max_agg_bw) {
547 case ICE_MAX_AGG_BW_200G:
548 case ICE_MAX_AGG_BW_100G:
549 case ICE_MAX_AGG_BW_50G:
550 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
551 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
553 case ICE_MAX_AGG_BW_25G:
554 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
555 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
561 * ice_get_nvm_version - get cached NVM version data
562 * @hw: pointer to the hardware structure
563 * @oem_ver: 8 bit NVM version
564 * @oem_build: 16 bit NVM build number
565 * @oem_patch: 8 NVM patch number
566 * @ver_hi: high 16 bits of the NVM version
567 * @ver_lo: low 16 bits of the NVM version
570 ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
571 u8 *oem_patch, u8 *ver_hi, u8 *ver_lo)
573 struct ice_nvm_info *nvm = &hw->nvm;
575 *oem_ver = (u8)((nvm->oem_ver & ICE_OEM_VER_MASK) >> ICE_OEM_VER_SHIFT);
576 *oem_patch = (u8)(nvm->oem_ver & ICE_OEM_VER_PATCH_MASK);
577 *oem_build = (u16)((nvm->oem_ver & ICE_OEM_VER_BUILD_MASK) >>
578 ICE_OEM_VER_BUILD_SHIFT);
579 *ver_hi = (nvm->ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
580 *ver_lo = (nvm->ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
584 * ice_print_rollback_msg - print FW rollback message
585 * @hw: pointer to the hardware structure
587 void ice_print_rollback_msg(struct ice_hw *hw)
589 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
590 u8 oem_ver, oem_patch, ver_hi, ver_lo;
593 ice_get_nvm_version(hw, &oem_ver, &oem_build, &oem_patch, &ver_hi,
595 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", ver_hi,
596 ver_lo, hw->nvm.eetrack, oem_ver, oem_build, oem_patch);
598 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode",
599 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
603 * ice_init_hw - main hardware initialization routine
604 * @hw: pointer to the hardware structure
606 enum ice_status ice_init_hw(struct ice_hw *hw)
608 struct ice_aqc_get_phy_caps_data *pcaps;
609 enum ice_status status;
613 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
615 /* Set MAC type based on DeviceID */
616 status = ice_set_mac_type(hw);
620 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
621 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
622 PF_FUNC_RID_FUNCTION_NUMBER_S;
624 status = ice_reset(hw, ICE_RESET_PFR);
628 ice_get_itr_intrl_gran(hw);
630 status = ice_create_all_ctrlq(hw);
632 goto err_unroll_cqinit;
634 status = ice_init_nvm(hw);
636 goto err_unroll_cqinit;
638 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
639 ice_print_rollback_msg(hw);
641 status = ice_clear_pf_cfg(hw);
643 goto err_unroll_cqinit;
645 /* Set bit to enable Flow Director filters */
646 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
647 INIT_LIST_HEAD(&hw->fdir_list_head);
649 ice_clear_pxe_mode(hw);
652 status = ice_get_caps(hw);
654 goto err_unroll_cqinit;
656 hw->port_info = (struct ice_port_info *)
657 ice_malloc(hw, sizeof(*hw->port_info));
658 if (!hw->port_info) {
659 status = ICE_ERR_NO_MEMORY;
660 goto err_unroll_cqinit;
663 /* set the back pointer to HW */
664 hw->port_info->hw = hw;
666 /* Initialize port_info struct with switch configuration data */
667 status = ice_get_initial_sw_cfg(hw);
669 goto err_unroll_alloc;
673 /* Query the allocated resources for Tx scheduler */
674 status = ice_sched_query_res_alloc(hw);
676 ice_debug(hw, ICE_DBG_SCHED,
677 "Failed to get scheduler allocated resources\n");
678 goto err_unroll_alloc;
681 /* Initialize port_info struct with scheduler data */
682 status = ice_sched_init_port(hw->port_info);
684 goto err_unroll_sched;
686 pcaps = (struct ice_aqc_get_phy_caps_data *)
687 ice_malloc(hw, sizeof(*pcaps));
689 status = ICE_ERR_NO_MEMORY;
690 goto err_unroll_sched;
693 /* Initialize port_info struct with PHY capabilities */
694 status = ice_aq_get_phy_caps(hw->port_info, false,
695 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
698 goto err_unroll_sched;
700 /* Initialize port_info struct with link information */
701 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
703 goto err_unroll_sched;
704 /* need a valid SW entry point to build a Tx tree */
705 if (!hw->sw_entry_point_layer) {
706 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
707 status = ICE_ERR_CFG;
708 goto err_unroll_sched;
710 INIT_LIST_HEAD(&hw->agg_list);
711 /* Initialize max burst size */
712 if (!hw->max_burst_size)
713 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
715 status = ice_init_fltr_mgmt_struct(hw);
717 goto err_unroll_sched;
719 /* Get MAC information */
720 /* A single port can report up to two (LAN and WoL) addresses */
721 mac_buf = ice_calloc(hw, 2,
722 sizeof(struct ice_aqc_manage_mac_read_resp));
723 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
726 status = ICE_ERR_NO_MEMORY;
727 goto err_unroll_fltr_mgmt_struct;
730 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
731 ice_free(hw, mac_buf);
734 goto err_unroll_fltr_mgmt_struct;
735 /* Obtain counter base index which would be used by flow director */
736 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
738 goto err_unroll_fltr_mgmt_struct;
739 status = ice_init_hw_tbls(hw);
741 goto err_unroll_fltr_mgmt_struct;
744 err_unroll_fltr_mgmt_struct:
745 ice_cleanup_fltr_mgmt_struct(hw);
747 ice_sched_cleanup_all(hw);
749 ice_free(hw, hw->port_info);
750 hw->port_info = NULL;
752 ice_destroy_all_ctrlq(hw);
757 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
758 * @hw: pointer to the hardware structure
760 * This should be called only during nominal operation, not as a result of
761 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
762 * applicable initializations if it fails for any reason.
764 void ice_deinit_hw(struct ice_hw *hw)
766 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
767 ice_cleanup_fltr_mgmt_struct(hw);
769 ice_sched_cleanup_all(hw);
770 ice_sched_clear_agg(hw);
772 ice_free_hw_tbls(hw);
775 ice_free(hw, hw->port_info);
776 hw->port_info = NULL;
779 ice_destroy_all_ctrlq(hw);
781 /* Clear VSI contexts if not already cleared */
782 ice_clear_all_vsi_ctx(hw);
786 * ice_check_reset - Check to see if a global reset is complete
787 * @hw: pointer to the hardware structure
789 enum ice_status ice_check_reset(struct ice_hw *hw)
791 u32 cnt, reg = 0, grst_delay;
793 /* Poll for Device Active state in case a recent CORER, GLOBR,
794 * or EMPR has occurred. The grst delay value is in 100ms units.
795 * Add 1sec for outstanding AQ commands that can take a long time.
797 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
798 GLGEN_RSTCTL_GRSTDEL_S) + 10;
800 for (cnt = 0; cnt < grst_delay; cnt++) {
801 ice_msec_delay(100, true);
802 reg = rd32(hw, GLGEN_RSTAT);
803 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
807 if (cnt == grst_delay) {
808 ice_debug(hw, ICE_DBG_INIT,
809 "Global reset polling failed to complete.\n");
810 return ICE_ERR_RESET_FAILED;
813 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
814 GLNVM_ULD_GLOBR_DONE_M)
816 /* Device is Active; check Global Reset processes are done */
817 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
818 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
819 if (reg == ICE_RESET_DONE_MASK) {
820 ice_debug(hw, ICE_DBG_INIT,
821 "Global reset processes done. %d\n", cnt);
824 ice_msec_delay(10, true);
827 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
828 ice_debug(hw, ICE_DBG_INIT,
829 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
831 return ICE_ERR_RESET_FAILED;
838 * ice_pf_reset - Reset the PF
839 * @hw: pointer to the hardware structure
841 * If a global reset has been triggered, this function checks
842 * for its completion and then issues the PF reset
844 static enum ice_status ice_pf_reset(struct ice_hw *hw)
848 /* If at function entry a global reset was already in progress, i.e.
849 * state is not 'device active' or any of the reset done bits are not
850 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
851 * global reset is done.
853 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
854 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
855 /* poll on global reset currently in progress until done */
856 if (ice_check_reset(hw))
857 return ICE_ERR_RESET_FAILED;
863 reg = rd32(hw, PFGEN_CTRL);
865 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
867 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
868 reg = rd32(hw, PFGEN_CTRL);
869 if (!(reg & PFGEN_CTRL_PFSWR_M))
872 ice_msec_delay(1, true);
875 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
876 ice_debug(hw, ICE_DBG_INIT,
877 "PF reset polling failed to complete.\n");
878 return ICE_ERR_RESET_FAILED;
885 * ice_reset - Perform different types of reset
886 * @hw: pointer to the hardware structure
887 * @req: reset request
889 * This function triggers a reset as specified by the req parameter.
892 * If anything other than a PF reset is triggered, PXE mode is restored.
893 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
894 * interface has been restored in the rebuild flow.
896 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
902 return ice_pf_reset(hw);
903 case ICE_RESET_CORER:
904 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
905 val = GLGEN_RTRIG_CORER_M;
907 case ICE_RESET_GLOBR:
908 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
909 val = GLGEN_RTRIG_GLOBR_M;
912 return ICE_ERR_PARAM;
915 val |= rd32(hw, GLGEN_RTRIG);
916 wr32(hw, GLGEN_RTRIG, val);
919 /* wait for the FW to be ready */
920 return ice_check_reset(hw);
924 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
925 * @hw: pointer to hardware structure
926 * @module_tlv: pointer to module TLV to return
927 * @module_tlv_len: pointer to module TLV length to return
928 * @module_type: module type requested
930 * Finds the requested sub module TLV type from the Preserved Field
931 * Area (PFA) and returns the TLV pointer and length. The caller can
932 * use these to read the variable length TLV value.
935 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
938 enum ice_status status;
939 u16 pfa_len, pfa_ptr;
942 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
943 if (status != ICE_SUCCESS) {
944 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
947 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
948 if (status != ICE_SUCCESS) {
949 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
952 /* Starting with first TLV after PFA length, iterate through the list
953 * of TLVs to find the requested one.
955 next_tlv = pfa_ptr + 1;
956 while (next_tlv < pfa_ptr + pfa_len) {
957 u16 tlv_sub_module_type;
961 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
962 if (status != ICE_SUCCESS) {
963 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
966 /* Read TLV length */
967 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
968 if (status != ICE_SUCCESS) {
969 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
972 if (tlv_sub_module_type == module_type) {
974 *module_tlv = next_tlv;
975 *module_tlv_len = tlv_len;
978 return ICE_ERR_INVAL_SIZE;
980 /* Check next TLV, i.e. current TLV pointer + length + 2 words
981 * (for current TLV's type and length)
983 next_tlv = next_tlv + tlv_len + 2;
985 /* Module does not exist */
986 return ICE_ERR_DOES_NOT_EXIST;
990 * ice_copy_rxq_ctx_to_hw
991 * @hw: pointer to the hardware structure
992 * @ice_rxq_ctx: pointer to the rxq context
993 * @rxq_index: the index of the Rx queue
995 * Copies rxq context from dense structure to HW register space
997 static enum ice_status
998 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1003 return ICE_ERR_BAD_PTR;
1005 if (rxq_index > QRX_CTRL_MAX_INDEX)
1006 return ICE_ERR_PARAM;
1008 /* Copy each dword separately to HW */
1009 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1010 wr32(hw, QRX_CONTEXT(i, rxq_index),
1011 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1013 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1014 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1020 /* LAN Rx Queue Context */
1021 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1022 /* Field Width LSB */
1023 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1024 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1025 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1026 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1027 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1028 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1029 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1030 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1031 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1032 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1033 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1034 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1035 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1036 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1037 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1038 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1039 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1040 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1041 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1042 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1048 * @hw: pointer to the hardware structure
1049 * @rlan_ctx: pointer to the rxq context
1050 * @rxq_index: the index of the Rx queue
1052 * Converts rxq context from sparse to dense structure and then writes
1053 * it to HW register space and enables the hardware to prefetch descriptors
1054 * instead of only fetching them on demand
1057 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1060 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1063 return ICE_ERR_BAD_PTR;
1065 rlan_ctx->prefena = 1;
1067 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1068 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1071 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1074 * @hw: pointer to the hardware structure
1075 * @rxq_index: the index of the Rx queue to clear
1077 * Clears rxq context in HW register space
1079 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1083 if (rxq_index > QRX_CTRL_MAX_INDEX)
1084 return ICE_ERR_PARAM;
1086 /* Clear each dword register separately */
1087 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1088 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1092 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1094 /* LAN Tx Queue Context */
1095 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1096 /* Field Width LSB */
1097 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1098 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1099 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1100 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1101 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1102 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1103 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1104 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1105 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1106 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1107 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1108 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1109 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1110 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1111 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1112 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1113 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1114 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1115 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1116 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1117 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1118 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1119 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1120 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1121 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1122 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1123 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1124 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1128 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1130 * ice_copy_tx_cmpltnq_ctx_to_hw
1131 * @hw: pointer to the hardware structure
1132 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1133 * @tx_cmpltnq_index: the index of the completion queue
1135 * Copies Tx completion queue context from dense structure to HW register space
1137 static enum ice_status
1138 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1139 u32 tx_cmpltnq_index)
1143 if (!ice_tx_cmpltnq_ctx)
1144 return ICE_ERR_BAD_PTR;
1146 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1147 return ICE_ERR_PARAM;
1149 /* Copy each dword separately to HW */
1150 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1151 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1152 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1154 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1155 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1161 /* LAN Tx Completion Queue Context */
1162 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1163 /* Field Width LSB */
1164 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1165 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1166 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1167 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1168 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1169 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1170 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1171 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1172 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1173 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1178 * ice_write_tx_cmpltnq_ctx
1179 * @hw: pointer to the hardware structure
1180 * @tx_cmpltnq_ctx: pointer to the completion queue context
1181 * @tx_cmpltnq_index: the index of the completion queue
1183 * Converts completion queue context from sparse to dense structure and then
1184 * writes it to HW register space
1187 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1188 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1189 u32 tx_cmpltnq_index)
1191 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1193 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1194 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1198 * ice_clear_tx_cmpltnq_ctx
1199 * @hw: pointer to the hardware structure
1200 * @tx_cmpltnq_index: the index of the completion queue to clear
1202 * Clears Tx completion queue context in HW register space
1205 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1209 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1210 return ICE_ERR_PARAM;
1212 /* Clear each dword register separately */
1213 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1214 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1220 * ice_copy_tx_drbell_q_ctx_to_hw
1221 * @hw: pointer to the hardware structure
1222 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1223 * @tx_drbell_q_index: the index of the doorbell queue
1225 * Copies doorbell queue context from dense structure to HW register space
1227 static enum ice_status
1228 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1229 u32 tx_drbell_q_index)
1233 if (!ice_tx_drbell_q_ctx)
1234 return ICE_ERR_BAD_PTR;
1236 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1237 return ICE_ERR_PARAM;
1239 /* Copy each dword separately to HW */
1240 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1241 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1242 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1244 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1245 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1251 /* LAN Tx Doorbell Queue Context info */
1252 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1253 /* Field Width LSB */
1254 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1255 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1256 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1257 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1258 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1259 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1260 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1261 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1262 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1263 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1264 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1269 * ice_write_tx_drbell_q_ctx
1270 * @hw: pointer to the hardware structure
1271 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1272 * @tx_drbell_q_index: the index of the doorbell queue
1274 * Converts doorbell queue context from sparse to dense structure and then
1275 * writes it to HW register space
1278 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1279 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1280 u32 tx_drbell_q_index)
1282 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1284 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1285 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1289 * ice_clear_tx_drbell_q_ctx
1290 * @hw: pointer to the hardware structure
1291 * @tx_drbell_q_index: the index of the doorbell queue to clear
1293 * Clears doorbell queue context in HW register space
1296 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1300 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1301 return ICE_ERR_PARAM;
1303 /* Clear each dword register separately */
1304 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1305 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1309 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1311 /* FW Admin Queue command wrappers */
1314 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1315 * @hw: pointer to the HW struct
1316 * @desc: descriptor describing the command
1317 * @buf: buffer to use for indirect commands (NULL for direct commands)
1318 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1319 * @cd: pointer to command details structure
1321 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1324 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1325 u16 buf_size, struct ice_sq_cd *cd)
1327 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1332 * @hw: pointer to the HW struct
1333 * @cd: pointer to command details structure or NULL
1335 * Get the firmware version (0x0001) from the admin queue commands
1337 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1339 struct ice_aqc_get_ver *resp;
1340 struct ice_aq_desc desc;
1341 enum ice_status status;
1343 resp = &desc.params.get_ver;
1345 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1347 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1350 hw->fw_branch = resp->fw_branch;
1351 hw->fw_maj_ver = resp->fw_major;
1352 hw->fw_min_ver = resp->fw_minor;
1353 hw->fw_patch = resp->fw_patch;
1354 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1355 hw->api_branch = resp->api_branch;
1356 hw->api_maj_ver = resp->api_major;
1357 hw->api_min_ver = resp->api_minor;
1358 hw->api_patch = resp->api_patch;
1365 * ice_aq_send_driver_ver
1366 * @hw: pointer to the HW struct
1367 * @dv: driver's major, minor version
1368 * @cd: pointer to command details structure or NULL
1370 * Send the driver version (0x0002) to the firmware
1373 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1374 struct ice_sq_cd *cd)
1376 struct ice_aqc_driver_ver *cmd;
1377 struct ice_aq_desc desc;
1380 cmd = &desc.params.driver_ver;
1383 return ICE_ERR_PARAM;
1385 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1387 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1388 cmd->major_ver = dv->major_ver;
1389 cmd->minor_ver = dv->minor_ver;
1390 cmd->build_ver = dv->build_ver;
1391 cmd->subbuild_ver = dv->subbuild_ver;
1394 while (len < sizeof(dv->driver_string) &&
1395 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1398 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1403 * @hw: pointer to the HW struct
1404 * @unloading: is the driver unloading itself
1406 * Tell the Firmware that we're shutting down the AdminQ and whether
1407 * or not the driver is unloading as well (0x0003).
1409 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1411 struct ice_aqc_q_shutdown *cmd;
1412 struct ice_aq_desc desc;
1414 cmd = &desc.params.q_shutdown;
1416 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1419 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1421 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1426 * @hw: pointer to the HW struct
1428 * @access: access type
1429 * @sdp_number: resource number
1430 * @timeout: the maximum time in ms that the driver may hold the resource
1431 * @cd: pointer to command details structure or NULL
1433 * Requests common resource using the admin queue commands (0x0008).
1434 * When attempting to acquire the Global Config Lock, the driver can
1435 * learn of three states:
1436 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1437 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1438 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1439 * successfully downloaded the package; the driver does
1440 * not have to download the package and can continue
1443 * Note that if the caller is in an acquire lock, perform action, release lock
1444 * phase of operation, it is possible that the FW may detect a timeout and issue
1445 * a CORER. In this case, the driver will receive a CORER interrupt and will
1446 * have to determine its cause. The calling thread that is handling this flow
1447 * will likely get an error propagated back to it indicating the Download
1448 * Package, Update Package or the Release Resource AQ commands timed out.
1450 static enum ice_status
1451 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1452 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1453 struct ice_sq_cd *cd)
1455 struct ice_aqc_req_res *cmd_resp;
1456 struct ice_aq_desc desc;
1457 enum ice_status status;
1459 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1461 cmd_resp = &desc.params.res_owner;
1463 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1465 cmd_resp->res_id = CPU_TO_LE16(res);
1466 cmd_resp->access_type = CPU_TO_LE16(access);
1467 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1468 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1471 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1473 /* The completion specifies the maximum time in ms that the driver
1474 * may hold the resource in the Timeout field.
1477 /* Global config lock response utilizes an additional status field.
1479 * If the Global config lock resource is held by some other driver, the
1480 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1481 * and the timeout field indicates the maximum time the current owner
1482 * of the resource has to free it.
1484 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1485 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1486 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1488 } else if (LE16_TO_CPU(cmd_resp->status) ==
1489 ICE_AQ_RES_GLBL_IN_PROG) {
1490 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1491 return ICE_ERR_AQ_ERROR;
1492 } else if (LE16_TO_CPU(cmd_resp->status) ==
1493 ICE_AQ_RES_GLBL_DONE) {
1494 return ICE_ERR_AQ_NO_WORK;
1497 /* invalid FW response, force a timeout immediately */
1499 return ICE_ERR_AQ_ERROR;
1502 /* If the resource is held by some other driver, the command completes
1503 * with a busy return value and the timeout field indicates the maximum
1504 * time the current owner of the resource has to free it.
1506 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1507 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1513 * ice_aq_release_res
1514 * @hw: pointer to the HW struct
1516 * @sdp_number: resource number
1517 * @cd: pointer to command details structure or NULL
1519 * release common resource using the admin queue commands (0x0009)
1521 static enum ice_status
1522 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1523 struct ice_sq_cd *cd)
1525 struct ice_aqc_req_res *cmd;
1526 struct ice_aq_desc desc;
1528 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1530 cmd = &desc.params.res_owner;
1532 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1534 cmd->res_id = CPU_TO_LE16(res);
1535 cmd->res_number = CPU_TO_LE32(sdp_number);
1537 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1542 * @hw: pointer to the HW structure
1544 * @access: access type (read or write)
1545 * @timeout: timeout in milliseconds
1547 * This function will attempt to acquire the ownership of a resource.
1550 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1551 enum ice_aq_res_access_type access, u32 timeout)
1553 #define ICE_RES_POLLING_DELAY_MS 10
1554 u32 delay = ICE_RES_POLLING_DELAY_MS;
1555 u32 time_left = timeout;
1556 enum ice_status status;
1558 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1560 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1562 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1563 * previously acquired the resource and performed any necessary updates;
1564 * in this case the caller does not obtain the resource and has no
1565 * further work to do.
1567 if (status == ICE_ERR_AQ_NO_WORK)
1568 goto ice_acquire_res_exit;
1571 ice_debug(hw, ICE_DBG_RES,
1572 "resource %d acquire type %d failed.\n", res, access);
1574 /* If necessary, poll until the current lock owner timeouts */
1575 timeout = time_left;
1576 while (status && timeout && time_left) {
1577 ice_msec_delay(delay, true);
1578 timeout = (timeout > delay) ? timeout - delay : 0;
1579 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1581 if (status == ICE_ERR_AQ_NO_WORK)
1582 /* lock free, but no work to do */
1589 if (status && status != ICE_ERR_AQ_NO_WORK)
1590 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1592 ice_acquire_res_exit:
1593 if (status == ICE_ERR_AQ_NO_WORK) {
1594 if (access == ICE_RES_WRITE)
1595 ice_debug(hw, ICE_DBG_RES,
1596 "resource indicates no work to do.\n");
1598 ice_debug(hw, ICE_DBG_RES,
1599 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1606 * @hw: pointer to the HW structure
1609 * This function will release a resource using the proper Admin Command.
1611 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1613 enum ice_status status;
1614 u32 total_delay = 0;
1616 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1618 status = ice_aq_release_res(hw, res, 0, NULL);
1620 /* there are some rare cases when trying to release the resource
1621 * results in an admin queue timeout, so handle them correctly
1623 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1624 (total_delay < hw->adminq.sq_cmd_timeout)) {
1625 ice_msec_delay(1, true);
1626 status = ice_aq_release_res(hw, res, 0, NULL);
1632 * ice_aq_alloc_free_res - command to allocate/free resources
1633 * @hw: pointer to the HW struct
1634 * @num_entries: number of resource entries in buffer
1635 * @buf: Indirect buffer to hold data parameters and response
1636 * @buf_size: size of buffer for indirect commands
1637 * @opc: pass in the command opcode
1638 * @cd: pointer to command details structure or NULL
1640 * Helper function to allocate/free resources using the admin queue commands
1643 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1644 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1645 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1647 struct ice_aqc_alloc_free_res_cmd *cmd;
1648 struct ice_aq_desc desc;
1650 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1652 cmd = &desc.params.sw_res_ctrl;
1655 return ICE_ERR_PARAM;
1657 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1658 return ICE_ERR_PARAM;
1660 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1662 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1664 cmd->num_entries = CPU_TO_LE16(num_entries);
1666 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1670 * ice_alloc_hw_res - allocate resource
1671 * @hw: pointer to the HW struct
1672 * @type: type of resource
1673 * @num: number of resources to allocate
1674 * @btm: allocate from bottom
1675 * @res: pointer to array that will receive the resources
1678 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1680 struct ice_aqc_alloc_free_res_elem *buf;
1681 enum ice_status status;
1684 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1685 buf = (struct ice_aqc_alloc_free_res_elem *)
1686 ice_malloc(hw, buf_len);
1688 return ICE_ERR_NO_MEMORY;
1690 /* Prepare buffer to allocate resource. */
1691 buf->num_elems = CPU_TO_LE16(num);
1692 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1693 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1695 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1697 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1698 ice_aqc_opc_alloc_res, NULL);
1700 goto ice_alloc_res_exit;
1702 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1703 ICE_NONDMA_TO_NONDMA);
1711 * ice_free_hw_res - free allocated HW resource
1712 * @hw: pointer to the HW struct
1713 * @type: type of resource to free
1714 * @num: number of resources
1715 * @res: pointer to array that contains the resources to free
1718 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1720 struct ice_aqc_alloc_free_res_elem *buf;
1721 enum ice_status status;
1724 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1725 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1727 return ICE_ERR_NO_MEMORY;
1729 /* Prepare buffer to free resource. */
1730 buf->num_elems = CPU_TO_LE16(num);
1731 buf->res_type = CPU_TO_LE16(type);
1732 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1733 ICE_NONDMA_TO_NONDMA);
1735 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1736 ice_aqc_opc_free_res, NULL);
1738 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1745 * ice_get_num_per_func - determine number of resources per PF
1746 * @hw: pointer to the HW structure
1747 * @max: value to be evenly split between each PF
1749 * Determine the number of valid functions by going through the bitmap returned
1750 * from parsing capabilities and use this to calculate the number of resources
1751 * per PF based on the max value passed in.
1753 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1757 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1758 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1759 ICE_CAPS_VALID_FUNCS_M);
1768 * ice_parse_caps - parse function/device capabilities
1769 * @hw: pointer to the HW struct
1770 * @buf: pointer to a buffer containing function/device capability records
1771 * @cap_count: number of capability records in the list
1772 * @opc: type of capabilities list to parse
1774 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1777 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1778 enum ice_adminq_opc opc)
1780 struct ice_aqc_list_caps_elem *cap_resp;
1781 struct ice_hw_func_caps *func_p = NULL;
1782 struct ice_hw_dev_caps *dev_p = NULL;
1783 struct ice_hw_common_caps *caps;
1790 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1792 if (opc == ice_aqc_opc_list_dev_caps) {
1793 dev_p = &hw->dev_caps;
1794 caps = &dev_p->common_cap;
1796 } else if (opc == ice_aqc_opc_list_func_caps) {
1797 func_p = &hw->func_caps;
1798 caps = &func_p->common_cap;
1799 prefix = "func cap";
1801 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1805 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1806 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1807 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1808 u32 number = LE32_TO_CPU(cap_resp->number);
1809 u16 cap = LE16_TO_CPU(cap_resp->cap);
1812 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1813 caps->valid_functions = number;
1814 ice_debug(hw, ICE_DBG_INIT,
1815 "%s: valid_functions (bitmap) = %d\n", prefix,
1816 caps->valid_functions);
1818 /* store func count for resource management purposes */
1820 dev_p->num_funcs = ice_hweight32(number);
1822 case ICE_AQC_CAPS_VSI:
1824 dev_p->num_vsi_allocd_to_host = number;
1825 ice_debug(hw, ICE_DBG_INIT,
1826 "%s: num_vsi_allocd_to_host = %d\n",
1828 dev_p->num_vsi_allocd_to_host);
1829 } else if (func_p) {
1830 func_p->guar_num_vsi =
1831 ice_get_num_per_func(hw, ICE_MAX_VSI);
1832 ice_debug(hw, ICE_DBG_INIT,
1833 "%s: guar_num_vsi (fw) = %d\n",
1835 ice_debug(hw, ICE_DBG_INIT,
1836 "%s: guar_num_vsi = %d\n",
1837 prefix, func_p->guar_num_vsi);
1840 case ICE_AQC_CAPS_DCB:
1841 caps->dcb = (number == 1);
1842 caps->active_tc_bitmap = logical_id;
1843 caps->maxtc = phys_id;
1844 ice_debug(hw, ICE_DBG_INIT,
1845 "%s: dcb = %d\n", prefix, caps->dcb);
1846 ice_debug(hw, ICE_DBG_INIT,
1847 "%s: active_tc_bitmap = %d\n", prefix,
1848 caps->active_tc_bitmap);
1849 ice_debug(hw, ICE_DBG_INIT,
1850 "%s: maxtc = %d\n", prefix, caps->maxtc);
1852 case ICE_AQC_CAPS_RSS:
1853 caps->rss_table_size = number;
1854 caps->rss_table_entry_width = logical_id;
1855 ice_debug(hw, ICE_DBG_INIT,
1856 "%s: rss_table_size = %d\n", prefix,
1857 caps->rss_table_size);
1858 ice_debug(hw, ICE_DBG_INIT,
1859 "%s: rss_table_entry_width = %d\n", prefix,
1860 caps->rss_table_entry_width);
1862 case ICE_AQC_CAPS_RXQS:
1863 caps->num_rxq = number;
1864 caps->rxq_first_id = phys_id;
1865 ice_debug(hw, ICE_DBG_INIT,
1866 "%s: num_rxq = %d\n", prefix,
1868 ice_debug(hw, ICE_DBG_INIT,
1869 "%s: rxq_first_id = %d\n", prefix,
1870 caps->rxq_first_id);
1872 case ICE_AQC_CAPS_TXQS:
1873 caps->num_txq = number;
1874 caps->txq_first_id = phys_id;
1875 ice_debug(hw, ICE_DBG_INIT,
1876 "%s: num_txq = %d\n", prefix,
1878 ice_debug(hw, ICE_DBG_INIT,
1879 "%s: txq_first_id = %d\n", prefix,
1880 caps->txq_first_id);
1882 case ICE_AQC_CAPS_MSIX:
1883 caps->num_msix_vectors = number;
1884 caps->msix_vector_first_id = phys_id;
1885 ice_debug(hw, ICE_DBG_INIT,
1886 "%s: num_msix_vectors = %d\n", prefix,
1887 caps->num_msix_vectors);
1888 ice_debug(hw, ICE_DBG_INIT,
1889 "%s: msix_vector_first_id = %d\n", prefix,
1890 caps->msix_vector_first_id);
1892 case ICE_AQC_CAPS_FD:
1897 dev_p->num_flow_director_fltr = number;
1898 ice_debug(hw, ICE_DBG_INIT,
1899 "%s: num_flow_director_fltr = %d\n",
1901 dev_p->num_flow_director_fltr);
1904 reg_val = rd32(hw, GLQF_FD_SIZE);
1905 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
1906 GLQF_FD_SIZE_FD_GSIZE_S;
1907 func_p->fd_fltr_guar =
1908 ice_get_num_per_func(hw, val);
1909 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
1910 GLQF_FD_SIZE_FD_BSIZE_S;
1911 func_p->fd_fltr_best_effort = val;
1912 ice_debug(hw, ICE_DBG_INIT,
1913 "%s: fd_fltr_guar = %d\n",
1914 prefix, func_p->fd_fltr_guar);
1915 ice_debug(hw, ICE_DBG_INIT,
1916 "%s: fd_fltr_best_effort = %d\n",
1917 prefix, func_p->fd_fltr_best_effort);
1921 case ICE_AQC_CAPS_MAX_MTU:
1922 caps->max_mtu = number;
1923 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1924 prefix, caps->max_mtu);
1927 ice_debug(hw, ICE_DBG_INIT,
1928 "%s: unknown capability[%d]: 0x%x\n", prefix,
1934 /* Re-calculate capabilities that are dependent on the number of
1935 * physical ports; i.e. some features are not supported or function
1936 * differently on devices with more than 4 ports.
1938 if (hw->dev_caps.num_funcs > 4) {
1939 /* Max 4 TCs per port */
1941 ice_debug(hw, ICE_DBG_INIT,
1942 "%s: maxtc = %d (based on #ports)\n", prefix,
1948 * ice_aq_discover_caps - query function/device capabilities
1949 * @hw: pointer to the HW struct
1950 * @buf: a virtual buffer to hold the capabilities
1951 * @buf_size: Size of the virtual buffer
1952 * @cap_count: cap count needed if AQ err==ENOMEM
1953 * @opc: capabilities type to discover - pass in the command opcode
1954 * @cd: pointer to command details structure or NULL
1956 * Get the function(0x000a)/device(0x000b) capabilities description from
1959 static enum ice_status
1960 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
1961 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1963 struct ice_aqc_list_caps *cmd;
1964 struct ice_aq_desc desc;
1965 enum ice_status status;
1967 cmd = &desc.params.get_cap;
1969 if (opc != ice_aqc_opc_list_func_caps &&
1970 opc != ice_aqc_opc_list_dev_caps)
1971 return ICE_ERR_PARAM;
1973 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1975 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1977 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
1978 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
1979 *cap_count = LE32_TO_CPU(cmd->count);
1984 * ice_discover_caps - get info about the HW
1985 * @hw: pointer to the hardware structure
1986 * @opc: capabilities type to discover - pass in the command opcode
1988 static enum ice_status
1989 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
1991 enum ice_status status;
1996 /* The driver doesn't know how many capabilities the device will return
1997 * so the buffer size required isn't known ahead of time. The driver
1998 * starts with cbuf_len and if this turns out to be insufficient, the
1999 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2000 * The driver then allocates the buffer based on the count and retries
2001 * the operation. So it follows that the retry count is 2.
2003 #define ICE_GET_CAP_BUF_COUNT 40
2004 #define ICE_GET_CAP_RETRY_COUNT 2
2006 cap_count = ICE_GET_CAP_BUF_COUNT;
2007 retries = ICE_GET_CAP_RETRY_COUNT;
2012 cbuf_len = (u16)(cap_count *
2013 sizeof(struct ice_aqc_list_caps_elem));
2014 cbuf = ice_malloc(hw, cbuf_len);
2016 return ICE_ERR_NO_MEMORY;
2018 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2022 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2025 /* If ENOMEM is returned, try again with bigger buffer */
2026 } while (--retries);
2032 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2033 * @hw: pointer to the hardware structure
2035 void ice_set_safe_mode_caps(struct ice_hw *hw)
2037 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2038 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2039 u32 valid_func, rxq_first_id, txq_first_id;
2040 u32 msix_vector_first_id, max_mtu;
2043 /* cache some func_caps values that should be restored after memset */
2044 valid_func = func_caps->common_cap.valid_functions;
2045 txq_first_id = func_caps->common_cap.txq_first_id;
2046 rxq_first_id = func_caps->common_cap.rxq_first_id;
2047 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
2048 max_mtu = func_caps->common_cap.max_mtu;
2050 /* unset func capabilities */
2051 memset(func_caps, 0, sizeof(*func_caps));
2053 /* restore cached values */
2054 func_caps->common_cap.valid_functions = valid_func;
2055 func_caps->common_cap.txq_first_id = txq_first_id;
2056 func_caps->common_cap.rxq_first_id = rxq_first_id;
2057 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2058 func_caps->common_cap.max_mtu = max_mtu;
2060 /* one Tx and one Rx queue in safe mode */
2061 func_caps->common_cap.num_rxq = 1;
2062 func_caps->common_cap.num_txq = 1;
2064 /* two MSIX vectors, one for traffic and one for misc causes */
2065 func_caps->common_cap.num_msix_vectors = 2;
2066 func_caps->guar_num_vsi = 1;
2068 /* cache some dev_caps values that should be restored after memset */
2069 valid_func = dev_caps->common_cap.valid_functions;
2070 txq_first_id = dev_caps->common_cap.txq_first_id;
2071 rxq_first_id = dev_caps->common_cap.rxq_first_id;
2072 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
2073 max_mtu = dev_caps->common_cap.max_mtu;
2074 num_funcs = dev_caps->num_funcs;
2076 /* unset dev capabilities */
2077 memset(dev_caps, 0, sizeof(*dev_caps));
2079 /* restore cached values */
2080 dev_caps->common_cap.valid_functions = valid_func;
2081 dev_caps->common_cap.txq_first_id = txq_first_id;
2082 dev_caps->common_cap.rxq_first_id = rxq_first_id;
2083 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2084 dev_caps->common_cap.max_mtu = max_mtu;
2085 dev_caps->num_funcs = num_funcs;
2087 /* one Tx and one Rx queue per function in safe mode */
2088 dev_caps->common_cap.num_rxq = num_funcs;
2089 dev_caps->common_cap.num_txq = num_funcs;
2091 /* two MSIX vectors per function */
2092 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2096 * ice_get_caps - get info about the HW
2097 * @hw: pointer to the hardware structure
2099 enum ice_status ice_get_caps(struct ice_hw *hw)
2101 enum ice_status status;
2103 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2105 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2111 * ice_aq_manage_mac_write - manage MAC address write command
2112 * @hw: pointer to the HW struct
2113 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2114 * @flags: flags to control write behavior
2115 * @cd: pointer to command details structure or NULL
2117 * This function is used to write MAC address to the NVM (0x0108).
2120 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2121 struct ice_sq_cd *cd)
2123 struct ice_aqc_manage_mac_write *cmd;
2124 struct ice_aq_desc desc;
2126 cmd = &desc.params.mac_write;
2127 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2131 /* Prep values for flags, sah, sal */
2132 cmd->sah = HTONS(*((const u16 *)mac_addr));
2133 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
2135 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2139 * ice_aq_clear_pxe_mode
2140 * @hw: pointer to the HW struct
2142 * Tell the firmware that the driver is taking over from PXE (0x0110).
2144 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2146 struct ice_aq_desc desc;
2148 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2149 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2151 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2155 * ice_clear_pxe_mode - clear pxe operations mode
2156 * @hw: pointer to the HW struct
2158 * Make sure all PXE mode settings are cleared, including things
2159 * like descriptor fetch/write-back mode.
2161 void ice_clear_pxe_mode(struct ice_hw *hw)
2163 if (ice_check_sq_alive(hw, &hw->adminq))
2164 ice_aq_clear_pxe_mode(hw);
2168 * ice_get_link_speed_based_on_phy_type - returns link speed
2169 * @phy_type_low: lower part of phy_type
2170 * @phy_type_high: higher part of phy_type
2172 * This helper function will convert an entry in PHY type structure
2173 * [phy_type_low, phy_type_high] to its corresponding link speed.
2174 * Note: In the structure of [phy_type_low, phy_type_high], there should
2175 * be one bit set, as this function will convert one PHY type to its
2177 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2178 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2181 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2183 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2184 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2186 switch (phy_type_low) {
2187 case ICE_PHY_TYPE_LOW_100BASE_TX:
2188 case ICE_PHY_TYPE_LOW_100M_SGMII:
2189 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2191 case ICE_PHY_TYPE_LOW_1000BASE_T:
2192 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2193 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2194 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2195 case ICE_PHY_TYPE_LOW_1G_SGMII:
2196 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2198 case ICE_PHY_TYPE_LOW_2500BASE_T:
2199 case ICE_PHY_TYPE_LOW_2500BASE_X:
2200 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2201 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2203 case ICE_PHY_TYPE_LOW_5GBASE_T:
2204 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2205 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2207 case ICE_PHY_TYPE_LOW_10GBASE_T:
2208 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2209 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2210 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2211 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2212 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2213 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2214 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2216 case ICE_PHY_TYPE_LOW_25GBASE_T:
2217 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2218 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2219 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2220 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2221 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2222 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2223 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2224 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2225 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2226 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2227 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2229 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2230 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2231 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2232 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2233 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2234 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2235 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2237 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2238 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2239 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2240 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2241 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2242 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2243 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2244 case ICE_PHY_TYPE_LOW_50G_AUI2:
2245 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2246 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2247 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2248 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2249 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2250 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2251 case ICE_PHY_TYPE_LOW_50G_AUI1:
2252 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2254 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2255 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2256 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2257 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2258 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2259 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2260 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2261 case ICE_PHY_TYPE_LOW_100G_AUI4:
2262 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2263 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2264 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2265 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2266 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2267 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2270 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2274 switch (phy_type_high) {
2275 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2276 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2277 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2278 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2279 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2280 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2283 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2287 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2288 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2289 return ICE_AQ_LINK_SPEED_UNKNOWN;
2290 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2291 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2292 return ICE_AQ_LINK_SPEED_UNKNOWN;
2293 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2294 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2295 return speed_phy_type_low;
2297 return speed_phy_type_high;
2301 * ice_update_phy_type
2302 * @phy_type_low: pointer to the lower part of phy_type
2303 * @phy_type_high: pointer to the higher part of phy_type
2304 * @link_speeds_bitmap: targeted link speeds bitmap
2306 * Note: For the link_speeds_bitmap structure, you can check it at
2307 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2308 * link_speeds_bitmap include multiple speeds.
2310 * Each entry in this [phy_type_low, phy_type_high] structure will
2311 * present a certain link speed. This helper function will turn on bits
2312 * in [phy_type_low, phy_type_high] structure based on the value of
2313 * link_speeds_bitmap input parameter.
2316 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2317 u16 link_speeds_bitmap)
2324 /* We first check with low part of phy_type */
2325 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2326 pt_low = BIT_ULL(index);
2327 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2329 if (link_speeds_bitmap & speed)
2330 *phy_type_low |= BIT_ULL(index);
2333 /* We then check with high part of phy_type */
2334 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2335 pt_high = BIT_ULL(index);
2336 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2338 if (link_speeds_bitmap & speed)
2339 *phy_type_high |= BIT_ULL(index);
2344 * ice_aq_set_phy_cfg
2345 * @hw: pointer to the HW struct
2346 * @pi: port info structure of the interested logical port
2347 * @cfg: structure with PHY configuration data to be set
2348 * @cd: pointer to command details structure or NULL
2350 * Set the various PHY configuration parameters supported on the Port.
2351 * One or more of the Set PHY config parameters may be ignored in an MFP
2352 * mode as the PF may not have the privilege to set some of the PHY Config
2353 * parameters. This status will be indicated by the command response (0x0601).
2356 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2357 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2359 struct ice_aq_desc desc;
2360 enum ice_status status;
2363 return ICE_ERR_PARAM;
2365 /* Ensure that only valid bits of cfg->caps can be turned on. */
2366 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2367 ice_debug(hw, ICE_DBG_PHY,
2368 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2371 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2374 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2375 desc.params.set_phy.lport_num = pi->lport;
2376 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2378 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2379 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2380 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2381 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2382 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2383 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n",
2384 cfg->low_power_ctrl);
2385 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2386 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2387 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2389 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2392 pi->phy.curr_user_phy_cfg = *cfg;
2398 * ice_update_link_info - update status of the HW network link
2399 * @pi: port info structure of the interested logical port
2401 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2403 struct ice_link_status *li;
2404 enum ice_status status;
2407 return ICE_ERR_PARAM;
2409 li = &pi->phy.link_info;
2411 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2415 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2416 struct ice_aqc_get_phy_caps_data *pcaps;
2420 pcaps = (struct ice_aqc_get_phy_caps_data *)
2421 ice_malloc(hw, sizeof(*pcaps));
2423 return ICE_ERR_NO_MEMORY;
2425 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2427 if (status == ICE_SUCCESS)
2428 ice_memcpy(li->module_type, &pcaps->module_type,
2429 sizeof(li->module_type),
2430 ICE_NONDMA_TO_NONDMA);
2432 ice_free(hw, pcaps);
2439 * ice_cache_phy_user_req
2440 * @pi: port information structure
2441 * @cache_data: PHY logging data
2442 * @cache_mode: PHY logging mode
2444 * Log the user request on (FC, FEC, SPEED) for later user.
2447 ice_cache_phy_user_req(struct ice_port_info *pi,
2448 struct ice_phy_cache_mode_data cache_data,
2449 enum ice_phy_cache_mode cache_mode)
2454 switch (cache_mode) {
2456 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2458 case ICE_SPEED_MODE:
2459 pi->phy.curr_user_speed_req =
2460 cache_data.data.curr_user_speed_req;
2463 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2471 * ice_caps_to_fc_mode
2472 * @caps: PHY capabilities
2474 * Convert PHY FC capabilities to ice FC mode
2476 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2478 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2479 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2482 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2483 return ICE_FC_TX_PAUSE;
2485 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2486 return ICE_FC_RX_PAUSE;
2492 * ice_caps_to_fec_mode
2493 * @caps: PHY capabilities
2494 * @fec_options: Link FEC options
2496 * Convert PHY FEC capabilities to ice FEC mode
2498 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2500 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2501 return ICE_FEC_AUTO;
2503 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2504 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2505 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2506 ICE_AQC_PHY_FEC_25G_KR_REQ))
2507 return ICE_FEC_BASER;
2509 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2510 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2511 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2514 return ICE_FEC_NONE;
2519 * @pi: port information structure
2520 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2521 * @ena_auto_link_update: enable automatic link update
2523 * Set the requested flow control mode.
2526 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2528 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2529 struct ice_phy_cache_mode_data cache_data;
2530 struct ice_aqc_get_phy_caps_data *pcaps;
2531 enum ice_status status;
2532 u8 pause_mask = 0x0;
2536 return ICE_ERR_PARAM;
2538 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2540 /* Cache user FC request */
2541 cache_data.data.curr_user_fc_req = pi->fc.req_mode;
2542 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2544 switch (pi->fc.req_mode) {
2546 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2547 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2549 case ICE_FC_RX_PAUSE:
2550 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2552 case ICE_FC_TX_PAUSE:
2553 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2559 pcaps = (struct ice_aqc_get_phy_caps_data *)
2560 ice_malloc(hw, sizeof(*pcaps));
2562 return ICE_ERR_NO_MEMORY;
2564 /* Get the current PHY config */
2565 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2568 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2572 /* clear the old pause settings */
2573 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2574 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2576 /* set the new capabilities */
2577 cfg.caps |= pause_mask;
2579 /* If the capabilities have changed, then set the new config */
2580 if (cfg.caps != pcaps->caps) {
2581 int retry_count, retry_max = 10;
2583 /* Auto restart link so settings take effect */
2584 if (ena_auto_link_update)
2585 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2586 /* Copy over all the old settings */
2587 cfg.phy_type_high = pcaps->phy_type_high;
2588 cfg.phy_type_low = pcaps->phy_type_low;
2589 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2590 cfg.eee_cap = pcaps->eee_cap;
2591 cfg.eeer_value = pcaps->eeer_value;
2592 cfg.link_fec_opt = pcaps->link_fec_options;
2594 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2596 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2600 /* Update the link info
2601 * It sometimes takes a really long time for link to
2602 * come back from the atomic reset. Thus, we wait a
2605 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2606 status = ice_update_link_info(pi);
2608 if (status == ICE_SUCCESS)
2611 ice_msec_delay(100, true);
2615 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2619 ice_free(hw, pcaps);
2624 * ice_phy_caps_equals_cfg
2625 * @phy_caps: PHY capabilities
2626 * @phy_cfg: PHY configuration
2628 * Helper function to determine if PHY capabilities matches PHY
2632 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2633 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2635 u8 caps_mask, cfg_mask;
2637 if (!phy_caps || !phy_cfg)
2640 /* These bits are not common between capabilities and configuration.
2641 * Do not use them to determine equality.
2643 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2644 ICE_AQC_PHY_EN_MOD_QUAL);
2645 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2647 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2648 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2649 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2650 phy_caps->low_power_ctrl != phy_cfg->low_power_ctrl ||
2651 phy_caps->eee_cap != phy_cfg->eee_cap ||
2652 phy_caps->eeer_value != phy_cfg->eeer_value ||
2653 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2660 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2661 * @caps: PHY ability structure to copy date from
2662 * @cfg: PHY configuration structure to copy data to
2664 * Helper function to copy AQC PHY get ability data to PHY set configuration
2668 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2669 struct ice_aqc_set_phy_cfg_data *cfg)
2674 cfg->phy_type_low = caps->phy_type_low;
2675 cfg->phy_type_high = caps->phy_type_high;
2676 cfg->caps = caps->caps;
2677 cfg->low_power_ctrl = caps->low_power_ctrl;
2678 cfg->eee_cap = caps->eee_cap;
2679 cfg->eeer_value = caps->eeer_value;
2680 cfg->link_fec_opt = caps->link_fec_options;
2684 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2685 * @cfg: PHY configuration data to set FEC mode
2686 * @fec: FEC mode to configure
2688 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2689 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2690 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2693 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2697 /* Clear RS bits, and AND BASE-R ability
2698 * bits and OR request bits.
2700 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2701 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2702 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2703 ICE_AQC_PHY_FEC_25G_KR_REQ;
2706 /* Clear BASE-R bits, and AND RS ability
2707 * bits and OR request bits.
2709 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2710 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2711 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2714 /* Clear all FEC option bits. */
2715 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2718 /* AND auto FEC bit, and all caps bits. */
2719 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2725 * ice_get_link_status - get status of the HW network link
2726 * @pi: port information structure
2727 * @link_up: pointer to bool (true/false = linkup/linkdown)
2729 * Variable link_up is true if link is up, false if link is down.
2730 * The variable link_up is invalid if status is non zero. As a
2731 * result of this call, link status reporting becomes enabled
2733 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2735 struct ice_phy_info *phy_info;
2736 enum ice_status status = ICE_SUCCESS;
2738 if (!pi || !link_up)
2739 return ICE_ERR_PARAM;
2741 phy_info = &pi->phy;
2743 if (phy_info->get_link_info) {
2744 status = ice_update_link_info(pi);
2747 ice_debug(pi->hw, ICE_DBG_LINK,
2748 "get link status error, status = %d\n",
2752 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2758 * ice_aq_set_link_restart_an
2759 * @pi: pointer to the port information structure
2760 * @ena_link: if true: enable link, if false: disable link
2761 * @cd: pointer to command details structure or NULL
2763 * Sets up the link and restarts the Auto-Negotiation over the link.
2766 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2767 struct ice_sq_cd *cd)
2769 struct ice_aqc_restart_an *cmd;
2770 struct ice_aq_desc desc;
2772 cmd = &desc.params.restart_an;
2774 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2776 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2777 cmd->lport_num = pi->lport;
2779 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2781 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2783 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2787 * ice_aq_set_event_mask
2788 * @hw: pointer to the HW struct
2789 * @port_num: port number of the physical function
2790 * @mask: event mask to be set
2791 * @cd: pointer to command details structure or NULL
2793 * Set event mask (0x0613)
2796 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2797 struct ice_sq_cd *cd)
2799 struct ice_aqc_set_event_mask *cmd;
2800 struct ice_aq_desc desc;
2802 cmd = &desc.params.set_event_mask;
2804 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2806 cmd->lport_num = port_num;
2808 cmd->event_mask = CPU_TO_LE16(mask);
2809 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2813 * ice_aq_set_mac_loopback
2814 * @hw: pointer to the HW struct
2815 * @ena_lpbk: Enable or Disable loopback
2816 * @cd: pointer to command details structure or NULL
2818 * Enable/disable loopback on a given port
2821 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2823 struct ice_aqc_set_mac_lb *cmd;
2824 struct ice_aq_desc desc;
2826 cmd = &desc.params.set_mac_lb;
2828 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2830 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2832 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2836 * ice_aq_set_port_id_led
2837 * @pi: pointer to the port information
2838 * @is_orig_mode: is this LED set to original mode (by the net-list)
2839 * @cd: pointer to command details structure or NULL
2841 * Set LED value for the given port (0x06e9)
2844 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2845 struct ice_sq_cd *cd)
2847 struct ice_aqc_set_port_id_led *cmd;
2848 struct ice_hw *hw = pi->hw;
2849 struct ice_aq_desc desc;
2851 cmd = &desc.params.set_port_id_led;
2853 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2856 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2858 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2860 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2865 * @hw: pointer to the HW struct
2866 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
2867 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
2868 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
2870 * @set_page: set or ignore the page
2871 * @data: pointer to data buffer to be read/written to the I2C device.
2872 * @length: 1-16 for read, 1 for write.
2873 * @write: 0 read, 1 for write.
2874 * @cd: pointer to command details structure or NULL
2876 * Read/Write SFF EEPROM (0x06EE)
2879 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
2880 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
2881 bool write, struct ice_sq_cd *cd)
2883 struct ice_aqc_sff_eeprom *cmd;
2884 struct ice_aq_desc desc;
2885 enum ice_status status;
2887 if (!data || (mem_addr & 0xff00))
2888 return ICE_ERR_PARAM;
2890 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
2891 cmd = &desc.params.read_write_sff_param;
2892 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
2893 cmd->lport_num = (u8)(lport & 0xff);
2894 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
2895 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
2896 ICE_AQC_SFF_I2CBUS_7BIT_M) |
2898 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
2899 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
2900 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
2901 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
2903 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
2905 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
2910 * __ice_aq_get_set_rss_lut
2911 * @hw: pointer to the hardware structure
2912 * @vsi_id: VSI FW index
2913 * @lut_type: LUT table type
2914 * @lut: pointer to the LUT buffer provided by the caller
2915 * @lut_size: size of the LUT buffer
2916 * @glob_lut_idx: global LUT index
2917 * @set: set true to set the table, false to get the table
2919 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2921 static enum ice_status
2922 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2923 u16 lut_size, u8 glob_lut_idx, bool set)
2925 struct ice_aqc_get_set_rss_lut *cmd_resp;
2926 struct ice_aq_desc desc;
2927 enum ice_status status;
2930 cmd_resp = &desc.params.get_set_rss_lut;
2933 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2934 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2936 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2939 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2940 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2941 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2942 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2945 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2946 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2947 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2948 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2949 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2952 status = ICE_ERR_PARAM;
2953 goto ice_aq_get_set_rss_lut_exit;
2956 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2957 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2958 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2961 goto ice_aq_get_set_rss_lut_send;
2962 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2964 goto ice_aq_get_set_rss_lut_send;
2966 goto ice_aq_get_set_rss_lut_send;
2969 /* LUT size is only valid for Global and PF table types */
2971 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2972 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
2973 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2974 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2976 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
2977 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2978 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2979 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2981 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
2982 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2983 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
2984 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2985 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2990 status = ICE_ERR_PARAM;
2991 goto ice_aq_get_set_rss_lut_exit;
2994 ice_aq_get_set_rss_lut_send:
2995 cmd_resp->flags = CPU_TO_LE16(flags);
2996 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
2998 ice_aq_get_set_rss_lut_exit:
3003 * ice_aq_get_rss_lut
3004 * @hw: pointer to the hardware structure
3005 * @vsi_handle: software VSI handle
3006 * @lut_type: LUT table type
3007 * @lut: pointer to the LUT buffer provided by the caller
3008 * @lut_size: size of the LUT buffer
3010 * get the RSS lookup table, PF or VSI type
3013 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3014 u8 *lut, u16 lut_size)
3016 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3017 return ICE_ERR_PARAM;
3019 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3020 lut_type, lut, lut_size, 0, false);
3024 * ice_aq_set_rss_lut
3025 * @hw: pointer to the hardware structure
3026 * @vsi_handle: software VSI handle
3027 * @lut_type: LUT table type
3028 * @lut: pointer to the LUT buffer provided by the caller
3029 * @lut_size: size of the LUT buffer
3031 * set the RSS lookup table, PF or VSI type
3034 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3035 u8 *lut, u16 lut_size)
3037 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3038 return ICE_ERR_PARAM;
3040 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3041 lut_type, lut, lut_size, 0, true);
3045 * __ice_aq_get_set_rss_key
3046 * @hw: pointer to the HW struct
3047 * @vsi_id: VSI FW index
3048 * @key: pointer to key info struct
3049 * @set: set true to set the key, false to get the key
3051 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3054 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3055 struct ice_aqc_get_set_rss_keys *key,
3058 struct ice_aqc_get_set_rss_key *cmd_resp;
3059 u16 key_size = sizeof(*key);
3060 struct ice_aq_desc desc;
3062 cmd_resp = &desc.params.get_set_rss_key;
3065 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3066 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3068 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3071 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3072 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3073 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3074 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3076 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3080 * ice_aq_get_rss_key
3081 * @hw: pointer to the HW struct
3082 * @vsi_handle: software VSI handle
3083 * @key: pointer to key info struct
3085 * get the RSS key per VSI
3088 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3089 struct ice_aqc_get_set_rss_keys *key)
3091 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3092 return ICE_ERR_PARAM;
3094 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3099 * ice_aq_set_rss_key
3100 * @hw: pointer to the HW struct
3101 * @vsi_handle: software VSI handle
3102 * @keys: pointer to key info struct
3104 * set the RSS key per VSI
3107 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3108 struct ice_aqc_get_set_rss_keys *keys)
3110 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3111 return ICE_ERR_PARAM;
3113 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3118 * ice_aq_add_lan_txq
3119 * @hw: pointer to the hardware structure
3120 * @num_qgrps: Number of added queue groups
3121 * @qg_list: list of queue groups to be added
3122 * @buf_size: size of buffer for indirect command
3123 * @cd: pointer to command details structure or NULL
3125 * Add Tx LAN queue (0x0C30)
3128 * Prior to calling add Tx LAN queue:
3129 * Initialize the following as part of the Tx queue context:
3130 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3131 * Cache profile and Packet shaper profile.
3133 * After add Tx LAN queue AQ command is completed:
3134 * Interrupts should be associated with specific queues,
3135 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3139 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3140 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3141 struct ice_sq_cd *cd)
3143 u16 i, sum_header_size, sum_q_size = 0;
3144 struct ice_aqc_add_tx_qgrp *list;
3145 struct ice_aqc_add_txqs *cmd;
3146 struct ice_aq_desc desc;
3148 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3150 cmd = &desc.params.add_txqs;
3152 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3155 return ICE_ERR_PARAM;
3157 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3158 return ICE_ERR_PARAM;
3160 sum_header_size = num_qgrps *
3161 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3164 for (i = 0; i < num_qgrps; i++) {
3165 struct ice_aqc_add_txqs_perq *q = list->txqs;
3167 sum_q_size += list->num_txqs * sizeof(*q);
3168 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3171 if (buf_size != (sum_header_size + sum_q_size))
3172 return ICE_ERR_PARAM;
3174 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3176 cmd->num_qgrps = num_qgrps;
3178 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3182 * ice_aq_dis_lan_txq
3183 * @hw: pointer to the hardware structure
3184 * @num_qgrps: number of groups in the list
3185 * @qg_list: the list of groups to disable
3186 * @buf_size: the total size of the qg_list buffer in bytes
3187 * @rst_src: if called due to reset, specifies the reset source
3188 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3189 * @cd: pointer to command details structure or NULL
3191 * Disable LAN Tx queue (0x0C31)
3193 static enum ice_status
3194 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3195 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3196 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3197 struct ice_sq_cd *cd)
3199 struct ice_aqc_dis_txqs *cmd;
3200 struct ice_aq_desc desc;
3201 enum ice_status status;
3204 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3205 cmd = &desc.params.dis_txqs;
3206 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3208 /* qg_list can be NULL only in VM/VF reset flow */
3209 if (!qg_list && !rst_src)
3210 return ICE_ERR_PARAM;
3212 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3213 return ICE_ERR_PARAM;
3215 cmd->num_entries = num_qgrps;
3217 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3218 ICE_AQC_Q_DIS_TIMEOUT_M);
3222 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3223 cmd->vmvf_and_timeout |=
3224 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3231 /* flush pipe on time out */
3232 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3233 /* If no queue group info, we are in a reset flow. Issue the AQ */
3237 /* set RD bit to indicate that command buffer is provided by the driver
3238 * and it needs to be read by the firmware
3240 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3242 for (i = 0; i < num_qgrps; ++i) {
3243 /* Calculate the size taken up by the queue IDs in this group */
3244 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3246 /* Add the size of the group header */
3247 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3249 /* If the num of queues is even, add 2 bytes of padding */
3250 if ((qg_list[i].num_qs % 2) == 0)
3255 return ICE_ERR_PARAM;
3258 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3261 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3262 vmvf_num, hw->adminq.sq_last_status);
3264 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3265 LE16_TO_CPU(qg_list[0].q_id[0]),
3266 hw->adminq.sq_last_status);
3272 * ice_aq_move_recfg_lan_txq
3273 * @hw: pointer to the hardware structure
3274 * @num_qs: number of queues to move/reconfigure
3275 * @is_move: true if this operation involves node movement
3276 * @is_tc_change: true if this operation involves a TC change
3277 * @subseq_call: true if this operation is a subsequent call
3278 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3279 * @timeout: timeout in units of 100 usec (valid values 0-50)
3280 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3281 * @buf: struct containing src/dest TEID and per-queue info
3282 * @buf_size: size of buffer for indirect command
3283 * @txqs_moved: out param, number of queues successfully moved
3284 * @cd: pointer to command details structure or NULL
3286 * Move / Reconfigure Tx LAN queues (0x0C32)
3289 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3290 bool is_tc_change, bool subseq_call, bool flush_pipe,
3291 u8 timeout, u32 *blocked_cgds,
3292 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3293 u8 *txqs_moved, struct ice_sq_cd *cd)
3295 struct ice_aqc_move_txqs *cmd;
3296 struct ice_aq_desc desc;
3297 enum ice_status status;
3299 cmd = &desc.params.move_txqs;
3300 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3302 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3303 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3304 return ICE_ERR_PARAM;
3306 if (is_tc_change && !flush_pipe && !blocked_cgds)
3307 return ICE_ERR_PARAM;
3309 if (!is_move && !is_tc_change)
3310 return ICE_ERR_PARAM;
3312 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3315 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3318 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3321 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3324 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3326 cmd->num_qs = num_qs;
3327 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3328 ICE_AQC_Q_CMD_TIMEOUT_M);
3330 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3332 if (!status && txqs_moved)
3333 *txqs_moved = cmd->num_qs;
3335 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3336 is_tc_change && !flush_pipe)
3337 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3342 /* End of FW Admin Queue command wrappers */
3345 * ice_write_byte - write a byte to a packed context structure
3346 * @src_ctx: the context structure to read from
3347 * @dest_ctx: the context to be written to
3348 * @ce_info: a description of the struct to be filled
3351 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3353 u8 src_byte, dest_byte, mask;
3357 /* copy from the next struct field */
3358 from = src_ctx + ce_info->offset;
3360 /* prepare the bits and mask */
3361 shift_width = ce_info->lsb % 8;
3362 mask = (u8)(BIT(ce_info->width) - 1);
3367 /* shift to correct alignment */
3368 mask <<= shift_width;
3369 src_byte <<= shift_width;
3371 /* get the current bits from the target bit string */
3372 dest = dest_ctx + (ce_info->lsb / 8);
3374 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3376 dest_byte &= ~mask; /* get the bits not changing */
3377 dest_byte |= src_byte; /* add in the new bits */
3379 /* put it all back */
3380 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3384 * ice_write_word - write a word to a packed context structure
3385 * @src_ctx: the context structure to read from
3386 * @dest_ctx: the context to be written to
3387 * @ce_info: a description of the struct to be filled
3390 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3397 /* copy from the next struct field */
3398 from = src_ctx + ce_info->offset;
3400 /* prepare the bits and mask */
3401 shift_width = ce_info->lsb % 8;
3402 mask = BIT(ce_info->width) - 1;
3404 /* don't swizzle the bits until after the mask because the mask bits
3405 * will be in a different bit position on big endian machines
3407 src_word = *(u16 *)from;
3410 /* shift to correct alignment */
3411 mask <<= shift_width;
3412 src_word <<= shift_width;
3414 /* get the current bits from the target bit string */
3415 dest = dest_ctx + (ce_info->lsb / 8);
3417 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3419 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3420 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3422 /* put it all back */
3423 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3427 * ice_write_dword - write a dword to a packed context structure
3428 * @src_ctx: the context structure to read from
3429 * @dest_ctx: the context to be written to
3430 * @ce_info: a description of the struct to be filled
3433 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3435 u32 src_dword, mask;
3440 /* copy from the next struct field */
3441 from = src_ctx + ce_info->offset;
3443 /* prepare the bits and mask */
3444 shift_width = ce_info->lsb % 8;
3446 /* if the field width is exactly 32 on an x86 machine, then the shift
3447 * operation will not work because the SHL instructions count is masked
3448 * to 5 bits so the shift will do nothing
3450 if (ce_info->width < 32)
3451 mask = BIT(ce_info->width) - 1;
3455 /* don't swizzle the bits until after the mask because the mask bits
3456 * will be in a different bit position on big endian machines
3458 src_dword = *(u32 *)from;
3461 /* shift to correct alignment */
3462 mask <<= shift_width;
3463 src_dword <<= shift_width;
3465 /* get the current bits from the target bit string */
3466 dest = dest_ctx + (ce_info->lsb / 8);
3468 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3470 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3471 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3473 /* put it all back */
3474 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3478 * ice_write_qword - write a qword to a packed context structure
3479 * @src_ctx: the context structure to read from
3480 * @dest_ctx: the context to be written to
3481 * @ce_info: a description of the struct to be filled
3484 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3486 u64 src_qword, mask;
3491 /* copy from the next struct field */
3492 from = src_ctx + ce_info->offset;
3494 /* prepare the bits and mask */
3495 shift_width = ce_info->lsb % 8;
3497 /* if the field width is exactly 64 on an x86 machine, then the shift
3498 * operation will not work because the SHL instructions count is masked
3499 * to 6 bits so the shift will do nothing
3501 if (ce_info->width < 64)
3502 mask = BIT_ULL(ce_info->width) - 1;
3506 /* don't swizzle the bits until after the mask because the mask bits
3507 * will be in a different bit position on big endian machines
3509 src_qword = *(u64 *)from;
3512 /* shift to correct alignment */
3513 mask <<= shift_width;
3514 src_qword <<= shift_width;
3516 /* get the current bits from the target bit string */
3517 dest = dest_ctx + (ce_info->lsb / 8);
3519 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3521 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3522 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3524 /* put it all back */
3525 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3529 * ice_set_ctx - set context bits in packed structure
3530 * @src_ctx: pointer to a generic non-packed context structure
3531 * @dest_ctx: pointer to memory for the packed structure
3532 * @ce_info: a description of the structure to be transformed
3535 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3539 for (f = 0; ce_info[f].width; f++) {
3540 /* We have to deal with each element of the FW response
3541 * using the correct size so that we are correct regardless
3542 * of the endianness of the machine.
3544 switch (ce_info[f].size_of) {
3546 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3549 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3552 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3555 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3558 return ICE_ERR_INVAL_SIZE;
3566 * ice_read_byte - read context byte into struct
3567 * @src_ctx: the context structure to read from
3568 * @dest_ctx: the context to be written to
3569 * @ce_info: a description of the struct to be filled
3572 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3578 /* prepare the bits and mask */
3579 shift_width = ce_info->lsb % 8;
3580 mask = (u8)(BIT(ce_info->width) - 1);
3582 /* shift to correct alignment */
3583 mask <<= shift_width;
3585 /* get the current bits from the src bit string */
3586 src = src_ctx + (ce_info->lsb / 8);
3588 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3590 dest_byte &= ~(mask);
3592 dest_byte >>= shift_width;
3594 /* get the address from the struct field */
3595 target = dest_ctx + ce_info->offset;
3597 /* put it back in the struct */
3598 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3602 * ice_read_word - read context word into struct
3603 * @src_ctx: the context structure to read from
3604 * @dest_ctx: the context to be written to
3605 * @ce_info: a description of the struct to be filled
3608 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3610 u16 dest_word, mask;
3615 /* prepare the bits and mask */
3616 shift_width = ce_info->lsb % 8;
3617 mask = BIT(ce_info->width) - 1;
3619 /* shift to correct alignment */
3620 mask <<= shift_width;
3622 /* get the current bits from the src bit string */
3623 src = src_ctx + (ce_info->lsb / 8);
3625 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3627 /* the data in the memory is stored as little endian so mask it
3630 src_word &= ~(CPU_TO_LE16(mask));
3632 /* get the data back into host order before shifting */
3633 dest_word = LE16_TO_CPU(src_word);
3635 dest_word >>= shift_width;
3637 /* get the address from the struct field */
3638 target = dest_ctx + ce_info->offset;
3640 /* put it back in the struct */
3641 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3645 * ice_read_dword - read context dword into struct
3646 * @src_ctx: the context structure to read from
3647 * @dest_ctx: the context to be written to
3648 * @ce_info: a description of the struct to be filled
3651 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3653 u32 dest_dword, mask;
3658 /* prepare the bits and mask */
3659 shift_width = ce_info->lsb % 8;
3661 /* if the field width is exactly 32 on an x86 machine, then the shift
3662 * operation will not work because the SHL instructions count is masked
3663 * to 5 bits so the shift will do nothing
3665 if (ce_info->width < 32)
3666 mask = BIT(ce_info->width) - 1;
3670 /* shift to correct alignment */
3671 mask <<= shift_width;
3673 /* get the current bits from the src bit string */
3674 src = src_ctx + (ce_info->lsb / 8);
3676 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3678 /* the data in the memory is stored as little endian so mask it
3681 src_dword &= ~(CPU_TO_LE32(mask));
3683 /* get the data back into host order before shifting */
3684 dest_dword = LE32_TO_CPU(src_dword);
3686 dest_dword >>= shift_width;
3688 /* get the address from the struct field */
3689 target = dest_ctx + ce_info->offset;
3691 /* put it back in the struct */
3692 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3696 * ice_read_qword - read context qword into struct
3697 * @src_ctx: the context structure to read from
3698 * @dest_ctx: the context to be written to
3699 * @ce_info: a description of the struct to be filled
3702 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3704 u64 dest_qword, mask;
3709 /* prepare the bits and mask */
3710 shift_width = ce_info->lsb % 8;
3712 /* if the field width is exactly 64 on an x86 machine, then the shift
3713 * operation will not work because the SHL instructions count is masked
3714 * to 6 bits so the shift will do nothing
3716 if (ce_info->width < 64)
3717 mask = BIT_ULL(ce_info->width) - 1;
3721 /* shift to correct alignment */
3722 mask <<= shift_width;
3724 /* get the current bits from the src bit string */
3725 src = src_ctx + (ce_info->lsb / 8);
3727 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3729 /* the data in the memory is stored as little endian so mask it
3732 src_qword &= ~(CPU_TO_LE64(mask));
3734 /* get the data back into host order before shifting */
3735 dest_qword = LE64_TO_CPU(src_qword);
3737 dest_qword >>= shift_width;
3739 /* get the address from the struct field */
3740 target = dest_ctx + ce_info->offset;
3742 /* put it back in the struct */
3743 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3747 * ice_get_ctx - extract context bits from a packed structure
3748 * @src_ctx: pointer to a generic packed context structure
3749 * @dest_ctx: pointer to a generic non-packed context structure
3750 * @ce_info: a description of the structure to be read from
3753 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3757 for (f = 0; ce_info[f].width; f++) {
3758 switch (ce_info[f].size_of) {
3760 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3763 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3766 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3769 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3772 /* nothing to do, just keep going */
3781 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3782 * @hw: pointer to the HW struct
3783 * @vsi_handle: software VSI handle
3785 * @q_handle: software queue handle
3788 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3790 struct ice_vsi_ctx *vsi;
3791 struct ice_q_ctx *q_ctx;
3793 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3796 if (q_handle >= vsi->num_lan_q_entries[tc])
3798 if (!vsi->lan_q_ctx[tc])
3800 q_ctx = vsi->lan_q_ctx[tc];
3801 return &q_ctx[q_handle];
3806 * @pi: port information structure
3807 * @vsi_handle: software VSI handle
3809 * @q_handle: software queue handle
3810 * @num_qgrps: Number of added queue groups
3811 * @buf: list of queue groups to be added
3812 * @buf_size: size of buffer for indirect command
3813 * @cd: pointer to command details structure or NULL
3815 * This function adds one LAN queue
3818 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3819 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3820 struct ice_sq_cd *cd)
3822 struct ice_aqc_txsched_elem_data node = { 0 };
3823 struct ice_sched_node *parent;
3824 struct ice_q_ctx *q_ctx;
3825 enum ice_status status;
3828 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3831 if (num_qgrps > 1 || buf->num_txqs > 1)
3832 return ICE_ERR_MAX_LIMIT;
3836 if (!ice_is_vsi_valid(hw, vsi_handle))
3837 return ICE_ERR_PARAM;
3839 ice_acquire_lock(&pi->sched_lock);
3841 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3843 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3845 status = ICE_ERR_PARAM;
3849 /* find a parent node */
3850 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3851 ICE_SCHED_NODE_OWNER_LAN);
3853 status = ICE_ERR_PARAM;
3857 buf->parent_teid = parent->info.node_teid;
3858 node.parent_teid = parent->info.node_teid;
3859 /* Mark that the values in the "generic" section as valid. The default
3860 * value in the "generic" section is zero. This means that :
3861 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3862 * - 0 priority among siblings, indicated by Bit 1-3.
3863 * - WFQ, indicated by Bit 4.
3864 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3866 * - Bit 7 is reserved.
3867 * Without setting the generic section as valid in valid_sections, the
3868 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3870 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3872 /* add the LAN queue */
3873 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3874 if (status != ICE_SUCCESS) {
3875 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3876 LE16_TO_CPU(buf->txqs[0].txq_id),
3877 hw->adminq.sq_last_status);
3881 node.node_teid = buf->txqs[0].q_teid;
3882 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3883 q_ctx->q_handle = q_handle;
3884 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
3886 /* add a leaf node into scheduler tree queue layer */
3887 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3889 status = ice_sched_replay_q_bw(pi, q_ctx);
3892 ice_release_lock(&pi->sched_lock);
3898 * @pi: port information structure
3899 * @vsi_handle: software VSI handle
3901 * @num_queues: number of queues
3902 * @q_handles: pointer to software queue handle array
3903 * @q_ids: pointer to the q_id array
3904 * @q_teids: pointer to queue node teids
3905 * @rst_src: if called due to reset, specifies the reset source
3906 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3907 * @cd: pointer to command details structure or NULL
3909 * This function removes queues and their corresponding nodes in SW DB
3912 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3913 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3914 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3915 struct ice_sq_cd *cd)
3917 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3918 struct ice_aqc_dis_txq_item qg_list;
3919 struct ice_q_ctx *q_ctx;
3922 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3926 /* if queue is disabled already yet the disable queue command
3927 * has to be sent to complete the VF reset, then call
3928 * ice_aq_dis_lan_txq without any queue information
3931 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
3936 ice_acquire_lock(&pi->sched_lock);
3938 for (i = 0; i < num_queues; i++) {
3939 struct ice_sched_node *node;
3941 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3944 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3946 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3950 if (q_ctx->q_handle != q_handles[i]) {
3951 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3952 q_ctx->q_handle, q_handles[i]);
3955 qg_list.parent_teid = node->info.parent_teid;
3957 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
3958 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3959 sizeof(qg_list), rst_src, vmvf_num,
3962 if (status != ICE_SUCCESS)
3964 ice_free_sched_node(pi, node);
3965 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
3967 ice_release_lock(&pi->sched_lock);
3972 * ice_cfg_vsi_qs - configure the new/existing VSI queues
3973 * @pi: port information structure
3974 * @vsi_handle: software VSI handle
3975 * @tc_bitmap: TC bitmap
3976 * @maxqs: max queues array per TC
3977 * @owner: LAN or RDMA
3979 * This function adds/updates the VSI queues per TC.
3981 static enum ice_status
3982 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3983 u16 *maxqs, u8 owner)
3985 enum ice_status status = ICE_SUCCESS;
3988 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3991 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3992 return ICE_ERR_PARAM;
3994 ice_acquire_lock(&pi->sched_lock);
3996 ice_for_each_traffic_class(i) {
3997 /* configuration is possible only if TC node is present */
3998 if (!ice_sched_get_tc_node(pi, i))
4001 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4002 ice_is_tc_ena(tc_bitmap, i));
4007 ice_release_lock(&pi->sched_lock);
4012 * ice_cfg_vsi_lan - configure VSI LAN queues
4013 * @pi: port information structure
4014 * @vsi_handle: software VSI handle
4015 * @tc_bitmap: TC bitmap
4016 * @max_lanqs: max LAN queues array per TC
4018 * This function adds/updates the VSI LAN queues per TC.
4021 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4024 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4025 ICE_SCHED_NODE_OWNER_LAN);
4029 * ice_replay_pre_init - replay pre initialization
4030 * @hw: pointer to the HW struct
4032 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4034 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
4036 struct ice_switch_info *sw = hw->switch_info;
4039 /* Delete old entries from replay filter list head if there is any */
4040 ice_rm_all_sw_replay_rule_info(hw);
4041 /* In start of replay, move entries into replay_rules list, it
4042 * will allow adding rules entries back to filt_rules list,
4043 * which is operational list.
4045 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4046 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4047 &sw->recp_list[i].filt_replay_rules);
4048 ice_sched_replay_agg_vsi_preinit(hw);
4050 return ice_sched_replay_tc_node_bw(hw->port_info);
4054 * ice_replay_vsi - replay VSI configuration
4055 * @hw: pointer to the HW struct
4056 * @vsi_handle: driver VSI handle
4058 * Restore all VSI configuration after reset. It is required to call this
4059 * function with main VSI first.
4061 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4063 enum ice_status status;
4065 if (!ice_is_vsi_valid(hw, vsi_handle))
4066 return ICE_ERR_PARAM;
4068 /* Replay pre-initialization if there is any */
4069 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
4070 status = ice_replay_pre_init(hw);
4074 /* Replay per VSI all RSS configurations */
4075 status = ice_replay_rss_cfg(hw, vsi_handle);
4078 /* Replay per VSI all filters */
4079 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
4081 status = ice_replay_vsi_agg(hw, vsi_handle);
4086 * ice_replay_post - post replay configuration cleanup
4087 * @hw: pointer to the HW struct
4089 * Post replay cleanup.
4091 void ice_replay_post(struct ice_hw *hw)
4093 /* Delete old entries from replay filter list head */
4094 ice_rm_all_sw_replay_rule_info(hw);
4095 ice_sched_replay_agg(hw);
4099 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4100 * @hw: ptr to the hardware info
4101 * @reg: offset of 64 bit HW register to read from
4102 * @prev_stat_loaded: bool to specify if previous stats are loaded
4103 * @prev_stat: ptr to previous loaded stat value
4104 * @cur_stat: ptr to current stat value
4107 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4108 u64 *prev_stat, u64 *cur_stat)
4110 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4112 /* device stats are not reset at PFR, they likely will not be zeroed
4113 * when the driver starts. Thus, save the value from the first read
4114 * without adding to the statistic value so that we report stats which
4115 * count up from zero.
4117 if (!prev_stat_loaded) {
4118 *prev_stat = new_data;
4122 /* Calculate the difference between the new and old values, and then
4123 * add it to the software stat value.
4125 if (new_data >= *prev_stat)
4126 *cur_stat += new_data - *prev_stat;
4128 /* to manage the potential roll-over */
4129 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4131 /* Update the previously stored value to prepare for next read */
4132 *prev_stat = new_data;
4136 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4137 * @hw: ptr to the hardware info
4138 * @reg: offset of HW register to read from
4139 * @prev_stat_loaded: bool to specify if previous stats are loaded
4140 * @prev_stat: ptr to previous loaded stat value
4141 * @cur_stat: ptr to current stat value
4144 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4145 u64 *prev_stat, u64 *cur_stat)
4149 new_data = rd32(hw, reg);
4151 /* device stats are not reset at PFR, they likely will not be zeroed
4152 * when the driver starts. Thus, save the value from the first read
4153 * without adding to the statistic value so that we report stats which
4154 * count up from zero.
4156 if (!prev_stat_loaded) {
4157 *prev_stat = new_data;
4161 /* Calculate the difference between the new and old values, and then
4162 * add it to the software stat value.
4164 if (new_data >= *prev_stat)
4165 *cur_stat += new_data - *prev_stat;
4167 /* to manage the potential roll-over */
4168 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4170 /* Update the previously stored value to prepare for next read */
4171 *prev_stat = new_data;
4175 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4176 * @hw: ptr to the hardware info
4177 * @vsi_handle: VSI handle
4178 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4179 * @cur_stats: ptr to current stats structure
4181 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4182 * thus cannot be read using the normal ice_stat_update32 function.
4184 * Read the GLV_REPC register associated with the given VSI, and update the
4185 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4187 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4188 * cleared each time it's read.
4190 * Note that the GLV_RDPC register also counts the causes that would trigger
4191 * GLV_REPC. However, it does not give the finer grained detail about why the
4192 * packets are being dropped. The GLV_REPC values can be used to distinguish
4193 * whether Rx packets are dropped due to errors or due to no available
4197 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4198 struct ice_eth_stats *cur_stats)
4200 u16 vsi_num, no_desc, error_cnt;
4203 if (!ice_is_vsi_valid(hw, vsi_handle))
4206 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4208 /* If we haven't loaded stats yet, just clear the current value */
4209 if (!prev_stat_loaded) {
4210 wr32(hw, GLV_REPC(vsi_num), 0);
4214 repc = rd32(hw, GLV_REPC(vsi_num));
4215 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4216 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4218 /* Clear the count by writing to the stats register */
4219 wr32(hw, GLV_REPC(vsi_num), 0);
4221 cur_stats->rx_no_desc += no_desc;
4222 cur_stats->rx_errors += error_cnt;
4226 * ice_sched_query_elem - query element information from HW
4227 * @hw: pointer to the HW struct
4228 * @node_teid: node TEID to be queried
4229 * @buf: buffer to element information
4231 * This function queries HW element information
4234 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4235 struct ice_aqc_get_elem *buf)
4237 u16 buf_size, num_elem_ret = 0;
4238 enum ice_status status;
4240 buf_size = sizeof(*buf);
4241 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4242 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4243 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4245 if (status != ICE_SUCCESS || num_elem_ret != 1)
4246 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4251 * ice_get_fw_mode - returns FW mode
4252 * @hw: pointer to the HW struct
4254 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4256 #define ICE_FW_MODE_DBG_M BIT(0)
4257 #define ICE_FW_MODE_REC_M BIT(1)
4258 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4261 /* check the current FW mode */
4262 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4264 if (fw_mode & ICE_FW_MODE_DBG_M)
4265 return ICE_FW_MODE_DBG;
4266 else if (fw_mode & ICE_FW_MODE_REC_M)
4267 return ICE_FW_MODE_REC;
4268 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4269 return ICE_FW_MODE_ROLLBACK;
4271 return ICE_FW_MODE_NORMAL;