1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 200
14 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
15 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
16 ((ICE_RX_OPC_MDID << \
17 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
18 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
19 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
20 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
22 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
23 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
24 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
26 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
28 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
29 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
30 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
31 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
35 * ice_set_mac_type - Sets MAC type
36 * @hw: pointer to the HW structure
38 * This function sets the MAC type of the adapter based on the
39 * vendor ID and device ID stored in the HW structure.
41 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
43 enum ice_status status = ICE_SUCCESS;
45 ice_debug(hw, ICE_DBG_TRACE, "ice_set_mac_type\n");
47 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) {
48 switch (hw->device_id) {
50 hw->mac_type = ICE_MAC_GENERIC;
54 status = ICE_ERR_DEVICE_NOT_SUPPORTED;
57 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n",
58 hw->mac_type, status);
65 * ice_clear_pf_cfg - Clear PF configuration
66 * @hw: pointer to the hardware structure
68 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
69 * configuration, flow director filters, etc.).
71 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
73 struct ice_aq_desc desc;
75 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
77 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
81 * ice_aq_manage_mac_read - manage MAC address read command
82 * @hw: pointer to the HW struct
83 * @buf: a virtual buffer to hold the manage MAC read response
84 * @buf_size: Size of the virtual buffer
85 * @cd: pointer to command details structure or NULL
87 * This function is used to return per PF station MAC address (0x0107).
88 * NOTE: Upon successful completion of this command, MAC address information
89 * is returned in user specified buffer. Please interpret user specified
90 * buffer as "manage_mac_read" response.
91 * Response such as various MAC addresses are stored in HW struct (port.mac)
92 * ice_aq_discover_caps is expected to be called before this function is called.
94 static enum ice_status
95 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
98 struct ice_aqc_manage_mac_read_resp *resp;
99 struct ice_aqc_manage_mac_read *cmd;
100 struct ice_aq_desc desc;
101 enum ice_status status;
105 cmd = &desc.params.mac_read;
107 if (buf_size < sizeof(*resp))
108 return ICE_ERR_BUF_TOO_SHORT;
110 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
112 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
116 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
117 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
119 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
120 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
124 /* A single port can report up to two (LAN and WoL) addresses */
125 for (i = 0; i < cmd->num_addr; i++)
126 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
127 ice_memcpy(hw->port_info->mac.lan_addr,
128 resp[i].mac_addr, ETH_ALEN,
130 ice_memcpy(hw->port_info->mac.perm_addr,
132 ETH_ALEN, ICE_DMA_TO_NONDMA);
140 * ice_aq_get_phy_caps - returns PHY capabilities
141 * @pi: port information structure
142 * @qual_mods: report qualified modules
143 * @report_mode: report mode capabilities
144 * @pcaps: structure for PHY capabilities to be filled
145 * @cd: pointer to command details structure or NULL
147 * Returns the various PHY capabilities supported on the Port (0x0600)
150 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
151 struct ice_aqc_get_phy_caps_data *pcaps,
152 struct ice_sq_cd *cd)
154 struct ice_aqc_get_phy_caps *cmd;
155 u16 pcaps_size = sizeof(*pcaps);
156 struct ice_aq_desc desc;
157 enum ice_status status;
159 cmd = &desc.params.get_phy;
161 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
162 return ICE_ERR_PARAM;
164 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
167 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
169 cmd->param0 |= CPU_TO_LE16(report_mode);
170 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
172 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
173 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
174 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
181 * ice_get_media_type - Gets media type
182 * @pi: port information structure
184 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
186 struct ice_link_status *hw_link_info;
189 return ICE_MEDIA_UNKNOWN;
191 hw_link_info = &pi->phy.link_info;
192 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
193 /* If more than one media type is selected, report unknown */
194 return ICE_MEDIA_UNKNOWN;
196 if (hw_link_info->phy_type_low) {
197 switch (hw_link_info->phy_type_low) {
198 case ICE_PHY_TYPE_LOW_1000BASE_SX:
199 case ICE_PHY_TYPE_LOW_1000BASE_LX:
200 case ICE_PHY_TYPE_LOW_10GBASE_SR:
201 case ICE_PHY_TYPE_LOW_10GBASE_LR:
202 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
203 case ICE_PHY_TYPE_LOW_25GBASE_SR:
204 case ICE_PHY_TYPE_LOW_25GBASE_LR:
205 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
206 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
207 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
208 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
209 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
210 case ICE_PHY_TYPE_LOW_50GBASE_SR:
211 case ICE_PHY_TYPE_LOW_50GBASE_FR:
212 case ICE_PHY_TYPE_LOW_50GBASE_LR:
213 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
214 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
215 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
216 case ICE_PHY_TYPE_LOW_100GBASE_DR:
217 return ICE_MEDIA_FIBER;
218 case ICE_PHY_TYPE_LOW_100BASE_TX:
219 case ICE_PHY_TYPE_LOW_1000BASE_T:
220 case ICE_PHY_TYPE_LOW_2500BASE_T:
221 case ICE_PHY_TYPE_LOW_5GBASE_T:
222 case ICE_PHY_TYPE_LOW_10GBASE_T:
223 case ICE_PHY_TYPE_LOW_25GBASE_T:
224 return ICE_MEDIA_BASET;
225 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
226 case ICE_PHY_TYPE_LOW_25GBASE_CR:
227 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
228 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
229 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
230 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
231 case ICE_PHY_TYPE_LOW_50GBASE_CP:
232 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
233 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
234 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
236 case ICE_PHY_TYPE_LOW_1000BASE_KX:
237 case ICE_PHY_TYPE_LOW_2500BASE_KX:
238 case ICE_PHY_TYPE_LOW_2500BASE_X:
239 case ICE_PHY_TYPE_LOW_5GBASE_KR:
240 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
241 case ICE_PHY_TYPE_LOW_25GBASE_KR:
242 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
243 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
244 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
245 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
246 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
247 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
248 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
249 return ICE_MEDIA_BACKPLANE;
252 switch (hw_link_info->phy_type_high) {
253 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
254 return ICE_MEDIA_BACKPLANE;
257 return ICE_MEDIA_UNKNOWN;
261 * ice_aq_get_link_info
262 * @pi: port information structure
263 * @ena_lse: enable/disable LinkStatusEvent reporting
264 * @link: pointer to link status structure - optional
265 * @cd: pointer to command details structure or NULL
267 * Get Link Status (0x607). Returns the link status of the adapter.
270 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
271 struct ice_link_status *link, struct ice_sq_cd *cd)
273 struct ice_aqc_get_link_status_data link_data = { 0 };
274 struct ice_aqc_get_link_status *resp;
275 struct ice_link_status *li_old, *li;
276 enum ice_media_type *hw_media_type;
277 struct ice_fc_info *hw_fc_info;
278 bool tx_pause, rx_pause;
279 struct ice_aq_desc desc;
280 enum ice_status status;
285 return ICE_ERR_PARAM;
287 li_old = &pi->phy.link_info_old;
288 hw_media_type = &pi->phy.media_type;
289 li = &pi->phy.link_info;
290 hw_fc_info = &pi->fc;
292 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
293 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
294 resp = &desc.params.get_link_status;
295 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
296 resp->lport_num = pi->lport;
298 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
300 if (status != ICE_SUCCESS)
303 /* save off old link status information */
306 /* update current link status information */
307 li->link_speed = LE16_TO_CPU(link_data.link_speed);
308 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
309 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
310 *hw_media_type = ice_get_media_type(pi);
311 li->link_info = link_data.link_info;
312 li->an_info = link_data.an_info;
313 li->ext_info = link_data.ext_info;
314 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
315 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
316 li->topo_media_conflict = link_data.topo_media_conflict;
317 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
318 ICE_AQ_CFG_PACING_TYPE_M);
321 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
322 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
323 if (tx_pause && rx_pause)
324 hw_fc_info->current_mode = ICE_FC_FULL;
326 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
328 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
330 hw_fc_info->current_mode = ICE_FC_NONE;
332 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
334 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
335 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
336 (unsigned long long)li->phy_type_low);
337 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
338 (unsigned long long)li->phy_type_high);
339 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
340 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
341 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
342 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
343 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
344 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
345 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
347 /* save link status information */
351 /* flag cleared so calling functions don't call AQ again */
352 pi->phy.get_link_info = false;
358 * ice_init_flex_flags
359 * @hw: pointer to the hardware structure
360 * @prof_id: Rx Descriptor Builder profile ID
362 * Function to initialize Rx flex flags
364 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
368 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
369 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
370 * flexiflags1[3:0] - Not used for flag programming
371 * flexiflags2[7:0] - Tunnel and VLAN types
372 * 2 invalid fields in last index
375 /* Rx flex flags are currently programmed for the NIC profiles only.
376 * Different flag bit programming configurations can be added per
379 case ICE_RXDID_FLEX_NIC:
380 case ICE_RXDID_FLEX_NIC_2:
381 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
382 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
384 /* flex flag 1 is not used for flexi-flag programming, skipping
385 * these four FLG64 bits.
387 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
388 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
389 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
390 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
391 ICE_FLG_EVLAN_x9100, idx++);
392 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
393 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
394 ICE_FLG_TNL0, idx++);
395 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
396 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
400 ice_debug(hw, ICE_DBG_INIT,
401 "Flag programming for profile ID %d not supported\n",
408 * @hw: pointer to the hardware structure
409 * @prof_id: Rx Descriptor Builder profile ID
411 * Function to initialize flex descriptors
413 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
415 enum ice_flex_mdid mdid;
418 case ICE_RXDID_FLEX_NIC:
419 case ICE_RXDID_FLEX_NIC_2:
420 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
421 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
422 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
424 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
425 ICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH;
427 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
429 ice_init_flex_flags(hw, prof_id);
433 ice_debug(hw, ICE_DBG_INIT,
434 "Field init for profile ID %d not supported\n",
441 * @hw: pointer to the HW struct
442 * @max_frame_size: Maximum Frame Size to be supported
443 * @cd: pointer to command details structure or NULL
445 * Set MAC configuration (0x0603)
448 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
450 u16 fc_threshold_val, tx_timer_val;
451 struct ice_aqc_set_mac_cfg *cmd;
452 struct ice_aq_desc desc;
455 cmd = &desc.params.set_mac_cfg;
457 if (max_frame_size == 0)
458 return ICE_ERR_PARAM;
460 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
462 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
464 /* We read back the transmit timer and fc threshold value of
465 * LFC. Thus, we will use index =
466 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
468 * Also, because we are opearating on transmit timer and fc
469 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
471 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
473 /* Retrieve the transmit timer */
475 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
476 tx_timer_val = reg_val &
477 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
478 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
480 /* Retrieve the fc threshold */
482 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
483 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);
484 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);
486 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
490 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
491 * @hw: pointer to the HW struct
493 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
495 struct ice_switch_info *sw;
497 hw->switch_info = (struct ice_switch_info *)
498 ice_malloc(hw, sizeof(*hw->switch_info));
499 sw = hw->switch_info;
502 return ICE_ERR_NO_MEMORY;
504 INIT_LIST_HEAD(&sw->vsi_list_map_head);
506 return ice_init_def_sw_recp(hw);
510 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
511 * @hw: pointer to the HW struct
513 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
515 struct ice_switch_info *sw = hw->switch_info;
516 struct ice_vsi_list_map_info *v_pos_map;
517 struct ice_vsi_list_map_info *v_tmp_map;
518 struct ice_sw_recipe *recps;
521 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
522 ice_vsi_list_map_info, list_entry) {
523 LIST_DEL(&v_pos_map->list_entry);
524 ice_free(hw, v_pos_map);
526 recps = hw->switch_info->recp_list;
527 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
528 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
530 recps[i].root_rid = i;
531 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
532 &recps[i].rg_list, ice_recp_grp_entry,
534 LIST_DEL(&rg_entry->l_entry);
535 ice_free(hw, rg_entry);
538 if (recps[i].adv_rule) {
539 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
540 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
542 ice_destroy_lock(&recps[i].filt_rule_lock);
543 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
544 &recps[i].filt_rules,
545 ice_adv_fltr_mgmt_list_entry,
547 LIST_DEL(&lst_itr->list_entry);
548 ice_free(hw, lst_itr->lkups);
549 ice_free(hw, lst_itr);
552 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
554 ice_destroy_lock(&recps[i].filt_rule_lock);
555 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
556 &recps[i].filt_rules,
557 ice_fltr_mgmt_list_entry,
559 LIST_DEL(&lst_itr->list_entry);
560 ice_free(hw, lst_itr);
563 if (recps[i].root_buf)
564 ice_free(hw, recps[i].root_buf);
566 ice_rm_all_sw_replay_rule_info(hw);
567 ice_free(hw, sw->recp_list);
571 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \
572 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))
573 #define ICE_FW_LOG_DESC_SIZE_MAX \
574 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)
577 * ice_get_fw_log_cfg - get FW logging configuration
578 * @hw: pointer to the HW struct
580 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw)
582 struct ice_aqc_fw_logging_data *config;
583 struct ice_aq_desc desc;
584 enum ice_status status;
587 size = ICE_FW_LOG_DESC_SIZE_MAX;
588 config = (struct ice_aqc_fw_logging_data *)ice_malloc(hw, size);
590 return ICE_ERR_NO_MEMORY;
592 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info);
594 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_BUF);
595 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
597 status = ice_aq_send_cmd(hw, &desc, config, size, NULL);
601 /* Save fw logging information into the HW structure */
602 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
605 v = LE16_TO_CPU(config->entry[i]);
606 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
607 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S;
609 if (m < ICE_AQC_FW_LOG_ID_MAX)
610 hw->fw_log.evnts[m].cur = flgs;
614 ice_free(hw, config);
620 * ice_cfg_fw_log - configure FW logging
621 * @hw: pointer to the HW struct
622 * @enable: enable certain FW logging events if true, disable all if false
624 * This function enables/disables the FW logging via Rx CQ events and a UART
625 * port based on predetermined configurations. FW logging via the Rx CQ can be
626 * enabled/disabled for individual PF's. However, FW logging via the UART can
627 * only be enabled/disabled for all PFs on the same device.
629 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
630 * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
631 * before initializing the device.
633 * When re/configuring FW logging, callers need to update the "cfg" elements of
634 * the hw->fw_log.evnts array with the desired logging event configurations for
635 * modules of interest. When disabling FW logging completely, the callers can
636 * just pass false in the "enable" parameter. On completion, the function will
637 * update the "cur" element of the hw->fw_log.evnts array with the resulting
638 * logging event configurations of the modules that are being re/configured. FW
639 * logging modules that are not part of a reconfiguration operation retain their
642 * Before resetting the device, it is recommended that the driver disables FW
643 * logging before shutting down the control queue. When disabling FW logging
644 * ("enable" = false), the latest configurations of FW logging events stored in
645 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
648 * When enabling FW logging to emit log messages via the Rx CQ during the
649 * device's initialization phase, a mechanism alternative to interrupt handlers
650 * needs to be used to extract FW log messages from the Rx CQ periodically and
651 * to prevent the Rx CQ from being full and stalling other types of control
652 * messages from FW to SW. Interrupts are typically disabled during the device's
653 * initialization phase.
655 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
657 struct ice_aqc_fw_logging_data *data = NULL;
658 struct ice_aqc_fw_logging *cmd;
659 enum ice_status status = ICE_SUCCESS;
660 u16 i, chgs = 0, len = 0;
661 struct ice_aq_desc desc;
665 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
668 /* Disable FW logging only when the control queue is still responsive */
670 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
673 /* Get current FW log settings */
674 status = ice_get_fw_log_cfg(hw);
678 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
679 cmd = &desc.params.fw_logging;
681 /* Indicate which controls are valid */
682 if (hw->fw_log.cq_en)
683 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
685 if (hw->fw_log.uart_en)
686 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
689 /* Fill in an array of entries with FW logging modules and
690 * logging events being reconfigured.
692 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
695 /* Keep track of enabled event types */
696 actv_evnts |= hw->fw_log.evnts[i].cfg;
698 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
702 data = (struct ice_aqc_fw_logging_data *)
704 ICE_FW_LOG_DESC_SIZE_MAX);
706 return ICE_ERR_NO_MEMORY;
709 val = i << ICE_AQC_FW_LOG_ID_S;
710 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
711 data->entry[chgs++] = CPU_TO_LE16(val);
714 /* Only enable FW logging if at least one module is specified.
715 * If FW logging is currently enabled but all modules are not
716 * enabled to emit log messages, disable FW logging altogether.
719 /* Leave if there is effectively no change */
723 if (hw->fw_log.cq_en)
724 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
726 if (hw->fw_log.uart_en)
727 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
730 len = ICE_FW_LOG_DESC_SIZE(chgs);
731 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
735 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
737 /* Update the current configuration to reflect events enabled.
738 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
739 * logging mode is enabled for the device. They do not reflect
740 * actual modules being enabled to emit log messages. So, their
741 * values remain unchanged even when all modules are disabled.
743 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
745 hw->fw_log.actv_evnts = actv_evnts;
746 for (i = 0; i < cnt; i++) {
750 /* When disabling all FW logging events as part
751 * of device's de-initialization, the original
752 * configurations are retained, and can be used
753 * to reconfigure FW logging later if the device
756 hw->fw_log.evnts[i].cur = 0;
760 v = LE16_TO_CPU(data->entry[i]);
761 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
762 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
775 * @hw: pointer to the HW struct
776 * @desc: pointer to the AQ message descriptor
777 * @buf: pointer to the buffer accompanying the AQ message
779 * Formats a FW Log message and outputs it via the standard driver logs.
781 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
783 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n");
784 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf,
785 LE16_TO_CPU(desc->datalen));
786 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n");
790 * ice_get_itr_intrl_gran - determine int/intrl granularity
791 * @hw: pointer to the HW struct
793 * Determines the itr/intrl granularities based on the maximum aggregate
794 * bandwidth according to the device's configuration during power-on.
796 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
798 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
799 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
800 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
802 switch (max_agg_bw) {
803 case ICE_MAX_AGG_BW_200G:
804 case ICE_MAX_AGG_BW_100G:
805 case ICE_MAX_AGG_BW_50G:
806 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
807 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
809 case ICE_MAX_AGG_BW_25G:
810 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
811 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
817 * ice_init_hw - main hardware initialization routine
818 * @hw: pointer to the hardware structure
820 enum ice_status ice_init_hw(struct ice_hw *hw)
822 struct ice_aqc_get_phy_caps_data *pcaps;
823 enum ice_status status;
827 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
830 /* Set MAC type based on DeviceID */
831 status = ice_set_mac_type(hw);
835 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
836 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
837 PF_FUNC_RID_FUNCTION_NUMBER_S;
840 status = ice_reset(hw, ICE_RESET_PFR);
844 ice_get_itr_intrl_gran(hw);
847 status = ice_create_all_ctrlq(hw);
849 goto err_unroll_cqinit;
851 /* Enable FW logging. Not fatal if this fails. */
852 status = ice_cfg_fw_log(hw, true);
854 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
856 status = ice_clear_pf_cfg(hw);
858 goto err_unroll_cqinit;
860 /* Set bit to enable Flow Director filters */
861 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
862 INIT_LIST_HEAD(&hw->fdir_list_head);
864 ice_clear_pxe_mode(hw);
866 status = ice_init_nvm(hw);
868 goto err_unroll_cqinit;
870 status = ice_get_caps(hw);
872 goto err_unroll_cqinit;
874 hw->port_info = (struct ice_port_info *)
875 ice_malloc(hw, sizeof(*hw->port_info));
876 if (!hw->port_info) {
877 status = ICE_ERR_NO_MEMORY;
878 goto err_unroll_cqinit;
881 /* set the back pointer to HW */
882 hw->port_info->hw = hw;
884 /* Initialize port_info struct with switch configuration data */
885 status = ice_get_initial_sw_cfg(hw);
887 goto err_unroll_alloc;
891 /* Query the allocated resources for Tx scheduler */
892 status = ice_sched_query_res_alloc(hw);
894 ice_debug(hw, ICE_DBG_SCHED,
895 "Failed to get scheduler allocated resources\n");
896 goto err_unroll_alloc;
900 /* Initialize port_info struct with scheduler data */
901 status = ice_sched_init_port(hw->port_info);
903 goto err_unroll_sched;
905 pcaps = (struct ice_aqc_get_phy_caps_data *)
906 ice_malloc(hw, sizeof(*pcaps));
908 status = ICE_ERR_NO_MEMORY;
909 goto err_unroll_sched;
912 /* Initialize port_info struct with PHY capabilities */
913 status = ice_aq_get_phy_caps(hw->port_info, false,
914 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
917 goto err_unroll_sched;
919 /* Initialize port_info struct with link information */
920 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
922 goto err_unroll_sched;
923 /* need a valid SW entry point to build a Tx tree */
924 if (!hw->sw_entry_point_layer) {
925 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
926 status = ICE_ERR_CFG;
927 goto err_unroll_sched;
929 INIT_LIST_HEAD(&hw->agg_list);
930 /* Initialize max burst size */
931 if (!hw->max_burst_size)
932 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
934 status = ice_init_fltr_mgmt_struct(hw);
936 goto err_unroll_sched;
939 /* Get MAC information */
940 /* A single port can report up to two (LAN and WoL) addresses */
941 mac_buf = ice_calloc(hw, 2,
942 sizeof(struct ice_aqc_manage_mac_read_resp));
943 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
946 status = ICE_ERR_NO_MEMORY;
947 goto err_unroll_fltr_mgmt_struct;
950 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
951 ice_free(hw, mac_buf);
954 goto err_unroll_fltr_mgmt_struct;
956 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
957 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
958 /* Obtain counter base index which would be used by flow director */
959 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
961 goto err_unroll_fltr_mgmt_struct;
962 status = ice_init_hw_tbls(hw);
964 goto err_unroll_fltr_mgmt_struct;
967 err_unroll_fltr_mgmt_struct:
968 ice_cleanup_fltr_mgmt_struct(hw);
970 ice_sched_cleanup_all(hw);
972 ice_free(hw, hw->port_info);
973 hw->port_info = NULL;
975 ice_destroy_all_ctrlq(hw);
980 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
981 * @hw: pointer to the hardware structure
983 * This should be called only during nominal operation, not as a result of
984 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
985 * applicable initializations if it fails for any reason.
987 void ice_deinit_hw(struct ice_hw *hw)
989 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
990 ice_cleanup_fltr_mgmt_struct(hw);
992 ice_sched_cleanup_all(hw);
993 ice_sched_clear_agg(hw);
995 ice_free_hw_tbls(hw);
998 ice_free(hw, hw->port_info);
999 hw->port_info = NULL;
1002 /* Attempt to disable FW logging before shutting down control queues */
1003 ice_cfg_fw_log(hw, false);
1004 ice_destroy_all_ctrlq(hw);
1006 /* Clear VSI contexts if not already cleared */
1007 ice_clear_all_vsi_ctx(hw);
1011 * ice_check_reset - Check to see if a global reset is complete
1012 * @hw: pointer to the hardware structure
1014 enum ice_status ice_check_reset(struct ice_hw *hw)
1016 u32 cnt, reg = 0, grst_delay;
1018 /* Poll for Device Active state in case a recent CORER, GLOBR,
1019 * or EMPR has occurred. The grst delay value is in 100ms units.
1020 * Add 1sec for outstanding AQ commands that can take a long time.
1022 #define GLGEN_RSTCTL 0x000B8180 /* Reset Source: POR */
1023 #define GLGEN_RSTCTL_GRSTDEL_S 0
1024 #define GLGEN_RSTCTL_GRSTDEL_M MAKEMASK(0x3F, GLGEN_RSTCTL_GRSTDEL_S)
1025 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
1026 GLGEN_RSTCTL_GRSTDEL_S) + 10;
1028 for (cnt = 0; cnt < grst_delay; cnt++) {
1029 ice_msec_delay(100, true);
1030 reg = rd32(hw, GLGEN_RSTAT);
1031 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1035 if (cnt == grst_delay) {
1036 ice_debug(hw, ICE_DBG_INIT,
1037 "Global reset polling failed to complete.\n");
1038 return ICE_ERR_RESET_FAILED;
1041 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
1042 GLNVM_ULD_GLOBR_DONE_M)
1044 /* Device is Active; check Global Reset processes are done */
1045 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1046 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
1047 if (reg == ICE_RESET_DONE_MASK) {
1048 ice_debug(hw, ICE_DBG_INIT,
1049 "Global reset processes done. %d\n", cnt);
1052 ice_msec_delay(10, true);
1055 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1056 ice_debug(hw, ICE_DBG_INIT,
1057 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1059 return ICE_ERR_RESET_FAILED;
1066 * ice_pf_reset - Reset the PF
1067 * @hw: pointer to the hardware structure
1069 * If a global reset has been triggered, this function checks
1070 * for its completion and then issues the PF reset
1072 static enum ice_status ice_pf_reset(struct ice_hw *hw)
1076 /* If at function entry a global reset was already in progress, i.e.
1077 * state is not 'device active' or any of the reset done bits are not
1078 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1079 * global reset is done.
1081 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1082 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1083 /* poll on global reset currently in progress until done */
1084 if (ice_check_reset(hw))
1085 return ICE_ERR_RESET_FAILED;
1091 reg = rd32(hw, PFGEN_CTRL);
1093 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1095 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1096 reg = rd32(hw, PFGEN_CTRL);
1097 if (!(reg & PFGEN_CTRL_PFSWR_M))
1100 ice_msec_delay(1, true);
1103 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1104 ice_debug(hw, ICE_DBG_INIT,
1105 "PF reset polling failed to complete.\n");
1106 return ICE_ERR_RESET_FAILED;
1113 * ice_reset - Perform different types of reset
1114 * @hw: pointer to the hardware structure
1115 * @req: reset request
1117 * This function triggers a reset as specified by the req parameter.
1120 * If anything other than a PF reset is triggered, PXE mode is restored.
1121 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1122 * interface has been restored in the rebuild flow.
1124 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1130 return ice_pf_reset(hw);
1131 case ICE_RESET_CORER:
1132 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1133 val = GLGEN_RTRIG_CORER_M;
1135 case ICE_RESET_GLOBR:
1136 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1137 val = GLGEN_RTRIG_GLOBR_M;
1140 return ICE_ERR_PARAM;
1143 val |= rd32(hw, GLGEN_RTRIG);
1144 wr32(hw, GLGEN_RTRIG, val);
1148 /* wait for the FW to be ready */
1149 return ice_check_reset(hw);
1155 * ice_copy_rxq_ctx_to_hw
1156 * @hw: pointer to the hardware structure
1157 * @ice_rxq_ctx: pointer to the rxq context
1158 * @rxq_index: the index of the Rx queue
1160 * Copies rxq context from dense structure to HW register space
1162 static enum ice_status
1163 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1168 return ICE_ERR_BAD_PTR;
1170 if (rxq_index > QRX_CTRL_MAX_INDEX)
1171 return ICE_ERR_PARAM;
1173 /* Copy each dword separately to HW */
1174 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1175 wr32(hw, QRX_CONTEXT(i, rxq_index),
1176 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1178 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1179 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1185 /* LAN Rx Queue Context */
1186 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1187 /* Field Width LSB */
1188 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1189 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1190 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1191 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1192 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1193 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1194 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1195 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1196 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1197 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1198 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1199 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1200 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1201 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1202 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1203 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1204 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1205 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1206 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1207 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1213 * @hw: pointer to the hardware structure
1214 * @rlan_ctx: pointer to the rxq context
1215 * @rxq_index: the index of the Rx queue
1217 * Converts rxq context from sparse to dense structure and then writes
1218 * it to HW register space and enables the hardware to prefetch descriptors
1219 * instead of only fetching them on demand
1222 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1225 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1228 return ICE_ERR_BAD_PTR;
1230 rlan_ctx->prefena = 1;
1232 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1233 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1236 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1239 * @hw: pointer to the hardware structure
1240 * @rxq_index: the index of the Rx queue to clear
1242 * Clears rxq context in HW register space
1244 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1248 if (rxq_index > QRX_CTRL_MAX_INDEX)
1249 return ICE_ERR_PARAM;
1251 /* Clear each dword register separately */
1252 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1253 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1257 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1259 /* LAN Tx Queue Context */
1260 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1261 /* Field Width LSB */
1262 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1263 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1264 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1265 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1266 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1267 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1268 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1269 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1270 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1271 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1272 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1273 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1274 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1275 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1276 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1277 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1278 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1279 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1280 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1281 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1282 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1283 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1284 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1285 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1286 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1287 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1288 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 110, 171),
1292 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1294 * ice_copy_tx_cmpltnq_ctx_to_hw
1295 * @hw: pointer to the hardware structure
1296 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1297 * @tx_cmpltnq_index: the index of the completion queue
1299 * Copies Tx completion queue context from dense structure to HW register space
1301 static enum ice_status
1302 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1303 u32 tx_cmpltnq_index)
1307 if (!ice_tx_cmpltnq_ctx)
1308 return ICE_ERR_BAD_PTR;
1310 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1311 return ICE_ERR_PARAM;
1313 /* Copy each dword separately to HW */
1314 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1315 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1316 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1318 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1319 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1325 /* LAN Tx Completion Queue Context */
1326 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1327 /* Field Width LSB */
1328 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1329 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1330 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1331 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1332 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1333 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1334 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1335 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1336 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1337 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1342 * ice_write_tx_cmpltnq_ctx
1343 * @hw: pointer to the hardware structure
1344 * @tx_cmpltnq_ctx: pointer to the completion queue context
1345 * @tx_cmpltnq_index: the index of the completion queue
1347 * Converts completion queue context from sparse to dense structure and then
1348 * writes it to HW register space
1351 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1352 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1353 u32 tx_cmpltnq_index)
1355 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1357 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1358 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1362 * ice_clear_tx_cmpltnq_ctx
1363 * @hw: pointer to the hardware structure
1364 * @tx_cmpltnq_index: the index of the completion queue to clear
1366 * Clears Tx completion queue context in HW register space
1369 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1373 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1374 return ICE_ERR_PARAM;
1376 /* Clear each dword register separately */
1377 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1378 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1384 * ice_copy_tx_drbell_q_ctx_to_hw
1385 * @hw: pointer to the hardware structure
1386 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1387 * @tx_drbell_q_index: the index of the doorbell queue
1389 * Copies doorbell queue context from dense structure to HW register space
1391 static enum ice_status
1392 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1393 u32 tx_drbell_q_index)
1397 if (!ice_tx_drbell_q_ctx)
1398 return ICE_ERR_BAD_PTR;
1400 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1401 return ICE_ERR_PARAM;
1403 /* Copy each dword separately to HW */
1404 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1405 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1406 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1408 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1409 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1415 /* LAN Tx Doorbell Queue Context info */
1416 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1417 /* Field Width LSB */
1418 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1419 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1420 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1421 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1422 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1423 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1424 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1425 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1426 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1427 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1428 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1433 * ice_write_tx_drbell_q_ctx
1434 * @hw: pointer to the hardware structure
1435 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1436 * @tx_drbell_q_index: the index of the doorbell queue
1438 * Converts doorbell queue context from sparse to dense structure and then
1439 * writes it to HW register space
1442 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1443 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1444 u32 tx_drbell_q_index)
1446 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1448 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1449 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1453 * ice_clear_tx_drbell_q_ctx
1454 * @hw: pointer to the hardware structure
1455 * @tx_drbell_q_index: the index of the doorbell queue to clear
1457 * Clears doorbell queue context in HW register space
1460 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1464 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1465 return ICE_ERR_PARAM;
1467 /* Clear each dword register separately */
1468 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1469 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1473 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1476 /* FW Admin Queue command wrappers */
1479 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1480 * @hw: pointer to the HW struct
1481 * @desc: descriptor describing the command
1482 * @buf: buffer to use for indirect commands (NULL for direct commands)
1483 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1484 * @cd: pointer to command details structure
1486 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1489 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1490 u16 buf_size, struct ice_sq_cd *cd)
1492 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1497 * @hw: pointer to the HW struct
1498 * @cd: pointer to command details structure or NULL
1500 * Get the firmware version (0x0001) from the admin queue commands
1502 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1504 struct ice_aqc_get_ver *resp;
1505 struct ice_aq_desc desc;
1506 enum ice_status status;
1508 resp = &desc.params.get_ver;
1510 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1512 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1515 hw->fw_branch = resp->fw_branch;
1516 hw->fw_maj_ver = resp->fw_major;
1517 hw->fw_min_ver = resp->fw_minor;
1518 hw->fw_patch = resp->fw_patch;
1519 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1520 hw->api_branch = resp->api_branch;
1521 hw->api_maj_ver = resp->api_major;
1522 hw->api_min_ver = resp->api_minor;
1523 hw->api_patch = resp->api_patch;
1530 * ice_aq_send_driver_ver
1531 * @hw: pointer to the HW struct
1532 * @dv: driver's major, minor version
1533 * @cd: pointer to command details structure or NULL
1535 * Send the driver version (0x0002) to the firmware
1538 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1539 struct ice_sq_cd *cd)
1541 struct ice_aqc_driver_ver *cmd;
1542 struct ice_aq_desc desc;
1545 cmd = &desc.params.driver_ver;
1548 return ICE_ERR_PARAM;
1550 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1552 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1553 cmd->major_ver = dv->major_ver;
1554 cmd->minor_ver = dv->minor_ver;
1555 cmd->build_ver = dv->build_ver;
1556 cmd->subbuild_ver = dv->subbuild_ver;
1559 while (len < sizeof(dv->driver_string) &&
1560 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1563 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1568 * @hw: pointer to the HW struct
1569 * @unloading: is the driver unloading itself
1571 * Tell the Firmware that we're shutting down the AdminQ and whether
1572 * or not the driver is unloading as well (0x0003).
1574 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1576 struct ice_aqc_q_shutdown *cmd;
1577 struct ice_aq_desc desc;
1579 cmd = &desc.params.q_shutdown;
1581 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1584 cmd->driver_unloading = CPU_TO_LE32(ICE_AQC_DRIVER_UNLOADING);
1586 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1591 * @hw: pointer to the HW struct
1593 * @access: access type
1594 * @sdp_number: resource number
1595 * @timeout: the maximum time in ms that the driver may hold the resource
1596 * @cd: pointer to command details structure or NULL
1598 * Requests common resource using the admin queue commands (0x0008).
1599 * When attempting to acquire the Global Config Lock, the driver can
1600 * learn of three states:
1601 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1602 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1603 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1604 * successfully downloaded the package; the driver does
1605 * not have to download the package and can continue
1608 * Note that if the caller is in an acquire lock, perform action, release lock
1609 * phase of operation, it is possible that the FW may detect a timeout and issue
1610 * a CORER. In this case, the driver will receive a CORER interrupt and will
1611 * have to determine its cause. The calling thread that is handling this flow
1612 * will likely get an error propagated back to it indicating the Download
1613 * Package, Update Package or the Release Resource AQ commands timed out.
1615 static enum ice_status
1616 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1617 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1618 struct ice_sq_cd *cd)
1620 struct ice_aqc_req_res *cmd_resp;
1621 struct ice_aq_desc desc;
1622 enum ice_status status;
1624 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1626 cmd_resp = &desc.params.res_owner;
1628 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1630 cmd_resp->res_id = CPU_TO_LE16(res);
1631 cmd_resp->access_type = CPU_TO_LE16(access);
1632 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1633 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1636 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1638 /* The completion specifies the maximum time in ms that the driver
1639 * may hold the resource in the Timeout field.
1642 /* Global config lock response utilizes an additional status field.
1644 * If the Global config lock resource is held by some other driver, the
1645 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1646 * and the timeout field indicates the maximum time the current owner
1647 * of the resource has to free it.
1649 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1650 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1651 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1653 } else if (LE16_TO_CPU(cmd_resp->status) ==
1654 ICE_AQ_RES_GLBL_IN_PROG) {
1655 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1656 return ICE_ERR_AQ_ERROR;
1657 } else if (LE16_TO_CPU(cmd_resp->status) ==
1658 ICE_AQ_RES_GLBL_DONE) {
1659 return ICE_ERR_AQ_NO_WORK;
1662 /* invalid FW response, force a timeout immediately */
1664 return ICE_ERR_AQ_ERROR;
1667 /* If the resource is held by some other driver, the command completes
1668 * with a busy return value and the timeout field indicates the maximum
1669 * time the current owner of the resource has to free it.
1671 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1672 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1678 * ice_aq_release_res
1679 * @hw: pointer to the HW struct
1681 * @sdp_number: resource number
1682 * @cd: pointer to command details structure or NULL
1684 * release common resource using the admin queue commands (0x0009)
1686 static enum ice_status
1687 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1688 struct ice_sq_cd *cd)
1690 struct ice_aqc_req_res *cmd;
1691 struct ice_aq_desc desc;
1693 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1695 cmd = &desc.params.res_owner;
1697 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1699 cmd->res_id = CPU_TO_LE16(res);
1700 cmd->res_number = CPU_TO_LE32(sdp_number);
1702 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1707 * @hw: pointer to the HW structure
1709 * @access: access type (read or write)
1710 * @timeout: timeout in milliseconds
1712 * This function will attempt to acquire the ownership of a resource.
1715 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1716 enum ice_aq_res_access_type access, u32 timeout)
1718 #define ICE_RES_POLLING_DELAY_MS 10
1719 u32 delay = ICE_RES_POLLING_DELAY_MS;
1720 u32 time_left = timeout;
1721 enum ice_status status;
1723 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1725 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1727 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1728 * previously acquired the resource and performed any necessary updates;
1729 * in this case the caller does not obtain the resource and has no
1730 * further work to do.
1732 if (status == ICE_ERR_AQ_NO_WORK)
1733 goto ice_acquire_res_exit;
1736 ice_debug(hw, ICE_DBG_RES,
1737 "resource %d acquire type %d failed.\n", res, access);
1739 /* If necessary, poll until the current lock owner timeouts */
1740 timeout = time_left;
1741 while (status && timeout && time_left) {
1742 ice_msec_delay(delay, true);
1743 timeout = (timeout > delay) ? timeout - delay : 0;
1744 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1746 if (status == ICE_ERR_AQ_NO_WORK)
1747 /* lock free, but no work to do */
1754 if (status && status != ICE_ERR_AQ_NO_WORK)
1755 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1757 ice_acquire_res_exit:
1758 if (status == ICE_ERR_AQ_NO_WORK) {
1759 if (access == ICE_RES_WRITE)
1760 ice_debug(hw, ICE_DBG_RES,
1761 "resource indicates no work to do.\n");
1763 ice_debug(hw, ICE_DBG_RES,
1764 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1771 * @hw: pointer to the HW structure
1774 * This function will release a resource using the proper Admin Command.
1776 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1778 enum ice_status status;
1779 u32 total_delay = 0;
1781 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1783 status = ice_aq_release_res(hw, res, 0, NULL);
1785 /* there are some rare cases when trying to release the resource
1786 * results in an admin queue timeout, so handle them correctly
1788 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1789 (total_delay < hw->adminq.sq_cmd_timeout)) {
1790 ice_msec_delay(1, true);
1791 status = ice_aq_release_res(hw, res, 0, NULL);
1797 * ice_aq_alloc_free_res - command to allocate/free resources
1798 * @hw: pointer to the HW struct
1799 * @num_entries: number of resource entries in buffer
1800 * @buf: Indirect buffer to hold data parameters and response
1801 * @buf_size: size of buffer for indirect commands
1802 * @opc: pass in the command opcode
1803 * @cd: pointer to command details structure or NULL
1805 * Helper function to allocate/free resources using the admin queue commands
1808 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1809 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1810 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1812 struct ice_aqc_alloc_free_res_cmd *cmd;
1813 struct ice_aq_desc desc;
1815 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1817 cmd = &desc.params.sw_res_ctrl;
1820 return ICE_ERR_PARAM;
1822 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1823 return ICE_ERR_PARAM;
1825 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1827 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1829 cmd->num_entries = CPU_TO_LE16(num_entries);
1831 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1835 * ice_alloc_hw_res - allocate resource
1836 * @hw: pointer to the HW struct
1837 * @type: type of resource
1838 * @num: number of resources to allocate
1839 * @btm: allocate from bottom
1840 * @res: pointer to array that will receive the resources
1843 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1845 struct ice_aqc_alloc_free_res_elem *buf;
1846 enum ice_status status;
1849 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1850 buf = (struct ice_aqc_alloc_free_res_elem *)
1851 ice_malloc(hw, buf_len);
1853 return ICE_ERR_NO_MEMORY;
1855 /* Prepare buffer to allocate resource. */
1856 buf->num_elems = CPU_TO_LE16(num);
1857 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1858 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1860 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1862 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1863 ice_aqc_opc_alloc_res, NULL);
1865 goto ice_alloc_res_exit;
1867 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1868 ICE_NONDMA_TO_NONDMA);
1876 * ice_free_hw_res - free allocated HW resource
1877 * @hw: pointer to the HW struct
1878 * @type: type of resource to free
1879 * @num: number of resources
1880 * @res: pointer to array that contains the resources to free
1883 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1885 struct ice_aqc_alloc_free_res_elem *buf;
1886 enum ice_status status;
1889 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1890 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1892 return ICE_ERR_NO_MEMORY;
1894 /* Prepare buffer to free resource. */
1895 buf->num_elems = CPU_TO_LE16(num);
1896 buf->res_type = CPU_TO_LE16(type);
1897 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1898 ICE_NONDMA_TO_NONDMA);
1900 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1901 ice_aqc_opc_free_res, NULL);
1903 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1910 * ice_get_num_per_func - determine number of resources per PF
1911 * @hw: pointer to the HW structure
1912 * @max: value to be evenly split between each PF
1914 * Determine the number of valid functions by going through the bitmap returned
1915 * from parsing capabilities and use this to calculate the number of resources
1916 * per PF based on the max value passed in.
1918 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1922 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1923 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1924 ICE_CAPS_VALID_FUNCS_M);
1933 * ice_parse_caps - parse function/device capabilities
1934 * @hw: pointer to the HW struct
1935 * @buf: pointer to a buffer containing function/device capability records
1936 * @cap_count: number of capability records in the list
1937 * @opc: type of capabilities list to parse
1939 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1942 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1943 enum ice_adminq_opc opc)
1945 struct ice_aqc_list_caps_elem *cap_resp;
1946 struct ice_hw_func_caps *func_p = NULL;
1947 struct ice_hw_dev_caps *dev_p = NULL;
1948 struct ice_hw_common_caps *caps;
1955 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1957 if (opc == ice_aqc_opc_list_dev_caps) {
1958 dev_p = &hw->dev_caps;
1959 caps = &dev_p->common_cap;
1961 } else if (opc == ice_aqc_opc_list_func_caps) {
1962 func_p = &hw->func_caps;
1963 caps = &func_p->common_cap;
1964 prefix = "func cap";
1966 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1970 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1971 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1972 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1973 u32 number = LE32_TO_CPU(cap_resp->number);
1974 u16 cap = LE16_TO_CPU(cap_resp->cap);
1977 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1978 caps->valid_functions = number;
1979 ice_debug(hw, ICE_DBG_INIT,
1980 "%s: valid functions = %d\n", prefix,
1981 caps->valid_functions);
1983 case ICE_AQC_CAPS_VSI:
1985 dev_p->num_vsi_allocd_to_host = number;
1986 ice_debug(hw, ICE_DBG_INIT,
1987 "%s: num VSI alloc to host = %d\n",
1989 dev_p->num_vsi_allocd_to_host);
1990 } else if (func_p) {
1991 func_p->guar_num_vsi =
1992 ice_get_num_per_func(hw, ICE_MAX_VSI);
1993 ice_debug(hw, ICE_DBG_INIT,
1994 "%s: num guaranteed VSI (fw) = %d\n",
1996 ice_debug(hw, ICE_DBG_INIT,
1997 "%s: num guaranteed VSI = %d\n",
1998 prefix, func_p->guar_num_vsi);
2001 case ICE_AQC_CAPS_DCB:
2002 caps->dcb = (number == 1);
2003 caps->active_tc_bitmap = logical_id;
2004 caps->maxtc = phys_id;
2005 ice_debug(hw, ICE_DBG_INIT,
2006 "%s: DCB = %d\n", prefix, caps->dcb);
2007 ice_debug(hw, ICE_DBG_INIT,
2008 "%s: active TC bitmap = %d\n", prefix,
2009 caps->active_tc_bitmap);
2010 ice_debug(hw, ICE_DBG_INIT,
2011 "%s: TC max = %d\n", prefix, caps->maxtc);
2013 case ICE_AQC_CAPS_RSS:
2014 caps->rss_table_size = number;
2015 caps->rss_table_entry_width = logical_id;
2016 ice_debug(hw, ICE_DBG_INIT,
2017 "%s: RSS table size = %d\n", prefix,
2018 caps->rss_table_size);
2019 ice_debug(hw, ICE_DBG_INIT,
2020 "%s: RSS table width = %d\n", prefix,
2021 caps->rss_table_entry_width);
2023 case ICE_AQC_CAPS_RXQS:
2024 caps->num_rxq = number;
2025 caps->rxq_first_id = phys_id;
2026 ice_debug(hw, ICE_DBG_INIT,
2027 "%s: num Rx queues = %d\n", prefix,
2029 ice_debug(hw, ICE_DBG_INIT,
2030 "%s: Rx first queue ID = %d\n", prefix,
2031 caps->rxq_first_id);
2033 case ICE_AQC_CAPS_TXQS:
2034 caps->num_txq = number;
2035 caps->txq_first_id = phys_id;
2036 ice_debug(hw, ICE_DBG_INIT,
2037 "%s: num Tx queues = %d\n", prefix,
2039 ice_debug(hw, ICE_DBG_INIT,
2040 "%s: Tx first queue ID = %d\n", prefix,
2041 caps->txq_first_id);
2043 case ICE_AQC_CAPS_MSIX:
2044 caps->num_msix_vectors = number;
2045 caps->msix_vector_first_id = phys_id;
2046 ice_debug(hw, ICE_DBG_INIT,
2047 "%s: MSIX vector count = %d\n", prefix,
2048 caps->num_msix_vectors);
2049 ice_debug(hw, ICE_DBG_INIT,
2050 "%s: MSIX first vector index = %d\n", prefix,
2051 caps->msix_vector_first_id);
2053 case ICE_AQC_CAPS_FD:
2058 dev_p->num_flow_director_fltr = number;
2059 ice_debug(hw, ICE_DBG_INIT,
2060 "%s: num FD filters = %d\n", prefix,
2061 dev_p->num_flow_director_fltr);
2064 reg_val = rd32(hw, GLQF_FD_SIZE);
2065 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2066 GLQF_FD_SIZE_FD_GSIZE_S;
2067 func_p->fd_fltr_guar =
2068 ice_get_num_per_func(hw, val);
2069 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2070 GLQF_FD_SIZE_FD_BSIZE_S;
2071 func_p->fd_fltr_best_effort = val;
2072 ice_debug(hw, ICE_DBG_INIT,
2073 "%s: num guaranteed FD filters = %d\n",
2074 prefix, func_p->fd_fltr_guar);
2075 ice_debug(hw, ICE_DBG_INIT,
2076 "%s: num best effort FD filters = %d\n",
2077 prefix, func_p->fd_fltr_best_effort);
2081 case ICE_AQC_CAPS_MAX_MTU:
2082 caps->max_mtu = number;
2083 ice_debug(hw, ICE_DBG_INIT, "%s: max MTU = %d\n",
2084 prefix, caps->max_mtu);
2087 ice_debug(hw, ICE_DBG_INIT,
2088 "%s: unknown capability[%d]: 0x%x\n", prefix,
2094 /* Re-calculate capabilities that are dependent on the number of
2095 * physical ports; i.e. some features are not supported or function
2096 * differently on devices with more than 4 ports.
2098 if (caps && (ice_hweight32(caps->valid_functions) > 4)) {
2099 /* Max 4 TCs per port */
2101 ice_debug(hw, ICE_DBG_INIT,
2102 "%s: TC max = %d (based on #ports)\n", prefix,
2108 * ice_aq_discover_caps - query function/device capabilities
2109 * @hw: pointer to the HW struct
2110 * @buf: a virtual buffer to hold the capabilities
2111 * @buf_size: Size of the virtual buffer
2112 * @cap_count: cap count needed if AQ err==ENOMEM
2113 * @opc: capabilities type to discover - pass in the command opcode
2114 * @cd: pointer to command details structure or NULL
2116 * Get the function(0x000a)/device(0x000b) capabilities description from
2119 static enum ice_status
2120 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2121 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2123 struct ice_aqc_list_caps *cmd;
2124 struct ice_aq_desc desc;
2125 enum ice_status status;
2127 cmd = &desc.params.get_cap;
2129 if (opc != ice_aqc_opc_list_func_caps &&
2130 opc != ice_aqc_opc_list_dev_caps)
2131 return ICE_ERR_PARAM;
2133 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2135 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2137 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
2138 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
2139 *cap_count = LE32_TO_CPU(cmd->count);
2144 * ice_discover_caps - get info about the HW
2145 * @hw: pointer to the hardware structure
2146 * @opc: capabilities type to discover - pass in the command opcode
2148 static enum ice_status
2149 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
2151 enum ice_status status;
2156 /* The driver doesn't know how many capabilities the device will return
2157 * so the buffer size required isn't known ahead of time. The driver
2158 * starts with cbuf_len and if this turns out to be insufficient, the
2159 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2160 * The driver then allocates the buffer based on the count and retries
2161 * the operation. So it follows that the retry count is 2.
2163 #define ICE_GET_CAP_BUF_COUNT 40
2164 #define ICE_GET_CAP_RETRY_COUNT 2
2166 cap_count = ICE_GET_CAP_BUF_COUNT;
2167 retries = ICE_GET_CAP_RETRY_COUNT;
2172 cbuf_len = (u16)(cap_count *
2173 sizeof(struct ice_aqc_list_caps_elem));
2174 cbuf = ice_malloc(hw, cbuf_len);
2176 return ICE_ERR_NO_MEMORY;
2178 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2182 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2185 /* If ENOMEM is returned, try again with bigger buffer */
2186 } while (--retries);
2192 * ice_get_caps - get info about the HW
2193 * @hw: pointer to the hardware structure
2195 enum ice_status ice_get_caps(struct ice_hw *hw)
2197 enum ice_status status;
2199 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2201 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2207 * ice_aq_manage_mac_write - manage MAC address write command
2208 * @hw: pointer to the HW struct
2209 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2210 * @flags: flags to control write behavior
2211 * @cd: pointer to command details structure or NULL
2213 * This function is used to write MAC address to the NVM (0x0108).
2216 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2217 struct ice_sq_cd *cd)
2219 struct ice_aqc_manage_mac_write *cmd;
2220 struct ice_aq_desc desc;
2222 cmd = &desc.params.mac_write;
2223 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2228 /* Prep values for flags, sah, sal */
2229 cmd->sah = HTONS(*((const u16 *)mac_addr));
2230 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
2232 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2236 * ice_aq_clear_pxe_mode
2237 * @hw: pointer to the HW struct
2239 * Tell the firmware that the driver is taking over from PXE (0x0110).
2241 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2243 struct ice_aq_desc desc;
2245 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2246 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2248 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2252 * ice_clear_pxe_mode - clear pxe operations mode
2253 * @hw: pointer to the HW struct
2255 * Make sure all PXE mode settings are cleared, including things
2256 * like descriptor fetch/write-back mode.
2258 void ice_clear_pxe_mode(struct ice_hw *hw)
2260 if (ice_check_sq_alive(hw, &hw->adminq))
2261 ice_aq_clear_pxe_mode(hw);
2266 * ice_get_link_speed_based_on_phy_type - returns link speed
2267 * @phy_type_low: lower part of phy_type
2268 * @phy_type_high: higher part of phy_type
2270 * This helper function will convert an entry in PHY type structure
2271 * [phy_type_low, phy_type_high] to its corresponding link speed.
2272 * Note: In the structure of [phy_type_low, phy_type_high], there should
2273 * be one bit set, as this function will convert one PHY type to its
2275 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2276 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2279 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2281 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2282 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2284 switch (phy_type_low) {
2285 case ICE_PHY_TYPE_LOW_100BASE_TX:
2286 case ICE_PHY_TYPE_LOW_100M_SGMII:
2287 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2289 case ICE_PHY_TYPE_LOW_1000BASE_T:
2290 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2291 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2292 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2293 case ICE_PHY_TYPE_LOW_1G_SGMII:
2294 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2296 case ICE_PHY_TYPE_LOW_2500BASE_T:
2297 case ICE_PHY_TYPE_LOW_2500BASE_X:
2298 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2299 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2301 case ICE_PHY_TYPE_LOW_5GBASE_T:
2302 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2303 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2305 case ICE_PHY_TYPE_LOW_10GBASE_T:
2306 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2307 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2308 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2309 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2310 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2311 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2312 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2314 case ICE_PHY_TYPE_LOW_25GBASE_T:
2315 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2316 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2317 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2318 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2319 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2320 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2321 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2322 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2323 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2324 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2325 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2327 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2328 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2329 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2330 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2331 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2332 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2333 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2335 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2336 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2337 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2338 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2339 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2340 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2341 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2342 case ICE_PHY_TYPE_LOW_50G_AUI2:
2343 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2344 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2345 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2346 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2347 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2348 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2349 case ICE_PHY_TYPE_LOW_50G_AUI1:
2350 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2352 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2353 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2354 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2355 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2356 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2357 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2358 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2359 case ICE_PHY_TYPE_LOW_100G_AUI4:
2360 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2361 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2362 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2363 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2364 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2365 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2368 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2372 switch (phy_type_high) {
2373 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2374 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2375 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2376 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2377 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2378 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2381 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2385 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2386 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2387 return ICE_AQ_LINK_SPEED_UNKNOWN;
2388 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2389 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2390 return ICE_AQ_LINK_SPEED_UNKNOWN;
2391 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2392 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2393 return speed_phy_type_low;
2395 return speed_phy_type_high;
2399 * ice_update_phy_type
2400 * @phy_type_low: pointer to the lower part of phy_type
2401 * @phy_type_high: pointer to the higher part of phy_type
2402 * @link_speeds_bitmap: targeted link speeds bitmap
2404 * Note: For the link_speeds_bitmap structure, you can check it at
2405 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2406 * link_speeds_bitmap include multiple speeds.
2408 * Each entry in this [phy_type_low, phy_type_high] structure will
2409 * present a certain link speed. This helper function will turn on bits
2410 * in [phy_type_low, phy_type_high] structure based on the value of
2411 * link_speeds_bitmap input parameter.
2414 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2415 u16 link_speeds_bitmap)
2422 /* We first check with low part of phy_type */
2423 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2424 pt_low = BIT_ULL(index);
2425 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2427 if (link_speeds_bitmap & speed)
2428 *phy_type_low |= BIT_ULL(index);
2431 /* We then check with high part of phy_type */
2432 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2433 pt_high = BIT_ULL(index);
2434 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2436 if (link_speeds_bitmap & speed)
2437 *phy_type_high |= BIT_ULL(index);
2442 * ice_aq_set_phy_cfg
2443 * @hw: pointer to the HW struct
2444 * @pi: port info structure of the interested logical port
2445 * @cfg: structure with PHY configuration data to be set
2446 * @cd: pointer to command details structure or NULL
2448 * Set the various PHY configuration parameters supported on the Port.
2449 * One or more of the Set PHY config parameters may be ignored in an MFP
2450 * mode as the PF may not have the privilege to set some of the PHY Config
2451 * parameters. This status will be indicated by the command response (0x0601).
2454 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2455 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2457 struct ice_aq_desc desc;
2458 enum ice_status status;
2461 return ICE_ERR_PARAM;
2463 /* Ensure that only valid bits of cfg->caps can be turned on. */
2464 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2465 ice_debug(hw, ICE_DBG_PHY,
2466 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2469 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2472 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2473 desc.params.set_phy.lport_num = pi->lport;
2474 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2476 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2477 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2478 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2479 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2480 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2481 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n",
2482 cfg->low_power_ctrl);
2483 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2484 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2485 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2487 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2490 pi->phy.curr_user_phy_cfg = *cfg;
2496 * ice_update_link_info - update status of the HW network link
2497 * @pi: port info structure of the interested logical port
2499 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2501 struct ice_link_status *li;
2502 enum ice_status status;
2505 return ICE_ERR_PARAM;
2507 li = &pi->phy.link_info;
2509 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2513 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2514 struct ice_aqc_get_phy_caps_data *pcaps;
2518 pcaps = (struct ice_aqc_get_phy_caps_data *)
2519 ice_malloc(hw, sizeof(*pcaps));
2521 return ICE_ERR_NO_MEMORY;
2523 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2525 if (status == ICE_SUCCESS)
2526 ice_memcpy(li->module_type, &pcaps->module_type,
2527 sizeof(li->module_type),
2528 ICE_NONDMA_TO_NONDMA);
2530 ice_free(hw, pcaps);
2537 * ice_cache_phy_user_req
2538 * @pi: port information structure
2539 * @cache_data: PHY logging data
2540 * @cache_mode: PHY logging mode
2542 * Log the user request on (FC, FEC, SPEED) for later user.
2545 ice_cache_phy_user_req(struct ice_port_info *pi,
2546 struct ice_phy_cache_mode_data cache_data,
2547 enum ice_phy_cache_mode cache_mode)
2552 switch (cache_mode) {
2554 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2556 case ICE_SPEED_MODE:
2557 pi->phy.curr_user_speed_req =
2558 cache_data.data.curr_user_speed_req;
2561 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2570 * @pi: port information structure
2571 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2572 * @ena_auto_link_update: enable automatic link update
2574 * Set the requested flow control mode.
2577 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2579 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2580 struct ice_phy_cache_mode_data cache_data;
2581 struct ice_aqc_get_phy_caps_data *pcaps;
2582 enum ice_status status;
2583 u8 pause_mask = 0x0;
2587 return ICE_ERR_PARAM;
2589 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2591 /* Cache user FC request */
2592 cache_data.data.curr_user_fc_req = pi->fc.req_mode;
2593 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2595 switch (pi->fc.req_mode) {
2597 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2598 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2600 case ICE_FC_RX_PAUSE:
2601 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2603 case ICE_FC_TX_PAUSE:
2604 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2610 pcaps = (struct ice_aqc_get_phy_caps_data *)
2611 ice_malloc(hw, sizeof(*pcaps));
2613 return ICE_ERR_NO_MEMORY;
2615 /* Get the current PHY config */
2616 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2619 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2623 /* clear the old pause settings */
2624 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2625 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2627 /* set the new capabilities */
2628 cfg.caps |= pause_mask;
2630 /* If the capabilities have changed, then set the new config */
2631 if (cfg.caps != pcaps->caps) {
2632 int retry_count, retry_max = 10;
2634 /* Auto restart link so settings take effect */
2635 if (ena_auto_link_update)
2636 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2637 /* Copy over all the old settings */
2638 cfg.phy_type_high = pcaps->phy_type_high;
2639 cfg.phy_type_low = pcaps->phy_type_low;
2640 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2641 cfg.eee_cap = pcaps->eee_cap;
2642 cfg.eeer_value = pcaps->eeer_value;
2643 cfg.link_fec_opt = pcaps->link_fec_options;
2645 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2647 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2651 /* Update the link info
2652 * It sometimes takes a really long time for link to
2653 * come back from the atomic reset. Thus, we wait a
2656 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2657 status = ice_update_link_info(pi);
2659 if (status == ICE_SUCCESS)
2662 ice_msec_delay(100, true);
2666 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2670 ice_free(hw, pcaps);
2675 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2676 * @caps: PHY ability structure to copy date from
2677 * @cfg: PHY configuration structure to copy data to
2679 * Helper function to copy AQC PHY get ability data to PHY set configuration
2683 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2684 struct ice_aqc_set_phy_cfg_data *cfg)
2689 cfg->phy_type_low = caps->phy_type_low;
2690 cfg->phy_type_high = caps->phy_type_high;
2691 cfg->caps = caps->caps;
2692 cfg->low_power_ctrl = caps->low_power_ctrl;
2693 cfg->eee_cap = caps->eee_cap;
2694 cfg->eeer_value = caps->eeer_value;
2695 cfg->link_fec_opt = caps->link_fec_options;
2699 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2700 * @cfg: PHY configuration data to set FEC mode
2701 * @fec: FEC mode to configure
2703 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2704 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2705 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2708 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2712 /* Clear RS bits, and AND BASE-R ability
2713 * bits and OR request bits.
2715 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2716 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2717 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2718 ICE_AQC_PHY_FEC_25G_KR_REQ;
2721 /* Clear BASE-R bits, and AND RS ability
2722 * bits and OR request bits.
2724 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2725 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2726 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2729 /* Clear all FEC option bits. */
2730 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2733 /* AND auto FEC bit, and all caps bits. */
2734 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2740 * ice_get_link_status - get status of the HW network link
2741 * @pi: port information structure
2742 * @link_up: pointer to bool (true/false = linkup/linkdown)
2744 * Variable link_up is true if link is up, false if link is down.
2745 * The variable link_up is invalid if status is non zero. As a
2746 * result of this call, link status reporting becomes enabled
2748 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2750 struct ice_phy_info *phy_info;
2751 enum ice_status status = ICE_SUCCESS;
2753 if (!pi || !link_up)
2754 return ICE_ERR_PARAM;
2756 phy_info = &pi->phy;
2758 if (phy_info->get_link_info) {
2759 status = ice_update_link_info(pi);
2762 ice_debug(pi->hw, ICE_DBG_LINK,
2763 "get link status error, status = %d\n",
2767 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2773 * ice_aq_set_link_restart_an
2774 * @pi: pointer to the port information structure
2775 * @ena_link: if true: enable link, if false: disable link
2776 * @cd: pointer to command details structure or NULL
2778 * Sets up the link and restarts the Auto-Negotiation over the link.
2781 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2782 struct ice_sq_cd *cd)
2784 struct ice_aqc_restart_an *cmd;
2785 struct ice_aq_desc desc;
2787 cmd = &desc.params.restart_an;
2789 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2791 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2792 cmd->lport_num = pi->lport;
2794 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2796 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2798 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2802 * ice_aq_set_event_mask
2803 * @hw: pointer to the HW struct
2804 * @port_num: port number of the physical function
2805 * @mask: event mask to be set
2806 * @cd: pointer to command details structure or NULL
2808 * Set event mask (0x0613)
2811 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2812 struct ice_sq_cd *cd)
2814 struct ice_aqc_set_event_mask *cmd;
2815 struct ice_aq_desc desc;
2817 cmd = &desc.params.set_event_mask;
2819 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2821 cmd->lport_num = port_num;
2823 cmd->event_mask = CPU_TO_LE16(mask);
2824 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2828 * ice_aq_set_mac_loopback
2829 * @hw: pointer to the HW struct
2830 * @ena_lpbk: Enable or Disable loopback
2831 * @cd: pointer to command details structure or NULL
2833 * Enable/disable loopback on a given port
2836 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2838 struct ice_aqc_set_mac_lb *cmd;
2839 struct ice_aq_desc desc;
2841 cmd = &desc.params.set_mac_lb;
2843 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2845 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2847 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2852 * ice_aq_set_port_id_led
2853 * @pi: pointer to the port information
2854 * @is_orig_mode: is this LED set to original mode (by the net-list)
2855 * @cd: pointer to command details structure or NULL
2857 * Set LED value for the given port (0x06e9)
2860 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2861 struct ice_sq_cd *cd)
2863 struct ice_aqc_set_port_id_led *cmd;
2864 struct ice_hw *hw = pi->hw;
2865 struct ice_aq_desc desc;
2867 cmd = &desc.params.set_port_id_led;
2869 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2873 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2875 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2877 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2881 * __ice_aq_get_set_rss_lut
2882 * @hw: pointer to the hardware structure
2883 * @vsi_id: VSI FW index
2884 * @lut_type: LUT table type
2885 * @lut: pointer to the LUT buffer provided by the caller
2886 * @lut_size: size of the LUT buffer
2887 * @glob_lut_idx: global LUT index
2888 * @set: set true to set the table, false to get the table
2890 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2892 static enum ice_status
2893 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2894 u16 lut_size, u8 glob_lut_idx, bool set)
2896 struct ice_aqc_get_set_rss_lut *cmd_resp;
2897 struct ice_aq_desc desc;
2898 enum ice_status status;
2901 cmd_resp = &desc.params.get_set_rss_lut;
2904 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2905 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2907 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2910 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2911 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2912 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2913 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2916 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2917 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2918 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2919 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2920 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2923 status = ICE_ERR_PARAM;
2924 goto ice_aq_get_set_rss_lut_exit;
2927 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2928 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2929 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2932 goto ice_aq_get_set_rss_lut_send;
2933 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2935 goto ice_aq_get_set_rss_lut_send;
2937 goto ice_aq_get_set_rss_lut_send;
2940 /* LUT size is only valid for Global and PF table types */
2942 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2943 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
2944 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2945 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2947 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
2948 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2949 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2950 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2952 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
2953 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2954 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
2955 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2956 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2961 status = ICE_ERR_PARAM;
2962 goto ice_aq_get_set_rss_lut_exit;
2965 ice_aq_get_set_rss_lut_send:
2966 cmd_resp->flags = CPU_TO_LE16(flags);
2967 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
2969 ice_aq_get_set_rss_lut_exit:
2974 * ice_aq_get_rss_lut
2975 * @hw: pointer to the hardware structure
2976 * @vsi_handle: software VSI handle
2977 * @lut_type: LUT table type
2978 * @lut: pointer to the LUT buffer provided by the caller
2979 * @lut_size: size of the LUT buffer
2981 * get the RSS lookup table, PF or VSI type
2984 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2985 u8 *lut, u16 lut_size)
2987 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2988 return ICE_ERR_PARAM;
2990 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2991 lut_type, lut, lut_size, 0, false);
2995 * ice_aq_set_rss_lut
2996 * @hw: pointer to the hardware structure
2997 * @vsi_handle: software VSI handle
2998 * @lut_type: LUT table type
2999 * @lut: pointer to the LUT buffer provided by the caller
3000 * @lut_size: size of the LUT buffer
3002 * set the RSS lookup table, PF or VSI type
3005 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3006 u8 *lut, u16 lut_size)
3008 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3009 return ICE_ERR_PARAM;
3011 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3012 lut_type, lut, lut_size, 0, true);
3016 * __ice_aq_get_set_rss_key
3017 * @hw: pointer to the HW struct
3018 * @vsi_id: VSI FW index
3019 * @key: pointer to key info struct
3020 * @set: set true to set the key, false to get the key
3022 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3025 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3026 struct ice_aqc_get_set_rss_keys *key,
3029 struct ice_aqc_get_set_rss_key *cmd_resp;
3030 u16 key_size = sizeof(*key);
3031 struct ice_aq_desc desc;
3033 cmd_resp = &desc.params.get_set_rss_key;
3036 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3037 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3039 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3042 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3043 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3044 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3045 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3047 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3051 * ice_aq_get_rss_key
3052 * @hw: pointer to the HW struct
3053 * @vsi_handle: software VSI handle
3054 * @key: pointer to key info struct
3056 * get the RSS key per VSI
3059 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3060 struct ice_aqc_get_set_rss_keys *key)
3062 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3063 return ICE_ERR_PARAM;
3065 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3070 * ice_aq_set_rss_key
3071 * @hw: pointer to the HW struct
3072 * @vsi_handle: software VSI handle
3073 * @keys: pointer to key info struct
3075 * set the RSS key per VSI
3078 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3079 struct ice_aqc_get_set_rss_keys *keys)
3081 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3082 return ICE_ERR_PARAM;
3084 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3089 * ice_aq_add_lan_txq
3090 * @hw: pointer to the hardware structure
3091 * @num_qgrps: Number of added queue groups
3092 * @qg_list: list of queue groups to be added
3093 * @buf_size: size of buffer for indirect command
3094 * @cd: pointer to command details structure or NULL
3096 * Add Tx LAN queue (0x0C30)
3099 * Prior to calling add Tx LAN queue:
3100 * Initialize the following as part of the Tx queue context:
3101 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3102 * Cache profile and Packet shaper profile.
3104 * After add Tx LAN queue AQ command is completed:
3105 * Interrupts should be associated with specific queues,
3106 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3110 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3111 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3112 struct ice_sq_cd *cd)
3114 u16 i, sum_header_size, sum_q_size = 0;
3115 struct ice_aqc_add_tx_qgrp *list;
3116 struct ice_aqc_add_txqs *cmd;
3117 struct ice_aq_desc desc;
3119 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3121 cmd = &desc.params.add_txqs;
3123 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3126 return ICE_ERR_PARAM;
3128 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3129 return ICE_ERR_PARAM;
3131 sum_header_size = num_qgrps *
3132 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3135 for (i = 0; i < num_qgrps; i++) {
3136 struct ice_aqc_add_txqs_perq *q = list->txqs;
3138 sum_q_size += list->num_txqs * sizeof(*q);
3139 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3142 if (buf_size != (sum_header_size + sum_q_size))
3143 return ICE_ERR_PARAM;
3145 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3147 cmd->num_qgrps = num_qgrps;
3149 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3153 * ice_aq_dis_lan_txq
3154 * @hw: pointer to the hardware structure
3155 * @num_qgrps: number of groups in the list
3156 * @qg_list: the list of groups to disable
3157 * @buf_size: the total size of the qg_list buffer in bytes
3158 * @rst_src: if called due to reset, specifies the reset source
3159 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3160 * @cd: pointer to command details structure or NULL
3162 * Disable LAN Tx queue (0x0C31)
3164 static enum ice_status
3165 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3166 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3167 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3168 struct ice_sq_cd *cd)
3170 struct ice_aqc_dis_txqs *cmd;
3171 struct ice_aq_desc desc;
3172 enum ice_status status;
3175 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3176 cmd = &desc.params.dis_txqs;
3177 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3179 /* qg_list can be NULL only in VM/VF reset flow */
3180 if (!qg_list && !rst_src)
3181 return ICE_ERR_PARAM;
3183 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3184 return ICE_ERR_PARAM;
3186 cmd->num_entries = num_qgrps;
3188 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3189 ICE_AQC_Q_DIS_TIMEOUT_M);
3193 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3194 cmd->vmvf_and_timeout |=
3195 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3202 /* flush pipe on time out */
3203 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3204 /* If no queue group info, we are in a reset flow. Issue the AQ */
3208 /* set RD bit to indicate that command buffer is provided by the driver
3209 * and it needs to be read by the firmware
3211 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3213 for (i = 0; i < num_qgrps; ++i) {
3214 /* Calculate the size taken up by the queue IDs in this group */
3215 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3217 /* Add the size of the group header */
3218 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3220 /* If the num of queues is even, add 2 bytes of padding */
3221 if ((qg_list[i].num_qs % 2) == 0)
3226 return ICE_ERR_PARAM;
3229 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3232 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3233 vmvf_num, hw->adminq.sq_last_status);
3235 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3236 LE16_TO_CPU(qg_list[0].q_id[0]),
3237 hw->adminq.sq_last_status);
3243 /* End of FW Admin Queue command wrappers */
3246 * ice_write_byte - write a byte to a packed context structure
3247 * @src_ctx: the context structure to read from
3248 * @dest_ctx: the context to be written to
3249 * @ce_info: a description of the struct to be filled
3252 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3254 u8 src_byte, dest_byte, mask;
3258 /* copy from the next struct field */
3259 from = src_ctx + ce_info->offset;
3261 /* prepare the bits and mask */
3262 shift_width = ce_info->lsb % 8;
3263 mask = (u8)(BIT(ce_info->width) - 1);
3268 /* shift to correct alignment */
3269 mask <<= shift_width;
3270 src_byte <<= shift_width;
3272 /* get the current bits from the target bit string */
3273 dest = dest_ctx + (ce_info->lsb / 8);
3275 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3277 dest_byte &= ~mask; /* get the bits not changing */
3278 dest_byte |= src_byte; /* add in the new bits */
3280 /* put it all back */
3281 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3285 * ice_write_word - write a word to a packed context structure
3286 * @src_ctx: the context structure to read from
3287 * @dest_ctx: the context to be written to
3288 * @ce_info: a description of the struct to be filled
3291 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3298 /* copy from the next struct field */
3299 from = src_ctx + ce_info->offset;
3301 /* prepare the bits and mask */
3302 shift_width = ce_info->lsb % 8;
3303 mask = BIT(ce_info->width) - 1;
3305 /* don't swizzle the bits until after the mask because the mask bits
3306 * will be in a different bit position on big endian machines
3308 src_word = *(u16 *)from;
3311 /* shift to correct alignment */
3312 mask <<= shift_width;
3313 src_word <<= shift_width;
3315 /* get the current bits from the target bit string */
3316 dest = dest_ctx + (ce_info->lsb / 8);
3318 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3320 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3321 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3323 /* put it all back */
3324 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3328 * ice_write_dword - write a dword to a packed context structure
3329 * @src_ctx: the context structure to read from
3330 * @dest_ctx: the context to be written to
3331 * @ce_info: a description of the struct to be filled
3334 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3336 u32 src_dword, mask;
3341 /* copy from the next struct field */
3342 from = src_ctx + ce_info->offset;
3344 /* prepare the bits and mask */
3345 shift_width = ce_info->lsb % 8;
3347 /* if the field width is exactly 32 on an x86 machine, then the shift
3348 * operation will not work because the SHL instructions count is masked
3349 * to 5 bits so the shift will do nothing
3351 if (ce_info->width < 32)
3352 mask = BIT(ce_info->width) - 1;
3356 /* don't swizzle the bits until after the mask because the mask bits
3357 * will be in a different bit position on big endian machines
3359 src_dword = *(u32 *)from;
3362 /* shift to correct alignment */
3363 mask <<= shift_width;
3364 src_dword <<= shift_width;
3366 /* get the current bits from the target bit string */
3367 dest = dest_ctx + (ce_info->lsb / 8);
3369 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3371 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3372 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3374 /* put it all back */
3375 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3379 * ice_write_qword - write a qword to a packed context structure
3380 * @src_ctx: the context structure to read from
3381 * @dest_ctx: the context to be written to
3382 * @ce_info: a description of the struct to be filled
3385 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3387 u64 src_qword, mask;
3392 /* copy from the next struct field */
3393 from = src_ctx + ce_info->offset;
3395 /* prepare the bits and mask */
3396 shift_width = ce_info->lsb % 8;
3398 /* if the field width is exactly 64 on an x86 machine, then the shift
3399 * operation will not work because the SHL instructions count is masked
3400 * to 6 bits so the shift will do nothing
3402 if (ce_info->width < 64)
3403 mask = BIT_ULL(ce_info->width) - 1;
3407 /* don't swizzle the bits until after the mask because the mask bits
3408 * will be in a different bit position on big endian machines
3410 src_qword = *(u64 *)from;
3413 /* shift to correct alignment */
3414 mask <<= shift_width;
3415 src_qword <<= shift_width;
3417 /* get the current bits from the target bit string */
3418 dest = dest_ctx + (ce_info->lsb / 8);
3420 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3422 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3423 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3425 /* put it all back */
3426 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3430 * ice_set_ctx - set context bits in packed structure
3431 * @src_ctx: pointer to a generic non-packed context structure
3432 * @dest_ctx: pointer to memory for the packed structure
3433 * @ce_info: a description of the structure to be transformed
3436 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3440 for (f = 0; ce_info[f].width; f++) {
3441 /* We have to deal with each element of the FW response
3442 * using the correct size so that we are correct regardless
3443 * of the endianness of the machine.
3445 switch (ce_info[f].size_of) {
3447 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3450 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3453 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3456 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3459 return ICE_ERR_INVAL_SIZE;
3470 * ice_read_byte - read context byte into struct
3471 * @src_ctx: the context structure to read from
3472 * @dest_ctx: the context to be written to
3473 * @ce_info: a description of the struct to be filled
3476 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3482 /* prepare the bits and mask */
3483 shift_width = ce_info->lsb % 8;
3484 mask = (u8)(BIT(ce_info->width) - 1);
3486 /* shift to correct alignment */
3487 mask <<= shift_width;
3489 /* get the current bits from the src bit string */
3490 src = src_ctx + (ce_info->lsb / 8);
3492 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3494 dest_byte &= ~(mask);
3496 dest_byte >>= shift_width;
3498 /* get the address from the struct field */
3499 target = dest_ctx + ce_info->offset;
3501 /* put it back in the struct */
3502 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3506 * ice_read_word - read context word into struct
3507 * @src_ctx: the context structure to read from
3508 * @dest_ctx: the context to be written to
3509 * @ce_info: a description of the struct to be filled
3512 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3514 u16 dest_word, mask;
3519 /* prepare the bits and mask */
3520 shift_width = ce_info->lsb % 8;
3521 mask = BIT(ce_info->width) - 1;
3523 /* shift to correct alignment */
3524 mask <<= shift_width;
3526 /* get the current bits from the src bit string */
3527 src = src_ctx + (ce_info->lsb / 8);
3529 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3531 /* the data in the memory is stored as little endian so mask it
3534 src_word &= ~(CPU_TO_LE16(mask));
3536 /* get the data back into host order before shifting */
3537 dest_word = LE16_TO_CPU(src_word);
3539 dest_word >>= shift_width;
3541 /* get the address from the struct field */
3542 target = dest_ctx + ce_info->offset;
3544 /* put it back in the struct */
3545 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3549 * ice_read_dword - read context dword into struct
3550 * @src_ctx: the context structure to read from
3551 * @dest_ctx: the context to be written to
3552 * @ce_info: a description of the struct to be filled
3555 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3557 u32 dest_dword, mask;
3562 /* prepare the bits and mask */
3563 shift_width = ce_info->lsb % 8;
3565 /* if the field width is exactly 32 on an x86 machine, then the shift
3566 * operation will not work because the SHL instructions count is masked
3567 * to 5 bits so the shift will do nothing
3569 if (ce_info->width < 32)
3570 mask = BIT(ce_info->width) - 1;
3574 /* shift to correct alignment */
3575 mask <<= shift_width;
3577 /* get the current bits from the src bit string */
3578 src = src_ctx + (ce_info->lsb / 8);
3580 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3582 /* the data in the memory is stored as little endian so mask it
3585 src_dword &= ~(CPU_TO_LE32(mask));
3587 /* get the data back into host order before shifting */
3588 dest_dword = LE32_TO_CPU(src_dword);
3590 dest_dword >>= shift_width;
3592 /* get the address from the struct field */
3593 target = dest_ctx + ce_info->offset;
3595 /* put it back in the struct */
3596 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3600 * ice_read_qword - read context qword into struct
3601 * @src_ctx: the context structure to read from
3602 * @dest_ctx: the context to be written to
3603 * @ce_info: a description of the struct to be filled
3606 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3608 u64 dest_qword, mask;
3613 /* prepare the bits and mask */
3614 shift_width = ce_info->lsb % 8;
3616 /* if the field width is exactly 64 on an x86 machine, then the shift
3617 * operation will not work because the SHL instructions count is masked
3618 * to 6 bits so the shift will do nothing
3620 if (ce_info->width < 64)
3621 mask = BIT_ULL(ce_info->width) - 1;
3625 /* shift to correct alignment */
3626 mask <<= shift_width;
3628 /* get the current bits from the src bit string */
3629 src = src_ctx + (ce_info->lsb / 8);
3631 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3633 /* the data in the memory is stored as little endian so mask it
3636 src_qword &= ~(CPU_TO_LE64(mask));
3638 /* get the data back into host order before shifting */
3639 dest_qword = LE64_TO_CPU(src_qword);
3641 dest_qword >>= shift_width;
3643 /* get the address from the struct field */
3644 target = dest_ctx + ce_info->offset;
3646 /* put it back in the struct */
3647 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3651 * ice_get_ctx - extract context bits from a packed structure
3652 * @src_ctx: pointer to a generic packed context structure
3653 * @dest_ctx: pointer to a generic non-packed context structure
3654 * @ce_info: a description of the structure to be read from
3657 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3661 for (f = 0; ce_info[f].width; f++) {
3662 switch (ce_info[f].size_of) {
3664 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3667 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3670 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3673 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3676 /* nothing to do, just keep going */
3685 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3686 * @hw: pointer to the HW struct
3687 * @vsi_handle: software VSI handle
3689 * @q_handle: software queue handle
3692 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3694 struct ice_vsi_ctx *vsi;
3695 struct ice_q_ctx *q_ctx;
3697 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3700 if (q_handle >= vsi->num_lan_q_entries[tc])
3702 if (!vsi->lan_q_ctx[tc])
3704 q_ctx = vsi->lan_q_ctx[tc];
3705 return &q_ctx[q_handle];
3710 * @pi: port information structure
3711 * @vsi_handle: software VSI handle
3713 * @q_handle: software queue handle
3714 * @num_qgrps: Number of added queue groups
3715 * @buf: list of queue groups to be added
3716 * @buf_size: size of buffer for indirect command
3717 * @cd: pointer to command details structure or NULL
3719 * This function adds one LAN queue
3722 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3723 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3724 struct ice_sq_cd *cd)
3726 struct ice_aqc_txsched_elem_data node = { 0 };
3727 struct ice_sched_node *parent;
3728 struct ice_q_ctx *q_ctx;
3729 enum ice_status status;
3732 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3735 if (num_qgrps > 1 || buf->num_txqs > 1)
3736 return ICE_ERR_MAX_LIMIT;
3740 if (!ice_is_vsi_valid(hw, vsi_handle))
3741 return ICE_ERR_PARAM;
3743 ice_acquire_lock(&pi->sched_lock);
3745 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3747 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3749 status = ICE_ERR_PARAM;
3753 /* find a parent node */
3754 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3755 ICE_SCHED_NODE_OWNER_LAN);
3757 status = ICE_ERR_PARAM;
3761 buf->parent_teid = parent->info.node_teid;
3762 node.parent_teid = parent->info.node_teid;
3763 /* Mark that the values in the "generic" section as valid. The default
3764 * value in the "generic" section is zero. This means that :
3765 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3766 * - 0 priority among siblings, indicated by Bit 1-3.
3767 * - WFQ, indicated by Bit 4.
3768 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3770 * - Bit 7 is reserved.
3771 * Without setting the generic section as valid in valid_sections, the
3772 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3774 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3776 /* add the LAN queue */
3777 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3778 if (status != ICE_SUCCESS) {
3779 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3780 LE16_TO_CPU(buf->txqs[0].txq_id),
3781 hw->adminq.sq_last_status);
3785 node.node_teid = buf->txqs[0].q_teid;
3786 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3787 q_ctx->q_handle = q_handle;
3788 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
3790 /* add a leaf node into scheduler tree queue layer */
3791 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3793 status = ice_sched_replay_q_bw(pi, q_ctx);
3796 ice_release_lock(&pi->sched_lock);
3802 * @pi: port information structure
3803 * @vsi_handle: software VSI handle
3805 * @num_queues: number of queues
3806 * @q_handles: pointer to software queue handle array
3807 * @q_ids: pointer to the q_id array
3808 * @q_teids: pointer to queue node teids
3809 * @rst_src: if called due to reset, specifies the reset source
3810 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3811 * @cd: pointer to command details structure or NULL
3813 * This function removes queues and their corresponding nodes in SW DB
3816 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3817 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3818 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3819 struct ice_sq_cd *cd)
3821 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3822 struct ice_aqc_dis_txq_item qg_list;
3823 struct ice_q_ctx *q_ctx;
3826 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3830 /* if queue is disabled already yet the disable queue command
3831 * has to be sent to complete the VF reset, then call
3832 * ice_aq_dis_lan_txq without any queue information
3835 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
3840 ice_acquire_lock(&pi->sched_lock);
3842 for (i = 0; i < num_queues; i++) {
3843 struct ice_sched_node *node;
3845 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3848 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3850 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3854 if (q_ctx->q_handle != q_handles[i]) {
3855 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3856 q_ctx->q_handle, q_handles[i]);
3859 qg_list.parent_teid = node->info.parent_teid;
3861 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
3862 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3863 sizeof(qg_list), rst_src, vmvf_num,
3866 if (status != ICE_SUCCESS)
3868 ice_free_sched_node(pi, node);
3869 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
3871 ice_release_lock(&pi->sched_lock);
3876 * ice_cfg_vsi_qs - configure the new/existing VSI queues
3877 * @pi: port information structure
3878 * @vsi_handle: software VSI handle
3879 * @tc_bitmap: TC bitmap
3880 * @maxqs: max queues array per TC
3881 * @owner: LAN or RDMA
3883 * This function adds/updates the VSI queues per TC.
3885 static enum ice_status
3886 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3887 u16 *maxqs, u8 owner)
3889 enum ice_status status = ICE_SUCCESS;
3892 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3895 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3896 return ICE_ERR_PARAM;
3898 ice_acquire_lock(&pi->sched_lock);
3900 ice_for_each_traffic_class(i) {
3901 /* configuration is possible only if TC node is present */
3902 if (!ice_sched_get_tc_node(pi, i))
3905 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
3906 ice_is_tc_ena(tc_bitmap, i));
3911 ice_release_lock(&pi->sched_lock);
3916 * ice_cfg_vsi_lan - configure VSI LAN queues
3917 * @pi: port information structure
3918 * @vsi_handle: software VSI handle
3919 * @tc_bitmap: TC bitmap
3920 * @max_lanqs: max LAN queues array per TC
3922 * This function adds/updates the VSI LAN queues per TC.
3925 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3928 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
3929 ICE_SCHED_NODE_OWNER_LAN);
3935 * ice_replay_pre_init - replay pre initialization
3936 * @hw: pointer to the HW struct
3938 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
3940 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
3942 struct ice_switch_info *sw = hw->switch_info;
3945 /* Delete old entries from replay filter list head if there is any */
3946 ice_rm_all_sw_replay_rule_info(hw);
3947 /* In start of replay, move entries into replay_rules list, it
3948 * will allow adding rules entries back to filt_rules list,
3949 * which is operational list.
3951 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
3952 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
3953 &sw->recp_list[i].filt_replay_rules);
3954 ice_sched_replay_agg_vsi_preinit(hw);
3956 return ice_sched_replay_tc_node_bw(hw);
3960 * ice_replay_vsi - replay VSI configuration
3961 * @hw: pointer to the HW struct
3962 * @vsi_handle: driver VSI handle
3964 * Restore all VSI configuration after reset. It is required to call this
3965 * function with main VSI first.
3967 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
3969 enum ice_status status;
3971 if (!ice_is_vsi_valid(hw, vsi_handle))
3972 return ICE_ERR_PARAM;
3974 /* Replay pre-initialization if there is any */
3975 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
3976 status = ice_replay_pre_init(hw);
3980 /* Replay per VSI all RSS configurations */
3981 status = ice_replay_rss_cfg(hw, vsi_handle);
3984 /* Replay per VSI all filters */
3985 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
3987 status = ice_replay_vsi_agg(hw, vsi_handle);
3992 * ice_replay_post - post replay configuration cleanup
3993 * @hw: pointer to the HW struct
3995 * Post replay cleanup.
3997 void ice_replay_post(struct ice_hw *hw)
3999 /* Delete old entries from replay filter list head */
4000 ice_rm_all_sw_replay_rule_info(hw);
4001 ice_sched_replay_agg(hw);
4005 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4006 * @hw: ptr to the hardware info
4007 * @reg: offset of 64 bit HW register to read from
4008 * @prev_stat_loaded: bool to specify if previous stats are loaded
4009 * @prev_stat: ptr to previous loaded stat value
4010 * @cur_stat: ptr to current stat value
4013 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4014 u64 *prev_stat, u64 *cur_stat)
4016 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4018 /* device stats are not reset at PFR, they likely will not be zeroed
4019 * when the driver starts. Thus, save the value from the first read
4020 * without adding to the statistic value so that we report stats which
4021 * count up from zero.
4023 if (!prev_stat_loaded) {
4024 *prev_stat = new_data;
4028 /* Calculate the difference between the new and old values, and then
4029 * add it to the software stat value.
4031 if (new_data >= *prev_stat)
4032 *cur_stat += new_data - *prev_stat;
4034 /* to manage the potential roll-over */
4035 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4037 /* Update the previously stored value to prepare for next read */
4038 *prev_stat = new_data;
4042 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4043 * @hw: ptr to the hardware info
4044 * @reg: offset of HW register to read from
4045 * @prev_stat_loaded: bool to specify if previous stats are loaded
4046 * @prev_stat: ptr to previous loaded stat value
4047 * @cur_stat: ptr to current stat value
4050 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4051 u64 *prev_stat, u64 *cur_stat)
4055 new_data = rd32(hw, reg);
4057 /* device stats are not reset at PFR, they likely will not be zeroed
4058 * when the driver starts. Thus, save the value from the first read
4059 * without adding to the statistic value so that we report stats which
4060 * count up from zero.
4062 if (!prev_stat_loaded) {
4063 *prev_stat = new_data;
4067 /* Calculate the difference between the new and old values, and then
4068 * add it to the software stat value.
4070 if (new_data >= *prev_stat)
4071 *cur_stat += new_data - *prev_stat;
4073 /* to manage the potential roll-over */
4074 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4076 /* Update the previously stored value to prepare for next read */
4077 *prev_stat = new_data;
4082 * ice_sched_query_elem - query element information from HW
4083 * @hw: pointer to the HW struct
4084 * @node_teid: node TEID to be queried
4085 * @buf: buffer to element information
4087 * This function queries HW element information
4090 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4091 struct ice_aqc_get_elem *buf)
4093 u16 buf_size, num_elem_ret = 0;
4094 enum ice_status status;
4096 buf_size = sizeof(*buf);
4097 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4098 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4099 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4101 if (status != ICE_SUCCESS || num_elem_ret != 1)
4102 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4107 * ice_is_fw_in_rec_mode
4108 * @hw: pointer to the HW struct
4110 * This function returns true if fw is in recovery mode
4112 bool ice_is_fw_in_rec_mode(struct ice_hw *hw)
4116 /* check the current FW mode */
4117 reg = rd32(hw, GL_MNG_FWSM);
4118 return (reg & GL_MNG_FWSM_FW_MODES_M) > ICE_FW_MODE_DBG;