1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 200
15 * ice_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
18 * This function sets the MAC type of the adapter based on the
19 * vendor ID and device ID stored in the HW structure.
21 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
23 enum ice_status status = ICE_SUCCESS;
25 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
27 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) {
28 switch (hw->device_id) {
30 hw->mac_type = ICE_MAC_GENERIC;
34 status = ICE_ERR_DEVICE_NOT_SUPPORTED;
37 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n",
38 hw->mac_type, status);
44 * ice_clear_pf_cfg - Clear PF configuration
45 * @hw: pointer to the hardware structure
47 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
48 * configuration, flow director filters, etc.).
50 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
52 struct ice_aq_desc desc;
54 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
56 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
60 * ice_aq_manage_mac_read - manage MAC address read command
61 * @hw: pointer to the HW struct
62 * @buf: a virtual buffer to hold the manage MAC read response
63 * @buf_size: Size of the virtual buffer
64 * @cd: pointer to command details structure or NULL
66 * This function is used to return per PF station MAC address (0x0107).
67 * NOTE: Upon successful completion of this command, MAC address information
68 * is returned in user specified buffer. Please interpret user specified
69 * buffer as "manage_mac_read" response.
70 * Response such as various MAC addresses are stored in HW struct (port.mac)
71 * ice_aq_discover_caps is expected to be called before this function is called.
73 static enum ice_status
74 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
77 struct ice_aqc_manage_mac_read_resp *resp;
78 struct ice_aqc_manage_mac_read *cmd;
79 struct ice_aq_desc desc;
80 enum ice_status status;
84 cmd = &desc.params.mac_read;
86 if (buf_size < sizeof(*resp))
87 return ICE_ERR_BUF_TOO_SHORT;
89 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
91 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
95 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
96 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
98 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
99 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
103 /* A single port can report up to two (LAN and WoL) addresses */
104 for (i = 0; i < cmd->num_addr; i++)
105 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
106 ice_memcpy(hw->port_info->mac.lan_addr,
107 resp[i].mac_addr, ETH_ALEN,
109 ice_memcpy(hw->port_info->mac.perm_addr,
111 ETH_ALEN, ICE_DMA_TO_NONDMA);
118 * ice_aq_get_phy_caps - returns PHY capabilities
119 * @pi: port information structure
120 * @qual_mods: report qualified modules
121 * @report_mode: report mode capabilities
122 * @pcaps: structure for PHY capabilities to be filled
123 * @cd: pointer to command details structure or NULL
125 * Returns the various PHY capabilities supported on the Port (0x0600)
128 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
129 struct ice_aqc_get_phy_caps_data *pcaps,
130 struct ice_sq_cd *cd)
132 struct ice_aqc_get_phy_caps *cmd;
133 u16 pcaps_size = sizeof(*pcaps);
134 struct ice_aq_desc desc;
135 enum ice_status status;
137 cmd = &desc.params.get_phy;
139 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
140 return ICE_ERR_PARAM;
142 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
145 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
147 cmd->param0 |= CPU_TO_LE16(report_mode);
148 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
150 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
151 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
152 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
159 * ice_aq_get_link_topo_handle - get link topology node return status
160 * @pi: port information structure
161 * @node_type: requested node type
162 * @cd: pointer to command details structure or NULL
164 * Get link topology node return status for specified node type (0x06E0)
166 * Node type cage can be used to determine if cage is present. If AQC
167 * returns error (ENOENT), then no cage present. If no cage present, then
168 * connection type is backplane or BASE-T.
170 static enum ice_status
171 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
172 struct ice_sq_cd *cd)
174 struct ice_aqc_get_link_topo *cmd;
175 struct ice_aq_desc desc;
177 cmd = &desc.params.get_link_topo;
179 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
181 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
182 ICE_AQC_LINK_TOPO_NODE_CTX_S);
185 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
187 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
191 * ice_is_media_cage_present
192 * @pi: port information structure
194 * Returns true if media cage is present, else false. If no cage, then
195 * media type is backplane or BASE-T.
197 static bool ice_is_media_cage_present(struct ice_port_info *pi)
199 /* Node type cage can be used to determine if cage is present. If AQC
200 * returns error (ENOENT), then no cage present. If no cage present then
201 * connection type is backplane or BASE-T.
203 return !ice_aq_get_link_topo_handle(pi,
204 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
209 * ice_get_media_type - Gets media type
210 * @pi: port information structure
212 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
214 struct ice_link_status *hw_link_info;
217 return ICE_MEDIA_UNKNOWN;
219 hw_link_info = &pi->phy.link_info;
220 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
221 /* If more than one media type is selected, report unknown */
222 return ICE_MEDIA_UNKNOWN;
224 if (hw_link_info->phy_type_low) {
225 switch (hw_link_info->phy_type_low) {
226 case ICE_PHY_TYPE_LOW_1000BASE_SX:
227 case ICE_PHY_TYPE_LOW_1000BASE_LX:
228 case ICE_PHY_TYPE_LOW_10GBASE_SR:
229 case ICE_PHY_TYPE_LOW_10GBASE_LR:
230 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
231 case ICE_PHY_TYPE_LOW_25GBASE_SR:
232 case ICE_PHY_TYPE_LOW_25GBASE_LR:
233 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
234 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
235 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
236 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
237 case ICE_PHY_TYPE_LOW_50GBASE_SR:
238 case ICE_PHY_TYPE_LOW_50GBASE_FR:
239 case ICE_PHY_TYPE_LOW_50GBASE_LR:
240 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
241 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
242 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
243 case ICE_PHY_TYPE_LOW_100GBASE_DR:
244 return ICE_MEDIA_FIBER;
245 case ICE_PHY_TYPE_LOW_100BASE_TX:
246 case ICE_PHY_TYPE_LOW_1000BASE_T:
247 case ICE_PHY_TYPE_LOW_2500BASE_T:
248 case ICE_PHY_TYPE_LOW_5GBASE_T:
249 case ICE_PHY_TYPE_LOW_10GBASE_T:
250 case ICE_PHY_TYPE_LOW_25GBASE_T:
251 return ICE_MEDIA_BASET;
252 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
253 case ICE_PHY_TYPE_LOW_25GBASE_CR:
254 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
255 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
256 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
257 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
258 case ICE_PHY_TYPE_LOW_50GBASE_CP:
259 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
260 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
261 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
263 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
264 case ICE_PHY_TYPE_LOW_40G_XLAUI:
265 case ICE_PHY_TYPE_LOW_50G_LAUI2:
266 case ICE_PHY_TYPE_LOW_50G_AUI2:
267 case ICE_PHY_TYPE_LOW_50G_AUI1:
268 case ICE_PHY_TYPE_LOW_100G_AUI4:
269 case ICE_PHY_TYPE_LOW_100G_CAUI4:
270 if (ice_is_media_cage_present(pi))
273 case ICE_PHY_TYPE_LOW_1000BASE_KX:
274 case ICE_PHY_TYPE_LOW_2500BASE_KX:
275 case ICE_PHY_TYPE_LOW_2500BASE_X:
276 case ICE_PHY_TYPE_LOW_5GBASE_KR:
277 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
278 case ICE_PHY_TYPE_LOW_25GBASE_KR:
279 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
280 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
281 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
282 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
283 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
284 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
285 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
286 return ICE_MEDIA_BACKPLANE;
289 switch (hw_link_info->phy_type_high) {
290 case ICE_PHY_TYPE_HIGH_100G_AUI2:
291 if (ice_is_media_cage_present(pi))
294 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
295 return ICE_MEDIA_BACKPLANE;
298 return ICE_MEDIA_UNKNOWN;
302 * ice_aq_get_link_info
303 * @pi: port information structure
304 * @ena_lse: enable/disable LinkStatusEvent reporting
305 * @link: pointer to link status structure - optional
306 * @cd: pointer to command details structure or NULL
308 * Get Link Status (0x607). Returns the link status of the adapter.
311 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
312 struct ice_link_status *link, struct ice_sq_cd *cd)
314 struct ice_aqc_get_link_status_data link_data = { 0 };
315 struct ice_aqc_get_link_status *resp;
316 struct ice_link_status *li_old, *li;
317 enum ice_media_type *hw_media_type;
318 struct ice_fc_info *hw_fc_info;
319 bool tx_pause, rx_pause;
320 struct ice_aq_desc desc;
321 enum ice_status status;
326 return ICE_ERR_PARAM;
328 li_old = &pi->phy.link_info_old;
329 hw_media_type = &pi->phy.media_type;
330 li = &pi->phy.link_info;
331 hw_fc_info = &pi->fc;
333 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
334 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
335 resp = &desc.params.get_link_status;
336 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
337 resp->lport_num = pi->lport;
339 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
341 if (status != ICE_SUCCESS)
344 /* save off old link status information */
347 /* update current link status information */
348 li->link_speed = LE16_TO_CPU(link_data.link_speed);
349 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
350 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
351 *hw_media_type = ice_get_media_type(pi);
352 li->link_info = link_data.link_info;
353 li->an_info = link_data.an_info;
354 li->ext_info = link_data.ext_info;
355 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
356 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
357 li->topo_media_conflict = link_data.topo_media_conflict;
358 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
359 ICE_AQ_CFG_PACING_TYPE_M);
362 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
363 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
364 if (tx_pause && rx_pause)
365 hw_fc_info->current_mode = ICE_FC_FULL;
367 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
369 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
371 hw_fc_info->current_mode = ICE_FC_NONE;
373 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
375 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
376 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
377 (unsigned long long)li->phy_type_low);
378 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
379 (unsigned long long)li->phy_type_high);
380 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
381 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
382 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
383 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
384 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
385 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
386 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
388 /* save link status information */
392 /* flag cleared so calling functions don't call AQ again */
393 pi->phy.get_link_info = false;
400 * @hw: pointer to the HW struct
401 * @max_frame_size: Maximum Frame Size to be supported
402 * @cd: pointer to command details structure or NULL
404 * Set MAC configuration (0x0603)
407 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
409 u16 fc_threshold_val, tx_timer_val;
410 struct ice_aqc_set_mac_cfg *cmd;
411 struct ice_aq_desc desc;
414 cmd = &desc.params.set_mac_cfg;
416 if (max_frame_size == 0)
417 return ICE_ERR_PARAM;
419 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
421 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
423 /* We read back the transmit timer and fc threshold value of
424 * LFC. Thus, we will use index =
425 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
427 * Also, because we are opearating on transmit timer and fc
428 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
430 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
432 /* Retrieve the transmit timer */
434 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
435 tx_timer_val = reg_val &
436 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
437 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
439 /* Retrieve the fc threshold */
441 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
442 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);
443 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);
445 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
449 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
450 * @hw: pointer to the HW struct
452 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
454 struct ice_switch_info *sw;
456 hw->switch_info = (struct ice_switch_info *)
457 ice_malloc(hw, sizeof(*hw->switch_info));
458 sw = hw->switch_info;
461 return ICE_ERR_NO_MEMORY;
463 INIT_LIST_HEAD(&sw->vsi_list_map_head);
465 return ice_init_def_sw_recp(hw);
469 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
470 * @hw: pointer to the HW struct
472 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
474 struct ice_switch_info *sw = hw->switch_info;
475 struct ice_vsi_list_map_info *v_pos_map;
476 struct ice_vsi_list_map_info *v_tmp_map;
477 struct ice_sw_recipe *recps;
480 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
481 ice_vsi_list_map_info, list_entry) {
482 LIST_DEL(&v_pos_map->list_entry);
483 ice_free(hw, v_pos_map);
485 recps = hw->switch_info->recp_list;
486 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
487 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
489 recps[i].root_rid = i;
490 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
491 &recps[i].rg_list, ice_recp_grp_entry,
493 LIST_DEL(&rg_entry->l_entry);
494 ice_free(hw, rg_entry);
497 if (recps[i].adv_rule) {
498 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
499 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
501 ice_destroy_lock(&recps[i].filt_rule_lock);
502 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
503 &recps[i].filt_rules,
504 ice_adv_fltr_mgmt_list_entry,
506 LIST_DEL(&lst_itr->list_entry);
507 ice_free(hw, lst_itr->lkups);
508 ice_free(hw, lst_itr);
511 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
513 ice_destroy_lock(&recps[i].filt_rule_lock);
514 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
515 &recps[i].filt_rules,
516 ice_fltr_mgmt_list_entry,
518 LIST_DEL(&lst_itr->list_entry);
519 ice_free(hw, lst_itr);
522 if (recps[i].root_buf)
523 ice_free(hw, recps[i].root_buf);
525 ice_rm_all_sw_replay_rule_info(hw);
526 ice_free(hw, sw->recp_list);
531 * ice_get_itr_intrl_gran
532 * @hw: pointer to the HW struct
534 * Determines the ITR/INTRL granularities based on the maximum aggregate
535 * bandwidth according to the device's configuration during power-on.
537 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
539 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
540 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
541 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
543 switch (max_agg_bw) {
544 case ICE_MAX_AGG_BW_200G:
545 case ICE_MAX_AGG_BW_100G:
546 case ICE_MAX_AGG_BW_50G:
547 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
548 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
550 case ICE_MAX_AGG_BW_25G:
551 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
552 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
558 * ice_get_nvm_version - get cached NVM version data
559 * @hw: pointer to the hardware structure
560 * @oem_ver: 8 bit NVM version
561 * @oem_build: 16 bit NVM build number
562 * @oem_patch: 8 NVM patch number
563 * @ver_hi: high 16 bits of the NVM version
564 * @ver_lo: low 16 bits of the NVM version
567 ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
568 u8 *oem_patch, u8 *ver_hi, u8 *ver_lo)
570 struct ice_nvm_info *nvm = &hw->nvm;
572 *oem_ver = (u8)((nvm->oem_ver & ICE_OEM_VER_MASK) >> ICE_OEM_VER_SHIFT);
573 *oem_patch = (u8)(nvm->oem_ver & ICE_OEM_VER_PATCH_MASK);
574 *oem_build = (u16)((nvm->oem_ver & ICE_OEM_VER_BUILD_MASK) >>
575 ICE_OEM_VER_BUILD_SHIFT);
576 *ver_hi = (nvm->ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
577 *ver_lo = (nvm->ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
581 * ice_print_rollback_msg - print FW rollback message
582 * @hw: pointer to the hardware structure
584 void ice_print_rollback_msg(struct ice_hw *hw)
586 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
587 u8 oem_ver, oem_patch, ver_hi, ver_lo;
590 ice_get_nvm_version(hw, &oem_ver, &oem_build, &oem_patch, &ver_hi,
592 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", ver_hi,
593 ver_lo, hw->nvm.eetrack, oem_ver, oem_build, oem_patch);
595 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode",
596 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
600 * ice_init_hw - main hardware initialization routine
601 * @hw: pointer to the hardware structure
603 enum ice_status ice_init_hw(struct ice_hw *hw)
605 struct ice_aqc_get_phy_caps_data *pcaps;
606 enum ice_status status;
610 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
612 /* Set MAC type based on DeviceID */
613 status = ice_set_mac_type(hw);
617 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
618 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
619 PF_FUNC_RID_FUNCTION_NUMBER_S;
621 status = ice_reset(hw, ICE_RESET_PFR);
625 ice_get_itr_intrl_gran(hw);
627 status = ice_create_all_ctrlq(hw);
629 goto err_unroll_cqinit;
631 status = ice_init_nvm(hw);
633 goto err_unroll_cqinit;
635 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
636 ice_print_rollback_msg(hw);
638 status = ice_clear_pf_cfg(hw);
640 goto err_unroll_cqinit;
642 /* Set bit to enable Flow Director filters */
643 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
644 INIT_LIST_HEAD(&hw->fdir_list_head);
646 ice_clear_pxe_mode(hw);
648 status = ice_get_caps(hw);
650 goto err_unroll_cqinit;
652 hw->port_info = (struct ice_port_info *)
653 ice_malloc(hw, sizeof(*hw->port_info));
654 if (!hw->port_info) {
655 status = ICE_ERR_NO_MEMORY;
656 goto err_unroll_cqinit;
659 /* set the back pointer to HW */
660 hw->port_info->hw = hw;
662 /* Initialize port_info struct with switch configuration data */
663 status = ice_get_initial_sw_cfg(hw);
665 goto err_unroll_alloc;
668 /* Query the allocated resources for Tx scheduler */
669 status = ice_sched_query_res_alloc(hw);
671 ice_debug(hw, ICE_DBG_SCHED,
672 "Failed to get scheduler allocated resources\n");
673 goto err_unroll_alloc;
676 /* Initialize port_info struct with scheduler data */
677 status = ice_sched_init_port(hw->port_info);
679 goto err_unroll_sched;
681 pcaps = (struct ice_aqc_get_phy_caps_data *)
682 ice_malloc(hw, sizeof(*pcaps));
684 status = ICE_ERR_NO_MEMORY;
685 goto err_unroll_sched;
688 /* Initialize port_info struct with PHY capabilities */
689 status = ice_aq_get_phy_caps(hw->port_info, false,
690 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
693 goto err_unroll_sched;
695 /* Initialize port_info struct with link information */
696 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
698 goto err_unroll_sched;
699 /* need a valid SW entry point to build a Tx tree */
700 if (!hw->sw_entry_point_layer) {
701 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
702 status = ICE_ERR_CFG;
703 goto err_unroll_sched;
705 INIT_LIST_HEAD(&hw->agg_list);
706 /* Initialize max burst size */
707 if (!hw->max_burst_size)
708 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
710 status = ice_init_fltr_mgmt_struct(hw);
712 goto err_unroll_sched;
714 /* Get MAC information */
715 /* A single port can report up to two (LAN and WoL) addresses */
716 mac_buf = ice_calloc(hw, 2,
717 sizeof(struct ice_aqc_manage_mac_read_resp));
718 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
721 status = ICE_ERR_NO_MEMORY;
722 goto err_unroll_fltr_mgmt_struct;
725 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
726 ice_free(hw, mac_buf);
729 goto err_unroll_fltr_mgmt_struct;
730 /* Obtain counter base index which would be used by flow director */
731 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
733 goto err_unroll_fltr_mgmt_struct;
734 status = ice_init_hw_tbls(hw);
736 goto err_unroll_fltr_mgmt_struct;
739 err_unroll_fltr_mgmt_struct:
740 ice_cleanup_fltr_mgmt_struct(hw);
742 ice_sched_cleanup_all(hw);
744 ice_free(hw, hw->port_info);
745 hw->port_info = NULL;
747 ice_destroy_all_ctrlq(hw);
752 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
753 * @hw: pointer to the hardware structure
755 * This should be called only during nominal operation, not as a result of
756 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
757 * applicable initializations if it fails for any reason.
759 void ice_deinit_hw(struct ice_hw *hw)
761 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
762 ice_cleanup_fltr_mgmt_struct(hw);
764 ice_sched_cleanup_all(hw);
765 ice_sched_clear_agg(hw);
767 ice_free_hw_tbls(hw);
770 ice_free(hw, hw->port_info);
771 hw->port_info = NULL;
774 ice_destroy_all_ctrlq(hw);
776 /* Clear VSI contexts if not already cleared */
777 ice_clear_all_vsi_ctx(hw);
781 * ice_check_reset - Check to see if a global reset is complete
782 * @hw: pointer to the hardware structure
784 enum ice_status ice_check_reset(struct ice_hw *hw)
786 u32 cnt, reg = 0, grst_delay, uld_mask;
788 /* Poll for Device Active state in case a recent CORER, GLOBR,
789 * or EMPR has occurred. The grst delay value is in 100ms units.
790 * Add 1sec for outstanding AQ commands that can take a long time.
792 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
793 GLGEN_RSTCTL_GRSTDEL_S) + 10;
795 for (cnt = 0; cnt < grst_delay; cnt++) {
796 ice_msec_delay(100, true);
797 reg = rd32(hw, GLGEN_RSTAT);
798 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
802 if (cnt == grst_delay) {
803 ice_debug(hw, ICE_DBG_INIT,
804 "Global reset polling failed to complete.\n");
805 return ICE_ERR_RESET_FAILED;
808 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
809 GLNVM_ULD_PCIER_DONE_1_M |\
810 GLNVM_ULD_CORER_DONE_M |\
811 GLNVM_ULD_GLOBR_DONE_M |\
812 GLNVM_ULD_POR_DONE_M |\
813 GLNVM_ULD_POR_DONE_1_M |\
814 GLNVM_ULD_PCIER_DONE_2_M)
816 uld_mask = ICE_RESET_DONE_MASK;
818 /* Device is Active; check Global Reset processes are done */
819 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
820 reg = rd32(hw, GLNVM_ULD) & uld_mask;
821 if (reg == uld_mask) {
822 ice_debug(hw, ICE_DBG_INIT,
823 "Global reset processes done. %d\n", cnt);
826 ice_msec_delay(10, true);
829 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
830 ice_debug(hw, ICE_DBG_INIT,
831 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
833 return ICE_ERR_RESET_FAILED;
840 * ice_pf_reset - Reset the PF
841 * @hw: pointer to the hardware structure
843 * If a global reset has been triggered, this function checks
844 * for its completion and then issues the PF reset
846 static enum ice_status ice_pf_reset(struct ice_hw *hw)
850 /* If at function entry a global reset was already in progress, i.e.
851 * state is not 'device active' or any of the reset done bits are not
852 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
853 * global reset is done.
855 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
856 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
857 /* poll on global reset currently in progress until done */
858 if (ice_check_reset(hw))
859 return ICE_ERR_RESET_FAILED;
865 reg = rd32(hw, PFGEN_CTRL);
867 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
869 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
870 reg = rd32(hw, PFGEN_CTRL);
871 if (!(reg & PFGEN_CTRL_PFSWR_M))
874 ice_msec_delay(1, true);
877 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
878 ice_debug(hw, ICE_DBG_INIT,
879 "PF reset polling failed to complete.\n");
880 return ICE_ERR_RESET_FAILED;
887 * ice_reset - Perform different types of reset
888 * @hw: pointer to the hardware structure
889 * @req: reset request
891 * This function triggers a reset as specified by the req parameter.
894 * If anything other than a PF reset is triggered, PXE mode is restored.
895 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
896 * interface has been restored in the rebuild flow.
898 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
904 return ice_pf_reset(hw);
905 case ICE_RESET_CORER:
906 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
907 val = GLGEN_RTRIG_CORER_M;
909 case ICE_RESET_GLOBR:
910 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
911 val = GLGEN_RTRIG_GLOBR_M;
914 return ICE_ERR_PARAM;
917 val |= rd32(hw, GLGEN_RTRIG);
918 wr32(hw, GLGEN_RTRIG, val);
921 /* wait for the FW to be ready */
922 return ice_check_reset(hw);
926 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
927 * @hw: pointer to hardware structure
928 * @module_tlv: pointer to module TLV to return
929 * @module_tlv_len: pointer to module TLV length to return
930 * @module_type: module type requested
932 * Finds the requested sub module TLV type from the Preserved Field
933 * Area (PFA) and returns the TLV pointer and length. The caller can
934 * use these to read the variable length TLV value.
937 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
940 enum ice_status status;
941 u16 pfa_len, pfa_ptr;
944 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
945 if (status != ICE_SUCCESS) {
946 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
949 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
950 if (status != ICE_SUCCESS) {
951 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
954 /* Starting with first TLV after PFA length, iterate through the list
955 * of TLVs to find the requested one.
957 next_tlv = pfa_ptr + 1;
958 while (next_tlv < pfa_ptr + pfa_len) {
959 u16 tlv_sub_module_type;
963 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
964 if (status != ICE_SUCCESS) {
965 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
968 /* Read TLV length */
969 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
970 if (status != ICE_SUCCESS) {
971 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
974 if (tlv_sub_module_type == module_type) {
976 *module_tlv = next_tlv;
977 *module_tlv_len = tlv_len;
980 return ICE_ERR_INVAL_SIZE;
982 /* Check next TLV, i.e. current TLV pointer + length + 2 words
983 * (for current TLV's type and length)
985 next_tlv = next_tlv + tlv_len + 2;
987 /* Module does not exist */
988 return ICE_ERR_DOES_NOT_EXIST;
992 * ice_copy_rxq_ctx_to_hw
993 * @hw: pointer to the hardware structure
994 * @ice_rxq_ctx: pointer to the rxq context
995 * @rxq_index: the index of the Rx queue
997 * Copies rxq context from dense structure to HW register space
999 static enum ice_status
1000 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1005 return ICE_ERR_BAD_PTR;
1007 if (rxq_index > QRX_CTRL_MAX_INDEX)
1008 return ICE_ERR_PARAM;
1010 /* Copy each dword separately to HW */
1011 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1012 wr32(hw, QRX_CONTEXT(i, rxq_index),
1013 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1015 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1016 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1022 /* LAN Rx Queue Context */
1023 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1024 /* Field Width LSB */
1025 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1026 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1027 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1028 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1029 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1030 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1031 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1032 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1033 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1034 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1035 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1036 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1037 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1038 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1039 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1040 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1041 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1042 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1043 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1044 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1050 * @hw: pointer to the hardware structure
1051 * @rlan_ctx: pointer to the rxq context
1052 * @rxq_index: the index of the Rx queue
1054 * Converts rxq context from sparse to dense structure and then writes
1055 * it to HW register space and enables the hardware to prefetch descriptors
1056 * instead of only fetching them on demand
1059 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1062 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1065 return ICE_ERR_BAD_PTR;
1067 rlan_ctx->prefena = 1;
1069 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1070 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1075 * @hw: pointer to the hardware structure
1076 * @rxq_index: the index of the Rx queue to clear
1078 * Clears rxq context in HW register space
1080 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1084 if (rxq_index > QRX_CTRL_MAX_INDEX)
1085 return ICE_ERR_PARAM;
1087 /* Clear each dword register separately */
1088 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1089 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1094 /* LAN Tx Queue Context */
1095 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1096 /* Field Width LSB */
1097 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1098 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1099 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1100 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1101 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1102 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1103 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1104 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1105 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1106 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1107 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1108 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1109 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1110 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1111 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1112 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1113 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1114 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1115 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1116 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1117 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1118 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1119 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1120 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1121 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1122 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1123 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1124 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1129 * ice_copy_tx_cmpltnq_ctx_to_hw
1130 * @hw: pointer to the hardware structure
1131 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1132 * @tx_cmpltnq_index: the index of the completion queue
1134 * Copies Tx completion queue context from dense structure to HW register space
1136 static enum ice_status
1137 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1138 u32 tx_cmpltnq_index)
1142 if (!ice_tx_cmpltnq_ctx)
1143 return ICE_ERR_BAD_PTR;
1145 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1146 return ICE_ERR_PARAM;
1148 /* Copy each dword separately to HW */
1149 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1150 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1151 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1153 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1154 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1160 /* LAN Tx Completion Queue Context */
1161 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1162 /* Field Width LSB */
1163 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1164 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1165 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1166 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1167 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1168 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1169 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1170 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1171 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1172 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1177 * ice_write_tx_cmpltnq_ctx
1178 * @hw: pointer to the hardware structure
1179 * @tx_cmpltnq_ctx: pointer to the completion queue context
1180 * @tx_cmpltnq_index: the index of the completion queue
1182 * Converts completion queue context from sparse to dense structure and then
1183 * writes it to HW register space
1186 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1187 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1188 u32 tx_cmpltnq_index)
1190 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1192 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1193 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1197 * ice_clear_tx_cmpltnq_ctx
1198 * @hw: pointer to the hardware structure
1199 * @tx_cmpltnq_index: the index of the completion queue to clear
1201 * Clears Tx completion queue context in HW register space
1204 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1208 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1209 return ICE_ERR_PARAM;
1211 /* Clear each dword register separately */
1212 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1213 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1219 * ice_copy_tx_drbell_q_ctx_to_hw
1220 * @hw: pointer to the hardware structure
1221 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1222 * @tx_drbell_q_index: the index of the doorbell queue
1224 * Copies doorbell queue context from dense structure to HW register space
1226 static enum ice_status
1227 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1228 u32 tx_drbell_q_index)
1232 if (!ice_tx_drbell_q_ctx)
1233 return ICE_ERR_BAD_PTR;
1235 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1236 return ICE_ERR_PARAM;
1238 /* Copy each dword separately to HW */
1239 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1240 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1241 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1243 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1244 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1250 /* LAN Tx Doorbell Queue Context info */
1251 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1252 /* Field Width LSB */
1253 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1254 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1255 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1256 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1257 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1258 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1259 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1260 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1261 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1262 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1263 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1268 * ice_write_tx_drbell_q_ctx
1269 * @hw: pointer to the hardware structure
1270 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1271 * @tx_drbell_q_index: the index of the doorbell queue
1273 * Converts doorbell queue context from sparse to dense structure and then
1274 * writes it to HW register space
1277 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1278 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1279 u32 tx_drbell_q_index)
1281 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1283 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1284 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1288 * ice_clear_tx_drbell_q_ctx
1289 * @hw: pointer to the hardware structure
1290 * @tx_drbell_q_index: the index of the doorbell queue to clear
1292 * Clears doorbell queue context in HW register space
1295 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1299 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1300 return ICE_ERR_PARAM;
1302 /* Clear each dword register separately */
1303 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1304 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1309 /* FW Admin Queue command wrappers */
1312 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1313 * @hw: pointer to the HW struct
1314 * @desc: descriptor describing the command
1315 * @buf: buffer to use for indirect commands (NULL for direct commands)
1316 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1317 * @cd: pointer to command details structure
1319 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1322 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1323 u16 buf_size, struct ice_sq_cd *cd)
1325 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1330 * @hw: pointer to the HW struct
1331 * @cd: pointer to command details structure or NULL
1333 * Get the firmware version (0x0001) from the admin queue commands
1335 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1337 struct ice_aqc_get_ver *resp;
1338 struct ice_aq_desc desc;
1339 enum ice_status status;
1341 resp = &desc.params.get_ver;
1343 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1345 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1348 hw->fw_branch = resp->fw_branch;
1349 hw->fw_maj_ver = resp->fw_major;
1350 hw->fw_min_ver = resp->fw_minor;
1351 hw->fw_patch = resp->fw_patch;
1352 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1353 hw->api_branch = resp->api_branch;
1354 hw->api_maj_ver = resp->api_major;
1355 hw->api_min_ver = resp->api_minor;
1356 hw->api_patch = resp->api_patch;
1363 * ice_aq_send_driver_ver
1364 * @hw: pointer to the HW struct
1365 * @dv: driver's major, minor version
1366 * @cd: pointer to command details structure or NULL
1368 * Send the driver version (0x0002) to the firmware
1371 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1372 struct ice_sq_cd *cd)
1374 struct ice_aqc_driver_ver *cmd;
1375 struct ice_aq_desc desc;
1378 cmd = &desc.params.driver_ver;
1381 return ICE_ERR_PARAM;
1383 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1385 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1386 cmd->major_ver = dv->major_ver;
1387 cmd->minor_ver = dv->minor_ver;
1388 cmd->build_ver = dv->build_ver;
1389 cmd->subbuild_ver = dv->subbuild_ver;
1392 while (len < sizeof(dv->driver_string) &&
1393 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1396 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1401 * @hw: pointer to the HW struct
1402 * @unloading: is the driver unloading itself
1404 * Tell the Firmware that we're shutting down the AdminQ and whether
1405 * or not the driver is unloading as well (0x0003).
1407 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1409 struct ice_aqc_q_shutdown *cmd;
1410 struct ice_aq_desc desc;
1412 cmd = &desc.params.q_shutdown;
1414 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1417 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1419 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1424 * @hw: pointer to the HW struct
1426 * @access: access type
1427 * @sdp_number: resource number
1428 * @timeout: the maximum time in ms that the driver may hold the resource
1429 * @cd: pointer to command details structure or NULL
1431 * Requests common resource using the admin queue commands (0x0008).
1432 * When attempting to acquire the Global Config Lock, the driver can
1433 * learn of three states:
1434 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1435 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1436 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1437 * successfully downloaded the package; the driver does
1438 * not have to download the package and can continue
1441 * Note that if the caller is in an acquire lock, perform action, release lock
1442 * phase of operation, it is possible that the FW may detect a timeout and issue
1443 * a CORER. In this case, the driver will receive a CORER interrupt and will
1444 * have to determine its cause. The calling thread that is handling this flow
1445 * will likely get an error propagated back to it indicating the Download
1446 * Package, Update Package or the Release Resource AQ commands timed out.
1448 static enum ice_status
1449 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1450 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1451 struct ice_sq_cd *cd)
1453 struct ice_aqc_req_res *cmd_resp;
1454 struct ice_aq_desc desc;
1455 enum ice_status status;
1457 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1459 cmd_resp = &desc.params.res_owner;
1461 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1463 cmd_resp->res_id = CPU_TO_LE16(res);
1464 cmd_resp->access_type = CPU_TO_LE16(access);
1465 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1466 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1469 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1471 /* The completion specifies the maximum time in ms that the driver
1472 * may hold the resource in the Timeout field.
1475 /* Global config lock response utilizes an additional status field.
1477 * If the Global config lock resource is held by some other driver, the
1478 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1479 * and the timeout field indicates the maximum time the current owner
1480 * of the resource has to free it.
1482 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1483 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1484 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1486 } else if (LE16_TO_CPU(cmd_resp->status) ==
1487 ICE_AQ_RES_GLBL_IN_PROG) {
1488 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1489 return ICE_ERR_AQ_ERROR;
1490 } else if (LE16_TO_CPU(cmd_resp->status) ==
1491 ICE_AQ_RES_GLBL_DONE) {
1492 return ICE_ERR_AQ_NO_WORK;
1495 /* invalid FW response, force a timeout immediately */
1497 return ICE_ERR_AQ_ERROR;
1500 /* If the resource is held by some other driver, the command completes
1501 * with a busy return value and the timeout field indicates the maximum
1502 * time the current owner of the resource has to free it.
1504 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1505 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1511 * ice_aq_release_res
1512 * @hw: pointer to the HW struct
1514 * @sdp_number: resource number
1515 * @cd: pointer to command details structure or NULL
1517 * release common resource using the admin queue commands (0x0009)
1519 static enum ice_status
1520 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1521 struct ice_sq_cd *cd)
1523 struct ice_aqc_req_res *cmd;
1524 struct ice_aq_desc desc;
1526 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1528 cmd = &desc.params.res_owner;
1530 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1532 cmd->res_id = CPU_TO_LE16(res);
1533 cmd->res_number = CPU_TO_LE32(sdp_number);
1535 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1540 * @hw: pointer to the HW structure
1542 * @access: access type (read or write)
1543 * @timeout: timeout in milliseconds
1545 * This function will attempt to acquire the ownership of a resource.
1548 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1549 enum ice_aq_res_access_type access, u32 timeout)
1551 #define ICE_RES_POLLING_DELAY_MS 10
1552 u32 delay = ICE_RES_POLLING_DELAY_MS;
1553 u32 time_left = timeout;
1554 enum ice_status status;
1556 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1558 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1560 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1561 * previously acquired the resource and performed any necessary updates;
1562 * in this case the caller does not obtain the resource and has no
1563 * further work to do.
1565 if (status == ICE_ERR_AQ_NO_WORK)
1566 goto ice_acquire_res_exit;
1569 ice_debug(hw, ICE_DBG_RES,
1570 "resource %d acquire type %d failed.\n", res, access);
1572 /* If necessary, poll until the current lock owner timeouts */
1573 timeout = time_left;
1574 while (status && timeout && time_left) {
1575 ice_msec_delay(delay, true);
1576 timeout = (timeout > delay) ? timeout - delay : 0;
1577 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1579 if (status == ICE_ERR_AQ_NO_WORK)
1580 /* lock free, but no work to do */
1587 if (status && status != ICE_ERR_AQ_NO_WORK)
1588 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1590 ice_acquire_res_exit:
1591 if (status == ICE_ERR_AQ_NO_WORK) {
1592 if (access == ICE_RES_WRITE)
1593 ice_debug(hw, ICE_DBG_RES,
1594 "resource indicates no work to do.\n");
1596 ice_debug(hw, ICE_DBG_RES,
1597 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1604 * @hw: pointer to the HW structure
1607 * This function will release a resource using the proper Admin Command.
1609 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1611 enum ice_status status;
1612 u32 total_delay = 0;
1614 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1616 status = ice_aq_release_res(hw, res, 0, NULL);
1618 /* there are some rare cases when trying to release the resource
1619 * results in an admin queue timeout, so handle them correctly
1621 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1622 (total_delay < hw->adminq.sq_cmd_timeout)) {
1623 ice_msec_delay(1, true);
1624 status = ice_aq_release_res(hw, res, 0, NULL);
1630 * ice_aq_alloc_free_res - command to allocate/free resources
1631 * @hw: pointer to the HW struct
1632 * @num_entries: number of resource entries in buffer
1633 * @buf: Indirect buffer to hold data parameters and response
1634 * @buf_size: size of buffer for indirect commands
1635 * @opc: pass in the command opcode
1636 * @cd: pointer to command details structure or NULL
1638 * Helper function to allocate/free resources using the admin queue commands
1641 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1642 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1643 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1645 struct ice_aqc_alloc_free_res_cmd *cmd;
1646 struct ice_aq_desc desc;
1648 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1650 cmd = &desc.params.sw_res_ctrl;
1653 return ICE_ERR_PARAM;
1655 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1656 return ICE_ERR_PARAM;
1658 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1660 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1662 cmd->num_entries = CPU_TO_LE16(num_entries);
1664 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1668 * ice_alloc_hw_res - allocate resource
1669 * @hw: pointer to the HW struct
1670 * @type: type of resource
1671 * @num: number of resources to allocate
1672 * @btm: allocate from bottom
1673 * @res: pointer to array that will receive the resources
1676 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1678 struct ice_aqc_alloc_free_res_elem *buf;
1679 enum ice_status status;
1682 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1683 buf = (struct ice_aqc_alloc_free_res_elem *)
1684 ice_malloc(hw, buf_len);
1686 return ICE_ERR_NO_MEMORY;
1688 /* Prepare buffer to allocate resource. */
1689 buf->num_elems = CPU_TO_LE16(num);
1690 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1691 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1693 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1695 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1696 ice_aqc_opc_alloc_res, NULL);
1698 goto ice_alloc_res_exit;
1700 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1701 ICE_NONDMA_TO_NONDMA);
1709 * ice_free_hw_res - free allocated HW resource
1710 * @hw: pointer to the HW struct
1711 * @type: type of resource to free
1712 * @num: number of resources
1713 * @res: pointer to array that contains the resources to free
1716 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1718 struct ice_aqc_alloc_free_res_elem *buf;
1719 enum ice_status status;
1722 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1723 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1725 return ICE_ERR_NO_MEMORY;
1727 /* Prepare buffer to free resource. */
1728 buf->num_elems = CPU_TO_LE16(num);
1729 buf->res_type = CPU_TO_LE16(type);
1730 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1731 ICE_NONDMA_TO_NONDMA);
1733 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1734 ice_aqc_opc_free_res, NULL);
1736 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1743 * ice_get_num_per_func - determine number of resources per PF
1744 * @hw: pointer to the HW structure
1745 * @max: value to be evenly split between each PF
1747 * Determine the number of valid functions by going through the bitmap returned
1748 * from parsing capabilities and use this to calculate the number of resources
1749 * per PF based on the max value passed in.
1751 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1755 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1756 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1757 ICE_CAPS_VALID_FUNCS_M);
1766 * ice_parse_caps - parse function/device capabilities
1767 * @hw: pointer to the HW struct
1768 * @buf: pointer to a buffer containing function/device capability records
1769 * @cap_count: number of capability records in the list
1770 * @opc: type of capabilities list to parse
1772 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1775 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1776 enum ice_adminq_opc opc)
1778 struct ice_aqc_list_caps_elem *cap_resp;
1779 struct ice_hw_func_caps *func_p = NULL;
1780 struct ice_hw_dev_caps *dev_p = NULL;
1781 struct ice_hw_common_caps *caps;
1788 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1790 if (opc == ice_aqc_opc_list_dev_caps) {
1791 dev_p = &hw->dev_caps;
1792 caps = &dev_p->common_cap;
1794 } else if (opc == ice_aqc_opc_list_func_caps) {
1795 func_p = &hw->func_caps;
1796 caps = &func_p->common_cap;
1797 prefix = "func cap";
1799 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1803 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1804 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1805 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1806 u32 number = LE32_TO_CPU(cap_resp->number);
1807 u16 cap = LE16_TO_CPU(cap_resp->cap);
1810 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1811 caps->valid_functions = number;
1812 ice_debug(hw, ICE_DBG_INIT,
1813 "%s: valid_functions (bitmap) = %d\n", prefix,
1814 caps->valid_functions);
1816 /* store func count for resource management purposes */
1818 dev_p->num_funcs = ice_hweight32(number);
1820 case ICE_AQC_CAPS_VSI:
1822 dev_p->num_vsi_allocd_to_host = number;
1823 ice_debug(hw, ICE_DBG_INIT,
1824 "%s: num_vsi_allocd_to_host = %d\n",
1826 dev_p->num_vsi_allocd_to_host);
1827 } else if (func_p) {
1828 func_p->guar_num_vsi =
1829 ice_get_num_per_func(hw, ICE_MAX_VSI);
1830 ice_debug(hw, ICE_DBG_INIT,
1831 "%s: guar_num_vsi (fw) = %d\n",
1833 ice_debug(hw, ICE_DBG_INIT,
1834 "%s: guar_num_vsi = %d\n",
1835 prefix, func_p->guar_num_vsi);
1838 case ICE_AQC_CAPS_DCB:
1839 caps->dcb = (number == 1);
1840 caps->active_tc_bitmap = logical_id;
1841 caps->maxtc = phys_id;
1842 ice_debug(hw, ICE_DBG_INIT,
1843 "%s: dcb = %d\n", prefix, caps->dcb);
1844 ice_debug(hw, ICE_DBG_INIT,
1845 "%s: active_tc_bitmap = %d\n", prefix,
1846 caps->active_tc_bitmap);
1847 ice_debug(hw, ICE_DBG_INIT,
1848 "%s: maxtc = %d\n", prefix, caps->maxtc);
1850 case ICE_AQC_CAPS_RSS:
1851 caps->rss_table_size = number;
1852 caps->rss_table_entry_width = logical_id;
1853 ice_debug(hw, ICE_DBG_INIT,
1854 "%s: rss_table_size = %d\n", prefix,
1855 caps->rss_table_size);
1856 ice_debug(hw, ICE_DBG_INIT,
1857 "%s: rss_table_entry_width = %d\n", prefix,
1858 caps->rss_table_entry_width);
1860 case ICE_AQC_CAPS_RXQS:
1861 caps->num_rxq = number;
1862 caps->rxq_first_id = phys_id;
1863 ice_debug(hw, ICE_DBG_INIT,
1864 "%s: num_rxq = %d\n", prefix,
1866 ice_debug(hw, ICE_DBG_INIT,
1867 "%s: rxq_first_id = %d\n", prefix,
1868 caps->rxq_first_id);
1870 case ICE_AQC_CAPS_TXQS:
1871 caps->num_txq = number;
1872 caps->txq_first_id = phys_id;
1873 ice_debug(hw, ICE_DBG_INIT,
1874 "%s: num_txq = %d\n", prefix,
1876 ice_debug(hw, ICE_DBG_INIT,
1877 "%s: txq_first_id = %d\n", prefix,
1878 caps->txq_first_id);
1880 case ICE_AQC_CAPS_MSIX:
1881 caps->num_msix_vectors = number;
1882 caps->msix_vector_first_id = phys_id;
1883 ice_debug(hw, ICE_DBG_INIT,
1884 "%s: num_msix_vectors = %d\n", prefix,
1885 caps->num_msix_vectors);
1886 ice_debug(hw, ICE_DBG_INIT,
1887 "%s: msix_vector_first_id = %d\n", prefix,
1888 caps->msix_vector_first_id);
1890 case ICE_AQC_CAPS_FD:
1895 dev_p->num_flow_director_fltr = number;
1896 ice_debug(hw, ICE_DBG_INIT,
1897 "%s: num_flow_director_fltr = %d\n",
1899 dev_p->num_flow_director_fltr);
1902 reg_val = rd32(hw, GLQF_FD_SIZE);
1903 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
1904 GLQF_FD_SIZE_FD_GSIZE_S;
1905 func_p->fd_fltr_guar =
1906 ice_get_num_per_func(hw, val);
1907 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
1908 GLQF_FD_SIZE_FD_BSIZE_S;
1909 func_p->fd_fltr_best_effort = val;
1910 ice_debug(hw, ICE_DBG_INIT,
1911 "%s: fd_fltr_guar = %d\n",
1912 prefix, func_p->fd_fltr_guar);
1913 ice_debug(hw, ICE_DBG_INIT,
1914 "%s: fd_fltr_best_effort = %d\n",
1915 prefix, func_p->fd_fltr_best_effort);
1919 case ICE_AQC_CAPS_MAX_MTU:
1920 caps->max_mtu = number;
1921 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1922 prefix, caps->max_mtu);
1925 ice_debug(hw, ICE_DBG_INIT,
1926 "%s: unknown capability[%d]: 0x%x\n", prefix,
1932 /* Re-calculate capabilities that are dependent on the number of
1933 * physical ports; i.e. some features are not supported or function
1934 * differently on devices with more than 4 ports.
1936 if (hw->dev_caps.num_funcs > 4) {
1937 /* Max 4 TCs per port */
1939 ice_debug(hw, ICE_DBG_INIT,
1940 "%s: maxtc = %d (based on #ports)\n", prefix,
1946 * ice_aq_discover_caps - query function/device capabilities
1947 * @hw: pointer to the HW struct
1948 * @buf: a virtual buffer to hold the capabilities
1949 * @buf_size: Size of the virtual buffer
1950 * @cap_count: cap count needed if AQ err==ENOMEM
1951 * @opc: capabilities type to discover - pass in the command opcode
1952 * @cd: pointer to command details structure or NULL
1954 * Get the function(0x000a)/device(0x000b) capabilities description from
1957 static enum ice_status
1958 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
1959 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1961 struct ice_aqc_list_caps *cmd;
1962 struct ice_aq_desc desc;
1963 enum ice_status status;
1965 cmd = &desc.params.get_cap;
1967 if (opc != ice_aqc_opc_list_func_caps &&
1968 opc != ice_aqc_opc_list_dev_caps)
1969 return ICE_ERR_PARAM;
1971 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1973 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1975 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
1976 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
1977 *cap_count = LE32_TO_CPU(cmd->count);
1982 * ice_discover_caps - get info about the HW
1983 * @hw: pointer to the hardware structure
1984 * @opc: capabilities type to discover - pass in the command opcode
1986 static enum ice_status
1987 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
1989 enum ice_status status;
1994 /* The driver doesn't know how many capabilities the device will return
1995 * so the buffer size required isn't known ahead of time. The driver
1996 * starts with cbuf_len and if this turns out to be insufficient, the
1997 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
1998 * The driver then allocates the buffer based on the count and retries
1999 * the operation. So it follows that the retry count is 2.
2001 #define ICE_GET_CAP_BUF_COUNT 40
2002 #define ICE_GET_CAP_RETRY_COUNT 2
2004 cap_count = ICE_GET_CAP_BUF_COUNT;
2005 retries = ICE_GET_CAP_RETRY_COUNT;
2010 cbuf_len = (u16)(cap_count *
2011 sizeof(struct ice_aqc_list_caps_elem));
2012 cbuf = ice_malloc(hw, cbuf_len);
2014 return ICE_ERR_NO_MEMORY;
2016 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2020 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2023 /* If ENOMEM is returned, try again with bigger buffer */
2024 } while (--retries);
2030 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2031 * @hw: pointer to the hardware structure
2033 void ice_set_safe_mode_caps(struct ice_hw *hw)
2035 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2036 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2037 u32 valid_func, rxq_first_id, txq_first_id;
2038 u32 msix_vector_first_id, max_mtu;
2041 /* cache some func_caps values that should be restored after memset */
2042 valid_func = func_caps->common_cap.valid_functions;
2043 txq_first_id = func_caps->common_cap.txq_first_id;
2044 rxq_first_id = func_caps->common_cap.rxq_first_id;
2045 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
2046 max_mtu = func_caps->common_cap.max_mtu;
2048 /* unset func capabilities */
2049 memset(func_caps, 0, sizeof(*func_caps));
2051 /* restore cached values */
2052 func_caps->common_cap.valid_functions = valid_func;
2053 func_caps->common_cap.txq_first_id = txq_first_id;
2054 func_caps->common_cap.rxq_first_id = rxq_first_id;
2055 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2056 func_caps->common_cap.max_mtu = max_mtu;
2058 /* one Tx and one Rx queue in safe mode */
2059 func_caps->common_cap.num_rxq = 1;
2060 func_caps->common_cap.num_txq = 1;
2062 /* two MSIX vectors, one for traffic and one for misc causes */
2063 func_caps->common_cap.num_msix_vectors = 2;
2064 func_caps->guar_num_vsi = 1;
2066 /* cache some dev_caps values that should be restored after memset */
2067 valid_func = dev_caps->common_cap.valid_functions;
2068 txq_first_id = dev_caps->common_cap.txq_first_id;
2069 rxq_first_id = dev_caps->common_cap.rxq_first_id;
2070 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
2071 max_mtu = dev_caps->common_cap.max_mtu;
2072 num_funcs = dev_caps->num_funcs;
2074 /* unset dev capabilities */
2075 memset(dev_caps, 0, sizeof(*dev_caps));
2077 /* restore cached values */
2078 dev_caps->common_cap.valid_functions = valid_func;
2079 dev_caps->common_cap.txq_first_id = txq_first_id;
2080 dev_caps->common_cap.rxq_first_id = rxq_first_id;
2081 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2082 dev_caps->common_cap.max_mtu = max_mtu;
2083 dev_caps->num_funcs = num_funcs;
2085 /* one Tx and one Rx queue per function in safe mode */
2086 dev_caps->common_cap.num_rxq = num_funcs;
2087 dev_caps->common_cap.num_txq = num_funcs;
2089 /* two MSIX vectors per function */
2090 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2094 * ice_get_caps - get info about the HW
2095 * @hw: pointer to the hardware structure
2097 enum ice_status ice_get_caps(struct ice_hw *hw)
2099 enum ice_status status;
2101 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2103 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2109 * ice_aq_manage_mac_write - manage MAC address write command
2110 * @hw: pointer to the HW struct
2111 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2112 * @flags: flags to control write behavior
2113 * @cd: pointer to command details structure or NULL
2115 * This function is used to write MAC address to the NVM (0x0108).
2118 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2119 struct ice_sq_cd *cd)
2121 struct ice_aqc_manage_mac_write *cmd;
2122 struct ice_aq_desc desc;
2124 cmd = &desc.params.mac_write;
2125 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2129 /* Prep values for flags, sah, sal */
2130 cmd->sah = HTONS(*((const u16 *)mac_addr));
2131 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
2133 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2137 * ice_aq_clear_pxe_mode
2138 * @hw: pointer to the HW struct
2140 * Tell the firmware that the driver is taking over from PXE (0x0110).
2142 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2144 struct ice_aq_desc desc;
2146 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2147 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2149 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2153 * ice_clear_pxe_mode - clear pxe operations mode
2154 * @hw: pointer to the HW struct
2156 * Make sure all PXE mode settings are cleared, including things
2157 * like descriptor fetch/write-back mode.
2159 void ice_clear_pxe_mode(struct ice_hw *hw)
2161 if (ice_check_sq_alive(hw, &hw->adminq))
2162 ice_aq_clear_pxe_mode(hw);
2166 * ice_get_link_speed_based_on_phy_type - returns link speed
2167 * @phy_type_low: lower part of phy_type
2168 * @phy_type_high: higher part of phy_type
2170 * This helper function will convert an entry in PHY type structure
2171 * [phy_type_low, phy_type_high] to its corresponding link speed.
2172 * Note: In the structure of [phy_type_low, phy_type_high], there should
2173 * be one bit set, as this function will convert one PHY type to its
2175 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2176 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2179 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2181 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2182 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2184 switch (phy_type_low) {
2185 case ICE_PHY_TYPE_LOW_100BASE_TX:
2186 case ICE_PHY_TYPE_LOW_100M_SGMII:
2187 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2189 case ICE_PHY_TYPE_LOW_1000BASE_T:
2190 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2191 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2192 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2193 case ICE_PHY_TYPE_LOW_1G_SGMII:
2194 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2196 case ICE_PHY_TYPE_LOW_2500BASE_T:
2197 case ICE_PHY_TYPE_LOW_2500BASE_X:
2198 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2199 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2201 case ICE_PHY_TYPE_LOW_5GBASE_T:
2202 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2203 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2205 case ICE_PHY_TYPE_LOW_10GBASE_T:
2206 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2207 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2208 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2209 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2210 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2211 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2212 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2214 case ICE_PHY_TYPE_LOW_25GBASE_T:
2215 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2216 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2217 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2218 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2219 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2220 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2221 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2222 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2223 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2224 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2225 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2227 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2228 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2229 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2230 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2231 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2232 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2233 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2235 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2236 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2237 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2238 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2239 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2240 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2241 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2242 case ICE_PHY_TYPE_LOW_50G_AUI2:
2243 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2244 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2245 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2246 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2247 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2248 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2249 case ICE_PHY_TYPE_LOW_50G_AUI1:
2250 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2252 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2253 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2254 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2255 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2256 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2257 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2258 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2259 case ICE_PHY_TYPE_LOW_100G_AUI4:
2260 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2261 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2262 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2263 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2264 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2265 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2268 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2272 switch (phy_type_high) {
2273 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2274 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2275 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2276 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2277 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2278 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2281 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2285 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2286 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2287 return ICE_AQ_LINK_SPEED_UNKNOWN;
2288 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2289 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2290 return ICE_AQ_LINK_SPEED_UNKNOWN;
2291 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2292 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2293 return speed_phy_type_low;
2295 return speed_phy_type_high;
2299 * ice_update_phy_type
2300 * @phy_type_low: pointer to the lower part of phy_type
2301 * @phy_type_high: pointer to the higher part of phy_type
2302 * @link_speeds_bitmap: targeted link speeds bitmap
2304 * Note: For the link_speeds_bitmap structure, you can check it at
2305 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2306 * link_speeds_bitmap include multiple speeds.
2308 * Each entry in this [phy_type_low, phy_type_high] structure will
2309 * present a certain link speed. This helper function will turn on bits
2310 * in [phy_type_low, phy_type_high] structure based on the value of
2311 * link_speeds_bitmap input parameter.
2314 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2315 u16 link_speeds_bitmap)
2322 /* We first check with low part of phy_type */
2323 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2324 pt_low = BIT_ULL(index);
2325 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2327 if (link_speeds_bitmap & speed)
2328 *phy_type_low |= BIT_ULL(index);
2331 /* We then check with high part of phy_type */
2332 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2333 pt_high = BIT_ULL(index);
2334 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2336 if (link_speeds_bitmap & speed)
2337 *phy_type_high |= BIT_ULL(index);
2342 * ice_aq_set_phy_cfg
2343 * @hw: pointer to the HW struct
2344 * @pi: port info structure of the interested logical port
2345 * @cfg: structure with PHY configuration data to be set
2346 * @cd: pointer to command details structure or NULL
2348 * Set the various PHY configuration parameters supported on the Port.
2349 * One or more of the Set PHY config parameters may be ignored in an MFP
2350 * mode as the PF may not have the privilege to set some of the PHY Config
2351 * parameters. This status will be indicated by the command response (0x0601).
2354 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2355 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2357 struct ice_aq_desc desc;
2358 enum ice_status status;
2361 return ICE_ERR_PARAM;
2363 /* Ensure that only valid bits of cfg->caps can be turned on. */
2364 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2365 ice_debug(hw, ICE_DBG_PHY,
2366 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2369 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2372 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2373 desc.params.set_phy.lport_num = pi->lport;
2374 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2376 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2377 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2378 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2379 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2380 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2381 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n",
2382 cfg->low_power_ctrl);
2383 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2384 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2385 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2387 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2390 pi->phy.curr_user_phy_cfg = *cfg;
2396 * ice_update_link_info - update status of the HW network link
2397 * @pi: port info structure of the interested logical port
2399 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2401 struct ice_link_status *li;
2402 enum ice_status status;
2405 return ICE_ERR_PARAM;
2407 li = &pi->phy.link_info;
2409 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2413 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2414 struct ice_aqc_get_phy_caps_data *pcaps;
2418 pcaps = (struct ice_aqc_get_phy_caps_data *)
2419 ice_malloc(hw, sizeof(*pcaps));
2421 return ICE_ERR_NO_MEMORY;
2423 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2425 if (status == ICE_SUCCESS)
2426 ice_memcpy(li->module_type, &pcaps->module_type,
2427 sizeof(li->module_type),
2428 ICE_NONDMA_TO_NONDMA);
2430 ice_free(hw, pcaps);
2437 * ice_cache_phy_user_req
2438 * @pi: port information structure
2439 * @cache_data: PHY logging data
2440 * @cache_mode: PHY logging mode
2442 * Log the user request on (FC, FEC, SPEED) for later user.
2445 ice_cache_phy_user_req(struct ice_port_info *pi,
2446 struct ice_phy_cache_mode_data cache_data,
2447 enum ice_phy_cache_mode cache_mode)
2452 switch (cache_mode) {
2454 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2456 case ICE_SPEED_MODE:
2457 pi->phy.curr_user_speed_req =
2458 cache_data.data.curr_user_speed_req;
2461 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2469 * ice_caps_to_fc_mode
2470 * @caps: PHY capabilities
2472 * Convert PHY FC capabilities to ice FC mode
2474 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2476 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2477 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2480 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2481 return ICE_FC_TX_PAUSE;
2483 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2484 return ICE_FC_RX_PAUSE;
2490 * ice_caps_to_fec_mode
2491 * @caps: PHY capabilities
2492 * @fec_options: Link FEC options
2494 * Convert PHY FEC capabilities to ice FEC mode
2496 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2498 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2499 return ICE_FEC_AUTO;
2501 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2502 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2503 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2504 ICE_AQC_PHY_FEC_25G_KR_REQ))
2505 return ICE_FEC_BASER;
2507 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2508 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2509 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2512 return ICE_FEC_NONE;
2517 * @pi: port information structure
2518 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2519 * @ena_auto_link_update: enable automatic link update
2521 * Set the requested flow control mode.
2524 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2526 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2527 struct ice_phy_cache_mode_data cache_data;
2528 struct ice_aqc_get_phy_caps_data *pcaps;
2529 enum ice_status status;
2530 u8 pause_mask = 0x0;
2534 return ICE_ERR_PARAM;
2536 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2538 /* Cache user FC request */
2539 cache_data.data.curr_user_fc_req = pi->fc.req_mode;
2540 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2542 switch (pi->fc.req_mode) {
2544 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2545 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2547 case ICE_FC_RX_PAUSE:
2548 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2550 case ICE_FC_TX_PAUSE:
2551 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2557 pcaps = (struct ice_aqc_get_phy_caps_data *)
2558 ice_malloc(hw, sizeof(*pcaps));
2560 return ICE_ERR_NO_MEMORY;
2562 /* Get the current PHY config */
2563 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2566 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2570 /* clear the old pause settings */
2571 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2572 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2574 /* set the new capabilities */
2575 cfg.caps |= pause_mask;
2577 /* If the capabilities have changed, then set the new config */
2578 if (cfg.caps != pcaps->caps) {
2579 int retry_count, retry_max = 10;
2581 /* Auto restart link so settings take effect */
2582 if (ena_auto_link_update)
2583 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2584 /* Copy over all the old settings */
2585 cfg.phy_type_high = pcaps->phy_type_high;
2586 cfg.phy_type_low = pcaps->phy_type_low;
2587 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2588 cfg.eee_cap = pcaps->eee_cap;
2589 cfg.eeer_value = pcaps->eeer_value;
2590 cfg.link_fec_opt = pcaps->link_fec_options;
2592 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2594 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2598 /* Update the link info
2599 * It sometimes takes a really long time for link to
2600 * come back from the atomic reset. Thus, we wait a
2603 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2604 status = ice_update_link_info(pi);
2606 if (status == ICE_SUCCESS)
2609 ice_msec_delay(100, true);
2613 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2617 ice_free(hw, pcaps);
2622 * ice_phy_caps_equals_cfg
2623 * @phy_caps: PHY capabilities
2624 * @phy_cfg: PHY configuration
2626 * Helper function to determine if PHY capabilities matches PHY
2630 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2631 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2633 u8 caps_mask, cfg_mask;
2635 if (!phy_caps || !phy_cfg)
2638 /* These bits are not common between capabilities and configuration.
2639 * Do not use them to determine equality.
2641 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2642 ICE_AQC_PHY_EN_MOD_QUAL);
2643 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2645 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2646 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2647 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2648 phy_caps->low_power_ctrl != phy_cfg->low_power_ctrl ||
2649 phy_caps->eee_cap != phy_cfg->eee_cap ||
2650 phy_caps->eeer_value != phy_cfg->eeer_value ||
2651 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2658 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2659 * @caps: PHY ability structure to copy date from
2660 * @cfg: PHY configuration structure to copy data to
2662 * Helper function to copy AQC PHY get ability data to PHY set configuration
2666 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2667 struct ice_aqc_set_phy_cfg_data *cfg)
2672 cfg->phy_type_low = caps->phy_type_low;
2673 cfg->phy_type_high = caps->phy_type_high;
2674 cfg->caps = caps->caps;
2675 cfg->low_power_ctrl = caps->low_power_ctrl;
2676 cfg->eee_cap = caps->eee_cap;
2677 cfg->eeer_value = caps->eeer_value;
2678 cfg->link_fec_opt = caps->link_fec_options;
2682 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2683 * @cfg: PHY configuration data to set FEC mode
2684 * @fec: FEC mode to configure
2686 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2687 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2688 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2691 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2695 /* Clear RS bits, and AND BASE-R ability
2696 * bits and OR request bits.
2698 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2699 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2700 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2701 ICE_AQC_PHY_FEC_25G_KR_REQ;
2704 /* Clear BASE-R bits, and AND RS ability
2705 * bits and OR request bits.
2707 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2708 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2709 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2712 /* Clear all FEC option bits. */
2713 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2716 /* AND auto FEC bit, and all caps bits. */
2717 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2723 * ice_get_link_status - get status of the HW network link
2724 * @pi: port information structure
2725 * @link_up: pointer to bool (true/false = linkup/linkdown)
2727 * Variable link_up is true if link is up, false if link is down.
2728 * The variable link_up is invalid if status is non zero. As a
2729 * result of this call, link status reporting becomes enabled
2731 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2733 struct ice_phy_info *phy_info;
2734 enum ice_status status = ICE_SUCCESS;
2736 if (!pi || !link_up)
2737 return ICE_ERR_PARAM;
2739 phy_info = &pi->phy;
2741 if (phy_info->get_link_info) {
2742 status = ice_update_link_info(pi);
2745 ice_debug(pi->hw, ICE_DBG_LINK,
2746 "get link status error, status = %d\n",
2750 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2756 * ice_aq_set_link_restart_an
2757 * @pi: pointer to the port information structure
2758 * @ena_link: if true: enable link, if false: disable link
2759 * @cd: pointer to command details structure or NULL
2761 * Sets up the link and restarts the Auto-Negotiation over the link.
2764 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2765 struct ice_sq_cd *cd)
2767 struct ice_aqc_restart_an *cmd;
2768 struct ice_aq_desc desc;
2770 cmd = &desc.params.restart_an;
2772 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2774 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2775 cmd->lport_num = pi->lport;
2777 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2779 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2781 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2785 * ice_aq_set_event_mask
2786 * @hw: pointer to the HW struct
2787 * @port_num: port number of the physical function
2788 * @mask: event mask to be set
2789 * @cd: pointer to command details structure or NULL
2791 * Set event mask (0x0613)
2794 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2795 struct ice_sq_cd *cd)
2797 struct ice_aqc_set_event_mask *cmd;
2798 struct ice_aq_desc desc;
2800 cmd = &desc.params.set_event_mask;
2802 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2804 cmd->lport_num = port_num;
2806 cmd->event_mask = CPU_TO_LE16(mask);
2807 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2811 * ice_aq_set_mac_loopback
2812 * @hw: pointer to the HW struct
2813 * @ena_lpbk: Enable or Disable loopback
2814 * @cd: pointer to command details structure or NULL
2816 * Enable/disable loopback on a given port
2819 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2821 struct ice_aqc_set_mac_lb *cmd;
2822 struct ice_aq_desc desc;
2824 cmd = &desc.params.set_mac_lb;
2826 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2828 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2830 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2834 * ice_aq_set_port_id_led
2835 * @pi: pointer to the port information
2836 * @is_orig_mode: is this LED set to original mode (by the net-list)
2837 * @cd: pointer to command details structure or NULL
2839 * Set LED value for the given port (0x06e9)
2842 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2843 struct ice_sq_cd *cd)
2845 struct ice_aqc_set_port_id_led *cmd;
2846 struct ice_hw *hw = pi->hw;
2847 struct ice_aq_desc desc;
2849 cmd = &desc.params.set_port_id_led;
2851 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2854 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2856 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2858 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2863 * @hw: pointer to the HW struct
2864 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
2865 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
2866 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
2868 * @set_page: set or ignore the page
2869 * @data: pointer to data buffer to be read/written to the I2C device.
2870 * @length: 1-16 for read, 1 for write.
2871 * @write: 0 read, 1 for write.
2872 * @cd: pointer to command details structure or NULL
2874 * Read/Write SFF EEPROM (0x06EE)
2877 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
2878 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
2879 bool write, struct ice_sq_cd *cd)
2881 struct ice_aqc_sff_eeprom *cmd;
2882 struct ice_aq_desc desc;
2883 enum ice_status status;
2885 if (!data || (mem_addr & 0xff00))
2886 return ICE_ERR_PARAM;
2888 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
2889 cmd = &desc.params.read_write_sff_param;
2890 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
2891 cmd->lport_num = (u8)(lport & 0xff);
2892 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
2893 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
2894 ICE_AQC_SFF_I2CBUS_7BIT_M) |
2896 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
2897 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
2898 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
2899 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
2901 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
2903 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
2908 * __ice_aq_get_set_rss_lut
2909 * @hw: pointer to the hardware structure
2910 * @vsi_id: VSI FW index
2911 * @lut_type: LUT table type
2912 * @lut: pointer to the LUT buffer provided by the caller
2913 * @lut_size: size of the LUT buffer
2914 * @glob_lut_idx: global LUT index
2915 * @set: set true to set the table, false to get the table
2917 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2919 static enum ice_status
2920 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2921 u16 lut_size, u8 glob_lut_idx, bool set)
2923 struct ice_aqc_get_set_rss_lut *cmd_resp;
2924 struct ice_aq_desc desc;
2925 enum ice_status status;
2928 cmd_resp = &desc.params.get_set_rss_lut;
2931 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2932 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2934 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2937 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2938 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2939 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2940 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2943 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2944 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2945 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2946 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2947 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2950 status = ICE_ERR_PARAM;
2951 goto ice_aq_get_set_rss_lut_exit;
2954 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2955 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2956 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2959 goto ice_aq_get_set_rss_lut_send;
2960 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2962 goto ice_aq_get_set_rss_lut_send;
2964 goto ice_aq_get_set_rss_lut_send;
2967 /* LUT size is only valid for Global and PF table types */
2969 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2970 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
2971 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2972 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2974 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
2975 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2976 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2977 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2979 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
2980 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2981 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
2982 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2983 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2988 status = ICE_ERR_PARAM;
2989 goto ice_aq_get_set_rss_lut_exit;
2992 ice_aq_get_set_rss_lut_send:
2993 cmd_resp->flags = CPU_TO_LE16(flags);
2994 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
2996 ice_aq_get_set_rss_lut_exit:
3001 * ice_aq_get_rss_lut
3002 * @hw: pointer to the hardware structure
3003 * @vsi_handle: software VSI handle
3004 * @lut_type: LUT table type
3005 * @lut: pointer to the LUT buffer provided by the caller
3006 * @lut_size: size of the LUT buffer
3008 * get the RSS lookup table, PF or VSI type
3011 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3012 u8 *lut, u16 lut_size)
3014 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3015 return ICE_ERR_PARAM;
3017 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3018 lut_type, lut, lut_size, 0, false);
3022 * ice_aq_set_rss_lut
3023 * @hw: pointer to the hardware structure
3024 * @vsi_handle: software VSI handle
3025 * @lut_type: LUT table type
3026 * @lut: pointer to the LUT buffer provided by the caller
3027 * @lut_size: size of the LUT buffer
3029 * set the RSS lookup table, PF or VSI type
3032 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3033 u8 *lut, u16 lut_size)
3035 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3036 return ICE_ERR_PARAM;
3038 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3039 lut_type, lut, lut_size, 0, true);
3043 * __ice_aq_get_set_rss_key
3044 * @hw: pointer to the HW struct
3045 * @vsi_id: VSI FW index
3046 * @key: pointer to key info struct
3047 * @set: set true to set the key, false to get the key
3049 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3052 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3053 struct ice_aqc_get_set_rss_keys *key,
3056 struct ice_aqc_get_set_rss_key *cmd_resp;
3057 u16 key_size = sizeof(*key);
3058 struct ice_aq_desc desc;
3060 cmd_resp = &desc.params.get_set_rss_key;
3063 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3064 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3066 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3069 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3070 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3071 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3072 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3074 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3078 * ice_aq_get_rss_key
3079 * @hw: pointer to the HW struct
3080 * @vsi_handle: software VSI handle
3081 * @key: pointer to key info struct
3083 * get the RSS key per VSI
3086 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3087 struct ice_aqc_get_set_rss_keys *key)
3089 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3090 return ICE_ERR_PARAM;
3092 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3097 * ice_aq_set_rss_key
3098 * @hw: pointer to the HW struct
3099 * @vsi_handle: software VSI handle
3100 * @keys: pointer to key info struct
3102 * set the RSS key per VSI
3105 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3106 struct ice_aqc_get_set_rss_keys *keys)
3108 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3109 return ICE_ERR_PARAM;
3111 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3116 * ice_aq_add_lan_txq
3117 * @hw: pointer to the hardware structure
3118 * @num_qgrps: Number of added queue groups
3119 * @qg_list: list of queue groups to be added
3120 * @buf_size: size of buffer for indirect command
3121 * @cd: pointer to command details structure or NULL
3123 * Add Tx LAN queue (0x0C30)
3126 * Prior to calling add Tx LAN queue:
3127 * Initialize the following as part of the Tx queue context:
3128 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3129 * Cache profile and Packet shaper profile.
3131 * After add Tx LAN queue AQ command is completed:
3132 * Interrupts should be associated with specific queues,
3133 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3137 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3138 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3139 struct ice_sq_cd *cd)
3141 u16 i, sum_header_size, sum_q_size = 0;
3142 struct ice_aqc_add_tx_qgrp *list;
3143 struct ice_aqc_add_txqs *cmd;
3144 struct ice_aq_desc desc;
3146 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3148 cmd = &desc.params.add_txqs;
3150 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3153 return ICE_ERR_PARAM;
3155 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3156 return ICE_ERR_PARAM;
3158 sum_header_size = num_qgrps *
3159 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3162 for (i = 0; i < num_qgrps; i++) {
3163 struct ice_aqc_add_txqs_perq *q = list->txqs;
3165 sum_q_size += list->num_txqs * sizeof(*q);
3166 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3169 if (buf_size != (sum_header_size + sum_q_size))
3170 return ICE_ERR_PARAM;
3172 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3174 cmd->num_qgrps = num_qgrps;
3176 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3180 * ice_aq_dis_lan_txq
3181 * @hw: pointer to the hardware structure
3182 * @num_qgrps: number of groups in the list
3183 * @qg_list: the list of groups to disable
3184 * @buf_size: the total size of the qg_list buffer in bytes
3185 * @rst_src: if called due to reset, specifies the reset source
3186 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3187 * @cd: pointer to command details structure or NULL
3189 * Disable LAN Tx queue (0x0C31)
3191 static enum ice_status
3192 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3193 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3194 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3195 struct ice_sq_cd *cd)
3197 struct ice_aqc_dis_txqs *cmd;
3198 struct ice_aq_desc desc;
3199 enum ice_status status;
3202 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3203 cmd = &desc.params.dis_txqs;
3204 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3206 /* qg_list can be NULL only in VM/VF reset flow */
3207 if (!qg_list && !rst_src)
3208 return ICE_ERR_PARAM;
3210 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3211 return ICE_ERR_PARAM;
3213 cmd->num_entries = num_qgrps;
3215 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3216 ICE_AQC_Q_DIS_TIMEOUT_M);
3220 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3221 cmd->vmvf_and_timeout |=
3222 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3229 /* flush pipe on time out */
3230 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3231 /* If no queue group info, we are in a reset flow. Issue the AQ */
3235 /* set RD bit to indicate that command buffer is provided by the driver
3236 * and it needs to be read by the firmware
3238 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3240 for (i = 0; i < num_qgrps; ++i) {
3241 /* Calculate the size taken up by the queue IDs in this group */
3242 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3244 /* Add the size of the group header */
3245 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3247 /* If the num of queues is even, add 2 bytes of padding */
3248 if ((qg_list[i].num_qs % 2) == 0)
3253 return ICE_ERR_PARAM;
3256 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3259 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3260 vmvf_num, hw->adminq.sq_last_status);
3262 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3263 LE16_TO_CPU(qg_list[0].q_id[0]),
3264 hw->adminq.sq_last_status);
3270 * ice_aq_move_recfg_lan_txq
3271 * @hw: pointer to the hardware structure
3272 * @num_qs: number of queues to move/reconfigure
3273 * @is_move: true if this operation involves node movement
3274 * @is_tc_change: true if this operation involves a TC change
3275 * @subseq_call: true if this operation is a subsequent call
3276 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3277 * @timeout: timeout in units of 100 usec (valid values 0-50)
3278 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3279 * @buf: struct containing src/dest TEID and per-queue info
3280 * @buf_size: size of buffer for indirect command
3281 * @txqs_moved: out param, number of queues successfully moved
3282 * @cd: pointer to command details structure or NULL
3284 * Move / Reconfigure Tx LAN queues (0x0C32)
3287 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3288 bool is_tc_change, bool subseq_call, bool flush_pipe,
3289 u8 timeout, u32 *blocked_cgds,
3290 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3291 u8 *txqs_moved, struct ice_sq_cd *cd)
3293 struct ice_aqc_move_txqs *cmd;
3294 struct ice_aq_desc desc;
3295 enum ice_status status;
3297 cmd = &desc.params.move_txqs;
3298 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3300 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3301 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3302 return ICE_ERR_PARAM;
3304 if (is_tc_change && !flush_pipe && !blocked_cgds)
3305 return ICE_ERR_PARAM;
3307 if (!is_move && !is_tc_change)
3308 return ICE_ERR_PARAM;
3310 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3313 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3316 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3319 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3322 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3324 cmd->num_qs = num_qs;
3325 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3326 ICE_AQC_Q_CMD_TIMEOUT_M);
3328 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3330 if (!status && txqs_moved)
3331 *txqs_moved = cmd->num_qs;
3333 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3334 is_tc_change && !flush_pipe)
3335 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3340 /* End of FW Admin Queue command wrappers */
3343 * ice_write_byte - write a byte to a packed context structure
3344 * @src_ctx: the context structure to read from
3345 * @dest_ctx: the context to be written to
3346 * @ce_info: a description of the struct to be filled
3349 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3351 u8 src_byte, dest_byte, mask;
3355 /* copy from the next struct field */
3356 from = src_ctx + ce_info->offset;
3358 /* prepare the bits and mask */
3359 shift_width = ce_info->lsb % 8;
3360 mask = (u8)(BIT(ce_info->width) - 1);
3365 /* shift to correct alignment */
3366 mask <<= shift_width;
3367 src_byte <<= shift_width;
3369 /* get the current bits from the target bit string */
3370 dest = dest_ctx + (ce_info->lsb / 8);
3372 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3374 dest_byte &= ~mask; /* get the bits not changing */
3375 dest_byte |= src_byte; /* add in the new bits */
3377 /* put it all back */
3378 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3382 * ice_write_word - write a word to a packed context structure
3383 * @src_ctx: the context structure to read from
3384 * @dest_ctx: the context to be written to
3385 * @ce_info: a description of the struct to be filled
3388 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3395 /* copy from the next struct field */
3396 from = src_ctx + ce_info->offset;
3398 /* prepare the bits and mask */
3399 shift_width = ce_info->lsb % 8;
3400 mask = BIT(ce_info->width) - 1;
3402 /* don't swizzle the bits until after the mask because the mask bits
3403 * will be in a different bit position on big endian machines
3405 src_word = *(u16 *)from;
3408 /* shift to correct alignment */
3409 mask <<= shift_width;
3410 src_word <<= shift_width;
3412 /* get the current bits from the target bit string */
3413 dest = dest_ctx + (ce_info->lsb / 8);
3415 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3417 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3418 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3420 /* put it all back */
3421 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3425 * ice_write_dword - write a dword to a packed context structure
3426 * @src_ctx: the context structure to read from
3427 * @dest_ctx: the context to be written to
3428 * @ce_info: a description of the struct to be filled
3431 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3433 u32 src_dword, mask;
3438 /* copy from the next struct field */
3439 from = src_ctx + ce_info->offset;
3441 /* prepare the bits and mask */
3442 shift_width = ce_info->lsb % 8;
3444 /* if the field width is exactly 32 on an x86 machine, then the shift
3445 * operation will not work because the SHL instructions count is masked
3446 * to 5 bits so the shift will do nothing
3448 if (ce_info->width < 32)
3449 mask = BIT(ce_info->width) - 1;
3453 /* don't swizzle the bits until after the mask because the mask bits
3454 * will be in a different bit position on big endian machines
3456 src_dword = *(u32 *)from;
3459 /* shift to correct alignment */
3460 mask <<= shift_width;
3461 src_dword <<= shift_width;
3463 /* get the current bits from the target bit string */
3464 dest = dest_ctx + (ce_info->lsb / 8);
3466 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3468 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3469 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3471 /* put it all back */
3472 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3476 * ice_write_qword - write a qword to a packed context structure
3477 * @src_ctx: the context structure to read from
3478 * @dest_ctx: the context to be written to
3479 * @ce_info: a description of the struct to be filled
3482 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3484 u64 src_qword, mask;
3489 /* copy from the next struct field */
3490 from = src_ctx + ce_info->offset;
3492 /* prepare the bits and mask */
3493 shift_width = ce_info->lsb % 8;
3495 /* if the field width is exactly 64 on an x86 machine, then the shift
3496 * operation will not work because the SHL instructions count is masked
3497 * to 6 bits so the shift will do nothing
3499 if (ce_info->width < 64)
3500 mask = BIT_ULL(ce_info->width) - 1;
3504 /* don't swizzle the bits until after the mask because the mask bits
3505 * will be in a different bit position on big endian machines
3507 src_qword = *(u64 *)from;
3510 /* shift to correct alignment */
3511 mask <<= shift_width;
3512 src_qword <<= shift_width;
3514 /* get the current bits from the target bit string */
3515 dest = dest_ctx + (ce_info->lsb / 8);
3517 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3519 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3520 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3522 /* put it all back */
3523 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3527 * ice_set_ctx - set context bits in packed structure
3528 * @src_ctx: pointer to a generic non-packed context structure
3529 * @dest_ctx: pointer to memory for the packed structure
3530 * @ce_info: a description of the structure to be transformed
3533 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3537 for (f = 0; ce_info[f].width; f++) {
3538 /* We have to deal with each element of the FW response
3539 * using the correct size so that we are correct regardless
3540 * of the endianness of the machine.
3542 switch (ce_info[f].size_of) {
3544 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3547 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3550 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3553 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3556 return ICE_ERR_INVAL_SIZE;
3564 * ice_read_byte - read context byte into struct
3565 * @src_ctx: the context structure to read from
3566 * @dest_ctx: the context to be written to
3567 * @ce_info: a description of the struct to be filled
3570 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3576 /* prepare the bits and mask */
3577 shift_width = ce_info->lsb % 8;
3578 mask = (u8)(BIT(ce_info->width) - 1);
3580 /* shift to correct alignment */
3581 mask <<= shift_width;
3583 /* get the current bits from the src bit string */
3584 src = src_ctx + (ce_info->lsb / 8);
3586 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3588 dest_byte &= ~(mask);
3590 dest_byte >>= shift_width;
3592 /* get the address from the struct field */
3593 target = dest_ctx + ce_info->offset;
3595 /* put it back in the struct */
3596 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3600 * ice_read_word - read context word into struct
3601 * @src_ctx: the context structure to read from
3602 * @dest_ctx: the context to be written to
3603 * @ce_info: a description of the struct to be filled
3606 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3608 u16 dest_word, mask;
3613 /* prepare the bits and mask */
3614 shift_width = ce_info->lsb % 8;
3615 mask = BIT(ce_info->width) - 1;
3617 /* shift to correct alignment */
3618 mask <<= shift_width;
3620 /* get the current bits from the src bit string */
3621 src = src_ctx + (ce_info->lsb / 8);
3623 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3625 /* the data in the memory is stored as little endian so mask it
3628 src_word &= ~(CPU_TO_LE16(mask));
3630 /* get the data back into host order before shifting */
3631 dest_word = LE16_TO_CPU(src_word);
3633 dest_word >>= shift_width;
3635 /* get the address from the struct field */
3636 target = dest_ctx + ce_info->offset;
3638 /* put it back in the struct */
3639 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3643 * ice_read_dword - read context dword into struct
3644 * @src_ctx: the context structure to read from
3645 * @dest_ctx: the context to be written to
3646 * @ce_info: a description of the struct to be filled
3649 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3651 u32 dest_dword, mask;
3656 /* prepare the bits and mask */
3657 shift_width = ce_info->lsb % 8;
3659 /* if the field width is exactly 32 on an x86 machine, then the shift
3660 * operation will not work because the SHL instructions count is masked
3661 * to 5 bits so the shift will do nothing
3663 if (ce_info->width < 32)
3664 mask = BIT(ce_info->width) - 1;
3668 /* shift to correct alignment */
3669 mask <<= shift_width;
3671 /* get the current bits from the src bit string */
3672 src = src_ctx + (ce_info->lsb / 8);
3674 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3676 /* the data in the memory is stored as little endian so mask it
3679 src_dword &= ~(CPU_TO_LE32(mask));
3681 /* get the data back into host order before shifting */
3682 dest_dword = LE32_TO_CPU(src_dword);
3684 dest_dword >>= shift_width;
3686 /* get the address from the struct field */
3687 target = dest_ctx + ce_info->offset;
3689 /* put it back in the struct */
3690 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3694 * ice_read_qword - read context qword into struct
3695 * @src_ctx: the context structure to read from
3696 * @dest_ctx: the context to be written to
3697 * @ce_info: a description of the struct to be filled
3700 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3702 u64 dest_qword, mask;
3707 /* prepare the bits and mask */
3708 shift_width = ce_info->lsb % 8;
3710 /* if the field width is exactly 64 on an x86 machine, then the shift
3711 * operation will not work because the SHL instructions count is masked
3712 * to 6 bits so the shift will do nothing
3714 if (ce_info->width < 64)
3715 mask = BIT_ULL(ce_info->width) - 1;
3719 /* shift to correct alignment */
3720 mask <<= shift_width;
3722 /* get the current bits from the src bit string */
3723 src = src_ctx + (ce_info->lsb / 8);
3725 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3727 /* the data in the memory is stored as little endian so mask it
3730 src_qword &= ~(CPU_TO_LE64(mask));
3732 /* get the data back into host order before shifting */
3733 dest_qword = LE64_TO_CPU(src_qword);
3735 dest_qword >>= shift_width;
3737 /* get the address from the struct field */
3738 target = dest_ctx + ce_info->offset;
3740 /* put it back in the struct */
3741 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3745 * ice_get_ctx - extract context bits from a packed structure
3746 * @src_ctx: pointer to a generic packed context structure
3747 * @dest_ctx: pointer to a generic non-packed context structure
3748 * @ce_info: a description of the structure to be read from
3751 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3755 for (f = 0; ce_info[f].width; f++) {
3756 switch (ce_info[f].size_of) {
3758 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3761 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3764 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3767 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3770 /* nothing to do, just keep going */
3779 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3780 * @hw: pointer to the HW struct
3781 * @vsi_handle: software VSI handle
3783 * @q_handle: software queue handle
3786 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3788 struct ice_vsi_ctx *vsi;
3789 struct ice_q_ctx *q_ctx;
3791 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3794 if (q_handle >= vsi->num_lan_q_entries[tc])
3796 if (!vsi->lan_q_ctx[tc])
3798 q_ctx = vsi->lan_q_ctx[tc];
3799 return &q_ctx[q_handle];
3804 * @pi: port information structure
3805 * @vsi_handle: software VSI handle
3807 * @q_handle: software queue handle
3808 * @num_qgrps: Number of added queue groups
3809 * @buf: list of queue groups to be added
3810 * @buf_size: size of buffer for indirect command
3811 * @cd: pointer to command details structure or NULL
3813 * This function adds one LAN queue
3816 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3817 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3818 struct ice_sq_cd *cd)
3820 struct ice_aqc_txsched_elem_data node = { 0 };
3821 struct ice_sched_node *parent;
3822 struct ice_q_ctx *q_ctx;
3823 enum ice_status status;
3826 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3829 if (num_qgrps > 1 || buf->num_txqs > 1)
3830 return ICE_ERR_MAX_LIMIT;
3834 if (!ice_is_vsi_valid(hw, vsi_handle))
3835 return ICE_ERR_PARAM;
3837 ice_acquire_lock(&pi->sched_lock);
3839 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3841 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3843 status = ICE_ERR_PARAM;
3847 /* find a parent node */
3848 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3849 ICE_SCHED_NODE_OWNER_LAN);
3851 status = ICE_ERR_PARAM;
3855 buf->parent_teid = parent->info.node_teid;
3856 node.parent_teid = parent->info.node_teid;
3857 /* Mark that the values in the "generic" section as valid. The default
3858 * value in the "generic" section is zero. This means that :
3859 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3860 * - 0 priority among siblings, indicated by Bit 1-3.
3861 * - WFQ, indicated by Bit 4.
3862 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3864 * - Bit 7 is reserved.
3865 * Without setting the generic section as valid in valid_sections, the
3866 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3868 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3870 /* add the LAN queue */
3871 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3872 if (status != ICE_SUCCESS) {
3873 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3874 LE16_TO_CPU(buf->txqs[0].txq_id),
3875 hw->adminq.sq_last_status);
3879 node.node_teid = buf->txqs[0].q_teid;
3880 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3881 q_ctx->q_handle = q_handle;
3882 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
3884 /* add a leaf node into scheduler tree queue layer */
3885 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3887 status = ice_sched_replay_q_bw(pi, q_ctx);
3890 ice_release_lock(&pi->sched_lock);
3896 * @pi: port information structure
3897 * @vsi_handle: software VSI handle
3899 * @num_queues: number of queues
3900 * @q_handles: pointer to software queue handle array
3901 * @q_ids: pointer to the q_id array
3902 * @q_teids: pointer to queue node teids
3903 * @rst_src: if called due to reset, specifies the reset source
3904 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3905 * @cd: pointer to command details structure or NULL
3907 * This function removes queues and their corresponding nodes in SW DB
3910 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3911 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3912 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3913 struct ice_sq_cd *cd)
3915 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3916 struct ice_aqc_dis_txq_item qg_list;
3917 struct ice_q_ctx *q_ctx;
3920 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3924 /* if queue is disabled already yet the disable queue command
3925 * has to be sent to complete the VF reset, then call
3926 * ice_aq_dis_lan_txq without any queue information
3929 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
3934 ice_acquire_lock(&pi->sched_lock);
3936 for (i = 0; i < num_queues; i++) {
3937 struct ice_sched_node *node;
3939 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3942 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3944 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3948 if (q_ctx->q_handle != q_handles[i]) {
3949 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3950 q_ctx->q_handle, q_handles[i]);
3953 qg_list.parent_teid = node->info.parent_teid;
3955 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
3956 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3957 sizeof(qg_list), rst_src, vmvf_num,
3960 if (status != ICE_SUCCESS)
3962 ice_free_sched_node(pi, node);
3963 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
3965 ice_release_lock(&pi->sched_lock);
3970 * ice_cfg_vsi_qs - configure the new/existing VSI queues
3971 * @pi: port information structure
3972 * @vsi_handle: software VSI handle
3973 * @tc_bitmap: TC bitmap
3974 * @maxqs: max queues array per TC
3975 * @owner: LAN or RDMA
3977 * This function adds/updates the VSI queues per TC.
3979 static enum ice_status
3980 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3981 u16 *maxqs, u8 owner)
3983 enum ice_status status = ICE_SUCCESS;
3986 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3989 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3990 return ICE_ERR_PARAM;
3992 ice_acquire_lock(&pi->sched_lock);
3994 ice_for_each_traffic_class(i) {
3995 /* configuration is possible only if TC node is present */
3996 if (!ice_sched_get_tc_node(pi, i))
3999 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4000 ice_is_tc_ena(tc_bitmap, i));
4005 ice_release_lock(&pi->sched_lock);
4010 * ice_cfg_vsi_lan - configure VSI LAN queues
4011 * @pi: port information structure
4012 * @vsi_handle: software VSI handle
4013 * @tc_bitmap: TC bitmap
4014 * @max_lanqs: max LAN queues array per TC
4016 * This function adds/updates the VSI LAN queues per TC.
4019 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4022 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4023 ICE_SCHED_NODE_OWNER_LAN);
4027 * ice_replay_pre_init - replay pre initialization
4028 * @hw: pointer to the HW struct
4030 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4032 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
4034 struct ice_switch_info *sw = hw->switch_info;
4037 /* Delete old entries from replay filter list head if there is any */
4038 ice_rm_all_sw_replay_rule_info(hw);
4039 /* In start of replay, move entries into replay_rules list, it
4040 * will allow adding rules entries back to filt_rules list,
4041 * which is operational list.
4043 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4044 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4045 &sw->recp_list[i].filt_replay_rules);
4046 ice_sched_replay_agg_vsi_preinit(hw);
4048 return ice_sched_replay_tc_node_bw(hw->port_info);
4052 * ice_replay_vsi - replay VSI configuration
4053 * @hw: pointer to the HW struct
4054 * @vsi_handle: driver VSI handle
4056 * Restore all VSI configuration after reset. It is required to call this
4057 * function with main VSI first.
4059 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4061 enum ice_status status;
4063 if (!ice_is_vsi_valid(hw, vsi_handle))
4064 return ICE_ERR_PARAM;
4066 /* Replay pre-initialization if there is any */
4067 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
4068 status = ice_replay_pre_init(hw);
4072 /* Replay per VSI all RSS configurations */
4073 status = ice_replay_rss_cfg(hw, vsi_handle);
4076 /* Replay per VSI all filters */
4077 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
4079 status = ice_replay_vsi_agg(hw, vsi_handle);
4084 * ice_replay_post - post replay configuration cleanup
4085 * @hw: pointer to the HW struct
4087 * Post replay cleanup.
4089 void ice_replay_post(struct ice_hw *hw)
4091 /* Delete old entries from replay filter list head */
4092 ice_rm_all_sw_replay_rule_info(hw);
4093 ice_sched_replay_agg(hw);
4097 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4098 * @hw: ptr to the hardware info
4099 * @reg: offset of 64 bit HW register to read from
4100 * @prev_stat_loaded: bool to specify if previous stats are loaded
4101 * @prev_stat: ptr to previous loaded stat value
4102 * @cur_stat: ptr to current stat value
4105 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4106 u64 *prev_stat, u64 *cur_stat)
4108 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4110 /* device stats are not reset at PFR, they likely will not be zeroed
4111 * when the driver starts. Thus, save the value from the first read
4112 * without adding to the statistic value so that we report stats which
4113 * count up from zero.
4115 if (!prev_stat_loaded) {
4116 *prev_stat = new_data;
4120 /* Calculate the difference between the new and old values, and then
4121 * add it to the software stat value.
4123 if (new_data >= *prev_stat)
4124 *cur_stat += new_data - *prev_stat;
4126 /* to manage the potential roll-over */
4127 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4129 /* Update the previously stored value to prepare for next read */
4130 *prev_stat = new_data;
4134 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4135 * @hw: ptr to the hardware info
4136 * @reg: offset of HW register to read from
4137 * @prev_stat_loaded: bool to specify if previous stats are loaded
4138 * @prev_stat: ptr to previous loaded stat value
4139 * @cur_stat: ptr to current stat value
4142 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4143 u64 *prev_stat, u64 *cur_stat)
4147 new_data = rd32(hw, reg);
4149 /* device stats are not reset at PFR, they likely will not be zeroed
4150 * when the driver starts. Thus, save the value from the first read
4151 * without adding to the statistic value so that we report stats which
4152 * count up from zero.
4154 if (!prev_stat_loaded) {
4155 *prev_stat = new_data;
4159 /* Calculate the difference between the new and old values, and then
4160 * add it to the software stat value.
4162 if (new_data >= *prev_stat)
4163 *cur_stat += new_data - *prev_stat;
4165 /* to manage the potential roll-over */
4166 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4168 /* Update the previously stored value to prepare for next read */
4169 *prev_stat = new_data;
4173 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4174 * @hw: ptr to the hardware info
4175 * @vsi_handle: VSI handle
4176 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4177 * @cur_stats: ptr to current stats structure
4179 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4180 * thus cannot be read using the normal ice_stat_update32 function.
4182 * Read the GLV_REPC register associated with the given VSI, and update the
4183 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4185 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4186 * cleared each time it's read.
4188 * Note that the GLV_RDPC register also counts the causes that would trigger
4189 * GLV_REPC. However, it does not give the finer grained detail about why the
4190 * packets are being dropped. The GLV_REPC values can be used to distinguish
4191 * whether Rx packets are dropped due to errors or due to no available
4195 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4196 struct ice_eth_stats *cur_stats)
4198 u16 vsi_num, no_desc, error_cnt;
4201 if (!ice_is_vsi_valid(hw, vsi_handle))
4204 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4206 /* If we haven't loaded stats yet, just clear the current value */
4207 if (!prev_stat_loaded) {
4208 wr32(hw, GLV_REPC(vsi_num), 0);
4212 repc = rd32(hw, GLV_REPC(vsi_num));
4213 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4214 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4216 /* Clear the count by writing to the stats register */
4217 wr32(hw, GLV_REPC(vsi_num), 0);
4219 cur_stats->rx_no_desc += no_desc;
4220 cur_stats->rx_errors += error_cnt;
4224 * ice_sched_query_elem - query element information from HW
4225 * @hw: pointer to the HW struct
4226 * @node_teid: node TEID to be queried
4227 * @buf: buffer to element information
4229 * This function queries HW element information
4232 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4233 struct ice_aqc_get_elem *buf)
4235 u16 buf_size, num_elem_ret = 0;
4236 enum ice_status status;
4238 buf_size = sizeof(*buf);
4239 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4240 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4241 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4243 if (status != ICE_SUCCESS || num_elem_ret != 1)
4244 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4249 * ice_get_fw_mode - returns FW mode
4250 * @hw: pointer to the HW struct
4252 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4254 #define ICE_FW_MODE_DBG_M BIT(0)
4255 #define ICE_FW_MODE_REC_M BIT(1)
4256 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4259 /* check the current FW mode */
4260 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4262 if (fw_mode & ICE_FW_MODE_DBG_M)
4263 return ICE_FW_MODE_DBG;
4264 else if (fw_mode & ICE_FW_MODE_REC_M)
4265 return ICE_FW_MODE_REC;
4266 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4267 return ICE_FW_MODE_ROLLBACK;
4269 return ICE_FW_MODE_NORMAL;