1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 200
14 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
15 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
16 ((ICE_RX_OPC_MDID << \
17 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
18 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
19 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
20 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
22 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
23 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
24 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
26 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
28 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
29 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
30 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
31 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
35 * ice_set_mac_type - Sets MAC type
36 * @hw: pointer to the HW structure
38 * This function sets the MAC type of the adapter based on the
39 * vendor ID and device ID stored in the HW structure.
41 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
43 enum ice_status status = ICE_SUCCESS;
45 ice_debug(hw, ICE_DBG_TRACE, "ice_set_mac_type\n");
47 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) {
48 switch (hw->device_id) {
50 hw->mac_type = ICE_MAC_GENERIC;
54 status = ICE_ERR_DEVICE_NOT_SUPPORTED;
57 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n",
58 hw->mac_type, status);
65 * ice_clear_pf_cfg - Clear PF configuration
66 * @hw: pointer to the hardware structure
68 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
69 * configuration, flow director filters, etc.).
71 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
73 struct ice_aq_desc desc;
75 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
77 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
81 * ice_aq_manage_mac_read - manage MAC address read command
82 * @hw: pointer to the HW struct
83 * @buf: a virtual buffer to hold the manage MAC read response
84 * @buf_size: Size of the virtual buffer
85 * @cd: pointer to command details structure or NULL
87 * This function is used to return per PF station MAC address (0x0107).
88 * NOTE: Upon successful completion of this command, MAC address information
89 * is returned in user specified buffer. Please interpret user specified
90 * buffer as "manage_mac_read" response.
91 * Response such as various MAC addresses are stored in HW struct (port.mac)
92 * ice_aq_discover_caps is expected to be called before this function is called.
94 static enum ice_status
95 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
98 struct ice_aqc_manage_mac_read_resp *resp;
99 struct ice_aqc_manage_mac_read *cmd;
100 struct ice_aq_desc desc;
101 enum ice_status status;
105 cmd = &desc.params.mac_read;
107 if (buf_size < sizeof(*resp))
108 return ICE_ERR_BUF_TOO_SHORT;
110 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
112 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
116 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
117 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
119 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
120 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
124 /* A single port can report up to two (LAN and WoL) addresses */
125 for (i = 0; i < cmd->num_addr; i++)
126 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
127 ice_memcpy(hw->port_info->mac.lan_addr,
128 resp[i].mac_addr, ETH_ALEN,
130 ice_memcpy(hw->port_info->mac.perm_addr,
132 ETH_ALEN, ICE_DMA_TO_NONDMA);
140 * ice_aq_get_phy_caps - returns PHY capabilities
141 * @pi: port information structure
142 * @qual_mods: report qualified modules
143 * @report_mode: report mode capabilities
144 * @pcaps: structure for PHY capabilities to be filled
145 * @cd: pointer to command details structure or NULL
147 * Returns the various PHY capabilities supported on the Port (0x0600)
150 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
151 struct ice_aqc_get_phy_caps_data *pcaps,
152 struct ice_sq_cd *cd)
154 struct ice_aqc_get_phy_caps *cmd;
155 u16 pcaps_size = sizeof(*pcaps);
156 struct ice_aq_desc desc;
157 enum ice_status status;
159 cmd = &desc.params.get_phy;
161 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
162 return ICE_ERR_PARAM;
164 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
167 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
169 cmd->param0 |= CPU_TO_LE16(report_mode);
170 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
172 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
173 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
174 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
181 * ice_get_media_type - Gets media type
182 * @pi: port information structure
184 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
186 struct ice_link_status *hw_link_info;
189 return ICE_MEDIA_UNKNOWN;
191 hw_link_info = &pi->phy.link_info;
192 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
193 /* If more than one media type is selected, report unknown */
194 return ICE_MEDIA_UNKNOWN;
196 if (hw_link_info->phy_type_low) {
197 switch (hw_link_info->phy_type_low) {
198 case ICE_PHY_TYPE_LOW_1000BASE_SX:
199 case ICE_PHY_TYPE_LOW_1000BASE_LX:
200 case ICE_PHY_TYPE_LOW_10GBASE_SR:
201 case ICE_PHY_TYPE_LOW_10GBASE_LR:
202 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
203 case ICE_PHY_TYPE_LOW_25GBASE_SR:
204 case ICE_PHY_TYPE_LOW_25GBASE_LR:
205 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
206 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
207 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
208 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
209 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
210 case ICE_PHY_TYPE_LOW_50GBASE_SR:
211 case ICE_PHY_TYPE_LOW_50GBASE_FR:
212 case ICE_PHY_TYPE_LOW_50GBASE_LR:
213 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
214 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
215 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
216 case ICE_PHY_TYPE_LOW_100GBASE_DR:
217 return ICE_MEDIA_FIBER;
218 case ICE_PHY_TYPE_LOW_100BASE_TX:
219 case ICE_PHY_TYPE_LOW_1000BASE_T:
220 case ICE_PHY_TYPE_LOW_2500BASE_T:
221 case ICE_PHY_TYPE_LOW_5GBASE_T:
222 case ICE_PHY_TYPE_LOW_10GBASE_T:
223 case ICE_PHY_TYPE_LOW_25GBASE_T:
224 return ICE_MEDIA_BASET;
225 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
226 case ICE_PHY_TYPE_LOW_25GBASE_CR:
227 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
228 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
229 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
230 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
231 case ICE_PHY_TYPE_LOW_50GBASE_CP:
232 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
233 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
234 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
236 case ICE_PHY_TYPE_LOW_1000BASE_KX:
237 case ICE_PHY_TYPE_LOW_2500BASE_KX:
238 case ICE_PHY_TYPE_LOW_2500BASE_X:
239 case ICE_PHY_TYPE_LOW_5GBASE_KR:
240 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
241 case ICE_PHY_TYPE_LOW_25GBASE_KR:
242 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
243 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
244 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
245 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
246 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
247 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
248 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
249 return ICE_MEDIA_BACKPLANE;
252 switch (hw_link_info->phy_type_high) {
253 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
254 return ICE_MEDIA_BACKPLANE;
257 return ICE_MEDIA_UNKNOWN;
261 * ice_aq_get_link_info
262 * @pi: port information structure
263 * @ena_lse: enable/disable LinkStatusEvent reporting
264 * @link: pointer to link status structure - optional
265 * @cd: pointer to command details structure or NULL
267 * Get Link Status (0x607). Returns the link status of the adapter.
270 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
271 struct ice_link_status *link, struct ice_sq_cd *cd)
273 struct ice_link_status *hw_link_info_old, *hw_link_info;
274 struct ice_aqc_get_link_status_data link_data = { 0 };
275 struct ice_aqc_get_link_status *resp;
276 enum ice_media_type *hw_media_type;
277 struct ice_fc_info *hw_fc_info;
278 bool tx_pause, rx_pause;
279 struct ice_aq_desc desc;
280 enum ice_status status;
284 return ICE_ERR_PARAM;
285 hw_link_info_old = &pi->phy.link_info_old;
286 hw_media_type = &pi->phy.media_type;
287 hw_link_info = &pi->phy.link_info;
288 hw_fc_info = &pi->fc;
290 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
291 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
292 resp = &desc.params.get_link_status;
293 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
294 resp->lport_num = pi->lport;
296 status = ice_aq_send_cmd(pi->hw, &desc, &link_data, sizeof(link_data),
299 if (status != ICE_SUCCESS)
302 /* save off old link status information */
303 *hw_link_info_old = *hw_link_info;
305 /* update current link status information */
306 hw_link_info->link_speed = LE16_TO_CPU(link_data.link_speed);
307 hw_link_info->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
308 hw_link_info->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
309 *hw_media_type = ice_get_media_type(pi);
310 hw_link_info->link_info = link_data.link_info;
311 hw_link_info->an_info = link_data.an_info;
312 hw_link_info->ext_info = link_data.ext_info;
313 hw_link_info->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
314 hw_link_info->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
315 hw_link_info->topo_media_conflict = link_data.topo_media_conflict;
316 hw_link_info->pacing = link_data.cfg & ICE_AQ_CFG_PACING_M;
319 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
320 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
321 if (tx_pause && rx_pause)
322 hw_fc_info->current_mode = ICE_FC_FULL;
324 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
326 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
328 hw_fc_info->current_mode = ICE_FC_NONE;
330 hw_link_info->lse_ena =
331 !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
334 /* save link status information */
336 *link = *hw_link_info;
338 /* flag cleared so calling functions don't call AQ again */
339 pi->phy.get_link_info = false;
345 * ice_init_flex_flags
346 * @hw: pointer to the hardware structure
347 * @prof_id: Rx Descriptor Builder profile ID
349 * Function to initialize Rx flex flags
351 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
355 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
356 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
357 * flexiflags1[3:0] - Not used for flag programming
358 * flexiflags2[7:0] - Tunnel and VLAN types
359 * 2 invalid fields in last index
362 /* Rx flex flags are currently programmed for the NIC profiles only.
363 * Different flag bit programming configurations can be added per
366 case ICE_RXDID_FLEX_NIC:
367 case ICE_RXDID_FLEX_NIC_2:
368 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
369 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
371 /* flex flag 1 is not used for flexi-flag programming, skipping
372 * these four FLG64 bits.
374 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
375 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
376 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
377 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
378 ICE_FLG_EVLAN_x9100, idx++);
379 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
380 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
381 ICE_FLG_TNL0, idx++);
382 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
383 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
387 ice_debug(hw, ICE_DBG_INIT,
388 "Flag programming for profile ID %d not supported\n",
395 * @hw: pointer to the hardware structure
396 * @prof_id: Rx Descriptor Builder profile ID
398 * Function to initialize flex descriptors
400 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
402 enum ice_flex_mdid mdid;
405 case ICE_RXDID_FLEX_NIC:
406 case ICE_RXDID_FLEX_NIC_2:
407 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
408 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
409 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
411 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
412 ICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH;
414 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
416 ice_init_flex_flags(hw, prof_id);
420 ice_debug(hw, ICE_DBG_INIT,
421 "Field init for profile ID %d not supported\n",
428 * @hw: pointer to the HW struct
429 * @max_frame_size: Maximum Frame Size to be supported
430 * @cd: pointer to command details structure or NULL
432 * Set MAC configuration (0x0603)
435 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
437 u16 fc_threshold_val, tx_timer_val;
438 struct ice_aqc_set_mac_cfg *cmd;
439 struct ice_port_info *pi;
440 struct ice_aq_desc desc;
441 enum ice_status status;
446 cmd = &desc.params.set_mac_cfg;
448 if (max_frame_size == 0)
449 return ICE_ERR_PARAM;
451 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
453 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
455 /* Retrieve the current data_pacing value in FW*/
456 pi = &hw->port_info[port_num];
458 /* We turn on the get_link_info so that ice_update_link_info(...)
461 pi->phy.get_link_info = 1;
463 status = ice_get_link_status(pi, &link_up);
468 cmd->params = pi->phy.link_info.pacing;
470 /* We read back the transmit timer and fc threshold value of
471 * LFC. Thus, we will use index =
472 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
474 * Also, because we are opearating on transmit timer and fc
475 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
477 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
479 /* Retrieve the transmit timer */
481 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
482 tx_timer_val = reg_val &
483 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
484 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
486 /* Retrieve the fc threshold */
488 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
489 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);
490 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);
492 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
496 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
497 * @hw: pointer to the HW struct
499 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
501 struct ice_switch_info *sw;
503 hw->switch_info = (struct ice_switch_info *)
504 ice_malloc(hw, sizeof(*hw->switch_info));
505 sw = hw->switch_info;
508 return ICE_ERR_NO_MEMORY;
510 INIT_LIST_HEAD(&sw->vsi_list_map_head);
512 return ice_init_def_sw_recp(hw);
516 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
517 * @hw: pointer to the HW struct
519 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
521 struct ice_switch_info *sw = hw->switch_info;
522 struct ice_vsi_list_map_info *v_pos_map;
523 struct ice_vsi_list_map_info *v_tmp_map;
524 struct ice_sw_recipe *recps;
527 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
528 ice_vsi_list_map_info, list_entry) {
529 LIST_DEL(&v_pos_map->list_entry);
530 ice_free(hw, v_pos_map);
532 recps = hw->switch_info->recp_list;
533 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
534 recps[i].root_rid = i;
536 if (recps[i].adv_rule) {
537 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
538 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
540 ice_destroy_lock(&recps[i].filt_rule_lock);
541 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
542 &recps[i].filt_rules,
543 ice_adv_fltr_mgmt_list_entry,
545 LIST_DEL(&lst_itr->list_entry);
546 ice_free(hw, lst_itr->lkups);
547 ice_free(hw, lst_itr);
550 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
552 ice_destroy_lock(&recps[i].filt_rule_lock);
553 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
554 &recps[i].filt_rules,
555 ice_fltr_mgmt_list_entry,
557 LIST_DEL(&lst_itr->list_entry);
558 ice_free(hw, lst_itr);
562 ice_rm_all_sw_replay_rule_info(hw);
563 ice_free(hw, sw->recp_list);
567 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \
568 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))
569 #define ICE_FW_LOG_DESC_SIZE_MAX \
570 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)
573 * ice_cfg_fw_log - configure FW logging
574 * @hw: pointer to the HW struct
575 * @enable: enable certain FW logging events if true, disable all if false
577 * This function enables/disables the FW logging via Rx CQ events and a UART
578 * port based on predetermined configurations. FW logging via the Rx CQ can be
579 * enabled/disabled for individual PF's. However, FW logging via the UART can
580 * only be enabled/disabled for all PFs on the same device.
582 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
583 * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
584 * before initializing the device.
586 * When re/configuring FW logging, callers need to update the "cfg" elements of
587 * the hw->fw_log.evnts array with the desired logging event configurations for
588 * modules of interest. When disabling FW logging completely, the callers can
589 * just pass false in the "enable" parameter. On completion, the function will
590 * update the "cur" element of the hw->fw_log.evnts array with the resulting
591 * logging event configurations of the modules that are being re/configured. FW
592 * logging modules that are not part of a reconfiguration operation retain their
595 * Before resetting the device, it is recommended that the driver disables FW
596 * logging before shutting down the control queue. When disabling FW logging
597 * ("enable" = false), the latest configurations of FW logging events stored in
598 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
601 * When enabling FW logging to emit log messages via the Rx CQ during the
602 * device's initialization phase, a mechanism alternative to interrupt handlers
603 * needs to be used to extract FW log messages from the Rx CQ periodically and
604 * to prevent the Rx CQ from being full and stalling other types of control
605 * messages from FW to SW. Interrupts are typically disabled during the device's
606 * initialization phase.
608 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
610 struct ice_aqc_fw_logging_data *data = NULL;
611 struct ice_aqc_fw_logging *cmd;
612 enum ice_status status = ICE_SUCCESS;
613 u16 i, chgs = 0, len = 0;
614 struct ice_aq_desc desc;
618 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
621 /* Disable FW logging only when the control queue is still responsive */
623 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
626 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
627 cmd = &desc.params.fw_logging;
629 /* Indicate which controls are valid */
630 if (hw->fw_log.cq_en)
631 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
633 if (hw->fw_log.uart_en)
634 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
637 /* Fill in an array of entries with FW logging modules and
638 * logging events being reconfigured.
640 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
643 /* Keep track of enabled event types */
644 actv_evnts |= hw->fw_log.evnts[i].cfg;
646 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
650 data = (struct ice_aqc_fw_logging_data *)
652 ICE_FW_LOG_DESC_SIZE_MAX);
654 return ICE_ERR_NO_MEMORY;
657 val = i << ICE_AQC_FW_LOG_ID_S;
658 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
659 data->entry[chgs++] = CPU_TO_LE16(val);
662 /* Only enable FW logging if at least one module is specified.
663 * If FW logging is currently enabled but all modules are not
664 * enabled to emit log messages, disable FW logging altogether.
667 /* Leave if there is effectively no change */
671 if (hw->fw_log.cq_en)
672 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
674 if (hw->fw_log.uart_en)
675 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
678 len = ICE_FW_LOG_DESC_SIZE(chgs);
679 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
683 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
685 /* Update the current configuration to reflect events enabled.
686 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
687 * logging mode is enabled for the device. They do not reflect
688 * actual modules being enabled to emit log messages. So, their
689 * values remain unchanged even when all modules are disabled.
691 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
693 hw->fw_log.actv_evnts = actv_evnts;
694 for (i = 0; i < cnt; i++) {
698 /* When disabling all FW logging events as part
699 * of device's de-initialization, the original
700 * configurations are retained, and can be used
701 * to reconfigure FW logging later if the device
704 hw->fw_log.evnts[i].cur = 0;
708 v = LE16_TO_CPU(data->entry[i]);
709 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
710 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
723 * @hw: pointer to the HW struct
724 * @desc: pointer to the AQ message descriptor
725 * @buf: pointer to the buffer accompanying the AQ message
727 * Formats a FW Log message and outputs it via the standard driver logs.
729 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
731 ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg Start ]\n");
732 ice_debug_array(hw, ICE_DBG_AQ_MSG, 16, 1, (u8 *)buf,
733 LE16_TO_CPU(desc->datalen));
734 ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg End ]\n");
738 * ice_get_itr_intrl_gran - determine int/intrl granularity
739 * @hw: pointer to the HW struct
741 * Determines the itr/intrl granularities based on the maximum aggregate
742 * bandwidth according to the device's configuration during power-on.
744 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
746 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
747 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
748 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
750 switch (max_agg_bw) {
751 case ICE_MAX_AGG_BW_200G:
752 case ICE_MAX_AGG_BW_100G:
753 case ICE_MAX_AGG_BW_50G:
754 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
755 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
757 case ICE_MAX_AGG_BW_25G:
758 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
759 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
765 * ice_init_hw - main hardware initialization routine
766 * @hw: pointer to the hardware structure
768 enum ice_status ice_init_hw(struct ice_hw *hw)
770 struct ice_aqc_get_phy_caps_data *pcaps;
771 enum ice_status status;
775 ice_debug(hw, ICE_DBG_TRACE, "ice_init_hw");
778 /* Set MAC type based on DeviceID */
779 status = ice_set_mac_type(hw);
783 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
784 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
785 PF_FUNC_RID_FUNCTION_NUMBER_S;
788 status = ice_reset(hw, ICE_RESET_PFR);
792 ice_get_itr_intrl_gran(hw);
795 status = ice_init_all_ctrlq(hw);
797 goto err_unroll_cqinit;
799 /* Enable FW logging. Not fatal if this fails. */
800 status = ice_cfg_fw_log(hw, true);
802 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
804 status = ice_clear_pf_cfg(hw);
806 goto err_unroll_cqinit;
808 /* Set bit to enable Flow Director filters */
809 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
810 INIT_LIST_HEAD(&hw->fdir_list_head);
812 ice_clear_pxe_mode(hw);
814 status = ice_init_nvm(hw);
816 goto err_unroll_cqinit;
818 status = ice_get_caps(hw);
820 goto err_unroll_cqinit;
822 hw->port_info = (struct ice_port_info *)
823 ice_malloc(hw, sizeof(*hw->port_info));
824 if (!hw->port_info) {
825 status = ICE_ERR_NO_MEMORY;
826 goto err_unroll_cqinit;
829 /* set the back pointer to HW */
830 hw->port_info->hw = hw;
832 /* Initialize port_info struct with switch configuration data */
833 status = ice_get_initial_sw_cfg(hw);
835 goto err_unroll_alloc;
839 /* Query the allocated resources for Tx scheduler */
840 status = ice_sched_query_res_alloc(hw);
842 ice_debug(hw, ICE_DBG_SCHED,
843 "Failed to get scheduler allocated resources\n");
844 goto err_unroll_alloc;
848 /* Initialize port_info struct with scheduler data */
849 status = ice_sched_init_port(hw->port_info);
851 goto err_unroll_sched;
853 pcaps = (struct ice_aqc_get_phy_caps_data *)
854 ice_malloc(hw, sizeof(*pcaps));
856 status = ICE_ERR_NO_MEMORY;
857 goto err_unroll_sched;
860 /* Initialize port_info struct with PHY capabilities */
861 status = ice_aq_get_phy_caps(hw->port_info, false,
862 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
865 goto err_unroll_sched;
867 /* Initialize port_info struct with link information */
868 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
870 goto err_unroll_sched;
871 /* need a valid SW entry point to build a Tx tree */
872 if (!hw->sw_entry_point_layer) {
873 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
874 status = ICE_ERR_CFG;
875 goto err_unroll_sched;
877 INIT_LIST_HEAD(&hw->agg_list);
878 /* Initialize max burst size */
879 if (!hw->max_burst_size)
880 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
882 status = ice_init_fltr_mgmt_struct(hw);
884 goto err_unroll_sched;
887 /* Get MAC information */
888 /* A single port can report up to two (LAN and WoL) addresses */
889 mac_buf = ice_calloc(hw, 2,
890 sizeof(struct ice_aqc_manage_mac_read_resp));
891 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
894 status = ICE_ERR_NO_MEMORY;
895 goto err_unroll_fltr_mgmt_struct;
898 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
899 ice_free(hw, mac_buf);
902 goto err_unroll_fltr_mgmt_struct;
904 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
905 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
907 /* Obtain counter base index which would be used by flow director */
908 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
910 goto err_unroll_fltr_mgmt_struct;
914 err_unroll_fltr_mgmt_struct:
915 ice_cleanup_fltr_mgmt_struct(hw);
917 ice_sched_cleanup_all(hw);
919 ice_free(hw, hw->port_info);
920 hw->port_info = NULL;
922 ice_shutdown_all_ctrlq(hw);
927 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
928 * @hw: pointer to the hardware structure
930 * This should be called only during nominal operation, not as a result of
931 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
932 * applicable initializations if it fails for any reason.
934 void ice_deinit_hw(struct ice_hw *hw)
936 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
937 ice_cleanup_fltr_mgmt_struct(hw);
939 ice_sched_cleanup_all(hw);
940 ice_sched_clear_agg(hw);
944 ice_free(hw, hw->port_info);
945 hw->port_info = NULL;
948 /* Attempt to disable FW logging before shutting down control queues */
949 ice_cfg_fw_log(hw, false);
950 ice_shutdown_all_ctrlq(hw);
952 /* Clear VSI contexts if not already cleared */
953 ice_clear_all_vsi_ctx(hw);
957 * ice_check_reset - Check to see if a global reset is complete
958 * @hw: pointer to the hardware structure
960 enum ice_status ice_check_reset(struct ice_hw *hw)
962 u32 cnt, reg = 0, grst_delay;
964 /* Poll for Device Active state in case a recent CORER, GLOBR,
965 * or EMPR has occurred. The grst delay value is in 100ms units.
966 * Add 1sec for outstanding AQ commands that can take a long time.
968 #define GLGEN_RSTCTL 0x000B8180 /* Reset Source: POR */
969 #define GLGEN_RSTCTL_GRSTDEL_S 0
970 #define GLGEN_RSTCTL_GRSTDEL_M MAKEMASK(0x3F, GLGEN_RSTCTL_GRSTDEL_S)
971 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
972 GLGEN_RSTCTL_GRSTDEL_S) + 10;
974 for (cnt = 0; cnt < grst_delay; cnt++) {
975 ice_msec_delay(100, true);
976 reg = rd32(hw, GLGEN_RSTAT);
977 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
981 if (cnt == grst_delay) {
982 ice_debug(hw, ICE_DBG_INIT,
983 "Global reset polling failed to complete.\n");
984 return ICE_ERR_RESET_FAILED;
987 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
988 GLNVM_ULD_GLOBR_DONE_M)
990 /* Device is Active; check Global Reset processes are done */
991 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
992 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
993 if (reg == ICE_RESET_DONE_MASK) {
994 ice_debug(hw, ICE_DBG_INIT,
995 "Global reset processes done. %d\n", cnt);
998 ice_msec_delay(10, true);
1001 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1002 ice_debug(hw, ICE_DBG_INIT,
1003 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1005 return ICE_ERR_RESET_FAILED;
1012 * ice_pf_reset - Reset the PF
1013 * @hw: pointer to the hardware structure
1015 * If a global reset has been triggered, this function checks
1016 * for its completion and then issues the PF reset
1018 static enum ice_status ice_pf_reset(struct ice_hw *hw)
1022 /* If at function entry a global reset was already in progress, i.e.
1023 * state is not 'device active' or any of the reset done bits are not
1024 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1025 * global reset is done.
1027 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1028 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1029 /* poll on global reset currently in progress until done */
1030 if (ice_check_reset(hw))
1031 return ICE_ERR_RESET_FAILED;
1037 reg = rd32(hw, PFGEN_CTRL);
1039 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1041 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1042 reg = rd32(hw, PFGEN_CTRL);
1043 if (!(reg & PFGEN_CTRL_PFSWR_M))
1046 ice_msec_delay(1, true);
1049 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1050 ice_debug(hw, ICE_DBG_INIT,
1051 "PF reset polling failed to complete.\n");
1052 return ICE_ERR_RESET_FAILED;
1059 * ice_reset - Perform different types of reset
1060 * @hw: pointer to the hardware structure
1061 * @req: reset request
1063 * This function triggers a reset as specified by the req parameter.
1066 * If anything other than a PF reset is triggered, PXE mode is restored.
1067 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1068 * interface has been restored in the rebuild flow.
1070 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1076 return ice_pf_reset(hw);
1077 case ICE_RESET_CORER:
1078 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1079 val = GLGEN_RTRIG_CORER_M;
1081 case ICE_RESET_GLOBR:
1082 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1083 val = GLGEN_RTRIG_GLOBR_M;
1086 return ICE_ERR_PARAM;
1089 val |= rd32(hw, GLGEN_RTRIG);
1090 wr32(hw, GLGEN_RTRIG, val);
1094 /* wait for the FW to be ready */
1095 return ice_check_reset(hw);
1101 * ice_copy_rxq_ctx_to_hw
1102 * @hw: pointer to the hardware structure
1103 * @ice_rxq_ctx: pointer to the rxq context
1104 * @rxq_index: the index of the Rx queue
1106 * Copies rxq context from dense structure to HW register space
1108 static enum ice_status
1109 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1114 return ICE_ERR_BAD_PTR;
1116 if (rxq_index > QRX_CTRL_MAX_INDEX)
1117 return ICE_ERR_PARAM;
1119 /* Copy each dword separately to HW */
1120 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1121 wr32(hw, QRX_CONTEXT(i, rxq_index),
1122 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1124 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1125 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1131 /* LAN Rx Queue Context */
1132 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1133 /* Field Width LSB */
1134 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1135 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1136 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1137 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1138 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1139 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1140 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1141 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1142 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1143 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1144 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1145 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1146 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1147 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1148 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1149 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1150 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1151 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1152 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1158 * @hw: pointer to the hardware structure
1159 * @rlan_ctx: pointer to the rxq context
1160 * @rxq_index: the index of the Rx queue
1162 * Converts rxq context from sparse to dense structure and then writes
1163 * it to HW register space
1166 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1169 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1171 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1172 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1175 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1178 * @hw: pointer to the hardware structure
1179 * @rxq_index: the index of the Rx queue to clear
1181 * Clears rxq context in HW register space
1183 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1187 if (rxq_index > QRX_CTRL_MAX_INDEX)
1188 return ICE_ERR_PARAM;
1190 /* Clear each dword register separately */
1191 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1192 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1196 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1198 /* LAN Tx Queue Context */
1199 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1200 /* Field Width LSB */
1201 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1202 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1203 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1204 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1205 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1206 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1207 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1208 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1209 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1210 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1211 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1212 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1213 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1214 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1215 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1216 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1217 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1218 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1219 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1220 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1221 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1222 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1223 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1224 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1225 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1226 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1227 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 110, 171),
1231 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1233 * ice_copy_tx_cmpltnq_ctx_to_hw
1234 * @hw: pointer to the hardware structure
1235 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1236 * @tx_cmpltnq_index: the index of the completion queue
1238 * Copies Tx completion queue context from dense structure to HW register space
1240 static enum ice_status
1241 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1242 u32 tx_cmpltnq_index)
1246 if (!ice_tx_cmpltnq_ctx)
1247 return ICE_ERR_BAD_PTR;
1249 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1250 return ICE_ERR_PARAM;
1252 /* Copy each dword separately to HW */
1253 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1254 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1255 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1257 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1258 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1264 /* LAN Tx Completion Queue Context */
1265 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1266 /* Field Width LSB */
1267 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1268 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1269 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1270 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1271 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1272 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1273 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1274 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1275 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1276 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1281 * ice_write_tx_cmpltnq_ctx
1282 * @hw: pointer to the hardware structure
1283 * @tx_cmpltnq_ctx: pointer to the completion queue context
1284 * @tx_cmpltnq_index: the index of the completion queue
1286 * Converts completion queue context from sparse to dense structure and then
1287 * writes it to HW register space
1290 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1291 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1292 u32 tx_cmpltnq_index)
1294 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1296 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1297 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1301 * ice_clear_tx_cmpltnq_ctx
1302 * @hw: pointer to the hardware structure
1303 * @tx_cmpltnq_index: the index of the completion queue to clear
1305 * Clears Tx completion queue context in HW register space
1308 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1312 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1313 return ICE_ERR_PARAM;
1315 /* Clear each dword register separately */
1316 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1317 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1323 * ice_copy_tx_drbell_q_ctx_to_hw
1324 * @hw: pointer to the hardware structure
1325 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1326 * @tx_drbell_q_index: the index of the doorbell queue
1328 * Copies doorbell queue context from dense structure to HW register space
1330 static enum ice_status
1331 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1332 u32 tx_drbell_q_index)
1336 if (!ice_tx_drbell_q_ctx)
1337 return ICE_ERR_BAD_PTR;
1339 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1340 return ICE_ERR_PARAM;
1342 /* Copy each dword separately to HW */
1343 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1344 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1345 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1347 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1348 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1354 /* LAN Tx Doorbell Queue Context info */
1355 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1356 /* Field Width LSB */
1357 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1358 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1359 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1360 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1361 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1362 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1363 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1364 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1365 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1366 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1367 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1372 * ice_write_tx_drbell_q_ctx
1373 * @hw: pointer to the hardware structure
1374 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1375 * @tx_drbell_q_index: the index of the doorbell queue
1377 * Converts doorbell queue context from sparse to dense structure and then
1378 * writes it to HW register space
1381 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1382 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1383 u32 tx_drbell_q_index)
1385 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1387 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1388 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1392 * ice_clear_tx_drbell_q_ctx
1393 * @hw: pointer to the hardware structure
1394 * @tx_drbell_q_index: the index of the doorbell queue to clear
1396 * Clears doorbell queue context in HW register space
1399 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1403 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1404 return ICE_ERR_PARAM;
1406 /* Clear each dword register separately */
1407 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1408 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1412 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1416 * @hw: pointer to the hardware structure
1418 * @desc: pointer to control queue descriptor
1419 * @buf: pointer to command buffer
1420 * @buf_len: max length of buf
1422 * Dumps debug log about control command with descriptor contents.
1425 ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf, u16 buf_len)
1427 struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;
1430 if (!(mask & hw->debug_mask))
1436 len = LE16_TO_CPU(cq_desc->datalen);
1439 "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
1440 LE16_TO_CPU(cq_desc->opcode),
1441 LE16_TO_CPU(cq_desc->flags),
1442 LE16_TO_CPU(cq_desc->datalen), LE16_TO_CPU(cq_desc->retval));
1443 ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
1444 LE32_TO_CPU(cq_desc->cookie_high),
1445 LE32_TO_CPU(cq_desc->cookie_low));
1446 ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
1447 LE32_TO_CPU(cq_desc->params.generic.param0),
1448 LE32_TO_CPU(cq_desc->params.generic.param1));
1449 ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
1450 LE32_TO_CPU(cq_desc->params.generic.addr_high),
1451 LE32_TO_CPU(cq_desc->params.generic.addr_low));
1452 if (buf && cq_desc->datalen != 0) {
1453 ice_debug(hw, mask, "Buffer:\n");
1457 ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len);
1462 /* FW Admin Queue command wrappers */
1465 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1466 * @hw: pointer to the HW struct
1467 * @desc: descriptor describing the command
1468 * @buf: buffer to use for indirect commands (NULL for direct commands)
1469 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1470 * @cd: pointer to command details structure
1472 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1475 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1476 u16 buf_size, struct ice_sq_cd *cd)
1478 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1483 * @hw: pointer to the HW struct
1484 * @cd: pointer to command details structure or NULL
1486 * Get the firmware version (0x0001) from the admin queue commands
1488 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1490 struct ice_aqc_get_ver *resp;
1491 struct ice_aq_desc desc;
1492 enum ice_status status;
1494 resp = &desc.params.get_ver;
1496 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1498 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1501 hw->fw_branch = resp->fw_branch;
1502 hw->fw_maj_ver = resp->fw_major;
1503 hw->fw_min_ver = resp->fw_minor;
1504 hw->fw_patch = resp->fw_patch;
1505 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1506 hw->api_branch = resp->api_branch;
1507 hw->api_maj_ver = resp->api_major;
1508 hw->api_min_ver = resp->api_minor;
1509 hw->api_patch = resp->api_patch;
1518 * @hw: pointer to the HW struct
1519 * @unloading: is the driver unloading itself
1521 * Tell the Firmware that we're shutting down the AdminQ and whether
1522 * or not the driver is unloading as well (0x0003).
1524 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1526 struct ice_aqc_q_shutdown *cmd;
1527 struct ice_aq_desc desc;
1529 cmd = &desc.params.q_shutdown;
1531 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1534 cmd->driver_unloading = CPU_TO_LE32(ICE_AQC_DRIVER_UNLOADING);
1536 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1541 * @hw: pointer to the HW struct
1543 * @access: access type
1544 * @sdp_number: resource number
1545 * @timeout: the maximum time in ms that the driver may hold the resource
1546 * @cd: pointer to command details structure or NULL
1548 * Requests common resource using the admin queue commands (0x0008).
1549 * When attempting to acquire the Global Config Lock, the driver can
1550 * learn of three states:
1551 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1552 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1553 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1554 * successfully downloaded the package; the driver does
1555 * not have to download the package and can continue
1558 * Note that if the caller is in an acquire lock, perform action, release lock
1559 * phase of operation, it is possible that the FW may detect a timeout and issue
1560 * a CORER. In this case, the driver will receive a CORER interrupt and will
1561 * have to determine its cause. The calling thread that is handling this flow
1562 * will likely get an error propagated back to it indicating the Download
1563 * Package, Update Package or the Release Resource AQ commands timed out.
1565 static enum ice_status
1566 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1567 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1568 struct ice_sq_cd *cd)
1570 struct ice_aqc_req_res *cmd_resp;
1571 struct ice_aq_desc desc;
1572 enum ice_status status;
1574 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_req_res");
1576 cmd_resp = &desc.params.res_owner;
1578 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1580 cmd_resp->res_id = CPU_TO_LE16(res);
1581 cmd_resp->access_type = CPU_TO_LE16(access);
1582 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1583 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1586 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1588 /* The completion specifies the maximum time in ms that the driver
1589 * may hold the resource in the Timeout field.
1592 /* Global config lock response utilizes an additional status field.
1594 * If the Global config lock resource is held by some other driver, the
1595 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1596 * and the timeout field indicates the maximum time the current owner
1597 * of the resource has to free it.
1599 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1600 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1601 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1603 } else if (LE16_TO_CPU(cmd_resp->status) ==
1604 ICE_AQ_RES_GLBL_IN_PROG) {
1605 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1606 return ICE_ERR_AQ_ERROR;
1607 } else if (LE16_TO_CPU(cmd_resp->status) ==
1608 ICE_AQ_RES_GLBL_DONE) {
1609 return ICE_ERR_AQ_NO_WORK;
1612 /* invalid FW response, force a timeout immediately */
1614 return ICE_ERR_AQ_ERROR;
1617 /* If the resource is held by some other driver, the command completes
1618 * with a busy return value and the timeout field indicates the maximum
1619 * time the current owner of the resource has to free it.
1621 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1622 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1628 * ice_aq_release_res
1629 * @hw: pointer to the HW struct
1631 * @sdp_number: resource number
1632 * @cd: pointer to command details structure or NULL
1634 * release common resource using the admin queue commands (0x0009)
1636 static enum ice_status
1637 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1638 struct ice_sq_cd *cd)
1640 struct ice_aqc_req_res *cmd;
1641 struct ice_aq_desc desc;
1643 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_release_res");
1645 cmd = &desc.params.res_owner;
1647 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1649 cmd->res_id = CPU_TO_LE16(res);
1650 cmd->res_number = CPU_TO_LE32(sdp_number);
1652 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1657 * @hw: pointer to the HW structure
1659 * @access: access type (read or write)
1660 * @timeout: timeout in milliseconds
1662 * This function will attempt to acquire the ownership of a resource.
1665 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1666 enum ice_aq_res_access_type access, u32 timeout)
1668 #define ICE_RES_POLLING_DELAY_MS 10
1669 u32 delay = ICE_RES_POLLING_DELAY_MS;
1670 u32 time_left = timeout;
1671 enum ice_status status;
1673 ice_debug(hw, ICE_DBG_TRACE, "ice_acquire_res");
1675 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1677 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1678 * previously acquired the resource and performed any necessary updates;
1679 * in this case the caller does not obtain the resource and has no
1680 * further work to do.
1682 if (status == ICE_ERR_AQ_NO_WORK)
1683 goto ice_acquire_res_exit;
1686 ice_debug(hw, ICE_DBG_RES,
1687 "resource %d acquire type %d failed.\n", res, access);
1689 /* If necessary, poll until the current lock owner timeouts */
1690 timeout = time_left;
1691 while (status && timeout && time_left) {
1692 ice_msec_delay(delay, true);
1693 timeout = (timeout > delay) ? timeout - delay : 0;
1694 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1696 if (status == ICE_ERR_AQ_NO_WORK)
1697 /* lock free, but no work to do */
1704 if (status && status != ICE_ERR_AQ_NO_WORK)
1705 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1707 ice_acquire_res_exit:
1708 if (status == ICE_ERR_AQ_NO_WORK) {
1709 if (access == ICE_RES_WRITE)
1710 ice_debug(hw, ICE_DBG_RES,
1711 "resource indicates no work to do.\n");
1713 ice_debug(hw, ICE_DBG_RES,
1714 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1721 * @hw: pointer to the HW structure
1724 * This function will release a resource using the proper Admin Command.
1726 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1728 enum ice_status status;
1729 u32 total_delay = 0;
1731 ice_debug(hw, ICE_DBG_TRACE, "ice_release_res");
1733 status = ice_aq_release_res(hw, res, 0, NULL);
1735 /* there are some rare cases when trying to release the resource
1736 * results in an admin queue timeout, so handle them correctly
1738 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1739 (total_delay < hw->adminq.sq_cmd_timeout)) {
1740 ice_msec_delay(1, true);
1741 status = ice_aq_release_res(hw, res, 0, NULL);
1747 * ice_aq_alloc_free_res - command to allocate/free resources
1748 * @hw: pointer to the HW struct
1749 * @num_entries: number of resource entries in buffer
1750 * @buf: Indirect buffer to hold data parameters and response
1751 * @buf_size: size of buffer for indirect commands
1752 * @opc: pass in the command opcode
1753 * @cd: pointer to command details structure or NULL
1755 * Helper function to allocate/free resources using the admin queue commands
1758 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1759 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1760 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1762 struct ice_aqc_alloc_free_res_cmd *cmd;
1763 struct ice_aq_desc desc;
1765 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_alloc_free_res");
1767 cmd = &desc.params.sw_res_ctrl;
1770 return ICE_ERR_PARAM;
1772 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1773 return ICE_ERR_PARAM;
1775 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1777 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1779 cmd->num_entries = CPU_TO_LE16(num_entries);
1781 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1785 * ice_alloc_hw_res - allocate resource
1786 * @hw: pointer to the HW struct
1787 * @type: type of resource
1788 * @num: number of resources to allocate
1789 * @btm: allocate from bottom
1790 * @res: pointer to array that will receive the resources
1793 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1795 struct ice_aqc_alloc_free_res_elem *buf;
1796 enum ice_status status;
1799 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1800 buf = (struct ice_aqc_alloc_free_res_elem *)
1801 ice_malloc(hw, buf_len);
1803 return ICE_ERR_NO_MEMORY;
1805 /* Prepare buffer to allocate resource. */
1806 buf->num_elems = CPU_TO_LE16(num);
1807 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1808 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1810 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1812 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1813 ice_aqc_opc_alloc_res, NULL);
1815 goto ice_alloc_res_exit;
1817 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1818 ICE_NONDMA_TO_NONDMA);
1826 * ice_free_hw_res - free allocated HW resource
1827 * @hw: pointer to the HW struct
1828 * @type: type of resource to free
1829 * @num: number of resources
1830 * @res: pointer to array that contains the resources to free
1833 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1835 struct ice_aqc_alloc_free_res_elem *buf;
1836 enum ice_status status;
1839 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1840 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1842 return ICE_ERR_NO_MEMORY;
1844 /* Prepare buffer to free resource. */
1845 buf->num_elems = CPU_TO_LE16(num);
1846 buf->res_type = CPU_TO_LE16(type);
1847 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1848 ICE_NONDMA_TO_NONDMA);
1850 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1851 ice_aqc_opc_free_res, NULL);
1853 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1860 * ice_get_num_per_func - determine number of resources per PF
1861 * @hw: pointer to the HW structure
1862 * @max: value to be evenly split between each PF
1864 * Determine the number of valid functions by going through the bitmap returned
1865 * from parsing capabilities and use this to calculate the number of resources
1866 * per PF based on the max value passed in.
1868 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1872 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1873 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1874 ICE_CAPS_VALID_FUNCS_M);
1883 * ice_parse_caps - parse function/device capabilities
1884 * @hw: pointer to the HW struct
1885 * @buf: pointer to a buffer containing function/device capability records
1886 * @cap_count: number of capability records in the list
1887 * @opc: type of capabilities list to parse
1889 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1892 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1893 enum ice_adminq_opc opc)
1895 struct ice_aqc_list_caps_elem *cap_resp;
1896 struct ice_hw_func_caps *func_p = NULL;
1897 struct ice_hw_dev_caps *dev_p = NULL;
1898 struct ice_hw_common_caps *caps;
1904 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1906 if (opc == ice_aqc_opc_list_dev_caps) {
1907 dev_p = &hw->dev_caps;
1908 caps = &dev_p->common_cap;
1909 } else if (opc == ice_aqc_opc_list_func_caps) {
1910 func_p = &hw->func_caps;
1911 caps = &func_p->common_cap;
1913 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1917 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1918 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1919 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1920 u32 number = LE32_TO_CPU(cap_resp->number);
1921 u16 cap = LE16_TO_CPU(cap_resp->cap);
1924 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1925 caps->valid_functions = number;
1926 ice_debug(hw, ICE_DBG_INIT,
1927 "HW caps: Valid Functions = %d\n",
1928 caps->valid_functions);
1930 case ICE_AQC_CAPS_VSI:
1932 dev_p->num_vsi_allocd_to_host = number;
1933 ice_debug(hw, ICE_DBG_INIT,
1934 "HW caps: Dev.VSI cnt = %d\n",
1935 dev_p->num_vsi_allocd_to_host);
1936 } else if (func_p) {
1937 func_p->guar_num_vsi =
1938 ice_get_num_per_func(hw, ICE_MAX_VSI);
1939 ice_debug(hw, ICE_DBG_INIT,
1940 "HW caps: Func.VSI cnt = %d\n",
1944 case ICE_AQC_CAPS_DCB:
1945 caps->dcb = (number == 1);
1946 caps->active_tc_bitmap = logical_id;
1947 caps->maxtc = phys_id;
1948 ice_debug(hw, ICE_DBG_INIT,
1949 "HW caps: DCB = %d\n", caps->dcb);
1950 ice_debug(hw, ICE_DBG_INIT,
1951 "HW caps: Active TC bitmap = %d\n",
1952 caps->active_tc_bitmap);
1953 ice_debug(hw, ICE_DBG_INIT,
1954 "HW caps: TC Max = %d\n", caps->maxtc);
1956 case ICE_AQC_CAPS_RSS:
1957 caps->rss_table_size = number;
1958 caps->rss_table_entry_width = logical_id;
1959 ice_debug(hw, ICE_DBG_INIT,
1960 "HW caps: RSS table size = %d\n",
1961 caps->rss_table_size);
1962 ice_debug(hw, ICE_DBG_INIT,
1963 "HW caps: RSS table width = %d\n",
1964 caps->rss_table_entry_width);
1966 case ICE_AQC_CAPS_RXQS:
1967 caps->num_rxq = number;
1968 caps->rxq_first_id = phys_id;
1969 ice_debug(hw, ICE_DBG_INIT,
1970 "HW caps: Num Rx Qs = %d\n", caps->num_rxq);
1971 ice_debug(hw, ICE_DBG_INIT,
1972 "HW caps: Rx first queue ID = %d\n",
1973 caps->rxq_first_id);
1975 case ICE_AQC_CAPS_TXQS:
1976 caps->num_txq = number;
1977 caps->txq_first_id = phys_id;
1978 ice_debug(hw, ICE_DBG_INIT,
1979 "HW caps: Num Tx Qs = %d\n", caps->num_txq);
1980 ice_debug(hw, ICE_DBG_INIT,
1981 "HW caps: Tx first queue ID = %d\n",
1982 caps->txq_first_id);
1984 case ICE_AQC_CAPS_MSIX:
1985 caps->num_msix_vectors = number;
1986 caps->msix_vector_first_id = phys_id;
1987 ice_debug(hw, ICE_DBG_INIT,
1988 "HW caps: MSIX vector count = %d\n",
1989 caps->num_msix_vectors);
1990 ice_debug(hw, ICE_DBG_INIT,
1991 "HW caps: MSIX first vector index = %d\n",
1992 caps->msix_vector_first_id);
1994 case ICE_AQC_CAPS_FD:
1999 dev_p->num_flow_director_fltr = number;
2000 ice_debug(hw, ICE_DBG_INIT,
2001 "HW caps: Dev.fd_fltr =%d\n",
2002 dev_p->num_flow_director_fltr);
2005 reg_val = rd32(hw, GLQF_FD_SIZE);
2006 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2007 GLQF_FD_SIZE_FD_GSIZE_S;
2008 func_p->fd_fltr_guar =
2009 ice_get_num_per_func(hw, val);
2010 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2011 GLQF_FD_SIZE_FD_BSIZE_S;
2012 func_p->fd_fltr_best_effort = val;
2013 ice_debug(hw, ICE_DBG_INIT,
2014 "HW:func.fd_fltr guar= %d\n",
2015 func_p->fd_fltr_guar);
2016 ice_debug(hw, ICE_DBG_INIT,
2017 "HW:func.fd_fltr best effort=%d\n",
2018 func_p->fd_fltr_best_effort);
2022 case ICE_AQC_CAPS_MAX_MTU:
2023 caps->max_mtu = number;
2025 ice_debug(hw, ICE_DBG_INIT,
2026 "HW caps: Dev.MaxMTU = %d\n",
2029 ice_debug(hw, ICE_DBG_INIT,
2030 "HW caps: func.MaxMTU = %d\n",
2034 ice_debug(hw, ICE_DBG_INIT,
2035 "HW caps: Unknown capability[%d]: 0x%x\n", i,
2043 * ice_aq_discover_caps - query function/device capabilities
2044 * @hw: pointer to the HW struct
2045 * @buf: a virtual buffer to hold the capabilities
2046 * @buf_size: Size of the virtual buffer
2047 * @cap_count: cap count needed if AQ err==ENOMEM
2048 * @opc: capabilities type to discover - pass in the command opcode
2049 * @cd: pointer to command details structure or NULL
2051 * Get the function(0x000a)/device(0x000b) capabilities description from
2054 static enum ice_status
2055 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2056 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2058 struct ice_aqc_list_caps *cmd;
2059 struct ice_aq_desc desc;
2060 enum ice_status status;
2062 cmd = &desc.params.get_cap;
2064 if (opc != ice_aqc_opc_list_func_caps &&
2065 opc != ice_aqc_opc_list_dev_caps)
2066 return ICE_ERR_PARAM;
2068 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2070 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2072 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
2073 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
2074 *cap_count = LE32_TO_CPU(cmd->count);
2079 * ice_discover_caps - get info about the HW
2080 * @hw: pointer to the hardware structure
2081 * @opc: capabilities type to discover - pass in the command opcode
2083 static enum ice_status
2084 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
2086 enum ice_status status;
2091 /* The driver doesn't know how many capabilities the device will return
2092 * so the buffer size required isn't known ahead of time. The driver
2093 * starts with cbuf_len and if this turns out to be insufficient, the
2094 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2095 * The driver then allocates the buffer based on the count and retries
2096 * the operation. So it follows that the retry count is 2.
2098 #define ICE_GET_CAP_BUF_COUNT 40
2099 #define ICE_GET_CAP_RETRY_COUNT 2
2101 cap_count = ICE_GET_CAP_BUF_COUNT;
2102 retries = ICE_GET_CAP_RETRY_COUNT;
2107 cbuf_len = (u16)(cap_count *
2108 sizeof(struct ice_aqc_list_caps_elem));
2109 cbuf = ice_malloc(hw, cbuf_len);
2111 return ICE_ERR_NO_MEMORY;
2113 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2117 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2120 /* If ENOMEM is returned, try again with bigger buffer */
2121 } while (--retries);
2127 * ice_get_caps - get info about the HW
2128 * @hw: pointer to the hardware structure
2130 enum ice_status ice_get_caps(struct ice_hw *hw)
2132 enum ice_status status;
2134 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2136 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2142 * ice_aq_manage_mac_write - manage MAC address write command
2143 * @hw: pointer to the HW struct
2144 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2145 * @flags: flags to control write behavior
2146 * @cd: pointer to command details structure or NULL
2148 * This function is used to write MAC address to the NVM (0x0108).
2151 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2152 struct ice_sq_cd *cd)
2154 struct ice_aqc_manage_mac_write *cmd;
2155 struct ice_aq_desc desc;
2157 cmd = &desc.params.mac_write;
2158 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2163 /* Prep values for flags, sah, sal */
2164 cmd->sah = HTONS(*((const u16 *)mac_addr));
2165 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
2167 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2171 * ice_aq_clear_pxe_mode
2172 * @hw: pointer to the HW struct
2174 * Tell the firmware that the driver is taking over from PXE (0x0110).
2176 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2178 struct ice_aq_desc desc;
2180 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2181 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2183 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2187 * ice_clear_pxe_mode - clear pxe operations mode
2188 * @hw: pointer to the HW struct
2190 * Make sure all PXE mode settings are cleared, including things
2191 * like descriptor fetch/write-back mode.
2193 void ice_clear_pxe_mode(struct ice_hw *hw)
2195 if (ice_check_sq_alive(hw, &hw->adminq))
2196 ice_aq_clear_pxe_mode(hw);
2201 * ice_get_link_speed_based_on_phy_type - returns link speed
2202 * @phy_type_low: lower part of phy_type
2203 * @phy_type_high: higher part of phy_type
2205 * This helper function will convert an entry in PHY type structure
2206 * [phy_type_low, phy_type_high] to its corresponding link speed.
2207 * Note: In the structure of [phy_type_low, phy_type_high], there should
2208 * be one bit set, as this function will convert one PHY type to its
2210 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2211 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2214 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2216 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2217 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2219 switch (phy_type_low) {
2220 case ICE_PHY_TYPE_LOW_100BASE_TX:
2221 case ICE_PHY_TYPE_LOW_100M_SGMII:
2222 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2224 case ICE_PHY_TYPE_LOW_1000BASE_T:
2225 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2226 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2227 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2228 case ICE_PHY_TYPE_LOW_1G_SGMII:
2229 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2231 case ICE_PHY_TYPE_LOW_2500BASE_T:
2232 case ICE_PHY_TYPE_LOW_2500BASE_X:
2233 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2234 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2236 case ICE_PHY_TYPE_LOW_5GBASE_T:
2237 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2238 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2240 case ICE_PHY_TYPE_LOW_10GBASE_T:
2241 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2242 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2243 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2244 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2245 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2246 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2247 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2249 case ICE_PHY_TYPE_LOW_25GBASE_T:
2250 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2251 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2252 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2253 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2254 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2255 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2256 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2257 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2258 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2259 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2260 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2262 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2263 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2264 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2265 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2266 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2267 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2268 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2270 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2271 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2272 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2273 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2274 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2275 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2276 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2277 case ICE_PHY_TYPE_LOW_50G_AUI2:
2278 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2279 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2280 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2281 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2282 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2283 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2284 case ICE_PHY_TYPE_LOW_50G_AUI1:
2285 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2287 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2288 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2289 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2290 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2291 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2292 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2293 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2294 case ICE_PHY_TYPE_LOW_100G_AUI4:
2295 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2296 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2297 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2298 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2299 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2300 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2303 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2307 switch (phy_type_high) {
2308 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2309 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2310 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2311 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2312 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2313 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2316 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2320 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2321 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2322 return ICE_AQ_LINK_SPEED_UNKNOWN;
2323 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2324 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2325 return ICE_AQ_LINK_SPEED_UNKNOWN;
2326 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2327 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2328 return speed_phy_type_low;
2330 return speed_phy_type_high;
2334 * ice_update_phy_type
2335 * @phy_type_low: pointer to the lower part of phy_type
2336 * @phy_type_high: pointer to the higher part of phy_type
2337 * @link_speeds_bitmap: targeted link speeds bitmap
2339 * Note: For the link_speeds_bitmap structure, you can check it at
2340 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2341 * link_speeds_bitmap include multiple speeds.
2343 * Each entry in this [phy_type_low, phy_type_high] structure will
2344 * present a certain link speed. This helper function will turn on bits
2345 * in [phy_type_low, phy_type_high] structure based on the value of
2346 * link_speeds_bitmap input parameter.
2349 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2350 u16 link_speeds_bitmap)
2352 u16 speed = ICE_AQ_LINK_SPEED_UNKNOWN;
2357 /* We first check with low part of phy_type */
2358 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2359 pt_low = BIT_ULL(index);
2360 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2362 if (link_speeds_bitmap & speed)
2363 *phy_type_low |= BIT_ULL(index);
2366 /* We then check with high part of phy_type */
2367 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2368 pt_high = BIT_ULL(index);
2369 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2371 if (link_speeds_bitmap & speed)
2372 *phy_type_high |= BIT_ULL(index);
2377 * ice_aq_set_phy_cfg
2378 * @hw: pointer to the HW struct
2379 * @lport: logical port number
2380 * @cfg: structure with PHY configuration data to be set
2381 * @cd: pointer to command details structure or NULL
2383 * Set the various PHY configuration parameters supported on the Port.
2384 * One or more of the Set PHY config parameters may be ignored in an MFP
2385 * mode as the PF may not have the privilege to set some of the PHY Config
2386 * parameters. This status will be indicated by the command response (0x0601).
2389 ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,
2390 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2392 struct ice_aq_desc desc;
2395 return ICE_ERR_PARAM;
2397 /* Ensure that only valid bits of cfg->caps can be turned on. */
2398 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2399 ice_debug(hw, ICE_DBG_PHY,
2400 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2403 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2406 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2407 desc.params.set_phy.lport_num = lport;
2408 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2410 return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2414 * ice_update_link_info - update status of the HW network link
2415 * @pi: port info structure of the interested logical port
2417 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2419 struct ice_aqc_get_phy_caps_data *pcaps;
2420 struct ice_phy_info *phy_info;
2421 enum ice_status status;
2425 return ICE_ERR_PARAM;
2429 pcaps = (struct ice_aqc_get_phy_caps_data *)
2430 ice_malloc(hw, sizeof(*pcaps));
2432 return ICE_ERR_NO_MEMORY;
2434 phy_info = &pi->phy;
2435 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2439 if (phy_info->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) {
2440 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG,
2445 ice_memcpy(phy_info->link_info.module_type, &pcaps->module_type,
2446 sizeof(phy_info->link_info.module_type),
2447 ICE_NONDMA_TO_NONDMA);
2450 ice_free(hw, pcaps);
2456 * @pi: port information structure
2457 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2458 * @ena_auto_link_update: enable automatic link update
2460 * Set the requested flow control mode.
2463 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2465 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2466 struct ice_aqc_get_phy_caps_data *pcaps;
2467 enum ice_status status;
2468 u8 pause_mask = 0x0;
2472 return ICE_ERR_PARAM;
2474 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2476 switch (pi->fc.req_mode) {
2478 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2479 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2481 case ICE_FC_RX_PAUSE:
2482 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2484 case ICE_FC_TX_PAUSE:
2485 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2491 pcaps = (struct ice_aqc_get_phy_caps_data *)
2492 ice_malloc(hw, sizeof(*pcaps));
2494 return ICE_ERR_NO_MEMORY;
2496 /* Get the current PHY config */
2497 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2500 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2504 /* clear the old pause settings */
2505 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2506 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2507 /* set the new capabilities */
2508 cfg.caps |= pause_mask;
2509 /* If the capabilities have changed, then set the new config */
2510 if (cfg.caps != pcaps->caps) {
2511 int retry_count, retry_max = 10;
2513 /* Auto restart link so settings take effect */
2514 if (ena_auto_link_update)
2515 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2516 /* Copy over all the old settings */
2517 cfg.phy_type_high = pcaps->phy_type_high;
2518 cfg.phy_type_low = pcaps->phy_type_low;
2519 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2520 cfg.eee_cap = pcaps->eee_cap;
2521 cfg.eeer_value = pcaps->eeer_value;
2522 cfg.link_fec_opt = pcaps->link_fec_options;
2524 status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL);
2526 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2530 /* Update the link info
2531 * It sometimes takes a really long time for link to
2532 * come back from the atomic reset. Thus, we wait a
2535 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2536 status = ice_update_link_info(pi);
2538 if (status == ICE_SUCCESS)
2541 ice_msec_delay(100, true);
2545 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2549 ice_free(hw, pcaps);
2554 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2555 * @caps: PHY ability structure to copy date from
2556 * @cfg: PHY configuration structure to copy data to
2558 * Helper function to copy AQC PHY get ability data to PHY set configuration
2562 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2563 struct ice_aqc_set_phy_cfg_data *cfg)
2568 cfg->phy_type_low = caps->phy_type_low;
2569 cfg->phy_type_high = caps->phy_type_high;
2570 cfg->caps = caps->caps;
2571 cfg->low_power_ctrl = caps->low_power_ctrl;
2572 cfg->eee_cap = caps->eee_cap;
2573 cfg->eeer_value = caps->eeer_value;
2574 cfg->link_fec_opt = caps->link_fec_options;
2578 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2579 * @cfg: PHY configuration data to set FEC mode
2580 * @fec: FEC mode to configure
2582 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2583 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2584 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2587 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2591 /* Clear auto FEC and RS bits, and AND BASE-R ability
2592 * bits and OR request bits.
2594 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2595 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2596 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2597 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2598 ICE_AQC_PHY_FEC_25G_KR_REQ;
2601 /* Clear auto FEC and BASE-R bits, and AND RS ability
2602 * bits and OR request bits.
2604 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2605 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2606 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2607 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2610 /* Clear auto FEC and all FEC option bits. */
2611 cfg->caps &= ~ICE_AQC_PHY_EN_AUTO_FEC;
2612 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2615 /* AND auto FEC bit, and all caps bits. */
2616 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2622 * ice_get_link_status - get status of the HW network link
2623 * @pi: port information structure
2624 * @link_up: pointer to bool (true/false = linkup/linkdown)
2626 * Variable link_up is true if link is up, false if link is down.
2627 * The variable link_up is invalid if status is non zero. As a
2628 * result of this call, link status reporting becomes enabled
2630 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2632 struct ice_phy_info *phy_info;
2633 enum ice_status status = ICE_SUCCESS;
2635 if (!pi || !link_up)
2636 return ICE_ERR_PARAM;
2638 phy_info = &pi->phy;
2640 if (phy_info->get_link_info) {
2641 status = ice_update_link_info(pi);
2644 ice_debug(pi->hw, ICE_DBG_LINK,
2645 "get link status error, status = %d\n",
2649 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2655 * ice_aq_set_link_restart_an
2656 * @pi: pointer to the port information structure
2657 * @ena_link: if true: enable link, if false: disable link
2658 * @cd: pointer to command details structure or NULL
2660 * Sets up the link and restarts the Auto-Negotiation over the link.
2663 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2664 struct ice_sq_cd *cd)
2666 struct ice_aqc_restart_an *cmd;
2667 struct ice_aq_desc desc;
2669 cmd = &desc.params.restart_an;
2671 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2673 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2674 cmd->lport_num = pi->lport;
2676 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2678 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2680 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2684 * ice_aq_set_event_mask
2685 * @hw: pointer to the HW struct
2686 * @port_num: port number of the physical function
2687 * @mask: event mask to be set
2688 * @cd: pointer to command details structure or NULL
2690 * Set event mask (0x0613)
2693 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2694 struct ice_sq_cd *cd)
2696 struct ice_aqc_set_event_mask *cmd;
2697 struct ice_aq_desc desc;
2699 cmd = &desc.params.set_event_mask;
2701 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2703 cmd->lport_num = port_num;
2705 cmd->event_mask = CPU_TO_LE16(mask);
2706 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2710 * ice_aq_set_mac_loopback
2711 * @hw: pointer to the HW struct
2712 * @ena_lpbk: Enable or Disable loopback
2713 * @cd: pointer to command details structure or NULL
2715 * Enable/disable loopback on a given port
2718 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2720 struct ice_aqc_set_mac_lb *cmd;
2721 struct ice_aq_desc desc;
2723 cmd = &desc.params.set_mac_lb;
2725 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2727 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2729 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2734 * ice_aq_set_port_id_led
2735 * @pi: pointer to the port information
2736 * @is_orig_mode: is this LED set to original mode (by the net-list)
2737 * @cd: pointer to command details structure or NULL
2739 * Set LED value for the given port (0x06e9)
2742 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2743 struct ice_sq_cd *cd)
2745 struct ice_aqc_set_port_id_led *cmd;
2746 struct ice_hw *hw = pi->hw;
2747 struct ice_aq_desc desc;
2749 cmd = &desc.params.set_port_id_led;
2751 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2755 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2757 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2759 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2763 * __ice_aq_get_set_rss_lut
2764 * @hw: pointer to the hardware structure
2765 * @vsi_id: VSI FW index
2766 * @lut_type: LUT table type
2767 * @lut: pointer to the LUT buffer provided by the caller
2768 * @lut_size: size of the LUT buffer
2769 * @glob_lut_idx: global LUT index
2770 * @set: set true to set the table, false to get the table
2772 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2774 static enum ice_status
2775 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2776 u16 lut_size, u8 glob_lut_idx, bool set)
2778 struct ice_aqc_get_set_rss_lut *cmd_resp;
2779 struct ice_aq_desc desc;
2780 enum ice_status status;
2783 cmd_resp = &desc.params.get_set_rss_lut;
2786 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2787 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2789 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2792 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2793 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2794 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2795 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2798 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2799 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2800 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2801 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2802 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2805 status = ICE_ERR_PARAM;
2806 goto ice_aq_get_set_rss_lut_exit;
2809 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2810 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2811 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2814 goto ice_aq_get_set_rss_lut_send;
2815 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2817 goto ice_aq_get_set_rss_lut_send;
2819 goto ice_aq_get_set_rss_lut_send;
2822 /* LUT size is only valid for Global and PF table types */
2824 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2825 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
2826 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2827 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2829 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
2830 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2831 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2832 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2834 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
2835 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2836 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
2837 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2838 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2843 status = ICE_ERR_PARAM;
2844 goto ice_aq_get_set_rss_lut_exit;
2847 ice_aq_get_set_rss_lut_send:
2848 cmd_resp->flags = CPU_TO_LE16(flags);
2849 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
2851 ice_aq_get_set_rss_lut_exit:
2856 * ice_aq_get_rss_lut
2857 * @hw: pointer to the hardware structure
2858 * @vsi_handle: software VSI handle
2859 * @lut_type: LUT table type
2860 * @lut: pointer to the LUT buffer provided by the caller
2861 * @lut_size: size of the LUT buffer
2863 * get the RSS lookup table, PF or VSI type
2866 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2867 u8 *lut, u16 lut_size)
2869 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2870 return ICE_ERR_PARAM;
2872 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2873 lut_type, lut, lut_size, 0, false);
2877 * ice_aq_set_rss_lut
2878 * @hw: pointer to the hardware structure
2879 * @vsi_handle: software VSI handle
2880 * @lut_type: LUT table type
2881 * @lut: pointer to the LUT buffer provided by the caller
2882 * @lut_size: size of the LUT buffer
2884 * set the RSS lookup table, PF or VSI type
2887 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2888 u8 *lut, u16 lut_size)
2890 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2891 return ICE_ERR_PARAM;
2893 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2894 lut_type, lut, lut_size, 0, true);
2898 * __ice_aq_get_set_rss_key
2899 * @hw: pointer to the HW struct
2900 * @vsi_id: VSI FW index
2901 * @key: pointer to key info struct
2902 * @set: set true to set the key, false to get the key
2904 * get (0x0B04) or set (0x0B02) the RSS key per VSI
2907 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
2908 struct ice_aqc_get_set_rss_keys *key,
2911 struct ice_aqc_get_set_rss_key *cmd_resp;
2912 u16 key_size = sizeof(*key);
2913 struct ice_aq_desc desc;
2915 cmd_resp = &desc.params.get_set_rss_key;
2918 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
2919 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2921 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
2924 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2925 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
2926 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
2927 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
2929 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
2933 * ice_aq_get_rss_key
2934 * @hw: pointer to the HW struct
2935 * @vsi_handle: software VSI handle
2936 * @key: pointer to key info struct
2938 * get the RSS key per VSI
2941 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
2942 struct ice_aqc_get_set_rss_keys *key)
2944 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
2945 return ICE_ERR_PARAM;
2947 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2952 * ice_aq_set_rss_key
2953 * @hw: pointer to the HW struct
2954 * @vsi_handle: software VSI handle
2955 * @keys: pointer to key info struct
2957 * set the RSS key per VSI
2960 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
2961 struct ice_aqc_get_set_rss_keys *keys)
2963 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
2964 return ICE_ERR_PARAM;
2966 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2971 * ice_aq_add_lan_txq
2972 * @hw: pointer to the hardware structure
2973 * @num_qgrps: Number of added queue groups
2974 * @qg_list: list of queue groups to be added
2975 * @buf_size: size of buffer for indirect command
2976 * @cd: pointer to command details structure or NULL
2978 * Add Tx LAN queue (0x0C30)
2981 * Prior to calling add Tx LAN queue:
2982 * Initialize the following as part of the Tx queue context:
2983 * Completion queue ID if the queue uses Completion queue, Quanta profile,
2984 * Cache profile and Packet shaper profile.
2986 * After add Tx LAN queue AQ command is completed:
2987 * Interrupts should be associated with specific queues,
2988 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
2992 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
2993 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
2994 struct ice_sq_cd *cd)
2996 u16 i, sum_header_size, sum_q_size = 0;
2997 struct ice_aqc_add_tx_qgrp *list;
2998 struct ice_aqc_add_txqs *cmd;
2999 struct ice_aq_desc desc;
3001 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_add_lan_txq");
3003 cmd = &desc.params.add_txqs;
3005 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3008 return ICE_ERR_PARAM;
3010 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3011 return ICE_ERR_PARAM;
3013 sum_header_size = num_qgrps *
3014 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3017 for (i = 0; i < num_qgrps; i++) {
3018 struct ice_aqc_add_txqs_perq *q = list->txqs;
3020 sum_q_size += list->num_txqs * sizeof(*q);
3021 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3024 if (buf_size != (sum_header_size + sum_q_size))
3025 return ICE_ERR_PARAM;
3027 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3029 cmd->num_qgrps = num_qgrps;
3031 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3035 * ice_aq_dis_lan_txq
3036 * @hw: pointer to the hardware structure
3037 * @num_qgrps: number of groups in the list
3038 * @qg_list: the list of groups to disable
3039 * @buf_size: the total size of the qg_list buffer in bytes
3040 * @rst_src: if called due to reset, specifies the reset source
3041 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3042 * @cd: pointer to command details structure or NULL
3044 * Disable LAN Tx queue (0x0C31)
3046 static enum ice_status
3047 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3048 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3049 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3050 struct ice_sq_cd *cd)
3052 struct ice_aqc_dis_txqs *cmd;
3053 struct ice_aq_desc desc;
3054 enum ice_status status;
3057 ice_debug(hw, ICE_DBG_TRACE, "ice_aq_dis_lan_txq");
3058 cmd = &desc.params.dis_txqs;
3059 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3061 /* qg_list can be NULL only in VM/VF reset flow */
3062 if (!qg_list && !rst_src)
3063 return ICE_ERR_PARAM;
3065 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3066 return ICE_ERR_PARAM;
3068 cmd->num_entries = num_qgrps;
3070 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3071 ICE_AQC_Q_DIS_TIMEOUT_M);
3075 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3076 cmd->vmvf_and_timeout |=
3077 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3084 /* flush pipe on time out */
3085 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3086 /* If no queue group info, we are in a reset flow. Issue the AQ */
3090 /* set RD bit to indicate that command buffer is provided by the driver
3091 * and it needs to be read by the firmware
3093 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3095 for (i = 0; i < num_qgrps; ++i) {
3096 /* Calculate the size taken up by the queue IDs in this group */
3097 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3099 /* Add the size of the group header */
3100 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3102 /* If the num of queues is even, add 2 bytes of padding */
3103 if ((qg_list[i].num_qs % 2) == 0)
3108 return ICE_ERR_PARAM;
3111 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3114 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3115 vmvf_num, hw->adminq.sq_last_status);
3117 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3118 LE16_TO_CPU(qg_list[0].q_id[0]),
3119 hw->adminq.sq_last_status);
3125 /* End of FW Admin Queue command wrappers */
3128 * ice_write_byte - write a byte to a packed context structure
3129 * @src_ctx: the context structure to read from
3130 * @dest_ctx: the context to be written to
3131 * @ce_info: a description of the struct to be filled
3134 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3136 u8 src_byte, dest_byte, mask;
3140 /* copy from the next struct field */
3141 from = src_ctx + ce_info->offset;
3143 /* prepare the bits and mask */
3144 shift_width = ce_info->lsb % 8;
3145 mask = (u8)(BIT(ce_info->width) - 1);
3150 /* shift to correct alignment */
3151 mask <<= shift_width;
3152 src_byte <<= shift_width;
3154 /* get the current bits from the target bit string */
3155 dest = dest_ctx + (ce_info->lsb / 8);
3157 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3159 dest_byte &= ~mask; /* get the bits not changing */
3160 dest_byte |= src_byte; /* add in the new bits */
3162 /* put it all back */
3163 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3167 * ice_write_word - write a word to a packed context structure
3168 * @src_ctx: the context structure to read from
3169 * @dest_ctx: the context to be written to
3170 * @ce_info: a description of the struct to be filled
3173 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3180 /* copy from the next struct field */
3181 from = src_ctx + ce_info->offset;
3183 /* prepare the bits and mask */
3184 shift_width = ce_info->lsb % 8;
3185 mask = BIT(ce_info->width) - 1;
3187 /* don't swizzle the bits until after the mask because the mask bits
3188 * will be in a different bit position on big endian machines
3190 src_word = *(u16 *)from;
3193 /* shift to correct alignment */
3194 mask <<= shift_width;
3195 src_word <<= shift_width;
3197 /* get the current bits from the target bit string */
3198 dest = dest_ctx + (ce_info->lsb / 8);
3200 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3202 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3203 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3205 /* put it all back */
3206 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3210 * ice_write_dword - write a dword to a packed context structure
3211 * @src_ctx: the context structure to read from
3212 * @dest_ctx: the context to be written to
3213 * @ce_info: a description of the struct to be filled
3216 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3218 u32 src_dword, mask;
3223 /* copy from the next struct field */
3224 from = src_ctx + ce_info->offset;
3226 /* prepare the bits and mask */
3227 shift_width = ce_info->lsb % 8;
3229 /* if the field width is exactly 32 on an x86 machine, then the shift
3230 * operation will not work because the SHL instructions count is masked
3231 * to 5 bits so the shift will do nothing
3233 if (ce_info->width < 32)
3234 mask = BIT(ce_info->width) - 1;
3238 /* don't swizzle the bits until after the mask because the mask bits
3239 * will be in a different bit position on big endian machines
3241 src_dword = *(u32 *)from;
3244 /* shift to correct alignment */
3245 mask <<= shift_width;
3246 src_dword <<= shift_width;
3248 /* get the current bits from the target bit string */
3249 dest = dest_ctx + (ce_info->lsb / 8);
3251 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3253 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3254 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3256 /* put it all back */
3257 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3261 * ice_write_qword - write a qword to a packed context structure
3262 * @src_ctx: the context structure to read from
3263 * @dest_ctx: the context to be written to
3264 * @ce_info: a description of the struct to be filled
3267 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3269 u64 src_qword, mask;
3274 /* copy from the next struct field */
3275 from = src_ctx + ce_info->offset;
3277 /* prepare the bits and mask */
3278 shift_width = ce_info->lsb % 8;
3280 /* if the field width is exactly 64 on an x86 machine, then the shift
3281 * operation will not work because the SHL instructions count is masked
3282 * to 6 bits so the shift will do nothing
3284 if (ce_info->width < 64)
3285 mask = BIT_ULL(ce_info->width) - 1;
3289 /* don't swizzle the bits until after the mask because the mask bits
3290 * will be in a different bit position on big endian machines
3292 src_qword = *(u64 *)from;
3295 /* shift to correct alignment */
3296 mask <<= shift_width;
3297 src_qword <<= shift_width;
3299 /* get the current bits from the target bit string */
3300 dest = dest_ctx + (ce_info->lsb / 8);
3302 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3304 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3305 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3307 /* put it all back */
3308 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3312 * ice_set_ctx - set context bits in packed structure
3313 * @src_ctx: pointer to a generic non-packed context structure
3314 * @dest_ctx: pointer to memory for the packed structure
3315 * @ce_info: a description of the structure to be transformed
3318 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3322 for (f = 0; ce_info[f].width; f++) {
3323 /* We have to deal with each element of the FW response
3324 * using the correct size so that we are correct regardless
3325 * of the endianness of the machine.
3327 switch (ce_info[f].size_of) {
3329 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3332 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3335 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3338 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3341 return ICE_ERR_INVAL_SIZE;
3352 * ice_read_byte - read context byte into struct
3353 * @src_ctx: the context structure to read from
3354 * @dest_ctx: the context to be written to
3355 * @ce_info: a description of the struct to be filled
3358 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3364 /* prepare the bits and mask */
3365 shift_width = ce_info->lsb % 8;
3366 mask = (u8)(BIT(ce_info->width) - 1);
3368 /* shift to correct alignment */
3369 mask <<= shift_width;
3371 /* get the current bits from the src bit string */
3372 src = src_ctx + (ce_info->lsb / 8);
3374 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3376 dest_byte &= ~(mask);
3378 dest_byte >>= shift_width;
3380 /* get the address from the struct field */
3381 target = dest_ctx + ce_info->offset;
3383 /* put it back in the struct */
3384 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3388 * ice_read_word - read context word into struct
3389 * @src_ctx: the context structure to read from
3390 * @dest_ctx: the context to be written to
3391 * @ce_info: a description of the struct to be filled
3394 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3396 u16 dest_word, mask;
3401 /* prepare the bits and mask */
3402 shift_width = ce_info->lsb % 8;
3403 mask = BIT(ce_info->width) - 1;
3405 /* shift to correct alignment */
3406 mask <<= shift_width;
3408 /* get the current bits from the src bit string */
3409 src = src_ctx + (ce_info->lsb / 8);
3411 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3413 /* the data in the memory is stored as little endian so mask it
3416 src_word &= ~(CPU_TO_LE16(mask));
3418 /* get the data back into host order before shifting */
3419 dest_word = LE16_TO_CPU(src_word);
3421 dest_word >>= shift_width;
3423 /* get the address from the struct field */
3424 target = dest_ctx + ce_info->offset;
3426 /* put it back in the struct */
3427 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3431 * ice_read_dword - read context dword into struct
3432 * @src_ctx: the context structure to read from
3433 * @dest_ctx: the context to be written to
3434 * @ce_info: a description of the struct to be filled
3437 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3439 u32 dest_dword, mask;
3444 /* prepare the bits and mask */
3445 shift_width = ce_info->lsb % 8;
3447 /* if the field width is exactly 32 on an x86 machine, then the shift
3448 * operation will not work because the SHL instructions count is masked
3449 * to 5 bits so the shift will do nothing
3451 if (ce_info->width < 32)
3452 mask = BIT(ce_info->width) - 1;
3456 /* shift to correct alignment */
3457 mask <<= shift_width;
3459 /* get the current bits from the src bit string */
3460 src = src_ctx + (ce_info->lsb / 8);
3462 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3464 /* the data in the memory is stored as little endian so mask it
3467 src_dword &= ~(CPU_TO_LE32(mask));
3469 /* get the data back into host order before shifting */
3470 dest_dword = LE32_TO_CPU(src_dword);
3472 dest_dword >>= shift_width;
3474 /* get the address from the struct field */
3475 target = dest_ctx + ce_info->offset;
3477 /* put it back in the struct */
3478 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3482 * ice_read_qword - read context qword into struct
3483 * @src_ctx: the context structure to read from
3484 * @dest_ctx: the context to be written to
3485 * @ce_info: a description of the struct to be filled
3488 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3490 u64 dest_qword, mask;
3495 /* prepare the bits and mask */
3496 shift_width = ce_info->lsb % 8;
3498 /* if the field width is exactly 64 on an x86 machine, then the shift
3499 * operation will not work because the SHL instructions count is masked
3500 * to 6 bits so the shift will do nothing
3502 if (ce_info->width < 64)
3503 mask = BIT_ULL(ce_info->width) - 1;
3507 /* shift to correct alignment */
3508 mask <<= shift_width;
3510 /* get the current bits from the src bit string */
3511 src = src_ctx + (ce_info->lsb / 8);
3513 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3515 /* the data in the memory is stored as little endian so mask it
3518 src_qword &= ~(CPU_TO_LE64(mask));
3520 /* get the data back into host order before shifting */
3521 dest_qword = LE64_TO_CPU(src_qword);
3523 dest_qword >>= shift_width;
3525 /* get the address from the struct field */
3526 target = dest_ctx + ce_info->offset;
3528 /* put it back in the struct */
3529 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3533 * ice_get_ctx - extract context bits from a packed structure
3534 * @src_ctx: pointer to a generic packed context structure
3535 * @dest_ctx: pointer to a generic non-packed context structure
3536 * @ce_info: a description of the structure to be read from
3539 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3543 for (f = 0; ce_info[f].width; f++) {
3544 switch (ce_info[f].size_of) {
3546 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3549 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3552 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3555 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3558 /* nothing to do, just keep going */
3567 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3568 * @hw: pointer to the HW struct
3569 * @vsi_handle: software VSI handle
3571 * @q_handle: software queue handle
3573 static struct ice_q_ctx *
3574 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3576 struct ice_vsi_ctx *vsi;
3577 struct ice_q_ctx *q_ctx;
3579 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3582 if (q_handle >= vsi->num_lan_q_entries[tc])
3584 if (!vsi->lan_q_ctx[tc])
3586 q_ctx = vsi->lan_q_ctx[tc];
3587 return &q_ctx[q_handle];
3592 * @pi: port information structure
3593 * @vsi_handle: software VSI handle
3595 * @q_handle: software queue handle
3596 * @num_qgrps: Number of added queue groups
3597 * @buf: list of queue groups to be added
3598 * @buf_size: size of buffer for indirect command
3599 * @cd: pointer to command details structure or NULL
3601 * This function adds one LAN queue
3604 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3605 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3606 struct ice_sq_cd *cd)
3608 struct ice_aqc_txsched_elem_data node = { 0 };
3609 struct ice_sched_node *parent;
3610 struct ice_q_ctx *q_ctx;
3611 enum ice_status status;
3614 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3617 if (num_qgrps > 1 || buf->num_txqs > 1)
3618 return ICE_ERR_MAX_LIMIT;
3622 if (!ice_is_vsi_valid(hw, vsi_handle))
3623 return ICE_ERR_PARAM;
3625 ice_acquire_lock(&pi->sched_lock);
3627 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3629 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3631 status = ICE_ERR_PARAM;
3635 /* find a parent node */
3636 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3637 ICE_SCHED_NODE_OWNER_LAN);
3639 status = ICE_ERR_PARAM;
3643 buf->parent_teid = parent->info.node_teid;
3644 node.parent_teid = parent->info.node_teid;
3645 /* Mark that the values in the "generic" section as valid. The default
3646 * value in the "generic" section is zero. This means that :
3647 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3648 * - 0 priority among siblings, indicated by Bit 1-3.
3649 * - WFQ, indicated by Bit 4.
3650 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3652 * - Bit 7 is reserved.
3653 * Without setting the generic section as valid in valid_sections, the
3654 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3656 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3658 /* add the LAN queue */
3659 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3660 if (status != ICE_SUCCESS) {
3661 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3662 LE16_TO_CPU(buf->txqs[0].txq_id),
3663 hw->adminq.sq_last_status);
3667 node.node_teid = buf->txqs[0].q_teid;
3668 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3669 q_ctx->q_handle = q_handle;
3671 /* add a leaf node into schduler tree queue layer */
3672 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3675 ice_release_lock(&pi->sched_lock);
3681 * @pi: port information structure
3682 * @vsi_handle: software VSI handle
3684 * @num_queues: number of queues
3685 * @q_handles: pointer to software queue handle array
3686 * @q_ids: pointer to the q_id array
3687 * @q_teids: pointer to queue node teids
3688 * @rst_src: if called due to reset, specifies the reset source
3689 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3690 * @cd: pointer to command details structure or NULL
3692 * This function removes queues and their corresponding nodes in SW DB
3695 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3696 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3697 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3698 struct ice_sq_cd *cd)
3700 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3701 struct ice_aqc_dis_txq_item qg_list;
3702 struct ice_q_ctx *q_ctx;
3705 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3710 /* if queue is disabled already yet the disable queue command
3711 * has to be sent to complete the VF reset, then call
3712 * ice_aq_dis_lan_txq without any queue information
3715 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
3720 ice_acquire_lock(&pi->sched_lock);
3722 for (i = 0; i < num_queues; i++) {
3723 struct ice_sched_node *node;
3725 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3728 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3730 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3734 if (q_ctx->q_handle != q_handles[i]) {
3735 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3736 q_ctx->q_handle, q_handles[i]);
3739 qg_list.parent_teid = node->info.parent_teid;
3741 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
3742 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3743 sizeof(qg_list), rst_src, vmvf_num,
3746 if (status != ICE_SUCCESS)
3748 ice_free_sched_node(pi, node);
3749 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
3751 ice_release_lock(&pi->sched_lock);
3756 * ice_cfg_vsi_qs - configure the new/existing VSI queues
3757 * @pi: port information structure
3758 * @vsi_handle: software VSI handle
3759 * @tc_bitmap: TC bitmap
3760 * @maxqs: max queues array per TC
3761 * @owner: LAN or RDMA
3763 * This function adds/updates the VSI queues per TC.
3765 static enum ice_status
3766 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3767 u16 *maxqs, u8 owner)
3769 enum ice_status status = ICE_SUCCESS;
3772 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3775 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3776 return ICE_ERR_PARAM;
3778 ice_acquire_lock(&pi->sched_lock);
3780 ice_for_each_traffic_class(i) {
3781 /* configuration is possible only if TC node is present */
3782 if (!ice_sched_get_tc_node(pi, i))
3785 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
3786 ice_is_tc_ena(tc_bitmap, i));
3791 ice_release_lock(&pi->sched_lock);
3796 * ice_cfg_vsi_lan - configure VSI LAN queues
3797 * @pi: port information structure
3798 * @vsi_handle: software VSI handle
3799 * @tc_bitmap: TC bitmap
3800 * @max_lanqs: max LAN queues array per TC
3802 * This function adds/updates the VSI LAN queues per TC.
3805 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3808 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
3809 ICE_SCHED_NODE_OWNER_LAN);
3815 * ice_replay_pre_init - replay pre initialization
3816 * @hw: pointer to the HW struct
3818 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
3820 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
3822 struct ice_switch_info *sw = hw->switch_info;
3825 /* Delete old entries from replay filter list head if there is any */
3826 ice_rm_all_sw_replay_rule_info(hw);
3827 /* In start of replay, move entries into replay_rules list, it
3828 * will allow adding rules entries back to filt_rules list,
3829 * which is operational list.
3831 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
3832 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
3833 &sw->recp_list[i].filt_replay_rules);
3834 ice_sched_replay_agg_vsi_preinit(hw);
3836 return ice_sched_replay_tc_node_bw(hw);
3840 * ice_replay_vsi - replay VSI configuration
3841 * @hw: pointer to the HW struct
3842 * @vsi_handle: driver VSI handle
3844 * Restore all VSI configuration after reset. It is required to call this
3845 * function with main VSI first.
3847 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
3849 enum ice_status status;
3851 if (!ice_is_vsi_valid(hw, vsi_handle))
3852 return ICE_ERR_PARAM;
3854 /* Replay pre-initialization if there is any */
3855 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
3856 status = ice_replay_pre_init(hw);
3860 /* Replay per VSI all RSS configurations */
3861 status = ice_replay_rss_cfg(hw, vsi_handle);
3864 /* Replay per VSI all filters */
3865 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
3867 status = ice_replay_vsi_agg(hw, vsi_handle);
3872 * ice_replay_post - post replay configuration cleanup
3873 * @hw: pointer to the HW struct
3875 * Post replay cleanup.
3877 void ice_replay_post(struct ice_hw *hw)
3879 /* Delete old entries from replay filter list head */
3880 ice_rm_all_sw_replay_rule_info(hw);
3881 ice_sched_replay_agg(hw);
3885 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
3886 * @hw: ptr to the hardware info
3887 * @hireg: high 32 bit HW register to read from
3888 * @loreg: low 32 bit HW register to read from
3889 * @prev_stat_loaded: bool to specify if previous stats are loaded
3890 * @prev_stat: ptr to previous loaded stat value
3891 * @cur_stat: ptr to current stat value
3894 ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg,
3895 bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat)
3899 new_data = rd32(hw, loreg);
3900 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
3902 /* device stats are not reset at PFR, they likely will not be zeroed
3903 * when the driver starts. So save the first values read and use them as
3904 * offsets to be subtracted from the raw values in order to report stats
3905 * that count from zero.
3907 if (!prev_stat_loaded)
3908 *prev_stat = new_data;
3909 if (new_data >= *prev_stat)
3910 *cur_stat = new_data - *prev_stat;
3912 /* to manage the potential roll-over */
3913 *cur_stat = (new_data + BIT_ULL(40)) - *prev_stat;
3914 *cur_stat &= 0xFFFFFFFFFFULL;
3918 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
3919 * @hw: ptr to the hardware info
3920 * @reg: HW register to read from
3921 * @prev_stat_loaded: bool to specify if previous stats are loaded
3922 * @prev_stat: ptr to previous loaded stat value
3923 * @cur_stat: ptr to current stat value
3926 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
3927 u64 *prev_stat, u64 *cur_stat)
3931 new_data = rd32(hw, reg);
3933 /* device stats are not reset at PFR, they likely will not be zeroed
3934 * when the driver starts. So save the first values read and use them as
3935 * offsets to be subtracted from the raw values in order to report stats
3936 * that count from zero.
3938 if (!prev_stat_loaded)
3939 *prev_stat = new_data;
3940 if (new_data >= *prev_stat)
3941 *cur_stat = new_data - *prev_stat;
3943 /* to manage the potential roll-over */
3944 *cur_stat = (new_data + BIT_ULL(32)) - *prev_stat;
3949 * ice_sched_query_elem - query element information from HW
3950 * @hw: pointer to the HW struct
3951 * @node_teid: node TEID to be queried
3952 * @buf: buffer to element information
3954 * This function queries HW element information
3957 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
3958 struct ice_aqc_get_elem *buf)
3960 u16 buf_size, num_elem_ret = 0;
3961 enum ice_status status;
3963 buf_size = sizeof(*buf);
3964 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
3965 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
3966 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
3968 if (status != ICE_SUCCESS || num_elem_ret != 1)
3969 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
3974 * ice_is_fw_in_rec_mode
3975 * @hw: pointer to the HW struct
3977 * This function returns true if fw is in recovery mode
3979 bool ice_is_fw_in_rec_mode(struct ice_hw *hw)
3983 /* check the current FW mode */
3984 reg = rd32(hw, GL_MNG_FWSM);
3985 return (reg & GL_MNG_FWSM_FW_MODES_M) > ICE_FW_MODE_DBG;