1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 200
14 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
15 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
16 ((ICE_RX_OPC_MDID << \
17 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
18 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
19 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
20 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
22 #define ICE_PROG_FLEX_ENTRY_EXTRACT(hw, rxdid, protid, off, idx) \
23 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
24 ((ICE_RX_OPC_EXTRACT << \
25 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
26 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
27 (((protid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
28 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M) | \
29 (((off) << GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_S) & \
30 GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_M))
32 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
33 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
34 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
35 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
36 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
37 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
38 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
39 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
40 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
41 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
45 * ice_set_mac_type - Sets MAC type
46 * @hw: pointer to the HW structure
48 * This function sets the MAC type of the adapter based on the
49 * vendor ID and device ID stored in the HW structure.
51 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
53 enum ice_status status = ICE_SUCCESS;
55 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
57 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) {
58 switch (hw->device_id) {
60 hw->mac_type = ICE_MAC_GENERIC;
64 status = ICE_ERR_DEVICE_NOT_SUPPORTED;
67 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n",
68 hw->mac_type, status);
75 * ice_clear_pf_cfg - Clear PF configuration
76 * @hw: pointer to the hardware structure
78 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
79 * configuration, flow director filters, etc.).
81 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
83 struct ice_aq_desc desc;
85 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
87 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
91 * ice_aq_manage_mac_read - manage MAC address read command
92 * @hw: pointer to the HW struct
93 * @buf: a virtual buffer to hold the manage MAC read response
94 * @buf_size: Size of the virtual buffer
95 * @cd: pointer to command details structure or NULL
97 * This function is used to return per PF station MAC address (0x0107).
98 * NOTE: Upon successful completion of this command, MAC address information
99 * is returned in user specified buffer. Please interpret user specified
100 * buffer as "manage_mac_read" response.
101 * Response such as various MAC addresses are stored in HW struct (port.mac)
102 * ice_aq_discover_caps is expected to be called before this function is called.
104 static enum ice_status
105 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
106 struct ice_sq_cd *cd)
108 struct ice_aqc_manage_mac_read_resp *resp;
109 struct ice_aqc_manage_mac_read *cmd;
110 struct ice_aq_desc desc;
111 enum ice_status status;
115 cmd = &desc.params.mac_read;
117 if (buf_size < sizeof(*resp))
118 return ICE_ERR_BUF_TOO_SHORT;
120 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
122 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
126 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
127 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
129 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
130 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
134 /* A single port can report up to two (LAN and WoL) addresses */
135 for (i = 0; i < cmd->num_addr; i++)
136 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
137 ice_memcpy(hw->port_info->mac.lan_addr,
138 resp[i].mac_addr, ETH_ALEN,
140 ice_memcpy(hw->port_info->mac.perm_addr,
142 ETH_ALEN, ICE_DMA_TO_NONDMA);
150 * ice_aq_get_phy_caps - returns PHY capabilities
151 * @pi: port information structure
152 * @qual_mods: report qualified modules
153 * @report_mode: report mode capabilities
154 * @pcaps: structure for PHY capabilities to be filled
155 * @cd: pointer to command details structure or NULL
157 * Returns the various PHY capabilities supported on the Port (0x0600)
160 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
161 struct ice_aqc_get_phy_caps_data *pcaps,
162 struct ice_sq_cd *cd)
164 struct ice_aqc_get_phy_caps *cmd;
165 u16 pcaps_size = sizeof(*pcaps);
166 struct ice_aq_desc desc;
167 enum ice_status status;
169 cmd = &desc.params.get_phy;
171 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
172 return ICE_ERR_PARAM;
174 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
177 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
179 cmd->param0 |= CPU_TO_LE16(report_mode);
180 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
182 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
183 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
184 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
191 * ice_get_media_type - Gets media type
192 * @pi: port information structure
194 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
196 struct ice_link_status *hw_link_info;
199 return ICE_MEDIA_UNKNOWN;
201 hw_link_info = &pi->phy.link_info;
202 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
203 /* If more than one media type is selected, report unknown */
204 return ICE_MEDIA_UNKNOWN;
206 if (hw_link_info->phy_type_low) {
207 switch (hw_link_info->phy_type_low) {
208 case ICE_PHY_TYPE_LOW_1000BASE_SX:
209 case ICE_PHY_TYPE_LOW_1000BASE_LX:
210 case ICE_PHY_TYPE_LOW_10GBASE_SR:
211 case ICE_PHY_TYPE_LOW_10GBASE_LR:
212 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
213 case ICE_PHY_TYPE_LOW_25GBASE_SR:
214 case ICE_PHY_TYPE_LOW_25GBASE_LR:
215 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
216 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
217 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
218 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
219 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
220 case ICE_PHY_TYPE_LOW_50GBASE_SR:
221 case ICE_PHY_TYPE_LOW_50GBASE_FR:
222 case ICE_PHY_TYPE_LOW_50GBASE_LR:
223 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
224 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
225 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
226 case ICE_PHY_TYPE_LOW_100GBASE_DR:
227 return ICE_MEDIA_FIBER;
228 case ICE_PHY_TYPE_LOW_100BASE_TX:
229 case ICE_PHY_TYPE_LOW_1000BASE_T:
230 case ICE_PHY_TYPE_LOW_2500BASE_T:
231 case ICE_PHY_TYPE_LOW_5GBASE_T:
232 case ICE_PHY_TYPE_LOW_10GBASE_T:
233 case ICE_PHY_TYPE_LOW_25GBASE_T:
234 return ICE_MEDIA_BASET;
235 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
236 case ICE_PHY_TYPE_LOW_25GBASE_CR:
237 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
238 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
239 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
240 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
241 case ICE_PHY_TYPE_LOW_50GBASE_CP:
242 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
243 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
244 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
246 case ICE_PHY_TYPE_LOW_1000BASE_KX:
247 case ICE_PHY_TYPE_LOW_2500BASE_KX:
248 case ICE_PHY_TYPE_LOW_2500BASE_X:
249 case ICE_PHY_TYPE_LOW_5GBASE_KR:
250 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
251 case ICE_PHY_TYPE_LOW_25GBASE_KR:
252 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
253 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
254 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
255 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
256 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
257 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
258 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
259 return ICE_MEDIA_BACKPLANE;
262 switch (hw_link_info->phy_type_high) {
263 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
264 return ICE_MEDIA_BACKPLANE;
267 return ICE_MEDIA_UNKNOWN;
271 * ice_aq_get_link_info
272 * @pi: port information structure
273 * @ena_lse: enable/disable LinkStatusEvent reporting
274 * @link: pointer to link status structure - optional
275 * @cd: pointer to command details structure or NULL
277 * Get Link Status (0x607). Returns the link status of the adapter.
280 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
281 struct ice_link_status *link, struct ice_sq_cd *cd)
283 struct ice_aqc_get_link_status_data link_data = { 0 };
284 struct ice_aqc_get_link_status *resp;
285 struct ice_link_status *li_old, *li;
286 enum ice_media_type *hw_media_type;
287 struct ice_fc_info *hw_fc_info;
288 bool tx_pause, rx_pause;
289 struct ice_aq_desc desc;
290 enum ice_status status;
295 return ICE_ERR_PARAM;
297 li_old = &pi->phy.link_info_old;
298 hw_media_type = &pi->phy.media_type;
299 li = &pi->phy.link_info;
300 hw_fc_info = &pi->fc;
302 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
303 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
304 resp = &desc.params.get_link_status;
305 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
306 resp->lport_num = pi->lport;
308 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
310 if (status != ICE_SUCCESS)
313 /* save off old link status information */
316 /* update current link status information */
317 li->link_speed = LE16_TO_CPU(link_data.link_speed);
318 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
319 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
320 *hw_media_type = ice_get_media_type(pi);
321 li->link_info = link_data.link_info;
322 li->an_info = link_data.an_info;
323 li->ext_info = link_data.ext_info;
324 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
325 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
326 li->topo_media_conflict = link_data.topo_media_conflict;
327 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
328 ICE_AQ_CFG_PACING_TYPE_M);
331 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
332 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
333 if (tx_pause && rx_pause)
334 hw_fc_info->current_mode = ICE_FC_FULL;
336 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
338 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
340 hw_fc_info->current_mode = ICE_FC_NONE;
342 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
344 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
345 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
346 (unsigned long long)li->phy_type_low);
347 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
348 (unsigned long long)li->phy_type_high);
349 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
350 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
351 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
352 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
353 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
354 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
355 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
357 /* save link status information */
361 /* flag cleared so calling functions don't call AQ again */
362 pi->phy.get_link_info = false;
368 * ice_init_flex_flags
369 * @hw: pointer to the hardware structure
370 * @prof_id: Rx Descriptor Builder profile ID
372 * Function to initialize Rx flex flags
374 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
378 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
379 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
380 * flexiflags1[3:0] - Not used for flag programming
381 * flexiflags2[7:0] - Tunnel and VLAN types
382 * 2 invalid fields in last index
385 /* Rx flex flags are currently programmed for the NIC profiles only.
386 * Different flag bit programming configurations can be added per
389 case ICE_RXDID_FLEX_NIC:
390 case ICE_RXDID_FLEX_NIC_2:
391 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
392 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
394 /* flex flag 1 is not used for flexi-flag programming, skipping
395 * these four FLG64 bits.
397 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
398 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
399 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
400 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
401 ICE_FLG_EVLAN_x9100, idx++);
402 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
403 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
404 ICE_FLG_TNL0, idx++);
405 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
406 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
410 ice_debug(hw, ICE_DBG_INIT,
411 "Flag programming for profile ID %d not supported\n",
418 * @hw: pointer to the hardware structure
419 * @prof_id: Rx Descriptor Builder profile ID
421 * Function to initialize flex descriptors
423 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
425 enum ice_prot_id protid_0, protid_1;
426 u16 offset_0, offset_1;
427 enum ice_flex_mdid mdid;
430 case ICE_RXDID_FLEX_NIC:
431 case ICE_RXDID_FLEX_NIC_2:
432 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
433 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
434 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
436 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
437 ICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH;
439 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
441 ice_init_flex_flags(hw, prof_id);
443 case ICE_RXDID_COMMS_GENERIC:
444 case ICE_RXDID_COMMS_AUX_VLAN:
445 case ICE_RXDID_COMMS_AUX_IPV4:
446 case ICE_RXDID_COMMS_AUX_IPV6:
447 case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
448 case ICE_RXDID_COMMS_AUX_TCP:
449 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
450 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
451 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
452 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_HIGH, 3);
454 if (prof_id == ICE_RXDID_COMMS_AUX_VLAN) {
455 /* FlexiMD.4: VLAN1 - single or EVLAN (first for QinQ).
456 * FlexiMD.5: VLAN2 - C-VLAN (second for QinQ).
458 protid_0 = ICE_PROT_EVLAN_O;
460 protid_1 = ICE_PROT_VLAN_O;
462 } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV4) {
463 /* FlexiMD.4: IPHDR1 - IPv4 header word 4, "TTL" and
465 * FlexiMD.5: IPHDR0 - IPv4 header word 0, "Ver",
466 * "Hdr Len" and "Type of Service" fields.
468 protid_0 = ICE_PROT_IPV4_OF_OR_S;
470 protid_1 = ICE_PROT_IPV4_OF_OR_S;
472 } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6) {
473 /* FlexiMD.4: IPHDR1 - IPv6 header word 3,
474 * "Next Header" and "Hop Limit" fields.
475 * FlexiMD.5: IPHDR0 - IPv6 header word 0,
476 * "Ver", "Traffic class" and high 4 bits of
477 * "Flow Label" fields.
479 protid_0 = ICE_PROT_IPV6_OF_OR_S;
481 protid_1 = ICE_PROT_IPV6_OF_OR_S;
483 } else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6_FLOW) {
484 /* FlexiMD.4: IPHDR1 - IPv6 header word 1,
485 * 16 low bits of the "Flow Label" field.
486 * FlexiMD.5: IPHDR0 - IPv6 header word 0,
487 * "Ver", "Traffic class" and high 4 bits
488 * of "Flow Label" fields.
490 protid_0 = ICE_PROT_IPV6_OF_OR_S;
492 protid_1 = ICE_PROT_IPV6_OF_OR_S;
494 } else if (prof_id == ICE_RXDID_COMMS_AUX_TCP) {
495 /* FlexiMD.4: TCPHDR - TCP header word 6,
496 * "Data Offset" and "Flags" fields.
497 * FlexiMD.5: Reserved
499 protid_0 = ICE_PROT_TCP_IL;
501 protid_1 = ICE_PROT_ID_INVAL;
504 protid_0 = ICE_PROT_ID_INVAL;
506 protid_1 = ICE_PROT_ID_INVAL;
510 ICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,
511 protid_0, offset_0, 4);
512 ICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,
513 protid_1, offset_1, 5);
515 ice_init_flex_flags(hw, prof_id);
518 ice_debug(hw, ICE_DBG_INIT,
519 "Field init for profile ID %d not supported\n",
526 * @hw: pointer to the HW struct
527 * @max_frame_size: Maximum Frame Size to be supported
528 * @cd: pointer to command details structure or NULL
530 * Set MAC configuration (0x0603)
533 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
535 u16 fc_threshold_val, tx_timer_val;
536 struct ice_aqc_set_mac_cfg *cmd;
537 struct ice_aq_desc desc;
540 cmd = &desc.params.set_mac_cfg;
542 if (max_frame_size == 0)
543 return ICE_ERR_PARAM;
545 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
547 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
549 /* We read back the transmit timer and fc threshold value of
550 * LFC. Thus, we will use index =
551 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
553 * Also, because we are opearating on transmit timer and fc
554 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
556 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
558 /* Retrieve the transmit timer */
560 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
561 tx_timer_val = reg_val &
562 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
563 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
565 /* Retrieve the fc threshold */
567 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
568 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);
569 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);
571 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
575 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
576 * @hw: pointer to the HW struct
578 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
580 struct ice_switch_info *sw;
582 hw->switch_info = (struct ice_switch_info *)
583 ice_malloc(hw, sizeof(*hw->switch_info));
584 sw = hw->switch_info;
587 return ICE_ERR_NO_MEMORY;
589 INIT_LIST_HEAD(&sw->vsi_list_map_head);
591 return ice_init_def_sw_recp(hw);
595 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
596 * @hw: pointer to the HW struct
598 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
600 struct ice_switch_info *sw = hw->switch_info;
601 struct ice_vsi_list_map_info *v_pos_map;
602 struct ice_vsi_list_map_info *v_tmp_map;
603 struct ice_sw_recipe *recps;
606 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
607 ice_vsi_list_map_info, list_entry) {
608 LIST_DEL(&v_pos_map->list_entry);
609 ice_free(hw, v_pos_map);
611 recps = hw->switch_info->recp_list;
612 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
613 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
615 recps[i].root_rid = i;
616 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
617 &recps[i].rg_list, ice_recp_grp_entry,
619 LIST_DEL(&rg_entry->l_entry);
620 ice_free(hw, rg_entry);
623 if (recps[i].adv_rule) {
624 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
625 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
627 ice_destroy_lock(&recps[i].filt_rule_lock);
628 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
629 &recps[i].filt_rules,
630 ice_adv_fltr_mgmt_list_entry,
632 LIST_DEL(&lst_itr->list_entry);
633 ice_free(hw, lst_itr->lkups);
634 ice_free(hw, lst_itr);
637 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
639 ice_destroy_lock(&recps[i].filt_rule_lock);
640 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
641 &recps[i].filt_rules,
642 ice_fltr_mgmt_list_entry,
644 LIST_DEL(&lst_itr->list_entry);
645 ice_free(hw, lst_itr);
648 if (recps[i].root_buf)
649 ice_free(hw, recps[i].root_buf);
651 ice_rm_all_sw_replay_rule_info(hw);
652 ice_free(hw, sw->recp_list);
658 * ice_get_itr_intrl_gran - determine int/intrl granularity
659 * @hw: pointer to the HW struct
661 * Determines the itr/intrl granularities based on the maximum aggregate
662 * bandwidth according to the device's configuration during power-on.
664 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
666 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
667 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
668 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
670 switch (max_agg_bw) {
671 case ICE_MAX_AGG_BW_200G:
672 case ICE_MAX_AGG_BW_100G:
673 case ICE_MAX_AGG_BW_50G:
674 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
675 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
677 case ICE_MAX_AGG_BW_25G:
678 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
679 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
685 * ice_get_nvm_version - get cached NVM version data
686 * @hw: pointer to the hardware structure
687 * @oem_ver: 8 bit NVM version
688 * @oem_build: 16 bit NVM build number
689 * @oem_patch: 8 NVM patch number
690 * @ver_hi: high 16 bits of the NVM version
691 * @ver_lo: low 16 bits of the NVM version
694 ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
695 u8 *oem_patch, u8 *ver_hi, u8 *ver_lo)
697 struct ice_nvm_info *nvm = &hw->nvm;
699 *oem_ver = (u8)((nvm->oem_ver & ICE_OEM_VER_MASK) >> ICE_OEM_VER_SHIFT);
700 *oem_patch = (u8)(nvm->oem_ver & ICE_OEM_VER_PATCH_MASK);
701 *oem_build = (u16)((nvm->oem_ver & ICE_OEM_VER_BUILD_MASK) >>
702 ICE_OEM_VER_BUILD_SHIFT);
703 *ver_hi = (nvm->ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
704 *ver_lo = (nvm->ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
708 * ice_print_rollback_msg - print FW rollback message
709 * @hw: pointer to the hardware structure
711 void ice_print_rollback_msg(struct ice_hw *hw)
713 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
714 u8 oem_ver, oem_patch, ver_hi, ver_lo;
717 ice_get_nvm_version(hw, &oem_ver, &oem_build, &oem_patch, &ver_hi,
719 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", ver_hi,
720 ver_lo, hw->nvm.eetrack, oem_ver, oem_build, oem_patch);
723 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode",
724 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
728 * ice_init_hw - main hardware initialization routine
729 * @hw: pointer to the hardware structure
731 enum ice_status ice_init_hw(struct ice_hw *hw)
733 struct ice_aqc_get_phy_caps_data *pcaps;
734 enum ice_status status;
738 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
741 /* Set MAC type based on DeviceID */
742 status = ice_set_mac_type(hw);
746 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
747 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
748 PF_FUNC_RID_FUNCTION_NUMBER_S;
751 status = ice_reset(hw, ICE_RESET_PFR);
755 ice_get_itr_intrl_gran(hw);
758 status = ice_create_all_ctrlq(hw);
760 goto err_unroll_cqinit;
762 status = ice_init_nvm(hw);
764 goto err_unroll_cqinit;
766 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
767 ice_print_rollback_msg(hw);
769 status = ice_clear_pf_cfg(hw);
771 goto err_unroll_cqinit;
773 /* Set bit to enable Flow Director filters */
774 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
775 INIT_LIST_HEAD(&hw->fdir_list_head);
777 ice_clear_pxe_mode(hw);
780 status = ice_get_caps(hw);
782 goto err_unroll_cqinit;
784 hw->port_info = (struct ice_port_info *)
785 ice_malloc(hw, sizeof(*hw->port_info));
786 if (!hw->port_info) {
787 status = ICE_ERR_NO_MEMORY;
788 goto err_unroll_cqinit;
791 /* set the back pointer to HW */
792 hw->port_info->hw = hw;
794 /* Initialize port_info struct with switch configuration data */
795 status = ice_get_initial_sw_cfg(hw);
797 goto err_unroll_alloc;
801 /* Query the allocated resources for Tx scheduler */
802 status = ice_sched_query_res_alloc(hw);
804 ice_debug(hw, ICE_DBG_SCHED,
805 "Failed to get scheduler allocated resources\n");
806 goto err_unroll_alloc;
810 /* Initialize port_info struct with scheduler data */
811 status = ice_sched_init_port(hw->port_info);
813 goto err_unroll_sched;
815 pcaps = (struct ice_aqc_get_phy_caps_data *)
816 ice_malloc(hw, sizeof(*pcaps));
818 status = ICE_ERR_NO_MEMORY;
819 goto err_unroll_sched;
822 /* Initialize port_info struct with PHY capabilities */
823 status = ice_aq_get_phy_caps(hw->port_info, false,
824 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
827 goto err_unroll_sched;
829 /* Initialize port_info struct with link information */
830 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
832 goto err_unroll_sched;
833 /* need a valid SW entry point to build a Tx tree */
834 if (!hw->sw_entry_point_layer) {
835 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
836 status = ICE_ERR_CFG;
837 goto err_unroll_sched;
839 INIT_LIST_HEAD(&hw->agg_list);
840 /* Initialize max burst size */
841 if (!hw->max_burst_size)
842 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
844 status = ice_init_fltr_mgmt_struct(hw);
846 goto err_unroll_sched;
849 /* Get MAC information */
850 /* A single port can report up to two (LAN and WoL) addresses */
851 mac_buf = ice_calloc(hw, 2,
852 sizeof(struct ice_aqc_manage_mac_read_resp));
853 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
856 status = ICE_ERR_NO_MEMORY;
857 goto err_unroll_fltr_mgmt_struct;
860 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
861 ice_free(hw, mac_buf);
864 goto err_unroll_fltr_mgmt_struct;
866 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
867 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
868 ice_init_flex_flds(hw, ICE_RXDID_COMMS_GENERIC);
869 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_VLAN);
870 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV4);
871 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6);
872 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6_FLOW);
873 ice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_TCP);
874 /* Obtain counter base index which would be used by flow director */
875 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
877 goto err_unroll_fltr_mgmt_struct;
878 status = ice_init_hw_tbls(hw);
880 goto err_unroll_fltr_mgmt_struct;
883 err_unroll_fltr_mgmt_struct:
884 ice_cleanup_fltr_mgmt_struct(hw);
886 ice_sched_cleanup_all(hw);
888 ice_free(hw, hw->port_info);
889 hw->port_info = NULL;
891 ice_destroy_all_ctrlq(hw);
896 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
897 * @hw: pointer to the hardware structure
899 * This should be called only during nominal operation, not as a result of
900 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
901 * applicable initializations if it fails for any reason.
903 void ice_deinit_hw(struct ice_hw *hw)
905 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
906 ice_cleanup_fltr_mgmt_struct(hw);
908 ice_sched_cleanup_all(hw);
909 ice_sched_clear_agg(hw);
911 ice_free_hw_tbls(hw);
914 ice_free(hw, hw->port_info);
915 hw->port_info = NULL;
918 ice_destroy_all_ctrlq(hw);
920 /* Clear VSI contexts if not already cleared */
921 ice_clear_all_vsi_ctx(hw);
925 * ice_check_reset - Check to see if a global reset is complete
926 * @hw: pointer to the hardware structure
928 enum ice_status ice_check_reset(struct ice_hw *hw)
930 u32 cnt, reg = 0, grst_delay;
932 /* Poll for Device Active state in case a recent CORER, GLOBR,
933 * or EMPR has occurred. The grst delay value is in 100ms units.
934 * Add 1sec for outstanding AQ commands that can take a long time.
936 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
937 GLGEN_RSTCTL_GRSTDEL_S) + 10;
939 for (cnt = 0; cnt < grst_delay; cnt++) {
940 ice_msec_delay(100, true);
941 reg = rd32(hw, GLGEN_RSTAT);
942 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
946 if (cnt == grst_delay) {
947 ice_debug(hw, ICE_DBG_INIT,
948 "Global reset polling failed to complete.\n");
949 return ICE_ERR_RESET_FAILED;
952 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
953 GLNVM_ULD_GLOBR_DONE_M)
955 /* Device is Active; check Global Reset processes are done */
956 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
957 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
958 if (reg == ICE_RESET_DONE_MASK) {
959 ice_debug(hw, ICE_DBG_INIT,
960 "Global reset processes done. %d\n", cnt);
963 ice_msec_delay(10, true);
966 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
967 ice_debug(hw, ICE_DBG_INIT,
968 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
970 return ICE_ERR_RESET_FAILED;
977 * ice_pf_reset - Reset the PF
978 * @hw: pointer to the hardware structure
980 * If a global reset has been triggered, this function checks
981 * for its completion and then issues the PF reset
983 static enum ice_status ice_pf_reset(struct ice_hw *hw)
987 /* If at function entry a global reset was already in progress, i.e.
988 * state is not 'device active' or any of the reset done bits are not
989 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
990 * global reset is done.
992 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
993 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
994 /* poll on global reset currently in progress until done */
995 if (ice_check_reset(hw))
996 return ICE_ERR_RESET_FAILED;
1002 reg = rd32(hw, PFGEN_CTRL);
1004 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1006 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1007 reg = rd32(hw, PFGEN_CTRL);
1008 if (!(reg & PFGEN_CTRL_PFSWR_M))
1011 ice_msec_delay(1, true);
1014 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1015 ice_debug(hw, ICE_DBG_INIT,
1016 "PF reset polling failed to complete.\n");
1017 return ICE_ERR_RESET_FAILED;
1024 * ice_reset - Perform different types of reset
1025 * @hw: pointer to the hardware structure
1026 * @req: reset request
1028 * This function triggers a reset as specified by the req parameter.
1031 * If anything other than a PF reset is triggered, PXE mode is restored.
1032 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1033 * interface has been restored in the rebuild flow.
1035 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1041 return ice_pf_reset(hw);
1042 case ICE_RESET_CORER:
1043 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1044 val = GLGEN_RTRIG_CORER_M;
1046 case ICE_RESET_GLOBR:
1047 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1048 val = GLGEN_RTRIG_GLOBR_M;
1051 return ICE_ERR_PARAM;
1054 val |= rd32(hw, GLGEN_RTRIG);
1055 wr32(hw, GLGEN_RTRIG, val);
1059 /* wait for the FW to be ready */
1060 return ice_check_reset(hw);
1064 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
1065 * @hw: pointer to hardware structure
1066 * @module_tlv: pointer to module TLV to return
1067 * @module_tlv_len: pointer to module TLV length to return
1068 * @module_type: module type requested
1070 * Finds the requested sub module TLV type from the Preserved Field
1071 * Area (PFA) and returns the TLV pointer and length. The caller can
1072 * use these to read the variable length TLV value.
1075 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
1078 enum ice_status status;
1079 u16 pfa_len, pfa_ptr;
1082 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
1083 if (status != ICE_SUCCESS) {
1084 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
1087 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
1088 if (status != ICE_SUCCESS) {
1089 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
1092 /* Starting with first TLV after PFA length, iterate through the list
1093 * of TLVs to find the requested one.
1095 next_tlv = pfa_ptr + 1;
1096 while (next_tlv < pfa_ptr + pfa_len) {
1097 u16 tlv_sub_module_type;
1101 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
1102 if (status != ICE_SUCCESS) {
1103 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
1106 /* Read TLV length */
1107 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
1108 if (status != ICE_SUCCESS) {
1109 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
1112 if (tlv_sub_module_type == module_type) {
1114 *module_tlv = next_tlv;
1115 *module_tlv_len = tlv_len;
1118 return ICE_ERR_INVAL_SIZE;
1120 /* Check next TLV, i.e. current TLV pointer + length + 2 words
1121 * (for current TLV's type and length)
1123 next_tlv = next_tlv + tlv_len + 2;
1125 /* Module does not exist */
1126 return ICE_ERR_DOES_NOT_EXIST;
1132 * ice_copy_rxq_ctx_to_hw
1133 * @hw: pointer to the hardware structure
1134 * @ice_rxq_ctx: pointer to the rxq context
1135 * @rxq_index: the index of the Rx queue
1137 * Copies rxq context from dense structure to HW register space
1139 static enum ice_status
1140 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1145 return ICE_ERR_BAD_PTR;
1147 if (rxq_index > QRX_CTRL_MAX_INDEX)
1148 return ICE_ERR_PARAM;
1150 /* Copy each dword separately to HW */
1151 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1152 wr32(hw, QRX_CONTEXT(i, rxq_index),
1153 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1155 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1156 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1162 /* LAN Rx Queue Context */
1163 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1164 /* Field Width LSB */
1165 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1166 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1167 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1168 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1169 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1170 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1171 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1172 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1173 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1174 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1175 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1176 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1177 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1178 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1179 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1180 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1181 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1182 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1183 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1184 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1190 * @hw: pointer to the hardware structure
1191 * @rlan_ctx: pointer to the rxq context
1192 * @rxq_index: the index of the Rx queue
1194 * Converts rxq context from sparse to dense structure and then writes
1195 * it to HW register space and enables the hardware to prefetch descriptors
1196 * instead of only fetching them on demand
1199 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1202 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1205 return ICE_ERR_BAD_PTR;
1207 rlan_ctx->prefena = 1;
1209 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1210 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1213 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1216 * @hw: pointer to the hardware structure
1217 * @rxq_index: the index of the Rx queue to clear
1219 * Clears rxq context in HW register space
1221 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1225 if (rxq_index > QRX_CTRL_MAX_INDEX)
1226 return ICE_ERR_PARAM;
1228 /* Clear each dword register separately */
1229 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1230 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1234 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1236 /* LAN Tx Queue Context */
1237 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1238 /* Field Width LSB */
1239 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1240 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1241 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1242 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1243 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1244 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1245 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1246 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1247 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1248 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1249 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1250 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1251 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1252 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1253 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1254 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1255 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1256 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1257 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1258 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1259 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1260 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1261 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1262 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1263 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1264 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1265 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1266 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1270 #if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)
1272 * ice_copy_tx_cmpltnq_ctx_to_hw
1273 * @hw: pointer to the hardware structure
1274 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1275 * @tx_cmpltnq_index: the index of the completion queue
1277 * Copies Tx completion queue context from dense structure to HW register space
1279 static enum ice_status
1280 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1281 u32 tx_cmpltnq_index)
1285 if (!ice_tx_cmpltnq_ctx)
1286 return ICE_ERR_BAD_PTR;
1288 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1289 return ICE_ERR_PARAM;
1291 /* Copy each dword separately to HW */
1292 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1293 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1294 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1296 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1297 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1303 /* LAN Tx Completion Queue Context */
1304 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1305 /* Field Width LSB */
1306 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1307 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1308 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1309 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1310 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1311 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1312 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1313 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1314 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1315 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1320 * ice_write_tx_cmpltnq_ctx
1321 * @hw: pointer to the hardware structure
1322 * @tx_cmpltnq_ctx: pointer to the completion queue context
1323 * @tx_cmpltnq_index: the index of the completion queue
1325 * Converts completion queue context from sparse to dense structure and then
1326 * writes it to HW register space
1329 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1330 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1331 u32 tx_cmpltnq_index)
1333 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1335 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1336 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1340 * ice_clear_tx_cmpltnq_ctx
1341 * @hw: pointer to the hardware structure
1342 * @tx_cmpltnq_index: the index of the completion queue to clear
1344 * Clears Tx completion queue context in HW register space
1347 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1351 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1352 return ICE_ERR_PARAM;
1354 /* Clear each dword register separately */
1355 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1356 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1362 * ice_copy_tx_drbell_q_ctx_to_hw
1363 * @hw: pointer to the hardware structure
1364 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1365 * @tx_drbell_q_index: the index of the doorbell queue
1367 * Copies doorbell queue context from dense structure to HW register space
1369 static enum ice_status
1370 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1371 u32 tx_drbell_q_index)
1375 if (!ice_tx_drbell_q_ctx)
1376 return ICE_ERR_BAD_PTR;
1378 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1379 return ICE_ERR_PARAM;
1381 /* Copy each dword separately to HW */
1382 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1383 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1384 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1386 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1387 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1393 /* LAN Tx Doorbell Queue Context info */
1394 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1395 /* Field Width LSB */
1396 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1397 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1398 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1399 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1400 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1401 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1402 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1403 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1404 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1405 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1406 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1411 * ice_write_tx_drbell_q_ctx
1412 * @hw: pointer to the hardware structure
1413 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1414 * @tx_drbell_q_index: the index of the doorbell queue
1416 * Converts doorbell queue context from sparse to dense structure and then
1417 * writes it to HW register space
1420 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1421 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1422 u32 tx_drbell_q_index)
1424 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1426 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1427 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1431 * ice_clear_tx_drbell_q_ctx
1432 * @hw: pointer to the hardware structure
1433 * @tx_drbell_q_index: the index of the doorbell queue to clear
1435 * Clears doorbell queue context in HW register space
1438 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1442 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1443 return ICE_ERR_PARAM;
1445 /* Clear each dword register separately */
1446 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1447 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1451 #endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */
1454 /* FW Admin Queue command wrappers */
1457 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1458 * @hw: pointer to the HW struct
1459 * @desc: descriptor describing the command
1460 * @buf: buffer to use for indirect commands (NULL for direct commands)
1461 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1462 * @cd: pointer to command details structure
1464 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1467 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1468 u16 buf_size, struct ice_sq_cd *cd)
1470 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1475 * @hw: pointer to the HW struct
1476 * @cd: pointer to command details structure or NULL
1478 * Get the firmware version (0x0001) from the admin queue commands
1480 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1482 struct ice_aqc_get_ver *resp;
1483 struct ice_aq_desc desc;
1484 enum ice_status status;
1486 resp = &desc.params.get_ver;
1488 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1490 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1493 hw->fw_branch = resp->fw_branch;
1494 hw->fw_maj_ver = resp->fw_major;
1495 hw->fw_min_ver = resp->fw_minor;
1496 hw->fw_patch = resp->fw_patch;
1497 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1498 hw->api_branch = resp->api_branch;
1499 hw->api_maj_ver = resp->api_major;
1500 hw->api_min_ver = resp->api_minor;
1501 hw->api_patch = resp->api_patch;
1508 * ice_aq_send_driver_ver
1509 * @hw: pointer to the HW struct
1510 * @dv: driver's major, minor version
1511 * @cd: pointer to command details structure or NULL
1513 * Send the driver version (0x0002) to the firmware
1516 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1517 struct ice_sq_cd *cd)
1519 struct ice_aqc_driver_ver *cmd;
1520 struct ice_aq_desc desc;
1523 cmd = &desc.params.driver_ver;
1526 return ICE_ERR_PARAM;
1528 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1530 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1531 cmd->major_ver = dv->major_ver;
1532 cmd->minor_ver = dv->minor_ver;
1533 cmd->build_ver = dv->build_ver;
1534 cmd->subbuild_ver = dv->subbuild_ver;
1537 while (len < sizeof(dv->driver_string) &&
1538 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1541 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1546 * @hw: pointer to the HW struct
1547 * @unloading: is the driver unloading itself
1549 * Tell the Firmware that we're shutting down the AdminQ and whether
1550 * or not the driver is unloading as well (0x0003).
1552 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1554 struct ice_aqc_q_shutdown *cmd;
1555 struct ice_aq_desc desc;
1557 cmd = &desc.params.q_shutdown;
1559 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1562 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1564 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1569 * @hw: pointer to the HW struct
1571 * @access: access type
1572 * @sdp_number: resource number
1573 * @timeout: the maximum time in ms that the driver may hold the resource
1574 * @cd: pointer to command details structure or NULL
1576 * Requests common resource using the admin queue commands (0x0008).
1577 * When attempting to acquire the Global Config Lock, the driver can
1578 * learn of three states:
1579 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1580 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1581 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1582 * successfully downloaded the package; the driver does
1583 * not have to download the package and can continue
1586 * Note that if the caller is in an acquire lock, perform action, release lock
1587 * phase of operation, it is possible that the FW may detect a timeout and issue
1588 * a CORER. In this case, the driver will receive a CORER interrupt and will
1589 * have to determine its cause. The calling thread that is handling this flow
1590 * will likely get an error propagated back to it indicating the Download
1591 * Package, Update Package or the Release Resource AQ commands timed out.
1593 static enum ice_status
1594 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1595 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1596 struct ice_sq_cd *cd)
1598 struct ice_aqc_req_res *cmd_resp;
1599 struct ice_aq_desc desc;
1600 enum ice_status status;
1602 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1604 cmd_resp = &desc.params.res_owner;
1606 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1608 cmd_resp->res_id = CPU_TO_LE16(res);
1609 cmd_resp->access_type = CPU_TO_LE16(access);
1610 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1611 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1614 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1616 /* The completion specifies the maximum time in ms that the driver
1617 * may hold the resource in the Timeout field.
1620 /* Global config lock response utilizes an additional status field.
1622 * If the Global config lock resource is held by some other driver, the
1623 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1624 * and the timeout field indicates the maximum time the current owner
1625 * of the resource has to free it.
1627 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1628 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1629 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1631 } else if (LE16_TO_CPU(cmd_resp->status) ==
1632 ICE_AQ_RES_GLBL_IN_PROG) {
1633 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1634 return ICE_ERR_AQ_ERROR;
1635 } else if (LE16_TO_CPU(cmd_resp->status) ==
1636 ICE_AQ_RES_GLBL_DONE) {
1637 return ICE_ERR_AQ_NO_WORK;
1640 /* invalid FW response, force a timeout immediately */
1642 return ICE_ERR_AQ_ERROR;
1645 /* If the resource is held by some other driver, the command completes
1646 * with a busy return value and the timeout field indicates the maximum
1647 * time the current owner of the resource has to free it.
1649 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1650 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1656 * ice_aq_release_res
1657 * @hw: pointer to the HW struct
1659 * @sdp_number: resource number
1660 * @cd: pointer to command details structure or NULL
1662 * release common resource using the admin queue commands (0x0009)
1664 static enum ice_status
1665 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1666 struct ice_sq_cd *cd)
1668 struct ice_aqc_req_res *cmd;
1669 struct ice_aq_desc desc;
1671 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1673 cmd = &desc.params.res_owner;
1675 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1677 cmd->res_id = CPU_TO_LE16(res);
1678 cmd->res_number = CPU_TO_LE32(sdp_number);
1680 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1685 * @hw: pointer to the HW structure
1687 * @access: access type (read or write)
1688 * @timeout: timeout in milliseconds
1690 * This function will attempt to acquire the ownership of a resource.
1693 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1694 enum ice_aq_res_access_type access, u32 timeout)
1696 #define ICE_RES_POLLING_DELAY_MS 10
1697 u32 delay = ICE_RES_POLLING_DELAY_MS;
1698 u32 time_left = timeout;
1699 enum ice_status status;
1701 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1703 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1705 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1706 * previously acquired the resource and performed any necessary updates;
1707 * in this case the caller does not obtain the resource and has no
1708 * further work to do.
1710 if (status == ICE_ERR_AQ_NO_WORK)
1711 goto ice_acquire_res_exit;
1714 ice_debug(hw, ICE_DBG_RES,
1715 "resource %d acquire type %d failed.\n", res, access);
1717 /* If necessary, poll until the current lock owner timeouts */
1718 timeout = time_left;
1719 while (status && timeout && time_left) {
1720 ice_msec_delay(delay, true);
1721 timeout = (timeout > delay) ? timeout - delay : 0;
1722 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1724 if (status == ICE_ERR_AQ_NO_WORK)
1725 /* lock free, but no work to do */
1732 if (status && status != ICE_ERR_AQ_NO_WORK)
1733 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1735 ice_acquire_res_exit:
1736 if (status == ICE_ERR_AQ_NO_WORK) {
1737 if (access == ICE_RES_WRITE)
1738 ice_debug(hw, ICE_DBG_RES,
1739 "resource indicates no work to do.\n");
1741 ice_debug(hw, ICE_DBG_RES,
1742 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1749 * @hw: pointer to the HW structure
1752 * This function will release a resource using the proper Admin Command.
1754 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1756 enum ice_status status;
1757 u32 total_delay = 0;
1759 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1761 status = ice_aq_release_res(hw, res, 0, NULL);
1763 /* there are some rare cases when trying to release the resource
1764 * results in an admin queue timeout, so handle them correctly
1766 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1767 (total_delay < hw->adminq.sq_cmd_timeout)) {
1768 ice_msec_delay(1, true);
1769 status = ice_aq_release_res(hw, res, 0, NULL);
1775 * ice_aq_alloc_free_res - command to allocate/free resources
1776 * @hw: pointer to the HW struct
1777 * @num_entries: number of resource entries in buffer
1778 * @buf: Indirect buffer to hold data parameters and response
1779 * @buf_size: size of buffer for indirect commands
1780 * @opc: pass in the command opcode
1781 * @cd: pointer to command details structure or NULL
1783 * Helper function to allocate/free resources using the admin queue commands
1786 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1787 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1788 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1790 struct ice_aqc_alloc_free_res_cmd *cmd;
1791 struct ice_aq_desc desc;
1793 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1795 cmd = &desc.params.sw_res_ctrl;
1798 return ICE_ERR_PARAM;
1800 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1801 return ICE_ERR_PARAM;
1803 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1805 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1807 cmd->num_entries = CPU_TO_LE16(num_entries);
1809 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1813 * ice_alloc_hw_res - allocate resource
1814 * @hw: pointer to the HW struct
1815 * @type: type of resource
1816 * @num: number of resources to allocate
1817 * @btm: allocate from bottom
1818 * @res: pointer to array that will receive the resources
1821 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1823 struct ice_aqc_alloc_free_res_elem *buf;
1824 enum ice_status status;
1827 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1828 buf = (struct ice_aqc_alloc_free_res_elem *)
1829 ice_malloc(hw, buf_len);
1831 return ICE_ERR_NO_MEMORY;
1833 /* Prepare buffer to allocate resource. */
1834 buf->num_elems = CPU_TO_LE16(num);
1835 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1836 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1838 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1840 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1841 ice_aqc_opc_alloc_res, NULL);
1843 goto ice_alloc_res_exit;
1845 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1846 ICE_NONDMA_TO_NONDMA);
1854 * ice_free_hw_res - free allocated HW resource
1855 * @hw: pointer to the HW struct
1856 * @type: type of resource to free
1857 * @num: number of resources
1858 * @res: pointer to array that contains the resources to free
1861 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1863 struct ice_aqc_alloc_free_res_elem *buf;
1864 enum ice_status status;
1867 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1868 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1870 return ICE_ERR_NO_MEMORY;
1872 /* Prepare buffer to free resource. */
1873 buf->num_elems = CPU_TO_LE16(num);
1874 buf->res_type = CPU_TO_LE16(type);
1875 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1876 ICE_NONDMA_TO_NONDMA);
1878 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1879 ice_aqc_opc_free_res, NULL);
1881 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1888 * ice_get_num_per_func - determine number of resources per PF
1889 * @hw: pointer to the HW structure
1890 * @max: value to be evenly split between each PF
1892 * Determine the number of valid functions by going through the bitmap returned
1893 * from parsing capabilities and use this to calculate the number of resources
1894 * per PF based on the max value passed in.
1896 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1900 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1901 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1902 ICE_CAPS_VALID_FUNCS_M);
1911 * ice_parse_caps - parse function/device capabilities
1912 * @hw: pointer to the HW struct
1913 * @buf: pointer to a buffer containing function/device capability records
1914 * @cap_count: number of capability records in the list
1915 * @opc: type of capabilities list to parse
1917 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1920 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1921 enum ice_adminq_opc opc)
1923 struct ice_aqc_list_caps_elem *cap_resp;
1924 struct ice_hw_func_caps *func_p = NULL;
1925 struct ice_hw_dev_caps *dev_p = NULL;
1926 struct ice_hw_common_caps *caps;
1933 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1935 if (opc == ice_aqc_opc_list_dev_caps) {
1936 dev_p = &hw->dev_caps;
1937 caps = &dev_p->common_cap;
1939 } else if (opc == ice_aqc_opc_list_func_caps) {
1940 func_p = &hw->func_caps;
1941 caps = &func_p->common_cap;
1942 prefix = "func cap";
1944 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1948 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1949 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1950 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1951 u32 number = LE32_TO_CPU(cap_resp->number);
1952 u16 cap = LE16_TO_CPU(cap_resp->cap);
1955 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1956 caps->valid_functions = number;
1957 ice_debug(hw, ICE_DBG_INIT,
1958 "%s: valid_functions (bitmap) = %d\n", prefix,
1959 caps->valid_functions);
1961 /* store func count for resource management purposes */
1963 dev_p->num_funcs = ice_hweight32(number);
1965 case ICE_AQC_CAPS_VSI:
1967 dev_p->num_vsi_allocd_to_host = number;
1968 ice_debug(hw, ICE_DBG_INIT,
1969 "%s: num_vsi_allocd_to_host = %d\n",
1971 dev_p->num_vsi_allocd_to_host);
1972 } else if (func_p) {
1973 func_p->guar_num_vsi =
1974 ice_get_num_per_func(hw, ICE_MAX_VSI);
1975 ice_debug(hw, ICE_DBG_INIT,
1976 "%s: guar_num_vsi (fw) = %d\n",
1978 ice_debug(hw, ICE_DBG_INIT,
1979 "%s: guar_num_vsi = %d\n",
1980 prefix, func_p->guar_num_vsi);
1983 case ICE_AQC_CAPS_DCB:
1984 caps->dcb = (number == 1);
1985 caps->active_tc_bitmap = logical_id;
1986 caps->maxtc = phys_id;
1987 ice_debug(hw, ICE_DBG_INIT,
1988 "%s: dcb = %d\n", prefix, caps->dcb);
1989 ice_debug(hw, ICE_DBG_INIT,
1990 "%s: active_tc_bitmap = %d\n", prefix,
1991 caps->active_tc_bitmap);
1992 ice_debug(hw, ICE_DBG_INIT,
1993 "%s: maxtc = %d\n", prefix, caps->maxtc);
1995 case ICE_AQC_CAPS_RSS:
1996 caps->rss_table_size = number;
1997 caps->rss_table_entry_width = logical_id;
1998 ice_debug(hw, ICE_DBG_INIT,
1999 "%s: rss_table_size = %d\n", prefix,
2000 caps->rss_table_size);
2001 ice_debug(hw, ICE_DBG_INIT,
2002 "%s: rss_table_entry_width = %d\n", prefix,
2003 caps->rss_table_entry_width);
2005 case ICE_AQC_CAPS_RXQS:
2006 caps->num_rxq = number;
2007 caps->rxq_first_id = phys_id;
2008 ice_debug(hw, ICE_DBG_INIT,
2009 "%s: num_rxq = %d\n", prefix,
2011 ice_debug(hw, ICE_DBG_INIT,
2012 "%s: rxq_first_id = %d\n", prefix,
2013 caps->rxq_first_id);
2015 case ICE_AQC_CAPS_TXQS:
2016 caps->num_txq = number;
2017 caps->txq_first_id = phys_id;
2018 ice_debug(hw, ICE_DBG_INIT,
2019 "%s: num_txq = %d\n", prefix,
2021 ice_debug(hw, ICE_DBG_INIT,
2022 "%s: txq_first_id = %d\n", prefix,
2023 caps->txq_first_id);
2025 case ICE_AQC_CAPS_MSIX:
2026 caps->num_msix_vectors = number;
2027 caps->msix_vector_first_id = phys_id;
2028 ice_debug(hw, ICE_DBG_INIT,
2029 "%s: num_msix_vectors = %d\n", prefix,
2030 caps->num_msix_vectors);
2031 ice_debug(hw, ICE_DBG_INIT,
2032 "%s: msix_vector_first_id = %d\n", prefix,
2033 caps->msix_vector_first_id);
2035 case ICE_AQC_CAPS_FD:
2040 dev_p->num_flow_director_fltr = number;
2041 ice_debug(hw, ICE_DBG_INIT,
2042 "%s: num_flow_director_fltr = %d\n",
2044 dev_p->num_flow_director_fltr);
2047 reg_val = rd32(hw, GLQF_FD_SIZE);
2048 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2049 GLQF_FD_SIZE_FD_GSIZE_S;
2050 func_p->fd_fltr_guar =
2051 ice_get_num_per_func(hw, val);
2052 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2053 GLQF_FD_SIZE_FD_BSIZE_S;
2054 func_p->fd_fltr_best_effort = val;
2055 ice_debug(hw, ICE_DBG_INIT,
2056 "%s: fd_fltr_guar = %d\n",
2057 prefix, func_p->fd_fltr_guar);
2058 ice_debug(hw, ICE_DBG_INIT,
2059 "%s: fd_fltr_best_effort = %d\n",
2060 prefix, func_p->fd_fltr_best_effort);
2064 case ICE_AQC_CAPS_MAX_MTU:
2065 caps->max_mtu = number;
2066 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
2067 prefix, caps->max_mtu);
2070 ice_debug(hw, ICE_DBG_INIT,
2071 "%s: unknown capability[%d]: 0x%x\n", prefix,
2077 /* Re-calculate capabilities that are dependent on the number of
2078 * physical ports; i.e. some features are not supported or function
2079 * differently on devices with more than 4 ports.
2081 if (hw->dev_caps.num_funcs > 4) {
2082 /* Max 4 TCs per port */
2084 ice_debug(hw, ICE_DBG_INIT,
2085 "%s: maxtc = %d (based on #ports)\n", prefix,
2091 * ice_aq_discover_caps - query function/device capabilities
2092 * @hw: pointer to the HW struct
2093 * @buf: a virtual buffer to hold the capabilities
2094 * @buf_size: Size of the virtual buffer
2095 * @cap_count: cap count needed if AQ err==ENOMEM
2096 * @opc: capabilities type to discover - pass in the command opcode
2097 * @cd: pointer to command details structure or NULL
2099 * Get the function(0x000a)/device(0x000b) capabilities description from
2102 static enum ice_status
2103 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2104 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2106 struct ice_aqc_list_caps *cmd;
2107 struct ice_aq_desc desc;
2108 enum ice_status status;
2110 cmd = &desc.params.get_cap;
2112 if (opc != ice_aqc_opc_list_func_caps &&
2113 opc != ice_aqc_opc_list_dev_caps)
2114 return ICE_ERR_PARAM;
2116 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2118 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2120 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
2121 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
2122 *cap_count = LE32_TO_CPU(cmd->count);
2127 * ice_discover_caps - get info about the HW
2128 * @hw: pointer to the hardware structure
2129 * @opc: capabilities type to discover - pass in the command opcode
2131 static enum ice_status
2132 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
2134 enum ice_status status;
2139 /* The driver doesn't know how many capabilities the device will return
2140 * so the buffer size required isn't known ahead of time. The driver
2141 * starts with cbuf_len and if this turns out to be insufficient, the
2142 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
2143 * The driver then allocates the buffer based on the count and retries
2144 * the operation. So it follows that the retry count is 2.
2146 #define ICE_GET_CAP_BUF_COUNT 40
2147 #define ICE_GET_CAP_RETRY_COUNT 2
2149 cap_count = ICE_GET_CAP_BUF_COUNT;
2150 retries = ICE_GET_CAP_RETRY_COUNT;
2155 cbuf_len = (u16)(cap_count *
2156 sizeof(struct ice_aqc_list_caps_elem));
2157 cbuf = ice_malloc(hw, cbuf_len);
2159 return ICE_ERR_NO_MEMORY;
2161 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2165 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2168 /* If ENOMEM is returned, try again with bigger buffer */
2169 } while (--retries);
2175 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2176 * @hw: pointer to the hardware structure
2178 void ice_set_safe_mode_caps(struct ice_hw *hw)
2180 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2181 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2182 u32 valid_func, rxq_first_id, txq_first_id;
2183 u32 msix_vector_first_id, max_mtu;
2186 /* cache some func_caps values that should be restored after memset */
2187 valid_func = func_caps->common_cap.valid_functions;
2188 txq_first_id = func_caps->common_cap.txq_first_id;
2189 rxq_first_id = func_caps->common_cap.rxq_first_id;
2190 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
2191 max_mtu = func_caps->common_cap.max_mtu;
2193 /* unset func capabilities */
2194 memset(func_caps, 0, sizeof(*func_caps));
2196 /* restore cached values */
2197 func_caps->common_cap.valid_functions = valid_func;
2198 func_caps->common_cap.txq_first_id = txq_first_id;
2199 func_caps->common_cap.rxq_first_id = rxq_first_id;
2200 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2201 func_caps->common_cap.max_mtu = max_mtu;
2203 /* one Tx and one Rx queue in safe mode */
2204 func_caps->common_cap.num_rxq = 1;
2205 func_caps->common_cap.num_txq = 1;
2207 /* two MSIX vectors, one for traffic and one for misc causes */
2208 func_caps->common_cap.num_msix_vectors = 2;
2209 func_caps->guar_num_vsi = 1;
2211 /* cache some dev_caps values that should be restored after memset */
2212 valid_func = dev_caps->common_cap.valid_functions;
2213 txq_first_id = dev_caps->common_cap.txq_first_id;
2214 rxq_first_id = dev_caps->common_cap.rxq_first_id;
2215 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
2216 max_mtu = dev_caps->common_cap.max_mtu;
2217 num_funcs = dev_caps->num_funcs;
2219 /* unset dev capabilities */
2220 memset(dev_caps, 0, sizeof(*dev_caps));
2222 /* restore cached values */
2223 dev_caps->common_cap.valid_functions = valid_func;
2224 dev_caps->common_cap.txq_first_id = txq_first_id;
2225 dev_caps->common_cap.rxq_first_id = rxq_first_id;
2226 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2227 dev_caps->common_cap.max_mtu = max_mtu;
2228 dev_caps->num_funcs = num_funcs;
2230 /* one Tx and one Rx queue per function in safe mode */
2231 dev_caps->common_cap.num_rxq = num_funcs;
2232 dev_caps->common_cap.num_txq = num_funcs;
2234 /* two MSIX vectors per function */
2235 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2239 * ice_get_caps - get info about the HW
2240 * @hw: pointer to the hardware structure
2242 enum ice_status ice_get_caps(struct ice_hw *hw)
2244 enum ice_status status;
2246 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2248 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2254 * ice_aq_manage_mac_write - manage MAC address write command
2255 * @hw: pointer to the HW struct
2256 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2257 * @flags: flags to control write behavior
2258 * @cd: pointer to command details structure or NULL
2260 * This function is used to write MAC address to the NVM (0x0108).
2263 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2264 struct ice_sq_cd *cd)
2266 struct ice_aqc_manage_mac_write *cmd;
2267 struct ice_aq_desc desc;
2269 cmd = &desc.params.mac_write;
2270 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2275 /* Prep values for flags, sah, sal */
2276 cmd->sah = HTONS(*((const u16 *)mac_addr));
2277 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
2279 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2283 * ice_aq_clear_pxe_mode
2284 * @hw: pointer to the HW struct
2286 * Tell the firmware that the driver is taking over from PXE (0x0110).
2288 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2290 struct ice_aq_desc desc;
2292 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2293 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2295 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2299 * ice_clear_pxe_mode - clear pxe operations mode
2300 * @hw: pointer to the HW struct
2302 * Make sure all PXE mode settings are cleared, including things
2303 * like descriptor fetch/write-back mode.
2305 void ice_clear_pxe_mode(struct ice_hw *hw)
2307 if (ice_check_sq_alive(hw, &hw->adminq))
2308 ice_aq_clear_pxe_mode(hw);
2313 * ice_get_link_speed_based_on_phy_type - returns link speed
2314 * @phy_type_low: lower part of phy_type
2315 * @phy_type_high: higher part of phy_type
2317 * This helper function will convert an entry in PHY type structure
2318 * [phy_type_low, phy_type_high] to its corresponding link speed.
2319 * Note: In the structure of [phy_type_low, phy_type_high], there should
2320 * be one bit set, as this function will convert one PHY type to its
2322 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2323 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2326 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2328 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2329 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2331 switch (phy_type_low) {
2332 case ICE_PHY_TYPE_LOW_100BASE_TX:
2333 case ICE_PHY_TYPE_LOW_100M_SGMII:
2334 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2336 case ICE_PHY_TYPE_LOW_1000BASE_T:
2337 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2338 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2339 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2340 case ICE_PHY_TYPE_LOW_1G_SGMII:
2341 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2343 case ICE_PHY_TYPE_LOW_2500BASE_T:
2344 case ICE_PHY_TYPE_LOW_2500BASE_X:
2345 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2346 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2348 case ICE_PHY_TYPE_LOW_5GBASE_T:
2349 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2350 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2352 case ICE_PHY_TYPE_LOW_10GBASE_T:
2353 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2354 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2355 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2356 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2357 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2358 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2359 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2361 case ICE_PHY_TYPE_LOW_25GBASE_T:
2362 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2363 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2364 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2365 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2366 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2367 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2368 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2369 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2370 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2371 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2372 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2374 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2375 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2376 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2377 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2378 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2379 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2380 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2382 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2383 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2384 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2385 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2386 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2387 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2388 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2389 case ICE_PHY_TYPE_LOW_50G_AUI2:
2390 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2391 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2392 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2393 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2394 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2395 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2396 case ICE_PHY_TYPE_LOW_50G_AUI1:
2397 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2399 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2400 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2401 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2402 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2403 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2404 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2405 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2406 case ICE_PHY_TYPE_LOW_100G_AUI4:
2407 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2408 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2409 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2410 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2411 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2412 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2415 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2419 switch (phy_type_high) {
2420 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2421 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2422 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2423 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2424 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2425 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2428 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2432 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2433 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2434 return ICE_AQ_LINK_SPEED_UNKNOWN;
2435 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2436 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2437 return ICE_AQ_LINK_SPEED_UNKNOWN;
2438 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2439 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2440 return speed_phy_type_low;
2442 return speed_phy_type_high;
2446 * ice_update_phy_type
2447 * @phy_type_low: pointer to the lower part of phy_type
2448 * @phy_type_high: pointer to the higher part of phy_type
2449 * @link_speeds_bitmap: targeted link speeds bitmap
2451 * Note: For the link_speeds_bitmap structure, you can check it at
2452 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2453 * link_speeds_bitmap include multiple speeds.
2455 * Each entry in this [phy_type_low, phy_type_high] structure will
2456 * present a certain link speed. This helper function will turn on bits
2457 * in [phy_type_low, phy_type_high] structure based on the value of
2458 * link_speeds_bitmap input parameter.
2461 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2462 u16 link_speeds_bitmap)
2469 /* We first check with low part of phy_type */
2470 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2471 pt_low = BIT_ULL(index);
2472 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2474 if (link_speeds_bitmap & speed)
2475 *phy_type_low |= BIT_ULL(index);
2478 /* We then check with high part of phy_type */
2479 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2480 pt_high = BIT_ULL(index);
2481 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2483 if (link_speeds_bitmap & speed)
2484 *phy_type_high |= BIT_ULL(index);
2489 * ice_aq_set_phy_cfg
2490 * @hw: pointer to the HW struct
2491 * @pi: port info structure of the interested logical port
2492 * @cfg: structure with PHY configuration data to be set
2493 * @cd: pointer to command details structure or NULL
2495 * Set the various PHY configuration parameters supported on the Port.
2496 * One or more of the Set PHY config parameters may be ignored in an MFP
2497 * mode as the PF may not have the privilege to set some of the PHY Config
2498 * parameters. This status will be indicated by the command response (0x0601).
2501 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2502 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2504 struct ice_aq_desc desc;
2505 enum ice_status status;
2508 return ICE_ERR_PARAM;
2510 /* Ensure that only valid bits of cfg->caps can be turned on. */
2511 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2512 ice_debug(hw, ICE_DBG_PHY,
2513 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2516 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2519 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2520 desc.params.set_phy.lport_num = pi->lport;
2521 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2523 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2524 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2525 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2526 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2527 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2528 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n",
2529 cfg->low_power_ctrl);
2530 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2531 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2532 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2534 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2537 pi->phy.curr_user_phy_cfg = *cfg;
2543 * ice_update_link_info - update status of the HW network link
2544 * @pi: port info structure of the interested logical port
2546 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2548 struct ice_link_status *li;
2549 enum ice_status status;
2552 return ICE_ERR_PARAM;
2554 li = &pi->phy.link_info;
2556 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2560 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2561 struct ice_aqc_get_phy_caps_data *pcaps;
2565 pcaps = (struct ice_aqc_get_phy_caps_data *)
2566 ice_malloc(hw, sizeof(*pcaps));
2568 return ICE_ERR_NO_MEMORY;
2570 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2572 if (status == ICE_SUCCESS)
2573 ice_memcpy(li->module_type, &pcaps->module_type,
2574 sizeof(li->module_type),
2575 ICE_NONDMA_TO_NONDMA);
2577 ice_free(hw, pcaps);
2584 * ice_cache_phy_user_req
2585 * @pi: port information structure
2586 * @cache_data: PHY logging data
2587 * @cache_mode: PHY logging mode
2589 * Log the user request on (FC, FEC, SPEED) for later user.
2592 ice_cache_phy_user_req(struct ice_port_info *pi,
2593 struct ice_phy_cache_mode_data cache_data,
2594 enum ice_phy_cache_mode cache_mode)
2599 switch (cache_mode) {
2601 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2603 case ICE_SPEED_MODE:
2604 pi->phy.curr_user_speed_req =
2605 cache_data.data.curr_user_speed_req;
2608 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2616 * ice_caps_to_fc_mode
2617 * @caps: PHY capabilities
2619 * Convert PHY FC capabilities to ice FC mode
2621 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2623 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2624 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2627 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2628 return ICE_FC_TX_PAUSE;
2630 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2631 return ICE_FC_RX_PAUSE;
2637 * ice_caps_to_fec_mode
2638 * @caps: PHY capabilities
2639 * @fec_options: Link FEC options
2641 * Convert PHY FEC capabilities to ice FEC mode
2643 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2645 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2646 return ICE_FEC_AUTO;
2648 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2649 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2650 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2651 ICE_AQC_PHY_FEC_25G_KR_REQ))
2652 return ICE_FEC_BASER;
2654 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2655 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2656 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2659 return ICE_FEC_NONE;
2664 * @pi: port information structure
2665 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2666 * @ena_auto_link_update: enable automatic link update
2668 * Set the requested flow control mode.
2671 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2673 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2674 struct ice_phy_cache_mode_data cache_data;
2675 struct ice_aqc_get_phy_caps_data *pcaps;
2676 enum ice_status status;
2677 u8 pause_mask = 0x0;
2681 return ICE_ERR_PARAM;
2683 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2685 /* Cache user FC request */
2686 cache_data.data.curr_user_fc_req = pi->fc.req_mode;
2687 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2689 switch (pi->fc.req_mode) {
2691 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2692 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2694 case ICE_FC_RX_PAUSE:
2695 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2697 case ICE_FC_TX_PAUSE:
2698 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2704 pcaps = (struct ice_aqc_get_phy_caps_data *)
2705 ice_malloc(hw, sizeof(*pcaps));
2707 return ICE_ERR_NO_MEMORY;
2709 /* Get the current PHY config */
2710 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2713 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2717 /* clear the old pause settings */
2718 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2719 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2721 /* set the new capabilities */
2722 cfg.caps |= pause_mask;
2724 /* If the capabilities have changed, then set the new config */
2725 if (cfg.caps != pcaps->caps) {
2726 int retry_count, retry_max = 10;
2728 /* Auto restart link so settings take effect */
2729 if (ena_auto_link_update)
2730 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2731 /* Copy over all the old settings */
2732 cfg.phy_type_high = pcaps->phy_type_high;
2733 cfg.phy_type_low = pcaps->phy_type_low;
2734 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2735 cfg.eee_cap = pcaps->eee_cap;
2736 cfg.eeer_value = pcaps->eeer_value;
2737 cfg.link_fec_opt = pcaps->link_fec_options;
2739 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2741 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2745 /* Update the link info
2746 * It sometimes takes a really long time for link to
2747 * come back from the atomic reset. Thus, we wait a
2750 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2751 status = ice_update_link_info(pi);
2753 if (status == ICE_SUCCESS)
2756 ice_msec_delay(100, true);
2760 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2764 ice_free(hw, pcaps);
2769 * ice_phy_caps_equals_cfg
2770 * @phy_caps: PHY capabilities
2771 * @phy_cfg: PHY configuration
2773 * Helper function to determine if PHY capabilities matches PHY
2777 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2778 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2780 u8 caps_mask, cfg_mask;
2782 if (!phy_caps || !phy_cfg)
2785 /* These bits are not common between capabilities and configuration.
2786 * Do not use them to determine equality.
2788 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2789 ICE_AQC_PHY_EN_MOD_QUAL);
2790 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2792 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2793 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2794 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2795 phy_caps->low_power_ctrl != phy_cfg->low_power_ctrl ||
2796 phy_caps->eee_cap != phy_cfg->eee_cap ||
2797 phy_caps->eeer_value != phy_cfg->eeer_value ||
2798 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2805 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2806 * @caps: PHY ability structure to copy date from
2807 * @cfg: PHY configuration structure to copy data to
2809 * Helper function to copy AQC PHY get ability data to PHY set configuration
2813 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2814 struct ice_aqc_set_phy_cfg_data *cfg)
2819 cfg->phy_type_low = caps->phy_type_low;
2820 cfg->phy_type_high = caps->phy_type_high;
2821 cfg->caps = caps->caps;
2822 cfg->low_power_ctrl = caps->low_power_ctrl;
2823 cfg->eee_cap = caps->eee_cap;
2824 cfg->eeer_value = caps->eeer_value;
2825 cfg->link_fec_opt = caps->link_fec_options;
2829 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2830 * @cfg: PHY configuration data to set FEC mode
2831 * @fec: FEC mode to configure
2833 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2834 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2835 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2838 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2842 /* Clear RS bits, and AND BASE-R ability
2843 * bits and OR request bits.
2845 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2846 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2847 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2848 ICE_AQC_PHY_FEC_25G_KR_REQ;
2851 /* Clear BASE-R bits, and AND RS ability
2852 * bits and OR request bits.
2854 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2855 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2856 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2859 /* Clear all FEC option bits. */
2860 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2863 /* AND auto FEC bit, and all caps bits. */
2864 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2870 * ice_get_link_status - get status of the HW network link
2871 * @pi: port information structure
2872 * @link_up: pointer to bool (true/false = linkup/linkdown)
2874 * Variable link_up is true if link is up, false if link is down.
2875 * The variable link_up is invalid if status is non zero. As a
2876 * result of this call, link status reporting becomes enabled
2878 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2880 struct ice_phy_info *phy_info;
2881 enum ice_status status = ICE_SUCCESS;
2883 if (!pi || !link_up)
2884 return ICE_ERR_PARAM;
2886 phy_info = &pi->phy;
2888 if (phy_info->get_link_info) {
2889 status = ice_update_link_info(pi);
2892 ice_debug(pi->hw, ICE_DBG_LINK,
2893 "get link status error, status = %d\n",
2897 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2903 * ice_aq_set_link_restart_an
2904 * @pi: pointer to the port information structure
2905 * @ena_link: if true: enable link, if false: disable link
2906 * @cd: pointer to command details structure or NULL
2908 * Sets up the link and restarts the Auto-Negotiation over the link.
2911 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2912 struct ice_sq_cd *cd)
2914 struct ice_aqc_restart_an *cmd;
2915 struct ice_aq_desc desc;
2917 cmd = &desc.params.restart_an;
2919 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2921 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2922 cmd->lport_num = pi->lport;
2924 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2926 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2928 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2932 * ice_aq_set_event_mask
2933 * @hw: pointer to the HW struct
2934 * @port_num: port number of the physical function
2935 * @mask: event mask to be set
2936 * @cd: pointer to command details structure or NULL
2938 * Set event mask (0x0613)
2941 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2942 struct ice_sq_cd *cd)
2944 struct ice_aqc_set_event_mask *cmd;
2945 struct ice_aq_desc desc;
2947 cmd = &desc.params.set_event_mask;
2949 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2951 cmd->lport_num = port_num;
2953 cmd->event_mask = CPU_TO_LE16(mask);
2954 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2958 * ice_aq_set_mac_loopback
2959 * @hw: pointer to the HW struct
2960 * @ena_lpbk: Enable or Disable loopback
2961 * @cd: pointer to command details structure or NULL
2963 * Enable/disable loopback on a given port
2966 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2968 struct ice_aqc_set_mac_lb *cmd;
2969 struct ice_aq_desc desc;
2971 cmd = &desc.params.set_mac_lb;
2973 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2975 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2977 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2982 * ice_aq_set_port_id_led
2983 * @pi: pointer to the port information
2984 * @is_orig_mode: is this LED set to original mode (by the net-list)
2985 * @cd: pointer to command details structure or NULL
2987 * Set LED value for the given port (0x06e9)
2990 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2991 struct ice_sq_cd *cd)
2993 struct ice_aqc_set_port_id_led *cmd;
2994 struct ice_hw *hw = pi->hw;
2995 struct ice_aq_desc desc;
2997 cmd = &desc.params.set_port_id_led;
2999 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
3003 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3005 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3007 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3012 * @hw: pointer to the HW struct
3013 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
3014 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
3015 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
3017 * @set_page: set or ignore the page
3018 * @data: pointer to data buffer to be read/written to the I2C device.
3019 * @length: 1-16 for read, 1 for write.
3020 * @write: 0 read, 1 for write.
3021 * @cd: pointer to command details structure or NULL
3023 * Read/Write SFF EEPROM (0x06EE)
3026 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
3027 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
3028 bool write, struct ice_sq_cd *cd)
3030 struct ice_aqc_sff_eeprom *cmd;
3031 struct ice_aq_desc desc;
3032 enum ice_status status;
3034 if (!data || (mem_addr & 0xff00))
3035 return ICE_ERR_PARAM;
3037 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
3038 cmd = &desc.params.read_write_sff_param;
3039 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
3040 cmd->lport_num = (u8)(lport & 0xff);
3041 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
3042 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
3043 ICE_AQC_SFF_I2CBUS_7BIT_M) |
3045 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
3046 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
3047 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
3048 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3050 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
3052 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3057 * __ice_aq_get_set_rss_lut
3058 * @hw: pointer to the hardware structure
3059 * @vsi_id: VSI FW index
3060 * @lut_type: LUT table type
3061 * @lut: pointer to the LUT buffer provided by the caller
3062 * @lut_size: size of the LUT buffer
3063 * @glob_lut_idx: global LUT index
3064 * @set: set true to set the table, false to get the table
3066 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3068 static enum ice_status
3069 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
3070 u16 lut_size, u8 glob_lut_idx, bool set)
3072 struct ice_aqc_get_set_rss_lut *cmd_resp;
3073 struct ice_aq_desc desc;
3074 enum ice_status status;
3077 cmd_resp = &desc.params.get_set_rss_lut;
3080 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3081 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3083 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3086 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3087 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3088 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3089 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3092 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3093 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3094 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3095 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3096 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3099 status = ICE_ERR_PARAM;
3100 goto ice_aq_get_set_rss_lut_exit;
3103 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3104 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3105 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3108 goto ice_aq_get_set_rss_lut_send;
3109 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3111 goto ice_aq_get_set_rss_lut_send;
3113 goto ice_aq_get_set_rss_lut_send;
3116 /* LUT size is only valid for Global and PF table types */
3118 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3119 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
3120 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3121 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3123 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3124 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3125 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3126 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3128 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3129 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3130 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3131 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3132 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3137 status = ICE_ERR_PARAM;
3138 goto ice_aq_get_set_rss_lut_exit;
3141 ice_aq_get_set_rss_lut_send:
3142 cmd_resp->flags = CPU_TO_LE16(flags);
3143 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3145 ice_aq_get_set_rss_lut_exit:
3150 * ice_aq_get_rss_lut
3151 * @hw: pointer to the hardware structure
3152 * @vsi_handle: software VSI handle
3153 * @lut_type: LUT table type
3154 * @lut: pointer to the LUT buffer provided by the caller
3155 * @lut_size: size of the LUT buffer
3157 * get the RSS lookup table, PF or VSI type
3160 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3161 u8 *lut, u16 lut_size)
3163 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3164 return ICE_ERR_PARAM;
3166 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3167 lut_type, lut, lut_size, 0, false);
3171 * ice_aq_set_rss_lut
3172 * @hw: pointer to the hardware structure
3173 * @vsi_handle: software VSI handle
3174 * @lut_type: LUT table type
3175 * @lut: pointer to the LUT buffer provided by the caller
3176 * @lut_size: size of the LUT buffer
3178 * set the RSS lookup table, PF or VSI type
3181 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3182 u8 *lut, u16 lut_size)
3184 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3185 return ICE_ERR_PARAM;
3187 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3188 lut_type, lut, lut_size, 0, true);
3192 * __ice_aq_get_set_rss_key
3193 * @hw: pointer to the HW struct
3194 * @vsi_id: VSI FW index
3195 * @key: pointer to key info struct
3196 * @set: set true to set the key, false to get the key
3198 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3201 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3202 struct ice_aqc_get_set_rss_keys *key,
3205 struct ice_aqc_get_set_rss_key *cmd_resp;
3206 u16 key_size = sizeof(*key);
3207 struct ice_aq_desc desc;
3209 cmd_resp = &desc.params.get_set_rss_key;
3212 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3213 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3215 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3218 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3219 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3220 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3221 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3223 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3227 * ice_aq_get_rss_key
3228 * @hw: pointer to the HW struct
3229 * @vsi_handle: software VSI handle
3230 * @key: pointer to key info struct
3232 * get the RSS key per VSI
3235 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3236 struct ice_aqc_get_set_rss_keys *key)
3238 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3239 return ICE_ERR_PARAM;
3241 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3246 * ice_aq_set_rss_key
3247 * @hw: pointer to the HW struct
3248 * @vsi_handle: software VSI handle
3249 * @keys: pointer to key info struct
3251 * set the RSS key per VSI
3254 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3255 struct ice_aqc_get_set_rss_keys *keys)
3257 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3258 return ICE_ERR_PARAM;
3260 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3265 * ice_aq_add_lan_txq
3266 * @hw: pointer to the hardware structure
3267 * @num_qgrps: Number of added queue groups
3268 * @qg_list: list of queue groups to be added
3269 * @buf_size: size of buffer for indirect command
3270 * @cd: pointer to command details structure or NULL
3272 * Add Tx LAN queue (0x0C30)
3275 * Prior to calling add Tx LAN queue:
3276 * Initialize the following as part of the Tx queue context:
3277 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3278 * Cache profile and Packet shaper profile.
3280 * After add Tx LAN queue AQ command is completed:
3281 * Interrupts should be associated with specific queues,
3282 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3286 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3287 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3288 struct ice_sq_cd *cd)
3290 u16 i, sum_header_size, sum_q_size = 0;
3291 struct ice_aqc_add_tx_qgrp *list;
3292 struct ice_aqc_add_txqs *cmd;
3293 struct ice_aq_desc desc;
3295 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3297 cmd = &desc.params.add_txqs;
3299 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3302 return ICE_ERR_PARAM;
3304 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3305 return ICE_ERR_PARAM;
3307 sum_header_size = num_qgrps *
3308 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3311 for (i = 0; i < num_qgrps; i++) {
3312 struct ice_aqc_add_txqs_perq *q = list->txqs;
3314 sum_q_size += list->num_txqs * sizeof(*q);
3315 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3318 if (buf_size != (sum_header_size + sum_q_size))
3319 return ICE_ERR_PARAM;
3321 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3323 cmd->num_qgrps = num_qgrps;
3325 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3329 * ice_aq_dis_lan_txq
3330 * @hw: pointer to the hardware structure
3331 * @num_qgrps: number of groups in the list
3332 * @qg_list: the list of groups to disable
3333 * @buf_size: the total size of the qg_list buffer in bytes
3334 * @rst_src: if called due to reset, specifies the reset source
3335 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3336 * @cd: pointer to command details structure or NULL
3338 * Disable LAN Tx queue (0x0C31)
3340 static enum ice_status
3341 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3342 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3343 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3344 struct ice_sq_cd *cd)
3346 struct ice_aqc_dis_txqs *cmd;
3347 struct ice_aq_desc desc;
3348 enum ice_status status;
3351 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3352 cmd = &desc.params.dis_txqs;
3353 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3355 /* qg_list can be NULL only in VM/VF reset flow */
3356 if (!qg_list && !rst_src)
3357 return ICE_ERR_PARAM;
3359 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3360 return ICE_ERR_PARAM;
3362 cmd->num_entries = num_qgrps;
3364 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3365 ICE_AQC_Q_DIS_TIMEOUT_M);
3369 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3370 cmd->vmvf_and_timeout |=
3371 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3378 /* flush pipe on time out */
3379 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3380 /* If no queue group info, we are in a reset flow. Issue the AQ */
3384 /* set RD bit to indicate that command buffer is provided by the driver
3385 * and it needs to be read by the firmware
3387 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3389 for (i = 0; i < num_qgrps; ++i) {
3390 /* Calculate the size taken up by the queue IDs in this group */
3391 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3393 /* Add the size of the group header */
3394 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3396 /* If the num of queues is even, add 2 bytes of padding */
3397 if ((qg_list[i].num_qs % 2) == 0)
3402 return ICE_ERR_PARAM;
3405 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3408 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3409 vmvf_num, hw->adminq.sq_last_status);
3411 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3412 LE16_TO_CPU(qg_list[0].q_id[0]),
3413 hw->adminq.sq_last_status);
3419 * ice_aq_move_recfg_lan_txq
3420 * @hw: pointer to the hardware structure
3421 * @num_qs: number of queues to move/reconfigure
3422 * @is_move: true if this operation involves node movement
3423 * @is_tc_change: true if this operation involves a TC change
3424 * @subseq_call: true if this operation is a subsequent call
3425 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3426 * @timeout: timeout in units of 100 usec (valid values 0-50)
3427 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3428 * @buf: struct containing src/dest TEID and per-queue info
3429 * @buf_size: size of buffer for indirect command
3430 * @txqs_moved: out param, number of queues successfully moved
3431 * @cd: pointer to command details structure or NULL
3433 * Move / Reconfigure Tx LAN queues (0x0C32)
3436 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3437 bool is_tc_change, bool subseq_call, bool flush_pipe,
3438 u8 timeout, u32 *blocked_cgds,
3439 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3440 u8 *txqs_moved, struct ice_sq_cd *cd)
3442 struct ice_aqc_move_txqs *cmd;
3443 struct ice_aq_desc desc;
3444 enum ice_status status;
3446 cmd = &desc.params.move_txqs;
3447 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3449 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3450 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3451 return ICE_ERR_PARAM;
3453 if (is_tc_change && !flush_pipe && !blocked_cgds)
3454 return ICE_ERR_PARAM;
3456 if (!is_move && !is_tc_change)
3457 return ICE_ERR_PARAM;
3459 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3462 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3465 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3468 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3471 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3473 cmd->num_qs = num_qs;
3474 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3475 ICE_AQC_Q_CMD_TIMEOUT_M);
3477 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3479 if (!status && txqs_moved)
3480 *txqs_moved = cmd->num_qs;
3482 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3483 is_tc_change && !flush_pipe)
3484 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3490 /* End of FW Admin Queue command wrappers */
3493 * ice_write_byte - write a byte to a packed context structure
3494 * @src_ctx: the context structure to read from
3495 * @dest_ctx: the context to be written to
3496 * @ce_info: a description of the struct to be filled
3499 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3501 u8 src_byte, dest_byte, mask;
3505 /* copy from the next struct field */
3506 from = src_ctx + ce_info->offset;
3508 /* prepare the bits and mask */
3509 shift_width = ce_info->lsb % 8;
3510 mask = (u8)(BIT(ce_info->width) - 1);
3515 /* shift to correct alignment */
3516 mask <<= shift_width;
3517 src_byte <<= shift_width;
3519 /* get the current bits from the target bit string */
3520 dest = dest_ctx + (ce_info->lsb / 8);
3522 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3524 dest_byte &= ~mask; /* get the bits not changing */
3525 dest_byte |= src_byte; /* add in the new bits */
3527 /* put it all back */
3528 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3532 * ice_write_word - write a word to a packed context structure
3533 * @src_ctx: the context structure to read from
3534 * @dest_ctx: the context to be written to
3535 * @ce_info: a description of the struct to be filled
3538 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3545 /* copy from the next struct field */
3546 from = src_ctx + ce_info->offset;
3548 /* prepare the bits and mask */
3549 shift_width = ce_info->lsb % 8;
3550 mask = BIT(ce_info->width) - 1;
3552 /* don't swizzle the bits until after the mask because the mask bits
3553 * will be in a different bit position on big endian machines
3555 src_word = *(u16 *)from;
3558 /* shift to correct alignment */
3559 mask <<= shift_width;
3560 src_word <<= shift_width;
3562 /* get the current bits from the target bit string */
3563 dest = dest_ctx + (ce_info->lsb / 8);
3565 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3567 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3568 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3570 /* put it all back */
3571 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3575 * ice_write_dword - write a dword to a packed context structure
3576 * @src_ctx: the context structure to read from
3577 * @dest_ctx: the context to be written to
3578 * @ce_info: a description of the struct to be filled
3581 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3583 u32 src_dword, mask;
3588 /* copy from the next struct field */
3589 from = src_ctx + ce_info->offset;
3591 /* prepare the bits and mask */
3592 shift_width = ce_info->lsb % 8;
3594 /* if the field width is exactly 32 on an x86 machine, then the shift
3595 * operation will not work because the SHL instructions count is masked
3596 * to 5 bits so the shift will do nothing
3598 if (ce_info->width < 32)
3599 mask = BIT(ce_info->width) - 1;
3603 /* don't swizzle the bits until after the mask because the mask bits
3604 * will be in a different bit position on big endian machines
3606 src_dword = *(u32 *)from;
3609 /* shift to correct alignment */
3610 mask <<= shift_width;
3611 src_dword <<= shift_width;
3613 /* get the current bits from the target bit string */
3614 dest = dest_ctx + (ce_info->lsb / 8);
3616 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3618 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3619 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3621 /* put it all back */
3622 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3626 * ice_write_qword - write a qword to a packed context structure
3627 * @src_ctx: the context structure to read from
3628 * @dest_ctx: the context to be written to
3629 * @ce_info: a description of the struct to be filled
3632 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3634 u64 src_qword, mask;
3639 /* copy from the next struct field */
3640 from = src_ctx + ce_info->offset;
3642 /* prepare the bits and mask */
3643 shift_width = ce_info->lsb % 8;
3645 /* if the field width is exactly 64 on an x86 machine, then the shift
3646 * operation will not work because the SHL instructions count is masked
3647 * to 6 bits so the shift will do nothing
3649 if (ce_info->width < 64)
3650 mask = BIT_ULL(ce_info->width) - 1;
3654 /* don't swizzle the bits until after the mask because the mask bits
3655 * will be in a different bit position on big endian machines
3657 src_qword = *(u64 *)from;
3660 /* shift to correct alignment */
3661 mask <<= shift_width;
3662 src_qword <<= shift_width;
3664 /* get the current bits from the target bit string */
3665 dest = dest_ctx + (ce_info->lsb / 8);
3667 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3669 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3670 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3672 /* put it all back */
3673 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3677 * ice_set_ctx - set context bits in packed structure
3678 * @src_ctx: pointer to a generic non-packed context structure
3679 * @dest_ctx: pointer to memory for the packed structure
3680 * @ce_info: a description of the structure to be transformed
3683 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3687 for (f = 0; ce_info[f].width; f++) {
3688 /* We have to deal with each element of the FW response
3689 * using the correct size so that we are correct regardless
3690 * of the endianness of the machine.
3692 switch (ce_info[f].size_of) {
3694 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3697 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3700 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3703 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3706 return ICE_ERR_INVAL_SIZE;
3717 * ice_read_byte - read context byte into struct
3718 * @src_ctx: the context structure to read from
3719 * @dest_ctx: the context to be written to
3720 * @ce_info: a description of the struct to be filled
3723 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3729 /* prepare the bits and mask */
3730 shift_width = ce_info->lsb % 8;
3731 mask = (u8)(BIT(ce_info->width) - 1);
3733 /* shift to correct alignment */
3734 mask <<= shift_width;
3736 /* get the current bits from the src bit string */
3737 src = src_ctx + (ce_info->lsb / 8);
3739 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3741 dest_byte &= ~(mask);
3743 dest_byte >>= shift_width;
3745 /* get the address from the struct field */
3746 target = dest_ctx + ce_info->offset;
3748 /* put it back in the struct */
3749 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3753 * ice_read_word - read context word into struct
3754 * @src_ctx: the context structure to read from
3755 * @dest_ctx: the context to be written to
3756 * @ce_info: a description of the struct to be filled
3759 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3761 u16 dest_word, mask;
3766 /* prepare the bits and mask */
3767 shift_width = ce_info->lsb % 8;
3768 mask = BIT(ce_info->width) - 1;
3770 /* shift to correct alignment */
3771 mask <<= shift_width;
3773 /* get the current bits from the src bit string */
3774 src = src_ctx + (ce_info->lsb / 8);
3776 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3778 /* the data in the memory is stored as little endian so mask it
3781 src_word &= ~(CPU_TO_LE16(mask));
3783 /* get the data back into host order before shifting */
3784 dest_word = LE16_TO_CPU(src_word);
3786 dest_word >>= shift_width;
3788 /* get the address from the struct field */
3789 target = dest_ctx + ce_info->offset;
3791 /* put it back in the struct */
3792 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3796 * ice_read_dword - read context dword into struct
3797 * @src_ctx: the context structure to read from
3798 * @dest_ctx: the context to be written to
3799 * @ce_info: a description of the struct to be filled
3802 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3804 u32 dest_dword, mask;
3809 /* prepare the bits and mask */
3810 shift_width = ce_info->lsb % 8;
3812 /* if the field width is exactly 32 on an x86 machine, then the shift
3813 * operation will not work because the SHL instructions count is masked
3814 * to 5 bits so the shift will do nothing
3816 if (ce_info->width < 32)
3817 mask = BIT(ce_info->width) - 1;
3821 /* shift to correct alignment */
3822 mask <<= shift_width;
3824 /* get the current bits from the src bit string */
3825 src = src_ctx + (ce_info->lsb / 8);
3827 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3829 /* the data in the memory is stored as little endian so mask it
3832 src_dword &= ~(CPU_TO_LE32(mask));
3834 /* get the data back into host order before shifting */
3835 dest_dword = LE32_TO_CPU(src_dword);
3837 dest_dword >>= shift_width;
3839 /* get the address from the struct field */
3840 target = dest_ctx + ce_info->offset;
3842 /* put it back in the struct */
3843 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3847 * ice_read_qword - read context qword into struct
3848 * @src_ctx: the context structure to read from
3849 * @dest_ctx: the context to be written to
3850 * @ce_info: a description of the struct to be filled
3853 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3855 u64 dest_qword, mask;
3860 /* prepare the bits and mask */
3861 shift_width = ce_info->lsb % 8;
3863 /* if the field width is exactly 64 on an x86 machine, then the shift
3864 * operation will not work because the SHL instructions count is masked
3865 * to 6 bits so the shift will do nothing
3867 if (ce_info->width < 64)
3868 mask = BIT_ULL(ce_info->width) - 1;
3872 /* shift to correct alignment */
3873 mask <<= shift_width;
3875 /* get the current bits from the src bit string */
3876 src = src_ctx + (ce_info->lsb / 8);
3878 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3880 /* the data in the memory is stored as little endian so mask it
3883 src_qword &= ~(CPU_TO_LE64(mask));
3885 /* get the data back into host order before shifting */
3886 dest_qword = LE64_TO_CPU(src_qword);
3888 dest_qword >>= shift_width;
3890 /* get the address from the struct field */
3891 target = dest_ctx + ce_info->offset;
3893 /* put it back in the struct */
3894 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3898 * ice_get_ctx - extract context bits from a packed structure
3899 * @src_ctx: pointer to a generic packed context structure
3900 * @dest_ctx: pointer to a generic non-packed context structure
3901 * @ce_info: a description of the structure to be read from
3904 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3908 for (f = 0; ce_info[f].width; f++) {
3909 switch (ce_info[f].size_of) {
3911 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3914 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3917 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3920 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3923 /* nothing to do, just keep going */
3932 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3933 * @hw: pointer to the HW struct
3934 * @vsi_handle: software VSI handle
3936 * @q_handle: software queue handle
3939 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3941 struct ice_vsi_ctx *vsi;
3942 struct ice_q_ctx *q_ctx;
3944 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3947 if (q_handle >= vsi->num_lan_q_entries[tc])
3949 if (!vsi->lan_q_ctx[tc])
3951 q_ctx = vsi->lan_q_ctx[tc];
3952 return &q_ctx[q_handle];
3957 * @pi: port information structure
3958 * @vsi_handle: software VSI handle
3960 * @q_handle: software queue handle
3961 * @num_qgrps: Number of added queue groups
3962 * @buf: list of queue groups to be added
3963 * @buf_size: size of buffer for indirect command
3964 * @cd: pointer to command details structure or NULL
3966 * This function adds one LAN queue
3969 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3970 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3971 struct ice_sq_cd *cd)
3973 struct ice_aqc_txsched_elem_data node = { 0 };
3974 struct ice_sched_node *parent;
3975 struct ice_q_ctx *q_ctx;
3976 enum ice_status status;
3979 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3982 if (num_qgrps > 1 || buf->num_txqs > 1)
3983 return ICE_ERR_MAX_LIMIT;
3987 if (!ice_is_vsi_valid(hw, vsi_handle))
3988 return ICE_ERR_PARAM;
3990 ice_acquire_lock(&pi->sched_lock);
3992 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3994 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3996 status = ICE_ERR_PARAM;
4000 /* find a parent node */
4001 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4002 ICE_SCHED_NODE_OWNER_LAN);
4004 status = ICE_ERR_PARAM;
4008 buf->parent_teid = parent->info.node_teid;
4009 node.parent_teid = parent->info.node_teid;
4010 /* Mark that the values in the "generic" section as valid. The default
4011 * value in the "generic" section is zero. This means that :
4012 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4013 * - 0 priority among siblings, indicated by Bit 1-3.
4014 * - WFQ, indicated by Bit 4.
4015 * - 0 Adjustment value is used in PSM credit update flow, indicated by
4017 * - Bit 7 is reserved.
4018 * Without setting the generic section as valid in valid_sections, the
4019 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4021 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
4023 /* add the LAN queue */
4024 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
4025 if (status != ICE_SUCCESS) {
4026 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
4027 LE16_TO_CPU(buf->txqs[0].txq_id),
4028 hw->adminq.sq_last_status);
4032 node.node_teid = buf->txqs[0].q_teid;
4033 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4034 q_ctx->q_handle = q_handle;
4035 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
4037 /* add a leaf node into scheduler tree queue layer */
4038 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
4040 status = ice_sched_replay_q_bw(pi, q_ctx);
4043 ice_release_lock(&pi->sched_lock);
4049 * @pi: port information structure
4050 * @vsi_handle: software VSI handle
4052 * @num_queues: number of queues
4053 * @q_handles: pointer to software queue handle array
4054 * @q_ids: pointer to the q_id array
4055 * @q_teids: pointer to queue node teids
4056 * @rst_src: if called due to reset, specifies the reset source
4057 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4058 * @cd: pointer to command details structure or NULL
4060 * This function removes queues and their corresponding nodes in SW DB
4063 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4064 u16 *q_handles, u16 *q_ids, u32 *q_teids,
4065 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4066 struct ice_sq_cd *cd)
4068 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
4069 struct ice_aqc_dis_txq_item qg_list;
4070 struct ice_q_ctx *q_ctx;
4073 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4077 /* if queue is disabled already yet the disable queue command
4078 * has to be sent to complete the VF reset, then call
4079 * ice_aq_dis_lan_txq without any queue information
4082 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
4087 ice_acquire_lock(&pi->sched_lock);
4089 for (i = 0; i < num_queues; i++) {
4090 struct ice_sched_node *node;
4092 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4095 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
4097 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4101 if (q_ctx->q_handle != q_handles[i]) {
4102 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4103 q_ctx->q_handle, q_handles[i]);
4106 qg_list.parent_teid = node->info.parent_teid;
4108 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
4109 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
4110 sizeof(qg_list), rst_src, vmvf_num,
4113 if (status != ICE_SUCCESS)
4115 ice_free_sched_node(pi, node);
4116 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4118 ice_release_lock(&pi->sched_lock);
4123 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4124 * @pi: port information structure
4125 * @vsi_handle: software VSI handle
4126 * @tc_bitmap: TC bitmap
4127 * @maxqs: max queues array per TC
4128 * @owner: LAN or RDMA
4130 * This function adds/updates the VSI queues per TC.
4132 static enum ice_status
4133 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4134 u16 *maxqs, u8 owner)
4136 enum ice_status status = ICE_SUCCESS;
4139 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4142 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4143 return ICE_ERR_PARAM;
4145 ice_acquire_lock(&pi->sched_lock);
4147 ice_for_each_traffic_class(i) {
4148 /* configuration is possible only if TC node is present */
4149 if (!ice_sched_get_tc_node(pi, i))
4152 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4153 ice_is_tc_ena(tc_bitmap, i));
4158 ice_release_lock(&pi->sched_lock);
4163 * ice_cfg_vsi_lan - configure VSI LAN queues
4164 * @pi: port information structure
4165 * @vsi_handle: software VSI handle
4166 * @tc_bitmap: TC bitmap
4167 * @max_lanqs: max LAN queues array per TC
4169 * This function adds/updates the VSI LAN queues per TC.
4172 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4175 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4176 ICE_SCHED_NODE_OWNER_LAN);
4182 * ice_replay_pre_init - replay pre initialization
4183 * @hw: pointer to the HW struct
4185 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4187 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
4189 struct ice_switch_info *sw = hw->switch_info;
4192 /* Delete old entries from replay filter list head if there is any */
4193 ice_rm_all_sw_replay_rule_info(hw);
4194 /* In start of replay, move entries into replay_rules list, it
4195 * will allow adding rules entries back to filt_rules list,
4196 * which is operational list.
4198 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4199 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4200 &sw->recp_list[i].filt_replay_rules);
4201 ice_sched_replay_agg_vsi_preinit(hw);
4203 return ice_sched_replay_tc_node_bw(hw->port_info);
4207 * ice_replay_vsi - replay VSI configuration
4208 * @hw: pointer to the HW struct
4209 * @vsi_handle: driver VSI handle
4211 * Restore all VSI configuration after reset. It is required to call this
4212 * function with main VSI first.
4214 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4216 enum ice_status status;
4218 if (!ice_is_vsi_valid(hw, vsi_handle))
4219 return ICE_ERR_PARAM;
4221 /* Replay pre-initialization if there is any */
4222 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
4223 status = ice_replay_pre_init(hw);
4227 /* Replay per VSI all RSS configurations */
4228 status = ice_replay_rss_cfg(hw, vsi_handle);
4231 /* Replay per VSI all filters */
4232 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
4234 status = ice_replay_vsi_agg(hw, vsi_handle);
4239 * ice_replay_post - post replay configuration cleanup
4240 * @hw: pointer to the HW struct
4242 * Post replay cleanup.
4244 void ice_replay_post(struct ice_hw *hw)
4246 /* Delete old entries from replay filter list head */
4247 ice_rm_all_sw_replay_rule_info(hw);
4248 ice_sched_replay_agg(hw);
4252 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4253 * @hw: ptr to the hardware info
4254 * @reg: offset of 64 bit HW register to read from
4255 * @prev_stat_loaded: bool to specify if previous stats are loaded
4256 * @prev_stat: ptr to previous loaded stat value
4257 * @cur_stat: ptr to current stat value
4260 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4261 u64 *prev_stat, u64 *cur_stat)
4263 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4265 /* device stats are not reset at PFR, they likely will not be zeroed
4266 * when the driver starts. Thus, save the value from the first read
4267 * without adding to the statistic value so that we report stats which
4268 * count up from zero.
4270 if (!prev_stat_loaded) {
4271 *prev_stat = new_data;
4275 /* Calculate the difference between the new and old values, and then
4276 * add it to the software stat value.
4278 if (new_data >= *prev_stat)
4279 *cur_stat += new_data - *prev_stat;
4281 /* to manage the potential roll-over */
4282 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4284 /* Update the previously stored value to prepare for next read */
4285 *prev_stat = new_data;
4289 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4290 * @hw: ptr to the hardware info
4291 * @reg: offset of HW register to read from
4292 * @prev_stat_loaded: bool to specify if previous stats are loaded
4293 * @prev_stat: ptr to previous loaded stat value
4294 * @cur_stat: ptr to current stat value
4297 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4298 u64 *prev_stat, u64 *cur_stat)
4302 new_data = rd32(hw, reg);
4304 /* device stats are not reset at PFR, they likely will not be zeroed
4305 * when the driver starts. Thus, save the value from the first read
4306 * without adding to the statistic value so that we report stats which
4307 * count up from zero.
4309 if (!prev_stat_loaded) {
4310 *prev_stat = new_data;
4314 /* Calculate the difference between the new and old values, and then
4315 * add it to the software stat value.
4317 if (new_data >= *prev_stat)
4318 *cur_stat += new_data - *prev_stat;
4320 /* to manage the potential roll-over */
4321 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4323 /* Update the previously stored value to prepare for next read */
4324 *prev_stat = new_data;
4328 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4329 * @hw: ptr to the hardware info
4330 * @vsi_handle: VSI handle
4331 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4332 * @cur_stats: ptr to current stats structure
4334 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4335 * thus cannot be read using the normal ice_stat_update32 function.
4337 * Read the GLV_REPC register associated with the given VSI, and update the
4338 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4340 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4341 * cleared each time it's read.
4343 * Note that the GLV_RDPC register also counts the causes that would trigger
4344 * GLV_REPC. However, it does not give the finer grained detail about why the
4345 * packets are being dropped. The GLV_REPC values can be used to distinguish
4346 * whether Rx packets are dropped due to errors or due to no available
4350 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4351 struct ice_eth_stats *cur_stats)
4353 u16 vsi_num, no_desc, error_cnt;
4356 if (!ice_is_vsi_valid(hw, vsi_handle))
4359 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4361 /* If we haven't loaded stats yet, just clear the current value */
4362 if (!prev_stat_loaded) {
4363 wr32(hw, GLV_REPC(vsi_num), 0);
4367 repc = rd32(hw, GLV_REPC(vsi_num));
4368 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4369 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4371 /* Clear the count by writing to the stats register */
4372 wr32(hw, GLV_REPC(vsi_num), 0);
4374 cur_stats->rx_no_desc += no_desc;
4375 cur_stats->rx_errors += error_cnt;
4380 * ice_sched_query_elem - query element information from HW
4381 * @hw: pointer to the HW struct
4382 * @node_teid: node TEID to be queried
4383 * @buf: buffer to element information
4385 * This function queries HW element information
4388 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4389 struct ice_aqc_get_elem *buf)
4391 u16 buf_size, num_elem_ret = 0;
4392 enum ice_status status;
4394 buf_size = sizeof(*buf);
4395 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4396 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4397 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4399 if (status != ICE_SUCCESS || num_elem_ret != 1)
4400 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4405 * ice_get_fw_mode - returns FW mode
4406 * @hw: pointer to the HW struct
4408 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4410 #define ICE_FW_MODE_DBG_M BIT(0)
4411 #define ICE_FW_MODE_REC_M BIT(1)
4412 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4415 /* check the current FW mode */
4416 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4418 if (fw_mode & ICE_FW_MODE_DBG_M)
4419 return ICE_FW_MODE_DBG;
4420 else if (fw_mode & ICE_FW_MODE_REC_M)
4421 return ICE_FW_MODE_REC;
4422 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4423 return ICE_FW_MODE_ROLLBACK;
4425 return ICE_FW_MODE_NORMAL;