1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 200
15 * ice_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
18 * This function sets the MAC type of the adapter based on the
19 * vendor ID and device ID stored in the HW structure.
21 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
23 enum ice_status status = ICE_SUCCESS;
25 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
27 if (hw->vendor_id == ICE_INTEL_VENDOR_ID) {
28 switch (hw->device_id) {
30 hw->mac_type = ICE_MAC_GENERIC;
34 status = ICE_ERR_DEVICE_NOT_SUPPORTED;
37 ice_debug(hw, ICE_DBG_INIT, "found mac_type: %d, status: %d\n",
38 hw->mac_type, status);
44 * ice_clear_pf_cfg - Clear PF configuration
45 * @hw: pointer to the hardware structure
47 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
48 * configuration, flow director filters, etc.).
50 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
52 struct ice_aq_desc desc;
54 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
56 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
60 * ice_aq_manage_mac_read - manage MAC address read command
61 * @hw: pointer to the HW struct
62 * @buf: a virtual buffer to hold the manage MAC read response
63 * @buf_size: Size of the virtual buffer
64 * @cd: pointer to command details structure or NULL
66 * This function is used to return per PF station MAC address (0x0107).
67 * NOTE: Upon successful completion of this command, MAC address information
68 * is returned in user specified buffer. Please interpret user specified
69 * buffer as "manage_mac_read" response.
70 * Response such as various MAC addresses are stored in HW struct (port.mac)
71 * ice_aq_discover_caps is expected to be called before this function is called.
73 static enum ice_status
74 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
77 struct ice_aqc_manage_mac_read_resp *resp;
78 struct ice_aqc_manage_mac_read *cmd;
79 struct ice_aq_desc desc;
80 enum ice_status status;
84 cmd = &desc.params.mac_read;
86 if (buf_size < sizeof(*resp))
87 return ICE_ERR_BUF_TOO_SHORT;
89 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
91 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
95 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
96 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
98 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
99 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
103 /* A single port can report up to two (LAN and WoL) addresses */
104 for (i = 0; i < cmd->num_addr; i++)
105 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
106 ice_memcpy(hw->port_info->mac.lan_addr,
107 resp[i].mac_addr, ETH_ALEN,
109 ice_memcpy(hw->port_info->mac.perm_addr,
111 ETH_ALEN, ICE_DMA_TO_NONDMA);
118 * ice_aq_get_phy_caps - returns PHY capabilities
119 * @pi: port information structure
120 * @qual_mods: report qualified modules
121 * @report_mode: report mode capabilities
122 * @pcaps: structure for PHY capabilities to be filled
123 * @cd: pointer to command details structure or NULL
125 * Returns the various PHY capabilities supported on the Port (0x0600)
128 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
129 struct ice_aqc_get_phy_caps_data *pcaps,
130 struct ice_sq_cd *cd)
132 struct ice_aqc_get_phy_caps *cmd;
133 u16 pcaps_size = sizeof(*pcaps);
134 struct ice_aq_desc desc;
135 enum ice_status status;
137 cmd = &desc.params.get_phy;
139 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
140 return ICE_ERR_PARAM;
142 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
145 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
147 cmd->param0 |= CPU_TO_LE16(report_mode);
148 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
150 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
151 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
152 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
159 * ice_aq_get_link_topo_handle - get link topology node return status
160 * @pi: port information structure
161 * @node_type: requested node type
162 * @cd: pointer to command details structure or NULL
164 * Get link topology node return status for specified node type (0x06E0)
166 * Node type cage can be used to determine if cage is present. If AQC
167 * returns error (ENOENT), then no cage present. If no cage present, then
168 * connection type is backplane or BASE-T.
170 static enum ice_status
171 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
172 struct ice_sq_cd *cd)
174 struct ice_aqc_get_link_topo *cmd;
175 struct ice_aq_desc desc;
177 cmd = &desc.params.get_link_topo;
179 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
181 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
182 ICE_AQC_LINK_TOPO_NODE_CTX_S);
185 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
187 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
191 * ice_is_media_cage_present
192 * @pi: port information structure
194 * Returns true if media cage is present, else false. If no cage, then
195 * media type is backplane or BASE-T.
197 static bool ice_is_media_cage_present(struct ice_port_info *pi)
199 /* Node type cage can be used to determine if cage is present. If AQC
200 * returns error (ENOENT), then no cage present. If no cage present then
201 * connection type is backplane or BASE-T.
203 return !ice_aq_get_link_topo_handle(pi,
204 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
209 * ice_get_media_type - Gets media type
210 * @pi: port information structure
212 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
214 struct ice_link_status *hw_link_info;
217 return ICE_MEDIA_UNKNOWN;
219 hw_link_info = &pi->phy.link_info;
220 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
221 /* If more than one media type is selected, report unknown */
222 return ICE_MEDIA_UNKNOWN;
224 if (hw_link_info->phy_type_low) {
225 switch (hw_link_info->phy_type_low) {
226 case ICE_PHY_TYPE_LOW_1000BASE_SX:
227 case ICE_PHY_TYPE_LOW_1000BASE_LX:
228 case ICE_PHY_TYPE_LOW_10GBASE_SR:
229 case ICE_PHY_TYPE_LOW_10GBASE_LR:
230 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
231 case ICE_PHY_TYPE_LOW_25GBASE_SR:
232 case ICE_PHY_TYPE_LOW_25GBASE_LR:
233 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
234 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
235 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
236 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
237 case ICE_PHY_TYPE_LOW_50GBASE_SR:
238 case ICE_PHY_TYPE_LOW_50GBASE_FR:
239 case ICE_PHY_TYPE_LOW_50GBASE_LR:
240 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
241 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
242 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
243 case ICE_PHY_TYPE_LOW_100GBASE_DR:
244 return ICE_MEDIA_FIBER;
245 case ICE_PHY_TYPE_LOW_100BASE_TX:
246 case ICE_PHY_TYPE_LOW_1000BASE_T:
247 case ICE_PHY_TYPE_LOW_2500BASE_T:
248 case ICE_PHY_TYPE_LOW_5GBASE_T:
249 case ICE_PHY_TYPE_LOW_10GBASE_T:
250 case ICE_PHY_TYPE_LOW_25GBASE_T:
251 return ICE_MEDIA_BASET;
252 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
253 case ICE_PHY_TYPE_LOW_25GBASE_CR:
254 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
255 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
256 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
257 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
258 case ICE_PHY_TYPE_LOW_50GBASE_CP:
259 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
260 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
261 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
263 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
264 case ICE_PHY_TYPE_LOW_40G_XLAUI:
265 case ICE_PHY_TYPE_LOW_50G_LAUI2:
266 case ICE_PHY_TYPE_LOW_50G_AUI2:
267 case ICE_PHY_TYPE_LOW_50G_AUI1:
268 case ICE_PHY_TYPE_LOW_100G_AUI4:
269 case ICE_PHY_TYPE_LOW_100G_CAUI4:
270 if (ice_is_media_cage_present(pi))
273 case ICE_PHY_TYPE_LOW_1000BASE_KX:
274 case ICE_PHY_TYPE_LOW_2500BASE_KX:
275 case ICE_PHY_TYPE_LOW_2500BASE_X:
276 case ICE_PHY_TYPE_LOW_5GBASE_KR:
277 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
278 case ICE_PHY_TYPE_LOW_25GBASE_KR:
279 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
280 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
281 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
282 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
283 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
284 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
285 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
286 return ICE_MEDIA_BACKPLANE;
289 switch (hw_link_info->phy_type_high) {
290 case ICE_PHY_TYPE_HIGH_100G_AUI2:
291 if (ice_is_media_cage_present(pi))
294 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
295 return ICE_MEDIA_BACKPLANE;
298 return ICE_MEDIA_UNKNOWN;
302 * ice_aq_get_link_info
303 * @pi: port information structure
304 * @ena_lse: enable/disable LinkStatusEvent reporting
305 * @link: pointer to link status structure - optional
306 * @cd: pointer to command details structure or NULL
308 * Get Link Status (0x607). Returns the link status of the adapter.
311 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
312 struct ice_link_status *link, struct ice_sq_cd *cd)
314 struct ice_aqc_get_link_status_data link_data = { 0 };
315 struct ice_aqc_get_link_status *resp;
316 struct ice_link_status *li_old, *li;
317 enum ice_media_type *hw_media_type;
318 struct ice_fc_info *hw_fc_info;
319 bool tx_pause, rx_pause;
320 struct ice_aq_desc desc;
321 enum ice_status status;
326 return ICE_ERR_PARAM;
328 li_old = &pi->phy.link_info_old;
329 hw_media_type = &pi->phy.media_type;
330 li = &pi->phy.link_info;
331 hw_fc_info = &pi->fc;
333 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
334 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
335 resp = &desc.params.get_link_status;
336 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
337 resp->lport_num = pi->lport;
339 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
341 if (status != ICE_SUCCESS)
344 /* save off old link status information */
347 /* update current link status information */
348 li->link_speed = LE16_TO_CPU(link_data.link_speed);
349 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
350 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
351 *hw_media_type = ice_get_media_type(pi);
352 li->link_info = link_data.link_info;
353 li->an_info = link_data.an_info;
354 li->ext_info = link_data.ext_info;
355 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
356 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
357 li->topo_media_conflict = link_data.topo_media_conflict;
358 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
359 ICE_AQ_CFG_PACING_TYPE_M);
362 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
363 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
364 if (tx_pause && rx_pause)
365 hw_fc_info->current_mode = ICE_FC_FULL;
367 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
369 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
371 hw_fc_info->current_mode = ICE_FC_NONE;
373 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
375 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
376 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
377 (unsigned long long)li->phy_type_low);
378 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
379 (unsigned long long)li->phy_type_high);
380 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
381 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
382 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
383 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
384 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
385 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
386 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
388 /* save link status information */
392 /* flag cleared so calling functions don't call AQ again */
393 pi->phy.get_link_info = false;
400 * @hw: pointer to the HW struct
401 * @max_frame_size: Maximum Frame Size to be supported
402 * @cd: pointer to command details structure or NULL
404 * Set MAC configuration (0x0603)
407 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
409 u16 fc_threshold_val, tx_timer_val;
410 struct ice_aqc_set_mac_cfg *cmd;
411 struct ice_aq_desc desc;
414 cmd = &desc.params.set_mac_cfg;
416 if (max_frame_size == 0)
417 return ICE_ERR_PARAM;
419 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
421 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
423 /* We read back the transmit timer and fc threshold value of
424 * LFC. Thus, we will use index =
425 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
427 * Also, because we are opearating on transmit timer and fc
428 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
430 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
432 /* Retrieve the transmit timer */
434 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
435 tx_timer_val = reg_val &
436 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
437 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
439 /* Retrieve the fc threshold */
441 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
442 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);
443 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);
445 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
449 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
450 * @hw: pointer to the HW struct
452 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
454 struct ice_switch_info *sw;
456 hw->switch_info = (struct ice_switch_info *)
457 ice_malloc(hw, sizeof(*hw->switch_info));
458 sw = hw->switch_info;
461 return ICE_ERR_NO_MEMORY;
463 INIT_LIST_HEAD(&sw->vsi_list_map_head);
465 return ice_init_def_sw_recp(hw);
469 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
470 * @hw: pointer to the HW struct
472 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
474 struct ice_switch_info *sw = hw->switch_info;
475 struct ice_vsi_list_map_info *v_pos_map;
476 struct ice_vsi_list_map_info *v_tmp_map;
477 struct ice_sw_recipe *recps;
480 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
481 ice_vsi_list_map_info, list_entry) {
482 LIST_DEL(&v_pos_map->list_entry);
483 ice_free(hw, v_pos_map);
485 recps = hw->switch_info->recp_list;
486 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
487 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
489 recps[i].root_rid = i;
490 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
491 &recps[i].rg_list, ice_recp_grp_entry,
493 LIST_DEL(&rg_entry->l_entry);
494 ice_free(hw, rg_entry);
497 if (recps[i].adv_rule) {
498 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
499 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
501 ice_destroy_lock(&recps[i].filt_rule_lock);
502 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
503 &recps[i].filt_rules,
504 ice_adv_fltr_mgmt_list_entry,
506 LIST_DEL(&lst_itr->list_entry);
507 ice_free(hw, lst_itr->lkups);
508 ice_free(hw, lst_itr);
511 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
513 ice_destroy_lock(&recps[i].filt_rule_lock);
514 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
515 &recps[i].filt_rules,
516 ice_fltr_mgmt_list_entry,
518 LIST_DEL(&lst_itr->list_entry);
519 ice_free(hw, lst_itr);
522 if (recps[i].root_buf)
523 ice_free(hw, recps[i].root_buf);
525 ice_rm_all_sw_replay_rule_info(hw);
526 ice_free(hw, sw->recp_list);
531 * ice_get_itr_intrl_gran
532 * @hw: pointer to the HW struct
534 * Determines the ITR/INTRL granularities based on the maximum aggregate
535 * bandwidth according to the device's configuration during power-on.
537 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
539 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
540 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
541 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
543 switch (max_agg_bw) {
544 case ICE_MAX_AGG_BW_200G:
545 case ICE_MAX_AGG_BW_100G:
546 case ICE_MAX_AGG_BW_50G:
547 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
548 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
550 case ICE_MAX_AGG_BW_25G:
551 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
552 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
558 * ice_get_nvm_version - get cached NVM version data
559 * @hw: pointer to the hardware structure
560 * @oem_ver: 8 bit NVM version
561 * @oem_build: 16 bit NVM build number
562 * @oem_patch: 8 NVM patch number
563 * @ver_hi: high 16 bits of the NVM version
564 * @ver_lo: low 16 bits of the NVM version
567 ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
568 u8 *oem_patch, u8 *ver_hi, u8 *ver_lo)
570 struct ice_nvm_info *nvm = &hw->nvm;
572 *oem_ver = (u8)((nvm->oem_ver & ICE_OEM_VER_MASK) >> ICE_OEM_VER_SHIFT);
573 *oem_patch = (u8)(nvm->oem_ver & ICE_OEM_VER_PATCH_MASK);
574 *oem_build = (u16)((nvm->oem_ver & ICE_OEM_VER_BUILD_MASK) >>
575 ICE_OEM_VER_BUILD_SHIFT);
576 *ver_hi = (nvm->ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
577 *ver_lo = (nvm->ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
581 * ice_print_rollback_msg - print FW rollback message
582 * @hw: pointer to the hardware structure
584 void ice_print_rollback_msg(struct ice_hw *hw)
586 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
587 u8 oem_ver, oem_patch, ver_hi, ver_lo;
590 ice_get_nvm_version(hw, &oem_ver, &oem_build, &oem_patch, &ver_hi,
592 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", ver_hi,
593 ver_lo, hw->nvm.eetrack, oem_ver, oem_build, oem_patch);
595 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode",
596 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
600 * ice_init_hw - main hardware initialization routine
601 * @hw: pointer to the hardware structure
603 enum ice_status ice_init_hw(struct ice_hw *hw)
605 struct ice_aqc_get_phy_caps_data *pcaps;
606 enum ice_status status;
610 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
612 /* Set MAC type based on DeviceID */
613 status = ice_set_mac_type(hw);
617 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
618 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
619 PF_FUNC_RID_FUNCTION_NUMBER_S;
621 status = ice_reset(hw, ICE_RESET_PFR);
625 ice_get_itr_intrl_gran(hw);
627 status = ice_create_all_ctrlq(hw);
629 goto err_unroll_cqinit;
631 status = ice_init_nvm(hw);
633 goto err_unroll_cqinit;
635 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
636 ice_print_rollback_msg(hw);
638 status = ice_clear_pf_cfg(hw);
640 goto err_unroll_cqinit;
642 /* Set bit to enable Flow Director filters */
643 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
644 INIT_LIST_HEAD(&hw->fdir_list_head);
646 ice_clear_pxe_mode(hw);
649 status = ice_get_caps(hw);
651 goto err_unroll_cqinit;
653 hw->port_info = (struct ice_port_info *)
654 ice_malloc(hw, sizeof(*hw->port_info));
655 if (!hw->port_info) {
656 status = ICE_ERR_NO_MEMORY;
657 goto err_unroll_cqinit;
660 /* set the back pointer to HW */
661 hw->port_info->hw = hw;
663 /* Initialize port_info struct with switch configuration data */
664 status = ice_get_initial_sw_cfg(hw);
666 goto err_unroll_alloc;
670 /* Query the allocated resources for Tx scheduler */
671 status = ice_sched_query_res_alloc(hw);
673 ice_debug(hw, ICE_DBG_SCHED,
674 "Failed to get scheduler allocated resources\n");
675 goto err_unroll_alloc;
678 /* Initialize port_info struct with scheduler data */
679 status = ice_sched_init_port(hw->port_info);
681 goto err_unroll_sched;
683 pcaps = (struct ice_aqc_get_phy_caps_data *)
684 ice_malloc(hw, sizeof(*pcaps));
686 status = ICE_ERR_NO_MEMORY;
687 goto err_unroll_sched;
690 /* Initialize port_info struct with PHY capabilities */
691 status = ice_aq_get_phy_caps(hw->port_info, false,
692 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
695 goto err_unroll_sched;
697 /* Initialize port_info struct with link information */
698 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
700 goto err_unroll_sched;
701 /* need a valid SW entry point to build a Tx tree */
702 if (!hw->sw_entry_point_layer) {
703 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
704 status = ICE_ERR_CFG;
705 goto err_unroll_sched;
707 INIT_LIST_HEAD(&hw->agg_list);
708 /* Initialize max burst size */
709 if (!hw->max_burst_size)
710 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
712 status = ice_init_fltr_mgmt_struct(hw);
714 goto err_unroll_sched;
716 /* Get MAC information */
717 /* A single port can report up to two (LAN and WoL) addresses */
718 mac_buf = ice_calloc(hw, 2,
719 sizeof(struct ice_aqc_manage_mac_read_resp));
720 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
723 status = ICE_ERR_NO_MEMORY;
724 goto err_unroll_fltr_mgmt_struct;
727 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
728 ice_free(hw, mac_buf);
731 goto err_unroll_fltr_mgmt_struct;
732 /* Obtain counter base index which would be used by flow director */
733 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
735 goto err_unroll_fltr_mgmt_struct;
736 status = ice_init_hw_tbls(hw);
738 goto err_unroll_fltr_mgmt_struct;
741 err_unroll_fltr_mgmt_struct:
742 ice_cleanup_fltr_mgmt_struct(hw);
744 ice_sched_cleanup_all(hw);
746 ice_free(hw, hw->port_info);
747 hw->port_info = NULL;
749 ice_destroy_all_ctrlq(hw);
754 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
755 * @hw: pointer to the hardware structure
757 * This should be called only during nominal operation, not as a result of
758 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
759 * applicable initializations if it fails for any reason.
761 void ice_deinit_hw(struct ice_hw *hw)
763 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
764 ice_cleanup_fltr_mgmt_struct(hw);
766 ice_sched_cleanup_all(hw);
767 ice_sched_clear_agg(hw);
769 ice_free_hw_tbls(hw);
772 ice_free(hw, hw->port_info);
773 hw->port_info = NULL;
776 ice_destroy_all_ctrlq(hw);
778 /* Clear VSI contexts if not already cleared */
779 ice_clear_all_vsi_ctx(hw);
783 * ice_check_reset - Check to see if a global reset is complete
784 * @hw: pointer to the hardware structure
786 enum ice_status ice_check_reset(struct ice_hw *hw)
788 u32 cnt, reg = 0, grst_delay;
790 /* Poll for Device Active state in case a recent CORER, GLOBR,
791 * or EMPR has occurred. The grst delay value is in 100ms units.
792 * Add 1sec for outstanding AQ commands that can take a long time.
794 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
795 GLGEN_RSTCTL_GRSTDEL_S) + 10;
797 for (cnt = 0; cnt < grst_delay; cnt++) {
798 ice_msec_delay(100, true);
799 reg = rd32(hw, GLGEN_RSTAT);
800 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
804 if (cnt == grst_delay) {
805 ice_debug(hw, ICE_DBG_INIT,
806 "Global reset polling failed to complete.\n");
807 return ICE_ERR_RESET_FAILED;
810 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
811 GLNVM_ULD_GLOBR_DONE_M)
813 /* Device is Active; check Global Reset processes are done */
814 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
815 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
816 if (reg == ICE_RESET_DONE_MASK) {
817 ice_debug(hw, ICE_DBG_INIT,
818 "Global reset processes done. %d\n", cnt);
821 ice_msec_delay(10, true);
824 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
825 ice_debug(hw, ICE_DBG_INIT,
826 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
828 return ICE_ERR_RESET_FAILED;
835 * ice_pf_reset - Reset the PF
836 * @hw: pointer to the hardware structure
838 * If a global reset has been triggered, this function checks
839 * for its completion and then issues the PF reset
841 static enum ice_status ice_pf_reset(struct ice_hw *hw)
845 /* If at function entry a global reset was already in progress, i.e.
846 * state is not 'device active' or any of the reset done bits are not
847 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
848 * global reset is done.
850 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
851 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
852 /* poll on global reset currently in progress until done */
853 if (ice_check_reset(hw))
854 return ICE_ERR_RESET_FAILED;
860 reg = rd32(hw, PFGEN_CTRL);
862 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
864 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
865 reg = rd32(hw, PFGEN_CTRL);
866 if (!(reg & PFGEN_CTRL_PFSWR_M))
869 ice_msec_delay(1, true);
872 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
873 ice_debug(hw, ICE_DBG_INIT,
874 "PF reset polling failed to complete.\n");
875 return ICE_ERR_RESET_FAILED;
882 * ice_reset - Perform different types of reset
883 * @hw: pointer to the hardware structure
884 * @req: reset request
886 * This function triggers a reset as specified by the req parameter.
889 * If anything other than a PF reset is triggered, PXE mode is restored.
890 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
891 * interface has been restored in the rebuild flow.
893 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
899 return ice_pf_reset(hw);
900 case ICE_RESET_CORER:
901 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
902 val = GLGEN_RTRIG_CORER_M;
904 case ICE_RESET_GLOBR:
905 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
906 val = GLGEN_RTRIG_GLOBR_M;
909 return ICE_ERR_PARAM;
912 val |= rd32(hw, GLGEN_RTRIG);
913 wr32(hw, GLGEN_RTRIG, val);
916 /* wait for the FW to be ready */
917 return ice_check_reset(hw);
921 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
922 * @hw: pointer to hardware structure
923 * @module_tlv: pointer to module TLV to return
924 * @module_tlv_len: pointer to module TLV length to return
925 * @module_type: module type requested
927 * Finds the requested sub module TLV type from the Preserved Field
928 * Area (PFA) and returns the TLV pointer and length. The caller can
929 * use these to read the variable length TLV value.
932 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
935 enum ice_status status;
936 u16 pfa_len, pfa_ptr;
939 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
940 if (status != ICE_SUCCESS) {
941 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
944 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
945 if (status != ICE_SUCCESS) {
946 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
949 /* Starting with first TLV after PFA length, iterate through the list
950 * of TLVs to find the requested one.
952 next_tlv = pfa_ptr + 1;
953 while (next_tlv < pfa_ptr + pfa_len) {
954 u16 tlv_sub_module_type;
958 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
959 if (status != ICE_SUCCESS) {
960 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
963 /* Read TLV length */
964 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
965 if (status != ICE_SUCCESS) {
966 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
969 if (tlv_sub_module_type == module_type) {
971 *module_tlv = next_tlv;
972 *module_tlv_len = tlv_len;
975 return ICE_ERR_INVAL_SIZE;
977 /* Check next TLV, i.e. current TLV pointer + length + 2 words
978 * (for current TLV's type and length)
980 next_tlv = next_tlv + tlv_len + 2;
982 /* Module does not exist */
983 return ICE_ERR_DOES_NOT_EXIST;
987 * ice_copy_rxq_ctx_to_hw
988 * @hw: pointer to the hardware structure
989 * @ice_rxq_ctx: pointer to the rxq context
990 * @rxq_index: the index of the Rx queue
992 * Copies rxq context from dense structure to HW register space
994 static enum ice_status
995 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1000 return ICE_ERR_BAD_PTR;
1002 if (rxq_index > QRX_CTRL_MAX_INDEX)
1003 return ICE_ERR_PARAM;
1005 /* Copy each dword separately to HW */
1006 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1007 wr32(hw, QRX_CONTEXT(i, rxq_index),
1008 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1010 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1011 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1017 /* LAN Rx Queue Context */
1018 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1019 /* Field Width LSB */
1020 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1021 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1022 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1023 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1024 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1025 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1026 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1027 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1028 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1029 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1030 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1031 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1032 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1033 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1034 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1035 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1036 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1037 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1038 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1039 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1045 * @hw: pointer to the hardware structure
1046 * @rlan_ctx: pointer to the rxq context
1047 * @rxq_index: the index of the Rx queue
1049 * Converts rxq context from sparse to dense structure and then writes
1050 * it to HW register space and enables the hardware to prefetch descriptors
1051 * instead of only fetching them on demand
1054 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1057 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1060 return ICE_ERR_BAD_PTR;
1062 rlan_ctx->prefena = 1;
1064 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1065 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1070 * @hw: pointer to the hardware structure
1071 * @rxq_index: the index of the Rx queue to clear
1073 * Clears rxq context in HW register space
1075 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1079 if (rxq_index > QRX_CTRL_MAX_INDEX)
1080 return ICE_ERR_PARAM;
1082 /* Clear each dword register separately */
1083 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1084 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1089 /* LAN Tx Queue Context */
1090 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1091 /* Field Width LSB */
1092 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1093 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1094 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1095 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1096 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1097 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1098 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1099 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1100 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1101 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1102 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1103 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1104 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1105 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1106 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1107 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1108 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1109 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1110 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1111 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1112 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1113 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1114 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1115 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1116 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1117 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1118 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1119 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1124 * ice_copy_tx_cmpltnq_ctx_to_hw
1125 * @hw: pointer to the hardware structure
1126 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1127 * @tx_cmpltnq_index: the index of the completion queue
1129 * Copies Tx completion queue context from dense structure to HW register space
1131 static enum ice_status
1132 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1133 u32 tx_cmpltnq_index)
1137 if (!ice_tx_cmpltnq_ctx)
1138 return ICE_ERR_BAD_PTR;
1140 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1141 return ICE_ERR_PARAM;
1143 /* Copy each dword separately to HW */
1144 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1145 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1146 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1148 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1149 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1155 /* LAN Tx Completion Queue Context */
1156 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1157 /* Field Width LSB */
1158 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1159 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1160 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1161 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1162 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1163 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1164 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1165 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1166 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1167 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1172 * ice_write_tx_cmpltnq_ctx
1173 * @hw: pointer to the hardware structure
1174 * @tx_cmpltnq_ctx: pointer to the completion queue context
1175 * @tx_cmpltnq_index: the index of the completion queue
1177 * Converts completion queue context from sparse to dense structure and then
1178 * writes it to HW register space
1181 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1182 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1183 u32 tx_cmpltnq_index)
1185 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1187 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1188 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1192 * ice_clear_tx_cmpltnq_ctx
1193 * @hw: pointer to the hardware structure
1194 * @tx_cmpltnq_index: the index of the completion queue to clear
1196 * Clears Tx completion queue context in HW register space
1199 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1203 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1204 return ICE_ERR_PARAM;
1206 /* Clear each dword register separately */
1207 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1208 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1214 * ice_copy_tx_drbell_q_ctx_to_hw
1215 * @hw: pointer to the hardware structure
1216 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1217 * @tx_drbell_q_index: the index of the doorbell queue
1219 * Copies doorbell queue context from dense structure to HW register space
1221 static enum ice_status
1222 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1223 u32 tx_drbell_q_index)
1227 if (!ice_tx_drbell_q_ctx)
1228 return ICE_ERR_BAD_PTR;
1230 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1231 return ICE_ERR_PARAM;
1233 /* Copy each dword separately to HW */
1234 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1235 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1236 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1238 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1239 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1245 /* LAN Tx Doorbell Queue Context info */
1246 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1247 /* Field Width LSB */
1248 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1249 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1250 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1251 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1252 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1253 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1254 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1255 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1256 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1257 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1258 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1263 * ice_write_tx_drbell_q_ctx
1264 * @hw: pointer to the hardware structure
1265 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1266 * @tx_drbell_q_index: the index of the doorbell queue
1268 * Converts doorbell queue context from sparse to dense structure and then
1269 * writes it to HW register space
1272 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1273 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1274 u32 tx_drbell_q_index)
1276 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1278 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1279 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1283 * ice_clear_tx_drbell_q_ctx
1284 * @hw: pointer to the hardware structure
1285 * @tx_drbell_q_index: the index of the doorbell queue to clear
1287 * Clears doorbell queue context in HW register space
1290 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1294 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1295 return ICE_ERR_PARAM;
1297 /* Clear each dword register separately */
1298 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1299 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1304 /* FW Admin Queue command wrappers */
1307 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1308 * @hw: pointer to the HW struct
1309 * @desc: descriptor describing the command
1310 * @buf: buffer to use for indirect commands (NULL for direct commands)
1311 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1312 * @cd: pointer to command details structure
1314 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1317 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1318 u16 buf_size, struct ice_sq_cd *cd)
1320 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1325 * @hw: pointer to the HW struct
1326 * @cd: pointer to command details structure or NULL
1328 * Get the firmware version (0x0001) from the admin queue commands
1330 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1332 struct ice_aqc_get_ver *resp;
1333 struct ice_aq_desc desc;
1334 enum ice_status status;
1336 resp = &desc.params.get_ver;
1338 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1340 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1343 hw->fw_branch = resp->fw_branch;
1344 hw->fw_maj_ver = resp->fw_major;
1345 hw->fw_min_ver = resp->fw_minor;
1346 hw->fw_patch = resp->fw_patch;
1347 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1348 hw->api_branch = resp->api_branch;
1349 hw->api_maj_ver = resp->api_major;
1350 hw->api_min_ver = resp->api_minor;
1351 hw->api_patch = resp->api_patch;
1358 * ice_aq_send_driver_ver
1359 * @hw: pointer to the HW struct
1360 * @dv: driver's major, minor version
1361 * @cd: pointer to command details structure or NULL
1363 * Send the driver version (0x0002) to the firmware
1366 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1367 struct ice_sq_cd *cd)
1369 struct ice_aqc_driver_ver *cmd;
1370 struct ice_aq_desc desc;
1373 cmd = &desc.params.driver_ver;
1376 return ICE_ERR_PARAM;
1378 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1380 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1381 cmd->major_ver = dv->major_ver;
1382 cmd->minor_ver = dv->minor_ver;
1383 cmd->build_ver = dv->build_ver;
1384 cmd->subbuild_ver = dv->subbuild_ver;
1387 while (len < sizeof(dv->driver_string) &&
1388 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1391 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1396 * @hw: pointer to the HW struct
1397 * @unloading: is the driver unloading itself
1399 * Tell the Firmware that we're shutting down the AdminQ and whether
1400 * or not the driver is unloading as well (0x0003).
1402 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1404 struct ice_aqc_q_shutdown *cmd;
1405 struct ice_aq_desc desc;
1407 cmd = &desc.params.q_shutdown;
1409 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1412 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1414 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1419 * @hw: pointer to the HW struct
1421 * @access: access type
1422 * @sdp_number: resource number
1423 * @timeout: the maximum time in ms that the driver may hold the resource
1424 * @cd: pointer to command details structure or NULL
1426 * Requests common resource using the admin queue commands (0x0008).
1427 * When attempting to acquire the Global Config Lock, the driver can
1428 * learn of three states:
1429 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1430 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1431 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1432 * successfully downloaded the package; the driver does
1433 * not have to download the package and can continue
1436 * Note that if the caller is in an acquire lock, perform action, release lock
1437 * phase of operation, it is possible that the FW may detect a timeout and issue
1438 * a CORER. In this case, the driver will receive a CORER interrupt and will
1439 * have to determine its cause. The calling thread that is handling this flow
1440 * will likely get an error propagated back to it indicating the Download
1441 * Package, Update Package or the Release Resource AQ commands timed out.
1443 static enum ice_status
1444 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1445 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1446 struct ice_sq_cd *cd)
1448 struct ice_aqc_req_res *cmd_resp;
1449 struct ice_aq_desc desc;
1450 enum ice_status status;
1452 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1454 cmd_resp = &desc.params.res_owner;
1456 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1458 cmd_resp->res_id = CPU_TO_LE16(res);
1459 cmd_resp->access_type = CPU_TO_LE16(access);
1460 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1461 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1464 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1466 /* The completion specifies the maximum time in ms that the driver
1467 * may hold the resource in the Timeout field.
1470 /* Global config lock response utilizes an additional status field.
1472 * If the Global config lock resource is held by some other driver, the
1473 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1474 * and the timeout field indicates the maximum time the current owner
1475 * of the resource has to free it.
1477 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1478 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1479 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1481 } else if (LE16_TO_CPU(cmd_resp->status) ==
1482 ICE_AQ_RES_GLBL_IN_PROG) {
1483 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1484 return ICE_ERR_AQ_ERROR;
1485 } else if (LE16_TO_CPU(cmd_resp->status) ==
1486 ICE_AQ_RES_GLBL_DONE) {
1487 return ICE_ERR_AQ_NO_WORK;
1490 /* invalid FW response, force a timeout immediately */
1492 return ICE_ERR_AQ_ERROR;
1495 /* If the resource is held by some other driver, the command completes
1496 * with a busy return value and the timeout field indicates the maximum
1497 * time the current owner of the resource has to free it.
1499 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1500 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1506 * ice_aq_release_res
1507 * @hw: pointer to the HW struct
1509 * @sdp_number: resource number
1510 * @cd: pointer to command details structure or NULL
1512 * release common resource using the admin queue commands (0x0009)
1514 static enum ice_status
1515 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1516 struct ice_sq_cd *cd)
1518 struct ice_aqc_req_res *cmd;
1519 struct ice_aq_desc desc;
1521 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1523 cmd = &desc.params.res_owner;
1525 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1527 cmd->res_id = CPU_TO_LE16(res);
1528 cmd->res_number = CPU_TO_LE32(sdp_number);
1530 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1535 * @hw: pointer to the HW structure
1537 * @access: access type (read or write)
1538 * @timeout: timeout in milliseconds
1540 * This function will attempt to acquire the ownership of a resource.
1543 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1544 enum ice_aq_res_access_type access, u32 timeout)
1546 #define ICE_RES_POLLING_DELAY_MS 10
1547 u32 delay = ICE_RES_POLLING_DELAY_MS;
1548 u32 time_left = timeout;
1549 enum ice_status status;
1551 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1553 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1555 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1556 * previously acquired the resource and performed any necessary updates;
1557 * in this case the caller does not obtain the resource and has no
1558 * further work to do.
1560 if (status == ICE_ERR_AQ_NO_WORK)
1561 goto ice_acquire_res_exit;
1564 ice_debug(hw, ICE_DBG_RES,
1565 "resource %d acquire type %d failed.\n", res, access);
1567 /* If necessary, poll until the current lock owner timeouts */
1568 timeout = time_left;
1569 while (status && timeout && time_left) {
1570 ice_msec_delay(delay, true);
1571 timeout = (timeout > delay) ? timeout - delay : 0;
1572 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1574 if (status == ICE_ERR_AQ_NO_WORK)
1575 /* lock free, but no work to do */
1582 if (status && status != ICE_ERR_AQ_NO_WORK)
1583 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1585 ice_acquire_res_exit:
1586 if (status == ICE_ERR_AQ_NO_WORK) {
1587 if (access == ICE_RES_WRITE)
1588 ice_debug(hw, ICE_DBG_RES,
1589 "resource indicates no work to do.\n");
1591 ice_debug(hw, ICE_DBG_RES,
1592 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1599 * @hw: pointer to the HW structure
1602 * This function will release a resource using the proper Admin Command.
1604 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1606 enum ice_status status;
1607 u32 total_delay = 0;
1609 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1611 status = ice_aq_release_res(hw, res, 0, NULL);
1613 /* there are some rare cases when trying to release the resource
1614 * results in an admin queue timeout, so handle them correctly
1616 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1617 (total_delay < hw->adminq.sq_cmd_timeout)) {
1618 ice_msec_delay(1, true);
1619 status = ice_aq_release_res(hw, res, 0, NULL);
1625 * ice_aq_alloc_free_res - command to allocate/free resources
1626 * @hw: pointer to the HW struct
1627 * @num_entries: number of resource entries in buffer
1628 * @buf: Indirect buffer to hold data parameters and response
1629 * @buf_size: size of buffer for indirect commands
1630 * @opc: pass in the command opcode
1631 * @cd: pointer to command details structure or NULL
1633 * Helper function to allocate/free resources using the admin queue commands
1636 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1637 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1638 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1640 struct ice_aqc_alloc_free_res_cmd *cmd;
1641 struct ice_aq_desc desc;
1643 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1645 cmd = &desc.params.sw_res_ctrl;
1648 return ICE_ERR_PARAM;
1650 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1651 return ICE_ERR_PARAM;
1653 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1655 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1657 cmd->num_entries = CPU_TO_LE16(num_entries);
1659 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1663 * ice_alloc_hw_res - allocate resource
1664 * @hw: pointer to the HW struct
1665 * @type: type of resource
1666 * @num: number of resources to allocate
1667 * @btm: allocate from bottom
1668 * @res: pointer to array that will receive the resources
1671 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1673 struct ice_aqc_alloc_free_res_elem *buf;
1674 enum ice_status status;
1677 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1678 buf = (struct ice_aqc_alloc_free_res_elem *)
1679 ice_malloc(hw, buf_len);
1681 return ICE_ERR_NO_MEMORY;
1683 /* Prepare buffer to allocate resource. */
1684 buf->num_elems = CPU_TO_LE16(num);
1685 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1686 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1688 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1690 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1691 ice_aqc_opc_alloc_res, NULL);
1693 goto ice_alloc_res_exit;
1695 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1696 ICE_NONDMA_TO_NONDMA);
1704 * ice_free_hw_res - free allocated HW resource
1705 * @hw: pointer to the HW struct
1706 * @type: type of resource to free
1707 * @num: number of resources
1708 * @res: pointer to array that contains the resources to free
1711 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1713 struct ice_aqc_alloc_free_res_elem *buf;
1714 enum ice_status status;
1717 buf_len = sizeof(*buf) + sizeof(buf->elem) * (num - 1);
1718 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1720 return ICE_ERR_NO_MEMORY;
1722 /* Prepare buffer to free resource. */
1723 buf->num_elems = CPU_TO_LE16(num);
1724 buf->res_type = CPU_TO_LE16(type);
1725 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1726 ICE_NONDMA_TO_NONDMA);
1728 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1729 ice_aqc_opc_free_res, NULL);
1731 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1738 * ice_get_num_per_func - determine number of resources per PF
1739 * @hw: pointer to the HW structure
1740 * @max: value to be evenly split between each PF
1742 * Determine the number of valid functions by going through the bitmap returned
1743 * from parsing capabilities and use this to calculate the number of resources
1744 * per PF based on the max value passed in.
1746 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1750 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1751 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1752 ICE_CAPS_VALID_FUNCS_M);
1761 * ice_parse_caps - parse function/device capabilities
1762 * @hw: pointer to the HW struct
1763 * @buf: pointer to a buffer containing function/device capability records
1764 * @cap_count: number of capability records in the list
1765 * @opc: type of capabilities list to parse
1767 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1770 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1771 enum ice_adminq_opc opc)
1773 struct ice_aqc_list_caps_elem *cap_resp;
1774 struct ice_hw_func_caps *func_p = NULL;
1775 struct ice_hw_dev_caps *dev_p = NULL;
1776 struct ice_hw_common_caps *caps;
1783 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1785 if (opc == ice_aqc_opc_list_dev_caps) {
1786 dev_p = &hw->dev_caps;
1787 caps = &dev_p->common_cap;
1789 } else if (opc == ice_aqc_opc_list_func_caps) {
1790 func_p = &hw->func_caps;
1791 caps = &func_p->common_cap;
1792 prefix = "func cap";
1794 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1798 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1799 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1800 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1801 u32 number = LE32_TO_CPU(cap_resp->number);
1802 u16 cap = LE16_TO_CPU(cap_resp->cap);
1805 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1806 caps->valid_functions = number;
1807 ice_debug(hw, ICE_DBG_INIT,
1808 "%s: valid_functions (bitmap) = %d\n", prefix,
1809 caps->valid_functions);
1811 /* store func count for resource management purposes */
1813 dev_p->num_funcs = ice_hweight32(number);
1815 case ICE_AQC_CAPS_VSI:
1817 dev_p->num_vsi_allocd_to_host = number;
1818 ice_debug(hw, ICE_DBG_INIT,
1819 "%s: num_vsi_allocd_to_host = %d\n",
1821 dev_p->num_vsi_allocd_to_host);
1822 } else if (func_p) {
1823 func_p->guar_num_vsi =
1824 ice_get_num_per_func(hw, ICE_MAX_VSI);
1825 ice_debug(hw, ICE_DBG_INIT,
1826 "%s: guar_num_vsi (fw) = %d\n",
1828 ice_debug(hw, ICE_DBG_INIT,
1829 "%s: guar_num_vsi = %d\n",
1830 prefix, func_p->guar_num_vsi);
1833 case ICE_AQC_CAPS_DCB:
1834 caps->dcb = (number == 1);
1835 caps->active_tc_bitmap = logical_id;
1836 caps->maxtc = phys_id;
1837 ice_debug(hw, ICE_DBG_INIT,
1838 "%s: dcb = %d\n", prefix, caps->dcb);
1839 ice_debug(hw, ICE_DBG_INIT,
1840 "%s: active_tc_bitmap = %d\n", prefix,
1841 caps->active_tc_bitmap);
1842 ice_debug(hw, ICE_DBG_INIT,
1843 "%s: maxtc = %d\n", prefix, caps->maxtc);
1845 case ICE_AQC_CAPS_RSS:
1846 caps->rss_table_size = number;
1847 caps->rss_table_entry_width = logical_id;
1848 ice_debug(hw, ICE_DBG_INIT,
1849 "%s: rss_table_size = %d\n", prefix,
1850 caps->rss_table_size);
1851 ice_debug(hw, ICE_DBG_INIT,
1852 "%s: rss_table_entry_width = %d\n", prefix,
1853 caps->rss_table_entry_width);
1855 case ICE_AQC_CAPS_RXQS:
1856 caps->num_rxq = number;
1857 caps->rxq_first_id = phys_id;
1858 ice_debug(hw, ICE_DBG_INIT,
1859 "%s: num_rxq = %d\n", prefix,
1861 ice_debug(hw, ICE_DBG_INIT,
1862 "%s: rxq_first_id = %d\n", prefix,
1863 caps->rxq_first_id);
1865 case ICE_AQC_CAPS_TXQS:
1866 caps->num_txq = number;
1867 caps->txq_first_id = phys_id;
1868 ice_debug(hw, ICE_DBG_INIT,
1869 "%s: num_txq = %d\n", prefix,
1871 ice_debug(hw, ICE_DBG_INIT,
1872 "%s: txq_first_id = %d\n", prefix,
1873 caps->txq_first_id);
1875 case ICE_AQC_CAPS_MSIX:
1876 caps->num_msix_vectors = number;
1877 caps->msix_vector_first_id = phys_id;
1878 ice_debug(hw, ICE_DBG_INIT,
1879 "%s: num_msix_vectors = %d\n", prefix,
1880 caps->num_msix_vectors);
1881 ice_debug(hw, ICE_DBG_INIT,
1882 "%s: msix_vector_first_id = %d\n", prefix,
1883 caps->msix_vector_first_id);
1885 case ICE_AQC_CAPS_FD:
1890 dev_p->num_flow_director_fltr = number;
1891 ice_debug(hw, ICE_DBG_INIT,
1892 "%s: num_flow_director_fltr = %d\n",
1894 dev_p->num_flow_director_fltr);
1897 reg_val = rd32(hw, GLQF_FD_SIZE);
1898 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
1899 GLQF_FD_SIZE_FD_GSIZE_S;
1900 func_p->fd_fltr_guar =
1901 ice_get_num_per_func(hw, val);
1902 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
1903 GLQF_FD_SIZE_FD_BSIZE_S;
1904 func_p->fd_fltr_best_effort = val;
1905 ice_debug(hw, ICE_DBG_INIT,
1906 "%s: fd_fltr_guar = %d\n",
1907 prefix, func_p->fd_fltr_guar);
1908 ice_debug(hw, ICE_DBG_INIT,
1909 "%s: fd_fltr_best_effort = %d\n",
1910 prefix, func_p->fd_fltr_best_effort);
1914 case ICE_AQC_CAPS_MAX_MTU:
1915 caps->max_mtu = number;
1916 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1917 prefix, caps->max_mtu);
1920 ice_debug(hw, ICE_DBG_INIT,
1921 "%s: unknown capability[%d]: 0x%x\n", prefix,
1927 /* Re-calculate capabilities that are dependent on the number of
1928 * physical ports; i.e. some features are not supported or function
1929 * differently on devices with more than 4 ports.
1931 if (hw->dev_caps.num_funcs > 4) {
1932 /* Max 4 TCs per port */
1934 ice_debug(hw, ICE_DBG_INIT,
1935 "%s: maxtc = %d (based on #ports)\n", prefix,
1941 * ice_aq_discover_caps - query function/device capabilities
1942 * @hw: pointer to the HW struct
1943 * @buf: a virtual buffer to hold the capabilities
1944 * @buf_size: Size of the virtual buffer
1945 * @cap_count: cap count needed if AQ err==ENOMEM
1946 * @opc: capabilities type to discover - pass in the command opcode
1947 * @cd: pointer to command details structure or NULL
1949 * Get the function(0x000a)/device(0x000b) capabilities description from
1952 static enum ice_status
1953 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
1954 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1956 struct ice_aqc_list_caps *cmd;
1957 struct ice_aq_desc desc;
1958 enum ice_status status;
1960 cmd = &desc.params.get_cap;
1962 if (opc != ice_aqc_opc_list_func_caps &&
1963 opc != ice_aqc_opc_list_dev_caps)
1964 return ICE_ERR_PARAM;
1966 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1968 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1970 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
1971 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
1972 *cap_count = LE32_TO_CPU(cmd->count);
1977 * ice_discover_caps - get info about the HW
1978 * @hw: pointer to the hardware structure
1979 * @opc: capabilities type to discover - pass in the command opcode
1981 static enum ice_status
1982 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
1984 enum ice_status status;
1989 /* The driver doesn't know how many capabilities the device will return
1990 * so the buffer size required isn't known ahead of time. The driver
1991 * starts with cbuf_len and if this turns out to be insufficient, the
1992 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
1993 * The driver then allocates the buffer based on the count and retries
1994 * the operation. So it follows that the retry count is 2.
1996 #define ICE_GET_CAP_BUF_COUNT 40
1997 #define ICE_GET_CAP_RETRY_COUNT 2
1999 cap_count = ICE_GET_CAP_BUF_COUNT;
2000 retries = ICE_GET_CAP_RETRY_COUNT;
2005 cbuf_len = (u16)(cap_count *
2006 sizeof(struct ice_aqc_list_caps_elem));
2007 cbuf = ice_malloc(hw, cbuf_len);
2009 return ICE_ERR_NO_MEMORY;
2011 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
2015 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
2018 /* If ENOMEM is returned, try again with bigger buffer */
2019 } while (--retries);
2025 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2026 * @hw: pointer to the hardware structure
2028 void ice_set_safe_mode_caps(struct ice_hw *hw)
2030 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2031 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2032 u32 valid_func, rxq_first_id, txq_first_id;
2033 u32 msix_vector_first_id, max_mtu;
2036 /* cache some func_caps values that should be restored after memset */
2037 valid_func = func_caps->common_cap.valid_functions;
2038 txq_first_id = func_caps->common_cap.txq_first_id;
2039 rxq_first_id = func_caps->common_cap.rxq_first_id;
2040 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
2041 max_mtu = func_caps->common_cap.max_mtu;
2043 /* unset func capabilities */
2044 memset(func_caps, 0, sizeof(*func_caps));
2046 /* restore cached values */
2047 func_caps->common_cap.valid_functions = valid_func;
2048 func_caps->common_cap.txq_first_id = txq_first_id;
2049 func_caps->common_cap.rxq_first_id = rxq_first_id;
2050 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2051 func_caps->common_cap.max_mtu = max_mtu;
2053 /* one Tx and one Rx queue in safe mode */
2054 func_caps->common_cap.num_rxq = 1;
2055 func_caps->common_cap.num_txq = 1;
2057 /* two MSIX vectors, one for traffic and one for misc causes */
2058 func_caps->common_cap.num_msix_vectors = 2;
2059 func_caps->guar_num_vsi = 1;
2061 /* cache some dev_caps values that should be restored after memset */
2062 valid_func = dev_caps->common_cap.valid_functions;
2063 txq_first_id = dev_caps->common_cap.txq_first_id;
2064 rxq_first_id = dev_caps->common_cap.rxq_first_id;
2065 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
2066 max_mtu = dev_caps->common_cap.max_mtu;
2067 num_funcs = dev_caps->num_funcs;
2069 /* unset dev capabilities */
2070 memset(dev_caps, 0, sizeof(*dev_caps));
2072 /* restore cached values */
2073 dev_caps->common_cap.valid_functions = valid_func;
2074 dev_caps->common_cap.txq_first_id = txq_first_id;
2075 dev_caps->common_cap.rxq_first_id = rxq_first_id;
2076 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2077 dev_caps->common_cap.max_mtu = max_mtu;
2078 dev_caps->num_funcs = num_funcs;
2080 /* one Tx and one Rx queue per function in safe mode */
2081 dev_caps->common_cap.num_rxq = num_funcs;
2082 dev_caps->common_cap.num_txq = num_funcs;
2084 /* two MSIX vectors per function */
2085 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2089 * ice_get_caps - get info about the HW
2090 * @hw: pointer to the hardware structure
2092 enum ice_status ice_get_caps(struct ice_hw *hw)
2094 enum ice_status status;
2096 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2098 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2104 * ice_aq_manage_mac_write - manage MAC address write command
2105 * @hw: pointer to the HW struct
2106 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2107 * @flags: flags to control write behavior
2108 * @cd: pointer to command details structure or NULL
2110 * This function is used to write MAC address to the NVM (0x0108).
2113 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2114 struct ice_sq_cd *cd)
2116 struct ice_aqc_manage_mac_write *cmd;
2117 struct ice_aq_desc desc;
2119 cmd = &desc.params.mac_write;
2120 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2124 /* Prep values for flags, sah, sal */
2125 cmd->sah = HTONS(*((const u16 *)mac_addr));
2126 cmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));
2128 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2132 * ice_aq_clear_pxe_mode
2133 * @hw: pointer to the HW struct
2135 * Tell the firmware that the driver is taking over from PXE (0x0110).
2137 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2139 struct ice_aq_desc desc;
2141 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2142 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2144 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2148 * ice_clear_pxe_mode - clear pxe operations mode
2149 * @hw: pointer to the HW struct
2151 * Make sure all PXE mode settings are cleared, including things
2152 * like descriptor fetch/write-back mode.
2154 void ice_clear_pxe_mode(struct ice_hw *hw)
2156 if (ice_check_sq_alive(hw, &hw->adminq))
2157 ice_aq_clear_pxe_mode(hw);
2161 * ice_get_link_speed_based_on_phy_type - returns link speed
2162 * @phy_type_low: lower part of phy_type
2163 * @phy_type_high: higher part of phy_type
2165 * This helper function will convert an entry in PHY type structure
2166 * [phy_type_low, phy_type_high] to its corresponding link speed.
2167 * Note: In the structure of [phy_type_low, phy_type_high], there should
2168 * be one bit set, as this function will convert one PHY type to its
2170 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2171 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2174 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2176 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2177 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2179 switch (phy_type_low) {
2180 case ICE_PHY_TYPE_LOW_100BASE_TX:
2181 case ICE_PHY_TYPE_LOW_100M_SGMII:
2182 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2184 case ICE_PHY_TYPE_LOW_1000BASE_T:
2185 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2186 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2187 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2188 case ICE_PHY_TYPE_LOW_1G_SGMII:
2189 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2191 case ICE_PHY_TYPE_LOW_2500BASE_T:
2192 case ICE_PHY_TYPE_LOW_2500BASE_X:
2193 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2194 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2196 case ICE_PHY_TYPE_LOW_5GBASE_T:
2197 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2198 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2200 case ICE_PHY_TYPE_LOW_10GBASE_T:
2201 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2202 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2203 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2204 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2205 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2206 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2207 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2209 case ICE_PHY_TYPE_LOW_25GBASE_T:
2210 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2211 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2212 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2213 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2214 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2215 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2216 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2217 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2218 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2219 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2220 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2222 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2223 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2224 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2225 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2226 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2227 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2228 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2230 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2231 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2232 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2233 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2234 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2235 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2236 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2237 case ICE_PHY_TYPE_LOW_50G_AUI2:
2238 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2239 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2240 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2241 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2242 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2243 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2244 case ICE_PHY_TYPE_LOW_50G_AUI1:
2245 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2247 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2248 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2249 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2250 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2251 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2252 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2253 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2254 case ICE_PHY_TYPE_LOW_100G_AUI4:
2255 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2256 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2257 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2258 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2259 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2260 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2263 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2267 switch (phy_type_high) {
2268 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2269 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2270 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2271 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2272 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2273 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2276 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2280 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2281 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2282 return ICE_AQ_LINK_SPEED_UNKNOWN;
2283 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2284 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2285 return ICE_AQ_LINK_SPEED_UNKNOWN;
2286 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2287 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2288 return speed_phy_type_low;
2290 return speed_phy_type_high;
2294 * ice_update_phy_type
2295 * @phy_type_low: pointer to the lower part of phy_type
2296 * @phy_type_high: pointer to the higher part of phy_type
2297 * @link_speeds_bitmap: targeted link speeds bitmap
2299 * Note: For the link_speeds_bitmap structure, you can check it at
2300 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2301 * link_speeds_bitmap include multiple speeds.
2303 * Each entry in this [phy_type_low, phy_type_high] structure will
2304 * present a certain link speed. This helper function will turn on bits
2305 * in [phy_type_low, phy_type_high] structure based on the value of
2306 * link_speeds_bitmap input parameter.
2309 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2310 u16 link_speeds_bitmap)
2317 /* We first check with low part of phy_type */
2318 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2319 pt_low = BIT_ULL(index);
2320 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2322 if (link_speeds_bitmap & speed)
2323 *phy_type_low |= BIT_ULL(index);
2326 /* We then check with high part of phy_type */
2327 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2328 pt_high = BIT_ULL(index);
2329 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2331 if (link_speeds_bitmap & speed)
2332 *phy_type_high |= BIT_ULL(index);
2337 * ice_aq_set_phy_cfg
2338 * @hw: pointer to the HW struct
2339 * @pi: port info structure of the interested logical port
2340 * @cfg: structure with PHY configuration data to be set
2341 * @cd: pointer to command details structure or NULL
2343 * Set the various PHY configuration parameters supported on the Port.
2344 * One or more of the Set PHY config parameters may be ignored in an MFP
2345 * mode as the PF may not have the privilege to set some of the PHY Config
2346 * parameters. This status will be indicated by the command response (0x0601).
2349 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2350 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2352 struct ice_aq_desc desc;
2353 enum ice_status status;
2356 return ICE_ERR_PARAM;
2358 /* Ensure that only valid bits of cfg->caps can be turned on. */
2359 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2360 ice_debug(hw, ICE_DBG_PHY,
2361 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2364 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2367 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2368 desc.params.set_phy.lport_num = pi->lport;
2369 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2371 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2372 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2373 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2374 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2375 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2376 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n",
2377 cfg->low_power_ctrl);
2378 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2379 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2380 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2382 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2385 pi->phy.curr_user_phy_cfg = *cfg;
2391 * ice_update_link_info - update status of the HW network link
2392 * @pi: port info structure of the interested logical port
2394 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2396 struct ice_link_status *li;
2397 enum ice_status status;
2400 return ICE_ERR_PARAM;
2402 li = &pi->phy.link_info;
2404 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2408 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2409 struct ice_aqc_get_phy_caps_data *pcaps;
2413 pcaps = (struct ice_aqc_get_phy_caps_data *)
2414 ice_malloc(hw, sizeof(*pcaps));
2416 return ICE_ERR_NO_MEMORY;
2418 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2420 if (status == ICE_SUCCESS)
2421 ice_memcpy(li->module_type, &pcaps->module_type,
2422 sizeof(li->module_type),
2423 ICE_NONDMA_TO_NONDMA);
2425 ice_free(hw, pcaps);
2432 * ice_cache_phy_user_req
2433 * @pi: port information structure
2434 * @cache_data: PHY logging data
2435 * @cache_mode: PHY logging mode
2437 * Log the user request on (FC, FEC, SPEED) for later user.
2440 ice_cache_phy_user_req(struct ice_port_info *pi,
2441 struct ice_phy_cache_mode_data cache_data,
2442 enum ice_phy_cache_mode cache_mode)
2447 switch (cache_mode) {
2449 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2451 case ICE_SPEED_MODE:
2452 pi->phy.curr_user_speed_req =
2453 cache_data.data.curr_user_speed_req;
2456 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2464 * ice_caps_to_fc_mode
2465 * @caps: PHY capabilities
2467 * Convert PHY FC capabilities to ice FC mode
2469 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2471 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2472 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2475 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2476 return ICE_FC_TX_PAUSE;
2478 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2479 return ICE_FC_RX_PAUSE;
2485 * ice_caps_to_fec_mode
2486 * @caps: PHY capabilities
2487 * @fec_options: Link FEC options
2489 * Convert PHY FEC capabilities to ice FEC mode
2491 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2493 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2494 return ICE_FEC_AUTO;
2496 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2497 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2498 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2499 ICE_AQC_PHY_FEC_25G_KR_REQ))
2500 return ICE_FEC_BASER;
2502 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2503 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2504 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2507 return ICE_FEC_NONE;
2512 * @pi: port information structure
2513 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2514 * @ena_auto_link_update: enable automatic link update
2516 * Set the requested flow control mode.
2519 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2521 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2522 struct ice_phy_cache_mode_data cache_data;
2523 struct ice_aqc_get_phy_caps_data *pcaps;
2524 enum ice_status status;
2525 u8 pause_mask = 0x0;
2529 return ICE_ERR_PARAM;
2531 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2533 /* Cache user FC request */
2534 cache_data.data.curr_user_fc_req = pi->fc.req_mode;
2535 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2537 switch (pi->fc.req_mode) {
2539 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2540 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2542 case ICE_FC_RX_PAUSE:
2543 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2545 case ICE_FC_TX_PAUSE:
2546 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2552 pcaps = (struct ice_aqc_get_phy_caps_data *)
2553 ice_malloc(hw, sizeof(*pcaps));
2555 return ICE_ERR_NO_MEMORY;
2557 /* Get the current PHY config */
2558 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2561 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2565 /* clear the old pause settings */
2566 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2567 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2569 /* set the new capabilities */
2570 cfg.caps |= pause_mask;
2572 /* If the capabilities have changed, then set the new config */
2573 if (cfg.caps != pcaps->caps) {
2574 int retry_count, retry_max = 10;
2576 /* Auto restart link so settings take effect */
2577 if (ena_auto_link_update)
2578 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2579 /* Copy over all the old settings */
2580 cfg.phy_type_high = pcaps->phy_type_high;
2581 cfg.phy_type_low = pcaps->phy_type_low;
2582 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2583 cfg.eee_cap = pcaps->eee_cap;
2584 cfg.eeer_value = pcaps->eeer_value;
2585 cfg.link_fec_opt = pcaps->link_fec_options;
2587 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2589 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2593 /* Update the link info
2594 * It sometimes takes a really long time for link to
2595 * come back from the atomic reset. Thus, we wait a
2598 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2599 status = ice_update_link_info(pi);
2601 if (status == ICE_SUCCESS)
2604 ice_msec_delay(100, true);
2608 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2612 ice_free(hw, pcaps);
2617 * ice_phy_caps_equals_cfg
2618 * @phy_caps: PHY capabilities
2619 * @phy_cfg: PHY configuration
2621 * Helper function to determine if PHY capabilities matches PHY
2625 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2626 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2628 u8 caps_mask, cfg_mask;
2630 if (!phy_caps || !phy_cfg)
2633 /* These bits are not common between capabilities and configuration.
2634 * Do not use them to determine equality.
2636 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2637 ICE_AQC_PHY_EN_MOD_QUAL);
2638 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2640 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2641 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2642 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2643 phy_caps->low_power_ctrl != phy_cfg->low_power_ctrl ||
2644 phy_caps->eee_cap != phy_cfg->eee_cap ||
2645 phy_caps->eeer_value != phy_cfg->eeer_value ||
2646 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2653 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2654 * @caps: PHY ability structure to copy date from
2655 * @cfg: PHY configuration structure to copy data to
2657 * Helper function to copy AQC PHY get ability data to PHY set configuration
2661 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2662 struct ice_aqc_set_phy_cfg_data *cfg)
2667 cfg->phy_type_low = caps->phy_type_low;
2668 cfg->phy_type_high = caps->phy_type_high;
2669 cfg->caps = caps->caps;
2670 cfg->low_power_ctrl = caps->low_power_ctrl;
2671 cfg->eee_cap = caps->eee_cap;
2672 cfg->eeer_value = caps->eeer_value;
2673 cfg->link_fec_opt = caps->link_fec_options;
2677 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2678 * @cfg: PHY configuration data to set FEC mode
2679 * @fec: FEC mode to configure
2681 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2682 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2683 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2686 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2690 /* Clear RS bits, and AND BASE-R ability
2691 * bits and OR request bits.
2693 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2694 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2695 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2696 ICE_AQC_PHY_FEC_25G_KR_REQ;
2699 /* Clear BASE-R bits, and AND RS ability
2700 * bits and OR request bits.
2702 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2703 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2704 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2707 /* Clear all FEC option bits. */
2708 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2711 /* AND auto FEC bit, and all caps bits. */
2712 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2718 * ice_get_link_status - get status of the HW network link
2719 * @pi: port information structure
2720 * @link_up: pointer to bool (true/false = linkup/linkdown)
2722 * Variable link_up is true if link is up, false if link is down.
2723 * The variable link_up is invalid if status is non zero. As a
2724 * result of this call, link status reporting becomes enabled
2726 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2728 struct ice_phy_info *phy_info;
2729 enum ice_status status = ICE_SUCCESS;
2731 if (!pi || !link_up)
2732 return ICE_ERR_PARAM;
2734 phy_info = &pi->phy;
2736 if (phy_info->get_link_info) {
2737 status = ice_update_link_info(pi);
2740 ice_debug(pi->hw, ICE_DBG_LINK,
2741 "get link status error, status = %d\n",
2745 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2751 * ice_aq_set_link_restart_an
2752 * @pi: pointer to the port information structure
2753 * @ena_link: if true: enable link, if false: disable link
2754 * @cd: pointer to command details structure or NULL
2756 * Sets up the link and restarts the Auto-Negotiation over the link.
2759 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2760 struct ice_sq_cd *cd)
2762 struct ice_aqc_restart_an *cmd;
2763 struct ice_aq_desc desc;
2765 cmd = &desc.params.restart_an;
2767 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2769 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2770 cmd->lport_num = pi->lport;
2772 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2774 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2776 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2780 * ice_aq_set_event_mask
2781 * @hw: pointer to the HW struct
2782 * @port_num: port number of the physical function
2783 * @mask: event mask to be set
2784 * @cd: pointer to command details structure or NULL
2786 * Set event mask (0x0613)
2789 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2790 struct ice_sq_cd *cd)
2792 struct ice_aqc_set_event_mask *cmd;
2793 struct ice_aq_desc desc;
2795 cmd = &desc.params.set_event_mask;
2797 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2799 cmd->lport_num = port_num;
2801 cmd->event_mask = CPU_TO_LE16(mask);
2802 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2806 * ice_aq_set_mac_loopback
2807 * @hw: pointer to the HW struct
2808 * @ena_lpbk: Enable or Disable loopback
2809 * @cd: pointer to command details structure or NULL
2811 * Enable/disable loopback on a given port
2814 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2816 struct ice_aqc_set_mac_lb *cmd;
2817 struct ice_aq_desc desc;
2819 cmd = &desc.params.set_mac_lb;
2821 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2823 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2825 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2829 * ice_aq_set_port_id_led
2830 * @pi: pointer to the port information
2831 * @is_orig_mode: is this LED set to original mode (by the net-list)
2832 * @cd: pointer to command details structure or NULL
2834 * Set LED value for the given port (0x06e9)
2837 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2838 struct ice_sq_cd *cd)
2840 struct ice_aqc_set_port_id_led *cmd;
2841 struct ice_hw *hw = pi->hw;
2842 struct ice_aq_desc desc;
2844 cmd = &desc.params.set_port_id_led;
2846 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2849 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2851 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2853 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2858 * @hw: pointer to the HW struct
2859 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
2860 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
2861 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
2863 * @set_page: set or ignore the page
2864 * @data: pointer to data buffer to be read/written to the I2C device.
2865 * @length: 1-16 for read, 1 for write.
2866 * @write: 0 read, 1 for write.
2867 * @cd: pointer to command details structure or NULL
2869 * Read/Write SFF EEPROM (0x06EE)
2872 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
2873 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
2874 bool write, struct ice_sq_cd *cd)
2876 struct ice_aqc_sff_eeprom *cmd;
2877 struct ice_aq_desc desc;
2878 enum ice_status status;
2880 if (!data || (mem_addr & 0xff00))
2881 return ICE_ERR_PARAM;
2883 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
2884 cmd = &desc.params.read_write_sff_param;
2885 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
2886 cmd->lport_num = (u8)(lport & 0xff);
2887 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
2888 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
2889 ICE_AQC_SFF_I2CBUS_7BIT_M) |
2891 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
2892 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
2893 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
2894 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
2896 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
2898 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
2903 * __ice_aq_get_set_rss_lut
2904 * @hw: pointer to the hardware structure
2905 * @vsi_id: VSI FW index
2906 * @lut_type: LUT table type
2907 * @lut: pointer to the LUT buffer provided by the caller
2908 * @lut_size: size of the LUT buffer
2909 * @glob_lut_idx: global LUT index
2910 * @set: set true to set the table, false to get the table
2912 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2914 static enum ice_status
2915 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2916 u16 lut_size, u8 glob_lut_idx, bool set)
2918 struct ice_aqc_get_set_rss_lut *cmd_resp;
2919 struct ice_aq_desc desc;
2920 enum ice_status status;
2923 cmd_resp = &desc.params.get_set_rss_lut;
2926 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2927 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2929 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2932 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2933 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2934 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2935 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2938 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2939 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2940 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2941 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2942 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2945 status = ICE_ERR_PARAM;
2946 goto ice_aq_get_set_rss_lut_exit;
2949 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2950 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2951 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2954 goto ice_aq_get_set_rss_lut_send;
2955 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2957 goto ice_aq_get_set_rss_lut_send;
2959 goto ice_aq_get_set_rss_lut_send;
2962 /* LUT size is only valid for Global and PF table types */
2964 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2965 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
2966 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2967 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2969 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
2970 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2971 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2972 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2974 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
2975 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2976 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
2977 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2978 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2983 status = ICE_ERR_PARAM;
2984 goto ice_aq_get_set_rss_lut_exit;
2987 ice_aq_get_set_rss_lut_send:
2988 cmd_resp->flags = CPU_TO_LE16(flags);
2989 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
2991 ice_aq_get_set_rss_lut_exit:
2996 * ice_aq_get_rss_lut
2997 * @hw: pointer to the hardware structure
2998 * @vsi_handle: software VSI handle
2999 * @lut_type: LUT table type
3000 * @lut: pointer to the LUT buffer provided by the caller
3001 * @lut_size: size of the LUT buffer
3003 * get the RSS lookup table, PF or VSI type
3006 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3007 u8 *lut, u16 lut_size)
3009 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3010 return ICE_ERR_PARAM;
3012 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3013 lut_type, lut, lut_size, 0, false);
3017 * ice_aq_set_rss_lut
3018 * @hw: pointer to the hardware structure
3019 * @vsi_handle: software VSI handle
3020 * @lut_type: LUT table type
3021 * @lut: pointer to the LUT buffer provided by the caller
3022 * @lut_size: size of the LUT buffer
3024 * set the RSS lookup table, PF or VSI type
3027 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3028 u8 *lut, u16 lut_size)
3030 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3031 return ICE_ERR_PARAM;
3033 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3034 lut_type, lut, lut_size, 0, true);
3038 * __ice_aq_get_set_rss_key
3039 * @hw: pointer to the HW struct
3040 * @vsi_id: VSI FW index
3041 * @key: pointer to key info struct
3042 * @set: set true to set the key, false to get the key
3044 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3047 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3048 struct ice_aqc_get_set_rss_keys *key,
3051 struct ice_aqc_get_set_rss_key *cmd_resp;
3052 u16 key_size = sizeof(*key);
3053 struct ice_aq_desc desc;
3055 cmd_resp = &desc.params.get_set_rss_key;
3058 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3059 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3061 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3064 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3065 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3066 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3067 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3069 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3073 * ice_aq_get_rss_key
3074 * @hw: pointer to the HW struct
3075 * @vsi_handle: software VSI handle
3076 * @key: pointer to key info struct
3078 * get the RSS key per VSI
3081 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3082 struct ice_aqc_get_set_rss_keys *key)
3084 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3085 return ICE_ERR_PARAM;
3087 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3092 * ice_aq_set_rss_key
3093 * @hw: pointer to the HW struct
3094 * @vsi_handle: software VSI handle
3095 * @keys: pointer to key info struct
3097 * set the RSS key per VSI
3100 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3101 struct ice_aqc_get_set_rss_keys *keys)
3103 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3104 return ICE_ERR_PARAM;
3106 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3111 * ice_aq_add_lan_txq
3112 * @hw: pointer to the hardware structure
3113 * @num_qgrps: Number of added queue groups
3114 * @qg_list: list of queue groups to be added
3115 * @buf_size: size of buffer for indirect command
3116 * @cd: pointer to command details structure or NULL
3118 * Add Tx LAN queue (0x0C30)
3121 * Prior to calling add Tx LAN queue:
3122 * Initialize the following as part of the Tx queue context:
3123 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3124 * Cache profile and Packet shaper profile.
3126 * After add Tx LAN queue AQ command is completed:
3127 * Interrupts should be associated with specific queues,
3128 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3132 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3133 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3134 struct ice_sq_cd *cd)
3136 u16 i, sum_header_size, sum_q_size = 0;
3137 struct ice_aqc_add_tx_qgrp *list;
3138 struct ice_aqc_add_txqs *cmd;
3139 struct ice_aq_desc desc;
3141 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3143 cmd = &desc.params.add_txqs;
3145 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3148 return ICE_ERR_PARAM;
3150 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3151 return ICE_ERR_PARAM;
3153 sum_header_size = num_qgrps *
3154 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3157 for (i = 0; i < num_qgrps; i++) {
3158 struct ice_aqc_add_txqs_perq *q = list->txqs;
3160 sum_q_size += list->num_txqs * sizeof(*q);
3161 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3164 if (buf_size != (sum_header_size + sum_q_size))
3165 return ICE_ERR_PARAM;
3167 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3169 cmd->num_qgrps = num_qgrps;
3171 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3175 * ice_aq_dis_lan_txq
3176 * @hw: pointer to the hardware structure
3177 * @num_qgrps: number of groups in the list
3178 * @qg_list: the list of groups to disable
3179 * @buf_size: the total size of the qg_list buffer in bytes
3180 * @rst_src: if called due to reset, specifies the reset source
3181 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3182 * @cd: pointer to command details structure or NULL
3184 * Disable LAN Tx queue (0x0C31)
3186 static enum ice_status
3187 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3188 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3189 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3190 struct ice_sq_cd *cd)
3192 struct ice_aqc_dis_txqs *cmd;
3193 struct ice_aq_desc desc;
3194 enum ice_status status;
3197 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3198 cmd = &desc.params.dis_txqs;
3199 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3201 /* qg_list can be NULL only in VM/VF reset flow */
3202 if (!qg_list && !rst_src)
3203 return ICE_ERR_PARAM;
3205 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3206 return ICE_ERR_PARAM;
3208 cmd->num_entries = num_qgrps;
3210 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3211 ICE_AQC_Q_DIS_TIMEOUT_M);
3215 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3216 cmd->vmvf_and_timeout |=
3217 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3224 /* flush pipe on time out */
3225 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3226 /* If no queue group info, we are in a reset flow. Issue the AQ */
3230 /* set RD bit to indicate that command buffer is provided by the driver
3231 * and it needs to be read by the firmware
3233 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3235 for (i = 0; i < num_qgrps; ++i) {
3236 /* Calculate the size taken up by the queue IDs in this group */
3237 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3239 /* Add the size of the group header */
3240 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3242 /* If the num of queues is even, add 2 bytes of padding */
3243 if ((qg_list[i].num_qs % 2) == 0)
3248 return ICE_ERR_PARAM;
3251 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3254 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3255 vmvf_num, hw->adminq.sq_last_status);
3257 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3258 LE16_TO_CPU(qg_list[0].q_id[0]),
3259 hw->adminq.sq_last_status);
3265 * ice_aq_move_recfg_lan_txq
3266 * @hw: pointer to the hardware structure
3267 * @num_qs: number of queues to move/reconfigure
3268 * @is_move: true if this operation involves node movement
3269 * @is_tc_change: true if this operation involves a TC change
3270 * @subseq_call: true if this operation is a subsequent call
3271 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3272 * @timeout: timeout in units of 100 usec (valid values 0-50)
3273 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3274 * @buf: struct containing src/dest TEID and per-queue info
3275 * @buf_size: size of buffer for indirect command
3276 * @txqs_moved: out param, number of queues successfully moved
3277 * @cd: pointer to command details structure or NULL
3279 * Move / Reconfigure Tx LAN queues (0x0C32)
3282 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3283 bool is_tc_change, bool subseq_call, bool flush_pipe,
3284 u8 timeout, u32 *blocked_cgds,
3285 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3286 u8 *txqs_moved, struct ice_sq_cd *cd)
3288 struct ice_aqc_move_txqs *cmd;
3289 struct ice_aq_desc desc;
3290 enum ice_status status;
3292 cmd = &desc.params.move_txqs;
3293 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3295 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3296 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3297 return ICE_ERR_PARAM;
3299 if (is_tc_change && !flush_pipe && !blocked_cgds)
3300 return ICE_ERR_PARAM;
3302 if (!is_move && !is_tc_change)
3303 return ICE_ERR_PARAM;
3305 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3308 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3311 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3314 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3317 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3319 cmd->num_qs = num_qs;
3320 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3321 ICE_AQC_Q_CMD_TIMEOUT_M);
3323 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3325 if (!status && txqs_moved)
3326 *txqs_moved = cmd->num_qs;
3328 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3329 is_tc_change && !flush_pipe)
3330 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3335 /* End of FW Admin Queue command wrappers */
3338 * ice_write_byte - write a byte to a packed context structure
3339 * @src_ctx: the context structure to read from
3340 * @dest_ctx: the context to be written to
3341 * @ce_info: a description of the struct to be filled
3344 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3346 u8 src_byte, dest_byte, mask;
3350 /* copy from the next struct field */
3351 from = src_ctx + ce_info->offset;
3353 /* prepare the bits and mask */
3354 shift_width = ce_info->lsb % 8;
3355 mask = (u8)(BIT(ce_info->width) - 1);
3360 /* shift to correct alignment */
3361 mask <<= shift_width;
3362 src_byte <<= shift_width;
3364 /* get the current bits from the target bit string */
3365 dest = dest_ctx + (ce_info->lsb / 8);
3367 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3369 dest_byte &= ~mask; /* get the bits not changing */
3370 dest_byte |= src_byte; /* add in the new bits */
3372 /* put it all back */
3373 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3377 * ice_write_word - write a word to a packed context structure
3378 * @src_ctx: the context structure to read from
3379 * @dest_ctx: the context to be written to
3380 * @ce_info: a description of the struct to be filled
3383 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3390 /* copy from the next struct field */
3391 from = src_ctx + ce_info->offset;
3393 /* prepare the bits and mask */
3394 shift_width = ce_info->lsb % 8;
3395 mask = BIT(ce_info->width) - 1;
3397 /* don't swizzle the bits until after the mask because the mask bits
3398 * will be in a different bit position on big endian machines
3400 src_word = *(u16 *)from;
3403 /* shift to correct alignment */
3404 mask <<= shift_width;
3405 src_word <<= shift_width;
3407 /* get the current bits from the target bit string */
3408 dest = dest_ctx + (ce_info->lsb / 8);
3410 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3412 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3413 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3415 /* put it all back */
3416 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3420 * ice_write_dword - write a dword to a packed context structure
3421 * @src_ctx: the context structure to read from
3422 * @dest_ctx: the context to be written to
3423 * @ce_info: a description of the struct to be filled
3426 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3428 u32 src_dword, mask;
3433 /* copy from the next struct field */
3434 from = src_ctx + ce_info->offset;
3436 /* prepare the bits and mask */
3437 shift_width = ce_info->lsb % 8;
3439 /* if the field width is exactly 32 on an x86 machine, then the shift
3440 * operation will not work because the SHL instructions count is masked
3441 * to 5 bits so the shift will do nothing
3443 if (ce_info->width < 32)
3444 mask = BIT(ce_info->width) - 1;
3448 /* don't swizzle the bits until after the mask because the mask bits
3449 * will be in a different bit position on big endian machines
3451 src_dword = *(u32 *)from;
3454 /* shift to correct alignment */
3455 mask <<= shift_width;
3456 src_dword <<= shift_width;
3458 /* get the current bits from the target bit string */
3459 dest = dest_ctx + (ce_info->lsb / 8);
3461 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3463 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3464 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3466 /* put it all back */
3467 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3471 * ice_write_qword - write a qword to a packed context structure
3472 * @src_ctx: the context structure to read from
3473 * @dest_ctx: the context to be written to
3474 * @ce_info: a description of the struct to be filled
3477 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3479 u64 src_qword, mask;
3484 /* copy from the next struct field */
3485 from = src_ctx + ce_info->offset;
3487 /* prepare the bits and mask */
3488 shift_width = ce_info->lsb % 8;
3490 /* if the field width is exactly 64 on an x86 machine, then the shift
3491 * operation will not work because the SHL instructions count is masked
3492 * to 6 bits so the shift will do nothing
3494 if (ce_info->width < 64)
3495 mask = BIT_ULL(ce_info->width) - 1;
3499 /* don't swizzle the bits until after the mask because the mask bits
3500 * will be in a different bit position on big endian machines
3502 src_qword = *(u64 *)from;
3505 /* shift to correct alignment */
3506 mask <<= shift_width;
3507 src_qword <<= shift_width;
3509 /* get the current bits from the target bit string */
3510 dest = dest_ctx + (ce_info->lsb / 8);
3512 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3514 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3515 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3517 /* put it all back */
3518 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3522 * ice_set_ctx - set context bits in packed structure
3523 * @src_ctx: pointer to a generic non-packed context structure
3524 * @dest_ctx: pointer to memory for the packed structure
3525 * @ce_info: a description of the structure to be transformed
3528 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3532 for (f = 0; ce_info[f].width; f++) {
3533 /* We have to deal with each element of the FW response
3534 * using the correct size so that we are correct regardless
3535 * of the endianness of the machine.
3537 switch (ce_info[f].size_of) {
3539 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3542 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3545 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3548 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3551 return ICE_ERR_INVAL_SIZE;
3559 * ice_read_byte - read context byte into struct
3560 * @src_ctx: the context structure to read from
3561 * @dest_ctx: the context to be written to
3562 * @ce_info: a description of the struct to be filled
3565 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3571 /* prepare the bits and mask */
3572 shift_width = ce_info->lsb % 8;
3573 mask = (u8)(BIT(ce_info->width) - 1);
3575 /* shift to correct alignment */
3576 mask <<= shift_width;
3578 /* get the current bits from the src bit string */
3579 src = src_ctx + (ce_info->lsb / 8);
3581 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3583 dest_byte &= ~(mask);
3585 dest_byte >>= shift_width;
3587 /* get the address from the struct field */
3588 target = dest_ctx + ce_info->offset;
3590 /* put it back in the struct */
3591 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3595 * ice_read_word - read context word into struct
3596 * @src_ctx: the context structure to read from
3597 * @dest_ctx: the context to be written to
3598 * @ce_info: a description of the struct to be filled
3601 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3603 u16 dest_word, mask;
3608 /* prepare the bits and mask */
3609 shift_width = ce_info->lsb % 8;
3610 mask = BIT(ce_info->width) - 1;
3612 /* shift to correct alignment */
3613 mask <<= shift_width;
3615 /* get the current bits from the src bit string */
3616 src = src_ctx + (ce_info->lsb / 8);
3618 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3620 /* the data in the memory is stored as little endian so mask it
3623 src_word &= ~(CPU_TO_LE16(mask));
3625 /* get the data back into host order before shifting */
3626 dest_word = LE16_TO_CPU(src_word);
3628 dest_word >>= shift_width;
3630 /* get the address from the struct field */
3631 target = dest_ctx + ce_info->offset;
3633 /* put it back in the struct */
3634 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3638 * ice_read_dword - read context dword into struct
3639 * @src_ctx: the context structure to read from
3640 * @dest_ctx: the context to be written to
3641 * @ce_info: a description of the struct to be filled
3644 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3646 u32 dest_dword, mask;
3651 /* prepare the bits and mask */
3652 shift_width = ce_info->lsb % 8;
3654 /* if the field width is exactly 32 on an x86 machine, then the shift
3655 * operation will not work because the SHL instructions count is masked
3656 * to 5 bits so the shift will do nothing
3658 if (ce_info->width < 32)
3659 mask = BIT(ce_info->width) - 1;
3663 /* shift to correct alignment */
3664 mask <<= shift_width;
3666 /* get the current bits from the src bit string */
3667 src = src_ctx + (ce_info->lsb / 8);
3669 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3671 /* the data in the memory is stored as little endian so mask it
3674 src_dword &= ~(CPU_TO_LE32(mask));
3676 /* get the data back into host order before shifting */
3677 dest_dword = LE32_TO_CPU(src_dword);
3679 dest_dword >>= shift_width;
3681 /* get the address from the struct field */
3682 target = dest_ctx + ce_info->offset;
3684 /* put it back in the struct */
3685 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3689 * ice_read_qword - read context qword into struct
3690 * @src_ctx: the context structure to read from
3691 * @dest_ctx: the context to be written to
3692 * @ce_info: a description of the struct to be filled
3695 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3697 u64 dest_qword, mask;
3702 /* prepare the bits and mask */
3703 shift_width = ce_info->lsb % 8;
3705 /* if the field width is exactly 64 on an x86 machine, then the shift
3706 * operation will not work because the SHL instructions count is masked
3707 * to 6 bits so the shift will do nothing
3709 if (ce_info->width < 64)
3710 mask = BIT_ULL(ce_info->width) - 1;
3714 /* shift to correct alignment */
3715 mask <<= shift_width;
3717 /* get the current bits from the src bit string */
3718 src = src_ctx + (ce_info->lsb / 8);
3720 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3722 /* the data in the memory is stored as little endian so mask it
3725 src_qword &= ~(CPU_TO_LE64(mask));
3727 /* get the data back into host order before shifting */
3728 dest_qword = LE64_TO_CPU(src_qword);
3730 dest_qword >>= shift_width;
3732 /* get the address from the struct field */
3733 target = dest_ctx + ce_info->offset;
3735 /* put it back in the struct */
3736 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3740 * ice_get_ctx - extract context bits from a packed structure
3741 * @src_ctx: pointer to a generic packed context structure
3742 * @dest_ctx: pointer to a generic non-packed context structure
3743 * @ce_info: a description of the structure to be read from
3746 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3750 for (f = 0; ce_info[f].width; f++) {
3751 switch (ce_info[f].size_of) {
3753 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3756 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3759 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3762 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3765 /* nothing to do, just keep going */
3774 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3775 * @hw: pointer to the HW struct
3776 * @vsi_handle: software VSI handle
3778 * @q_handle: software queue handle
3781 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3783 struct ice_vsi_ctx *vsi;
3784 struct ice_q_ctx *q_ctx;
3786 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3789 if (q_handle >= vsi->num_lan_q_entries[tc])
3791 if (!vsi->lan_q_ctx[tc])
3793 q_ctx = vsi->lan_q_ctx[tc];
3794 return &q_ctx[q_handle];
3799 * @pi: port information structure
3800 * @vsi_handle: software VSI handle
3802 * @q_handle: software queue handle
3803 * @num_qgrps: Number of added queue groups
3804 * @buf: list of queue groups to be added
3805 * @buf_size: size of buffer for indirect command
3806 * @cd: pointer to command details structure or NULL
3808 * This function adds one LAN queue
3811 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3812 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3813 struct ice_sq_cd *cd)
3815 struct ice_aqc_txsched_elem_data node = { 0 };
3816 struct ice_sched_node *parent;
3817 struct ice_q_ctx *q_ctx;
3818 enum ice_status status;
3821 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3824 if (num_qgrps > 1 || buf->num_txqs > 1)
3825 return ICE_ERR_MAX_LIMIT;
3829 if (!ice_is_vsi_valid(hw, vsi_handle))
3830 return ICE_ERR_PARAM;
3832 ice_acquire_lock(&pi->sched_lock);
3834 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3836 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3838 status = ICE_ERR_PARAM;
3842 /* find a parent node */
3843 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3844 ICE_SCHED_NODE_OWNER_LAN);
3846 status = ICE_ERR_PARAM;
3850 buf->parent_teid = parent->info.node_teid;
3851 node.parent_teid = parent->info.node_teid;
3852 /* Mark that the values in the "generic" section as valid. The default
3853 * value in the "generic" section is zero. This means that :
3854 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3855 * - 0 priority among siblings, indicated by Bit 1-3.
3856 * - WFQ, indicated by Bit 4.
3857 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3859 * - Bit 7 is reserved.
3860 * Without setting the generic section as valid in valid_sections, the
3861 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3863 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3865 /* add the LAN queue */
3866 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3867 if (status != ICE_SUCCESS) {
3868 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3869 LE16_TO_CPU(buf->txqs[0].txq_id),
3870 hw->adminq.sq_last_status);
3874 node.node_teid = buf->txqs[0].q_teid;
3875 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3876 q_ctx->q_handle = q_handle;
3877 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
3879 /* add a leaf node into scheduler tree queue layer */
3880 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3882 status = ice_sched_replay_q_bw(pi, q_ctx);
3885 ice_release_lock(&pi->sched_lock);
3891 * @pi: port information structure
3892 * @vsi_handle: software VSI handle
3894 * @num_queues: number of queues
3895 * @q_handles: pointer to software queue handle array
3896 * @q_ids: pointer to the q_id array
3897 * @q_teids: pointer to queue node teids
3898 * @rst_src: if called due to reset, specifies the reset source
3899 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3900 * @cd: pointer to command details structure or NULL
3902 * This function removes queues and their corresponding nodes in SW DB
3905 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3906 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3907 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3908 struct ice_sq_cd *cd)
3910 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3911 struct ice_aqc_dis_txq_item qg_list;
3912 struct ice_q_ctx *q_ctx;
3915 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3919 /* if queue is disabled already yet the disable queue command
3920 * has to be sent to complete the VF reset, then call
3921 * ice_aq_dis_lan_txq without any queue information
3924 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
3929 ice_acquire_lock(&pi->sched_lock);
3931 for (i = 0; i < num_queues; i++) {
3932 struct ice_sched_node *node;
3934 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3937 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3939 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3943 if (q_ctx->q_handle != q_handles[i]) {
3944 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3945 q_ctx->q_handle, q_handles[i]);
3948 qg_list.parent_teid = node->info.parent_teid;
3950 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
3951 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3952 sizeof(qg_list), rst_src, vmvf_num,
3955 if (status != ICE_SUCCESS)
3957 ice_free_sched_node(pi, node);
3958 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
3960 ice_release_lock(&pi->sched_lock);
3965 * ice_cfg_vsi_qs - configure the new/existing VSI queues
3966 * @pi: port information structure
3967 * @vsi_handle: software VSI handle
3968 * @tc_bitmap: TC bitmap
3969 * @maxqs: max queues array per TC
3970 * @owner: LAN or RDMA
3972 * This function adds/updates the VSI queues per TC.
3974 static enum ice_status
3975 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3976 u16 *maxqs, u8 owner)
3978 enum ice_status status = ICE_SUCCESS;
3981 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3984 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3985 return ICE_ERR_PARAM;
3987 ice_acquire_lock(&pi->sched_lock);
3989 ice_for_each_traffic_class(i) {
3990 /* configuration is possible only if TC node is present */
3991 if (!ice_sched_get_tc_node(pi, i))
3994 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
3995 ice_is_tc_ena(tc_bitmap, i));
4000 ice_release_lock(&pi->sched_lock);
4005 * ice_cfg_vsi_lan - configure VSI LAN queues
4006 * @pi: port information structure
4007 * @vsi_handle: software VSI handle
4008 * @tc_bitmap: TC bitmap
4009 * @max_lanqs: max LAN queues array per TC
4011 * This function adds/updates the VSI LAN queues per TC.
4014 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4017 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4018 ICE_SCHED_NODE_OWNER_LAN);
4022 * ice_replay_pre_init - replay pre initialization
4023 * @hw: pointer to the HW struct
4025 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4027 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
4029 struct ice_switch_info *sw = hw->switch_info;
4032 /* Delete old entries from replay filter list head if there is any */
4033 ice_rm_all_sw_replay_rule_info(hw);
4034 /* In start of replay, move entries into replay_rules list, it
4035 * will allow adding rules entries back to filt_rules list,
4036 * which is operational list.
4038 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4039 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4040 &sw->recp_list[i].filt_replay_rules);
4041 ice_sched_replay_agg_vsi_preinit(hw);
4043 return ice_sched_replay_tc_node_bw(hw->port_info);
4047 * ice_replay_vsi - replay VSI configuration
4048 * @hw: pointer to the HW struct
4049 * @vsi_handle: driver VSI handle
4051 * Restore all VSI configuration after reset. It is required to call this
4052 * function with main VSI first.
4054 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4056 enum ice_status status;
4058 if (!ice_is_vsi_valid(hw, vsi_handle))
4059 return ICE_ERR_PARAM;
4061 /* Replay pre-initialization if there is any */
4062 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
4063 status = ice_replay_pre_init(hw);
4067 /* Replay per VSI all RSS configurations */
4068 status = ice_replay_rss_cfg(hw, vsi_handle);
4071 /* Replay per VSI all filters */
4072 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
4074 status = ice_replay_vsi_agg(hw, vsi_handle);
4079 * ice_replay_post - post replay configuration cleanup
4080 * @hw: pointer to the HW struct
4082 * Post replay cleanup.
4084 void ice_replay_post(struct ice_hw *hw)
4086 /* Delete old entries from replay filter list head */
4087 ice_rm_all_sw_replay_rule_info(hw);
4088 ice_sched_replay_agg(hw);
4092 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4093 * @hw: ptr to the hardware info
4094 * @reg: offset of 64 bit HW register to read from
4095 * @prev_stat_loaded: bool to specify if previous stats are loaded
4096 * @prev_stat: ptr to previous loaded stat value
4097 * @cur_stat: ptr to current stat value
4100 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4101 u64 *prev_stat, u64 *cur_stat)
4103 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4105 /* device stats are not reset at PFR, they likely will not be zeroed
4106 * when the driver starts. Thus, save the value from the first read
4107 * without adding to the statistic value so that we report stats which
4108 * count up from zero.
4110 if (!prev_stat_loaded) {
4111 *prev_stat = new_data;
4115 /* Calculate the difference between the new and old values, and then
4116 * add it to the software stat value.
4118 if (new_data >= *prev_stat)
4119 *cur_stat += new_data - *prev_stat;
4121 /* to manage the potential roll-over */
4122 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4124 /* Update the previously stored value to prepare for next read */
4125 *prev_stat = new_data;
4129 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4130 * @hw: ptr to the hardware info
4131 * @reg: offset of HW register to read from
4132 * @prev_stat_loaded: bool to specify if previous stats are loaded
4133 * @prev_stat: ptr to previous loaded stat value
4134 * @cur_stat: ptr to current stat value
4137 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4138 u64 *prev_stat, u64 *cur_stat)
4142 new_data = rd32(hw, reg);
4144 /* device stats are not reset at PFR, they likely will not be zeroed
4145 * when the driver starts. Thus, save the value from the first read
4146 * without adding to the statistic value so that we report stats which
4147 * count up from zero.
4149 if (!prev_stat_loaded) {
4150 *prev_stat = new_data;
4154 /* Calculate the difference between the new and old values, and then
4155 * add it to the software stat value.
4157 if (new_data >= *prev_stat)
4158 *cur_stat += new_data - *prev_stat;
4160 /* to manage the potential roll-over */
4161 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4163 /* Update the previously stored value to prepare for next read */
4164 *prev_stat = new_data;
4168 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4169 * @hw: ptr to the hardware info
4170 * @vsi_handle: VSI handle
4171 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4172 * @cur_stats: ptr to current stats structure
4174 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4175 * thus cannot be read using the normal ice_stat_update32 function.
4177 * Read the GLV_REPC register associated with the given VSI, and update the
4178 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4180 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4181 * cleared each time it's read.
4183 * Note that the GLV_RDPC register also counts the causes that would trigger
4184 * GLV_REPC. However, it does not give the finer grained detail about why the
4185 * packets are being dropped. The GLV_REPC values can be used to distinguish
4186 * whether Rx packets are dropped due to errors or due to no available
4190 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4191 struct ice_eth_stats *cur_stats)
4193 u16 vsi_num, no_desc, error_cnt;
4196 if (!ice_is_vsi_valid(hw, vsi_handle))
4199 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4201 /* If we haven't loaded stats yet, just clear the current value */
4202 if (!prev_stat_loaded) {
4203 wr32(hw, GLV_REPC(vsi_num), 0);
4207 repc = rd32(hw, GLV_REPC(vsi_num));
4208 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4209 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4211 /* Clear the count by writing to the stats register */
4212 wr32(hw, GLV_REPC(vsi_num), 0);
4214 cur_stats->rx_no_desc += no_desc;
4215 cur_stats->rx_errors += error_cnt;
4219 * ice_sched_query_elem - query element information from HW
4220 * @hw: pointer to the HW struct
4221 * @node_teid: node TEID to be queried
4222 * @buf: buffer to element information
4224 * This function queries HW element information
4227 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4228 struct ice_aqc_get_elem *buf)
4230 u16 buf_size, num_elem_ret = 0;
4231 enum ice_status status;
4233 buf_size = sizeof(*buf);
4234 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4235 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4236 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4238 if (status != ICE_SUCCESS || num_elem_ret != 1)
4239 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4244 * ice_get_fw_mode - returns FW mode
4245 * @hw: pointer to the HW struct
4247 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4249 #define ICE_FW_MODE_DBG_M BIT(0)
4250 #define ICE_FW_MODE_REC_M BIT(1)
4251 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4254 /* check the current FW mode */
4255 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4257 if (fw_mode & ICE_FW_MODE_DBG_M)
4258 return ICE_FW_MODE_DBG;
4259 else if (fw_mode & ICE_FW_MODE_REC_M)
4260 return ICE_FW_MODE_REC;
4261 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4262 return ICE_FW_MODE_ROLLBACK;
4264 return ICE_FW_MODE_NORMAL;