1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020
5 #include "ice_common.h"
7 #include "ice_adminq_cmd.h"
10 #include "ice_switch.h"
12 #define ICE_PF_RESET_WAIT_COUNT 300
15 * ice_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
18 * This function sets the MAC type of the adapter based on the
19 * vendor ID and device ID stored in the HW structure.
21 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
23 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
25 if (hw->vendor_id != ICE_INTEL_VENDOR_ID)
26 return ICE_ERR_DEVICE_NOT_SUPPORTED;
28 switch (hw->device_id) {
29 case ICE_DEV_ID_E810C_BACKPLANE:
30 case ICE_DEV_ID_E810C_QSFP:
31 case ICE_DEV_ID_E810C_SFP:
32 case ICE_DEV_ID_E810_XXV_BACKPLANE:
33 case ICE_DEV_ID_E810_XXV_QSFP:
34 case ICE_DEV_ID_E810_XXV_SFP:
35 hw->mac_type = ICE_MAC_E810;
37 case ICE_DEV_ID_E822C_10G_BASE_T:
38 case ICE_DEV_ID_E822C_BACKPLANE:
39 case ICE_DEV_ID_E822C_QSFP:
40 case ICE_DEV_ID_E822C_SFP:
41 case ICE_DEV_ID_E822C_SGMII:
42 case ICE_DEV_ID_E822L_10G_BASE_T:
43 case ICE_DEV_ID_E822L_BACKPLANE:
44 case ICE_DEV_ID_E822L_SFP:
45 case ICE_DEV_ID_E822L_SGMII:
46 hw->mac_type = ICE_MAC_GENERIC;
49 hw->mac_type = ICE_MAC_UNKNOWN;
53 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
58 * ice_clear_pf_cfg - Clear PF configuration
59 * @hw: pointer to the hardware structure
61 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
62 * configuration, flow director filters, etc.).
64 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
66 struct ice_aq_desc desc;
68 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
70 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
74 * ice_aq_manage_mac_read - manage MAC address read command
75 * @hw: pointer to the HW struct
76 * @buf: a virtual buffer to hold the manage MAC read response
77 * @buf_size: Size of the virtual buffer
78 * @cd: pointer to command details structure or NULL
80 * This function is used to return per PF station MAC address (0x0107).
81 * NOTE: Upon successful completion of this command, MAC address information
82 * is returned in user specified buffer. Please interpret user specified
83 * buffer as "manage_mac_read" response.
84 * Response such as various MAC addresses are stored in HW struct (port.mac)
85 * ice_aq_discover_caps is expected to be called before this function is called.
87 static enum ice_status
88 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
91 struct ice_aqc_manage_mac_read_resp *resp;
92 struct ice_aqc_manage_mac_read *cmd;
93 struct ice_aq_desc desc;
94 enum ice_status status;
98 cmd = &desc.params.mac_read;
100 if (buf_size < sizeof(*resp))
101 return ICE_ERR_BUF_TOO_SHORT;
103 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
105 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
109 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
110 flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
112 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
113 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
117 /* A single port can report up to two (LAN and WoL) addresses */
118 for (i = 0; i < cmd->num_addr; i++)
119 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
120 ice_memcpy(hw->port_info->mac.lan_addr,
121 resp[i].mac_addr, ETH_ALEN,
123 ice_memcpy(hw->port_info->mac.perm_addr,
125 ETH_ALEN, ICE_DMA_TO_NONDMA);
132 * ice_aq_get_phy_caps - returns PHY capabilities
133 * @pi: port information structure
134 * @qual_mods: report qualified modules
135 * @report_mode: report mode capabilities
136 * @pcaps: structure for PHY capabilities to be filled
137 * @cd: pointer to command details structure or NULL
139 * Returns the various PHY capabilities supported on the Port (0x0600)
142 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
143 struct ice_aqc_get_phy_caps_data *pcaps,
144 struct ice_sq_cd *cd)
146 struct ice_aqc_get_phy_caps *cmd;
147 u16 pcaps_size = sizeof(*pcaps);
148 struct ice_aq_desc desc;
149 enum ice_status status;
151 cmd = &desc.params.get_phy;
153 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
154 return ICE_ERR_PARAM;
156 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
159 cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
161 cmd->param0 |= CPU_TO_LE16(report_mode);
162 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
164 if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
165 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
166 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
173 * ice_aq_get_link_topo_handle - get link topology node return status
174 * @pi: port information structure
175 * @node_type: requested node type
176 * @cd: pointer to command details structure or NULL
178 * Get link topology node return status for specified node type (0x06E0)
180 * Node type cage can be used to determine if cage is present. If AQC
181 * returns error (ENOENT), then no cage present. If no cage present, then
182 * connection type is backplane or BASE-T.
184 static enum ice_status
185 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
186 struct ice_sq_cd *cd)
188 struct ice_aqc_get_link_topo *cmd;
189 struct ice_aq_desc desc;
191 cmd = &desc.params.get_link_topo;
193 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
195 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
196 ICE_AQC_LINK_TOPO_NODE_CTX_S);
199 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
201 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
205 * ice_is_media_cage_present
206 * @pi: port information structure
208 * Returns true if media cage is present, else false. If no cage, then
209 * media type is backplane or BASE-T.
211 static bool ice_is_media_cage_present(struct ice_port_info *pi)
213 /* Node type cage can be used to determine if cage is present. If AQC
214 * returns error (ENOENT), then no cage present. If no cage present then
215 * connection type is backplane or BASE-T.
217 return !ice_aq_get_link_topo_handle(pi,
218 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
223 * ice_get_media_type - Gets media type
224 * @pi: port information structure
226 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
228 struct ice_link_status *hw_link_info;
231 return ICE_MEDIA_UNKNOWN;
233 hw_link_info = &pi->phy.link_info;
234 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
235 /* If more than one media type is selected, report unknown */
236 return ICE_MEDIA_UNKNOWN;
238 if (hw_link_info->phy_type_low) {
239 switch (hw_link_info->phy_type_low) {
240 case ICE_PHY_TYPE_LOW_1000BASE_SX:
241 case ICE_PHY_TYPE_LOW_1000BASE_LX:
242 case ICE_PHY_TYPE_LOW_10GBASE_SR:
243 case ICE_PHY_TYPE_LOW_10GBASE_LR:
244 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
245 case ICE_PHY_TYPE_LOW_25GBASE_SR:
246 case ICE_PHY_TYPE_LOW_25GBASE_LR:
247 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
248 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
249 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
250 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
251 case ICE_PHY_TYPE_LOW_50GBASE_SR:
252 case ICE_PHY_TYPE_LOW_50GBASE_FR:
253 case ICE_PHY_TYPE_LOW_50GBASE_LR:
254 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
255 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
256 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
257 case ICE_PHY_TYPE_LOW_100GBASE_DR:
258 return ICE_MEDIA_FIBER;
259 case ICE_PHY_TYPE_LOW_100BASE_TX:
260 case ICE_PHY_TYPE_LOW_1000BASE_T:
261 case ICE_PHY_TYPE_LOW_2500BASE_T:
262 case ICE_PHY_TYPE_LOW_5GBASE_T:
263 case ICE_PHY_TYPE_LOW_10GBASE_T:
264 case ICE_PHY_TYPE_LOW_25GBASE_T:
265 return ICE_MEDIA_BASET;
266 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
267 case ICE_PHY_TYPE_LOW_25GBASE_CR:
268 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
269 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
270 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
271 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
272 case ICE_PHY_TYPE_LOW_50GBASE_CP:
273 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
274 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
275 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
277 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
278 case ICE_PHY_TYPE_LOW_40G_XLAUI:
279 case ICE_PHY_TYPE_LOW_50G_LAUI2:
280 case ICE_PHY_TYPE_LOW_50G_AUI2:
281 case ICE_PHY_TYPE_LOW_50G_AUI1:
282 case ICE_PHY_TYPE_LOW_100G_AUI4:
283 case ICE_PHY_TYPE_LOW_100G_CAUI4:
284 if (ice_is_media_cage_present(pi))
287 case ICE_PHY_TYPE_LOW_1000BASE_KX:
288 case ICE_PHY_TYPE_LOW_2500BASE_KX:
289 case ICE_PHY_TYPE_LOW_2500BASE_X:
290 case ICE_PHY_TYPE_LOW_5GBASE_KR:
291 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
292 case ICE_PHY_TYPE_LOW_25GBASE_KR:
293 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
294 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
295 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
296 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
297 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
298 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
299 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
300 return ICE_MEDIA_BACKPLANE;
303 switch (hw_link_info->phy_type_high) {
304 case ICE_PHY_TYPE_HIGH_100G_AUI2:
305 if (ice_is_media_cage_present(pi))
308 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
309 return ICE_MEDIA_BACKPLANE;
312 return ICE_MEDIA_UNKNOWN;
316 * ice_aq_get_link_info
317 * @pi: port information structure
318 * @ena_lse: enable/disable LinkStatusEvent reporting
319 * @link: pointer to link status structure - optional
320 * @cd: pointer to command details structure or NULL
322 * Get Link Status (0x607). Returns the link status of the adapter.
325 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
326 struct ice_link_status *link, struct ice_sq_cd *cd)
328 struct ice_aqc_get_link_status_data link_data = { 0 };
329 struct ice_aqc_get_link_status *resp;
330 struct ice_link_status *li_old, *li;
331 enum ice_media_type *hw_media_type;
332 struct ice_fc_info *hw_fc_info;
333 bool tx_pause, rx_pause;
334 struct ice_aq_desc desc;
335 enum ice_status status;
340 return ICE_ERR_PARAM;
342 li_old = &pi->phy.link_info_old;
343 hw_media_type = &pi->phy.media_type;
344 li = &pi->phy.link_info;
345 hw_fc_info = &pi->fc;
347 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
348 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
349 resp = &desc.params.get_link_status;
350 resp->cmd_flags = CPU_TO_LE16(cmd_flags);
351 resp->lport_num = pi->lport;
353 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
355 if (status != ICE_SUCCESS)
358 /* save off old link status information */
361 /* update current link status information */
362 li->link_speed = LE16_TO_CPU(link_data.link_speed);
363 li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);
364 li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);
365 *hw_media_type = ice_get_media_type(pi);
366 li->link_info = link_data.link_info;
367 li->an_info = link_data.an_info;
368 li->ext_info = link_data.ext_info;
369 li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);
370 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
371 li->topo_media_conflict = link_data.topo_media_conflict;
372 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
373 ICE_AQ_CFG_PACING_TYPE_M);
376 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
377 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
378 if (tx_pause && rx_pause)
379 hw_fc_info->current_mode = ICE_FC_FULL;
381 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
383 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
385 hw_fc_info->current_mode = ICE_FC_NONE;
387 li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));
389 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
390 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
391 (unsigned long long)li->phy_type_low);
392 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
393 (unsigned long long)li->phy_type_high);
394 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
395 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
396 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
397 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
398 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
399 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
400 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
402 /* save link status information */
406 /* flag cleared so calling functions don't call AQ again */
407 pi->phy.get_link_info = false;
414 * @hw: pointer to the HW struct
415 * @max_frame_size: Maximum Frame Size to be supported
416 * @cd: pointer to command details structure or NULL
418 * Set MAC configuration (0x0603)
421 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
423 u16 fc_threshold_val, tx_timer_val;
424 struct ice_aqc_set_mac_cfg *cmd;
425 struct ice_aq_desc desc;
428 cmd = &desc.params.set_mac_cfg;
430 if (max_frame_size == 0)
431 return ICE_ERR_PARAM;
433 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
435 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
437 /* We read back the transmit timer and fc threshold value of
438 * LFC. Thus, we will use index =
439 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
441 * Also, because we are opearating on transmit timer and fc
442 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
444 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
446 /* Retrieve the transmit timer */
448 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
449 tx_timer_val = reg_val &
450 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
451 cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);
453 /* Retrieve the fc threshold */
455 PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
456 fc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);
457 cmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);
459 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
463 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
464 * @hw: pointer to the HW struct
466 enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
468 struct ice_switch_info *sw;
470 hw->switch_info = (struct ice_switch_info *)
471 ice_malloc(hw, sizeof(*hw->switch_info));
473 sw = hw->switch_info;
476 return ICE_ERR_NO_MEMORY;
478 INIT_LIST_HEAD(&sw->vsi_list_map_head);
480 return ice_init_def_sw_recp(hw, &hw->switch_info->recp_list);
484 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
485 * @hw: pointer to the HW struct
487 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
489 struct ice_switch_info *sw = hw->switch_info;
490 struct ice_vsi_list_map_info *v_pos_map;
491 struct ice_vsi_list_map_info *v_tmp_map;
492 struct ice_sw_recipe *recps;
495 LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
496 ice_vsi_list_map_info, list_entry) {
497 LIST_DEL(&v_pos_map->list_entry);
498 ice_free(hw, v_pos_map);
500 recps = hw->switch_info->recp_list;
501 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
502 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
504 recps[i].root_rid = i;
505 LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,
506 &recps[i].rg_list, ice_recp_grp_entry,
508 LIST_DEL(&rg_entry->l_entry);
509 ice_free(hw, rg_entry);
512 if (recps[i].adv_rule) {
513 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
514 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
516 ice_destroy_lock(&recps[i].filt_rule_lock);
517 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
518 &recps[i].filt_rules,
519 ice_adv_fltr_mgmt_list_entry,
521 LIST_DEL(&lst_itr->list_entry);
522 ice_free(hw, lst_itr->lkups);
523 ice_free(hw, lst_itr);
526 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
528 ice_destroy_lock(&recps[i].filt_rule_lock);
529 LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,
530 &recps[i].filt_rules,
531 ice_fltr_mgmt_list_entry,
533 LIST_DEL(&lst_itr->list_entry);
534 ice_free(hw, lst_itr);
537 if (recps[i].root_buf)
538 ice_free(hw, recps[i].root_buf);
540 ice_rm_all_sw_replay_rule_info(hw);
541 ice_free(hw, sw->recp_list);
546 * ice_get_itr_intrl_gran
547 * @hw: pointer to the HW struct
549 * Determines the ITR/INTRL granularities based on the maximum aggregate
550 * bandwidth according to the device's configuration during power-on.
552 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
554 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
555 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
556 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
558 switch (max_agg_bw) {
559 case ICE_MAX_AGG_BW_200G:
560 case ICE_MAX_AGG_BW_100G:
561 case ICE_MAX_AGG_BW_50G:
562 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
563 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
565 case ICE_MAX_AGG_BW_25G:
566 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
567 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
573 * ice_print_rollback_msg - print FW rollback message
574 * @hw: pointer to the hardware structure
576 void ice_print_rollback_msg(struct ice_hw *hw)
578 char nvm_str[ICE_NVM_VER_LEN] = { 0 };
579 struct ice_nvm_info *nvm = &hw->nvm;
580 struct ice_orom_info *orom;
584 SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d",
585 nvm->major_ver, nvm->minor_ver, nvm->eetrack, orom->major,
586 orom->build, orom->patch);
588 "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n",
589 nvm_str, hw->fw_maj_ver, hw->fw_min_ver);
593 * ice_init_hw - main hardware initialization routine
594 * @hw: pointer to the hardware structure
596 enum ice_status ice_init_hw(struct ice_hw *hw)
598 struct ice_aqc_get_phy_caps_data *pcaps;
599 enum ice_status status;
603 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
605 /* Set MAC type based on DeviceID */
606 status = ice_set_mac_type(hw);
610 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
611 PF_FUNC_RID_FUNCTION_NUMBER_M) >>
612 PF_FUNC_RID_FUNCTION_NUMBER_S;
614 status = ice_reset(hw, ICE_RESET_PFR);
618 ice_get_itr_intrl_gran(hw);
620 status = ice_create_all_ctrlq(hw);
622 goto err_unroll_cqinit;
624 status = ice_init_nvm(hw);
626 goto err_unroll_cqinit;
628 if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK)
629 ice_print_rollback_msg(hw);
631 status = ice_clear_pf_cfg(hw);
633 goto err_unroll_cqinit;
635 /* Set bit to enable Flow Director filters */
636 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
637 INIT_LIST_HEAD(&hw->fdir_list_head);
639 ice_clear_pxe_mode(hw);
641 status = ice_get_caps(hw);
643 goto err_unroll_cqinit;
645 hw->port_info = (struct ice_port_info *)
646 ice_malloc(hw, sizeof(*hw->port_info));
647 if (!hw->port_info) {
648 status = ICE_ERR_NO_MEMORY;
649 goto err_unroll_cqinit;
652 /* set the back pointer to HW */
653 hw->port_info->hw = hw;
655 /* Initialize port_info struct with switch configuration data */
656 status = ice_get_initial_sw_cfg(hw);
658 goto err_unroll_alloc;
661 /* Query the allocated resources for Tx scheduler */
662 status = ice_sched_query_res_alloc(hw);
664 ice_debug(hw, ICE_DBG_SCHED,
665 "Failed to get scheduler allocated resources\n");
666 goto err_unroll_alloc;
668 ice_sched_get_psm_clk_freq(hw);
670 /* Initialize port_info struct with scheduler data */
671 status = ice_sched_init_port(hw->port_info);
673 goto err_unroll_sched;
675 pcaps = (struct ice_aqc_get_phy_caps_data *)
676 ice_malloc(hw, sizeof(*pcaps));
678 status = ICE_ERR_NO_MEMORY;
679 goto err_unroll_sched;
682 /* Initialize port_info struct with PHY capabilities */
683 status = ice_aq_get_phy_caps(hw->port_info, false,
684 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
687 goto err_unroll_sched;
689 /* Initialize port_info struct with link information */
690 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
692 goto err_unroll_sched;
693 /* need a valid SW entry point to build a Tx tree */
694 if (!hw->sw_entry_point_layer) {
695 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
696 status = ICE_ERR_CFG;
697 goto err_unroll_sched;
699 INIT_LIST_HEAD(&hw->agg_list);
700 /* Initialize max burst size */
701 if (!hw->max_burst_size)
702 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
704 status = ice_init_fltr_mgmt_struct(hw);
706 goto err_unroll_sched;
708 /* Get MAC information */
709 /* A single port can report up to two (LAN and WoL) addresses */
710 mac_buf = ice_calloc(hw, 2,
711 sizeof(struct ice_aqc_manage_mac_read_resp));
712 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
715 status = ICE_ERR_NO_MEMORY;
716 goto err_unroll_fltr_mgmt_struct;
719 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
720 ice_free(hw, mac_buf);
723 goto err_unroll_fltr_mgmt_struct;
724 /* Obtain counter base index which would be used by flow director */
725 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
727 goto err_unroll_fltr_mgmt_struct;
728 status = ice_init_hw_tbls(hw);
730 goto err_unroll_fltr_mgmt_struct;
733 err_unroll_fltr_mgmt_struct:
734 ice_cleanup_fltr_mgmt_struct(hw);
736 ice_sched_cleanup_all(hw);
738 ice_free(hw, hw->port_info);
739 hw->port_info = NULL;
741 ice_destroy_all_ctrlq(hw);
746 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
747 * @hw: pointer to the hardware structure
749 * This should be called only during nominal operation, not as a result of
750 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
751 * applicable initializations if it fails for any reason.
753 void ice_deinit_hw(struct ice_hw *hw)
755 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
756 ice_cleanup_fltr_mgmt_struct(hw);
758 ice_sched_cleanup_all(hw);
759 ice_sched_clear_agg(hw);
761 ice_free_hw_tbls(hw);
764 ice_free(hw, hw->port_info);
765 hw->port_info = NULL;
768 ice_destroy_all_ctrlq(hw);
770 /* Clear VSI contexts if not already cleared */
771 ice_clear_all_vsi_ctx(hw);
775 * ice_check_reset - Check to see if a global reset is complete
776 * @hw: pointer to the hardware structure
778 enum ice_status ice_check_reset(struct ice_hw *hw)
780 u32 cnt, reg = 0, grst_delay, uld_mask;
782 /* Poll for Device Active state in case a recent CORER, GLOBR,
783 * or EMPR has occurred. The grst delay value is in 100ms units.
784 * Add 1sec for outstanding AQ commands that can take a long time.
786 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
787 GLGEN_RSTCTL_GRSTDEL_S) + 10;
789 for (cnt = 0; cnt < grst_delay; cnt++) {
790 ice_msec_delay(100, true);
791 reg = rd32(hw, GLGEN_RSTAT);
792 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
796 if (cnt == grst_delay) {
797 ice_debug(hw, ICE_DBG_INIT,
798 "Global reset polling failed to complete.\n");
799 return ICE_ERR_RESET_FAILED;
802 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
803 GLNVM_ULD_PCIER_DONE_1_M |\
804 GLNVM_ULD_CORER_DONE_M |\
805 GLNVM_ULD_GLOBR_DONE_M |\
806 GLNVM_ULD_POR_DONE_M |\
807 GLNVM_ULD_POR_DONE_1_M |\
808 GLNVM_ULD_PCIER_DONE_2_M)
810 uld_mask = ICE_RESET_DONE_MASK;
812 /* Device is Active; check Global Reset processes are done */
813 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
814 reg = rd32(hw, GLNVM_ULD) & uld_mask;
815 if (reg == uld_mask) {
816 ice_debug(hw, ICE_DBG_INIT,
817 "Global reset processes done. %d\n", cnt);
820 ice_msec_delay(10, true);
823 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
824 ice_debug(hw, ICE_DBG_INIT,
825 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
827 return ICE_ERR_RESET_FAILED;
834 * ice_pf_reset - Reset the PF
835 * @hw: pointer to the hardware structure
837 * If a global reset has been triggered, this function checks
838 * for its completion and then issues the PF reset
840 static enum ice_status ice_pf_reset(struct ice_hw *hw)
844 /* If at function entry a global reset was already in progress, i.e.
845 * state is not 'device active' or any of the reset done bits are not
846 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
847 * global reset is done.
849 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
850 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
851 /* poll on global reset currently in progress until done */
852 if (ice_check_reset(hw))
853 return ICE_ERR_RESET_FAILED;
859 reg = rd32(hw, PFGEN_CTRL);
861 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
863 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
864 reg = rd32(hw, PFGEN_CTRL);
865 if (!(reg & PFGEN_CTRL_PFSWR_M))
868 ice_msec_delay(1, true);
871 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
872 ice_debug(hw, ICE_DBG_INIT,
873 "PF reset polling failed to complete.\n");
874 return ICE_ERR_RESET_FAILED;
881 * ice_reset - Perform different types of reset
882 * @hw: pointer to the hardware structure
883 * @req: reset request
885 * This function triggers a reset as specified by the req parameter.
888 * If anything other than a PF reset is triggered, PXE mode is restored.
889 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
890 * interface has been restored in the rebuild flow.
892 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
898 return ice_pf_reset(hw);
899 case ICE_RESET_CORER:
900 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
901 val = GLGEN_RTRIG_CORER_M;
903 case ICE_RESET_GLOBR:
904 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
905 val = GLGEN_RTRIG_GLOBR_M;
908 return ICE_ERR_PARAM;
911 val |= rd32(hw, GLGEN_RTRIG);
912 wr32(hw, GLGEN_RTRIG, val);
915 /* wait for the FW to be ready */
916 return ice_check_reset(hw);
920 * ice_copy_rxq_ctx_to_hw
921 * @hw: pointer to the hardware structure
922 * @ice_rxq_ctx: pointer to the rxq context
923 * @rxq_index: the index of the Rx queue
925 * Copies rxq context from dense structure to HW register space
927 static enum ice_status
928 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
933 return ICE_ERR_BAD_PTR;
935 if (rxq_index > QRX_CTRL_MAX_INDEX)
936 return ICE_ERR_PARAM;
938 /* Copy each dword separately to HW */
939 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
940 wr32(hw, QRX_CONTEXT(i, rxq_index),
941 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
943 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
944 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
950 /* LAN Rx Queue Context */
951 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
952 /* Field Width LSB */
953 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
954 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
955 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
956 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
957 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
958 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
959 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
960 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
961 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
962 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
963 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
964 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
965 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
966 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
967 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
968 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
969 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
970 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
971 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
972 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
978 * @hw: pointer to the hardware structure
979 * @rlan_ctx: pointer to the rxq context
980 * @rxq_index: the index of the Rx queue
982 * Converts rxq context from sparse to dense structure and then writes
983 * it to HW register space and enables the hardware to prefetch descriptors
984 * instead of only fetching them on demand
987 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
990 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
993 return ICE_ERR_BAD_PTR;
995 rlan_ctx->prefena = 1;
997 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
998 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1003 * @hw: pointer to the hardware structure
1004 * @rxq_index: the index of the Rx queue to clear
1006 * Clears rxq context in HW register space
1008 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)
1012 if (rxq_index > QRX_CTRL_MAX_INDEX)
1013 return ICE_ERR_PARAM;
1015 /* Clear each dword register separately */
1016 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)
1017 wr32(hw, QRX_CONTEXT(i, rxq_index), 0);
1022 /* LAN Tx Queue Context */
1023 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1024 /* Field Width LSB */
1025 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1026 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1027 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1028 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1029 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1030 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1031 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1032 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1033 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1034 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1035 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1036 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1037 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1038 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1039 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1040 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1041 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1042 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1043 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1044 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1045 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1046 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1047 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1048 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1049 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1050 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1051 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1052 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1057 * ice_copy_tx_cmpltnq_ctx_to_hw
1058 * @hw: pointer to the hardware structure
1059 * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context
1060 * @tx_cmpltnq_index: the index of the completion queue
1062 * Copies Tx completion queue context from dense structure to HW register space
1064 static enum ice_status
1065 ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,
1066 u32 tx_cmpltnq_index)
1070 if (!ice_tx_cmpltnq_ctx)
1071 return ICE_ERR_BAD_PTR;
1073 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1074 return ICE_ERR_PARAM;
1076 /* Copy each dword separately to HW */
1077 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {
1078 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),
1079 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1081 ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i,
1082 *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));
1088 /* LAN Tx Completion Queue Context */
1089 static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {
1090 /* Field Width LSB */
1091 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0),
1092 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64),
1093 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96),
1094 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97),
1095 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128),
1096 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131),
1097 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141),
1098 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160),
1099 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161),
1100 ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192),
1105 * ice_write_tx_cmpltnq_ctx
1106 * @hw: pointer to the hardware structure
1107 * @tx_cmpltnq_ctx: pointer to the completion queue context
1108 * @tx_cmpltnq_index: the index of the completion queue
1110 * Converts completion queue context from sparse to dense structure and then
1111 * writes it to HW register space
1114 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,
1115 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,
1116 u32 tx_cmpltnq_index)
1118 u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1120 ice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);
1121 return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);
1125 * ice_clear_tx_cmpltnq_ctx
1126 * @hw: pointer to the hardware structure
1127 * @tx_cmpltnq_index: the index of the completion queue to clear
1129 * Clears Tx completion queue context in HW register space
1132 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)
1136 if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)
1137 return ICE_ERR_PARAM;
1139 /* Clear each dword register separately */
1140 for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)
1141 wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);
1147 * ice_copy_tx_drbell_q_ctx_to_hw
1148 * @hw: pointer to the hardware structure
1149 * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context
1150 * @tx_drbell_q_index: the index of the doorbell queue
1152 * Copies doorbell queue context from dense structure to HW register space
1154 static enum ice_status
1155 ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,
1156 u32 tx_drbell_q_index)
1160 if (!ice_tx_drbell_q_ctx)
1161 return ICE_ERR_BAD_PTR;
1163 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1164 return ICE_ERR_PARAM;
1166 /* Copy each dword separately to HW */
1167 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {
1168 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),
1169 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1171 ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i,
1172 *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));
1178 /* LAN Tx Doorbell Queue Context info */
1179 static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {
1180 /* Field Width LSB */
1181 ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0),
1182 ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64),
1183 ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80),
1184 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84),
1185 ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94),
1186 ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96),
1187 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104),
1188 ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108),
1189 ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112),
1190 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128),
1191 ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144),
1196 * ice_write_tx_drbell_q_ctx
1197 * @hw: pointer to the hardware structure
1198 * @tx_drbell_q_ctx: pointer to the doorbell queue context
1199 * @tx_drbell_q_index: the index of the doorbell queue
1201 * Converts doorbell queue context from sparse to dense structure and then
1202 * writes it to HW register space
1205 ice_write_tx_drbell_q_ctx(struct ice_hw *hw,
1206 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,
1207 u32 tx_drbell_q_index)
1209 u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };
1211 ice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);
1212 return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);
1216 * ice_clear_tx_drbell_q_ctx
1217 * @hw: pointer to the hardware structure
1218 * @tx_drbell_q_index: the index of the doorbell queue to clear
1220 * Clears doorbell queue context in HW register space
1223 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)
1227 if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)
1228 return ICE_ERR_PARAM;
1230 /* Clear each dword register separately */
1231 for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)
1232 wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);
1237 /* FW Admin Queue command wrappers */
1240 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1241 * @hw: pointer to the HW struct
1242 * @desc: descriptor describing the command
1243 * @buf: buffer to use for indirect commands (NULL for direct commands)
1244 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1245 * @cd: pointer to command details structure
1247 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1250 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1251 u16 buf_size, struct ice_sq_cd *cd)
1253 if (hw->aq_send_cmd_fn) {
1254 enum ice_status status = ICE_ERR_NOT_READY;
1255 u16 retval = ICE_AQ_RC_OK;
1257 ice_acquire_lock(&hw->adminq.sq_lock);
1258 if (!hw->aq_send_cmd_fn(hw->aq_send_cmd_param, desc,
1260 retval = LE16_TO_CPU(desc->retval);
1261 /* strip off FW internal code */
1264 if (retval == ICE_AQ_RC_OK)
1265 status = ICE_SUCCESS;
1267 status = ICE_ERR_AQ_ERROR;
1270 hw->adminq.sq_last_status = (enum ice_aq_err)retval;
1271 ice_release_lock(&hw->adminq.sq_lock);
1275 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1280 * @hw: pointer to the HW struct
1281 * @cd: pointer to command details structure or NULL
1283 * Get the firmware version (0x0001) from the admin queue commands
1285 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1287 struct ice_aqc_get_ver *resp;
1288 struct ice_aq_desc desc;
1289 enum ice_status status;
1291 resp = &desc.params.get_ver;
1293 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1295 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1298 hw->fw_branch = resp->fw_branch;
1299 hw->fw_maj_ver = resp->fw_major;
1300 hw->fw_min_ver = resp->fw_minor;
1301 hw->fw_patch = resp->fw_patch;
1302 hw->fw_build = LE32_TO_CPU(resp->fw_build);
1303 hw->api_branch = resp->api_branch;
1304 hw->api_maj_ver = resp->api_major;
1305 hw->api_min_ver = resp->api_minor;
1306 hw->api_patch = resp->api_patch;
1313 * ice_aq_send_driver_ver
1314 * @hw: pointer to the HW struct
1315 * @dv: driver's major, minor version
1316 * @cd: pointer to command details structure or NULL
1318 * Send the driver version (0x0002) to the firmware
1321 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1322 struct ice_sq_cd *cd)
1324 struct ice_aqc_driver_ver *cmd;
1325 struct ice_aq_desc desc;
1328 cmd = &desc.params.driver_ver;
1331 return ICE_ERR_PARAM;
1333 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1335 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1336 cmd->major_ver = dv->major_ver;
1337 cmd->minor_ver = dv->minor_ver;
1338 cmd->build_ver = dv->build_ver;
1339 cmd->subbuild_ver = dv->subbuild_ver;
1342 while (len < sizeof(dv->driver_string) &&
1343 IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])
1346 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1351 * @hw: pointer to the HW struct
1352 * @unloading: is the driver unloading itself
1354 * Tell the Firmware that we're shutting down the AdminQ and whether
1355 * or not the driver is unloading as well (0x0003).
1357 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1359 struct ice_aqc_q_shutdown *cmd;
1360 struct ice_aq_desc desc;
1362 cmd = &desc.params.q_shutdown;
1364 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1367 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1369 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1374 * @hw: pointer to the HW struct
1376 * @access: access type
1377 * @sdp_number: resource number
1378 * @timeout: the maximum time in ms that the driver may hold the resource
1379 * @cd: pointer to command details structure or NULL
1381 * Requests common resource using the admin queue commands (0x0008).
1382 * When attempting to acquire the Global Config Lock, the driver can
1383 * learn of three states:
1384 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1385 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1386 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1387 * successfully downloaded the package; the driver does
1388 * not have to download the package and can continue
1391 * Note that if the caller is in an acquire lock, perform action, release lock
1392 * phase of operation, it is possible that the FW may detect a timeout and issue
1393 * a CORER. In this case, the driver will receive a CORER interrupt and will
1394 * have to determine its cause. The calling thread that is handling this flow
1395 * will likely get an error propagated back to it indicating the Download
1396 * Package, Update Package or the Release Resource AQ commands timed out.
1398 static enum ice_status
1399 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1400 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1401 struct ice_sq_cd *cd)
1403 struct ice_aqc_req_res *cmd_resp;
1404 struct ice_aq_desc desc;
1405 enum ice_status status;
1407 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1409 cmd_resp = &desc.params.res_owner;
1411 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1413 cmd_resp->res_id = CPU_TO_LE16(res);
1414 cmd_resp->access_type = CPU_TO_LE16(access);
1415 cmd_resp->res_number = CPU_TO_LE32(sdp_number);
1416 cmd_resp->timeout = CPU_TO_LE32(*timeout);
1419 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1421 /* The completion specifies the maximum time in ms that the driver
1422 * may hold the resource in the Timeout field.
1425 /* Global config lock response utilizes an additional status field.
1427 * If the Global config lock resource is held by some other driver, the
1428 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1429 * and the timeout field indicates the maximum time the current owner
1430 * of the resource has to free it.
1432 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1433 if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1434 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1436 } else if (LE16_TO_CPU(cmd_resp->status) ==
1437 ICE_AQ_RES_GLBL_IN_PROG) {
1438 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1439 return ICE_ERR_AQ_ERROR;
1440 } else if (LE16_TO_CPU(cmd_resp->status) ==
1441 ICE_AQ_RES_GLBL_DONE) {
1442 return ICE_ERR_AQ_NO_WORK;
1445 /* invalid FW response, force a timeout immediately */
1447 return ICE_ERR_AQ_ERROR;
1450 /* If the resource is held by some other driver, the command completes
1451 * with a busy return value and the timeout field indicates the maximum
1452 * time the current owner of the resource has to free it.
1454 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1455 *timeout = LE32_TO_CPU(cmd_resp->timeout);
1461 * ice_aq_release_res
1462 * @hw: pointer to the HW struct
1464 * @sdp_number: resource number
1465 * @cd: pointer to command details structure or NULL
1467 * release common resource using the admin queue commands (0x0009)
1469 static enum ice_status
1470 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1471 struct ice_sq_cd *cd)
1473 struct ice_aqc_req_res *cmd;
1474 struct ice_aq_desc desc;
1476 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1478 cmd = &desc.params.res_owner;
1480 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1482 cmd->res_id = CPU_TO_LE16(res);
1483 cmd->res_number = CPU_TO_LE32(sdp_number);
1485 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1490 * @hw: pointer to the HW structure
1492 * @access: access type (read or write)
1493 * @timeout: timeout in milliseconds
1495 * This function will attempt to acquire the ownership of a resource.
1498 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1499 enum ice_aq_res_access_type access, u32 timeout)
1501 #define ICE_RES_POLLING_DELAY_MS 10
1502 u32 delay = ICE_RES_POLLING_DELAY_MS;
1503 u32 time_left = timeout;
1504 enum ice_status status;
1506 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1508 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1510 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1511 * previously acquired the resource and performed any necessary updates;
1512 * in this case the caller does not obtain the resource and has no
1513 * further work to do.
1515 if (status == ICE_ERR_AQ_NO_WORK)
1516 goto ice_acquire_res_exit;
1519 ice_debug(hw, ICE_DBG_RES,
1520 "resource %d acquire type %d failed.\n", res, access);
1522 /* If necessary, poll until the current lock owner timeouts */
1523 timeout = time_left;
1524 while (status && timeout && time_left) {
1525 ice_msec_delay(delay, true);
1526 timeout = (timeout > delay) ? timeout - delay : 0;
1527 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1529 if (status == ICE_ERR_AQ_NO_WORK)
1530 /* lock free, but no work to do */
1537 if (status && status != ICE_ERR_AQ_NO_WORK)
1538 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1540 ice_acquire_res_exit:
1541 if (status == ICE_ERR_AQ_NO_WORK) {
1542 if (access == ICE_RES_WRITE)
1543 ice_debug(hw, ICE_DBG_RES,
1544 "resource indicates no work to do.\n");
1546 ice_debug(hw, ICE_DBG_RES,
1547 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1554 * @hw: pointer to the HW structure
1557 * This function will release a resource using the proper Admin Command.
1559 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1561 enum ice_status status;
1562 u32 total_delay = 0;
1564 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1566 status = ice_aq_release_res(hw, res, 0, NULL);
1568 /* there are some rare cases when trying to release the resource
1569 * results in an admin queue timeout, so handle them correctly
1571 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1572 (total_delay < hw->adminq.sq_cmd_timeout)) {
1573 ice_msec_delay(1, true);
1574 status = ice_aq_release_res(hw, res, 0, NULL);
1580 * ice_aq_alloc_free_res - command to allocate/free resources
1581 * @hw: pointer to the HW struct
1582 * @num_entries: number of resource entries in buffer
1583 * @buf: Indirect buffer to hold data parameters and response
1584 * @buf_size: size of buffer for indirect commands
1585 * @opc: pass in the command opcode
1586 * @cd: pointer to command details structure or NULL
1588 * Helper function to allocate/free resources using the admin queue commands
1591 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1592 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1593 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1595 struct ice_aqc_alloc_free_res_cmd *cmd;
1596 struct ice_aq_desc desc;
1598 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
1600 cmd = &desc.params.sw_res_ctrl;
1603 return ICE_ERR_PARAM;
1605 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1606 return ICE_ERR_PARAM;
1608 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1610 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
1612 cmd->num_entries = CPU_TO_LE16(num_entries);
1614 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1618 * ice_alloc_hw_res - allocate resource
1619 * @hw: pointer to the HW struct
1620 * @type: type of resource
1621 * @num: number of resources to allocate
1622 * @btm: allocate from bottom
1623 * @res: pointer to array that will receive the resources
1626 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1628 struct ice_aqc_alloc_free_res_elem *buf;
1629 enum ice_status status;
1632 buf_len = ice_struct_size(buf, elem, num - 1);
1633 buf = (struct ice_aqc_alloc_free_res_elem *)
1634 ice_malloc(hw, buf_len);
1636 return ICE_ERR_NO_MEMORY;
1638 /* Prepare buffer to allocate resource. */
1639 buf->num_elems = CPU_TO_LE16(num);
1640 buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1641 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1643 buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1645 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1646 ice_aqc_opc_alloc_res, NULL);
1648 goto ice_alloc_res_exit;
1650 ice_memcpy(res, buf->elem, sizeof(buf->elem) * num,
1651 ICE_NONDMA_TO_NONDMA);
1659 * ice_free_hw_res - free allocated HW resource
1660 * @hw: pointer to the HW struct
1661 * @type: type of resource to free
1662 * @num: number of resources
1663 * @res: pointer to array that contains the resources to free
1666 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1668 struct ice_aqc_alloc_free_res_elem *buf;
1669 enum ice_status status;
1672 buf_len = ice_struct_size(buf, elem, num - 1);
1673 buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len);
1675 return ICE_ERR_NO_MEMORY;
1677 /* Prepare buffer to free resource. */
1678 buf->num_elems = CPU_TO_LE16(num);
1679 buf->res_type = CPU_TO_LE16(type);
1680 ice_memcpy(buf->elem, res, sizeof(buf->elem) * num,
1681 ICE_NONDMA_TO_NONDMA);
1683 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1684 ice_aqc_opc_free_res, NULL);
1686 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1693 * ice_get_num_per_func - determine number of resources per PF
1694 * @hw: pointer to the HW structure
1695 * @max: value to be evenly split between each PF
1697 * Determine the number of valid functions by going through the bitmap returned
1698 * from parsing capabilities and use this to calculate the number of resources
1699 * per PF based on the max value passed in.
1701 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1705 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1706 funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &
1707 ICE_CAPS_VALID_FUNCS_M);
1716 * ice_parse_caps - parse function/device capabilities
1717 * @hw: pointer to the HW struct
1718 * @buf: pointer to a buffer containing function/device capability records
1719 * @cap_count: number of capability records in the list
1720 * @opc: type of capabilities list to parse
1722 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1725 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1726 enum ice_adminq_opc opc)
1728 struct ice_aqc_list_caps_elem *cap_resp;
1729 struct ice_hw_func_caps *func_p = NULL;
1730 struct ice_hw_dev_caps *dev_p = NULL;
1731 struct ice_hw_common_caps *caps;
1738 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1740 if (opc == ice_aqc_opc_list_dev_caps) {
1741 dev_p = &hw->dev_caps;
1742 caps = &dev_p->common_cap;
1744 } else if (opc == ice_aqc_opc_list_func_caps) {
1745 func_p = &hw->func_caps;
1746 caps = &func_p->common_cap;
1747 prefix = "func cap";
1749 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1753 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1754 u32 logical_id = LE32_TO_CPU(cap_resp->logical_id);
1755 u32 phys_id = LE32_TO_CPU(cap_resp->phys_id);
1756 u32 number = LE32_TO_CPU(cap_resp->number);
1757 u16 cap = LE16_TO_CPU(cap_resp->cap);
1760 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1761 caps->valid_functions = number;
1762 ice_debug(hw, ICE_DBG_INIT,
1763 "%s: valid_functions (bitmap) = %d\n", prefix,
1764 caps->valid_functions);
1766 /* store func count for resource management purposes */
1768 dev_p->num_funcs = ice_hweight32(number);
1770 case ICE_AQC_CAPS_VSI:
1772 dev_p->num_vsi_allocd_to_host = number;
1773 ice_debug(hw, ICE_DBG_INIT,
1774 "%s: num_vsi_allocd_to_host = %d\n",
1776 dev_p->num_vsi_allocd_to_host);
1777 } else if (func_p) {
1778 func_p->guar_num_vsi =
1779 ice_get_num_per_func(hw, ICE_MAX_VSI);
1780 ice_debug(hw, ICE_DBG_INIT,
1781 "%s: guar_num_vsi (fw) = %d\n",
1783 ice_debug(hw, ICE_DBG_INIT,
1784 "%s: guar_num_vsi = %d\n",
1785 prefix, func_p->guar_num_vsi);
1788 case ICE_AQC_CAPS_DCB:
1789 caps->dcb = (number == 1);
1790 caps->active_tc_bitmap = logical_id;
1791 caps->maxtc = phys_id;
1792 ice_debug(hw, ICE_DBG_INIT,
1793 "%s: dcb = %d\n", prefix, caps->dcb);
1794 ice_debug(hw, ICE_DBG_INIT,
1795 "%s: active_tc_bitmap = %d\n", prefix,
1796 caps->active_tc_bitmap);
1797 ice_debug(hw, ICE_DBG_INIT,
1798 "%s: maxtc = %d\n", prefix, caps->maxtc);
1800 case ICE_AQC_CAPS_RSS:
1801 caps->rss_table_size = number;
1802 caps->rss_table_entry_width = logical_id;
1803 ice_debug(hw, ICE_DBG_INIT,
1804 "%s: rss_table_size = %d\n", prefix,
1805 caps->rss_table_size);
1806 ice_debug(hw, ICE_DBG_INIT,
1807 "%s: rss_table_entry_width = %d\n", prefix,
1808 caps->rss_table_entry_width);
1810 case ICE_AQC_CAPS_RXQS:
1811 caps->num_rxq = number;
1812 caps->rxq_first_id = phys_id;
1813 ice_debug(hw, ICE_DBG_INIT,
1814 "%s: num_rxq = %d\n", prefix,
1816 ice_debug(hw, ICE_DBG_INIT,
1817 "%s: rxq_first_id = %d\n", prefix,
1818 caps->rxq_first_id);
1820 case ICE_AQC_CAPS_TXQS:
1821 caps->num_txq = number;
1822 caps->txq_first_id = phys_id;
1823 ice_debug(hw, ICE_DBG_INIT,
1824 "%s: num_txq = %d\n", prefix,
1826 ice_debug(hw, ICE_DBG_INIT,
1827 "%s: txq_first_id = %d\n", prefix,
1828 caps->txq_first_id);
1830 case ICE_AQC_CAPS_MSIX:
1831 caps->num_msix_vectors = number;
1832 caps->msix_vector_first_id = phys_id;
1833 ice_debug(hw, ICE_DBG_INIT,
1834 "%s: num_msix_vectors = %d\n", prefix,
1835 caps->num_msix_vectors);
1836 ice_debug(hw, ICE_DBG_INIT,
1837 "%s: msix_vector_first_id = %d\n", prefix,
1838 caps->msix_vector_first_id);
1840 case ICE_AQC_CAPS_FD:
1845 dev_p->num_flow_director_fltr = number;
1846 ice_debug(hw, ICE_DBG_INIT,
1847 "%s: num_flow_director_fltr = %d\n",
1849 dev_p->num_flow_director_fltr);
1852 if (hw->dcf_enabled)
1854 reg_val = rd32(hw, GLQF_FD_SIZE);
1855 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
1856 GLQF_FD_SIZE_FD_GSIZE_S;
1857 func_p->fd_fltr_guar =
1858 ice_get_num_per_func(hw, val);
1859 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
1860 GLQF_FD_SIZE_FD_BSIZE_S;
1861 func_p->fd_fltr_best_effort = val;
1862 ice_debug(hw, ICE_DBG_INIT,
1863 "%s: fd_fltr_guar = %d\n",
1864 prefix, func_p->fd_fltr_guar);
1865 ice_debug(hw, ICE_DBG_INIT,
1866 "%s: fd_fltr_best_effort = %d\n",
1867 prefix, func_p->fd_fltr_best_effort);
1871 case ICE_AQC_CAPS_MAX_MTU:
1872 caps->max_mtu = number;
1873 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1874 prefix, caps->max_mtu);
1877 ice_debug(hw, ICE_DBG_INIT,
1878 "%s: unknown capability[%d]: 0x%x\n", prefix,
1884 /* Re-calculate capabilities that are dependent on the number of
1885 * physical ports; i.e. some features are not supported or function
1886 * differently on devices with more than 4 ports.
1888 if (hw->dev_caps.num_funcs > 4) {
1889 /* Max 4 TCs per port */
1891 ice_debug(hw, ICE_DBG_INIT,
1892 "%s: maxtc = %d (based on #ports)\n", prefix,
1898 * ice_aq_discover_caps - query function/device capabilities
1899 * @hw: pointer to the HW struct
1900 * @buf: a virtual buffer to hold the capabilities
1901 * @buf_size: Size of the virtual buffer
1902 * @cap_count: cap count needed if AQ err==ENOMEM
1903 * @opc: capabilities type to discover - pass in the command opcode
1904 * @cd: pointer to command details structure or NULL
1906 * Get the function(0x000a)/device(0x000b) capabilities description from
1909 static enum ice_status
1910 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
1911 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1913 struct ice_aqc_list_caps *cmd;
1914 struct ice_aq_desc desc;
1915 enum ice_status status;
1917 cmd = &desc.params.get_cap;
1919 if (opc != ice_aqc_opc_list_func_caps &&
1920 opc != ice_aqc_opc_list_dev_caps)
1921 return ICE_ERR_PARAM;
1923 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1925 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1927 ice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);
1928 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
1929 *cap_count = LE32_TO_CPU(cmd->count);
1934 * ice_discover_caps - get info about the HW
1935 * @hw: pointer to the hardware structure
1936 * @opc: capabilities type to discover - pass in the command opcode
1938 static enum ice_status
1939 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
1941 enum ice_status status;
1946 /* The driver doesn't know how many capabilities the device will return
1947 * so the buffer size required isn't known ahead of time. The driver
1948 * starts with cbuf_len and if this turns out to be insufficient, the
1949 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
1950 * The driver then allocates the buffer based on the count and retries
1951 * the operation. So it follows that the retry count is 2.
1953 #define ICE_GET_CAP_BUF_COUNT 40
1954 #define ICE_GET_CAP_RETRY_COUNT 2
1956 cap_count = ICE_GET_CAP_BUF_COUNT;
1957 retries = ICE_GET_CAP_RETRY_COUNT;
1962 cbuf_len = (u16)(cap_count *
1963 sizeof(struct ice_aqc_list_caps_elem));
1964 cbuf = ice_malloc(hw, cbuf_len);
1966 return ICE_ERR_NO_MEMORY;
1968 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
1972 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
1975 /* If ENOMEM is returned, try again with bigger buffer */
1976 } while (--retries);
1982 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
1983 * @hw: pointer to the hardware structure
1985 void ice_set_safe_mode_caps(struct ice_hw *hw)
1987 struct ice_hw_func_caps *func_caps = &hw->func_caps;
1988 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
1989 u32 valid_func, rxq_first_id, txq_first_id;
1990 u32 msix_vector_first_id, max_mtu;
1993 /* cache some func_caps values that should be restored after memset */
1994 valid_func = func_caps->common_cap.valid_functions;
1995 txq_first_id = func_caps->common_cap.txq_first_id;
1996 rxq_first_id = func_caps->common_cap.rxq_first_id;
1997 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
1998 max_mtu = func_caps->common_cap.max_mtu;
2000 /* unset func capabilities */
2001 memset(func_caps, 0, sizeof(*func_caps));
2003 /* restore cached values */
2004 func_caps->common_cap.valid_functions = valid_func;
2005 func_caps->common_cap.txq_first_id = txq_first_id;
2006 func_caps->common_cap.rxq_first_id = rxq_first_id;
2007 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2008 func_caps->common_cap.max_mtu = max_mtu;
2010 /* one Tx and one Rx queue in safe mode */
2011 func_caps->common_cap.num_rxq = 1;
2012 func_caps->common_cap.num_txq = 1;
2014 /* two MSIX vectors, one for traffic and one for misc causes */
2015 func_caps->common_cap.num_msix_vectors = 2;
2016 func_caps->guar_num_vsi = 1;
2018 /* cache some dev_caps values that should be restored after memset */
2019 valid_func = dev_caps->common_cap.valid_functions;
2020 txq_first_id = dev_caps->common_cap.txq_first_id;
2021 rxq_first_id = dev_caps->common_cap.rxq_first_id;
2022 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
2023 max_mtu = dev_caps->common_cap.max_mtu;
2024 num_funcs = dev_caps->num_funcs;
2026 /* unset dev capabilities */
2027 memset(dev_caps, 0, sizeof(*dev_caps));
2029 /* restore cached values */
2030 dev_caps->common_cap.valid_functions = valid_func;
2031 dev_caps->common_cap.txq_first_id = txq_first_id;
2032 dev_caps->common_cap.rxq_first_id = rxq_first_id;
2033 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
2034 dev_caps->common_cap.max_mtu = max_mtu;
2035 dev_caps->num_funcs = num_funcs;
2037 /* one Tx and one Rx queue per function in safe mode */
2038 dev_caps->common_cap.num_rxq = num_funcs;
2039 dev_caps->common_cap.num_txq = num_funcs;
2041 /* two MSIX vectors per function */
2042 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2046 * ice_get_caps - get info about the HW
2047 * @hw: pointer to the hardware structure
2049 enum ice_status ice_get_caps(struct ice_hw *hw)
2051 enum ice_status status;
2053 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
2055 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
2061 * ice_aq_manage_mac_write - manage MAC address write command
2062 * @hw: pointer to the HW struct
2063 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2064 * @flags: flags to control write behavior
2065 * @cd: pointer to command details structure or NULL
2067 * This function is used to write MAC address to the NVM (0x0108).
2070 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2071 struct ice_sq_cd *cd)
2073 struct ice_aqc_manage_mac_write *cmd;
2074 struct ice_aq_desc desc;
2076 cmd = &desc.params.mac_write;
2077 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2080 ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_DMA);
2082 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2086 * ice_aq_clear_pxe_mode
2087 * @hw: pointer to the HW struct
2089 * Tell the firmware that the driver is taking over from PXE (0x0110).
2091 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2093 struct ice_aq_desc desc;
2095 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2096 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2098 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2102 * ice_clear_pxe_mode - clear pxe operations mode
2103 * @hw: pointer to the HW struct
2105 * Make sure all PXE mode settings are cleared, including things
2106 * like descriptor fetch/write-back mode.
2108 void ice_clear_pxe_mode(struct ice_hw *hw)
2110 if (ice_check_sq_alive(hw, &hw->adminq))
2111 ice_aq_clear_pxe_mode(hw);
2115 * ice_get_link_speed_based_on_phy_type - returns link speed
2116 * @phy_type_low: lower part of phy_type
2117 * @phy_type_high: higher part of phy_type
2119 * This helper function will convert an entry in PHY type structure
2120 * [phy_type_low, phy_type_high] to its corresponding link speed.
2121 * Note: In the structure of [phy_type_low, phy_type_high], there should
2122 * be one bit set, as this function will convert one PHY type to its
2124 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2125 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2128 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2130 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2131 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2133 switch (phy_type_low) {
2134 case ICE_PHY_TYPE_LOW_100BASE_TX:
2135 case ICE_PHY_TYPE_LOW_100M_SGMII:
2136 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2138 case ICE_PHY_TYPE_LOW_1000BASE_T:
2139 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2140 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2141 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2142 case ICE_PHY_TYPE_LOW_1G_SGMII:
2143 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2145 case ICE_PHY_TYPE_LOW_2500BASE_T:
2146 case ICE_PHY_TYPE_LOW_2500BASE_X:
2147 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2148 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2150 case ICE_PHY_TYPE_LOW_5GBASE_T:
2151 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2152 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2154 case ICE_PHY_TYPE_LOW_10GBASE_T:
2155 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2156 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2157 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2158 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2159 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2160 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2161 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2163 case ICE_PHY_TYPE_LOW_25GBASE_T:
2164 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2165 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2166 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2167 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2168 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2169 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2170 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2171 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2172 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2173 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2174 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2176 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2177 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2178 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2179 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2180 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2181 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2182 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2184 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2185 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2186 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2187 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2188 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2189 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2190 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2191 case ICE_PHY_TYPE_LOW_50G_AUI2:
2192 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2193 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2194 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2195 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2196 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2197 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2198 case ICE_PHY_TYPE_LOW_50G_AUI1:
2199 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2201 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2202 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2203 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2204 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2205 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2206 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2207 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2208 case ICE_PHY_TYPE_LOW_100G_AUI4:
2209 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2210 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2211 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2212 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2213 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2214 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2217 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2221 switch (phy_type_high) {
2222 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2223 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2224 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2225 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2226 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2227 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2230 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2234 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2235 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2236 return ICE_AQ_LINK_SPEED_UNKNOWN;
2237 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2238 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2239 return ICE_AQ_LINK_SPEED_UNKNOWN;
2240 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2241 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2242 return speed_phy_type_low;
2244 return speed_phy_type_high;
2248 * ice_update_phy_type
2249 * @phy_type_low: pointer to the lower part of phy_type
2250 * @phy_type_high: pointer to the higher part of phy_type
2251 * @link_speeds_bitmap: targeted link speeds bitmap
2253 * Note: For the link_speeds_bitmap structure, you can check it at
2254 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2255 * link_speeds_bitmap include multiple speeds.
2257 * Each entry in this [phy_type_low, phy_type_high] structure will
2258 * present a certain link speed. This helper function will turn on bits
2259 * in [phy_type_low, phy_type_high] structure based on the value of
2260 * link_speeds_bitmap input parameter.
2263 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2264 u16 link_speeds_bitmap)
2271 /* We first check with low part of phy_type */
2272 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2273 pt_low = BIT_ULL(index);
2274 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2276 if (link_speeds_bitmap & speed)
2277 *phy_type_low |= BIT_ULL(index);
2280 /* We then check with high part of phy_type */
2281 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2282 pt_high = BIT_ULL(index);
2283 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2285 if (link_speeds_bitmap & speed)
2286 *phy_type_high |= BIT_ULL(index);
2291 * ice_aq_set_phy_cfg
2292 * @hw: pointer to the HW struct
2293 * @pi: port info structure of the interested logical port
2294 * @cfg: structure with PHY configuration data to be set
2295 * @cd: pointer to command details structure or NULL
2297 * Set the various PHY configuration parameters supported on the Port.
2298 * One or more of the Set PHY config parameters may be ignored in an MFP
2299 * mode as the PF may not have the privilege to set some of the PHY Config
2300 * parameters. This status will be indicated by the command response (0x0601).
2303 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2304 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2306 struct ice_aq_desc desc;
2307 enum ice_status status;
2310 return ICE_ERR_PARAM;
2312 /* Ensure that only valid bits of cfg->caps can be turned on. */
2313 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2314 ice_debug(hw, ICE_DBG_PHY,
2315 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2318 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2321 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2322 desc.params.set_phy.lport_num = pi->lport;
2323 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2325 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2326 (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));
2327 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2328 (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));
2329 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2330 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl_an = 0x%x\n",
2331 cfg->low_power_ctrl_an);
2332 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2333 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2334 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2336 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2339 pi->phy.curr_user_phy_cfg = *cfg;
2345 * ice_update_link_info - update status of the HW network link
2346 * @pi: port info structure of the interested logical port
2348 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2350 struct ice_link_status *li;
2351 enum ice_status status;
2354 return ICE_ERR_PARAM;
2356 li = &pi->phy.link_info;
2358 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2362 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2363 struct ice_aqc_get_phy_caps_data *pcaps;
2367 pcaps = (struct ice_aqc_get_phy_caps_data *)
2368 ice_malloc(hw, sizeof(*pcaps));
2370 return ICE_ERR_NO_MEMORY;
2372 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2374 if (status == ICE_SUCCESS)
2375 ice_memcpy(li->module_type, &pcaps->module_type,
2376 sizeof(li->module_type),
2377 ICE_NONDMA_TO_NONDMA);
2379 ice_free(hw, pcaps);
2386 * ice_cache_phy_user_req
2387 * @pi: port information structure
2388 * @cache_data: PHY logging data
2389 * @cache_mode: PHY logging mode
2391 * Log the user request on (FC, FEC, SPEED) for later user.
2394 ice_cache_phy_user_req(struct ice_port_info *pi,
2395 struct ice_phy_cache_mode_data cache_data,
2396 enum ice_phy_cache_mode cache_mode)
2401 switch (cache_mode) {
2403 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2405 case ICE_SPEED_MODE:
2406 pi->phy.curr_user_speed_req =
2407 cache_data.data.curr_user_speed_req;
2410 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2418 * ice_caps_to_fc_mode
2419 * @caps: PHY capabilities
2421 * Convert PHY FC capabilities to ice FC mode
2423 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2425 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2426 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2429 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2430 return ICE_FC_TX_PAUSE;
2432 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2433 return ICE_FC_RX_PAUSE;
2439 * ice_caps_to_fec_mode
2440 * @caps: PHY capabilities
2441 * @fec_options: Link FEC options
2443 * Convert PHY FEC capabilities to ice FEC mode
2445 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2447 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2448 return ICE_FEC_AUTO;
2450 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2451 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2452 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2453 ICE_AQC_PHY_FEC_25G_KR_REQ))
2454 return ICE_FEC_BASER;
2456 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2457 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2458 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2461 return ICE_FEC_NONE;
2466 * @pi: port information structure
2467 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2468 * @ena_auto_link_update: enable automatic link update
2470 * Set the requested flow control mode.
2473 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2475 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2476 struct ice_phy_cache_mode_data cache_data;
2477 struct ice_aqc_get_phy_caps_data *pcaps;
2478 enum ice_status status;
2479 u8 pause_mask = 0x0;
2482 if (!pi || !aq_failures)
2483 return ICE_ERR_PARAM;
2486 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2488 /* Cache user FC request */
2489 cache_data.data.curr_user_fc_req = pi->fc.req_mode;
2490 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2492 pcaps = (struct ice_aqc_get_phy_caps_data *)
2493 ice_malloc(hw, sizeof(*pcaps));
2495 return ICE_ERR_NO_MEMORY;
2497 switch (pi->fc.req_mode) {
2499 /* Query the value of FC that both the NIC and attached media
2502 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2505 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2509 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2510 pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2513 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2514 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2516 case ICE_FC_RX_PAUSE:
2517 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2519 case ICE_FC_TX_PAUSE:
2520 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2526 /* Get the current PHY config */
2527 ice_memset(pcaps, 0, sizeof(*pcaps), ICE_NONDMA_MEM);
2528 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2531 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2535 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
2537 /* clear the old pause settings */
2538 cfg.caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2539 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2541 /* set the new capabilities */
2542 cfg.caps |= pause_mask;
2544 /* If the capabilities have changed, then set the new config */
2545 if (cfg.caps != pcaps->caps) {
2546 int retry_count, retry_max = 10;
2548 /* Auto restart link so settings take effect */
2549 if (ena_auto_link_update)
2550 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2552 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2554 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2558 /* Update the link info
2559 * It sometimes takes a really long time for link to
2560 * come back from the atomic reset. Thus, we wait a
2563 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2564 status = ice_update_link_info(pi);
2566 if (status == ICE_SUCCESS)
2569 ice_msec_delay(100, true);
2573 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2577 ice_free(hw, pcaps);
2582 * ice_phy_caps_equals_cfg
2583 * @phy_caps: PHY capabilities
2584 * @phy_cfg: PHY configuration
2586 * Helper function to determine if PHY capabilities matches PHY
2590 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2591 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2593 u8 caps_mask, cfg_mask;
2595 if (!phy_caps || !phy_cfg)
2598 /* These bits are not common between capabilities and configuration.
2599 * Do not use them to determine equality.
2601 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2602 ICE_AQC_PHY_EN_MOD_QUAL);
2603 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2605 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2606 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2607 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2608 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
2609 phy_caps->eee_cap != phy_cfg->eee_cap ||
2610 phy_caps->eeer_value != phy_cfg->eeer_value ||
2611 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2618 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2619 * @pi: port information structure
2620 * @caps: PHY ability structure to copy date from
2621 * @cfg: PHY configuration structure to copy data to
2623 * Helper function to copy AQC PHY get ability data to PHY set configuration
2627 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
2628 struct ice_aqc_get_phy_caps_data *caps,
2629 struct ice_aqc_set_phy_cfg_data *cfg)
2631 if (!pi || !caps || !cfg)
2634 ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM);
2635 cfg->phy_type_low = caps->phy_type_low;
2636 cfg->phy_type_high = caps->phy_type_high;
2637 cfg->caps = caps->caps;
2638 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
2639 cfg->eee_cap = caps->eee_cap;
2640 cfg->eeer_value = caps->eeer_value;
2641 cfg->link_fec_opt = caps->link_fec_options;
2642 cfg->module_compliance_enforcement =
2643 caps->module_compliance_enforcement;
2645 if (ice_fw_supports_link_override(pi->hw)) {
2646 struct ice_link_default_override_tlv tlv;
2648 if (ice_get_link_default_override(&tlv, pi))
2651 if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE)
2652 cfg->module_compliance_enforcement |=
2653 ICE_LINK_OVERRIDE_STRICT_MODE;
2658 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2659 * @pi: port information structure
2660 * @cfg: PHY configuration data to set FEC mode
2661 * @fec: FEC mode to configure
2664 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2665 enum ice_fec_mode fec)
2667 struct ice_aqc_get_phy_caps_data *pcaps;
2668 enum ice_status status = ICE_SUCCESS;
2672 return ICE_ERR_BAD_PTR;
2676 pcaps = (struct ice_aqc_get_phy_caps_data *)
2677 ice_malloc(hw, sizeof(*pcaps));
2679 return ICE_ERR_NO_MEMORY;
2681 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps,
2688 /* Clear RS bits, and AND BASE-R ability
2689 * bits and OR request bits.
2691 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2692 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2693 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2694 ICE_AQC_PHY_FEC_25G_KR_REQ;
2697 /* Clear BASE-R bits, and AND RS ability
2698 * bits and OR request bits.
2700 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2701 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2702 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2705 /* Clear all FEC option bits. */
2706 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2709 /* AND auto FEC bit, and all caps bits. */
2710 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2711 cfg->link_fec_opt |= pcaps->link_fec_options;
2714 status = ICE_ERR_PARAM;
2718 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) {
2719 struct ice_link_default_override_tlv tlv;
2721 if (ice_get_link_default_override(&tlv, pi))
2724 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
2725 (tlv.options & ICE_LINK_OVERRIDE_EN))
2726 cfg->link_fec_opt = tlv.fec_options;
2730 ice_free(hw, pcaps);
2736 * ice_get_link_status - get status of the HW network link
2737 * @pi: port information structure
2738 * @link_up: pointer to bool (true/false = linkup/linkdown)
2740 * Variable link_up is true if link is up, false if link is down.
2741 * The variable link_up is invalid if status is non zero. As a
2742 * result of this call, link status reporting becomes enabled
2744 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2746 struct ice_phy_info *phy_info;
2747 enum ice_status status = ICE_SUCCESS;
2749 if (!pi || !link_up)
2750 return ICE_ERR_PARAM;
2752 phy_info = &pi->phy;
2754 if (phy_info->get_link_info) {
2755 status = ice_update_link_info(pi);
2758 ice_debug(pi->hw, ICE_DBG_LINK,
2759 "get link status error, status = %d\n",
2763 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2769 * ice_aq_set_link_restart_an
2770 * @pi: pointer to the port information structure
2771 * @ena_link: if true: enable link, if false: disable link
2772 * @cd: pointer to command details structure or NULL
2774 * Sets up the link and restarts the Auto-Negotiation over the link.
2777 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2778 struct ice_sq_cd *cd)
2780 struct ice_aqc_restart_an *cmd;
2781 struct ice_aq_desc desc;
2783 cmd = &desc.params.restart_an;
2785 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2787 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2788 cmd->lport_num = pi->lport;
2790 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2792 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2794 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2798 * ice_aq_set_event_mask
2799 * @hw: pointer to the HW struct
2800 * @port_num: port number of the physical function
2801 * @mask: event mask to be set
2802 * @cd: pointer to command details structure or NULL
2804 * Set event mask (0x0613)
2807 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2808 struct ice_sq_cd *cd)
2810 struct ice_aqc_set_event_mask *cmd;
2811 struct ice_aq_desc desc;
2813 cmd = &desc.params.set_event_mask;
2815 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2817 cmd->lport_num = port_num;
2819 cmd->event_mask = CPU_TO_LE16(mask);
2820 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2824 * ice_aq_set_mac_loopback
2825 * @hw: pointer to the HW struct
2826 * @ena_lpbk: Enable or Disable loopback
2827 * @cd: pointer to command details structure or NULL
2829 * Enable/disable loopback on a given port
2832 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2834 struct ice_aqc_set_mac_lb *cmd;
2835 struct ice_aq_desc desc;
2837 cmd = &desc.params.set_mac_lb;
2839 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2841 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2843 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2847 * ice_aq_set_port_id_led
2848 * @pi: pointer to the port information
2849 * @is_orig_mode: is this LED set to original mode (by the net-list)
2850 * @cd: pointer to command details structure or NULL
2852 * Set LED value for the given port (0x06e9)
2855 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2856 struct ice_sq_cd *cd)
2858 struct ice_aqc_set_port_id_led *cmd;
2859 struct ice_hw *hw = pi->hw;
2860 struct ice_aq_desc desc;
2862 cmd = &desc.params.set_port_id_led;
2864 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2867 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2869 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2871 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2876 * @hw: pointer to the HW struct
2877 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
2878 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
2879 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
2881 * @set_page: set or ignore the page
2882 * @data: pointer to data buffer to be read/written to the I2C device.
2883 * @length: 1-16 for read, 1 for write.
2884 * @write: 0 read, 1 for write.
2885 * @cd: pointer to command details structure or NULL
2887 * Read/Write SFF EEPROM (0x06EE)
2890 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
2891 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
2892 bool write, struct ice_sq_cd *cd)
2894 struct ice_aqc_sff_eeprom *cmd;
2895 struct ice_aq_desc desc;
2896 enum ice_status status;
2898 if (!data || (mem_addr & 0xff00))
2899 return ICE_ERR_PARAM;
2901 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
2902 cmd = &desc.params.read_write_sff_param;
2903 desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
2904 cmd->lport_num = (u8)(lport & 0xff);
2905 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
2906 cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) &
2907 ICE_AQC_SFF_I2CBUS_7BIT_M) |
2909 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
2910 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
2911 cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff);
2912 cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
2914 cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE);
2916 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
2921 * __ice_aq_get_set_rss_lut
2922 * @hw: pointer to the hardware structure
2923 * @vsi_id: VSI FW index
2924 * @lut_type: LUT table type
2925 * @lut: pointer to the LUT buffer provided by the caller
2926 * @lut_size: size of the LUT buffer
2927 * @glob_lut_idx: global LUT index
2928 * @set: set true to set the table, false to get the table
2930 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2932 static enum ice_status
2933 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2934 u16 lut_size, u8 glob_lut_idx, bool set)
2936 struct ice_aqc_get_set_rss_lut *cmd_resp;
2937 struct ice_aq_desc desc;
2938 enum ice_status status;
2941 cmd_resp = &desc.params.get_set_rss_lut;
2944 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2945 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
2947 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2950 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
2951 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2952 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2953 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2956 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2957 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2958 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2959 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2960 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2963 status = ICE_ERR_PARAM;
2964 goto ice_aq_get_set_rss_lut_exit;
2967 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2968 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2969 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2972 goto ice_aq_get_set_rss_lut_send;
2973 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2975 goto ice_aq_get_set_rss_lut_send;
2977 goto ice_aq_get_set_rss_lut_send;
2980 /* LUT size is only valid for Global and PF table types */
2982 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2983 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG <<
2984 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2985 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2987 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
2988 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2989 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2990 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2992 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
2993 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2994 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
2995 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2996 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3001 status = ICE_ERR_PARAM;
3002 goto ice_aq_get_set_rss_lut_exit;
3005 ice_aq_get_set_rss_lut_send:
3006 cmd_resp->flags = CPU_TO_LE16(flags);
3007 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3009 ice_aq_get_set_rss_lut_exit:
3014 * ice_aq_get_rss_lut
3015 * @hw: pointer to the hardware structure
3016 * @vsi_handle: software VSI handle
3017 * @lut_type: LUT table type
3018 * @lut: pointer to the LUT buffer provided by the caller
3019 * @lut_size: size of the LUT buffer
3021 * get the RSS lookup table, PF or VSI type
3024 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3025 u8 *lut, u16 lut_size)
3027 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3028 return ICE_ERR_PARAM;
3030 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3031 lut_type, lut, lut_size, 0, false);
3035 * ice_aq_set_rss_lut
3036 * @hw: pointer to the hardware structure
3037 * @vsi_handle: software VSI handle
3038 * @lut_type: LUT table type
3039 * @lut: pointer to the LUT buffer provided by the caller
3040 * @lut_size: size of the LUT buffer
3042 * set the RSS lookup table, PF or VSI type
3045 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3046 u8 *lut, u16 lut_size)
3048 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3049 return ICE_ERR_PARAM;
3051 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3052 lut_type, lut, lut_size, 0, true);
3056 * __ice_aq_get_set_rss_key
3057 * @hw: pointer to the HW struct
3058 * @vsi_id: VSI FW index
3059 * @key: pointer to key info struct
3060 * @set: set true to set the key, false to get the key
3062 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3065 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3066 struct ice_aqc_get_set_rss_keys *key,
3069 struct ice_aqc_get_set_rss_key *cmd_resp;
3070 u16 key_size = sizeof(*key);
3071 struct ice_aq_desc desc;
3073 cmd_resp = &desc.params.get_set_rss_key;
3076 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3077 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3079 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3082 cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<
3083 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3084 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3085 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3087 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3091 * ice_aq_get_rss_key
3092 * @hw: pointer to the HW struct
3093 * @vsi_handle: software VSI handle
3094 * @key: pointer to key info struct
3096 * get the RSS key per VSI
3099 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3100 struct ice_aqc_get_set_rss_keys *key)
3102 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3103 return ICE_ERR_PARAM;
3105 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3110 * ice_aq_set_rss_key
3111 * @hw: pointer to the HW struct
3112 * @vsi_handle: software VSI handle
3113 * @keys: pointer to key info struct
3115 * set the RSS key per VSI
3118 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3119 struct ice_aqc_get_set_rss_keys *keys)
3121 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3122 return ICE_ERR_PARAM;
3124 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3129 * ice_aq_add_lan_txq
3130 * @hw: pointer to the hardware structure
3131 * @num_qgrps: Number of added queue groups
3132 * @qg_list: list of queue groups to be added
3133 * @buf_size: size of buffer for indirect command
3134 * @cd: pointer to command details structure or NULL
3136 * Add Tx LAN queue (0x0C30)
3139 * Prior to calling add Tx LAN queue:
3140 * Initialize the following as part of the Tx queue context:
3141 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3142 * Cache profile and Packet shaper profile.
3144 * After add Tx LAN queue AQ command is completed:
3145 * Interrupts should be associated with specific queues,
3146 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3150 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3151 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3152 struct ice_sq_cd *cd)
3154 u16 i, sum_header_size, sum_q_size = 0;
3155 struct ice_aqc_add_tx_qgrp *list;
3156 struct ice_aqc_add_txqs *cmd;
3157 struct ice_aq_desc desc;
3159 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3161 cmd = &desc.params.add_txqs;
3163 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3166 return ICE_ERR_PARAM;
3168 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3169 return ICE_ERR_PARAM;
3171 sum_header_size = num_qgrps *
3172 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
3175 for (i = 0; i < num_qgrps; i++) {
3176 struct ice_aqc_add_txqs_perq *q = list->txqs;
3178 sum_q_size += list->num_txqs * sizeof(*q);
3179 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
3182 if (buf_size != (sum_header_size + sum_q_size))
3183 return ICE_ERR_PARAM;
3185 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3187 cmd->num_qgrps = num_qgrps;
3189 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3193 * ice_aq_dis_lan_txq
3194 * @hw: pointer to the hardware structure
3195 * @num_qgrps: number of groups in the list
3196 * @qg_list: the list of groups to disable
3197 * @buf_size: the total size of the qg_list buffer in bytes
3198 * @rst_src: if called due to reset, specifies the reset source
3199 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3200 * @cd: pointer to command details structure or NULL
3202 * Disable LAN Tx queue (0x0C31)
3204 static enum ice_status
3205 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3206 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3207 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3208 struct ice_sq_cd *cd)
3210 struct ice_aqc_dis_txqs *cmd;
3211 struct ice_aq_desc desc;
3212 enum ice_status status;
3215 ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
3216 cmd = &desc.params.dis_txqs;
3217 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3219 /* qg_list can be NULL only in VM/VF reset flow */
3220 if (!qg_list && !rst_src)
3221 return ICE_ERR_PARAM;
3223 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3224 return ICE_ERR_PARAM;
3226 cmd->num_entries = num_qgrps;
3228 cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3229 ICE_AQC_Q_DIS_TIMEOUT_M);
3233 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3234 cmd->vmvf_and_timeout |=
3235 CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3242 /* flush pipe on time out */
3243 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3244 /* If no queue group info, we are in a reset flow. Issue the AQ */
3248 /* set RD bit to indicate that command buffer is provided by the driver
3249 * and it needs to be read by the firmware
3251 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3253 for (i = 0; i < num_qgrps; ++i) {
3254 /* Calculate the size taken up by the queue IDs in this group */
3255 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
3257 /* Add the size of the group header */
3258 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
3260 /* If the num of queues is even, add 2 bytes of padding */
3261 if ((qg_list[i].num_qs % 2) == 0)
3266 return ICE_ERR_PARAM;
3269 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3272 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3273 vmvf_num, hw->adminq.sq_last_status);
3275 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3276 LE16_TO_CPU(qg_list[0].q_id[0]),
3277 hw->adminq.sq_last_status);
3283 * ice_aq_move_recfg_lan_txq
3284 * @hw: pointer to the hardware structure
3285 * @num_qs: number of queues to move/reconfigure
3286 * @is_move: true if this operation involves node movement
3287 * @is_tc_change: true if this operation involves a TC change
3288 * @subseq_call: true if this operation is a subsequent call
3289 * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN
3290 * @timeout: timeout in units of 100 usec (valid values 0-50)
3291 * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN
3292 * @buf: struct containing src/dest TEID and per-queue info
3293 * @buf_size: size of buffer for indirect command
3294 * @txqs_moved: out param, number of queues successfully moved
3295 * @cd: pointer to command details structure or NULL
3297 * Move / Reconfigure Tx LAN queues (0x0C32)
3300 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move,
3301 bool is_tc_change, bool subseq_call, bool flush_pipe,
3302 u8 timeout, u32 *blocked_cgds,
3303 struct ice_aqc_move_txqs_data *buf, u16 buf_size,
3304 u8 *txqs_moved, struct ice_sq_cd *cd)
3306 struct ice_aqc_move_txqs *cmd;
3307 struct ice_aq_desc desc;
3308 enum ice_status status;
3310 cmd = &desc.params.move_txqs;
3311 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs);
3313 #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50
3314 if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX)
3315 return ICE_ERR_PARAM;
3317 if (is_tc_change && !flush_pipe && !blocked_cgds)
3318 return ICE_ERR_PARAM;
3320 if (!is_move && !is_tc_change)
3321 return ICE_ERR_PARAM;
3323 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
3326 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE;
3329 cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE;
3332 cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL;
3335 cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE;
3337 cmd->num_qs = num_qs;
3338 cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) &
3339 ICE_AQC_Q_CMD_TIMEOUT_M);
3341 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
3343 if (!status && txqs_moved)
3344 *txqs_moved = cmd->num_qs;
3346 if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN &&
3347 is_tc_change && !flush_pipe)
3348 *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds);
3353 /* End of FW Admin Queue command wrappers */
3356 * ice_write_byte - write a byte to a packed context structure
3357 * @src_ctx: the context structure to read from
3358 * @dest_ctx: the context to be written to
3359 * @ce_info: a description of the struct to be filled
3362 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3364 u8 src_byte, dest_byte, mask;
3368 /* copy from the next struct field */
3369 from = src_ctx + ce_info->offset;
3371 /* prepare the bits and mask */
3372 shift_width = ce_info->lsb % 8;
3373 mask = (u8)(BIT(ce_info->width) - 1);
3378 /* shift to correct alignment */
3379 mask <<= shift_width;
3380 src_byte <<= shift_width;
3382 /* get the current bits from the target bit string */
3383 dest = dest_ctx + (ce_info->lsb / 8);
3385 ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3387 dest_byte &= ~mask; /* get the bits not changing */
3388 dest_byte |= src_byte; /* add in the new bits */
3390 /* put it all back */
3391 ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3395 * ice_write_word - write a word to a packed context structure
3396 * @src_ctx: the context structure to read from
3397 * @dest_ctx: the context to be written to
3398 * @ce_info: a description of the struct to be filled
3401 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3408 /* copy from the next struct field */
3409 from = src_ctx + ce_info->offset;
3411 /* prepare the bits and mask */
3412 shift_width = ce_info->lsb % 8;
3413 mask = BIT(ce_info->width) - 1;
3415 /* don't swizzle the bits until after the mask because the mask bits
3416 * will be in a different bit position on big endian machines
3418 src_word = *(u16 *)from;
3421 /* shift to correct alignment */
3422 mask <<= shift_width;
3423 src_word <<= shift_width;
3425 /* get the current bits from the target bit string */
3426 dest = dest_ctx + (ce_info->lsb / 8);
3428 ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);
3430 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
3431 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
3433 /* put it all back */
3434 ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3438 * ice_write_dword - write a dword to a packed context structure
3439 * @src_ctx: the context structure to read from
3440 * @dest_ctx: the context to be written to
3441 * @ce_info: a description of the struct to be filled
3444 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3446 u32 src_dword, mask;
3451 /* copy from the next struct field */
3452 from = src_ctx + ce_info->offset;
3454 /* prepare the bits and mask */
3455 shift_width = ce_info->lsb % 8;
3457 /* if the field width is exactly 32 on an x86 machine, then the shift
3458 * operation will not work because the SHL instructions count is masked
3459 * to 5 bits so the shift will do nothing
3461 if (ce_info->width < 32)
3462 mask = BIT(ce_info->width) - 1;
3466 /* don't swizzle the bits until after the mask because the mask bits
3467 * will be in a different bit position on big endian machines
3469 src_dword = *(u32 *)from;
3472 /* shift to correct alignment */
3473 mask <<= shift_width;
3474 src_dword <<= shift_width;
3476 /* get the current bits from the target bit string */
3477 dest = dest_ctx + (ce_info->lsb / 8);
3479 ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);
3481 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
3482 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
3484 /* put it all back */
3485 ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3489 * ice_write_qword - write a qword to a packed context structure
3490 * @src_ctx: the context structure to read from
3491 * @dest_ctx: the context to be written to
3492 * @ce_info: a description of the struct to be filled
3495 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3497 u64 src_qword, mask;
3502 /* copy from the next struct field */
3503 from = src_ctx + ce_info->offset;
3505 /* prepare the bits and mask */
3506 shift_width = ce_info->lsb % 8;
3508 /* if the field width is exactly 64 on an x86 machine, then the shift
3509 * operation will not work because the SHL instructions count is masked
3510 * to 6 bits so the shift will do nothing
3512 if (ce_info->width < 64)
3513 mask = BIT_ULL(ce_info->width) - 1;
3517 /* don't swizzle the bits until after the mask because the mask bits
3518 * will be in a different bit position on big endian machines
3520 src_qword = *(u64 *)from;
3523 /* shift to correct alignment */
3524 mask <<= shift_width;
3525 src_qword <<= shift_width;
3527 /* get the current bits from the target bit string */
3528 dest = dest_ctx + (ce_info->lsb / 8);
3530 ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);
3532 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
3533 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
3535 /* put it all back */
3536 ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3540 * ice_set_ctx - set context bits in packed structure
3541 * @src_ctx: pointer to a generic non-packed context structure
3542 * @dest_ctx: pointer to memory for the packed structure
3543 * @ce_info: a description of the structure to be transformed
3546 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3550 for (f = 0; ce_info[f].width; f++) {
3551 /* We have to deal with each element of the FW response
3552 * using the correct size so that we are correct regardless
3553 * of the endianness of the machine.
3555 switch (ce_info[f].size_of) {
3557 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3560 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3563 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3566 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3569 return ICE_ERR_INVAL_SIZE;
3577 * ice_read_byte - read context byte into struct
3578 * @src_ctx: the context structure to read from
3579 * @dest_ctx: the context to be written to
3580 * @ce_info: a description of the struct to be filled
3583 ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3589 /* prepare the bits and mask */
3590 shift_width = ce_info->lsb % 8;
3591 mask = (u8)(BIT(ce_info->width) - 1);
3593 /* shift to correct alignment */
3594 mask <<= shift_width;
3596 /* get the current bits from the src bit string */
3597 src = src_ctx + (ce_info->lsb / 8);
3599 ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);
3601 dest_byte &= ~(mask);
3603 dest_byte >>= shift_width;
3605 /* get the address from the struct field */
3606 target = dest_ctx + ce_info->offset;
3608 /* put it back in the struct */
3609 ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);
3613 * ice_read_word - read context word into struct
3614 * @src_ctx: the context structure to read from
3615 * @dest_ctx: the context to be written to
3616 * @ce_info: a description of the struct to be filled
3619 ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3621 u16 dest_word, mask;
3626 /* prepare the bits and mask */
3627 shift_width = ce_info->lsb % 8;
3628 mask = BIT(ce_info->width) - 1;
3630 /* shift to correct alignment */
3631 mask <<= shift_width;
3633 /* get the current bits from the src bit string */
3634 src = src_ctx + (ce_info->lsb / 8);
3636 ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);
3638 /* the data in the memory is stored as little endian so mask it
3641 src_word &= ~(CPU_TO_LE16(mask));
3643 /* get the data back into host order before shifting */
3644 dest_word = LE16_TO_CPU(src_word);
3646 dest_word >>= shift_width;
3648 /* get the address from the struct field */
3649 target = dest_ctx + ce_info->offset;
3651 /* put it back in the struct */
3652 ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);
3656 * ice_read_dword - read context dword into struct
3657 * @src_ctx: the context structure to read from
3658 * @dest_ctx: the context to be written to
3659 * @ce_info: a description of the struct to be filled
3662 ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3664 u32 dest_dword, mask;
3669 /* prepare the bits and mask */
3670 shift_width = ce_info->lsb % 8;
3672 /* if the field width is exactly 32 on an x86 machine, then the shift
3673 * operation will not work because the SHL instructions count is masked
3674 * to 5 bits so the shift will do nothing
3676 if (ce_info->width < 32)
3677 mask = BIT(ce_info->width) - 1;
3681 /* shift to correct alignment */
3682 mask <<= shift_width;
3684 /* get the current bits from the src bit string */
3685 src = src_ctx + (ce_info->lsb / 8);
3687 ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);
3689 /* the data in the memory is stored as little endian so mask it
3692 src_dword &= ~(CPU_TO_LE32(mask));
3694 /* get the data back into host order before shifting */
3695 dest_dword = LE32_TO_CPU(src_dword);
3697 dest_dword >>= shift_width;
3699 /* get the address from the struct field */
3700 target = dest_ctx + ce_info->offset;
3702 /* put it back in the struct */
3703 ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);
3707 * ice_read_qword - read context qword into struct
3708 * @src_ctx: the context structure to read from
3709 * @dest_ctx: the context to be written to
3710 * @ce_info: a description of the struct to be filled
3713 ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3715 u64 dest_qword, mask;
3720 /* prepare the bits and mask */
3721 shift_width = ce_info->lsb % 8;
3723 /* if the field width is exactly 64 on an x86 machine, then the shift
3724 * operation will not work because the SHL instructions count is masked
3725 * to 6 bits so the shift will do nothing
3727 if (ce_info->width < 64)
3728 mask = BIT_ULL(ce_info->width) - 1;
3732 /* shift to correct alignment */
3733 mask <<= shift_width;
3735 /* get the current bits from the src bit string */
3736 src = src_ctx + (ce_info->lsb / 8);
3738 ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);
3740 /* the data in the memory is stored as little endian so mask it
3743 src_qword &= ~(CPU_TO_LE64(mask));
3745 /* get the data back into host order before shifting */
3746 dest_qword = LE64_TO_CPU(src_qword);
3748 dest_qword >>= shift_width;
3750 /* get the address from the struct field */
3751 target = dest_ctx + ce_info->offset;
3753 /* put it back in the struct */
3754 ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);
3758 * ice_get_ctx - extract context bits from a packed structure
3759 * @src_ctx: pointer to a generic packed context structure
3760 * @dest_ctx: pointer to a generic non-packed context structure
3761 * @ce_info: a description of the structure to be read from
3764 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)
3768 for (f = 0; ce_info[f].width; f++) {
3769 switch (ce_info[f].size_of) {
3771 ice_read_byte(src_ctx, dest_ctx, &ce_info[f]);
3774 ice_read_word(src_ctx, dest_ctx, &ce_info[f]);
3777 ice_read_dword(src_ctx, dest_ctx, &ce_info[f]);
3780 ice_read_qword(src_ctx, dest_ctx, &ce_info[f]);
3783 /* nothing to do, just keep going */
3792 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3793 * @hw: pointer to the HW struct
3794 * @vsi_handle: software VSI handle
3796 * @q_handle: software queue handle
3799 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3801 struct ice_vsi_ctx *vsi;
3802 struct ice_q_ctx *q_ctx;
3804 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3807 if (q_handle >= vsi->num_lan_q_entries[tc])
3809 if (!vsi->lan_q_ctx[tc])
3811 q_ctx = vsi->lan_q_ctx[tc];
3812 return &q_ctx[q_handle];
3817 * @pi: port information structure
3818 * @vsi_handle: software VSI handle
3820 * @q_handle: software queue handle
3821 * @num_qgrps: Number of added queue groups
3822 * @buf: list of queue groups to be added
3823 * @buf_size: size of buffer for indirect command
3824 * @cd: pointer to command details structure or NULL
3826 * This function adds one LAN queue
3829 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3830 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3831 struct ice_sq_cd *cd)
3833 struct ice_aqc_txsched_elem_data node = { 0 };
3834 struct ice_sched_node *parent;
3835 struct ice_q_ctx *q_ctx;
3836 enum ice_status status;
3839 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3842 if (num_qgrps > 1 || buf->num_txqs > 1)
3843 return ICE_ERR_MAX_LIMIT;
3847 if (!ice_is_vsi_valid(hw, vsi_handle))
3848 return ICE_ERR_PARAM;
3850 ice_acquire_lock(&pi->sched_lock);
3852 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3854 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3856 status = ICE_ERR_PARAM;
3860 /* find a parent node */
3861 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3862 ICE_SCHED_NODE_OWNER_LAN);
3864 status = ICE_ERR_PARAM;
3868 buf->parent_teid = parent->info.node_teid;
3869 node.parent_teid = parent->info.node_teid;
3870 /* Mark that the values in the "generic" section as valid. The default
3871 * value in the "generic" section is zero. This means that :
3872 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3873 * - 0 priority among siblings, indicated by Bit 1-3.
3874 * - WFQ, indicated by Bit 4.
3875 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3877 * - Bit 7 is reserved.
3878 * Without setting the generic section as valid in valid_sections, the
3879 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3881 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3883 /* add the LAN queue */
3884 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3885 if (status != ICE_SUCCESS) {
3886 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3887 LE16_TO_CPU(buf->txqs[0].txq_id),
3888 hw->adminq.sq_last_status);
3892 node.node_teid = buf->txqs[0].q_teid;
3893 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3894 q_ctx->q_handle = q_handle;
3895 q_ctx->q_teid = LE32_TO_CPU(node.node_teid);
3897 /* add a leaf node into scheduler tree queue layer */
3898 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3900 status = ice_sched_replay_q_bw(pi, q_ctx);
3903 ice_release_lock(&pi->sched_lock);
3909 * @pi: port information structure
3910 * @vsi_handle: software VSI handle
3912 * @num_queues: number of queues
3913 * @q_handles: pointer to software queue handle array
3914 * @q_ids: pointer to the q_id array
3915 * @q_teids: pointer to queue node teids
3916 * @rst_src: if called due to reset, specifies the reset source
3917 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3918 * @cd: pointer to command details structure or NULL
3920 * This function removes queues and their corresponding nodes in SW DB
3923 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3924 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3925 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3926 struct ice_sq_cd *cd)
3928 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3929 struct ice_aqc_dis_txq_item qg_list;
3930 struct ice_q_ctx *q_ctx;
3933 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3937 /* if queue is disabled already yet the disable queue command
3938 * has to be sent to complete the VF reset, then call
3939 * ice_aq_dis_lan_txq without any queue information
3942 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
3947 ice_acquire_lock(&pi->sched_lock);
3949 for (i = 0; i < num_queues; i++) {
3950 struct ice_sched_node *node;
3952 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3955 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3957 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3961 if (q_ctx->q_handle != q_handles[i]) {
3962 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3963 q_ctx->q_handle, q_handles[i]);
3966 qg_list.parent_teid = node->info.parent_teid;
3968 qg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);
3969 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3970 sizeof(qg_list), rst_src, vmvf_num,
3973 if (status != ICE_SUCCESS)
3975 ice_free_sched_node(pi, node);
3976 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
3978 ice_release_lock(&pi->sched_lock);
3983 * ice_cfg_vsi_qs - configure the new/existing VSI queues
3984 * @pi: port information structure
3985 * @vsi_handle: software VSI handle
3986 * @tc_bitmap: TC bitmap
3987 * @maxqs: max queues array per TC
3988 * @owner: LAN or RDMA
3990 * This function adds/updates the VSI queues per TC.
3992 static enum ice_status
3993 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
3994 u16 *maxqs, u8 owner)
3996 enum ice_status status = ICE_SUCCESS;
3999 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4002 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4003 return ICE_ERR_PARAM;
4005 ice_acquire_lock(&pi->sched_lock);
4007 ice_for_each_traffic_class(i) {
4008 /* configuration is possible only if TC node is present */
4009 if (!ice_sched_get_tc_node(pi, i))
4012 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4013 ice_is_tc_ena(tc_bitmap, i));
4018 ice_release_lock(&pi->sched_lock);
4023 * ice_cfg_vsi_lan - configure VSI LAN queues
4024 * @pi: port information structure
4025 * @vsi_handle: software VSI handle
4026 * @tc_bitmap: TC bitmap
4027 * @max_lanqs: max LAN queues array per TC
4029 * This function adds/updates the VSI LAN queues per TC.
4032 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4035 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4036 ICE_SCHED_NODE_OWNER_LAN);
4040 * ice_replay_pre_init - replay pre initialization
4041 * @hw: pointer to the HW struct
4043 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4045 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
4047 struct ice_switch_info *sw = hw->switch_info;
4050 /* Delete old entries from replay filter list head if there is any */
4051 ice_rm_all_sw_replay_rule_info(hw);
4052 /* In start of replay, move entries into replay_rules list, it
4053 * will allow adding rules entries back to filt_rules list,
4054 * which is operational list.
4056 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4057 LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,
4058 &sw->recp_list[i].filt_replay_rules);
4059 ice_sched_replay_agg_vsi_preinit(hw);
4061 return ice_sched_replay_tc_node_bw(hw->port_info);
4065 * ice_replay_vsi - replay VSI configuration
4066 * @hw: pointer to the HW struct
4067 * @vsi_handle: driver VSI handle
4069 * Restore all VSI configuration after reset. It is required to call this
4070 * function with main VSI first.
4072 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4074 enum ice_status status;
4076 if (!ice_is_vsi_valid(hw, vsi_handle))
4077 return ICE_ERR_PARAM;
4079 /* Replay pre-initialization if there is any */
4080 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
4081 status = ice_replay_pre_init(hw);
4085 /* Replay per VSI all RSS configurations */
4086 status = ice_replay_rss_cfg(hw, vsi_handle);
4089 /* Replay per VSI all filters */
4090 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
4092 status = ice_replay_vsi_agg(hw, vsi_handle);
4097 * ice_replay_post - post replay configuration cleanup
4098 * @hw: pointer to the HW struct
4100 * Post replay cleanup.
4102 void ice_replay_post(struct ice_hw *hw)
4104 /* Delete old entries from replay filter list head */
4105 ice_rm_all_sw_replay_rule_info(hw);
4106 ice_sched_replay_agg(hw);
4110 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4111 * @hw: ptr to the hardware info
4112 * @reg: offset of 64 bit HW register to read from
4113 * @prev_stat_loaded: bool to specify if previous stats are loaded
4114 * @prev_stat: ptr to previous loaded stat value
4115 * @cur_stat: ptr to current stat value
4118 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4119 u64 *prev_stat, u64 *cur_stat)
4121 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4123 /* device stats are not reset at PFR, they likely will not be zeroed
4124 * when the driver starts. Thus, save the value from the first read
4125 * without adding to the statistic value so that we report stats which
4126 * count up from zero.
4128 if (!prev_stat_loaded) {
4129 *prev_stat = new_data;
4133 /* Calculate the difference between the new and old values, and then
4134 * add it to the software stat value.
4136 if (new_data >= *prev_stat)
4137 *cur_stat += new_data - *prev_stat;
4139 /* to manage the potential roll-over */
4140 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4142 /* Update the previously stored value to prepare for next read */
4143 *prev_stat = new_data;
4147 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4148 * @hw: ptr to the hardware info
4149 * @reg: offset of HW register to read from
4150 * @prev_stat_loaded: bool to specify if previous stats are loaded
4151 * @prev_stat: ptr to previous loaded stat value
4152 * @cur_stat: ptr to current stat value
4155 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4156 u64 *prev_stat, u64 *cur_stat)
4160 new_data = rd32(hw, reg);
4162 /* device stats are not reset at PFR, they likely will not be zeroed
4163 * when the driver starts. Thus, save the value from the first read
4164 * without adding to the statistic value so that we report stats which
4165 * count up from zero.
4167 if (!prev_stat_loaded) {
4168 *prev_stat = new_data;
4172 /* Calculate the difference between the new and old values, and then
4173 * add it to the software stat value.
4175 if (new_data >= *prev_stat)
4176 *cur_stat += new_data - *prev_stat;
4178 /* to manage the potential roll-over */
4179 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4181 /* Update the previously stored value to prepare for next read */
4182 *prev_stat = new_data;
4186 * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values
4187 * @hw: ptr to the hardware info
4188 * @vsi_handle: VSI handle
4189 * @prev_stat_loaded: bool to specify if the previous stat values are loaded
4190 * @cur_stats: ptr to current stats structure
4192 * The GLV_REPC statistic register actually tracks two 16bit statistics, and
4193 * thus cannot be read using the normal ice_stat_update32 function.
4195 * Read the GLV_REPC register associated with the given VSI, and update the
4196 * rx_no_desc and rx_error values in the ice_eth_stats structure.
4198 * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be
4199 * cleared each time it's read.
4201 * Note that the GLV_RDPC register also counts the causes that would trigger
4202 * GLV_REPC. However, it does not give the finer grained detail about why the
4203 * packets are being dropped. The GLV_REPC values can be used to distinguish
4204 * whether Rx packets are dropped due to errors or due to no available
4208 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded,
4209 struct ice_eth_stats *cur_stats)
4211 u16 vsi_num, no_desc, error_cnt;
4214 if (!ice_is_vsi_valid(hw, vsi_handle))
4217 vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);
4219 /* If we haven't loaded stats yet, just clear the current value */
4220 if (!prev_stat_loaded) {
4221 wr32(hw, GLV_REPC(vsi_num), 0);
4225 repc = rd32(hw, GLV_REPC(vsi_num));
4226 no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S;
4227 error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S;
4229 /* Clear the count by writing to the stats register */
4230 wr32(hw, GLV_REPC(vsi_num), 0);
4232 cur_stats->rx_no_desc += no_desc;
4233 cur_stats->rx_errors += error_cnt;
4237 * ice_sched_query_elem - query element information from HW
4238 * @hw: pointer to the HW struct
4239 * @node_teid: node TEID to be queried
4240 * @buf: buffer to element information
4242 * This function queries HW element information
4245 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4246 struct ice_aqc_get_elem *buf)
4248 u16 buf_size, num_elem_ret = 0;
4249 enum ice_status status;
4251 buf_size = sizeof(*buf);
4252 ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);
4253 buf->generic[0].node_teid = CPU_TO_LE32(node_teid);
4254 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4256 if (status != ICE_SUCCESS || num_elem_ret != 1)
4257 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4262 * ice_get_fw_mode - returns FW mode
4263 * @hw: pointer to the HW struct
4265 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
4267 #define ICE_FW_MODE_DBG_M BIT(0)
4268 #define ICE_FW_MODE_REC_M BIT(1)
4269 #define ICE_FW_MODE_ROLLBACK_M BIT(2)
4272 /* check the current FW mode */
4273 fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M;
4275 if (fw_mode & ICE_FW_MODE_DBG_M)
4276 return ICE_FW_MODE_DBG;
4277 else if (fw_mode & ICE_FW_MODE_REC_M)
4278 return ICE_FW_MODE_REC;
4279 else if (fw_mode & ICE_FW_MODE_ROLLBACK_M)
4280 return ICE_FW_MODE_ROLLBACK;
4282 return ICE_FW_MODE_NORMAL;
4286 * ice_fw_supports_link_override
4287 * @hw: pointer to the hardware structure
4289 * Checks if the firmware supports link override
4291 bool ice_fw_supports_link_override(struct ice_hw *hw)
4293 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
4294 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
4296 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
4297 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
4299 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
4307 * ice_get_link_default_override
4308 * @ldo: pointer to the link default override struct
4309 * @pi: pointer to the port info struct
4311 * Gets the link default override for a port
4314 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
4315 struct ice_port_info *pi)
4317 u16 i, tlv, tlv_len, tlv_start, buf, offset;
4318 struct ice_hw *hw = pi->hw;
4319 enum ice_status status;
4321 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
4322 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
4324 ice_debug(hw, ICE_DBG_INIT,
4325 "Failed to read link override TLV.\n");
4329 /* Each port has its own config; calculate for our port */
4330 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
4331 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
4333 /* link options first */
4334 status = ice_read_sr_word(hw, tlv_start, &buf);
4336 ice_debug(hw, ICE_DBG_INIT,
4337 "Failed to read override link options.\n");
4340 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
4341 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
4342 ICE_LINK_OVERRIDE_PHY_CFG_S;
4344 /* link PHY config */
4345 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
4346 status = ice_read_sr_word(hw, offset, &buf);
4348 ice_debug(hw, ICE_DBG_INIT,
4349 "Failed to read override phy config.\n");
4352 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
4355 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
4356 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4357 status = ice_read_sr_word(hw, (offset + i), &buf);
4359 ice_debug(hw, ICE_DBG_INIT,
4360 "Failed to read override link options.\n");
4363 /* shift 16 bits at a time to fill 64 bits */
4364 ldo->phy_type_low |= ((u64)buf << (i * 16));
4367 /* PHY types high */
4368 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
4369 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
4370 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4371 status = ice_read_sr_word(hw, (offset + i), &buf);
4373 ice_debug(hw, ICE_DBG_INIT,
4374 "Failed to read override link options.\n");
4377 /* shift 16 bits at a time to fill 64 bits */
4378 ldo->phy_type_high |= ((u64)buf << (i * 16));