1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2019
10 #define ETH_HEADER_LEN 14
12 #define BIT(a) (1UL << (a))
13 #define BIT_ULL(a) (1ULL << (a))
15 #define BITS_PER_BYTE 8
17 #define ICE_BYTES_PER_WORD 2
18 #define ICE_BYTES_PER_DWORD 4
19 #define ICE_MAX_TRAFFIC_CLASS 8
22 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
26 #define IS_ASCII(_ch) ((_ch) < 0x80)
29 #include "ice_status.h"
30 #include "ice_hw_autogen.h"
31 #include "ice_devids.h"
32 #include "ice_osdep.h"
33 #include "ice_bitops.h" /* Must come before ice_controlq.h */
34 #include "ice_controlq.h"
35 #include "ice_lan_tx_rx.h"
36 #include "ice_flex_type.h"
37 #include "ice_protocol_type.h"
39 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
41 return ice_is_bit_set(&bitmap, tc);
45 #define DIV_64BIT(n, d) ((n) / (d))
46 #endif /* DIV_64BIT */
48 static inline u64 round_up_64bit(u64 a, u32 b)
50 return DIV_64BIT(((a) + (b) / 2), (b));
53 static inline u32 ice_round_to_num(u32 N, u32 R)
55 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
56 ((((N) + (R) - 1) / (R)) * (R)));
59 /* Driver always calls main vsi_handle first */
60 #define ICE_MAIN_VSI_HANDLE 0
62 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
63 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
65 /* Data type manipulation macros. */
66 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
67 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
68 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
70 /* debug masks - set these bits in hw->debug_mask to control output */
71 #define ICE_DBG_INIT BIT_ULL(1)
72 #define ICE_DBG_RELEASE BIT_ULL(2)
74 #define ICE_DBG_LINK BIT_ULL(4)
75 #define ICE_DBG_PHY BIT_ULL(5)
76 #define ICE_DBG_QCTX BIT_ULL(6)
77 #define ICE_DBG_NVM BIT_ULL(7)
78 #define ICE_DBG_LAN BIT_ULL(8)
79 #define ICE_DBG_FLOW BIT_ULL(9)
80 #define ICE_DBG_DCB BIT_ULL(10)
81 #define ICE_DBG_DIAG BIT_ULL(11)
82 #define ICE_DBG_FD BIT_ULL(12)
83 #define ICE_DBG_SW BIT_ULL(13)
84 #define ICE_DBG_SCHED BIT_ULL(14)
86 #define ICE_DBG_PKG BIT_ULL(16)
87 #define ICE_DBG_RES BIT_ULL(17)
88 #define ICE_DBG_AQ_MSG BIT_ULL(24)
89 #define ICE_DBG_AQ_DESC BIT_ULL(25)
90 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
91 #define ICE_DBG_AQ_CMD BIT_ULL(27)
92 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
94 ICE_DBG_AQ_DESC_BUF | \
97 #define ICE_DBG_USER BIT_ULL(31)
98 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
105 enum ice_aq_res_ids {
108 ICE_CHANGE_LOCK_RES_ID,
109 ICE_GLOBAL_CFG_LOCK_RES_ID
112 /* FW update timeout definitions are in milliseconds */
113 #define ICE_NVM_TIMEOUT 180000
114 #define ICE_CHANGE_LOCK_TIMEOUT 1000
115 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
117 enum ice_aq_res_access_type {
122 struct ice_driver_ver {
127 u8 driver_string[32];
139 enum ice_phy_cache_mode {
152 struct ice_phy_cache_mode_data {
154 enum ice_fec_mode curr_user_fec_req;
155 enum ice_fc_mode curr_user_fc_req;
156 u16 curr_user_speed_req;
160 enum ice_set_fc_aq_failures {
161 ICE_SET_FC_AQ_FAIL_NONE = 0,
162 ICE_SET_FC_AQ_FAIL_GET,
163 ICE_SET_FC_AQ_FAIL_SET,
164 ICE_SET_FC_AQ_FAIL_UPDATE
167 /* These are structs for managing the hardware information and the operations */
175 enum ice_media_type {
176 ICE_MEDIA_UNKNOWN = 0,
183 /* Software VSI types. */
186 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
189 #endif /* ADQ_SUPPORT */
192 struct ice_link_status {
193 /* Refer to ice_aq_phy_type for bits definition */
196 u8 topo_media_conflict;
200 u8 lse_ena; /* Link Status Event notification */
206 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
207 * ice_aqc_get_phy_caps structure
209 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
212 /* Different data queue types: These are mainly for SW consumption. */
221 /* Different reset sources for which a disable queue AQ call has to be made in
222 * order to clean the Tx scheduler as a part of the reset
224 enum ice_disq_rst_src {
229 /* PHY info such as phy_type, etc... */
230 struct ice_phy_info {
231 struct ice_link_status link_info;
232 struct ice_link_status link_info_old;
235 enum ice_media_type media_type;
237 /* Please refer to struct ice_aqc_get_link_status_data to get
238 * detail of enable bit in curr_user_speed_req
240 u16 curr_user_speed_req;
241 enum ice_fec_mode curr_user_fec_req;
242 enum ice_fc_mode curr_user_fc_req;
243 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
246 #define ICE_MAX_NUM_MIRROR_RULES 64
248 /* protocol enumeration for filters */
249 enum ice_fltr_ptype {
250 /* NONE - used for undef/error */
251 ICE_FLTR_PTYPE_NONF_NONE = 0,
252 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
253 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
254 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
255 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
256 ICE_FLTR_PTYPE_FRAG_IPV4,
257 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
258 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
259 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
260 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
264 /* 6 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + 4 ICE_VSI_CHNL */
265 #define ICE_MAX_FDIR_VSI_PER_FILTER 6
267 struct ice_fd_hw_prof {
268 struct ice_flow_seg_info *fdir_seg;
270 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER];
271 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
274 /* Common HW capabilities for SW use */
275 struct ice_hw_common_caps {
276 /* Write CSR protection */
279 /* switching mode supported - EVB switching (including cloud) */
280 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
282 /* Manageablity mode & supported protocols over MCTP */
284 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
285 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
286 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
288 u32 mgmt_protocols_mctp;
289 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
290 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
291 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
292 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
296 /* DCB capabilities */
297 u32 active_tc_bitmap;
300 /* RSS related capabilities */
301 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
302 u32 rss_table_entry_width; /* RSS Entry width in bits */
305 u32 num_rxq; /* Number/Total Rx queues */
306 u32 rxq_first_id; /* First queue ID for Rx queues */
307 u32 num_txq; /* Number/Total Tx queues */
308 u32 txq_first_id; /* First queue ID for Tx queues */
311 u32 num_msix_vectors;
312 u32 msix_vector_first_id;
314 /* Max MTU for function or device */
318 u32 num_wol_proxy_fltr;
319 u32 wol_proxy_vsi_seid;
321 /* LED/SDP pin count */
325 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
326 #define ICE_MAX_SUPPORTED_GPIO_LED 12
327 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
328 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
329 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
331 /* EVB capabilities */
332 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
333 u8 evb_802_1_qbh; /* Bridge Port Extension */
339 /* WoL and APM support */
340 #define ICE_WOL_SUPPORT_M BIT(0)
341 #define ICE_ACPI_PROG_MTHD_M BIT(1)
342 #define ICE_PROXY_SUPPORT_M BIT(2)
349 /* Function specific capabilities */
350 struct ice_hw_func_caps {
351 struct ice_hw_common_caps common_cap;
353 u32 fd_fltr_guar; /* Number of filters guaranteed */
354 u32 fd_fltr_best_effort; /* Number of best effort filters */
357 /* Device wide capabilities */
358 struct ice_hw_dev_caps {
359 struct ice_hw_common_caps common_cap;
360 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
361 u32 num_flow_director_fltr; /* Number of FD filters available */
365 /* Information about MAC such as address, etc... */
366 struct ice_mac_info {
367 u8 lan_addr[ETH_ALEN];
368 u8 perm_addr[ETH_ALEN];
369 u8 port_addr[ETH_ALEN];
370 u8 wol_addr[ETH_ALEN];
377 ice_bus_embedded, /* Is device Embedded versus card */
382 enum ice_pcie_bus_speed {
383 ice_pcie_speed_unknown = 0xff,
384 ice_pcie_speed_2_5GT = 0x14,
385 ice_pcie_speed_5_0GT = 0x15,
386 ice_pcie_speed_8_0GT = 0x16,
387 ice_pcie_speed_16_0GT = 0x17
391 enum ice_pcie_link_width {
392 ice_pcie_lnk_width_resrv = 0x00,
393 ice_pcie_lnk_x1 = 0x01,
394 ice_pcie_lnk_x2 = 0x02,
395 ice_pcie_lnk_x4 = 0x04,
396 ice_pcie_lnk_x8 = 0x08,
397 ice_pcie_lnk_x12 = 0x0C,
398 ice_pcie_lnk_x16 = 0x10,
399 ice_pcie_lnk_x32 = 0x20,
400 ice_pcie_lnk_width_unknown = 0xff,
403 /* Reset types used to determine which kind of reset was requested. These
404 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
405 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
406 * because its reset source is different than the other types listed.
418 struct ice_bus_info {
419 enum ice_pcie_bus_speed speed;
420 enum ice_pcie_link_width width;
421 enum ice_bus_type type;
428 /* Flow control (FC) parameters */
430 enum ice_fc_mode current_mode; /* FC mode in effect */
431 enum ice_fc_mode req_mode; /* FC mode requested by caller */
434 /* NVM Information */
435 struct ice_nvm_info {
436 u32 eetrack; /* NVM data version */
437 u32 oem_ver; /* OEM version info */
438 u16 sr_words; /* Shadow RAM size in words */
439 u16 ver; /* NVM package version */
440 u8 blank_nvm_mode; /* is NVM empty (no FW present)*/
443 /* Max number of port to queue branches w.r.t topology */
444 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
446 #define ice_for_each_traffic_class(_i) \
447 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
449 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
450 * to driver defined policy for default aggregator
452 #define ICE_INVAL_TEID 0xFFFFFFFF
453 #define ICE_DFLT_AGG_ID 0
455 struct ice_sched_node {
456 struct ice_sched_node *parent;
457 struct ice_sched_node *sibling; /* next sibling in the same layer */
458 struct ice_sched_node **children;
459 struct ice_aqc_txsched_elem_data info;
460 u32 agg_id; /* aggregator group ID */
462 u8 in_use; /* suspended or in use */
463 u8 tx_sched_layer; /* Logical Layer (1-9) */
467 #define ICE_SCHED_NODE_OWNER_LAN 0
468 #define ICE_SCHED_NODE_OWNER_AE 1
469 #define ICE_SCHED_NODE_OWNER_RDMA 2
472 /* Access Macros for Tx Sched Elements data */
473 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
474 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
475 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
476 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
477 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
478 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
479 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
480 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
481 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
482 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
483 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
485 struct ice_sched_rl_profle {
486 u32 rate; /* In Kbps */
487 struct ice_aqc_rl_profile_elem info;
490 /* The aggregator type determines if identifier is for a VSI group,
491 * aggregator group, aggregator of queues, or queue group.
494 ICE_AGG_TYPE_UNKNOWN = 0,
496 ICE_AGG_TYPE_AGG, /* aggregator */
502 /* Rate limit types */
505 ICE_MIN_BW, /* for CIR profile */
506 ICE_MAX_BW, /* for EIR profile */
507 ICE_SHARED_BW /* for shared profile */
510 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
511 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
512 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
513 #define ICE_SCHED_NO_PRIORITY 0
514 #define ICE_SCHED_NO_BW_WT 0
515 #define ICE_SCHED_DFLT_RL_PROF_ID 0
516 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
517 #define ICE_SCHED_DFLT_BW_WT 1
518 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
519 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
521 /* Access Macros for Tx Sched RL Profile data */
522 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
523 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
524 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
525 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
526 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
529 /* The following tree example shows the naming conventions followed under
530 * ice_port_info struct for default scheduler tree topology.
534 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
538 * / |-> num_elements (range:1 - 9)
539 * * | implies num_of_layers
543 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
544 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
545 * need TEID of (a) to add queues.
548 * -> has 8 branches (one for each TC)
549 * -> First branch (TC0) has 4 elements
551 * -> (a) is the topmost layer node created by firmware on branch 0
553 * Note: Above asterisk tree covers only basic terminology and scenario.
554 * Refer to the documentation for more info.
557 /* Data structure for saving BW information */
565 ICE_BW_TYPE_CNT /* This must be last */
573 struct ice_bw_type_info {
574 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
576 struct ice_bw cir_bw;
577 struct ice_bw eir_bw;
581 /* VSI queue context structure for given TC */
585 /* bw_t_info saves queue BW information */
586 struct ice_bw_type_info bw_t_info;
589 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
590 struct ice_sched_vsi_info {
591 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
592 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
593 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
594 /* bw_t_info saves VSI BW information */
595 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
598 /* CEE or IEEE 802.1Qaz ETS Configuration data */
599 struct ice_dcb_ets_cfg {
603 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
604 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
605 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
608 /* CEE or IEEE 802.1Qaz PFC Configuration data */
609 struct ice_dcb_pfc_cfg {
616 /* CEE or IEEE 802.1Qaz Application Priority data */
617 struct ice_dcb_app_priority_table {
623 #define ICE_MAX_USER_PRIORITY 8
624 #define ICE_DCBX_MAX_APPS 32
625 #define ICE_LLDPDU_SIZE 1500
626 #define ICE_TLV_STATUS_OPER 0x1
627 #define ICE_TLV_STATUS_SYNC 0x2
628 #define ICE_TLV_STATUS_ERR 0x4
629 #define ICE_APP_PROT_ID_FCOE 0x8906
630 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
631 #define ICE_APP_PROT_ID_FIP 0x8914
632 #define ICE_APP_SEL_ETHTYPE 0x1
633 #define ICE_APP_SEL_TCPIP 0x2
634 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
635 #define ICE_CEE_APP_SEL_TCPIP 0x1
637 struct ice_dcbx_cfg {
639 u32 tlv_status; /* CEE mode TLV status */
640 struct ice_dcb_ets_cfg etscfg;
641 struct ice_dcb_ets_cfg etsrec;
642 struct ice_dcb_pfc_cfg pfc;
643 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
645 #define ICE_DCBX_MODE_CEE 0x1
646 #define ICE_DCBX_MODE_IEEE 0x2
648 #define ICE_DCBX_APPS_NON_WILLING 0x1
651 struct ice_port_info {
652 struct ice_sched_node *root; /* Root Node per Port */
653 struct ice_hw *hw; /* back pointer to HW instance */
654 u32 last_node_teid; /* scheduler last node info */
655 u16 sw_id; /* Initial switch ID belongs to port */
658 #define ICE_SCHED_PORT_STATE_INIT 0x0
659 #define ICE_SCHED_PORT_STATE_READY 0x1
661 #define ICE_LPORT_MASK 0xff
662 u16 dflt_tx_vsi_rule_id;
664 u16 dflt_rx_vsi_rule_id;
666 struct ice_fc_info fc;
667 struct ice_mac_info mac;
668 struct ice_phy_info phy;
669 struct ice_lock sched_lock; /* protect access to TXSched tree */
670 /* List contain profile ID(s) and other params per layer */
671 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
672 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
674 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
675 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
676 /* LLDP/DCBX Status */
677 u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */
682 struct ice_switch_info {
683 struct LIST_HEAD_TYPE vsi_list_map_head;
684 struct ice_sw_recipe *recp_list;
687 /* FW logging configuration */
688 struct ice_fw_log_evnt {
689 u8 cfg : 4; /* New event enables to configure */
690 u8 cur : 4; /* Current/active event enables */
693 struct ice_fw_log_cfg {
694 u8 cq_en : 1; /* FW logging is enabled via the control queue */
695 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
696 u8 actv_evnts; /* Cumulation of currently enabled log events */
698 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
699 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
700 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
701 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
702 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
705 /* Port hardware description */
709 struct ice_aqc_layer_props *layer_info;
710 struct ice_port_info *port_info;
711 /* 2D Array for each Tx Sched RL Profile type */
712 struct ice_sched_rl_profile **cir_profiles;
713 struct ice_sched_rl_profile **eir_profiles;
714 struct ice_sched_rl_profile **srl_profiles;
715 u64 debug_mask; /* BITMAP for debug mask */
716 enum ice_mac_type mac_type;
718 u16 fd_ctr_base; /* FD counter base index */
722 u16 subsystem_device_id;
723 u16 subsystem_vendor_id;
726 u8 pf_id; /* device profile info */
728 u16 max_burst_size; /* driver sets this value */
729 /* Tx Scheduler values */
730 u16 num_tx_sched_layers;
731 u16 num_tx_sched_phys_layers;
734 u8 sw_entry_point_layer;
735 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
736 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
737 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
738 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
739 u8 evb_veb; /* true for VEB, false for VEPA */
740 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
741 struct ice_bus_info bus;
742 struct ice_nvm_info nvm;
743 struct ice_hw_dev_caps dev_caps; /* device capabilities */
744 struct ice_hw_func_caps func_caps; /* function capabilities */
746 struct ice_switch_info *switch_info; /* switch filter lists */
748 /* Control Queue info */
749 struct ice_ctl_q_info adminq;
750 struct ice_ctl_q_info mailboxq;
752 u8 api_branch; /* API branch version */
753 u8 api_maj_ver; /* API major version */
754 u8 api_min_ver; /* API minor version */
755 u8 api_patch; /* API patch version */
756 u8 fw_branch; /* firmware branch version */
757 u8 fw_maj_ver; /* firmware major version */
758 u8 fw_min_ver; /* firmware minor version */
759 u8 fw_patch; /* firmware patch version */
760 u32 fw_build; /* firmware build number */
762 struct ice_fw_log_cfg fw_log;
764 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
765 * register. Used for determining the itr/intrl granularity during
768 #define ICE_MAX_AGG_BW_200G 0x0
769 #define ICE_MAX_AGG_BW_100G 0X1
770 #define ICE_MAX_AGG_BW_50G 0x2
771 #define ICE_MAX_AGG_BW_25G 0x3
772 /* ITR granularity for different speeds */
773 #define ICE_ITR_GRAN_ABOVE_25 2
774 #define ICE_ITR_GRAN_MAX_25 4
775 /* ITR granularity in 1 us */
777 /* INTRL granularity for different speeds */
778 #define ICE_INTRL_GRAN_ABOVE_25 4
779 #define ICE_INTRL_GRAN_MAX_25 8
780 /* INTRL granularity in 1 us */
783 u8 ucast_shared; /* true if VSIs can share unicast addr */
785 /* Active package version (currently active) */
786 struct ice_pkg_ver active_pkg_ver;
787 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
789 /* Driver's package ver - (from the Metadata seg) */
790 struct ice_pkg_ver pkg_ver;
791 u8 pkg_name[ICE_PKG_NAME_SIZE];
793 /* Driver's Ice package version (from the Ice seg) */
794 struct ice_pkg_ver ice_pkg_ver;
795 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
797 /* Pointer to the ice segment */
800 /* Pointer to allocated copy of pkg memory */
805 struct ice_tunnel_table tnl;
807 #define ICE_PKG_FILENAME "package_file"
808 #define ICE_PKG_FILENAME_EXT "pkg"
809 #define ICE_PKG_FILE_MAJ_VER 1
810 #define ICE_PKG_FILE_MIN_VER 0
812 /* HW block tables */
813 struct ice_blk_info blk[ICE_BLK_COUNT];
814 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
815 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
816 /* Flow Director filter info */
817 int fdir_active_fltr;
819 struct ice_lock fdir_fltr_lock; /* protect Flow Director */
820 struct LIST_HEAD_TYPE fdir_list_head;
822 /* Book-keeping of side-band filter count per flow-type.
823 * This is used to detect and handle input set changes for
824 * respective flow-type.
826 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
828 struct ice_fd_hw_prof **fdir_prof;
829 ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
830 struct ice_lock rss_locks; /* protect RSS configuration */
831 struct LIST_HEAD_TYPE rss_list_head;
834 /* Statistics collected by each port, VSI, VEB, and S-channel */
835 struct ice_eth_stats {
836 u64 rx_bytes; /* gorc */
837 u64 rx_unicast; /* uprc */
838 u64 rx_multicast; /* mprc */
839 u64 rx_broadcast; /* bprc */
840 u64 rx_discards; /* rdpc */
841 u64 rx_unknown_protocol; /* rupp */
842 u64 tx_bytes; /* gotc */
843 u64 tx_unicast; /* uptc */
844 u64 tx_multicast; /* mptc */
845 u64 tx_broadcast; /* bptc */
846 u64 tx_discards; /* tdpc */
847 u64 tx_errors; /* tepc */
852 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
853 struct ice_veb_up_stats {
854 u64 up_rx_pkts[ICE_MAX_UP];
855 u64 up_rx_bytes[ICE_MAX_UP];
856 u64 up_tx_pkts[ICE_MAX_UP];
857 u64 up_tx_bytes[ICE_MAX_UP];
860 /* Statistics collected by the MAC */
861 struct ice_hw_port_stats {
862 /* eth stats collected by the port */
863 struct ice_eth_stats eth;
864 /* additional port specific stats */
865 u64 tx_dropped_link_down; /* tdold */
866 u64 crc_errors; /* crcerrs */
867 u64 illegal_bytes; /* illerrc */
868 u64 error_bytes; /* errbc */
869 u64 mac_local_faults; /* mlfc */
870 u64 mac_remote_faults; /* mrfc */
871 u64 rx_len_errors; /* rlec */
872 u64 link_xon_rx; /* lxonrxc */
873 u64 link_xoff_rx; /* lxoffrxc */
874 u64 link_xon_tx; /* lxontxc */
875 u64 link_xoff_tx; /* lxofftxc */
876 u64 priority_xon_rx[8]; /* pxonrxc[8] */
877 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
878 u64 priority_xon_tx[8]; /* pxontxc[8] */
879 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
880 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
881 u64 rx_size_64; /* prc64 */
882 u64 rx_size_127; /* prc127 */
883 u64 rx_size_255; /* prc255 */
884 u64 rx_size_511; /* prc511 */
885 u64 rx_size_1023; /* prc1023 */
886 u64 rx_size_1522; /* prc1522 */
887 u64 rx_size_big; /* prc9522 */
888 u64 rx_undersize; /* ruc */
889 u64 rx_fragments; /* rfc */
890 u64 rx_oversize; /* roc */
891 u64 rx_jabber; /* rjc */
892 u64 tx_size_64; /* ptc64 */
893 u64 tx_size_127; /* ptc127 */
894 u64 tx_size_255; /* ptc255 */
895 u64 tx_size_511; /* ptc511 */
896 u64 tx_size_1023; /* ptc1023 */
897 u64 tx_size_1522; /* ptc1522 */
898 u64 tx_size_big; /* ptc9522 */
899 u64 mac_short_pkt_dropped; /* mspdc */
900 /* flow director stats */
905 #endif /* ADQ_SUPPORT */
908 enum ice_sw_fwd_act_type {
910 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
917 /* Checksum and Shadow RAM pointers */
918 #define ICE_SR_NVM_CTRL_WORD 0x00
919 #define ICE_SR_PHY_ANALOG_PTR 0x04
920 #define ICE_SR_OPTION_ROM_PTR 0x05
921 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
922 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
923 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
924 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
925 #define ICE_SR_EMP_IMAGE_PTR 0x0B
926 #define ICE_SR_PE_IMAGE_PTR 0x0C
927 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
928 #define ICE_SR_MNG_CFG_PTR 0x0E
929 #define ICE_SR_EMP_MODULE_PTR 0x0F
930 #define ICE_SR_PBA_FLAGS 0x15
931 #define ICE_SR_PBA_BLOCK_PTR 0x16
932 #define ICE_SR_BOOT_CFG_PTR 0x17
933 #define ICE_SR_NVM_WOL_CFG 0x19
934 #define ICE_NVM_OEM_VER_OFF 0x83
935 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
936 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
937 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
938 #define ICE_SR_NVM_MAP_VER 0x29
939 #define ICE_SR_NVM_IMAGE_VER 0x2A
940 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
941 #define ICE_SR_NVM_EETRACK_LO 0x2D
942 #define ICE_SR_NVM_EETRACK_HI 0x2E
943 #define ICE_NVM_VER_LO_SHIFT 0
944 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
945 #define ICE_NVM_VER_HI_SHIFT 12
946 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
947 #define ICE_OEM_EETRACK_ID 0xffffffff
948 #define ICE_OEM_VER_PATCH_SHIFT 0
949 #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT)
950 #define ICE_OEM_VER_BUILD_SHIFT 8
951 #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT)
952 #define ICE_OEM_VER_SHIFT 24
953 #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT)
954 #define ICE_SR_VPD_PTR 0x2F
955 #define ICE_SR_PXE_SETUP_PTR 0x30
956 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
957 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
958 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
959 #define ICE_SR_VLAN_CFG_PTR 0x37
960 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
961 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
962 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
963 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
964 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
965 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
966 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
967 #define ICE_SR_PFA_PTR 0x40
968 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
969 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
970 #define ICE_SR_NVM_BANK_SIZE 0x43
971 #define ICE_SR_1ND_OROM_BANK_PTR 0x44
972 #define ICE_SR_OROM_BANK_SIZE 0x45
973 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
974 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
975 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
977 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
978 #define ICE_SR_VPD_SIZE_WORDS 512
979 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
980 #define ICE_SR_CTRL_WORD_1_S 0x06
981 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
983 /* Shadow RAM related */
984 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
985 #define ICE_SR_BUF_ALIGNMENT 4096
986 #define ICE_SR_WORDS_IN_1KB 512
987 /* Checksum should be calculated such that after adding all the words,
988 * including the checksum word itself, the sum should be 0xBABA.
990 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
992 #define ICE_PBA_FLAG_DFLT 0xFAFA
993 /* Hash redirection LUT for VSI - maximum array size */
994 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
997 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
998 * This is needed to determine the BAR0 space for the VFs
1000 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1001 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1002 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1004 #endif /* _ICE_TYPE_H_ */