1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_ethdev_pci.h>
7 #include "base/ice_sched.h"
8 #include "ice_ethdev.h"
11 #define ICE_MAX_QP_NUM "max_queue_pair_num"
12 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
15 int ice_logtype_driver;
17 static int ice_dev_configure(struct rte_eth_dev *dev);
18 static int ice_dev_start(struct rte_eth_dev *dev);
19 static void ice_dev_stop(struct rte_eth_dev *dev);
20 static void ice_dev_close(struct rte_eth_dev *dev);
21 static int ice_dev_reset(struct rte_eth_dev *dev);
22 static void ice_dev_info_get(struct rte_eth_dev *dev,
23 struct rte_eth_dev_info *dev_info);
24 static int ice_link_update(struct rte_eth_dev *dev,
25 int wait_to_complete);
26 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
27 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
28 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
29 enum rte_vlan_type vlan_type,
31 static int ice_rss_reta_update(struct rte_eth_dev *dev,
32 struct rte_eth_rss_reta_entry64 *reta_conf,
34 static int ice_rss_reta_query(struct rte_eth_dev *dev,
35 struct rte_eth_rss_reta_entry64 *reta_conf,
37 static int ice_rss_hash_update(struct rte_eth_dev *dev,
38 struct rte_eth_rss_conf *rss_conf);
39 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
40 struct rte_eth_rss_conf *rss_conf);
41 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
44 static int ice_macaddr_set(struct rte_eth_dev *dev,
45 struct ether_addr *mac_addr);
46 static int ice_macaddr_add(struct rte_eth_dev *dev,
47 struct ether_addr *mac_addr,
48 __rte_unused uint32_t index,
50 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
51 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
53 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
55 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
57 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
58 uint16_t pvid, int on);
60 static const struct rte_pci_id pci_id_ice_map[] = {
61 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
62 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
63 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
64 { .vendor_id = 0, /* sentinel */ },
67 static const struct eth_dev_ops ice_eth_dev_ops = {
68 .dev_configure = ice_dev_configure,
69 .dev_start = ice_dev_start,
70 .dev_stop = ice_dev_stop,
71 .dev_close = ice_dev_close,
72 .dev_reset = ice_dev_reset,
73 .rx_queue_start = ice_rx_queue_start,
74 .rx_queue_stop = ice_rx_queue_stop,
75 .tx_queue_start = ice_tx_queue_start,
76 .tx_queue_stop = ice_tx_queue_stop,
77 .rx_queue_setup = ice_rx_queue_setup,
78 .rx_queue_release = ice_rx_queue_release,
79 .tx_queue_setup = ice_tx_queue_setup,
80 .tx_queue_release = ice_tx_queue_release,
81 .dev_infos_get = ice_dev_info_get,
82 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
83 .link_update = ice_link_update,
84 .mtu_set = ice_mtu_set,
85 .mac_addr_set = ice_macaddr_set,
86 .mac_addr_add = ice_macaddr_add,
87 .mac_addr_remove = ice_macaddr_remove,
88 .vlan_filter_set = ice_vlan_filter_set,
89 .vlan_offload_set = ice_vlan_offload_set,
90 .vlan_tpid_set = ice_vlan_tpid_set,
91 .reta_update = ice_rss_reta_update,
92 .reta_query = ice_rss_reta_query,
93 .rss_hash_update = ice_rss_hash_update,
94 .rss_hash_conf_get = ice_rss_hash_conf_get,
95 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
96 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
97 .fw_version_get = ice_fw_version_get,
98 .vlan_pvid_set = ice_vlan_pvid_set,
99 .rxq_info_get = ice_rxq_info_get,
100 .txq_info_get = ice_txq_info_get,
101 .rx_queue_count = ice_rx_queue_count,
105 ice_init_controlq_parameter(struct ice_hw *hw)
107 /* fields for adminq */
108 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
109 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
110 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
111 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
113 /* fields for mailboxq, DPDK used as PF host */
114 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
115 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
116 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
117 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
121 ice_check_qp_num(const char *key, const char *qp_value,
122 __rte_unused void *opaque)
127 while (isblank(*qp_value))
130 num = strtoul(qp_value, &end, 10);
132 if (!num || (*end == '-') || errno) {
133 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
143 ice_config_max_queue_pair_num(struct rte_devargs *devargs)
145 struct rte_kvargs *kvlist;
146 const char *queue_num_key = ICE_MAX_QP_NUM;
152 kvlist = rte_kvargs_parse(devargs->args, NULL);
156 if (!rte_kvargs_count(kvlist, queue_num_key)) {
157 rte_kvargs_free(kvlist);
161 if (rte_kvargs_process(kvlist, queue_num_key,
162 ice_check_qp_num, NULL) < 0) {
163 rte_kvargs_free(kvlist);
166 ret = rte_kvargs_process(kvlist, queue_num_key,
167 ice_check_qp_num, NULL);
168 rte_kvargs_free(kvlist);
174 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
177 struct pool_entry *entry;
182 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
185 "Failed to allocate memory for resource pool");
189 /* queue heap initialize */
190 pool->num_free = num;
193 LIST_INIT(&pool->alloc_list);
194 LIST_INIT(&pool->free_list);
196 /* Initialize element */
200 LIST_INSERT_HEAD(&pool->free_list, entry, next);
205 ice_res_pool_alloc(struct ice_res_pool_info *pool,
208 struct pool_entry *entry, *valid_entry;
211 PMD_INIT_LOG(ERR, "Invalid parameter");
215 if (pool->num_free < num) {
216 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
217 num, pool->num_free);
222 /* Lookup in free list and find most fit one */
223 LIST_FOREACH(entry, &pool->free_list, next) {
224 if (entry->len >= num) {
226 if (entry->len == num) {
231 valid_entry->len > entry->len)
236 /* Not find one to satisfy the request, return */
238 PMD_INIT_LOG(ERR, "No valid entry found");
242 * The entry have equal queue number as requested,
243 * remove it from alloc_list.
245 if (valid_entry->len == num) {
246 LIST_REMOVE(valid_entry, next);
249 * The entry have more numbers than requested,
250 * create a new entry for alloc_list and minus its
251 * queue base and number in free_list.
253 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
256 "Failed to allocate memory for "
260 entry->base = valid_entry->base;
262 valid_entry->base += num;
263 valid_entry->len -= num;
267 /* Insert it into alloc list, not sorted */
268 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
270 pool->num_free -= valid_entry->len;
271 pool->num_alloc += valid_entry->len;
273 return valid_entry->base + pool->base;
277 ice_res_pool_destroy(struct ice_res_pool_info *pool)
279 struct pool_entry *entry, *next_entry;
284 for (entry = LIST_FIRST(&pool->alloc_list);
285 entry && (next_entry = LIST_NEXT(entry, next), 1);
286 entry = next_entry) {
287 LIST_REMOVE(entry, next);
291 for (entry = LIST_FIRST(&pool->free_list);
292 entry && (next_entry = LIST_NEXT(entry, next), 1);
293 entry = next_entry) {
294 LIST_REMOVE(entry, next);
301 LIST_INIT(&pool->alloc_list);
302 LIST_INIT(&pool->free_list);
306 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
308 /* Set VSI LUT selection */
309 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
310 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
311 /* Set Hash scheme */
312 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
313 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
315 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
318 static enum ice_status
319 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
320 struct ice_aqc_vsi_props *info,
321 uint8_t enabled_tcmap)
323 uint16_t bsf, qp_idx;
325 /* default tc 0 now. Multi-TC supporting need to be done later.
326 * Configure TC and queue mapping parameters, for enabled TC,
327 * allocate qpnum_per_tc queues to this traffic.
329 if (enabled_tcmap != 0x01) {
330 PMD_INIT_LOG(ERR, "only TC0 is supported");
334 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
335 bsf = rte_bsf32(vsi->nb_qps);
336 /* Adjust the queue number to actual queues that can be applied */
337 vsi->nb_qps = 0x1 << bsf;
340 /* Set tc and queue mapping with VSI */
341 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
342 ICE_AQ_VSI_TC_Q_OFFSET_S) |
343 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
345 /* Associate queue number with VSI */
346 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
347 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
348 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
349 info->valid_sections |=
350 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
351 /* Set the info.ingress_table and info.egress_table
352 * for UP translate table. Now just set it to 1:1 map by default
353 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
355 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
356 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
357 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
358 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
363 ice_init_mac_address(struct rte_eth_dev *dev)
365 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
367 if (!is_unicast_ether_addr
368 ((struct ether_addr *)hw->port_info[0].mac.lan_addr)) {
369 PMD_INIT_LOG(ERR, "Invalid MAC address");
373 ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.lan_addr,
374 (struct ether_addr *)hw->port_info[0].mac.perm_addr);
376 dev->data->mac_addrs = rte_zmalloc(NULL, sizeof(struct ether_addr), 0);
377 if (!dev->data->mac_addrs) {
379 "Failed to allocate memory to store mac address");
382 /* store it to dev data */
383 ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.perm_addr,
384 &dev->data->mac_addrs[0]);
388 /* Find out specific MAC filter */
389 static struct ice_mac_filter *
390 ice_find_mac_filter(struct ice_vsi *vsi, struct ether_addr *macaddr)
392 struct ice_mac_filter *f;
394 TAILQ_FOREACH(f, &vsi->mac_list, next) {
395 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
403 ice_add_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr)
405 struct ice_fltr_list_entry *m_list_itr = NULL;
406 struct ice_mac_filter *f;
407 struct LIST_HEAD_TYPE list_head;
408 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
411 /* If it's added and configured, return */
412 f = ice_find_mac_filter(vsi, mac_addr);
414 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
418 INIT_LIST_HEAD(&list_head);
420 m_list_itr = (struct ice_fltr_list_entry *)
421 ice_malloc(hw, sizeof(*m_list_itr));
426 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
427 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
428 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
429 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
430 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
431 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
432 m_list_itr->fltr_info.vsi_handle = vsi->idx;
434 LIST_ADD(&m_list_itr->list_entry, &list_head);
437 ret = ice_add_mac(hw, &list_head);
438 if (ret != ICE_SUCCESS) {
439 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
443 /* Add the mac addr into mac list */
444 f = rte_zmalloc(NULL, sizeof(*f), 0);
446 PMD_DRV_LOG(ERR, "failed to allocate memory");
450 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
451 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
457 rte_free(m_list_itr);
462 ice_remove_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr)
464 struct ice_fltr_list_entry *m_list_itr = NULL;
465 struct ice_mac_filter *f;
466 struct LIST_HEAD_TYPE list_head;
467 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
470 /* Can't find it, return an error */
471 f = ice_find_mac_filter(vsi, mac_addr);
475 INIT_LIST_HEAD(&list_head);
477 m_list_itr = (struct ice_fltr_list_entry *)
478 ice_malloc(hw, sizeof(*m_list_itr));
483 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
484 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
485 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
486 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
487 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
488 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
489 m_list_itr->fltr_info.vsi_handle = vsi->idx;
491 LIST_ADD(&m_list_itr->list_entry, &list_head);
493 /* remove the mac filter */
494 ret = ice_remove_mac(hw, &list_head);
495 if (ret != ICE_SUCCESS) {
496 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
501 /* Remove the mac addr from mac list */
502 TAILQ_REMOVE(&vsi->mac_list, f, next);
508 rte_free(m_list_itr);
512 /* Find out specific VLAN filter */
513 static struct ice_vlan_filter *
514 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
516 struct ice_vlan_filter *f;
518 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
519 if (vlan_id == f->vlan_info.vlan_id)
527 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
529 struct ice_fltr_list_entry *v_list_itr = NULL;
530 struct ice_vlan_filter *f;
531 struct LIST_HEAD_TYPE list_head;
532 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
535 if (!vsi || vlan_id > ETHER_MAX_VLAN_ID)
538 /* If it's added and configured, return. */
539 f = ice_find_vlan_filter(vsi, vlan_id);
541 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
545 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
548 INIT_LIST_HEAD(&list_head);
550 v_list_itr = (struct ice_fltr_list_entry *)
551 ice_malloc(hw, sizeof(*v_list_itr));
556 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
557 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
558 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
559 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
560 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
561 v_list_itr->fltr_info.vsi_handle = vsi->idx;
563 LIST_ADD(&v_list_itr->list_entry, &list_head);
566 ret = ice_add_vlan(hw, &list_head);
567 if (ret != ICE_SUCCESS) {
568 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
573 /* Add vlan into vlan list */
574 f = rte_zmalloc(NULL, sizeof(*f), 0);
576 PMD_DRV_LOG(ERR, "failed to allocate memory");
580 f->vlan_info.vlan_id = vlan_id;
581 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
587 rte_free(v_list_itr);
592 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
594 struct ice_fltr_list_entry *v_list_itr = NULL;
595 struct ice_vlan_filter *f;
596 struct LIST_HEAD_TYPE list_head;
597 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
601 * Vlan 0 is the generic filter for untagged packets
602 * and can't be removed.
604 if (!vsi || vlan_id == 0 || vlan_id > ETHER_MAX_VLAN_ID)
607 /* Can't find it, return an error */
608 f = ice_find_vlan_filter(vsi, vlan_id);
612 INIT_LIST_HEAD(&list_head);
614 v_list_itr = (struct ice_fltr_list_entry *)
615 ice_malloc(hw, sizeof(*v_list_itr));
621 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
622 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
623 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
624 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
625 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
626 v_list_itr->fltr_info.vsi_handle = vsi->idx;
628 LIST_ADD(&v_list_itr->list_entry, &list_head);
630 /* remove the vlan filter */
631 ret = ice_remove_vlan(hw, &list_head);
632 if (ret != ICE_SUCCESS) {
633 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
638 /* Remove the vlan id from vlan list */
639 TAILQ_REMOVE(&vsi->vlan_list, f, next);
645 rte_free(v_list_itr);
650 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
652 struct ice_mac_filter *m_f;
653 struct ice_vlan_filter *v_f;
656 if (!vsi || !vsi->mac_num)
659 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
660 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
661 if (ret != ICE_SUCCESS) {
667 if (vsi->vlan_num == 0)
670 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
671 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
672 if (ret != ICE_SUCCESS) {
683 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
685 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
686 struct ice_vsi_ctx ctxt;
690 /* Check if it has been already on or off */
691 if (vsi->info.valid_sections &
692 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
694 if ((vsi->info.outer_tag_flags &
695 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
696 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
697 return 0; /* already on */
699 if (!(vsi->info.outer_tag_flags &
700 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
701 return 0; /* already off */
706 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
709 /* clear global insertion and use per packet insertion */
710 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
711 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
712 vsi->info.outer_tag_flags |= qinq_flags;
713 /* use default vlan type 0x8100 */
714 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
715 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
716 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
717 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
718 ctxt.info.valid_sections =
719 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
720 ctxt.vsi_num = vsi->vsi_id;
721 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
724 "Update VSI failed to %s qinq stripping",
725 on ? "enable" : "disable");
729 vsi->info.valid_sections |=
730 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
736 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
738 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
739 struct ice_vsi_ctx ctxt;
743 /* Check if it has been already on or off */
744 if (vsi->info.valid_sections &
745 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
747 if ((vsi->info.outer_tag_flags &
748 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
749 ICE_AQ_VSI_OUTER_TAG_COPY)
750 return 0; /* already on */
752 if ((vsi->info.outer_tag_flags &
753 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
754 ICE_AQ_VSI_OUTER_TAG_NOTHING)
755 return 0; /* already off */
760 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
762 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
763 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
764 vsi->info.outer_tag_flags |= qinq_flags;
765 /* use default vlan type 0x8100 */
766 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
767 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
768 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
769 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
770 ctxt.info.valid_sections =
771 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
772 ctxt.vsi_num = vsi->vsi_id;
773 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
776 "Update VSI failed to %s qinq stripping",
777 on ? "enable" : "disable");
781 vsi->info.valid_sections |=
782 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
788 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
792 ret = ice_vsi_config_qinq_stripping(vsi, on);
794 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
796 ret = ice_vsi_config_qinq_insertion(vsi, on);
798 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
805 ice_pf_enable_irq0(struct ice_hw *hw)
807 /* reset the registers */
808 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
809 ICE_READ_REG(hw, PFINT_OICR);
812 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
813 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
814 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
816 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
817 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
818 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
819 PFINT_OICR_CTL_ITR_INDX_M) |
820 PFINT_OICR_CTL_CAUSE_ENA_M);
822 ICE_WRITE_REG(hw, PFINT_FW_CTL,
823 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
824 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
825 PFINT_FW_CTL_ITR_INDX_M) |
826 PFINT_FW_CTL_CAUSE_ENA_M);
828 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
831 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
832 GLINT_DYN_CTL_INTENA_M |
833 GLINT_DYN_CTL_CLEARPBA_M |
834 GLINT_DYN_CTL_ITR_INDX_M);
841 ice_pf_disable_irq0(struct ice_hw *hw)
843 /* Disable all interrupt types */
844 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
850 ice_handle_aq_msg(struct rte_eth_dev *dev)
852 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
853 struct ice_ctl_q_info *cq = &hw->adminq;
854 struct ice_rq_event_info event;
855 uint16_t pending, opcode;
858 event.buf_len = ICE_AQ_MAX_BUF_LEN;
859 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
860 if (!event.msg_buf) {
861 PMD_DRV_LOG(ERR, "Failed to allocate mem");
867 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
869 if (ret != ICE_SUCCESS) {
871 "Failed to read msg from AdminQ, "
873 hw->adminq.sq_last_status);
876 opcode = rte_le_to_cpu_16(event.desc.opcode);
879 case ice_aqc_opc_get_link_status:
880 ret = ice_link_update(dev, 0);
882 _rte_eth_dev_callback_process
883 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
886 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
891 rte_free(event.msg_buf);
896 * Interrupt handler triggered by NIC for handling
897 * specific interrupt.
900 * Pointer to interrupt handle.
902 * The address of parameter (struct rte_eth_dev *) regsitered before.
908 ice_interrupt_handler(void *param)
910 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
911 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
921 /* Disable interrupt */
922 ice_pf_disable_irq0(hw);
924 /* read out interrupt causes */
925 oicr = ICE_READ_REG(hw, PFINT_OICR);
927 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
930 /* No interrupt event indicated */
931 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
932 PMD_DRV_LOG(INFO, "No interrupt event");
937 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
938 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
939 ice_handle_aq_msg(dev);
942 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
943 PMD_DRV_LOG(INFO, "OICR: link state change event");
944 ice_link_update(dev, 0);
948 if (oicr & PFINT_OICR_MAL_DETECT_M) {
949 PMD_DRV_LOG(WARNING, "OICR: MDD event");
950 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
951 if (reg & GL_MDET_TX_PQM_VALID_M) {
952 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
953 GL_MDET_TX_PQM_PF_NUM_S;
954 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
955 GL_MDET_TX_PQM_MAL_TYPE_S;
956 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
957 GL_MDET_TX_PQM_QNUM_S;
959 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
960 "%d by PQM on TX queue %d PF# %d",
961 event, queue, pf_num);
964 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
965 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
966 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
967 GL_MDET_TX_TCLAN_PF_NUM_S;
968 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
969 GL_MDET_TX_TCLAN_MAL_TYPE_S;
970 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
971 GL_MDET_TX_TCLAN_QNUM_S;
973 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
974 "%d by TCLAN on TX queue %d PF# %d",
975 event, queue, pf_num);
979 /* Enable interrupt */
980 ice_pf_enable_irq0(hw);
981 rte_intr_enable(dev->intr_handle);
984 /* Initialize SW parameters of PF */
986 ice_pf_sw_init(struct rte_eth_dev *dev)
988 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
989 struct ice_hw *hw = ICE_PF_TO_HW(pf);
991 if (ice_config_max_queue_pair_num(dev->device->devargs) > 0)
993 ice_config_max_queue_pair_num(dev->device->devargs);
996 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
997 hw->func_caps.common_cap.num_rxq);
999 pf->lan_nb_qps = pf->lan_nb_qp_max;
1004 static struct ice_vsi *
1005 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1007 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1008 struct ice_vsi *vsi = NULL;
1009 struct ice_vsi_ctx vsi_ctx;
1011 struct ether_addr broadcast = {
1012 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1013 struct ether_addr mac_addr;
1014 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1015 uint8_t tc_bitmap = 0x1;
1017 /* hw->num_lports = 1 in NIC mode */
1018 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1022 vsi->idx = pf->next_vsi_idx;
1025 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1026 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1027 vsi->vlan_anti_spoof_on = 0;
1028 vsi->vlan_filter_on = 1;
1029 TAILQ_INIT(&vsi->mac_list);
1030 TAILQ_INIT(&vsi->vlan_list);
1032 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1033 /* base_queue in used in queue mapping of VSI add/update command.
1034 * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1035 * cases in the first stage. Only Main VSI.
1037 vsi->base_queue = 0;
1040 vsi->nb_qps = pf->lan_nb_qps;
1041 ice_vsi_config_default_rss(&vsi_ctx.info);
1042 vsi_ctx.alloc_from_pool = true;
1043 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1044 /* switch_id is queried by get_switch_config aq, which is done
1047 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1048 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1049 /* Allow all untagged or tagged packets */
1050 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1051 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1052 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1053 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1054 /* Enable VLAN/UP trip */
1055 ret = ice_vsi_config_tc_queue_mapping(vsi,
1060 "tc queue mapping with vsi failed, "
1068 /* for other types of VSI */
1069 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1073 /* VF has MSIX interrupt in VF range, don't allocate here */
1074 if (type == ICE_VSI_PF) {
1075 ret = ice_res_pool_alloc(&pf->msix_pool,
1076 RTE_MIN(vsi->nb_qps,
1077 RTE_MAX_RXTX_INTR_VEC_ID));
1079 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1082 vsi->msix_intr = ret;
1083 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1088 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1089 if (ret != ICE_SUCCESS) {
1090 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1093 /* store vsi information is SW structure */
1094 vsi->vsi_id = vsi_ctx.vsi_num;
1095 vsi->info = vsi_ctx.info;
1096 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1097 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1099 /* MAC configuration */
1100 rte_memcpy(pf->dev_addr.addr_bytes,
1101 hw->port_info->mac.perm_addr,
1104 rte_memcpy(&mac_addr, &pf->dev_addr, ETHER_ADDR_LEN);
1105 ret = ice_add_mac_filter(vsi, &mac_addr);
1106 if (ret != ICE_SUCCESS)
1107 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1109 rte_memcpy(&mac_addr, &broadcast, ETHER_ADDR_LEN);
1110 ret = ice_add_mac_filter(vsi, &mac_addr);
1111 if (ret != ICE_SUCCESS)
1112 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1114 /* At the beginning, only TC0. */
1115 /* What we need here is the maximam number of the TX queues.
1116 * Currently vsi->nb_qps means it.
1117 * Correct it if any change.
1119 max_txqs[0] = vsi->nb_qps;
1120 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1121 tc_bitmap, max_txqs);
1122 if (ret != ICE_SUCCESS)
1123 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1133 ice_pf_setup(struct ice_pf *pf)
1135 struct ice_vsi *vsi;
1137 /* Clear all stats counters */
1138 pf->offset_loaded = FALSE;
1139 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1140 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1141 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1142 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1144 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1146 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1156 ice_dev_init(struct rte_eth_dev *dev)
1158 struct rte_pci_device *pci_dev;
1159 struct rte_intr_handle *intr_handle;
1160 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1161 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1162 struct ice_vsi *vsi;
1165 dev->dev_ops = &ice_eth_dev_ops;
1166 dev->rx_pkt_burst = ice_recv_pkts;
1167 dev->tx_pkt_burst = ice_xmit_pkts;
1168 dev->tx_pkt_prepare = ice_prep_pkts;
1170 ice_set_default_ptype_table(dev);
1171 pci_dev = RTE_DEV_TO_PCI(dev->device);
1172 intr_handle = &pci_dev->intr_handle;
1174 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1175 pf->adapter->eth_dev = dev;
1176 pf->dev_data = dev->data;
1177 hw->back = pf->adapter;
1178 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1179 hw->vendor_id = pci_dev->id.vendor_id;
1180 hw->device_id = pci_dev->id.device_id;
1181 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1182 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1183 hw->bus.device = pci_dev->addr.devid;
1184 hw->bus.func = pci_dev->addr.function;
1186 ice_init_controlq_parameter(hw);
1188 ret = ice_init_hw(hw);
1190 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1194 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1195 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1196 hw->api_maj_ver, hw->api_min_ver);
1198 ice_pf_sw_init(dev);
1199 ret = ice_init_mac_address(dev);
1201 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1205 ret = ice_res_pool_init(&pf->msix_pool, 1,
1206 hw->func_caps.common_cap.num_msix_vectors - 1);
1208 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1209 goto err_msix_pool_init;
1212 ret = ice_pf_setup(pf);
1214 PMD_INIT_LOG(ERR, "Failed to setup PF");
1220 /* Disable double vlan by default */
1221 ice_vsi_config_double_vlan(vsi, FALSE);
1223 /* register callback func to eal lib */
1224 rte_intr_callback_register(intr_handle,
1225 ice_interrupt_handler, dev);
1227 ice_pf_enable_irq0(hw);
1229 /* enable uio intr after callback register */
1230 rte_intr_enable(intr_handle);
1235 ice_res_pool_destroy(&pf->msix_pool);
1237 rte_free(dev->data->mac_addrs);
1239 ice_sched_cleanup_all(hw);
1240 rte_free(hw->port_info);
1241 ice_shutdown_all_ctrlq(hw);
1247 ice_release_vsi(struct ice_vsi *vsi)
1250 struct ice_vsi_ctx vsi_ctx;
1251 enum ice_status ret;
1256 hw = ICE_VSI_TO_HW(vsi);
1258 ice_remove_all_mac_vlan_filters(vsi);
1260 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1262 vsi_ctx.vsi_num = vsi->vsi_id;
1263 vsi_ctx.info = vsi->info;
1264 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
1265 if (ret != ICE_SUCCESS) {
1266 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
1276 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
1278 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1279 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1280 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1281 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1282 uint16_t msix_intr, i;
1284 /* disable interrupt and also clear all the exist config */
1285 for (i = 0; i < vsi->nb_qps; i++) {
1286 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1287 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1291 if (rte_intr_allow_others(intr_handle))
1293 for (i = 0; i < vsi->nb_msix; i++) {
1294 msix_intr = vsi->msix_intr + i;
1295 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1296 GLINT_DYN_CTL_WB_ON_ITR_M);
1300 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1304 ice_dev_stop(struct rte_eth_dev *dev)
1306 struct rte_eth_dev_data *data = dev->data;
1307 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1308 struct ice_vsi *main_vsi = pf->main_vsi;
1309 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1310 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1313 /* avoid stopping again */
1314 if (pf->adapter_stopped)
1317 /* stop and clear all Rx queues */
1318 for (i = 0; i < data->nb_rx_queues; i++)
1319 ice_rx_queue_stop(dev, i);
1321 /* stop and clear all Tx queues */
1322 for (i = 0; i < data->nb_tx_queues; i++)
1323 ice_tx_queue_stop(dev, i);
1325 /* disable all queue interrupts */
1326 ice_vsi_disable_queues_intr(main_vsi);
1328 /* Clear all queues and release mbufs */
1329 ice_clear_queues(dev);
1331 /* Clean datapath event and queue/vec mapping */
1332 rte_intr_efd_disable(intr_handle);
1333 if (intr_handle->intr_vec) {
1334 rte_free(intr_handle->intr_vec);
1335 intr_handle->intr_vec = NULL;
1338 pf->adapter_stopped = true;
1342 ice_dev_close(struct rte_eth_dev *dev)
1344 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1345 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349 /* release all queue resource */
1350 ice_free_queues(dev);
1352 ice_res_pool_destroy(&pf->msix_pool);
1353 ice_release_vsi(pf->main_vsi);
1355 ice_shutdown_all_ctrlq(hw);
1359 ice_dev_uninit(struct rte_eth_dev *dev)
1361 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1362 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1363 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1364 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1368 dev->dev_ops = NULL;
1369 dev->rx_pkt_burst = NULL;
1370 dev->tx_pkt_burst = NULL;
1372 rte_free(dev->data->mac_addrs);
1373 dev->data->mac_addrs = NULL;
1375 /* disable uio intr before callback unregister */
1376 rte_intr_disable(intr_handle);
1378 /* register callback func to eal lib */
1379 rte_intr_callback_unregister(intr_handle,
1380 ice_interrupt_handler, dev);
1382 ice_release_vsi(pf->main_vsi);
1383 ice_sched_cleanup_all(hw);
1384 rte_free(hw->port_info);
1385 ice_shutdown_all_ctrlq(hw);
1391 ice_dev_configure(__rte_unused struct rte_eth_dev *dev)
1393 struct ice_adapter *ad =
1394 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1396 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1397 * bulk allocation or vector Rx preconditions we will reset it.
1399 ad->rx_bulk_alloc_allowed = true;
1400 ad->tx_simple_allowed = true;
1405 static int ice_init_rss(struct ice_pf *pf)
1407 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1408 struct ice_vsi *vsi = pf->main_vsi;
1409 struct rte_eth_dev *dev = pf->adapter->eth_dev;
1410 struct rte_eth_rss_conf *rss_conf;
1411 struct ice_aqc_get_set_rss_keys key;
1415 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1416 nb_q = dev->data->nb_rx_queues;
1417 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1418 vsi->rss_lut_size = hw->func_caps.common_cap.rss_table_size;
1421 vsi->rss_key = rte_zmalloc(NULL,
1422 vsi->rss_key_size, 0);
1424 vsi->rss_lut = rte_zmalloc(NULL,
1425 vsi->rss_lut_size, 0);
1427 /* configure RSS key */
1428 if (!rss_conf->rss_key) {
1429 /* Calculate the default hash key */
1430 for (i = 0; i <= vsi->rss_key_size; i++)
1431 vsi->rss_key[i] = (uint8_t)rte_rand();
1433 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1434 RTE_MIN(rss_conf->rss_key_len,
1435 vsi->rss_key_size));
1437 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1438 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1442 /* init RSS LUT table */
1443 for (i = 0; i < vsi->rss_lut_size; i++)
1444 vsi->rss_lut[i] = i % nb_q;
1446 ret = ice_aq_set_rss_lut(hw, vsi->idx,
1447 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1448 vsi->rss_lut, vsi->rss_lut_size);
1456 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
1457 int base_queue, int nb_queue)
1459 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1460 uint32_t val, val_tx;
1463 for (i = 0; i < nb_queue; i++) {
1465 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
1466 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
1467 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
1468 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
1470 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
1471 base_queue + i, msix_vect);
1472 /* set ITR0 value */
1473 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
1474 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
1475 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
1480 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
1482 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1483 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1484 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1485 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1486 uint16_t msix_vect = vsi->msix_intr;
1487 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1488 uint16_t queue_idx = 0;
1492 /* clear Rx/Tx queue interrupt */
1493 for (i = 0; i < vsi->nb_used_qps; i++) {
1494 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1495 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1498 /* PF bind interrupt */
1499 if (rte_intr_dp_is_en(intr_handle)) {
1504 for (i = 0; i < vsi->nb_used_qps; i++) {
1506 if (!rte_intr_allow_others(intr_handle))
1507 msix_vect = ICE_MISC_VEC_ID;
1509 /* uio mapping all queue to one msix_vect */
1510 __vsi_queues_bind_intr(vsi, msix_vect,
1511 vsi->base_queue + i,
1512 vsi->nb_used_qps - i);
1514 for (; !!record && i < vsi->nb_used_qps; i++)
1515 intr_handle->intr_vec[queue_idx + i] =
1520 /* vfio 1:1 queue/msix_vect mapping */
1521 __vsi_queues_bind_intr(vsi, msix_vect,
1522 vsi->base_queue + i, 1);
1525 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1533 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
1535 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1536 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1537 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1538 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1539 uint16_t msix_intr, i;
1541 if (rte_intr_allow_others(intr_handle))
1542 for (i = 0; i < vsi->nb_used_qps; i++) {
1543 msix_intr = vsi->msix_intr + i;
1544 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1545 GLINT_DYN_CTL_INTENA_M |
1546 GLINT_DYN_CTL_CLEARPBA_M |
1547 GLINT_DYN_CTL_ITR_INDX_M |
1548 GLINT_DYN_CTL_WB_ON_ITR_M);
1551 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1552 GLINT_DYN_CTL_INTENA_M |
1553 GLINT_DYN_CTL_CLEARPBA_M |
1554 GLINT_DYN_CTL_ITR_INDX_M |
1555 GLINT_DYN_CTL_WB_ON_ITR_M);
1559 ice_rxq_intr_setup(struct rte_eth_dev *dev)
1561 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1562 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1563 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1564 struct ice_vsi *vsi = pf->main_vsi;
1565 uint32_t intr_vector = 0;
1567 rte_intr_disable(intr_handle);
1569 /* check and configure queue intr-vector mapping */
1570 if ((rte_intr_cap_multiple(intr_handle) ||
1571 !RTE_ETH_DEV_SRIOV(dev).active) &&
1572 dev->data->dev_conf.intr_conf.rxq != 0) {
1573 intr_vector = dev->data->nb_rx_queues;
1574 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
1575 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
1576 ICE_MAX_INTR_QUEUE_NUM);
1579 if (rte_intr_efd_enable(intr_handle, intr_vector))
1583 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1584 intr_handle->intr_vec =
1585 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
1587 if (!intr_handle->intr_vec) {
1589 "Failed to allocate %d rx_queues intr_vec",
1590 dev->data->nb_rx_queues);
1595 /* Map queues with MSIX interrupt */
1596 vsi->nb_used_qps = dev->data->nb_rx_queues;
1597 ice_vsi_queues_bind_intr(vsi);
1599 /* Enable interrupts for all the queues */
1600 ice_vsi_enable_queues_intr(vsi);
1602 rte_intr_enable(intr_handle);
1608 ice_dev_start(struct rte_eth_dev *dev)
1610 struct rte_eth_dev_data *data = dev->data;
1611 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1612 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1613 uint16_t nb_rxq = 0;
1617 /* program Tx queues' context in hardware */
1618 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
1619 ret = ice_tx_queue_start(dev, nb_txq);
1621 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
1626 /* program Rx queues' context in hardware*/
1627 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
1628 ret = ice_rx_queue_start(dev, nb_rxq);
1630 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
1635 ret = ice_init_rss(pf);
1637 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
1641 ice_set_rx_function(dev);
1643 /* enable Rx interrput and mapping Rx queue to interrupt vector */
1644 if (ice_rxq_intr_setup(dev))
1647 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
1648 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
1649 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
1650 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
1651 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
1652 ICE_AQ_LINK_EVENT_AN_COMPLETED |
1653 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
1655 if (ret != ICE_SUCCESS)
1656 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1658 /* Call get_link_info aq commond to enable/disable LSE */
1659 ice_link_update(dev, 0);
1661 pf->adapter_stopped = false;
1665 /* stop the started queues if failed to start all queues */
1667 for (i = 0; i < nb_rxq; i++)
1668 ice_rx_queue_stop(dev, i);
1670 for (i = 0; i < nb_txq; i++)
1671 ice_tx_queue_stop(dev, i);
1677 ice_dev_reset(struct rte_eth_dev *dev)
1681 if (dev->data->sriov.active)
1684 ret = ice_dev_uninit(dev);
1686 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
1690 ret = ice_dev_init(dev);
1692 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
1700 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1702 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1703 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704 struct ice_vsi *vsi = pf->main_vsi;
1705 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1707 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
1708 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
1709 dev_info->max_rx_queues = vsi->nb_qps;
1710 dev_info->max_tx_queues = vsi->nb_qps;
1711 dev_info->max_mac_addrs = vsi->max_macaddrs;
1712 dev_info->max_vfs = pci_dev->max_vfs;
1714 dev_info->rx_offload_capa =
1715 DEV_RX_OFFLOAD_VLAN_STRIP |
1716 DEV_RX_OFFLOAD_IPV4_CKSUM |
1717 DEV_RX_OFFLOAD_UDP_CKSUM |
1718 DEV_RX_OFFLOAD_TCP_CKSUM |
1719 DEV_RX_OFFLOAD_QINQ_STRIP |
1720 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1721 DEV_RX_OFFLOAD_VLAN_EXTEND |
1722 DEV_RX_OFFLOAD_JUMBO_FRAME |
1723 DEV_RX_OFFLOAD_KEEP_CRC |
1724 DEV_RX_OFFLOAD_VLAN_FILTER;
1725 dev_info->tx_offload_capa =
1726 DEV_TX_OFFLOAD_VLAN_INSERT |
1727 DEV_TX_OFFLOAD_QINQ_INSERT |
1728 DEV_TX_OFFLOAD_IPV4_CKSUM |
1729 DEV_TX_OFFLOAD_UDP_CKSUM |
1730 DEV_TX_OFFLOAD_TCP_CKSUM |
1731 DEV_TX_OFFLOAD_SCTP_CKSUM |
1732 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1733 DEV_TX_OFFLOAD_TCP_TSO |
1734 DEV_TX_OFFLOAD_MULTI_SEGS;
1735 dev_info->rx_queue_offload_capa = 0;
1736 dev_info->tx_queue_offload_capa = 0;
1738 dev_info->reta_size = hw->func_caps.common_cap.rss_table_size;
1739 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
1740 dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL;
1742 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1744 .pthresh = ICE_DEFAULT_RX_PTHRESH,
1745 .hthresh = ICE_DEFAULT_RX_HTHRESH,
1746 .wthresh = ICE_DEFAULT_RX_WTHRESH,
1748 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
1753 dev_info->default_txconf = (struct rte_eth_txconf) {
1755 .pthresh = ICE_DEFAULT_TX_PTHRESH,
1756 .hthresh = ICE_DEFAULT_TX_HTHRESH,
1757 .wthresh = ICE_DEFAULT_TX_WTHRESH,
1759 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
1760 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
1764 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1765 .nb_max = ICE_MAX_RING_DESC,
1766 .nb_min = ICE_MIN_RING_DESC,
1767 .nb_align = ICE_ALIGN_RING_DESC,
1770 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1771 .nb_max = ICE_MAX_RING_DESC,
1772 .nb_min = ICE_MIN_RING_DESC,
1773 .nb_align = ICE_ALIGN_RING_DESC,
1776 dev_info->speed_capa = ETH_LINK_SPEED_10M |
1777 ETH_LINK_SPEED_100M |
1779 ETH_LINK_SPEED_2_5G |
1781 ETH_LINK_SPEED_10G |
1782 ETH_LINK_SPEED_20G |
1783 ETH_LINK_SPEED_25G |
1786 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
1787 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
1789 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
1790 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
1791 dev_info->default_rxportconf.nb_queues = 1;
1792 dev_info->default_txportconf.nb_queues = 1;
1793 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
1794 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
1798 ice_atomic_read_link_status(struct rte_eth_dev *dev,
1799 struct rte_eth_link *link)
1801 struct rte_eth_link *dst = link;
1802 struct rte_eth_link *src = &dev->data->dev_link;
1804 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1805 *(uint64_t *)src) == 0)
1812 ice_atomic_write_link_status(struct rte_eth_dev *dev,
1813 struct rte_eth_link *link)
1815 struct rte_eth_link *dst = &dev->data->dev_link;
1816 struct rte_eth_link *src = link;
1818 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1819 *(uint64_t *)src) == 0)
1826 ice_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1828 #define CHECK_INTERVAL 100 /* 100ms */
1829 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1830 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1831 struct ice_link_status link_status;
1832 struct rte_eth_link link, old;
1834 unsigned int rep_cnt = MAX_REPEAT_TIME;
1835 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
1837 memset(&link, 0, sizeof(link));
1838 memset(&old, 0, sizeof(old));
1839 memset(&link_status, 0, sizeof(link_status));
1840 ice_atomic_read_link_status(dev, &old);
1843 /* Get link status information from hardware */
1844 status = ice_aq_get_link_info(hw->port_info, enable_lse,
1845 &link_status, NULL);
1846 if (status != ICE_SUCCESS) {
1847 link.link_speed = ETH_SPEED_NUM_100M;
1848 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1849 PMD_DRV_LOG(ERR, "Failed to get link info");
1853 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
1854 if (!wait_to_complete || link.link_status)
1857 rte_delay_ms(CHECK_INTERVAL);
1858 } while (--rep_cnt);
1860 if (!link.link_status)
1863 /* Full-duplex operation at all supported speeds */
1864 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1866 /* Parse the link status */
1867 switch (link_status.link_speed) {
1868 case ICE_AQ_LINK_SPEED_10MB:
1869 link.link_speed = ETH_SPEED_NUM_10M;
1871 case ICE_AQ_LINK_SPEED_100MB:
1872 link.link_speed = ETH_SPEED_NUM_100M;
1874 case ICE_AQ_LINK_SPEED_1000MB:
1875 link.link_speed = ETH_SPEED_NUM_1G;
1877 case ICE_AQ_LINK_SPEED_2500MB:
1878 link.link_speed = ETH_SPEED_NUM_2_5G;
1880 case ICE_AQ_LINK_SPEED_5GB:
1881 link.link_speed = ETH_SPEED_NUM_5G;
1883 case ICE_AQ_LINK_SPEED_10GB:
1884 link.link_speed = ETH_SPEED_NUM_10G;
1886 case ICE_AQ_LINK_SPEED_20GB:
1887 link.link_speed = ETH_SPEED_NUM_20G;
1889 case ICE_AQ_LINK_SPEED_25GB:
1890 link.link_speed = ETH_SPEED_NUM_25G;
1892 case ICE_AQ_LINK_SPEED_40GB:
1893 link.link_speed = ETH_SPEED_NUM_40G;
1895 case ICE_AQ_LINK_SPEED_UNKNOWN:
1897 PMD_DRV_LOG(ERR, "Unknown link speed");
1898 link.link_speed = ETH_SPEED_NUM_NONE;
1902 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1903 ETH_LINK_SPEED_FIXED);
1906 ice_atomic_write_link_status(dev, &link);
1907 if (link.link_status == old.link_status)
1914 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1916 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1917 struct rte_eth_dev_data *dev_data = pf->dev_data;
1918 uint32_t frame_size = mtu + ETHER_HDR_LEN
1919 + ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE;
1921 /* check if mtu is within the allowed range */
1922 if (mtu < ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
1925 /* mtu setting is forbidden if port is start */
1926 if (dev_data->dev_started) {
1928 "port %d must be stopped before configuration",
1933 if (frame_size > ETHER_MAX_LEN)
1934 dev_data->dev_conf.rxmode.offloads |=
1935 DEV_RX_OFFLOAD_JUMBO_FRAME;
1937 dev_data->dev_conf.rxmode.offloads &=
1938 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1940 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1945 static int ice_macaddr_set(struct rte_eth_dev *dev,
1946 struct ether_addr *mac_addr)
1948 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1950 struct ice_vsi *vsi = pf->main_vsi;
1951 struct ice_mac_filter *f;
1955 if (!is_valid_assigned_ether_addr(mac_addr)) {
1956 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
1960 TAILQ_FOREACH(f, &vsi->mac_list, next) {
1961 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
1966 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
1970 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
1971 if (ret != ICE_SUCCESS) {
1972 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
1975 ret = ice_add_mac_filter(vsi, mac_addr);
1976 if (ret != ICE_SUCCESS) {
1977 PMD_DRV_LOG(ERR, "Failed to add mac filter");
1980 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
1982 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
1983 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
1984 if (ret != ICE_SUCCESS)
1985 PMD_DRV_LOG(ERR, "Failed to set manage mac");
1990 /* Add a MAC address, and update filters */
1992 ice_macaddr_add(struct rte_eth_dev *dev,
1993 struct ether_addr *mac_addr,
1994 __rte_unused uint32_t index,
1995 __rte_unused uint32_t pool)
1997 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1998 struct ice_vsi *vsi = pf->main_vsi;
2001 ret = ice_add_mac_filter(vsi, mac_addr);
2002 if (ret != ICE_SUCCESS) {
2003 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2010 /* Remove a MAC address, and update filters */
2012 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2014 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2015 struct ice_vsi *vsi = pf->main_vsi;
2016 struct rte_eth_dev_data *data = dev->data;
2017 struct ether_addr *macaddr;
2020 macaddr = &data->mac_addrs[index];
2021 ret = ice_remove_mac_filter(vsi, macaddr);
2023 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2029 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2031 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2032 struct ice_vsi *vsi = pf->main_vsi;
2035 PMD_INIT_FUNC_TRACE();
2038 ret = ice_add_vlan_filter(vsi, vlan_id);
2040 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2044 ret = ice_remove_vlan_filter(vsi, vlan_id);
2046 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2054 /* Configure vlan filter on or off */
2056 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2058 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2059 struct ice_vsi_ctx ctxt;
2060 uint8_t sec_flags, sw_flags2;
2063 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2064 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2065 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2068 vsi->info.sec_flags |= sec_flags;
2069 vsi->info.sw_flags2 |= sw_flags2;
2071 vsi->info.sec_flags &= ~sec_flags;
2072 vsi->info.sw_flags2 &= ~sw_flags2;
2074 vsi->info.sw_id = hw->port_info->sw_id;
2075 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2076 ctxt.info.valid_sections =
2077 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2078 ICE_AQ_VSI_PROP_SECURITY_VALID);
2079 ctxt.vsi_num = vsi->vsi_id;
2081 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2083 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
2084 on ? "enable" : "disable");
2087 vsi->info.valid_sections |=
2088 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2089 ICE_AQ_VSI_PROP_SECURITY_VALID);
2096 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
2098 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2099 struct ice_vsi_ctx ctxt;
2103 /* Check if it has been already on or off */
2104 if (vsi->info.valid_sections &
2105 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
2107 if ((vsi->info.vlan_flags &
2108 ICE_AQ_VSI_VLAN_EMOD_M) ==
2109 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
2110 return 0; /* already on */
2112 if ((vsi->info.vlan_flags &
2113 ICE_AQ_VSI_VLAN_EMOD_M) ==
2114 ICE_AQ_VSI_VLAN_EMOD_NOTHING)
2115 return 0; /* already off */
2120 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2122 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2123 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
2124 vsi->info.vlan_flags |= vlan_flags;
2125 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2126 ctxt.info.valid_sections =
2127 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2128 ctxt.vsi_num = vsi->vsi_id;
2129 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2131 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2132 on ? "enable" : "disable");
2136 vsi->info.valid_sections |=
2137 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2143 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2145 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2146 struct ice_vsi *vsi = pf->main_vsi;
2147 struct rte_eth_rxmode *rxmode;
2149 rxmode = &dev->data->dev_conf.rxmode;
2150 if (mask & ETH_VLAN_FILTER_MASK) {
2151 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2152 ice_vsi_config_vlan_filter(vsi, TRUE);
2154 ice_vsi_config_vlan_filter(vsi, FALSE);
2157 if (mask & ETH_VLAN_STRIP_MASK) {
2158 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2159 ice_vsi_config_vlan_stripping(vsi, TRUE);
2161 ice_vsi_config_vlan_stripping(vsi, FALSE);
2164 if (mask & ETH_VLAN_EXTEND_MASK) {
2165 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2166 ice_vsi_config_double_vlan(vsi, TRUE);
2168 ice_vsi_config_double_vlan(vsi, FALSE);
2175 ice_vlan_tpid_set(struct rte_eth_dev *dev,
2176 enum rte_vlan_type vlan_type,
2179 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2180 uint64_t reg_r = 0, reg_w = 0;
2181 uint16_t reg_id = 0;
2183 int qinq = dev->data->dev_conf.rxmode.offloads &
2184 DEV_RX_OFFLOAD_VLAN_EXTEND;
2186 switch (vlan_type) {
2187 case ETH_VLAN_TYPE_OUTER:
2193 case ETH_VLAN_TYPE_INNER:
2198 "Unsupported vlan type in single vlan.");
2203 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2206 reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
2207 PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
2208 "0x%08"PRIx64"", reg_id, reg_r);
2210 reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
2211 reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
2212 if (reg_r == reg_w) {
2213 PMD_DRV_LOG(DEBUG, "No need to write");
2217 ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
2218 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2219 "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2225 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2227 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2228 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2234 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2235 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
2238 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2242 uint64_t *lut_dw = (uint64_t *)lut;
2243 uint16_t i, lut_size_dw = lut_size / 4;
2245 for (i = 0; i < lut_size_dw; i++)
2246 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
2253 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2255 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2256 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2262 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2263 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
2266 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2270 uint64_t *lut_dw = (uint64_t *)lut;
2271 uint16_t i, lut_size_dw = lut_size / 4;
2273 for (i = 0; i < lut_size_dw; i++)
2274 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
2283 ice_rss_reta_update(struct rte_eth_dev *dev,
2284 struct rte_eth_rss_reta_entry64 *reta_conf,
2287 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2288 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2289 uint16_t i, lut_size = hw->func_caps.common_cap.rss_table_size;
2290 uint16_t idx, shift;
2294 if (reta_size != lut_size ||
2295 reta_size > ETH_RSS_RETA_SIZE_512) {
2297 "The size of hash lookup table configured (%d)"
2298 "doesn't match the number hardware can "
2300 reta_size, lut_size);
2304 lut = rte_zmalloc(NULL, reta_size, 0);
2306 PMD_DRV_LOG(ERR, "No memory can be allocated");
2309 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2313 for (i = 0; i < reta_size; i++) {
2314 idx = i / RTE_RETA_GROUP_SIZE;
2315 shift = i % RTE_RETA_GROUP_SIZE;
2316 if (reta_conf[idx].mask & (1ULL << shift))
2317 lut[i] = reta_conf[idx].reta[shift];
2319 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
2328 ice_rss_reta_query(struct rte_eth_dev *dev,
2329 struct rte_eth_rss_reta_entry64 *reta_conf,
2332 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2333 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2334 uint16_t i, lut_size = hw->func_caps.common_cap.rss_table_size;
2335 uint16_t idx, shift;
2339 if (reta_size != lut_size ||
2340 reta_size > ETH_RSS_RETA_SIZE_512) {
2342 "The size of hash lookup table configured (%d)"
2343 "doesn't match the number hardware can "
2345 reta_size, lut_size);
2349 lut = rte_zmalloc(NULL, reta_size, 0);
2351 PMD_DRV_LOG(ERR, "No memory can be allocated");
2355 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2359 for (i = 0; i < reta_size; i++) {
2360 idx = i / RTE_RETA_GROUP_SIZE;
2361 shift = i % RTE_RETA_GROUP_SIZE;
2362 if (reta_conf[idx].mask & (1ULL << shift))
2363 reta_conf[idx].reta[shift] = lut[i];
2373 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
2375 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2378 if (!key || key_len == 0) {
2379 PMD_DRV_LOG(DEBUG, "No key to be configured");
2381 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
2383 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2387 struct ice_aqc_get_set_rss_keys *key_dw =
2388 (struct ice_aqc_get_set_rss_keys *)key;
2390 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
2392 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
2400 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
2402 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2405 if (!key || !key_len)
2408 ret = ice_aq_get_rss_key
2410 (struct ice_aqc_get_set_rss_keys *)key);
2412 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
2415 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2421 ice_rss_hash_update(struct rte_eth_dev *dev,
2422 struct rte_eth_rss_conf *rss_conf)
2424 enum ice_status status = ICE_SUCCESS;
2425 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2426 struct ice_vsi *vsi = pf->main_vsi;
2429 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
2433 /* TODO: hash enable config, ice_add_rss_cfg */
2438 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
2439 struct rte_eth_rss_conf *rss_conf)
2441 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2442 struct ice_vsi *vsi = pf->main_vsi;
2444 ice_get_rss_key(vsi, rss_conf->rss_key,
2445 &rss_conf->rss_key_len);
2447 /* TODO: default set to 0 as hf config is not supported now */
2448 rss_conf->rss_hf = 0;
2452 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
2455 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2456 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2457 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2461 msix_intr = intr_handle->intr_vec[queue_id];
2463 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
2464 GLINT_DYN_CTL_ITR_INDX_M;
2465 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
2467 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
2468 rte_intr_enable(&pci_dev->intr_handle);
2473 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
2476 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2477 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2478 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2481 msix_intr = intr_handle->intr_vec[queue_id];
2483 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
2489 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2491 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2494 ret = snprintf(fw_version, fw_size, "%d.%d.%05d %d.%d",
2495 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2496 hw->api_maj_ver, hw->api_min_ver);
2498 /* add the size of '\0' */
2500 if (fw_size < (u32)ret)
2507 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
2510 struct ice_vsi_ctx ctxt;
2511 uint8_t vlan_flags = 0;
2514 if (!vsi || !info) {
2515 PMD_DRV_LOG(ERR, "invalid parameters");
2520 vsi->info.pvid = info->config.pvid;
2522 * If insert pvid is enabled, only tagged pkts are
2523 * allowed to be sent out.
2525 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
2526 ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
2529 if (info->config.reject.tagged == 0)
2530 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
2532 if (info->config.reject.untagged == 0)
2533 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
2535 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
2536 ICE_AQ_VSI_VLAN_MODE_M);
2537 vsi->info.vlan_flags |= vlan_flags;
2538 memset(&ctxt, 0, sizeof(ctxt));
2539 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2540 ctxt.info.valid_sections =
2541 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2542 ctxt.vsi_num = vsi->vsi_id;
2544 hw = ICE_VSI_TO_HW(vsi);
2545 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2546 if (ret != ICE_SUCCESS) {
2548 "update VSI for VLAN insert failed, err %d",
2553 vsi->info.valid_sections |=
2554 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2560 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2562 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2563 struct ice_vsi *vsi = pf->main_vsi;
2564 struct rte_eth_dev_data *data = pf->dev_data;
2565 struct ice_vsi_vlan_pvid_info info;
2568 memset(&info, 0, sizeof(info));
2571 info.config.pvid = pvid;
2573 info.config.reject.tagged =
2574 data->dev_conf.txmode.hw_vlan_reject_tagged;
2575 info.config.reject.untagged =
2576 data->dev_conf.txmode.hw_vlan_reject_untagged;
2579 ret = ice_vsi_vlan_pvid_set(vsi, &info);
2581 PMD_DRV_LOG(ERR, "Failed to set pvid.");
2589 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2590 struct rte_pci_device *pci_dev)
2592 return rte_eth_dev_pci_generic_probe(pci_dev,
2593 sizeof(struct ice_adapter),
2598 ice_pci_remove(struct rte_pci_device *pci_dev)
2600 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
2603 static struct rte_pci_driver rte_ice_pmd = {
2604 .id_table = pci_id_ice_map,
2605 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2606 RTE_PCI_DRV_IOVA_AS_VA,
2607 .probe = ice_pci_probe,
2608 .remove = ice_pci_remove,
2612 * Driver initialization routine.
2613 * Invoked once at EAL init time.
2614 * Register itself as the [Poll Mode] Driver of PCI devices.
2616 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
2617 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
2618 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
2619 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
2620 ICE_MAX_QP_NUM "=<int>");
2622 RTE_INIT(ice_init_log)
2624 ice_logtype_init = rte_log_register("pmd.net.ice.init");
2625 if (ice_logtype_init >= 0)
2626 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
2627 ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
2628 if (ice_logtype_driver >= 0)
2629 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);