1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <rte_ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "ice_ethdev.h"
18 #include "ice_generic_flow.h"
21 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
22 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
23 #define ICE_PROTO_XTR_ARG "proto_xtr"
25 static const char * const ice_valid_args[] = {
26 ICE_SAFE_MODE_SUPPORT_ARG,
27 ICE_PIPELINE_MODE_SUPPORT_ARG,
32 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
34 /* DDP package search path */
35 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
36 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
37 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
38 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
40 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
41 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
42 #define ICE_MAX_PKG_FILENAME_SIZE 256
45 int ice_logtype_driver;
46 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
49 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
52 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
53 int ice_logtype_tx_free;
56 static int ice_dev_configure(struct rte_eth_dev *dev);
57 static int ice_dev_start(struct rte_eth_dev *dev);
58 static void ice_dev_stop(struct rte_eth_dev *dev);
59 static void ice_dev_close(struct rte_eth_dev *dev);
60 static int ice_dev_reset(struct rte_eth_dev *dev);
61 static int ice_dev_info_get(struct rte_eth_dev *dev,
62 struct rte_eth_dev_info *dev_info);
63 static int ice_link_update(struct rte_eth_dev *dev,
64 int wait_to_complete);
65 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
66 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
68 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
69 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
70 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
71 enum rte_vlan_type vlan_type,
73 static int ice_rss_reta_update(struct rte_eth_dev *dev,
74 struct rte_eth_rss_reta_entry64 *reta_conf,
76 static int ice_rss_reta_query(struct rte_eth_dev *dev,
77 struct rte_eth_rss_reta_entry64 *reta_conf,
79 static int ice_rss_hash_update(struct rte_eth_dev *dev,
80 struct rte_eth_rss_conf *rss_conf);
81 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
82 struct rte_eth_rss_conf *rss_conf);
83 static int ice_promisc_enable(struct rte_eth_dev *dev);
84 static int ice_promisc_disable(struct rte_eth_dev *dev);
85 static int ice_allmulti_enable(struct rte_eth_dev *dev);
86 static int ice_allmulti_disable(struct rte_eth_dev *dev);
87 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
90 static int ice_macaddr_set(struct rte_eth_dev *dev,
91 struct rte_ether_addr *mac_addr);
92 static int ice_macaddr_add(struct rte_eth_dev *dev,
93 struct rte_ether_addr *mac_addr,
94 __rte_unused uint32_t index,
96 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
97 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
99 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
101 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
103 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
104 uint16_t pvid, int on);
105 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
106 static int ice_get_eeprom(struct rte_eth_dev *dev,
107 struct rte_dev_eeprom_info *eeprom);
108 static int ice_stats_get(struct rte_eth_dev *dev,
109 struct rte_eth_stats *stats);
110 static int ice_stats_reset(struct rte_eth_dev *dev);
111 static int ice_xstats_get(struct rte_eth_dev *dev,
112 struct rte_eth_xstat *xstats, unsigned int n);
113 static int ice_xstats_get_names(struct rte_eth_dev *dev,
114 struct rte_eth_xstat_name *xstats_names,
116 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
117 enum rte_filter_type filter_type,
118 enum rte_filter_op filter_op,
120 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
121 struct rte_eth_udp_tunnel *udp_tunnel);
122 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
123 struct rte_eth_udp_tunnel *udp_tunnel);
125 static const struct rte_pci_id pci_id_ice_map[] = {
126 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
127 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
128 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
129 { .vendor_id = 0, /* sentinel */ },
132 static const struct eth_dev_ops ice_eth_dev_ops = {
133 .dev_configure = ice_dev_configure,
134 .dev_start = ice_dev_start,
135 .dev_stop = ice_dev_stop,
136 .dev_close = ice_dev_close,
137 .dev_reset = ice_dev_reset,
138 .dev_set_link_up = ice_dev_set_link_up,
139 .dev_set_link_down = ice_dev_set_link_down,
140 .rx_queue_start = ice_rx_queue_start,
141 .rx_queue_stop = ice_rx_queue_stop,
142 .tx_queue_start = ice_tx_queue_start,
143 .tx_queue_stop = ice_tx_queue_stop,
144 .rx_queue_setup = ice_rx_queue_setup,
145 .rx_queue_release = ice_rx_queue_release,
146 .tx_queue_setup = ice_tx_queue_setup,
147 .tx_queue_release = ice_tx_queue_release,
148 .dev_infos_get = ice_dev_info_get,
149 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
150 .link_update = ice_link_update,
151 .mtu_set = ice_mtu_set,
152 .mac_addr_set = ice_macaddr_set,
153 .mac_addr_add = ice_macaddr_add,
154 .mac_addr_remove = ice_macaddr_remove,
155 .vlan_filter_set = ice_vlan_filter_set,
156 .vlan_offload_set = ice_vlan_offload_set,
157 .vlan_tpid_set = ice_vlan_tpid_set,
158 .reta_update = ice_rss_reta_update,
159 .reta_query = ice_rss_reta_query,
160 .rss_hash_update = ice_rss_hash_update,
161 .rss_hash_conf_get = ice_rss_hash_conf_get,
162 .promiscuous_enable = ice_promisc_enable,
163 .promiscuous_disable = ice_promisc_disable,
164 .allmulticast_enable = ice_allmulti_enable,
165 .allmulticast_disable = ice_allmulti_disable,
166 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
167 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
168 .fw_version_get = ice_fw_version_get,
169 .vlan_pvid_set = ice_vlan_pvid_set,
170 .rxq_info_get = ice_rxq_info_get,
171 .txq_info_get = ice_txq_info_get,
172 .rx_burst_mode_get = ice_rx_burst_mode_get,
173 .tx_burst_mode_get = ice_tx_burst_mode_get,
174 .get_eeprom_length = ice_get_eeprom_length,
175 .get_eeprom = ice_get_eeprom,
176 .rx_queue_count = ice_rx_queue_count,
177 .rx_descriptor_status = ice_rx_descriptor_status,
178 .tx_descriptor_status = ice_tx_descriptor_status,
179 .stats_get = ice_stats_get,
180 .stats_reset = ice_stats_reset,
181 .xstats_get = ice_xstats_get,
182 .xstats_get_names = ice_xstats_get_names,
183 .xstats_reset = ice_stats_reset,
184 .filter_ctrl = ice_dev_filter_ctrl,
185 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
186 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
189 /* store statistics names and its offset in stats structure */
190 struct ice_xstats_name_off {
191 char name[RTE_ETH_XSTATS_NAME_SIZE];
195 static const struct ice_xstats_name_off ice_stats_strings[] = {
196 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
197 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
198 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
199 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
200 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
201 rx_unknown_protocol)},
202 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
203 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
204 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
205 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
208 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
209 sizeof(ice_stats_strings[0]))
211 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
212 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
213 tx_dropped_link_down)},
214 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
215 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
217 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
218 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
220 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
222 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
224 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
225 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
226 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
227 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
228 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
229 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
231 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
233 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
235 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
237 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
239 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
241 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
243 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
245 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
246 mac_short_pkt_dropped)},
247 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
249 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
250 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
251 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
253 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
255 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
257 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
259 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
261 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
265 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
266 sizeof(ice_hw_port_strings[0]))
269 ice_init_controlq_parameter(struct ice_hw *hw)
271 /* fields for adminq */
272 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
273 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
274 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
275 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
277 /* fields for mailboxq, DPDK used as PF host */
278 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
279 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
280 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
281 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
285 lookup_proto_xtr_type(const char *xtr_name)
289 enum proto_xtr_type type;
291 { "vlan", PROTO_XTR_VLAN },
292 { "ipv4", PROTO_XTR_IPV4 },
293 { "ipv6", PROTO_XTR_IPV6 },
294 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
295 { "tcp", PROTO_XTR_TCP },
299 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
300 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
301 return xtr_type_map[i].type;
308 * Parse elem, the elem could be single number/range or '(' ')' group
309 * 1) A single number elem, it's just a simple digit. e.g. 9
310 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
311 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
312 * Within group elem, '-' used for a range separator;
313 * ',' used for a single number.
316 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
318 const char *str = input;
323 while (isblank(*str))
326 if (!isdigit(*str) && *str != '(')
329 /* process single number or single range of number */
332 idx = strtoul(str, &end, 10);
333 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
336 while (isblank(*end))
342 /* process single <number>-<number> */
345 while (isblank(*end))
351 idx = strtoul(end, &end, 10);
352 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
356 while (isblank(*end))
363 for (idx = RTE_MIN(min, max);
364 idx <= RTE_MAX(min, max); idx++)
365 devargs->proto_xtr[idx] = xtr_type;
370 /* process set within bracket */
372 while (isblank(*str))
377 min = ICE_MAX_QUEUE_NUM;
379 /* go ahead to the first digit */
380 while (isblank(*str))
385 /* get the digit value */
387 idx = strtoul(str, &end, 10);
388 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
391 /* go ahead to separator '-',',' and ')' */
392 while (isblank(*end))
395 if (min == ICE_MAX_QUEUE_NUM)
397 else /* avoid continuous '-' */
399 } else if (*end == ',' || *end == ')') {
401 if (min == ICE_MAX_QUEUE_NUM)
404 for (idx = RTE_MIN(min, max);
405 idx <= RTE_MAX(min, max); idx++)
406 devargs->proto_xtr[idx] = xtr_type;
408 min = ICE_MAX_QUEUE_NUM;
414 } while (*end != ')' && *end != '\0');
420 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
422 const char *queue_start;
427 while (isblank(*queues))
430 if (*queues != '[') {
431 xtr_type = lookup_proto_xtr_type(queues);
435 devargs->proto_xtr_dflt = xtr_type;
442 while (isblank(*queues))
447 queue_start = queues;
449 /* go across a complete bracket */
450 if (*queue_start == '(') {
451 queues += strcspn(queues, ")");
456 /* scan the separator ':' */
457 queues += strcspn(queues, ":");
458 if (*queues++ != ':')
460 while (isblank(*queues))
463 for (idx = 0; ; idx++) {
464 if (isblank(queues[idx]) ||
465 queues[idx] == ',' ||
466 queues[idx] == ']' ||
470 if (idx > sizeof(xtr_name) - 2)
473 xtr_name[idx] = queues[idx];
475 xtr_name[idx] = '\0';
476 xtr_type = lookup_proto_xtr_type(xtr_name);
482 while (isblank(*queues) || *queues == ',' || *queues == ']')
485 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
487 } while (*queues != '\0');
493 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
496 struct ice_devargs *devargs = extra_args;
498 if (value == NULL || extra_args == NULL)
501 if (parse_queue_proto_xtr(value, devargs) < 0) {
503 "The protocol extraction parameter is wrong : '%s'",
512 ice_proto_xtr_support(struct ice_hw *hw)
514 #define FLX_REG(val, fld, idx) \
515 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
516 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
522 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
523 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
524 ICE_PROT_IPV4_OF_OR_S },
525 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
526 ICE_PROT_IPV6_OF_OR_S },
527 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
528 ICE_PROT_IPV6_OF_OR_S },
529 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
533 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
534 uint32_t rxdid = xtr_sets[i].rxdid;
537 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
538 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
540 if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
541 FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
545 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
546 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
548 if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
549 FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
558 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
561 struct pool_entry *entry;
566 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
569 "Failed to allocate memory for resource pool");
573 /* queue heap initialize */
574 pool->num_free = num;
577 LIST_INIT(&pool->alloc_list);
578 LIST_INIT(&pool->free_list);
580 /* Initialize element */
584 LIST_INSERT_HEAD(&pool->free_list, entry, next);
589 ice_res_pool_alloc(struct ice_res_pool_info *pool,
592 struct pool_entry *entry, *valid_entry;
595 PMD_INIT_LOG(ERR, "Invalid parameter");
599 if (pool->num_free < num) {
600 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
601 num, pool->num_free);
606 /* Lookup in free list and find most fit one */
607 LIST_FOREACH(entry, &pool->free_list, next) {
608 if (entry->len >= num) {
610 if (entry->len == num) {
615 valid_entry->len > entry->len)
620 /* Not find one to satisfy the request, return */
622 PMD_INIT_LOG(ERR, "No valid entry found");
626 * The entry have equal queue number as requested,
627 * remove it from alloc_list.
629 if (valid_entry->len == num) {
630 LIST_REMOVE(valid_entry, next);
633 * The entry have more numbers than requested,
634 * create a new entry for alloc_list and minus its
635 * queue base and number in free_list.
637 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
640 "Failed to allocate memory for "
644 entry->base = valid_entry->base;
646 valid_entry->base += num;
647 valid_entry->len -= num;
651 /* Insert it into alloc list, not sorted */
652 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
654 pool->num_free -= valid_entry->len;
655 pool->num_alloc += valid_entry->len;
657 return valid_entry->base + pool->base;
661 ice_res_pool_destroy(struct ice_res_pool_info *pool)
663 struct pool_entry *entry, *next_entry;
668 for (entry = LIST_FIRST(&pool->alloc_list);
669 entry && (next_entry = LIST_NEXT(entry, next), 1);
670 entry = next_entry) {
671 LIST_REMOVE(entry, next);
675 for (entry = LIST_FIRST(&pool->free_list);
676 entry && (next_entry = LIST_NEXT(entry, next), 1);
677 entry = next_entry) {
678 LIST_REMOVE(entry, next);
685 LIST_INIT(&pool->alloc_list);
686 LIST_INIT(&pool->free_list);
690 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
692 /* Set VSI LUT selection */
693 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
694 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
695 /* Set Hash scheme */
696 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
697 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
699 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
702 static enum ice_status
703 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
704 struct ice_aqc_vsi_props *info,
705 uint8_t enabled_tcmap)
707 uint16_t bsf, qp_idx;
709 /* default tc 0 now. Multi-TC supporting need to be done later.
710 * Configure TC and queue mapping parameters, for enabled TC,
711 * allocate qpnum_per_tc queues to this traffic.
713 if (enabled_tcmap != 0x01) {
714 PMD_INIT_LOG(ERR, "only TC0 is supported");
718 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
719 bsf = rte_bsf32(vsi->nb_qps);
720 /* Adjust the queue number to actual queues that can be applied */
721 vsi->nb_qps = 0x1 << bsf;
724 /* Set tc and queue mapping with VSI */
725 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
726 ICE_AQ_VSI_TC_Q_OFFSET_S) |
727 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
729 /* Associate queue number with VSI */
730 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
731 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
732 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
733 info->valid_sections |=
734 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
735 /* Set the info.ingress_table and info.egress_table
736 * for UP translate table. Now just set it to 1:1 map by default
737 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
739 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
740 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
741 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
742 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
747 ice_init_mac_address(struct rte_eth_dev *dev)
749 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
751 if (!rte_is_unicast_ether_addr
752 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
753 PMD_INIT_LOG(ERR, "Invalid MAC address");
758 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
759 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
761 dev->data->mac_addrs =
762 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
763 if (!dev->data->mac_addrs) {
765 "Failed to allocate memory to store mac address");
768 /* store it to dev data */
770 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
771 &dev->data->mac_addrs[0]);
775 /* Find out specific MAC filter */
776 static struct ice_mac_filter *
777 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
779 struct ice_mac_filter *f;
781 TAILQ_FOREACH(f, &vsi->mac_list, next) {
782 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
790 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
792 struct ice_fltr_list_entry *m_list_itr = NULL;
793 struct ice_mac_filter *f;
794 struct LIST_HEAD_TYPE list_head;
795 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
798 /* If it's added and configured, return */
799 f = ice_find_mac_filter(vsi, mac_addr);
801 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
805 INIT_LIST_HEAD(&list_head);
807 m_list_itr = (struct ice_fltr_list_entry *)
808 ice_malloc(hw, sizeof(*m_list_itr));
813 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
814 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
815 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
816 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
817 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
818 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
819 m_list_itr->fltr_info.vsi_handle = vsi->idx;
821 LIST_ADD(&m_list_itr->list_entry, &list_head);
824 ret = ice_add_mac(hw, &list_head);
825 if (ret != ICE_SUCCESS) {
826 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
830 /* Add the mac addr into mac list */
831 f = rte_zmalloc(NULL, sizeof(*f), 0);
833 PMD_DRV_LOG(ERR, "failed to allocate memory");
837 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
838 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
844 rte_free(m_list_itr);
849 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
851 struct ice_fltr_list_entry *m_list_itr = NULL;
852 struct ice_mac_filter *f;
853 struct LIST_HEAD_TYPE list_head;
854 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
857 /* Can't find it, return an error */
858 f = ice_find_mac_filter(vsi, mac_addr);
862 INIT_LIST_HEAD(&list_head);
864 m_list_itr = (struct ice_fltr_list_entry *)
865 ice_malloc(hw, sizeof(*m_list_itr));
870 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
871 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
872 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
873 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
874 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
875 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
876 m_list_itr->fltr_info.vsi_handle = vsi->idx;
878 LIST_ADD(&m_list_itr->list_entry, &list_head);
880 /* remove the mac filter */
881 ret = ice_remove_mac(hw, &list_head);
882 if (ret != ICE_SUCCESS) {
883 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
888 /* Remove the mac addr from mac list */
889 TAILQ_REMOVE(&vsi->mac_list, f, next);
895 rte_free(m_list_itr);
899 /* Find out specific VLAN filter */
900 static struct ice_vlan_filter *
901 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
903 struct ice_vlan_filter *f;
905 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
906 if (vlan_id == f->vlan_info.vlan_id)
914 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
916 struct ice_fltr_list_entry *v_list_itr = NULL;
917 struct ice_vlan_filter *f;
918 struct LIST_HEAD_TYPE list_head;
922 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
925 hw = ICE_VSI_TO_HW(vsi);
927 /* If it's added and configured, return. */
928 f = ice_find_vlan_filter(vsi, vlan_id);
930 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
934 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
937 INIT_LIST_HEAD(&list_head);
939 v_list_itr = (struct ice_fltr_list_entry *)
940 ice_malloc(hw, sizeof(*v_list_itr));
945 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
946 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
947 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
948 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
949 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
950 v_list_itr->fltr_info.vsi_handle = vsi->idx;
952 LIST_ADD(&v_list_itr->list_entry, &list_head);
955 ret = ice_add_vlan(hw, &list_head);
956 if (ret != ICE_SUCCESS) {
957 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
962 /* Add vlan into vlan list */
963 f = rte_zmalloc(NULL, sizeof(*f), 0);
965 PMD_DRV_LOG(ERR, "failed to allocate memory");
969 f->vlan_info.vlan_id = vlan_id;
970 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
976 rte_free(v_list_itr);
981 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
983 struct ice_fltr_list_entry *v_list_itr = NULL;
984 struct ice_vlan_filter *f;
985 struct LIST_HEAD_TYPE list_head;
990 * Vlan 0 is the generic filter for untagged packets
991 * and can't be removed.
993 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
996 hw = ICE_VSI_TO_HW(vsi);
998 /* Can't find it, return an error */
999 f = ice_find_vlan_filter(vsi, vlan_id);
1003 INIT_LIST_HEAD(&list_head);
1005 v_list_itr = (struct ice_fltr_list_entry *)
1006 ice_malloc(hw, sizeof(*v_list_itr));
1012 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1013 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1014 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1015 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1016 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1017 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1019 LIST_ADD(&v_list_itr->list_entry, &list_head);
1021 /* remove the vlan filter */
1022 ret = ice_remove_vlan(hw, &list_head);
1023 if (ret != ICE_SUCCESS) {
1024 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1029 /* Remove the vlan id from vlan list */
1030 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1036 rte_free(v_list_itr);
1041 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1043 struct ice_mac_filter *m_f;
1044 struct ice_vlan_filter *v_f;
1047 if (!vsi || !vsi->mac_num)
1050 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1051 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1052 if (ret != ICE_SUCCESS) {
1058 if (vsi->vlan_num == 0)
1061 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1062 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1063 if (ret != ICE_SUCCESS) {
1074 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1076 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1077 struct ice_vsi_ctx ctxt;
1081 /* Check if it has been already on or off */
1082 if (vsi->info.valid_sections &
1083 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1085 if ((vsi->info.outer_tag_flags &
1086 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1087 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1088 return 0; /* already on */
1090 if (!(vsi->info.outer_tag_flags &
1091 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1092 return 0; /* already off */
1097 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1100 /* clear global insertion and use per packet insertion */
1101 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1102 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1103 vsi->info.outer_tag_flags |= qinq_flags;
1104 /* use default vlan type 0x8100 */
1105 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1106 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1107 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1108 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1109 ctxt.info.valid_sections =
1110 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1111 ctxt.vsi_num = vsi->vsi_id;
1112 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1115 "Update VSI failed to %s qinq stripping",
1116 on ? "enable" : "disable");
1120 vsi->info.valid_sections |=
1121 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1127 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1129 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1130 struct ice_vsi_ctx ctxt;
1134 /* Check if it has been already on or off */
1135 if (vsi->info.valid_sections &
1136 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1138 if ((vsi->info.outer_tag_flags &
1139 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1140 ICE_AQ_VSI_OUTER_TAG_COPY)
1141 return 0; /* already on */
1143 if ((vsi->info.outer_tag_flags &
1144 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1145 ICE_AQ_VSI_OUTER_TAG_NOTHING)
1146 return 0; /* already off */
1151 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1153 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1154 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1155 vsi->info.outer_tag_flags |= qinq_flags;
1156 /* use default vlan type 0x8100 */
1157 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1158 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1159 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1160 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1161 ctxt.info.valid_sections =
1162 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1163 ctxt.vsi_num = vsi->vsi_id;
1164 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1167 "Update VSI failed to %s qinq stripping",
1168 on ? "enable" : "disable");
1172 vsi->info.valid_sections |=
1173 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1179 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1183 ret = ice_vsi_config_qinq_stripping(vsi, on);
1185 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1187 ret = ice_vsi_config_qinq_insertion(vsi, on);
1189 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1196 ice_pf_enable_irq0(struct ice_hw *hw)
1198 /* reset the registers */
1199 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1200 ICE_READ_REG(hw, PFINT_OICR);
1203 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1204 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1205 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1207 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1208 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1209 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1210 PFINT_OICR_CTL_ITR_INDX_M) |
1211 PFINT_OICR_CTL_CAUSE_ENA_M);
1213 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1214 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1215 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1216 PFINT_FW_CTL_ITR_INDX_M) |
1217 PFINT_FW_CTL_CAUSE_ENA_M);
1219 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1222 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1223 GLINT_DYN_CTL_INTENA_M |
1224 GLINT_DYN_CTL_CLEARPBA_M |
1225 GLINT_DYN_CTL_ITR_INDX_M);
1232 ice_pf_disable_irq0(struct ice_hw *hw)
1234 /* Disable all interrupt types */
1235 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1241 ice_handle_aq_msg(struct rte_eth_dev *dev)
1243 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1244 struct ice_ctl_q_info *cq = &hw->adminq;
1245 struct ice_rq_event_info event;
1246 uint16_t pending, opcode;
1249 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1250 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1251 if (!event.msg_buf) {
1252 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1258 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1260 if (ret != ICE_SUCCESS) {
1262 "Failed to read msg from AdminQ, "
1264 hw->adminq.sq_last_status);
1267 opcode = rte_le_to_cpu_16(event.desc.opcode);
1270 case ice_aqc_opc_get_link_status:
1271 ret = ice_link_update(dev, 0);
1273 _rte_eth_dev_callback_process
1274 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1277 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1282 rte_free(event.msg_buf);
1287 * Interrupt handler triggered by NIC for handling
1288 * specific interrupt.
1291 * Pointer to interrupt handle.
1293 * The address of parameter (struct rte_eth_dev *) regsitered before.
1299 ice_interrupt_handler(void *param)
1301 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1302 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1309 uint32_t int_fw_ctl;
1312 /* Disable interrupt */
1313 ice_pf_disable_irq0(hw);
1315 /* read out interrupt causes */
1316 oicr = ICE_READ_REG(hw, PFINT_OICR);
1318 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1321 /* No interrupt event indicated */
1322 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1323 PMD_DRV_LOG(INFO, "No interrupt event");
1328 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1329 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1330 ice_handle_aq_msg(dev);
1333 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1334 PMD_DRV_LOG(INFO, "OICR: link state change event");
1335 ice_link_update(dev, 0);
1339 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1340 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1341 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1342 if (reg & GL_MDET_TX_PQM_VALID_M) {
1343 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1344 GL_MDET_TX_PQM_PF_NUM_S;
1345 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1346 GL_MDET_TX_PQM_MAL_TYPE_S;
1347 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1348 GL_MDET_TX_PQM_QNUM_S;
1350 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1351 "%d by PQM on TX queue %d PF# %d",
1352 event, queue, pf_num);
1355 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1356 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1357 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1358 GL_MDET_TX_TCLAN_PF_NUM_S;
1359 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1360 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1361 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1362 GL_MDET_TX_TCLAN_QNUM_S;
1364 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1365 "%d by TCLAN on TX queue %d PF# %d",
1366 event, queue, pf_num);
1370 /* Enable interrupt */
1371 ice_pf_enable_irq0(hw);
1372 rte_intr_ack(dev->intr_handle);
1376 ice_init_proto_xtr(struct rte_eth_dev *dev)
1378 struct ice_adapter *ad =
1379 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1380 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1381 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1384 if (!ice_proto_xtr_support(hw)) {
1385 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1389 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1390 if (unlikely(pf->proto_xtr == NULL)) {
1391 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1395 for (i = 0; i < pf->lan_nb_qps; i++)
1396 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1397 ad->devargs.proto_xtr[i] :
1398 ad->devargs.proto_xtr_dflt;
1401 /* Initialize SW parameters of PF */
1403 ice_pf_sw_init(struct rte_eth_dev *dev)
1405 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1406 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1409 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1410 hw->func_caps.common_cap.num_rxq);
1412 pf->lan_nb_qps = pf->lan_nb_qp_max;
1414 ice_init_proto_xtr(dev);
1419 static struct ice_vsi *
1420 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1422 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1423 struct ice_vsi *vsi = NULL;
1424 struct ice_vsi_ctx vsi_ctx;
1426 struct rte_ether_addr broadcast = {
1427 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1428 struct rte_ether_addr mac_addr;
1429 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1430 uint8_t tc_bitmap = 0x1;
1432 /* hw->num_lports = 1 in NIC mode */
1433 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1437 vsi->idx = pf->next_vsi_idx;
1440 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1441 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1442 vsi->vlan_anti_spoof_on = 0;
1443 vsi->vlan_filter_on = 1;
1444 TAILQ_INIT(&vsi->mac_list);
1445 TAILQ_INIT(&vsi->vlan_list);
1447 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1448 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1449 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1450 hw->func_caps.common_cap.rss_table_size;
1451 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1453 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1454 /* base_queue in used in queue mapping of VSI add/update command.
1455 * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1456 * cases in the first stage. Only Main VSI.
1458 vsi->base_queue = 0;
1461 vsi->nb_qps = pf->lan_nb_qps;
1462 ice_vsi_config_default_rss(&vsi_ctx.info);
1463 vsi_ctx.alloc_from_pool = true;
1464 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1465 /* switch_id is queried by get_switch_config aq, which is done
1468 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1469 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1470 /* Allow all untagged or tagged packets */
1471 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1472 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1473 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1474 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1475 /* Enable VLAN/UP trip */
1476 ret = ice_vsi_config_tc_queue_mapping(vsi,
1481 "tc queue mapping with vsi failed, "
1489 /* for other types of VSI */
1490 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1494 /* VF has MSIX interrupt in VF range, don't allocate here */
1495 if (type == ICE_VSI_PF) {
1496 ret = ice_res_pool_alloc(&pf->msix_pool,
1497 RTE_MIN(vsi->nb_qps,
1498 RTE_MAX_RXTX_INTR_VEC_ID));
1500 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1503 vsi->msix_intr = ret;
1504 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1509 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1510 if (ret != ICE_SUCCESS) {
1511 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1514 /* store vsi information is SW structure */
1515 vsi->vsi_id = vsi_ctx.vsi_num;
1516 vsi->info = vsi_ctx.info;
1517 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1518 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1520 /* MAC configuration */
1521 rte_memcpy(pf->dev_addr.addr_bytes,
1522 hw->port_info->mac.perm_addr,
1525 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1526 ret = ice_add_mac_filter(vsi, &mac_addr);
1527 if (ret != ICE_SUCCESS)
1528 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1530 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1531 ret = ice_add_mac_filter(vsi, &mac_addr);
1532 if (ret != ICE_SUCCESS)
1533 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1535 /* At the beginning, only TC0. */
1536 /* What we need here is the maximam number of the TX queues.
1537 * Currently vsi->nb_qps means it.
1538 * Correct it if any change.
1540 max_txqs[0] = vsi->nb_qps;
1541 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1542 tc_bitmap, max_txqs);
1543 if (ret != ICE_SUCCESS)
1544 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1554 ice_send_driver_ver(struct ice_hw *hw)
1556 struct ice_driver_ver dv;
1558 /* we don't have driver version use 0 for dummy */
1562 dv.subbuild_ver = 0;
1563 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1565 return ice_aq_send_driver_ver(hw, &dv, NULL);
1569 ice_pf_setup(struct ice_pf *pf)
1571 struct ice_vsi *vsi;
1573 /* Clear all stats counters */
1574 pf->offset_loaded = FALSE;
1575 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1576 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1577 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1578 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1580 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1582 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1591 /* PCIe configuration space setting */
1592 #define PCI_CFG_SPACE_SIZE 256
1593 #define PCI_CFG_SPACE_EXP_SIZE 4096
1594 #define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)
1595 #define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)
1596 #define PCI_EXT_CAP_ID_DSN 0x03
1599 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1603 int pos = PCI_CFG_SPACE_SIZE;
1605 /* minimum 8 bytes per capability */
1606 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1608 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1609 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1614 * If we have no capabilities, this is indicated by cap ID,
1615 * cap version and next pointer all being 0.
1621 if (PCI_EXT_CAP_ID(header) == cap)
1624 pos = PCI_EXT_CAP_NEXT(header);
1626 if (pos < PCI_CFG_SPACE_SIZE)
1629 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1630 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1639 * Extract device serial number from PCIe Configuration Space and
1640 * determine the pkg file path according to the DSN.
1643 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1646 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1647 uint32_t dsn_low, dsn_high;
1648 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1650 pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1653 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1654 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1655 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1656 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1658 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1662 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1663 ICE_MAX_PKG_FILENAME_SIZE);
1664 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1667 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1668 ICE_MAX_PKG_FILENAME_SIZE);
1669 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1673 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1674 if (!access(pkg_file, 0))
1676 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1680 static enum ice_pkg_type
1681 ice_load_pkg_type(struct ice_hw *hw)
1683 enum ice_pkg_type package_type;
1685 /* store the activated package type (OS default or Comms) */
1686 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1688 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1689 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1691 package_type = ICE_PKG_TYPE_COMMS;
1693 package_type = ICE_PKG_TYPE_UNKNOWN;
1695 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1696 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1697 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1698 hw->active_pkg_name);
1700 return package_type;
1703 static int ice_load_pkg(struct rte_eth_dev *dev)
1705 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1706 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1712 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1713 struct ice_adapter *ad =
1714 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1716 ice_pkg_file_search_path(pci_dev, pkg_file);
1718 file = fopen(pkg_file, "rb");
1720 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1724 err = stat(pkg_file, &fstat);
1726 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1731 buf_len = fstat.st_size;
1732 buf = rte_malloc(NULL, buf_len, 0);
1735 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1741 err = fread(buf, buf_len, 1, file);
1743 PMD_INIT_LOG(ERR, "failed to read package data\n");
1751 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1753 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1757 /* store the loaded pkg type info */
1758 ad->active_pkg_type = ice_load_pkg_type(hw);
1760 err = ice_init_hw_tbls(hw);
1762 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1763 goto fail_init_tbls;
1769 rte_free(hw->pkg_copy);
1776 ice_base_queue_get(struct ice_pf *pf)
1779 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1781 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1782 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1783 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1785 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1791 parse_bool(const char *key, const char *value, void *args)
1793 int *i = (int *)args;
1797 num = strtoul(value, &end, 10);
1799 if (num != 0 && num != 1) {
1800 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1801 "value must be 0 or 1",
1810 static int ice_parse_devargs(struct rte_eth_dev *dev)
1812 struct ice_adapter *ad =
1813 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1814 struct rte_devargs *devargs = dev->device->devargs;
1815 struct rte_kvargs *kvlist;
1818 if (devargs == NULL)
1821 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1822 if (kvlist == NULL) {
1823 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1827 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1828 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1829 sizeof(ad->devargs.proto_xtr));
1831 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1832 &handle_proto_xtr_arg, &ad->devargs);
1836 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1837 &parse_bool, &ad->devargs.safe_mode_support);
1841 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1842 &parse_bool, &ad->devargs.pipe_mode_support);
1845 rte_kvargs_free(kvlist);
1849 /* Forward LLDP packets to default VSI by set switch rules */
1851 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
1853 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1854 struct ice_fltr_list_entry *s_list_itr = NULL;
1855 struct LIST_HEAD_TYPE list_head;
1858 INIT_LIST_HEAD(&list_head);
1860 s_list_itr = (struct ice_fltr_list_entry *)
1861 ice_malloc(hw, sizeof(*s_list_itr));
1864 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1865 s_list_itr->fltr_info.vsi_handle = vsi->idx;
1866 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1867 RTE_ETHER_TYPE_LLDP;
1868 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1869 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1870 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1871 LIST_ADD(&s_list_itr->list_entry, &list_head);
1873 ret = ice_add_eth_mac(hw, &list_head);
1875 ret = ice_remove_eth_mac(hw, &list_head);
1877 rte_free(s_list_itr);
1882 ice_dev_init(struct rte_eth_dev *dev)
1884 struct rte_pci_device *pci_dev;
1885 struct rte_intr_handle *intr_handle;
1886 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1887 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1888 struct ice_adapter *ad =
1889 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1890 struct ice_vsi *vsi;
1893 dev->dev_ops = &ice_eth_dev_ops;
1894 dev->rx_pkt_burst = ice_recv_pkts;
1895 dev->tx_pkt_burst = ice_xmit_pkts;
1896 dev->tx_pkt_prepare = ice_prep_pkts;
1898 /* for secondary processes, we don't initialise any further as primary
1899 * has already done this work.
1901 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1902 ice_set_rx_function(dev);
1903 ice_set_tx_function(dev);
1907 ice_set_default_ptype_table(dev);
1908 pci_dev = RTE_DEV_TO_PCI(dev->device);
1909 intr_handle = &pci_dev->intr_handle;
1911 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1912 pf->adapter->eth_dev = dev;
1913 pf->dev_data = dev->data;
1914 hw->back = pf->adapter;
1915 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1916 hw->vendor_id = pci_dev->id.vendor_id;
1917 hw->device_id = pci_dev->id.device_id;
1918 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1919 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1920 hw->bus.device = pci_dev->addr.devid;
1921 hw->bus.func = pci_dev->addr.function;
1923 ret = ice_parse_devargs(dev);
1925 PMD_INIT_LOG(ERR, "Failed to parse devargs");
1929 ice_init_controlq_parameter(hw);
1931 ret = ice_init_hw(hw);
1933 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1937 ret = ice_load_pkg(dev);
1939 if (ad->devargs.safe_mode_support == 0) {
1940 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
1941 "Use safe-mode-support=1 to enter Safe Mode");
1945 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1946 "Entering Safe Mode");
1947 ad->is_safe_mode = 1;
1950 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1951 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1952 hw->api_maj_ver, hw->api_min_ver);
1954 ice_pf_sw_init(dev);
1955 ret = ice_init_mac_address(dev);
1957 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1961 /* Pass the information to the rte_eth_dev_close() that it should also
1962 * release the private port resources.
1964 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1966 ret = ice_res_pool_init(&pf->msix_pool, 1,
1967 hw->func_caps.common_cap.num_msix_vectors - 1);
1969 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1970 goto err_msix_pool_init;
1973 ret = ice_pf_setup(pf);
1975 PMD_INIT_LOG(ERR, "Failed to setup PF");
1979 ret = ice_send_driver_ver(hw);
1981 PMD_INIT_LOG(ERR, "Failed to send driver version");
1987 /* Disable double vlan by default */
1988 ice_vsi_config_double_vlan(vsi, FALSE);
1990 ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
1991 if (ret != ICE_SUCCESS)
1992 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1993 ret = ice_init_dcb(hw, TRUE);
1994 if (ret != ICE_SUCCESS)
1995 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
1996 /* Forward LLDP packets to default VSI */
1997 ret = ice_vsi_config_sw_lldp(vsi, TRUE);
1998 if (ret != ICE_SUCCESS)
1999 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2000 /* register callback func to eal lib */
2001 rte_intr_callback_register(intr_handle,
2002 ice_interrupt_handler, dev);
2004 ice_pf_enable_irq0(hw);
2006 /* enable uio intr after callback register */
2007 rte_intr_enable(intr_handle);
2009 /* get base queue pairs index in the device */
2010 ice_base_queue_get(pf);
2012 ret = ice_flow_init(ad);
2014 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2021 ice_res_pool_destroy(&pf->msix_pool);
2023 rte_free(dev->data->mac_addrs);
2024 dev->data->mac_addrs = NULL;
2026 ice_sched_cleanup_all(hw);
2027 rte_free(hw->port_info);
2028 ice_shutdown_all_ctrlq(hw);
2029 rte_free(pf->proto_xtr);
2035 ice_release_vsi(struct ice_vsi *vsi)
2038 struct ice_vsi_ctx vsi_ctx;
2039 enum ice_status ret;
2044 hw = ICE_VSI_TO_HW(vsi);
2046 ice_remove_all_mac_vlan_filters(vsi);
2048 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2050 vsi_ctx.vsi_num = vsi->vsi_id;
2051 vsi_ctx.info = vsi->info;
2052 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2053 if (ret != ICE_SUCCESS) {
2054 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2064 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2066 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2067 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2068 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2069 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2070 uint16_t msix_intr, i;
2072 /* disable interrupt and also clear all the exist config */
2073 for (i = 0; i < vsi->nb_qps; i++) {
2074 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2075 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2079 if (rte_intr_allow_others(intr_handle))
2081 for (i = 0; i < vsi->nb_msix; i++) {
2082 msix_intr = vsi->msix_intr + i;
2083 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2084 GLINT_DYN_CTL_WB_ON_ITR_M);
2088 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2092 ice_dev_stop(struct rte_eth_dev *dev)
2094 struct rte_eth_dev_data *data = dev->data;
2095 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2096 struct ice_vsi *main_vsi = pf->main_vsi;
2097 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2098 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2101 /* avoid stopping again */
2102 if (pf->adapter_stopped)
2105 /* stop and clear all Rx queues */
2106 for (i = 0; i < data->nb_rx_queues; i++)
2107 ice_rx_queue_stop(dev, i);
2109 /* stop and clear all Tx queues */
2110 for (i = 0; i < data->nb_tx_queues; i++)
2111 ice_tx_queue_stop(dev, i);
2113 /* disable all queue interrupts */
2114 ice_vsi_disable_queues_intr(main_vsi);
2116 /* Clear all queues and release mbufs */
2117 ice_clear_queues(dev);
2119 ice_dev_set_link_down(dev);
2121 /* Clean datapath event and queue/vec mapping */
2122 rte_intr_efd_disable(intr_handle);
2123 if (intr_handle->intr_vec) {
2124 rte_free(intr_handle->intr_vec);
2125 intr_handle->intr_vec = NULL;
2128 pf->adapter_stopped = true;
2132 ice_dev_close(struct rte_eth_dev *dev)
2134 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2135 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2136 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2137 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2138 struct ice_adapter *ad =
2139 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2141 /* Since stop will make link down, then the link event will be
2142 * triggered, disable the irq firstly to avoid the port_infoe etc
2143 * resources deallocation causing the interrupt service thread
2146 ice_pf_disable_irq0(hw);
2150 ice_flow_uninit(ad);
2152 /* release all queue resource */
2153 ice_free_queues(dev);
2155 ice_res_pool_destroy(&pf->msix_pool);
2156 ice_release_vsi(pf->main_vsi);
2157 ice_sched_cleanup_all(hw);
2158 rte_free(hw->port_info);
2159 hw->port_info = NULL;
2160 ice_shutdown_all_ctrlq(hw);
2161 rte_free(pf->proto_xtr);
2162 pf->proto_xtr = NULL;
2164 dev->dev_ops = NULL;
2165 dev->rx_pkt_burst = NULL;
2166 dev->tx_pkt_burst = NULL;
2168 rte_free(dev->data->mac_addrs);
2169 dev->data->mac_addrs = NULL;
2171 /* disable uio intr before callback unregister */
2172 rte_intr_disable(intr_handle);
2174 /* unregister callback func from eal lib */
2175 rte_intr_callback_unregister(intr_handle,
2176 ice_interrupt_handler, dev);
2180 ice_dev_uninit(struct rte_eth_dev *dev)
2188 ice_dev_configure(struct rte_eth_dev *dev)
2190 struct ice_adapter *ad =
2191 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2193 /* Initialize to TRUE. If any of Rx queues doesn't meet the
2194 * bulk allocation or vector Rx preconditions we will reset it.
2196 ad->rx_bulk_alloc_allowed = true;
2197 ad->tx_simple_allowed = true;
2202 static int ice_init_rss(struct ice_pf *pf)
2204 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2205 struct ice_vsi *vsi = pf->main_vsi;
2206 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2207 struct rte_eth_rss_conf *rss_conf;
2208 struct ice_aqc_get_set_rss_keys key;
2211 bool is_safe_mode = pf->adapter->is_safe_mode;
2213 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2214 nb_q = dev->data->nb_rx_queues;
2215 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2216 vsi->rss_lut_size = pf->hash_lut_size;
2219 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2224 vsi->rss_key = rte_zmalloc(NULL,
2225 vsi->rss_key_size, 0);
2227 vsi->rss_lut = rte_zmalloc(NULL,
2228 vsi->rss_lut_size, 0);
2230 /* configure RSS key */
2231 if (!rss_conf->rss_key) {
2232 /* Calculate the default hash key */
2233 for (i = 0; i <= vsi->rss_key_size; i++)
2234 vsi->rss_key[i] = (uint8_t)rte_rand();
2236 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2237 RTE_MIN(rss_conf->rss_key_len,
2238 vsi->rss_key_size));
2240 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2241 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2245 /* init RSS LUT table */
2246 for (i = 0; i < vsi->rss_lut_size; i++)
2247 vsi->rss_lut[i] = i % nb_q;
2249 ret = ice_aq_set_rss_lut(hw, vsi->idx,
2250 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2251 vsi->rss_lut, vsi->rss_lut_size);
2255 /* configure RSS for IPv4 with input set IPv4 src/dst */
2256 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2257 ICE_FLOW_SEG_HDR_IPV4, 0);
2259 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2261 /* configure RSS for IPv6 with input set IPv6 src/dst */
2262 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2263 ICE_FLOW_SEG_HDR_IPV6, 0);
2265 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2267 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2268 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2269 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2271 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2273 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2274 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2275 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2277 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2279 /* configure RSS for sctp6 with input set IPv6 src/dst */
2280 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2281 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2283 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2286 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2287 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2288 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2290 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2292 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2293 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2294 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2296 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2298 /* configure RSS for sctp4 with input set IP src/dst */
2299 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2300 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2302 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2309 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2310 int base_queue, int nb_queue)
2312 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2313 uint32_t val, val_tx;
2316 for (i = 0; i < nb_queue; i++) {
2318 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2319 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2320 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2321 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2323 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2324 base_queue + i, msix_vect);
2325 /* set ITR0 value */
2326 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2327 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2328 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2333 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2335 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2336 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2337 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2338 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2339 uint16_t msix_vect = vsi->msix_intr;
2340 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2341 uint16_t queue_idx = 0;
2345 /* clear Rx/Tx queue interrupt */
2346 for (i = 0; i < vsi->nb_used_qps; i++) {
2347 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2348 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2351 /* PF bind interrupt */
2352 if (rte_intr_dp_is_en(intr_handle)) {
2357 for (i = 0; i < vsi->nb_used_qps; i++) {
2359 if (!rte_intr_allow_others(intr_handle))
2360 msix_vect = ICE_MISC_VEC_ID;
2362 /* uio mapping all queue to one msix_vect */
2363 __vsi_queues_bind_intr(vsi, msix_vect,
2364 vsi->base_queue + i,
2365 vsi->nb_used_qps - i);
2367 for (; !!record && i < vsi->nb_used_qps; i++)
2368 intr_handle->intr_vec[queue_idx + i] =
2373 /* vfio 1:1 queue/msix_vect mapping */
2374 __vsi_queues_bind_intr(vsi, msix_vect,
2375 vsi->base_queue + i, 1);
2378 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2386 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2388 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2389 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2390 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2391 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2392 uint16_t msix_intr, i;
2394 if (rte_intr_allow_others(intr_handle))
2395 for (i = 0; i < vsi->nb_used_qps; i++) {
2396 msix_intr = vsi->msix_intr + i;
2397 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2398 GLINT_DYN_CTL_INTENA_M |
2399 GLINT_DYN_CTL_CLEARPBA_M |
2400 GLINT_DYN_CTL_ITR_INDX_M |
2401 GLINT_DYN_CTL_WB_ON_ITR_M);
2404 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2405 GLINT_DYN_CTL_INTENA_M |
2406 GLINT_DYN_CTL_CLEARPBA_M |
2407 GLINT_DYN_CTL_ITR_INDX_M |
2408 GLINT_DYN_CTL_WB_ON_ITR_M);
2412 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2414 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2415 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2416 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2417 struct ice_vsi *vsi = pf->main_vsi;
2418 uint32_t intr_vector = 0;
2420 rte_intr_disable(intr_handle);
2422 /* check and configure queue intr-vector mapping */
2423 if ((rte_intr_cap_multiple(intr_handle) ||
2424 !RTE_ETH_DEV_SRIOV(dev).active) &&
2425 dev->data->dev_conf.intr_conf.rxq != 0) {
2426 intr_vector = dev->data->nb_rx_queues;
2427 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2428 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2429 ICE_MAX_INTR_QUEUE_NUM);
2432 if (rte_intr_efd_enable(intr_handle, intr_vector))
2436 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2437 intr_handle->intr_vec =
2438 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2440 if (!intr_handle->intr_vec) {
2442 "Failed to allocate %d rx_queues intr_vec",
2443 dev->data->nb_rx_queues);
2448 /* Map queues with MSIX interrupt */
2449 vsi->nb_used_qps = dev->data->nb_rx_queues;
2450 ice_vsi_queues_bind_intr(vsi);
2452 /* Enable interrupts for all the queues */
2453 ice_vsi_enable_queues_intr(vsi);
2455 rte_intr_enable(intr_handle);
2461 ice_dev_start(struct rte_eth_dev *dev)
2463 struct rte_eth_dev_data *data = dev->data;
2464 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2466 struct ice_vsi *vsi = pf->main_vsi;
2467 uint16_t nb_rxq = 0;
2471 /* program Tx queues' context in hardware */
2472 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2473 ret = ice_tx_queue_start(dev, nb_txq);
2475 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2480 /* program Rx queues' context in hardware*/
2481 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2482 ret = ice_rx_queue_start(dev, nb_rxq);
2484 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2489 ret = ice_init_rss(pf);
2491 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2495 ice_set_rx_function(dev);
2496 ice_set_tx_function(dev);
2498 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2499 ETH_VLAN_EXTEND_MASK;
2500 ret = ice_vlan_offload_set(dev, mask);
2502 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2506 /* enable Rx interrput and mapping Rx queue to interrupt vector */
2507 if (ice_rxq_intr_setup(dev))
2510 /* Enable receiving broadcast packets and transmitting packets */
2511 ret = ice_set_vsi_promisc(hw, vsi->idx,
2512 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2513 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2515 if (ret != ICE_SUCCESS)
2516 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2518 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2519 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2520 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2521 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2522 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2523 ICE_AQ_LINK_EVENT_AN_COMPLETED |
2524 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2526 if (ret != ICE_SUCCESS)
2527 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2529 ice_dev_set_link_up(dev);
2531 /* Call get_link_info aq commond to enable/disable LSE */
2532 ice_link_update(dev, 0);
2534 pf->adapter_stopped = false;
2538 /* stop the started queues if failed to start all queues */
2540 for (i = 0; i < nb_rxq; i++)
2541 ice_rx_queue_stop(dev, i);
2543 for (i = 0; i < nb_txq; i++)
2544 ice_tx_queue_stop(dev, i);
2550 ice_dev_reset(struct rte_eth_dev *dev)
2554 if (dev->data->sriov.active)
2557 ret = ice_dev_uninit(dev);
2559 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2563 ret = ice_dev_init(dev);
2565 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2573 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2575 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2576 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2577 struct ice_vsi *vsi = pf->main_vsi;
2578 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2579 bool is_safe_mode = pf->adapter->is_safe_mode;
2583 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2584 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2585 dev_info->max_rx_queues = vsi->nb_qps;
2586 dev_info->max_tx_queues = vsi->nb_qps;
2587 dev_info->max_mac_addrs = vsi->max_macaddrs;
2588 dev_info->max_vfs = pci_dev->max_vfs;
2589 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2590 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2592 dev_info->rx_offload_capa =
2593 DEV_RX_OFFLOAD_VLAN_STRIP |
2594 DEV_RX_OFFLOAD_JUMBO_FRAME |
2595 DEV_RX_OFFLOAD_KEEP_CRC |
2596 DEV_RX_OFFLOAD_SCATTER |
2597 DEV_RX_OFFLOAD_VLAN_FILTER;
2598 dev_info->tx_offload_capa =
2599 DEV_TX_OFFLOAD_VLAN_INSERT |
2600 DEV_TX_OFFLOAD_TCP_TSO |
2601 DEV_TX_OFFLOAD_MULTI_SEGS |
2602 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2603 dev_info->flow_type_rss_offloads = 0;
2605 if (!is_safe_mode) {
2606 dev_info->rx_offload_capa |=
2607 DEV_RX_OFFLOAD_IPV4_CKSUM |
2608 DEV_RX_OFFLOAD_UDP_CKSUM |
2609 DEV_RX_OFFLOAD_TCP_CKSUM |
2610 DEV_RX_OFFLOAD_QINQ_STRIP |
2611 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2612 DEV_RX_OFFLOAD_VLAN_EXTEND;
2613 dev_info->tx_offload_capa |=
2614 DEV_TX_OFFLOAD_QINQ_INSERT |
2615 DEV_TX_OFFLOAD_IPV4_CKSUM |
2616 DEV_TX_OFFLOAD_UDP_CKSUM |
2617 DEV_TX_OFFLOAD_TCP_CKSUM |
2618 DEV_TX_OFFLOAD_SCTP_CKSUM |
2619 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2620 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2621 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2624 dev_info->rx_queue_offload_capa = 0;
2625 dev_info->tx_queue_offload_capa = 0;
2627 dev_info->reta_size = pf->hash_lut_size;
2628 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2630 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2632 .pthresh = ICE_DEFAULT_RX_PTHRESH,
2633 .hthresh = ICE_DEFAULT_RX_HTHRESH,
2634 .wthresh = ICE_DEFAULT_RX_WTHRESH,
2636 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2641 dev_info->default_txconf = (struct rte_eth_txconf) {
2643 .pthresh = ICE_DEFAULT_TX_PTHRESH,
2644 .hthresh = ICE_DEFAULT_TX_HTHRESH,
2645 .wthresh = ICE_DEFAULT_TX_WTHRESH,
2647 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2648 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2652 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2653 .nb_max = ICE_MAX_RING_DESC,
2654 .nb_min = ICE_MIN_RING_DESC,
2655 .nb_align = ICE_ALIGN_RING_DESC,
2658 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2659 .nb_max = ICE_MAX_RING_DESC,
2660 .nb_min = ICE_MIN_RING_DESC,
2661 .nb_align = ICE_ALIGN_RING_DESC,
2664 dev_info->speed_capa = ETH_LINK_SPEED_10M |
2665 ETH_LINK_SPEED_100M |
2667 ETH_LINK_SPEED_2_5G |
2669 ETH_LINK_SPEED_10G |
2670 ETH_LINK_SPEED_20G |
2673 phy_type_low = hw->port_info->phy.phy_type_low;
2674 phy_type_high = hw->port_info->phy.phy_type_high;
2676 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2677 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2679 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2680 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2681 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2683 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2684 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2686 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2687 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2688 dev_info->default_rxportconf.nb_queues = 1;
2689 dev_info->default_txportconf.nb_queues = 1;
2690 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2691 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2697 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2698 struct rte_eth_link *link)
2700 struct rte_eth_link *dst = link;
2701 struct rte_eth_link *src = &dev->data->dev_link;
2703 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2704 *(uint64_t *)src) == 0)
2711 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2712 struct rte_eth_link *link)
2714 struct rte_eth_link *dst = &dev->data->dev_link;
2715 struct rte_eth_link *src = link;
2717 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2718 *(uint64_t *)src) == 0)
2725 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2727 #define CHECK_INTERVAL 100 /* 100ms */
2728 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2729 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2730 struct ice_link_status link_status;
2731 struct rte_eth_link link, old;
2733 unsigned int rep_cnt = MAX_REPEAT_TIME;
2734 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2736 memset(&link, 0, sizeof(link));
2737 memset(&old, 0, sizeof(old));
2738 memset(&link_status, 0, sizeof(link_status));
2739 ice_atomic_read_link_status(dev, &old);
2742 /* Get link status information from hardware */
2743 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2744 &link_status, NULL);
2745 if (status != ICE_SUCCESS) {
2746 link.link_speed = ETH_SPEED_NUM_100M;
2747 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2748 PMD_DRV_LOG(ERR, "Failed to get link info");
2752 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2753 if (!wait_to_complete || link.link_status)
2756 rte_delay_ms(CHECK_INTERVAL);
2757 } while (--rep_cnt);
2759 if (!link.link_status)
2762 /* Full-duplex operation at all supported speeds */
2763 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2765 /* Parse the link status */
2766 switch (link_status.link_speed) {
2767 case ICE_AQ_LINK_SPEED_10MB:
2768 link.link_speed = ETH_SPEED_NUM_10M;
2770 case ICE_AQ_LINK_SPEED_100MB:
2771 link.link_speed = ETH_SPEED_NUM_100M;
2773 case ICE_AQ_LINK_SPEED_1000MB:
2774 link.link_speed = ETH_SPEED_NUM_1G;
2776 case ICE_AQ_LINK_SPEED_2500MB:
2777 link.link_speed = ETH_SPEED_NUM_2_5G;
2779 case ICE_AQ_LINK_SPEED_5GB:
2780 link.link_speed = ETH_SPEED_NUM_5G;
2782 case ICE_AQ_LINK_SPEED_10GB:
2783 link.link_speed = ETH_SPEED_NUM_10G;
2785 case ICE_AQ_LINK_SPEED_20GB:
2786 link.link_speed = ETH_SPEED_NUM_20G;
2788 case ICE_AQ_LINK_SPEED_25GB:
2789 link.link_speed = ETH_SPEED_NUM_25G;
2791 case ICE_AQ_LINK_SPEED_40GB:
2792 link.link_speed = ETH_SPEED_NUM_40G;
2794 case ICE_AQ_LINK_SPEED_50GB:
2795 link.link_speed = ETH_SPEED_NUM_50G;
2797 case ICE_AQ_LINK_SPEED_100GB:
2798 link.link_speed = ETH_SPEED_NUM_100G;
2800 case ICE_AQ_LINK_SPEED_UNKNOWN:
2802 PMD_DRV_LOG(ERR, "Unknown link speed");
2803 link.link_speed = ETH_SPEED_NUM_NONE;
2807 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2808 ETH_LINK_SPEED_FIXED);
2811 ice_atomic_write_link_status(dev, &link);
2812 if (link.link_status == old.link_status)
2818 /* Force the physical link state by getting the current PHY capabilities from
2819 * hardware and setting the PHY config based on the determined capabilities. If
2820 * link changes, link event will be triggered because both the Enable Automatic
2821 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2823 static enum ice_status
2824 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2826 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2827 struct ice_aqc_get_phy_caps_data *pcaps;
2828 struct ice_port_info *pi;
2829 enum ice_status status;
2831 if (!hw || !hw->port_info)
2832 return ICE_ERR_PARAM;
2836 pcaps = (struct ice_aqc_get_phy_caps_data *)
2837 ice_malloc(hw, sizeof(*pcaps));
2839 return ICE_ERR_NO_MEMORY;
2841 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2846 /* No change in link */
2847 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2848 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2851 cfg.phy_type_low = pcaps->phy_type_low;
2852 cfg.phy_type_high = pcaps->phy_type_high;
2853 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2854 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2855 cfg.eee_cap = pcaps->eee_cap;
2856 cfg.eeer_value = pcaps->eeer_value;
2857 cfg.link_fec_opt = pcaps->link_fec_options;
2859 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2861 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2863 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2866 ice_free(hw, pcaps);
2871 ice_dev_set_link_up(struct rte_eth_dev *dev)
2873 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2875 return ice_force_phys_link_state(hw, true);
2879 ice_dev_set_link_down(struct rte_eth_dev *dev)
2881 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2883 return ice_force_phys_link_state(hw, false);
2887 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2889 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2890 struct rte_eth_dev_data *dev_data = pf->dev_data;
2891 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2893 /* check if mtu is within the allowed range */
2894 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2897 /* mtu setting is forbidden if port is start */
2898 if (dev_data->dev_started) {
2900 "port %d must be stopped before configuration",
2905 if (frame_size > RTE_ETHER_MAX_LEN)
2906 dev_data->dev_conf.rxmode.offloads |=
2907 DEV_RX_OFFLOAD_JUMBO_FRAME;
2909 dev_data->dev_conf.rxmode.offloads &=
2910 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2912 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2917 static int ice_macaddr_set(struct rte_eth_dev *dev,
2918 struct rte_ether_addr *mac_addr)
2920 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2921 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2922 struct ice_vsi *vsi = pf->main_vsi;
2923 struct ice_mac_filter *f;
2927 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
2928 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2932 TAILQ_FOREACH(f, &vsi->mac_list, next) {
2933 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2938 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2942 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2943 if (ret != ICE_SUCCESS) {
2944 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2947 ret = ice_add_mac_filter(vsi, mac_addr);
2948 if (ret != ICE_SUCCESS) {
2949 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2952 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2954 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2955 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2956 if (ret != ICE_SUCCESS)
2957 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2962 /* Add a MAC address, and update filters */
2964 ice_macaddr_add(struct rte_eth_dev *dev,
2965 struct rte_ether_addr *mac_addr,
2966 __rte_unused uint32_t index,
2967 __rte_unused uint32_t pool)
2969 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2970 struct ice_vsi *vsi = pf->main_vsi;
2973 ret = ice_add_mac_filter(vsi, mac_addr);
2974 if (ret != ICE_SUCCESS) {
2975 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2982 /* Remove a MAC address, and update filters */
2984 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2986 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2987 struct ice_vsi *vsi = pf->main_vsi;
2988 struct rte_eth_dev_data *data = dev->data;
2989 struct rte_ether_addr *macaddr;
2992 macaddr = &data->mac_addrs[index];
2993 ret = ice_remove_mac_filter(vsi, macaddr);
2995 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3001 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3003 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3004 struct ice_vsi *vsi = pf->main_vsi;
3007 PMD_INIT_FUNC_TRACE();
3010 ret = ice_add_vlan_filter(vsi, vlan_id);
3012 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3016 ret = ice_remove_vlan_filter(vsi, vlan_id);
3018 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3026 /* Configure vlan filter on or off */
3028 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3030 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3031 struct ice_vsi_ctx ctxt;
3032 uint8_t sec_flags, sw_flags2;
3035 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3036 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3037 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3040 vsi->info.sec_flags |= sec_flags;
3041 vsi->info.sw_flags2 |= sw_flags2;
3043 vsi->info.sec_flags &= ~sec_flags;
3044 vsi->info.sw_flags2 &= ~sw_flags2;
3046 vsi->info.sw_id = hw->port_info->sw_id;
3047 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3048 ctxt.info.valid_sections =
3049 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3050 ICE_AQ_VSI_PROP_SECURITY_VALID);
3051 ctxt.vsi_num = vsi->vsi_id;
3053 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3055 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3056 on ? "enable" : "disable");
3059 vsi->info.valid_sections |=
3060 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3061 ICE_AQ_VSI_PROP_SECURITY_VALID);
3064 /* consist with other drivers, allow untagged packet when vlan filter on */
3066 ret = ice_add_vlan_filter(vsi, 0);
3068 ret = ice_remove_vlan_filter(vsi, 0);
3074 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3076 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3077 struct ice_vsi_ctx ctxt;
3081 /* Check if it has been already on or off */
3082 if (vsi->info.valid_sections &
3083 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3085 if ((vsi->info.vlan_flags &
3086 ICE_AQ_VSI_VLAN_EMOD_M) ==
3087 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3088 return 0; /* already on */
3090 if ((vsi->info.vlan_flags &
3091 ICE_AQ_VSI_VLAN_EMOD_M) ==
3092 ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3093 return 0; /* already off */
3098 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3100 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3101 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3102 vsi->info.vlan_flags |= vlan_flags;
3103 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3104 ctxt.info.valid_sections =
3105 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3106 ctxt.vsi_num = vsi->vsi_id;
3107 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3109 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3110 on ? "enable" : "disable");
3114 vsi->info.valid_sections |=
3115 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3121 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3123 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3124 struct ice_vsi *vsi = pf->main_vsi;
3125 struct rte_eth_rxmode *rxmode;
3127 rxmode = &dev->data->dev_conf.rxmode;
3128 if (mask & ETH_VLAN_FILTER_MASK) {
3129 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3130 ice_vsi_config_vlan_filter(vsi, TRUE);
3132 ice_vsi_config_vlan_filter(vsi, FALSE);
3135 if (mask & ETH_VLAN_STRIP_MASK) {
3136 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3137 ice_vsi_config_vlan_stripping(vsi, TRUE);
3139 ice_vsi_config_vlan_stripping(vsi, FALSE);
3142 if (mask & ETH_VLAN_EXTEND_MASK) {
3143 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3144 ice_vsi_config_double_vlan(vsi, TRUE);
3146 ice_vsi_config_double_vlan(vsi, FALSE);
3153 ice_vlan_tpid_set(struct rte_eth_dev *dev,
3154 enum rte_vlan_type vlan_type,
3157 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3158 uint64_t reg_r = 0, reg_w = 0;
3159 uint16_t reg_id = 0;
3161 int qinq = dev->data->dev_conf.rxmode.offloads &
3162 DEV_RX_OFFLOAD_VLAN_EXTEND;
3164 switch (vlan_type) {
3165 case ETH_VLAN_TYPE_OUTER:
3171 case ETH_VLAN_TYPE_INNER:
3176 "Unsupported vlan type in single vlan.");
3181 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
3184 reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
3185 PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
3186 "0x%08"PRIx64"", reg_id, reg_r);
3188 reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
3189 reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
3190 if (reg_r == reg_w) {
3191 PMD_DRV_LOG(DEBUG, "No need to write");
3195 ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
3196 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
3197 "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
3203 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3205 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3206 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3212 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3213 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3214 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3216 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3220 uint64_t *lut_dw = (uint64_t *)lut;
3221 uint16_t i, lut_size_dw = lut_size / 4;
3223 for (i = 0; i < lut_size_dw; i++)
3224 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3231 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3240 pf = ICE_VSI_TO_PF(vsi);
3241 hw = ICE_VSI_TO_HW(vsi);
3243 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3244 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3245 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3247 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3251 uint64_t *lut_dw = (uint64_t *)lut;
3252 uint16_t i, lut_size_dw = lut_size / 4;
3254 for (i = 0; i < lut_size_dw; i++)
3255 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3264 ice_rss_reta_update(struct rte_eth_dev *dev,
3265 struct rte_eth_rss_reta_entry64 *reta_conf,
3268 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3269 uint16_t i, lut_size = pf->hash_lut_size;
3270 uint16_t idx, shift;
3274 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3275 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3276 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3278 "The size of hash lookup table configured (%d)"
3279 "doesn't match the number hardware can "
3280 "supported (128, 512, 2048)",
3285 /* It MUST use the current LUT size to get the RSS lookup table,
3286 * otherwise if will fail with -100 error code.
3288 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
3290 PMD_DRV_LOG(ERR, "No memory can be allocated");
3293 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3297 for (i = 0; i < reta_size; i++) {
3298 idx = i / RTE_RETA_GROUP_SIZE;
3299 shift = i % RTE_RETA_GROUP_SIZE;
3300 if (reta_conf[idx].mask & (1ULL << shift))
3301 lut[i] = reta_conf[idx].reta[shift];
3303 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3304 if (ret == 0 && lut_size != reta_size) {
3306 "The size of hash lookup table is changed from (%d) to (%d)",
3307 lut_size, reta_size);
3308 pf->hash_lut_size = reta_size;
3318 ice_rss_reta_query(struct rte_eth_dev *dev,
3319 struct rte_eth_rss_reta_entry64 *reta_conf,
3322 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3323 uint16_t i, lut_size = pf->hash_lut_size;
3324 uint16_t idx, shift;
3328 if (reta_size != lut_size) {
3330 "The size of hash lookup table configured (%d)"
3331 "doesn't match the number hardware can "
3333 reta_size, lut_size);
3337 lut = rte_zmalloc(NULL, reta_size, 0);
3339 PMD_DRV_LOG(ERR, "No memory can be allocated");
3343 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3347 for (i = 0; i < reta_size; i++) {
3348 idx = i / RTE_RETA_GROUP_SIZE;
3349 shift = i % RTE_RETA_GROUP_SIZE;
3350 if (reta_conf[idx].mask & (1ULL << shift))
3351 reta_conf[idx].reta[shift] = lut[i];
3361 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3363 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3366 if (!key || key_len == 0) {
3367 PMD_DRV_LOG(DEBUG, "No key to be configured");
3369 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3371 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3375 struct ice_aqc_get_set_rss_keys *key_dw =
3376 (struct ice_aqc_get_set_rss_keys *)key;
3378 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3380 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3388 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3390 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3393 if (!key || !key_len)
3396 ret = ice_aq_get_rss_key
3398 (struct ice_aqc_get_set_rss_keys *)key);
3400 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3403 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3409 ice_rss_hash_update(struct rte_eth_dev *dev,
3410 struct rte_eth_rss_conf *rss_conf)
3412 enum ice_status status = ICE_SUCCESS;
3413 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3414 struct ice_vsi *vsi = pf->main_vsi;
3417 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3421 /* TODO: hash enable config, ice_add_rss_cfg */
3426 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3427 struct rte_eth_rss_conf *rss_conf)
3429 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3430 struct ice_vsi *vsi = pf->main_vsi;
3432 ice_get_rss_key(vsi, rss_conf->rss_key,
3433 &rss_conf->rss_key_len);
3435 /* TODO: default set to 0 as hf config is not supported now */
3436 rss_conf->rss_hf = 0;
3441 ice_promisc_enable(struct rte_eth_dev *dev)
3443 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3444 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445 struct ice_vsi *vsi = pf->main_vsi;
3446 enum ice_status status;
3450 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3451 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3453 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3455 case ICE_ERR_ALREADY_EXISTS:
3456 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3460 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3468 ice_promisc_disable(struct rte_eth_dev *dev)
3470 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3471 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3472 struct ice_vsi *vsi = pf->main_vsi;
3473 enum ice_status status;
3477 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3478 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3480 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3481 if (status != ICE_SUCCESS) {
3482 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3490 ice_allmulti_enable(struct rte_eth_dev *dev)
3492 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3493 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3494 struct ice_vsi *vsi = pf->main_vsi;
3495 enum ice_status status;
3499 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3501 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3504 case ICE_ERR_ALREADY_EXISTS:
3505 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3509 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3517 ice_allmulti_disable(struct rte_eth_dev *dev)
3519 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3520 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3521 struct ice_vsi *vsi = pf->main_vsi;
3522 enum ice_status status;
3526 if (dev->data->promiscuous == 1)
3527 return 0; /* must remain in all_multicast mode */
3529 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3531 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3532 if (status != ICE_SUCCESS) {
3533 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3540 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3543 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3544 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3545 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3549 msix_intr = intr_handle->intr_vec[queue_id];
3551 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3552 GLINT_DYN_CTL_ITR_INDX_M;
3553 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3555 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3556 rte_intr_ack(&pci_dev->intr_handle);
3561 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3564 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3565 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3566 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3569 msix_intr = intr_handle->intr_vec[queue_id];
3571 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3577 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3579 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3585 full_ver = hw->nvm.oem_ver;
3586 ver = (u8)(full_ver >> 24);
3587 build = (u16)((full_ver >> 8) & 0xffff);
3588 patch = (u8)(full_ver & 0xff);
3590 ret = snprintf(fw_version, fw_size,
3591 "%d.%d%d 0x%08x %d.%d.%d",
3592 ((hw->nvm.ver >> 12) & 0xf),
3593 ((hw->nvm.ver >> 4) & 0xff),
3594 (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3597 /* add the size of '\0' */
3599 if (fw_size < (u32)ret)
3606 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3609 struct ice_vsi_ctx ctxt;
3610 uint8_t vlan_flags = 0;
3613 if (!vsi || !info) {
3614 PMD_DRV_LOG(ERR, "invalid parameters");
3619 vsi->info.pvid = info->config.pvid;
3621 * If insert pvid is enabled, only tagged pkts are
3622 * allowed to be sent out.
3624 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3625 ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3628 if (info->config.reject.tagged == 0)
3629 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3631 if (info->config.reject.untagged == 0)
3632 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3634 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3635 ICE_AQ_VSI_VLAN_MODE_M);
3636 vsi->info.vlan_flags |= vlan_flags;
3637 memset(&ctxt, 0, sizeof(ctxt));
3638 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3639 ctxt.info.valid_sections =
3640 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3641 ctxt.vsi_num = vsi->vsi_id;
3643 hw = ICE_VSI_TO_HW(vsi);
3644 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3645 if (ret != ICE_SUCCESS) {
3647 "update VSI for VLAN insert failed, err %d",
3652 vsi->info.valid_sections |=
3653 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3659 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3661 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3662 struct ice_vsi *vsi = pf->main_vsi;
3663 struct rte_eth_dev_data *data = pf->dev_data;
3664 struct ice_vsi_vlan_pvid_info info;
3667 memset(&info, 0, sizeof(info));
3670 info.config.pvid = pvid;
3672 info.config.reject.tagged =
3673 data->dev_conf.txmode.hw_vlan_reject_tagged;
3674 info.config.reject.untagged =
3675 data->dev_conf.txmode.hw_vlan_reject_untagged;
3678 ret = ice_vsi_vlan_pvid_set(vsi, &info);
3680 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3688 ice_get_eeprom_length(struct rte_eth_dev *dev)
3690 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3692 /* Convert word count to byte count */
3693 return hw->nvm.sr_words << 1;
3697 ice_get_eeprom(struct rte_eth_dev *dev,
3698 struct rte_dev_eeprom_info *eeprom)
3700 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3701 uint16_t *data = eeprom->data;
3702 uint16_t first_word, last_word, nwords;
3703 enum ice_status status = ICE_SUCCESS;
3705 first_word = eeprom->offset >> 1;
3706 last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3707 nwords = last_word - first_word + 1;
3709 if (first_word >= hw->nvm.sr_words ||
3710 last_word >= hw->nvm.sr_words) {
3711 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3715 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3717 status = ice_read_sr_buf(hw, first_word, &nwords, data);
3719 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3720 eeprom->length = sizeof(uint16_t) * nwords;
3728 ice_stat_update_32(struct ice_hw *hw,
3736 new_data = (uint64_t)ICE_READ_REG(hw, reg);
3740 if (new_data >= *offset)
3741 *stat = (uint64_t)(new_data - *offset);
3743 *stat = (uint64_t)((new_data +
3744 ((uint64_t)1 << ICE_32_BIT_WIDTH))
3749 ice_stat_update_40(struct ice_hw *hw,
3758 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3759 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3765 if (new_data >= *offset)
3766 *stat = new_data - *offset;
3768 *stat = (uint64_t)((new_data +
3769 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3772 *stat &= ICE_40_BIT_MASK;
3775 /* Get all the statistics of a VSI */
3777 ice_update_vsi_stats(struct ice_vsi *vsi)
3779 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3780 struct ice_eth_stats *nes = &vsi->eth_stats;
3781 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3782 int idx = rte_le_to_cpu_16(vsi->vsi_id);
3784 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3785 vsi->offset_loaded, &oes->rx_bytes,
3787 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3788 vsi->offset_loaded, &oes->rx_unicast,
3790 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3791 vsi->offset_loaded, &oes->rx_multicast,
3792 &nes->rx_multicast);
3793 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3794 vsi->offset_loaded, &oes->rx_broadcast,
3795 &nes->rx_broadcast);
3796 /* exclude CRC bytes */
3797 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3798 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3800 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3801 &oes->rx_discards, &nes->rx_discards);
3802 /* GLV_REPC not supported */
3803 /* GLV_RMPC not supported */
3804 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3805 &oes->rx_unknown_protocol,
3806 &nes->rx_unknown_protocol);
3807 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3808 vsi->offset_loaded, &oes->tx_bytes,
3810 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3811 vsi->offset_loaded, &oes->tx_unicast,
3813 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3814 vsi->offset_loaded, &oes->tx_multicast,
3815 &nes->tx_multicast);
3816 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3817 vsi->offset_loaded, &oes->tx_broadcast,
3818 &nes->tx_broadcast);
3819 /* GLV_TDPC not supported */
3820 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3821 &oes->tx_errors, &nes->tx_errors);
3822 vsi->offset_loaded = true;
3824 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3826 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3827 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3828 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3829 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3830 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3831 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3832 nes->rx_unknown_protocol);
3833 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3834 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3835 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3836 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3837 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3838 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3839 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3844 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3846 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3847 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3849 /* Get statistics of struct ice_eth_stats */
3850 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3851 GLPRT_GORCL(hw->port_info->lport),
3852 pf->offset_loaded, &os->eth.rx_bytes,
3854 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3855 GLPRT_UPRCL(hw->port_info->lport),
3856 pf->offset_loaded, &os->eth.rx_unicast,
3857 &ns->eth.rx_unicast);
3858 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3859 GLPRT_MPRCL(hw->port_info->lport),
3860 pf->offset_loaded, &os->eth.rx_multicast,
3861 &ns->eth.rx_multicast);
3862 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3863 GLPRT_BPRCL(hw->port_info->lport),
3864 pf->offset_loaded, &os->eth.rx_broadcast,
3865 &ns->eth.rx_broadcast);
3866 ice_stat_update_32(hw, PRTRPB_RDPC,
3867 pf->offset_loaded, &os->eth.rx_discards,
3868 &ns->eth.rx_discards);
3870 /* Workaround: CRC size should not be included in byte statistics,
3871 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3874 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3875 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3877 /* GLPRT_REPC not supported */
3878 /* GLPRT_RMPC not supported */
3879 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3881 &os->eth.rx_unknown_protocol,
3882 &ns->eth.rx_unknown_protocol);
3883 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3884 GLPRT_GOTCL(hw->port_info->lport),
3885 pf->offset_loaded, &os->eth.tx_bytes,
3887 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3888 GLPRT_UPTCL(hw->port_info->lport),
3889 pf->offset_loaded, &os->eth.tx_unicast,
3890 &ns->eth.tx_unicast);
3891 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3892 GLPRT_MPTCL(hw->port_info->lport),
3893 pf->offset_loaded, &os->eth.tx_multicast,
3894 &ns->eth.tx_multicast);
3895 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3896 GLPRT_BPTCL(hw->port_info->lport),
3897 pf->offset_loaded, &os->eth.tx_broadcast,
3898 &ns->eth.tx_broadcast);
3899 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3900 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3902 /* GLPRT_TEPC not supported */
3904 /* additional port specific stats */
3905 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3906 pf->offset_loaded, &os->tx_dropped_link_down,
3907 &ns->tx_dropped_link_down);
3908 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3909 pf->offset_loaded, &os->crc_errors,
3911 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3912 pf->offset_loaded, &os->illegal_bytes,
3913 &ns->illegal_bytes);
3914 /* GLPRT_ERRBC not supported */
3915 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3916 pf->offset_loaded, &os->mac_local_faults,
3917 &ns->mac_local_faults);
3918 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3919 pf->offset_loaded, &os->mac_remote_faults,
3920 &ns->mac_remote_faults);
3922 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3923 pf->offset_loaded, &os->rx_len_errors,
3924 &ns->rx_len_errors);
3926 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3927 pf->offset_loaded, &os->link_xon_rx,
3929 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3930 pf->offset_loaded, &os->link_xoff_rx,
3932 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3933 pf->offset_loaded, &os->link_xon_tx,
3935 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3936 pf->offset_loaded, &os->link_xoff_tx,
3938 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3939 GLPRT_PRC64L(hw->port_info->lport),
3940 pf->offset_loaded, &os->rx_size_64,
3942 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3943 GLPRT_PRC127L(hw->port_info->lport),
3944 pf->offset_loaded, &os->rx_size_127,
3946 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3947 GLPRT_PRC255L(hw->port_info->lport),
3948 pf->offset_loaded, &os->rx_size_255,
3950 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3951 GLPRT_PRC511L(hw->port_info->lport),
3952 pf->offset_loaded, &os->rx_size_511,
3954 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3955 GLPRT_PRC1023L(hw->port_info->lport),
3956 pf->offset_loaded, &os->rx_size_1023,
3958 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3959 GLPRT_PRC1522L(hw->port_info->lport),
3960 pf->offset_loaded, &os->rx_size_1522,
3962 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3963 GLPRT_PRC9522L(hw->port_info->lport),
3964 pf->offset_loaded, &os->rx_size_big,
3966 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3967 pf->offset_loaded, &os->rx_undersize,
3969 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3970 pf->offset_loaded, &os->rx_fragments,
3972 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3973 pf->offset_loaded, &os->rx_oversize,
3975 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3976 pf->offset_loaded, &os->rx_jabber,
3978 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3979 GLPRT_PTC64L(hw->port_info->lport),
3980 pf->offset_loaded, &os->tx_size_64,
3982 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3983 GLPRT_PTC127L(hw->port_info->lport),
3984 pf->offset_loaded, &os->tx_size_127,
3986 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3987 GLPRT_PTC255L(hw->port_info->lport),
3988 pf->offset_loaded, &os->tx_size_255,
3990 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3991 GLPRT_PTC511L(hw->port_info->lport),
3992 pf->offset_loaded, &os->tx_size_511,
3994 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3995 GLPRT_PTC1023L(hw->port_info->lport),
3996 pf->offset_loaded, &os->tx_size_1023,
3998 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3999 GLPRT_PTC1522L(hw->port_info->lport),
4000 pf->offset_loaded, &os->tx_size_1522,
4002 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4003 GLPRT_PTC9522L(hw->port_info->lport),
4004 pf->offset_loaded, &os->tx_size_big,
4007 /* GLPRT_MSPDC not supported */
4008 /* GLPRT_XEC not supported */
4010 pf->offset_loaded = true;
4013 ice_update_vsi_stats(pf->main_vsi);
4016 /* Get all statistics of a port */
4018 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4020 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4021 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4022 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4024 /* call read registers - updates values, now write them to struct */
4025 ice_read_stats_registers(pf, hw);
4027 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4028 pf->main_vsi->eth_stats.rx_multicast +
4029 pf->main_vsi->eth_stats.rx_broadcast -
4030 pf->main_vsi->eth_stats.rx_discards;
4031 stats->opackets = ns->eth.tx_unicast +
4032 ns->eth.tx_multicast +
4033 ns->eth.tx_broadcast;
4034 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
4035 stats->obytes = ns->eth.tx_bytes;
4036 stats->oerrors = ns->eth.tx_errors +
4037 pf->main_vsi->eth_stats.tx_errors;
4040 stats->imissed = ns->eth.rx_discards +
4041 pf->main_vsi->eth_stats.rx_discards;
4042 stats->ierrors = ns->crc_errors +
4044 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4046 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4047 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
4048 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4049 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4050 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4051 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4052 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4053 pf->main_vsi->eth_stats.rx_discards);
4054 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4055 ns->eth.rx_unknown_protocol);
4056 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
4057 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4058 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4059 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4060 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4061 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4062 pf->main_vsi->eth_stats.tx_discards);
4063 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
4065 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
4066 ns->tx_dropped_link_down);
4067 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4068 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
4070 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
4071 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
4072 ns->mac_local_faults);
4073 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
4074 ns->mac_remote_faults);
4075 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
4076 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
4077 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
4078 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
4079 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
4080 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
4081 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
4082 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
4083 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
4084 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
4085 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
4086 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
4087 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
4088 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
4089 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
4090 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
4091 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
4092 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
4093 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
4094 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
4095 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
4096 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
4097 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
4098 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4102 /* Reset the statistics */
4104 ice_stats_reset(struct rte_eth_dev *dev)
4106 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4107 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4109 /* Mark PF and VSI stats to update the offset, aka "reset" */
4110 pf->offset_loaded = false;
4112 pf->main_vsi->offset_loaded = false;
4114 /* read the stats, reading current register values into offset */
4115 ice_read_stats_registers(pf, hw);
4121 ice_xstats_calc_num(void)
4125 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4131 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4134 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4135 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4138 struct ice_hw_port_stats *hw_stats = &pf->stats;
4140 count = ice_xstats_calc_num();
4144 ice_read_stats_registers(pf, hw);
4151 /* Get stats from ice_eth_stats struct */
4152 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4153 xstats[count].value =
4154 *(uint64_t *)((char *)&hw_stats->eth +
4155 ice_stats_strings[i].offset);
4156 xstats[count].id = count;
4160 /* Get individiual stats from ice_hw_port struct */
4161 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4162 xstats[count].value =
4163 *(uint64_t *)((char *)hw_stats +
4164 ice_hw_port_strings[i].offset);
4165 xstats[count].id = count;
4172 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4173 struct rte_eth_xstat_name *xstats_names,
4174 __rte_unused unsigned int limit)
4176 unsigned int count = 0;
4180 return ice_xstats_calc_num();
4182 /* Note: limit checked in rte_eth_xstats_names() */
4184 /* Get stats from ice_eth_stats struct */
4185 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4186 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4187 sizeof(xstats_names[count].name));
4191 /* Get individiual stats from ice_hw_port struct */
4192 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4193 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4194 sizeof(xstats_names[count].name));
4202 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4203 enum rte_filter_type filter_type,
4204 enum rte_filter_op filter_op,
4212 switch (filter_type) {
4213 case RTE_ETH_FILTER_GENERIC:
4214 if (filter_op != RTE_ETH_FILTER_GET)
4216 *(const void **)arg = &ice_flow_ops;
4219 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4228 /* Add UDP tunneling port */
4230 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4231 struct rte_eth_udp_tunnel *udp_tunnel)
4234 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4236 if (udp_tunnel == NULL)
4239 switch (udp_tunnel->prot_type) {
4240 case RTE_TUNNEL_TYPE_VXLAN:
4241 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4244 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4252 /* Delete UDP tunneling port */
4254 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4255 struct rte_eth_udp_tunnel *udp_tunnel)
4258 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4260 if (udp_tunnel == NULL)
4263 switch (udp_tunnel->prot_type) {
4264 case RTE_TUNNEL_TYPE_VXLAN:
4265 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4268 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4277 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4278 struct rte_pci_device *pci_dev)
4280 return rte_eth_dev_pci_generic_probe(pci_dev,
4281 sizeof(struct ice_adapter),
4286 ice_pci_remove(struct rte_pci_device *pci_dev)
4288 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4291 static struct rte_pci_driver rte_ice_pmd = {
4292 .id_table = pci_id_ice_map,
4293 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4294 .probe = ice_pci_probe,
4295 .remove = ice_pci_remove,
4299 * Driver initialization routine.
4300 * Invoked once at EAL init time.
4301 * Register itself as the [Poll Mode] Driver of PCI devices.
4303 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4304 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4305 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4306 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4307 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4308 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4309 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
4311 RTE_INIT(ice_init_log)
4313 ice_logtype_init = rte_log_register("pmd.net.ice.init");
4314 if (ice_logtype_init >= 0)
4315 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4316 ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4317 if (ice_logtype_driver >= 0)
4318 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4320 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4321 ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4322 if (ice_logtype_rx >= 0)
4323 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4326 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4327 ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4328 if (ice_logtype_tx >= 0)
4329 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4332 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4333 ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4334 if (ice_logtype_tx_free >= 0)
4335 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);