1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_ethdev_pci.h>
7 #include "base/ice_sched.h"
8 #include "ice_ethdev.h"
11 #define ICE_MAX_QP_NUM "max_queue_pair_num"
12 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
15 int ice_logtype_driver;
17 static int ice_dev_configure(struct rte_eth_dev *dev);
18 static int ice_dev_start(struct rte_eth_dev *dev);
19 static void ice_dev_stop(struct rte_eth_dev *dev);
20 static void ice_dev_close(struct rte_eth_dev *dev);
21 static int ice_dev_reset(struct rte_eth_dev *dev);
22 static void ice_dev_info_get(struct rte_eth_dev *dev,
23 struct rte_eth_dev_info *dev_info);
24 static int ice_link_update(struct rte_eth_dev *dev,
25 int wait_to_complete);
26 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
27 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
28 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
29 enum rte_vlan_type vlan_type,
31 static int ice_rss_reta_update(struct rte_eth_dev *dev,
32 struct rte_eth_rss_reta_entry64 *reta_conf,
34 static int ice_rss_reta_query(struct rte_eth_dev *dev,
35 struct rte_eth_rss_reta_entry64 *reta_conf,
37 static int ice_rss_hash_update(struct rte_eth_dev *dev,
38 struct rte_eth_rss_conf *rss_conf);
39 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
40 struct rte_eth_rss_conf *rss_conf);
41 static void ice_promisc_enable(struct rte_eth_dev *dev);
42 static void ice_promisc_disable(struct rte_eth_dev *dev);
43 static void ice_allmulti_enable(struct rte_eth_dev *dev);
44 static void ice_allmulti_disable(struct rte_eth_dev *dev);
45 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
48 static int ice_macaddr_set(struct rte_eth_dev *dev,
49 struct ether_addr *mac_addr);
50 static int ice_macaddr_add(struct rte_eth_dev *dev,
51 struct ether_addr *mac_addr,
52 __rte_unused uint32_t index,
54 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
55 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
57 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
59 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
61 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
62 uint16_t pvid, int on);
63 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
64 static int ice_get_eeprom(struct rte_eth_dev *dev,
65 struct rte_dev_eeprom_info *eeprom);
66 static int ice_stats_get(struct rte_eth_dev *dev,
67 struct rte_eth_stats *stats);
68 static void ice_stats_reset(struct rte_eth_dev *dev);
69 static int ice_xstats_get(struct rte_eth_dev *dev,
70 struct rte_eth_xstat *xstats, unsigned int n);
71 static int ice_xstats_get_names(struct rte_eth_dev *dev,
72 struct rte_eth_xstat_name *xstats_names,
75 static const struct rte_pci_id pci_id_ice_map[] = {
76 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
77 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
78 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
79 { .vendor_id = 0, /* sentinel */ },
82 static const struct eth_dev_ops ice_eth_dev_ops = {
83 .dev_configure = ice_dev_configure,
84 .dev_start = ice_dev_start,
85 .dev_stop = ice_dev_stop,
86 .dev_close = ice_dev_close,
87 .dev_reset = ice_dev_reset,
88 .rx_queue_start = ice_rx_queue_start,
89 .rx_queue_stop = ice_rx_queue_stop,
90 .tx_queue_start = ice_tx_queue_start,
91 .tx_queue_stop = ice_tx_queue_stop,
92 .rx_queue_setup = ice_rx_queue_setup,
93 .rx_queue_release = ice_rx_queue_release,
94 .tx_queue_setup = ice_tx_queue_setup,
95 .tx_queue_release = ice_tx_queue_release,
96 .dev_infos_get = ice_dev_info_get,
97 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
98 .link_update = ice_link_update,
99 .mtu_set = ice_mtu_set,
100 .mac_addr_set = ice_macaddr_set,
101 .mac_addr_add = ice_macaddr_add,
102 .mac_addr_remove = ice_macaddr_remove,
103 .vlan_filter_set = ice_vlan_filter_set,
104 .vlan_offload_set = ice_vlan_offload_set,
105 .vlan_tpid_set = ice_vlan_tpid_set,
106 .reta_update = ice_rss_reta_update,
107 .reta_query = ice_rss_reta_query,
108 .rss_hash_update = ice_rss_hash_update,
109 .rss_hash_conf_get = ice_rss_hash_conf_get,
110 .promiscuous_enable = ice_promisc_enable,
111 .promiscuous_disable = ice_promisc_disable,
112 .allmulticast_enable = ice_allmulti_enable,
113 .allmulticast_disable = ice_allmulti_disable,
114 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
115 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
116 .fw_version_get = ice_fw_version_get,
117 .vlan_pvid_set = ice_vlan_pvid_set,
118 .rxq_info_get = ice_rxq_info_get,
119 .txq_info_get = ice_txq_info_get,
120 .get_eeprom_length = ice_get_eeprom_length,
121 .get_eeprom = ice_get_eeprom,
122 .rx_queue_count = ice_rx_queue_count,
123 .rx_descriptor_status = ice_rx_descriptor_status,
124 .tx_descriptor_status = ice_tx_descriptor_status,
125 .stats_get = ice_stats_get,
126 .stats_reset = ice_stats_reset,
127 .xstats_get = ice_xstats_get,
128 .xstats_get_names = ice_xstats_get_names,
129 .xstats_reset = ice_stats_reset,
132 /* store statistics names and its offset in stats structure */
133 struct ice_xstats_name_off {
134 char name[RTE_ETH_XSTATS_NAME_SIZE];
138 static const struct ice_xstats_name_off ice_stats_strings[] = {
139 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
140 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
141 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
142 {"rx_dropped", offsetof(struct ice_eth_stats, rx_discards)},
143 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
144 rx_unknown_protocol)},
145 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
146 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
147 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
148 {"tx_dropped", offsetof(struct ice_eth_stats, tx_discards)},
151 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
152 sizeof(ice_stats_strings[0]))
154 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
155 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
156 tx_dropped_link_down)},
157 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
158 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
160 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
161 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
163 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
165 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
167 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
168 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
169 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
170 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
171 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
172 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
174 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
176 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
178 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
180 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
182 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
184 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
186 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
188 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
189 mac_short_pkt_dropped)},
190 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
192 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
193 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
194 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
196 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
198 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
200 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
202 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
204 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
208 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
209 sizeof(ice_hw_port_strings[0]))
212 ice_init_controlq_parameter(struct ice_hw *hw)
214 /* fields for adminq */
215 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
216 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
217 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
218 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
220 /* fields for mailboxq, DPDK used as PF host */
221 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
222 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
223 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
224 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
228 ice_check_qp_num(const char *key, const char *qp_value,
229 __rte_unused void *opaque)
234 while (isblank(*qp_value))
237 num = strtoul(qp_value, &end, 10);
239 if (!num || (*end == '-') || errno) {
240 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
250 ice_config_max_queue_pair_num(struct rte_devargs *devargs)
252 struct rte_kvargs *kvlist;
253 const char *queue_num_key = ICE_MAX_QP_NUM;
259 kvlist = rte_kvargs_parse(devargs->args, NULL);
263 if (!rte_kvargs_count(kvlist, queue_num_key)) {
264 rte_kvargs_free(kvlist);
268 if (rte_kvargs_process(kvlist, queue_num_key,
269 ice_check_qp_num, NULL) < 0) {
270 rte_kvargs_free(kvlist);
273 ret = rte_kvargs_process(kvlist, queue_num_key,
274 ice_check_qp_num, NULL);
275 rte_kvargs_free(kvlist);
281 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
284 struct pool_entry *entry;
289 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
292 "Failed to allocate memory for resource pool");
296 /* queue heap initialize */
297 pool->num_free = num;
300 LIST_INIT(&pool->alloc_list);
301 LIST_INIT(&pool->free_list);
303 /* Initialize element */
307 LIST_INSERT_HEAD(&pool->free_list, entry, next);
312 ice_res_pool_alloc(struct ice_res_pool_info *pool,
315 struct pool_entry *entry, *valid_entry;
318 PMD_INIT_LOG(ERR, "Invalid parameter");
322 if (pool->num_free < num) {
323 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
324 num, pool->num_free);
329 /* Lookup in free list and find most fit one */
330 LIST_FOREACH(entry, &pool->free_list, next) {
331 if (entry->len >= num) {
333 if (entry->len == num) {
338 valid_entry->len > entry->len)
343 /* Not find one to satisfy the request, return */
345 PMD_INIT_LOG(ERR, "No valid entry found");
349 * The entry have equal queue number as requested,
350 * remove it from alloc_list.
352 if (valid_entry->len == num) {
353 LIST_REMOVE(valid_entry, next);
356 * The entry have more numbers than requested,
357 * create a new entry for alloc_list and minus its
358 * queue base and number in free_list.
360 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
363 "Failed to allocate memory for "
367 entry->base = valid_entry->base;
369 valid_entry->base += num;
370 valid_entry->len -= num;
374 /* Insert it into alloc list, not sorted */
375 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
377 pool->num_free -= valid_entry->len;
378 pool->num_alloc += valid_entry->len;
380 return valid_entry->base + pool->base;
384 ice_res_pool_destroy(struct ice_res_pool_info *pool)
386 struct pool_entry *entry, *next_entry;
391 for (entry = LIST_FIRST(&pool->alloc_list);
392 entry && (next_entry = LIST_NEXT(entry, next), 1);
393 entry = next_entry) {
394 LIST_REMOVE(entry, next);
398 for (entry = LIST_FIRST(&pool->free_list);
399 entry && (next_entry = LIST_NEXT(entry, next), 1);
400 entry = next_entry) {
401 LIST_REMOVE(entry, next);
408 LIST_INIT(&pool->alloc_list);
409 LIST_INIT(&pool->free_list);
413 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
415 /* Set VSI LUT selection */
416 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
417 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
418 /* Set Hash scheme */
419 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
420 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
422 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
425 static enum ice_status
426 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
427 struct ice_aqc_vsi_props *info,
428 uint8_t enabled_tcmap)
430 uint16_t bsf, qp_idx;
432 /* default tc 0 now. Multi-TC supporting need to be done later.
433 * Configure TC and queue mapping parameters, for enabled TC,
434 * allocate qpnum_per_tc queues to this traffic.
436 if (enabled_tcmap != 0x01) {
437 PMD_INIT_LOG(ERR, "only TC0 is supported");
441 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
442 bsf = rte_bsf32(vsi->nb_qps);
443 /* Adjust the queue number to actual queues that can be applied */
444 vsi->nb_qps = 0x1 << bsf;
447 /* Set tc and queue mapping with VSI */
448 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
449 ICE_AQ_VSI_TC_Q_OFFSET_S) |
450 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
452 /* Associate queue number with VSI */
453 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
454 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
455 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
456 info->valid_sections |=
457 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
458 /* Set the info.ingress_table and info.egress_table
459 * for UP translate table. Now just set it to 1:1 map by default
460 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
462 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
463 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
464 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
465 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
470 ice_init_mac_address(struct rte_eth_dev *dev)
472 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
474 if (!is_unicast_ether_addr
475 ((struct ether_addr *)hw->port_info[0].mac.lan_addr)) {
476 PMD_INIT_LOG(ERR, "Invalid MAC address");
480 ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.lan_addr,
481 (struct ether_addr *)hw->port_info[0].mac.perm_addr);
483 dev->data->mac_addrs = rte_zmalloc(NULL, sizeof(struct ether_addr), 0);
484 if (!dev->data->mac_addrs) {
486 "Failed to allocate memory to store mac address");
489 /* store it to dev data */
490 ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.perm_addr,
491 &dev->data->mac_addrs[0]);
495 /* Find out specific MAC filter */
496 static struct ice_mac_filter *
497 ice_find_mac_filter(struct ice_vsi *vsi, struct ether_addr *macaddr)
499 struct ice_mac_filter *f;
501 TAILQ_FOREACH(f, &vsi->mac_list, next) {
502 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
510 ice_add_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr)
512 struct ice_fltr_list_entry *m_list_itr = NULL;
513 struct ice_mac_filter *f;
514 struct LIST_HEAD_TYPE list_head;
515 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
518 /* If it's added and configured, return */
519 f = ice_find_mac_filter(vsi, mac_addr);
521 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
525 INIT_LIST_HEAD(&list_head);
527 m_list_itr = (struct ice_fltr_list_entry *)
528 ice_malloc(hw, sizeof(*m_list_itr));
533 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
534 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
535 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
536 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
537 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
538 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
539 m_list_itr->fltr_info.vsi_handle = vsi->idx;
541 LIST_ADD(&m_list_itr->list_entry, &list_head);
544 ret = ice_add_mac(hw, &list_head);
545 if (ret != ICE_SUCCESS) {
546 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
550 /* Add the mac addr into mac list */
551 f = rte_zmalloc(NULL, sizeof(*f), 0);
553 PMD_DRV_LOG(ERR, "failed to allocate memory");
557 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
558 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
564 rte_free(m_list_itr);
569 ice_remove_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr)
571 struct ice_fltr_list_entry *m_list_itr = NULL;
572 struct ice_mac_filter *f;
573 struct LIST_HEAD_TYPE list_head;
574 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
577 /* Can't find it, return an error */
578 f = ice_find_mac_filter(vsi, mac_addr);
582 INIT_LIST_HEAD(&list_head);
584 m_list_itr = (struct ice_fltr_list_entry *)
585 ice_malloc(hw, sizeof(*m_list_itr));
590 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
591 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
592 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
593 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
594 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
595 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
596 m_list_itr->fltr_info.vsi_handle = vsi->idx;
598 LIST_ADD(&m_list_itr->list_entry, &list_head);
600 /* remove the mac filter */
601 ret = ice_remove_mac(hw, &list_head);
602 if (ret != ICE_SUCCESS) {
603 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
608 /* Remove the mac addr from mac list */
609 TAILQ_REMOVE(&vsi->mac_list, f, next);
615 rte_free(m_list_itr);
619 /* Find out specific VLAN filter */
620 static struct ice_vlan_filter *
621 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
623 struct ice_vlan_filter *f;
625 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
626 if (vlan_id == f->vlan_info.vlan_id)
634 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
636 struct ice_fltr_list_entry *v_list_itr = NULL;
637 struct ice_vlan_filter *f;
638 struct LIST_HEAD_TYPE list_head;
639 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
642 if (!vsi || vlan_id > ETHER_MAX_VLAN_ID)
645 /* If it's added and configured, return. */
646 f = ice_find_vlan_filter(vsi, vlan_id);
648 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
652 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
655 INIT_LIST_HEAD(&list_head);
657 v_list_itr = (struct ice_fltr_list_entry *)
658 ice_malloc(hw, sizeof(*v_list_itr));
663 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
664 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
665 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
666 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
667 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
668 v_list_itr->fltr_info.vsi_handle = vsi->idx;
670 LIST_ADD(&v_list_itr->list_entry, &list_head);
673 ret = ice_add_vlan(hw, &list_head);
674 if (ret != ICE_SUCCESS) {
675 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
680 /* Add vlan into vlan list */
681 f = rte_zmalloc(NULL, sizeof(*f), 0);
683 PMD_DRV_LOG(ERR, "failed to allocate memory");
687 f->vlan_info.vlan_id = vlan_id;
688 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
694 rte_free(v_list_itr);
699 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
701 struct ice_fltr_list_entry *v_list_itr = NULL;
702 struct ice_vlan_filter *f;
703 struct LIST_HEAD_TYPE list_head;
704 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
708 * Vlan 0 is the generic filter for untagged packets
709 * and can't be removed.
711 if (!vsi || vlan_id == 0 || vlan_id > ETHER_MAX_VLAN_ID)
714 /* Can't find it, return an error */
715 f = ice_find_vlan_filter(vsi, vlan_id);
719 INIT_LIST_HEAD(&list_head);
721 v_list_itr = (struct ice_fltr_list_entry *)
722 ice_malloc(hw, sizeof(*v_list_itr));
728 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
729 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
730 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
731 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
732 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
733 v_list_itr->fltr_info.vsi_handle = vsi->idx;
735 LIST_ADD(&v_list_itr->list_entry, &list_head);
737 /* remove the vlan filter */
738 ret = ice_remove_vlan(hw, &list_head);
739 if (ret != ICE_SUCCESS) {
740 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
745 /* Remove the vlan id from vlan list */
746 TAILQ_REMOVE(&vsi->vlan_list, f, next);
752 rte_free(v_list_itr);
757 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
759 struct ice_mac_filter *m_f;
760 struct ice_vlan_filter *v_f;
763 if (!vsi || !vsi->mac_num)
766 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
767 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
768 if (ret != ICE_SUCCESS) {
774 if (vsi->vlan_num == 0)
777 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
778 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
779 if (ret != ICE_SUCCESS) {
790 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
792 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
793 struct ice_vsi_ctx ctxt;
797 /* Check if it has been already on or off */
798 if (vsi->info.valid_sections &
799 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
801 if ((vsi->info.outer_tag_flags &
802 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
803 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
804 return 0; /* already on */
806 if (!(vsi->info.outer_tag_flags &
807 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
808 return 0; /* already off */
813 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
816 /* clear global insertion and use per packet insertion */
817 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
818 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
819 vsi->info.outer_tag_flags |= qinq_flags;
820 /* use default vlan type 0x8100 */
821 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
822 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
823 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
824 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
825 ctxt.info.valid_sections =
826 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
827 ctxt.vsi_num = vsi->vsi_id;
828 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
831 "Update VSI failed to %s qinq stripping",
832 on ? "enable" : "disable");
836 vsi->info.valid_sections |=
837 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
843 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
845 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
846 struct ice_vsi_ctx ctxt;
850 /* Check if it has been already on or off */
851 if (vsi->info.valid_sections &
852 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
854 if ((vsi->info.outer_tag_flags &
855 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
856 ICE_AQ_VSI_OUTER_TAG_COPY)
857 return 0; /* already on */
859 if ((vsi->info.outer_tag_flags &
860 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
861 ICE_AQ_VSI_OUTER_TAG_NOTHING)
862 return 0; /* already off */
867 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
869 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
870 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
871 vsi->info.outer_tag_flags |= qinq_flags;
872 /* use default vlan type 0x8100 */
873 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
874 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
875 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
876 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
877 ctxt.info.valid_sections =
878 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
879 ctxt.vsi_num = vsi->vsi_id;
880 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
883 "Update VSI failed to %s qinq stripping",
884 on ? "enable" : "disable");
888 vsi->info.valid_sections |=
889 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
895 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
899 ret = ice_vsi_config_qinq_stripping(vsi, on);
901 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
903 ret = ice_vsi_config_qinq_insertion(vsi, on);
905 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
912 ice_pf_enable_irq0(struct ice_hw *hw)
914 /* reset the registers */
915 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
916 ICE_READ_REG(hw, PFINT_OICR);
919 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
920 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
921 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
923 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
924 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
925 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
926 PFINT_OICR_CTL_ITR_INDX_M) |
927 PFINT_OICR_CTL_CAUSE_ENA_M);
929 ICE_WRITE_REG(hw, PFINT_FW_CTL,
930 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
931 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
932 PFINT_FW_CTL_ITR_INDX_M) |
933 PFINT_FW_CTL_CAUSE_ENA_M);
935 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
938 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
939 GLINT_DYN_CTL_INTENA_M |
940 GLINT_DYN_CTL_CLEARPBA_M |
941 GLINT_DYN_CTL_ITR_INDX_M);
948 ice_pf_disable_irq0(struct ice_hw *hw)
950 /* Disable all interrupt types */
951 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
957 ice_handle_aq_msg(struct rte_eth_dev *dev)
959 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
960 struct ice_ctl_q_info *cq = &hw->adminq;
961 struct ice_rq_event_info event;
962 uint16_t pending, opcode;
965 event.buf_len = ICE_AQ_MAX_BUF_LEN;
966 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
967 if (!event.msg_buf) {
968 PMD_DRV_LOG(ERR, "Failed to allocate mem");
974 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
976 if (ret != ICE_SUCCESS) {
978 "Failed to read msg from AdminQ, "
980 hw->adminq.sq_last_status);
983 opcode = rte_le_to_cpu_16(event.desc.opcode);
986 case ice_aqc_opc_get_link_status:
987 ret = ice_link_update(dev, 0);
989 _rte_eth_dev_callback_process
990 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
993 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
998 rte_free(event.msg_buf);
1003 * Interrupt handler triggered by NIC for handling
1004 * specific interrupt.
1007 * Pointer to interrupt handle.
1009 * The address of parameter (struct rte_eth_dev *) regsitered before.
1015 ice_interrupt_handler(void *param)
1017 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1018 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1025 uint32_t int_fw_ctl;
1028 /* Disable interrupt */
1029 ice_pf_disable_irq0(hw);
1031 /* read out interrupt causes */
1032 oicr = ICE_READ_REG(hw, PFINT_OICR);
1034 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1037 /* No interrupt event indicated */
1038 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1039 PMD_DRV_LOG(INFO, "No interrupt event");
1044 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1045 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1046 ice_handle_aq_msg(dev);
1049 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1050 PMD_DRV_LOG(INFO, "OICR: link state change event");
1051 ice_link_update(dev, 0);
1055 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1056 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1057 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1058 if (reg & GL_MDET_TX_PQM_VALID_M) {
1059 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1060 GL_MDET_TX_PQM_PF_NUM_S;
1061 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1062 GL_MDET_TX_PQM_MAL_TYPE_S;
1063 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1064 GL_MDET_TX_PQM_QNUM_S;
1066 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1067 "%d by PQM on TX queue %d PF# %d",
1068 event, queue, pf_num);
1071 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1072 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1073 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1074 GL_MDET_TX_TCLAN_PF_NUM_S;
1075 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1076 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1077 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1078 GL_MDET_TX_TCLAN_QNUM_S;
1080 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1081 "%d by TCLAN on TX queue %d PF# %d",
1082 event, queue, pf_num);
1086 /* Enable interrupt */
1087 ice_pf_enable_irq0(hw);
1088 rte_intr_enable(dev->intr_handle);
1091 /* Initialize SW parameters of PF */
1093 ice_pf_sw_init(struct rte_eth_dev *dev)
1095 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1096 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1098 if (ice_config_max_queue_pair_num(dev->device->devargs) > 0)
1100 ice_config_max_queue_pair_num(dev->device->devargs);
1103 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1104 hw->func_caps.common_cap.num_rxq);
1106 pf->lan_nb_qps = pf->lan_nb_qp_max;
1111 static struct ice_vsi *
1112 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1114 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1115 struct ice_vsi *vsi = NULL;
1116 struct ice_vsi_ctx vsi_ctx;
1118 struct ether_addr broadcast = {
1119 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1120 struct ether_addr mac_addr;
1121 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1122 uint8_t tc_bitmap = 0x1;
1124 /* hw->num_lports = 1 in NIC mode */
1125 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1129 vsi->idx = pf->next_vsi_idx;
1132 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1133 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1134 vsi->vlan_anti_spoof_on = 0;
1135 vsi->vlan_filter_on = 1;
1136 TAILQ_INIT(&vsi->mac_list);
1137 TAILQ_INIT(&vsi->vlan_list);
1139 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1140 /* base_queue in used in queue mapping of VSI add/update command.
1141 * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1142 * cases in the first stage. Only Main VSI.
1144 vsi->base_queue = 0;
1147 vsi->nb_qps = pf->lan_nb_qps;
1148 ice_vsi_config_default_rss(&vsi_ctx.info);
1149 vsi_ctx.alloc_from_pool = true;
1150 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1151 /* switch_id is queried by get_switch_config aq, which is done
1154 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1155 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1156 /* Allow all untagged or tagged packets */
1157 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1158 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1159 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1160 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1161 /* Enable VLAN/UP trip */
1162 ret = ice_vsi_config_tc_queue_mapping(vsi,
1167 "tc queue mapping with vsi failed, "
1175 /* for other types of VSI */
1176 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1180 /* VF has MSIX interrupt in VF range, don't allocate here */
1181 if (type == ICE_VSI_PF) {
1182 ret = ice_res_pool_alloc(&pf->msix_pool,
1183 RTE_MIN(vsi->nb_qps,
1184 RTE_MAX_RXTX_INTR_VEC_ID));
1186 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1189 vsi->msix_intr = ret;
1190 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1195 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1196 if (ret != ICE_SUCCESS) {
1197 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1200 /* store vsi information is SW structure */
1201 vsi->vsi_id = vsi_ctx.vsi_num;
1202 vsi->info = vsi_ctx.info;
1203 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1204 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1206 /* MAC configuration */
1207 rte_memcpy(pf->dev_addr.addr_bytes,
1208 hw->port_info->mac.perm_addr,
1211 rte_memcpy(&mac_addr, &pf->dev_addr, ETHER_ADDR_LEN);
1212 ret = ice_add_mac_filter(vsi, &mac_addr);
1213 if (ret != ICE_SUCCESS)
1214 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1216 rte_memcpy(&mac_addr, &broadcast, ETHER_ADDR_LEN);
1217 ret = ice_add_mac_filter(vsi, &mac_addr);
1218 if (ret != ICE_SUCCESS)
1219 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1221 /* At the beginning, only TC0. */
1222 /* What we need here is the maximam number of the TX queues.
1223 * Currently vsi->nb_qps means it.
1224 * Correct it if any change.
1226 max_txqs[0] = vsi->nb_qps;
1227 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1228 tc_bitmap, max_txqs);
1229 if (ret != ICE_SUCCESS)
1230 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1240 ice_pf_setup(struct ice_pf *pf)
1242 struct ice_vsi *vsi;
1244 /* Clear all stats counters */
1245 pf->offset_loaded = FALSE;
1246 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1247 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1248 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1249 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1251 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1253 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1263 ice_dev_init(struct rte_eth_dev *dev)
1265 struct rte_pci_device *pci_dev;
1266 struct rte_intr_handle *intr_handle;
1267 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1268 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1269 struct ice_vsi *vsi;
1272 dev->dev_ops = &ice_eth_dev_ops;
1273 dev->rx_pkt_burst = ice_recv_pkts;
1274 dev->tx_pkt_burst = ice_xmit_pkts;
1275 dev->tx_pkt_prepare = ice_prep_pkts;
1277 ice_set_default_ptype_table(dev);
1278 pci_dev = RTE_DEV_TO_PCI(dev->device);
1279 intr_handle = &pci_dev->intr_handle;
1281 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1282 pf->adapter->eth_dev = dev;
1283 pf->dev_data = dev->data;
1284 hw->back = pf->adapter;
1285 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1286 hw->vendor_id = pci_dev->id.vendor_id;
1287 hw->device_id = pci_dev->id.device_id;
1288 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1289 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1290 hw->bus.device = pci_dev->addr.devid;
1291 hw->bus.func = pci_dev->addr.function;
1293 ice_init_controlq_parameter(hw);
1295 ret = ice_init_hw(hw);
1297 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1301 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1302 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1303 hw->api_maj_ver, hw->api_min_ver);
1305 ice_pf_sw_init(dev);
1306 ret = ice_init_mac_address(dev);
1308 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1312 ret = ice_res_pool_init(&pf->msix_pool, 1,
1313 hw->func_caps.common_cap.num_msix_vectors - 1);
1315 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1316 goto err_msix_pool_init;
1319 ret = ice_pf_setup(pf);
1321 PMD_INIT_LOG(ERR, "Failed to setup PF");
1327 /* Disable double vlan by default */
1328 ice_vsi_config_double_vlan(vsi, FALSE);
1330 /* register callback func to eal lib */
1331 rte_intr_callback_register(intr_handle,
1332 ice_interrupt_handler, dev);
1334 ice_pf_enable_irq0(hw);
1336 /* enable uio intr after callback register */
1337 rte_intr_enable(intr_handle);
1342 ice_res_pool_destroy(&pf->msix_pool);
1344 rte_free(dev->data->mac_addrs);
1346 ice_sched_cleanup_all(hw);
1347 rte_free(hw->port_info);
1348 ice_shutdown_all_ctrlq(hw);
1354 ice_release_vsi(struct ice_vsi *vsi)
1357 struct ice_vsi_ctx vsi_ctx;
1358 enum ice_status ret;
1363 hw = ICE_VSI_TO_HW(vsi);
1365 ice_remove_all_mac_vlan_filters(vsi);
1367 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1369 vsi_ctx.vsi_num = vsi->vsi_id;
1370 vsi_ctx.info = vsi->info;
1371 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
1372 if (ret != ICE_SUCCESS) {
1373 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
1383 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
1385 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1386 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1387 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1388 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1389 uint16_t msix_intr, i;
1391 /* disable interrupt and also clear all the exist config */
1392 for (i = 0; i < vsi->nb_qps; i++) {
1393 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1394 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1398 if (rte_intr_allow_others(intr_handle))
1400 for (i = 0; i < vsi->nb_msix; i++) {
1401 msix_intr = vsi->msix_intr + i;
1402 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1403 GLINT_DYN_CTL_WB_ON_ITR_M);
1407 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1411 ice_dev_stop(struct rte_eth_dev *dev)
1413 struct rte_eth_dev_data *data = dev->data;
1414 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1415 struct ice_vsi *main_vsi = pf->main_vsi;
1416 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1417 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1420 /* avoid stopping again */
1421 if (pf->adapter_stopped)
1424 /* stop and clear all Rx queues */
1425 for (i = 0; i < data->nb_rx_queues; i++)
1426 ice_rx_queue_stop(dev, i);
1428 /* stop and clear all Tx queues */
1429 for (i = 0; i < data->nb_tx_queues; i++)
1430 ice_tx_queue_stop(dev, i);
1432 /* disable all queue interrupts */
1433 ice_vsi_disable_queues_intr(main_vsi);
1435 /* Clear all queues and release mbufs */
1436 ice_clear_queues(dev);
1438 /* Clean datapath event and queue/vec mapping */
1439 rte_intr_efd_disable(intr_handle);
1440 if (intr_handle->intr_vec) {
1441 rte_free(intr_handle->intr_vec);
1442 intr_handle->intr_vec = NULL;
1445 pf->adapter_stopped = true;
1449 ice_dev_close(struct rte_eth_dev *dev)
1451 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1452 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1456 /* release all queue resource */
1457 ice_free_queues(dev);
1459 ice_res_pool_destroy(&pf->msix_pool);
1460 ice_release_vsi(pf->main_vsi);
1462 ice_shutdown_all_ctrlq(hw);
1466 ice_dev_uninit(struct rte_eth_dev *dev)
1468 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1469 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1470 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1471 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1475 dev->dev_ops = NULL;
1476 dev->rx_pkt_burst = NULL;
1477 dev->tx_pkt_burst = NULL;
1479 rte_free(dev->data->mac_addrs);
1480 dev->data->mac_addrs = NULL;
1482 /* disable uio intr before callback unregister */
1483 rte_intr_disable(intr_handle);
1485 /* register callback func to eal lib */
1486 rte_intr_callback_unregister(intr_handle,
1487 ice_interrupt_handler, dev);
1489 ice_release_vsi(pf->main_vsi);
1490 ice_sched_cleanup_all(hw);
1491 rte_free(hw->port_info);
1492 ice_shutdown_all_ctrlq(hw);
1498 ice_dev_configure(__rte_unused struct rte_eth_dev *dev)
1500 struct ice_adapter *ad =
1501 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1503 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1504 * bulk allocation or vector Rx preconditions we will reset it.
1506 ad->rx_bulk_alloc_allowed = true;
1507 ad->tx_simple_allowed = true;
1512 static int ice_init_rss(struct ice_pf *pf)
1514 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1515 struct ice_vsi *vsi = pf->main_vsi;
1516 struct rte_eth_dev *dev = pf->adapter->eth_dev;
1517 struct rte_eth_rss_conf *rss_conf;
1518 struct ice_aqc_get_set_rss_keys key;
1522 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1523 nb_q = dev->data->nb_rx_queues;
1524 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1525 vsi->rss_lut_size = hw->func_caps.common_cap.rss_table_size;
1528 vsi->rss_key = rte_zmalloc(NULL,
1529 vsi->rss_key_size, 0);
1531 vsi->rss_lut = rte_zmalloc(NULL,
1532 vsi->rss_lut_size, 0);
1534 /* configure RSS key */
1535 if (!rss_conf->rss_key) {
1536 /* Calculate the default hash key */
1537 for (i = 0; i <= vsi->rss_key_size; i++)
1538 vsi->rss_key[i] = (uint8_t)rte_rand();
1540 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1541 RTE_MIN(rss_conf->rss_key_len,
1542 vsi->rss_key_size));
1544 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1545 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1549 /* init RSS LUT table */
1550 for (i = 0; i < vsi->rss_lut_size; i++)
1551 vsi->rss_lut[i] = i % nb_q;
1553 ret = ice_aq_set_rss_lut(hw, vsi->idx,
1554 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1555 vsi->rss_lut, vsi->rss_lut_size);
1563 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
1564 int base_queue, int nb_queue)
1566 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1567 uint32_t val, val_tx;
1570 for (i = 0; i < nb_queue; i++) {
1572 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
1573 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
1574 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
1575 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
1577 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
1578 base_queue + i, msix_vect);
1579 /* set ITR0 value */
1580 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
1581 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
1582 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
1587 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
1589 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1590 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1591 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1592 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1593 uint16_t msix_vect = vsi->msix_intr;
1594 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1595 uint16_t queue_idx = 0;
1599 /* clear Rx/Tx queue interrupt */
1600 for (i = 0; i < vsi->nb_used_qps; i++) {
1601 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1602 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1605 /* PF bind interrupt */
1606 if (rte_intr_dp_is_en(intr_handle)) {
1611 for (i = 0; i < vsi->nb_used_qps; i++) {
1613 if (!rte_intr_allow_others(intr_handle))
1614 msix_vect = ICE_MISC_VEC_ID;
1616 /* uio mapping all queue to one msix_vect */
1617 __vsi_queues_bind_intr(vsi, msix_vect,
1618 vsi->base_queue + i,
1619 vsi->nb_used_qps - i);
1621 for (; !!record && i < vsi->nb_used_qps; i++)
1622 intr_handle->intr_vec[queue_idx + i] =
1627 /* vfio 1:1 queue/msix_vect mapping */
1628 __vsi_queues_bind_intr(vsi, msix_vect,
1629 vsi->base_queue + i, 1);
1632 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1640 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
1642 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1643 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1644 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1645 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1646 uint16_t msix_intr, i;
1648 if (rte_intr_allow_others(intr_handle))
1649 for (i = 0; i < vsi->nb_used_qps; i++) {
1650 msix_intr = vsi->msix_intr + i;
1651 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1652 GLINT_DYN_CTL_INTENA_M |
1653 GLINT_DYN_CTL_CLEARPBA_M |
1654 GLINT_DYN_CTL_ITR_INDX_M |
1655 GLINT_DYN_CTL_WB_ON_ITR_M);
1658 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1659 GLINT_DYN_CTL_INTENA_M |
1660 GLINT_DYN_CTL_CLEARPBA_M |
1661 GLINT_DYN_CTL_ITR_INDX_M |
1662 GLINT_DYN_CTL_WB_ON_ITR_M);
1666 ice_rxq_intr_setup(struct rte_eth_dev *dev)
1668 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1669 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1670 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1671 struct ice_vsi *vsi = pf->main_vsi;
1672 uint32_t intr_vector = 0;
1674 rte_intr_disable(intr_handle);
1676 /* check and configure queue intr-vector mapping */
1677 if ((rte_intr_cap_multiple(intr_handle) ||
1678 !RTE_ETH_DEV_SRIOV(dev).active) &&
1679 dev->data->dev_conf.intr_conf.rxq != 0) {
1680 intr_vector = dev->data->nb_rx_queues;
1681 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
1682 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
1683 ICE_MAX_INTR_QUEUE_NUM);
1686 if (rte_intr_efd_enable(intr_handle, intr_vector))
1690 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1691 intr_handle->intr_vec =
1692 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
1694 if (!intr_handle->intr_vec) {
1696 "Failed to allocate %d rx_queues intr_vec",
1697 dev->data->nb_rx_queues);
1702 /* Map queues with MSIX interrupt */
1703 vsi->nb_used_qps = dev->data->nb_rx_queues;
1704 ice_vsi_queues_bind_intr(vsi);
1706 /* Enable interrupts for all the queues */
1707 ice_vsi_enable_queues_intr(vsi);
1709 rte_intr_enable(intr_handle);
1715 ice_dev_start(struct rte_eth_dev *dev)
1717 struct rte_eth_dev_data *data = dev->data;
1718 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1720 struct ice_vsi *vsi = pf->main_vsi;
1721 uint16_t nb_rxq = 0;
1725 /* program Tx queues' context in hardware */
1726 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
1727 ret = ice_tx_queue_start(dev, nb_txq);
1729 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
1734 /* program Rx queues' context in hardware*/
1735 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
1736 ret = ice_rx_queue_start(dev, nb_rxq);
1738 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
1743 ret = ice_init_rss(pf);
1745 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
1749 ice_set_rx_function(dev);
1751 /* enable Rx interrput and mapping Rx queue to interrupt vector */
1752 if (ice_rxq_intr_setup(dev))
1755 /* Enable receiving broadcast packets and transmitting packets */
1756 ret = ice_set_vsi_promisc(hw, vsi->idx,
1757 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
1758 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
1760 if (ret != ICE_SUCCESS)
1761 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1763 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
1764 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
1765 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
1766 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
1767 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
1768 ICE_AQ_LINK_EVENT_AN_COMPLETED |
1769 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
1771 if (ret != ICE_SUCCESS)
1772 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1774 /* Call get_link_info aq commond to enable/disable LSE */
1775 ice_link_update(dev, 0);
1777 pf->adapter_stopped = false;
1781 /* stop the started queues if failed to start all queues */
1783 for (i = 0; i < nb_rxq; i++)
1784 ice_rx_queue_stop(dev, i);
1786 for (i = 0; i < nb_txq; i++)
1787 ice_tx_queue_stop(dev, i);
1793 ice_dev_reset(struct rte_eth_dev *dev)
1797 if (dev->data->sriov.active)
1800 ret = ice_dev_uninit(dev);
1802 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
1806 ret = ice_dev_init(dev);
1808 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
1816 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1818 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1819 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1820 struct ice_vsi *vsi = pf->main_vsi;
1821 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1823 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
1824 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
1825 dev_info->max_rx_queues = vsi->nb_qps;
1826 dev_info->max_tx_queues = vsi->nb_qps;
1827 dev_info->max_mac_addrs = vsi->max_macaddrs;
1828 dev_info->max_vfs = pci_dev->max_vfs;
1830 dev_info->rx_offload_capa =
1831 DEV_RX_OFFLOAD_VLAN_STRIP |
1832 DEV_RX_OFFLOAD_IPV4_CKSUM |
1833 DEV_RX_OFFLOAD_UDP_CKSUM |
1834 DEV_RX_OFFLOAD_TCP_CKSUM |
1835 DEV_RX_OFFLOAD_QINQ_STRIP |
1836 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1837 DEV_RX_OFFLOAD_VLAN_EXTEND |
1838 DEV_RX_OFFLOAD_JUMBO_FRAME |
1839 DEV_RX_OFFLOAD_KEEP_CRC |
1840 DEV_RX_OFFLOAD_SCATTER |
1841 DEV_RX_OFFLOAD_VLAN_FILTER;
1842 dev_info->tx_offload_capa =
1843 DEV_TX_OFFLOAD_VLAN_INSERT |
1844 DEV_TX_OFFLOAD_QINQ_INSERT |
1845 DEV_TX_OFFLOAD_IPV4_CKSUM |
1846 DEV_TX_OFFLOAD_UDP_CKSUM |
1847 DEV_TX_OFFLOAD_TCP_CKSUM |
1848 DEV_TX_OFFLOAD_SCTP_CKSUM |
1849 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1850 DEV_TX_OFFLOAD_TCP_TSO |
1851 DEV_TX_OFFLOAD_MULTI_SEGS |
1852 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1853 dev_info->rx_queue_offload_capa = 0;
1854 dev_info->tx_queue_offload_capa = 0;
1856 dev_info->reta_size = hw->func_caps.common_cap.rss_table_size;
1857 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
1858 dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL;
1860 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1862 .pthresh = ICE_DEFAULT_RX_PTHRESH,
1863 .hthresh = ICE_DEFAULT_RX_HTHRESH,
1864 .wthresh = ICE_DEFAULT_RX_WTHRESH,
1866 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
1871 dev_info->default_txconf = (struct rte_eth_txconf) {
1873 .pthresh = ICE_DEFAULT_TX_PTHRESH,
1874 .hthresh = ICE_DEFAULT_TX_HTHRESH,
1875 .wthresh = ICE_DEFAULT_TX_WTHRESH,
1877 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
1878 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
1882 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1883 .nb_max = ICE_MAX_RING_DESC,
1884 .nb_min = ICE_MIN_RING_DESC,
1885 .nb_align = ICE_ALIGN_RING_DESC,
1888 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1889 .nb_max = ICE_MAX_RING_DESC,
1890 .nb_min = ICE_MIN_RING_DESC,
1891 .nb_align = ICE_ALIGN_RING_DESC,
1894 dev_info->speed_capa = ETH_LINK_SPEED_10M |
1895 ETH_LINK_SPEED_100M |
1897 ETH_LINK_SPEED_2_5G |
1899 ETH_LINK_SPEED_10G |
1900 ETH_LINK_SPEED_20G |
1901 ETH_LINK_SPEED_25G |
1904 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
1905 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
1907 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
1908 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
1909 dev_info->default_rxportconf.nb_queues = 1;
1910 dev_info->default_txportconf.nb_queues = 1;
1911 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
1912 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
1916 ice_atomic_read_link_status(struct rte_eth_dev *dev,
1917 struct rte_eth_link *link)
1919 struct rte_eth_link *dst = link;
1920 struct rte_eth_link *src = &dev->data->dev_link;
1922 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1923 *(uint64_t *)src) == 0)
1930 ice_atomic_write_link_status(struct rte_eth_dev *dev,
1931 struct rte_eth_link *link)
1933 struct rte_eth_link *dst = &dev->data->dev_link;
1934 struct rte_eth_link *src = link;
1936 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1937 *(uint64_t *)src) == 0)
1944 ice_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
1946 #define CHECK_INTERVAL 100 /* 100ms */
1947 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1948 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949 struct ice_link_status link_status;
1950 struct rte_eth_link link, old;
1952 unsigned int rep_cnt = MAX_REPEAT_TIME;
1953 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
1955 memset(&link, 0, sizeof(link));
1956 memset(&old, 0, sizeof(old));
1957 memset(&link_status, 0, sizeof(link_status));
1958 ice_atomic_read_link_status(dev, &old);
1961 /* Get link status information from hardware */
1962 status = ice_aq_get_link_info(hw->port_info, enable_lse,
1963 &link_status, NULL);
1964 if (status != ICE_SUCCESS) {
1965 link.link_speed = ETH_SPEED_NUM_100M;
1966 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1967 PMD_DRV_LOG(ERR, "Failed to get link info");
1971 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
1972 if (!wait_to_complete || link.link_status)
1975 rte_delay_ms(CHECK_INTERVAL);
1976 } while (--rep_cnt);
1978 if (!link.link_status)
1981 /* Full-duplex operation at all supported speeds */
1982 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1984 /* Parse the link status */
1985 switch (link_status.link_speed) {
1986 case ICE_AQ_LINK_SPEED_10MB:
1987 link.link_speed = ETH_SPEED_NUM_10M;
1989 case ICE_AQ_LINK_SPEED_100MB:
1990 link.link_speed = ETH_SPEED_NUM_100M;
1992 case ICE_AQ_LINK_SPEED_1000MB:
1993 link.link_speed = ETH_SPEED_NUM_1G;
1995 case ICE_AQ_LINK_SPEED_2500MB:
1996 link.link_speed = ETH_SPEED_NUM_2_5G;
1998 case ICE_AQ_LINK_SPEED_5GB:
1999 link.link_speed = ETH_SPEED_NUM_5G;
2001 case ICE_AQ_LINK_SPEED_10GB:
2002 link.link_speed = ETH_SPEED_NUM_10G;
2004 case ICE_AQ_LINK_SPEED_20GB:
2005 link.link_speed = ETH_SPEED_NUM_20G;
2007 case ICE_AQ_LINK_SPEED_25GB:
2008 link.link_speed = ETH_SPEED_NUM_25G;
2010 case ICE_AQ_LINK_SPEED_40GB:
2011 link.link_speed = ETH_SPEED_NUM_40G;
2013 case ICE_AQ_LINK_SPEED_UNKNOWN:
2015 PMD_DRV_LOG(ERR, "Unknown link speed");
2016 link.link_speed = ETH_SPEED_NUM_NONE;
2020 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2021 ETH_LINK_SPEED_FIXED);
2024 ice_atomic_write_link_status(dev, &link);
2025 if (link.link_status == old.link_status)
2032 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2034 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2035 struct rte_eth_dev_data *dev_data = pf->dev_data;
2036 uint32_t frame_size = mtu + ETHER_HDR_LEN
2037 + ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE;
2039 /* check if mtu is within the allowed range */
2040 if (mtu < ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2043 /* mtu setting is forbidden if port is start */
2044 if (dev_data->dev_started) {
2046 "port %d must be stopped before configuration",
2051 if (frame_size > ETHER_MAX_LEN)
2052 dev_data->dev_conf.rxmode.offloads |=
2053 DEV_RX_OFFLOAD_JUMBO_FRAME;
2055 dev_data->dev_conf.rxmode.offloads &=
2056 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2058 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2063 static int ice_macaddr_set(struct rte_eth_dev *dev,
2064 struct ether_addr *mac_addr)
2066 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2068 struct ice_vsi *vsi = pf->main_vsi;
2069 struct ice_mac_filter *f;
2073 if (!is_valid_assigned_ether_addr(mac_addr)) {
2074 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2078 TAILQ_FOREACH(f, &vsi->mac_list, next) {
2079 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2084 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2088 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2089 if (ret != ICE_SUCCESS) {
2090 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2093 ret = ice_add_mac_filter(vsi, mac_addr);
2094 if (ret != ICE_SUCCESS) {
2095 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2098 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2100 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2101 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2102 if (ret != ICE_SUCCESS)
2103 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2108 /* Add a MAC address, and update filters */
2110 ice_macaddr_add(struct rte_eth_dev *dev,
2111 struct ether_addr *mac_addr,
2112 __rte_unused uint32_t index,
2113 __rte_unused uint32_t pool)
2115 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2116 struct ice_vsi *vsi = pf->main_vsi;
2119 ret = ice_add_mac_filter(vsi, mac_addr);
2120 if (ret != ICE_SUCCESS) {
2121 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2128 /* Remove a MAC address, and update filters */
2130 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2132 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2133 struct ice_vsi *vsi = pf->main_vsi;
2134 struct rte_eth_dev_data *data = dev->data;
2135 struct ether_addr *macaddr;
2138 macaddr = &data->mac_addrs[index];
2139 ret = ice_remove_mac_filter(vsi, macaddr);
2141 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2147 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2149 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2150 struct ice_vsi *vsi = pf->main_vsi;
2153 PMD_INIT_FUNC_TRACE();
2156 ret = ice_add_vlan_filter(vsi, vlan_id);
2158 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2162 ret = ice_remove_vlan_filter(vsi, vlan_id);
2164 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2172 /* Configure vlan filter on or off */
2174 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2176 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2177 struct ice_vsi_ctx ctxt;
2178 uint8_t sec_flags, sw_flags2;
2181 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2182 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2183 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2186 vsi->info.sec_flags |= sec_flags;
2187 vsi->info.sw_flags2 |= sw_flags2;
2189 vsi->info.sec_flags &= ~sec_flags;
2190 vsi->info.sw_flags2 &= ~sw_flags2;
2192 vsi->info.sw_id = hw->port_info->sw_id;
2193 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2194 ctxt.info.valid_sections =
2195 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2196 ICE_AQ_VSI_PROP_SECURITY_VALID);
2197 ctxt.vsi_num = vsi->vsi_id;
2199 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2201 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
2202 on ? "enable" : "disable");
2205 vsi->info.valid_sections |=
2206 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2207 ICE_AQ_VSI_PROP_SECURITY_VALID);
2210 /* consist with other drivers, allow untagged packet when vlan filter on */
2212 ret = ice_add_vlan_filter(vsi, 0);
2214 ret = ice_remove_vlan_filter(vsi, 0);
2220 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
2222 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2223 struct ice_vsi_ctx ctxt;
2227 /* Check if it has been already on or off */
2228 if (vsi->info.valid_sections &
2229 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
2231 if ((vsi->info.vlan_flags &
2232 ICE_AQ_VSI_VLAN_EMOD_M) ==
2233 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
2234 return 0; /* already on */
2236 if ((vsi->info.vlan_flags &
2237 ICE_AQ_VSI_VLAN_EMOD_M) ==
2238 ICE_AQ_VSI_VLAN_EMOD_NOTHING)
2239 return 0; /* already off */
2244 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2246 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2247 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
2248 vsi->info.vlan_flags |= vlan_flags;
2249 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2250 ctxt.info.valid_sections =
2251 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2252 ctxt.vsi_num = vsi->vsi_id;
2253 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2255 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2256 on ? "enable" : "disable");
2260 vsi->info.valid_sections |=
2261 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2267 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2269 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2270 struct ice_vsi *vsi = pf->main_vsi;
2271 struct rte_eth_rxmode *rxmode;
2273 rxmode = &dev->data->dev_conf.rxmode;
2274 if (mask & ETH_VLAN_FILTER_MASK) {
2275 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2276 ice_vsi_config_vlan_filter(vsi, TRUE);
2278 ice_vsi_config_vlan_filter(vsi, FALSE);
2281 if (mask & ETH_VLAN_STRIP_MASK) {
2282 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2283 ice_vsi_config_vlan_stripping(vsi, TRUE);
2285 ice_vsi_config_vlan_stripping(vsi, FALSE);
2288 if (mask & ETH_VLAN_EXTEND_MASK) {
2289 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2290 ice_vsi_config_double_vlan(vsi, TRUE);
2292 ice_vsi_config_double_vlan(vsi, FALSE);
2299 ice_vlan_tpid_set(struct rte_eth_dev *dev,
2300 enum rte_vlan_type vlan_type,
2303 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2304 uint64_t reg_r = 0, reg_w = 0;
2305 uint16_t reg_id = 0;
2307 int qinq = dev->data->dev_conf.rxmode.offloads &
2308 DEV_RX_OFFLOAD_VLAN_EXTEND;
2310 switch (vlan_type) {
2311 case ETH_VLAN_TYPE_OUTER:
2317 case ETH_VLAN_TYPE_INNER:
2322 "Unsupported vlan type in single vlan.");
2327 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2330 reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
2331 PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
2332 "0x%08"PRIx64"", reg_id, reg_r);
2334 reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
2335 reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
2336 if (reg_r == reg_w) {
2337 PMD_DRV_LOG(DEBUG, "No need to write");
2341 ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
2342 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2343 "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2349 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2351 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2352 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2358 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2359 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
2362 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2366 uint64_t *lut_dw = (uint64_t *)lut;
2367 uint16_t i, lut_size_dw = lut_size / 4;
2369 for (i = 0; i < lut_size_dw; i++)
2370 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
2377 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2379 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2380 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2386 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2387 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
2390 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2394 uint64_t *lut_dw = (uint64_t *)lut;
2395 uint16_t i, lut_size_dw = lut_size / 4;
2397 for (i = 0; i < lut_size_dw; i++)
2398 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
2407 ice_rss_reta_update(struct rte_eth_dev *dev,
2408 struct rte_eth_rss_reta_entry64 *reta_conf,
2411 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2412 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2413 uint16_t i, lut_size = hw->func_caps.common_cap.rss_table_size;
2414 uint16_t idx, shift;
2418 if (reta_size != lut_size ||
2419 reta_size > ETH_RSS_RETA_SIZE_512) {
2421 "The size of hash lookup table configured (%d)"
2422 "doesn't match the number hardware can "
2424 reta_size, lut_size);
2428 lut = rte_zmalloc(NULL, reta_size, 0);
2430 PMD_DRV_LOG(ERR, "No memory can be allocated");
2433 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2437 for (i = 0; i < reta_size; i++) {
2438 idx = i / RTE_RETA_GROUP_SIZE;
2439 shift = i % RTE_RETA_GROUP_SIZE;
2440 if (reta_conf[idx].mask & (1ULL << shift))
2441 lut[i] = reta_conf[idx].reta[shift];
2443 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
2452 ice_rss_reta_query(struct rte_eth_dev *dev,
2453 struct rte_eth_rss_reta_entry64 *reta_conf,
2456 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2457 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2458 uint16_t i, lut_size = hw->func_caps.common_cap.rss_table_size;
2459 uint16_t idx, shift;
2463 if (reta_size != lut_size ||
2464 reta_size > ETH_RSS_RETA_SIZE_512) {
2466 "The size of hash lookup table configured (%d)"
2467 "doesn't match the number hardware can "
2469 reta_size, lut_size);
2473 lut = rte_zmalloc(NULL, reta_size, 0);
2475 PMD_DRV_LOG(ERR, "No memory can be allocated");
2479 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2483 for (i = 0; i < reta_size; i++) {
2484 idx = i / RTE_RETA_GROUP_SIZE;
2485 shift = i % RTE_RETA_GROUP_SIZE;
2486 if (reta_conf[idx].mask & (1ULL << shift))
2487 reta_conf[idx].reta[shift] = lut[i];
2497 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
2499 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2502 if (!key || key_len == 0) {
2503 PMD_DRV_LOG(DEBUG, "No key to be configured");
2505 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
2507 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2511 struct ice_aqc_get_set_rss_keys *key_dw =
2512 (struct ice_aqc_get_set_rss_keys *)key;
2514 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
2516 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
2524 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
2526 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2529 if (!key || !key_len)
2532 ret = ice_aq_get_rss_key
2534 (struct ice_aqc_get_set_rss_keys *)key);
2536 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
2539 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2545 ice_rss_hash_update(struct rte_eth_dev *dev,
2546 struct rte_eth_rss_conf *rss_conf)
2548 enum ice_status status = ICE_SUCCESS;
2549 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2550 struct ice_vsi *vsi = pf->main_vsi;
2553 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
2557 /* TODO: hash enable config, ice_add_rss_cfg */
2562 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
2563 struct rte_eth_rss_conf *rss_conf)
2565 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2566 struct ice_vsi *vsi = pf->main_vsi;
2568 ice_get_rss_key(vsi, rss_conf->rss_key,
2569 &rss_conf->rss_key_len);
2571 /* TODO: default set to 0 as hf config is not supported now */
2572 rss_conf->rss_hf = 0;
2577 ice_promisc_enable(struct rte_eth_dev *dev)
2579 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2580 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581 struct ice_vsi *vsi = pf->main_vsi;
2585 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2586 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2588 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2589 if (status != ICE_SUCCESS)
2590 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
2594 ice_promisc_disable(struct rte_eth_dev *dev)
2596 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2597 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2598 struct ice_vsi *vsi = pf->main_vsi;
2602 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2603 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2605 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2606 if (status != ICE_SUCCESS)
2607 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
2611 ice_allmulti_enable(struct rte_eth_dev *dev)
2613 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2614 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615 struct ice_vsi *vsi = pf->main_vsi;
2619 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2621 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2622 if (status != ICE_SUCCESS)
2623 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
2627 ice_allmulti_disable(struct rte_eth_dev *dev)
2629 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2630 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2631 struct ice_vsi *vsi = pf->main_vsi;
2635 if (dev->data->promiscuous == 1)
2636 return; /* must remain in all_multicast mode */
2638 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2640 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2641 if (status != ICE_SUCCESS)
2642 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
2645 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
2648 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2649 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2650 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2654 msix_intr = intr_handle->intr_vec[queue_id];
2656 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
2657 GLINT_DYN_CTL_ITR_INDX_M;
2658 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
2660 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
2661 rte_intr_enable(&pci_dev->intr_handle);
2666 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
2669 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2670 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2671 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2674 msix_intr = intr_handle->intr_vec[queue_id];
2676 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
2682 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2684 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2690 full_ver = hw->nvm.oem_ver;
2691 ver = (u8)(full_ver >> 24);
2692 build = (u16)((full_ver >> 8) & 0xffff);
2693 patch = (u8)(full_ver & 0xff);
2695 ret = snprintf(fw_version, fw_size,
2696 "%d.%d%d 0x%08x %d.%d.%d",
2697 ((hw->nvm.ver >> 12) & 0xf),
2698 ((hw->nvm.ver >> 4) & 0xff),
2699 (hw->nvm.ver & 0xf), hw->nvm.eetrack,
2702 /* add the size of '\0' */
2704 if (fw_size < (u32)ret)
2711 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
2714 struct ice_vsi_ctx ctxt;
2715 uint8_t vlan_flags = 0;
2718 if (!vsi || !info) {
2719 PMD_DRV_LOG(ERR, "invalid parameters");
2724 vsi->info.pvid = info->config.pvid;
2726 * If insert pvid is enabled, only tagged pkts are
2727 * allowed to be sent out.
2729 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
2730 ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
2733 if (info->config.reject.tagged == 0)
2734 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
2736 if (info->config.reject.untagged == 0)
2737 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
2739 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
2740 ICE_AQ_VSI_VLAN_MODE_M);
2741 vsi->info.vlan_flags |= vlan_flags;
2742 memset(&ctxt, 0, sizeof(ctxt));
2743 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2744 ctxt.info.valid_sections =
2745 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2746 ctxt.vsi_num = vsi->vsi_id;
2748 hw = ICE_VSI_TO_HW(vsi);
2749 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2750 if (ret != ICE_SUCCESS) {
2752 "update VSI for VLAN insert failed, err %d",
2757 vsi->info.valid_sections |=
2758 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2764 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2766 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2767 struct ice_vsi *vsi = pf->main_vsi;
2768 struct rte_eth_dev_data *data = pf->dev_data;
2769 struct ice_vsi_vlan_pvid_info info;
2772 memset(&info, 0, sizeof(info));
2775 info.config.pvid = pvid;
2777 info.config.reject.tagged =
2778 data->dev_conf.txmode.hw_vlan_reject_tagged;
2779 info.config.reject.untagged =
2780 data->dev_conf.txmode.hw_vlan_reject_untagged;
2783 ret = ice_vsi_vlan_pvid_set(vsi, &info);
2785 PMD_DRV_LOG(ERR, "Failed to set pvid.");
2793 ice_get_eeprom_length(struct rte_eth_dev *dev)
2795 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2797 /* Convert word count to byte count */
2798 return hw->nvm.sr_words << 1;
2802 ice_get_eeprom(struct rte_eth_dev *dev,
2803 struct rte_dev_eeprom_info *eeprom)
2805 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2806 uint16_t *data = eeprom->data;
2807 uint16_t offset, length, i;
2808 enum ice_status ret_code = ICE_SUCCESS;
2810 offset = eeprom->offset >> 1;
2811 length = eeprom->length >> 1;
2813 if (offset > hw->nvm.sr_words ||
2814 offset + length > hw->nvm.sr_words) {
2815 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
2819 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
2821 for (i = 0; i < length; i++) {
2822 ret_code = ice_read_sr_word(hw, offset + i, &data[i]);
2823 if (ret_code != ICE_SUCCESS) {
2824 PMD_DRV_LOG(ERR, "EEPROM read failed.");
2833 ice_stat_update_32(struct ice_hw *hw,
2841 new_data = (uint64_t)ICE_READ_REG(hw, reg);
2845 if (new_data >= *offset)
2846 *stat = (uint64_t)(new_data - *offset);
2848 *stat = (uint64_t)((new_data +
2849 ((uint64_t)1 << ICE_32_BIT_WIDTH))
2854 ice_stat_update_40(struct ice_hw *hw,
2863 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
2864 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
2870 if (new_data >= *offset)
2871 *stat = new_data - *offset;
2873 *stat = (uint64_t)((new_data +
2874 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
2877 *stat &= ICE_40_BIT_MASK;
2880 /* Get all the statistics of a VSI */
2882 ice_update_vsi_stats(struct ice_vsi *vsi)
2884 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
2885 struct ice_eth_stats *nes = &vsi->eth_stats;
2886 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2887 int idx = rte_le_to_cpu_16(vsi->vsi_id);
2889 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
2890 vsi->offset_loaded, &oes->rx_bytes,
2892 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
2893 vsi->offset_loaded, &oes->rx_unicast,
2895 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
2896 vsi->offset_loaded, &oes->rx_multicast,
2897 &nes->rx_multicast);
2898 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
2899 vsi->offset_loaded, &oes->rx_broadcast,
2900 &nes->rx_broadcast);
2901 /* exclude CRC bytes */
2902 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2903 nes->rx_broadcast) * ETHER_CRC_LEN;
2905 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
2906 &oes->rx_discards, &nes->rx_discards);
2907 /* GLV_REPC not supported */
2908 /* GLV_RMPC not supported */
2909 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
2910 &oes->rx_unknown_protocol,
2911 &nes->rx_unknown_protocol);
2912 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
2913 vsi->offset_loaded, &oes->tx_bytes,
2915 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
2916 vsi->offset_loaded, &oes->tx_unicast,
2918 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
2919 vsi->offset_loaded, &oes->tx_multicast,
2920 &nes->tx_multicast);
2921 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
2922 vsi->offset_loaded, &oes->tx_broadcast,
2923 &nes->tx_broadcast);
2924 /* GLV_TDPC not supported */
2925 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
2926 &oes->tx_errors, &nes->tx_errors);
2927 vsi->offset_loaded = true;
2929 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
2931 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2932 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2933 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2934 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2935 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2936 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2937 nes->rx_unknown_protocol);
2938 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2939 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2940 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2941 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2942 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2943 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2944 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
2949 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
2951 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
2952 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
2954 /* Get statistics of struct ice_eth_stats */
2955 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
2956 GLPRT_GORCL(hw->port_info->lport),
2957 pf->offset_loaded, &os->eth.rx_bytes,
2959 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
2960 GLPRT_UPRCL(hw->port_info->lport),
2961 pf->offset_loaded, &os->eth.rx_unicast,
2962 &ns->eth.rx_unicast);
2963 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
2964 GLPRT_MPRCL(hw->port_info->lport),
2965 pf->offset_loaded, &os->eth.rx_multicast,
2966 &ns->eth.rx_multicast);
2967 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
2968 GLPRT_BPRCL(hw->port_info->lport),
2969 pf->offset_loaded, &os->eth.rx_broadcast,
2970 &ns->eth.rx_broadcast);
2971 ice_stat_update_32(hw, PRTRPB_RDPC,
2972 pf->offset_loaded, &os->eth.rx_discards,
2973 &ns->eth.rx_discards);
2975 /* Workaround: CRC size should not be included in byte statistics,
2976 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2978 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2979 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2981 /* GLPRT_REPC not supported */
2982 /* GLPRT_RMPC not supported */
2983 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
2985 &os->eth.rx_unknown_protocol,
2986 &ns->eth.rx_unknown_protocol);
2987 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
2988 GLPRT_GOTCL(hw->port_info->lport),
2989 pf->offset_loaded, &os->eth.tx_bytes,
2991 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
2992 GLPRT_UPTCL(hw->port_info->lport),
2993 pf->offset_loaded, &os->eth.tx_unicast,
2994 &ns->eth.tx_unicast);
2995 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
2996 GLPRT_MPTCL(hw->port_info->lport),
2997 pf->offset_loaded, &os->eth.tx_multicast,
2998 &ns->eth.tx_multicast);
2999 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3000 GLPRT_BPTCL(hw->port_info->lport),
3001 pf->offset_loaded, &os->eth.tx_broadcast,
3002 &ns->eth.tx_broadcast);
3003 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3004 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
3006 /* GLPRT_TEPC not supported */
3008 /* additional port specific stats */
3009 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3010 pf->offset_loaded, &os->tx_dropped_link_down,
3011 &ns->tx_dropped_link_down);
3012 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3013 pf->offset_loaded, &os->crc_errors,
3015 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3016 pf->offset_loaded, &os->illegal_bytes,
3017 &ns->illegal_bytes);
3018 /* GLPRT_ERRBC not supported */
3019 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3020 pf->offset_loaded, &os->mac_local_faults,
3021 &ns->mac_local_faults);
3022 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3023 pf->offset_loaded, &os->mac_remote_faults,
3024 &ns->mac_remote_faults);
3026 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3027 pf->offset_loaded, &os->rx_len_errors,
3028 &ns->rx_len_errors);
3030 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3031 pf->offset_loaded, &os->link_xon_rx,
3033 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3034 pf->offset_loaded, &os->link_xoff_rx,
3036 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3037 pf->offset_loaded, &os->link_xon_tx,
3039 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3040 pf->offset_loaded, &os->link_xoff_tx,
3042 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3043 GLPRT_PRC64L(hw->port_info->lport),
3044 pf->offset_loaded, &os->rx_size_64,
3046 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3047 GLPRT_PRC127L(hw->port_info->lport),
3048 pf->offset_loaded, &os->rx_size_127,
3050 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3051 GLPRT_PRC255L(hw->port_info->lport),
3052 pf->offset_loaded, &os->rx_size_255,
3054 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3055 GLPRT_PRC511L(hw->port_info->lport),
3056 pf->offset_loaded, &os->rx_size_511,
3058 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3059 GLPRT_PRC1023L(hw->port_info->lport),
3060 pf->offset_loaded, &os->rx_size_1023,
3062 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3063 GLPRT_PRC1522L(hw->port_info->lport),
3064 pf->offset_loaded, &os->rx_size_1522,
3066 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3067 GLPRT_PRC9522L(hw->port_info->lport),
3068 pf->offset_loaded, &os->rx_size_big,
3070 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3071 pf->offset_loaded, &os->rx_undersize,
3073 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3074 pf->offset_loaded, &os->rx_fragments,
3076 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3077 pf->offset_loaded, &os->rx_oversize,
3079 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3080 pf->offset_loaded, &os->rx_jabber,
3082 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3083 GLPRT_PTC64L(hw->port_info->lport),
3084 pf->offset_loaded, &os->tx_size_64,
3086 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3087 GLPRT_PTC127L(hw->port_info->lport),
3088 pf->offset_loaded, &os->tx_size_127,
3090 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3091 GLPRT_PTC255L(hw->port_info->lport),
3092 pf->offset_loaded, &os->tx_size_255,
3094 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3095 GLPRT_PTC511L(hw->port_info->lport),
3096 pf->offset_loaded, &os->tx_size_511,
3098 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3099 GLPRT_PTC1023L(hw->port_info->lport),
3100 pf->offset_loaded, &os->tx_size_1023,
3102 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3103 GLPRT_PTC1522L(hw->port_info->lport),
3104 pf->offset_loaded, &os->tx_size_1522,
3106 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3107 GLPRT_PTC9522L(hw->port_info->lport),
3108 pf->offset_loaded, &os->tx_size_big,
3111 /* GLPRT_MSPDC not supported */
3112 /* GLPRT_XEC not supported */
3114 pf->offset_loaded = true;
3117 ice_update_vsi_stats(pf->main_vsi);
3120 /* Get all statistics of a port */
3122 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3124 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3125 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3126 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3128 /* call read registers - updates values, now write them to struct */
3129 ice_read_stats_registers(pf, hw);
3131 stats->ipackets = ns->eth.rx_unicast +
3132 ns->eth.rx_multicast +
3133 ns->eth.rx_broadcast -
3134 ns->eth.rx_discards -
3135 pf->main_vsi->eth_stats.rx_discards;
3136 stats->opackets = ns->eth.tx_unicast +
3137 ns->eth.tx_multicast +
3138 ns->eth.tx_broadcast;
3139 stats->ibytes = ns->eth.rx_bytes;
3140 stats->obytes = ns->eth.tx_bytes;
3141 stats->oerrors = ns->eth.tx_errors +
3142 pf->main_vsi->eth_stats.tx_errors;
3145 stats->imissed = ns->eth.rx_discards +
3146 pf->main_vsi->eth_stats.rx_discards;
3147 stats->ierrors = ns->crc_errors +
3149 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3151 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
3152 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3153 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3154 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
3155 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
3156 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
3157 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
3158 pf->main_vsi->eth_stats.rx_discards);
3159 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3160 ns->eth.rx_unknown_protocol);
3161 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3162 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3163 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
3164 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
3165 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
3166 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
3167 pf->main_vsi->eth_stats.tx_discards);
3168 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3170 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3171 ns->tx_dropped_link_down);
3172 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3173 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3175 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3176 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3177 ns->mac_local_faults);
3178 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3179 ns->mac_remote_faults);
3180 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3181 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3182 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3183 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3184 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3185 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3186 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3187 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3188 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3189 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3190 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3191 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3192 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3193 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3194 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3195 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3196 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3197 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3198 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3199 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3200 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3201 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3202 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
3203 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
3207 /* Reset the statistics */
3209 ice_stats_reset(struct rte_eth_dev *dev)
3211 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3212 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3214 /* Mark PF and VSI stats to update the offset, aka "reset" */
3215 pf->offset_loaded = false;
3217 pf->main_vsi->offset_loaded = false;
3219 /* read the stats, reading current register values into offset */
3220 ice_read_stats_registers(pf, hw);
3224 ice_xstats_calc_num(void)
3228 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
3234 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3237 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3238 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3241 struct ice_hw_port_stats *hw_stats = &pf->stats;
3243 count = ice_xstats_calc_num();
3247 ice_read_stats_registers(pf, hw);
3254 /* Get stats from ice_eth_stats struct */
3255 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3256 xstats[count].value =
3257 *(uint64_t *)((char *)&hw_stats->eth +
3258 ice_stats_strings[i].offset);
3259 xstats[count].id = count;
3263 /* Get individiual stats from ice_hw_port struct */
3264 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3265 xstats[count].value =
3266 *(uint64_t *)((char *)hw_stats +
3267 ice_hw_port_strings[i].offset);
3268 xstats[count].id = count;
3275 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3276 struct rte_eth_xstat_name *xstats_names,
3277 __rte_unused unsigned int limit)
3279 unsigned int count = 0;
3283 return ice_xstats_calc_num();
3285 /* Note: limit checked in rte_eth_xstats_names() */
3287 /* Get stats from ice_eth_stats struct */
3288 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3289 snprintf(xstats_names[count].name,
3290 sizeof(xstats_names[count].name),
3291 "%s", ice_stats_strings[i].name);
3295 /* Get individiual stats from ice_hw_port struct */
3296 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3297 snprintf(xstats_names[count].name,
3298 sizeof(xstats_names[count].name),
3299 "%s", ice_hw_port_strings[i].name);
3307 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3308 struct rte_pci_device *pci_dev)
3310 return rte_eth_dev_pci_generic_probe(pci_dev,
3311 sizeof(struct ice_adapter),
3316 ice_pci_remove(struct rte_pci_device *pci_dev)
3318 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
3321 static struct rte_pci_driver rte_ice_pmd = {
3322 .id_table = pci_id_ice_map,
3323 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3324 RTE_PCI_DRV_IOVA_AS_VA,
3325 .probe = ice_pci_probe,
3326 .remove = ice_pci_remove,
3330 * Driver initialization routine.
3331 * Invoked once at EAL init time.
3332 * Register itself as the [Poll Mode] Driver of PCI devices.
3334 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
3335 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
3336 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
3337 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
3338 ICE_MAX_QP_NUM "=<int>");
3340 RTE_INIT(ice_init_log)
3342 ice_logtype_init = rte_log_register("pmd.net.ice.init");
3343 if (ice_logtype_init >= 0)
3344 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
3345 ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
3346 if (ice_logtype_driver >= 0)
3347 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);