1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <rte_ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "base/ice_common.h"
18 #include "rte_pmd_ice.h"
19 #include "ice_ethdev.h"
21 #include "ice_generic_flow.h"
24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
25 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
26 #define ICE_FLOW_MARK_SUPPORT_ARG "flow-mark-support"
27 #define ICE_PROTO_XTR_ARG "proto_xtr"
29 static const char * const ice_valid_args[] = {
30 ICE_SAFE_MODE_SUPPORT_ARG,
31 ICE_PIPELINE_MODE_SUPPORT_ARG,
32 ICE_FLOW_MARK_SUPPORT_ARG,
37 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
38 .name = "ice_dynfield_proto_xtr_metadata",
39 .size = sizeof(uint32_t),
40 .align = __alignof__(uint32_t),
44 struct proto_xtr_ol_flag {
45 const struct rte_mbuf_dynflag param;
50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
52 .param = { .name = "ice_dynflag_proto_xtr_vlan" },
53 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
55 .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
56 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
58 .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
59 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
60 [PROTO_XTR_IPV6_FLOW] = {
61 .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
62 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
64 .param = { .name = "ice_dynflag_proto_xtr_tcp" },
65 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
68 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
70 /* DDP package search path */
71 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
72 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
73 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
74 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
76 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
77 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
78 #define ICE_MAX_PKG_FILENAME_SIZE 256
79 #define ICE_MAX_RES_DESC_NUM 1024
82 int ice_logtype_driver;
83 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
86 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
89 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
90 int ice_logtype_tx_free;
93 static int ice_dev_configure(struct rte_eth_dev *dev);
94 static int ice_dev_start(struct rte_eth_dev *dev);
95 static void ice_dev_stop(struct rte_eth_dev *dev);
96 static void ice_dev_close(struct rte_eth_dev *dev);
97 static int ice_dev_reset(struct rte_eth_dev *dev);
98 static int ice_dev_info_get(struct rte_eth_dev *dev,
99 struct rte_eth_dev_info *dev_info);
100 static int ice_link_update(struct rte_eth_dev *dev,
101 int wait_to_complete);
102 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
103 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
105 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
106 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
107 static int ice_rss_reta_update(struct rte_eth_dev *dev,
108 struct rte_eth_rss_reta_entry64 *reta_conf,
110 static int ice_rss_reta_query(struct rte_eth_dev *dev,
111 struct rte_eth_rss_reta_entry64 *reta_conf,
113 static int ice_rss_hash_update(struct rte_eth_dev *dev,
114 struct rte_eth_rss_conf *rss_conf);
115 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
116 struct rte_eth_rss_conf *rss_conf);
117 static int ice_promisc_enable(struct rte_eth_dev *dev);
118 static int ice_promisc_disable(struct rte_eth_dev *dev);
119 static int ice_allmulti_enable(struct rte_eth_dev *dev);
120 static int ice_allmulti_disable(struct rte_eth_dev *dev);
121 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
124 static int ice_macaddr_set(struct rte_eth_dev *dev,
125 struct rte_ether_addr *mac_addr);
126 static int ice_macaddr_add(struct rte_eth_dev *dev,
127 struct rte_ether_addr *mac_addr,
128 __rte_unused uint32_t index,
130 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
131 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
133 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
135 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
137 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
138 uint16_t pvid, int on);
139 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
140 static int ice_get_eeprom(struct rte_eth_dev *dev,
141 struct rte_dev_eeprom_info *eeprom);
142 static int ice_stats_get(struct rte_eth_dev *dev,
143 struct rte_eth_stats *stats);
144 static int ice_stats_reset(struct rte_eth_dev *dev);
145 static int ice_xstats_get(struct rte_eth_dev *dev,
146 struct rte_eth_xstat *xstats, unsigned int n);
147 static int ice_xstats_get_names(struct rte_eth_dev *dev,
148 struct rte_eth_xstat_name *xstats_names,
150 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
151 enum rte_filter_type filter_type,
152 enum rte_filter_op filter_op,
154 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
155 struct rte_eth_udp_tunnel *udp_tunnel);
156 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
157 struct rte_eth_udp_tunnel *udp_tunnel);
159 static const struct rte_pci_id pci_id_ice_map[] = {
160 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
161 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
162 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
163 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
164 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
165 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
166 { .vendor_id = 0, /* sentinel */ },
169 static const struct eth_dev_ops ice_eth_dev_ops = {
170 .dev_configure = ice_dev_configure,
171 .dev_start = ice_dev_start,
172 .dev_stop = ice_dev_stop,
173 .dev_close = ice_dev_close,
174 .dev_reset = ice_dev_reset,
175 .dev_set_link_up = ice_dev_set_link_up,
176 .dev_set_link_down = ice_dev_set_link_down,
177 .rx_queue_start = ice_rx_queue_start,
178 .rx_queue_stop = ice_rx_queue_stop,
179 .tx_queue_start = ice_tx_queue_start,
180 .tx_queue_stop = ice_tx_queue_stop,
181 .rx_queue_setup = ice_rx_queue_setup,
182 .rx_queue_release = ice_rx_queue_release,
183 .tx_queue_setup = ice_tx_queue_setup,
184 .tx_queue_release = ice_tx_queue_release,
185 .dev_infos_get = ice_dev_info_get,
186 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
187 .link_update = ice_link_update,
188 .mtu_set = ice_mtu_set,
189 .mac_addr_set = ice_macaddr_set,
190 .mac_addr_add = ice_macaddr_add,
191 .mac_addr_remove = ice_macaddr_remove,
192 .vlan_filter_set = ice_vlan_filter_set,
193 .vlan_offload_set = ice_vlan_offload_set,
194 .reta_update = ice_rss_reta_update,
195 .reta_query = ice_rss_reta_query,
196 .rss_hash_update = ice_rss_hash_update,
197 .rss_hash_conf_get = ice_rss_hash_conf_get,
198 .promiscuous_enable = ice_promisc_enable,
199 .promiscuous_disable = ice_promisc_disable,
200 .allmulticast_enable = ice_allmulti_enable,
201 .allmulticast_disable = ice_allmulti_disable,
202 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
203 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
204 .fw_version_get = ice_fw_version_get,
205 .vlan_pvid_set = ice_vlan_pvid_set,
206 .rxq_info_get = ice_rxq_info_get,
207 .txq_info_get = ice_txq_info_get,
208 .rx_burst_mode_get = ice_rx_burst_mode_get,
209 .tx_burst_mode_get = ice_tx_burst_mode_get,
210 .get_eeprom_length = ice_get_eeprom_length,
211 .get_eeprom = ice_get_eeprom,
212 .rx_queue_count = ice_rx_queue_count,
213 .rx_descriptor_status = ice_rx_descriptor_status,
214 .tx_descriptor_status = ice_tx_descriptor_status,
215 .stats_get = ice_stats_get,
216 .stats_reset = ice_stats_reset,
217 .xstats_get = ice_xstats_get,
218 .xstats_get_names = ice_xstats_get_names,
219 .xstats_reset = ice_stats_reset,
220 .filter_ctrl = ice_dev_filter_ctrl,
221 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
222 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
225 /* store statistics names and its offset in stats structure */
226 struct ice_xstats_name_off {
227 char name[RTE_ETH_XSTATS_NAME_SIZE];
231 static const struct ice_xstats_name_off ice_stats_strings[] = {
232 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
233 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
234 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
235 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
236 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
237 rx_unknown_protocol)},
238 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
239 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
240 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
241 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
244 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
245 sizeof(ice_stats_strings[0]))
247 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
248 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
249 tx_dropped_link_down)},
250 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
251 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
253 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
254 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
256 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
258 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
260 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
261 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
262 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
263 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
264 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
265 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
267 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
269 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
271 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
273 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
275 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
277 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
279 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
281 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
282 mac_short_pkt_dropped)},
283 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
285 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
286 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
287 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
289 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
291 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
293 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
295 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
297 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
301 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
302 sizeof(ice_hw_port_strings[0]))
305 ice_init_controlq_parameter(struct ice_hw *hw)
307 /* fields for adminq */
308 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
309 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
310 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
311 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
313 /* fields for mailboxq, DPDK used as PF host */
314 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
315 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
316 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
317 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
321 lookup_proto_xtr_type(const char *xtr_name)
325 enum proto_xtr_type type;
327 { "vlan", PROTO_XTR_VLAN },
328 { "ipv4", PROTO_XTR_IPV4 },
329 { "ipv6", PROTO_XTR_IPV6 },
330 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
331 { "tcp", PROTO_XTR_TCP },
335 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
336 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
337 return xtr_type_map[i].type;
344 * Parse elem, the elem could be single number/range or '(' ')' group
345 * 1) A single number elem, it's just a simple digit. e.g. 9
346 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
347 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
348 * Within group elem, '-' used for a range separator;
349 * ',' used for a single number.
352 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
354 const char *str = input;
359 while (isblank(*str))
362 if (!isdigit(*str) && *str != '(')
365 /* process single number or single range of number */
368 idx = strtoul(str, &end, 10);
369 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
372 while (isblank(*end))
378 /* process single <number>-<number> */
381 while (isblank(*end))
387 idx = strtoul(end, &end, 10);
388 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
392 while (isblank(*end))
399 for (idx = RTE_MIN(min, max);
400 idx <= RTE_MAX(min, max); idx++)
401 devargs->proto_xtr[idx] = xtr_type;
406 /* process set within bracket */
408 while (isblank(*str))
413 min = ICE_MAX_QUEUE_NUM;
415 /* go ahead to the first digit */
416 while (isblank(*str))
421 /* get the digit value */
423 idx = strtoul(str, &end, 10);
424 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
427 /* go ahead to separator '-',',' and ')' */
428 while (isblank(*end))
431 if (min == ICE_MAX_QUEUE_NUM)
433 else /* avoid continuous '-' */
435 } else if (*end == ',' || *end == ')') {
437 if (min == ICE_MAX_QUEUE_NUM)
440 for (idx = RTE_MIN(min, max);
441 idx <= RTE_MAX(min, max); idx++)
442 devargs->proto_xtr[idx] = xtr_type;
444 min = ICE_MAX_QUEUE_NUM;
450 } while (*end != ')' && *end != '\0');
456 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
458 const char *queue_start;
463 while (isblank(*queues))
466 if (*queues != '[') {
467 xtr_type = lookup_proto_xtr_type(queues);
471 devargs->proto_xtr_dflt = xtr_type;
478 while (isblank(*queues))
483 queue_start = queues;
485 /* go across a complete bracket */
486 if (*queue_start == '(') {
487 queues += strcspn(queues, ")");
492 /* scan the separator ':' */
493 queues += strcspn(queues, ":");
494 if (*queues++ != ':')
496 while (isblank(*queues))
499 for (idx = 0; ; idx++) {
500 if (isblank(queues[idx]) ||
501 queues[idx] == ',' ||
502 queues[idx] == ']' ||
506 if (idx > sizeof(xtr_name) - 2)
509 xtr_name[idx] = queues[idx];
511 xtr_name[idx] = '\0';
512 xtr_type = lookup_proto_xtr_type(xtr_name);
518 while (isblank(*queues) || *queues == ',' || *queues == ']')
521 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
523 } while (*queues != '\0');
529 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
532 struct ice_devargs *devargs = extra_args;
534 if (value == NULL || extra_args == NULL)
537 if (parse_queue_proto_xtr(value, devargs) < 0) {
539 "The protocol extraction parameter is wrong : '%s'",
548 ice_proto_xtr_support(struct ice_hw *hw)
550 #define FLX_REG(val, fld, idx) \
551 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
552 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
558 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
559 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
560 ICE_PROT_IPV4_OF_OR_S },
561 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
562 ICE_PROT_IPV6_OF_OR_S },
563 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
564 ICE_PROT_IPV6_OF_OR_S },
565 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
569 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
570 uint32_t rxdid = xtr_sets[i].rxdid;
573 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
574 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
576 if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
577 FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
581 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
582 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
584 if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
585 FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
594 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
597 struct pool_entry *entry;
602 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
605 "Failed to allocate memory for resource pool");
609 /* queue heap initialize */
610 pool->num_free = num;
613 LIST_INIT(&pool->alloc_list);
614 LIST_INIT(&pool->free_list);
616 /* Initialize element */
620 LIST_INSERT_HEAD(&pool->free_list, entry, next);
625 ice_res_pool_alloc(struct ice_res_pool_info *pool,
628 struct pool_entry *entry, *valid_entry;
631 PMD_INIT_LOG(ERR, "Invalid parameter");
635 if (pool->num_free < num) {
636 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
637 num, pool->num_free);
642 /* Lookup in free list and find most fit one */
643 LIST_FOREACH(entry, &pool->free_list, next) {
644 if (entry->len >= num) {
646 if (entry->len == num) {
651 valid_entry->len > entry->len)
656 /* Not find one to satisfy the request, return */
658 PMD_INIT_LOG(ERR, "No valid entry found");
662 * The entry have equal queue number as requested,
663 * remove it from alloc_list.
665 if (valid_entry->len == num) {
666 LIST_REMOVE(valid_entry, next);
669 * The entry have more numbers than requested,
670 * create a new entry for alloc_list and minus its
671 * queue base and number in free_list.
673 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
676 "Failed to allocate memory for "
680 entry->base = valid_entry->base;
682 valid_entry->base += num;
683 valid_entry->len -= num;
687 /* Insert it into alloc list, not sorted */
688 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
690 pool->num_free -= valid_entry->len;
691 pool->num_alloc += valid_entry->len;
693 return valid_entry->base + pool->base;
697 ice_res_pool_destroy(struct ice_res_pool_info *pool)
699 struct pool_entry *entry, *next_entry;
704 for (entry = LIST_FIRST(&pool->alloc_list);
705 entry && (next_entry = LIST_NEXT(entry, next), 1);
706 entry = next_entry) {
707 LIST_REMOVE(entry, next);
711 for (entry = LIST_FIRST(&pool->free_list);
712 entry && (next_entry = LIST_NEXT(entry, next), 1);
713 entry = next_entry) {
714 LIST_REMOVE(entry, next);
721 LIST_INIT(&pool->alloc_list);
722 LIST_INIT(&pool->free_list);
726 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
728 /* Set VSI LUT selection */
729 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
730 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
731 /* Set Hash scheme */
732 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
733 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
735 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
738 static enum ice_status
739 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
740 struct ice_aqc_vsi_props *info,
741 uint8_t enabled_tcmap)
743 uint16_t bsf, qp_idx;
745 /* default tc 0 now. Multi-TC supporting need to be done later.
746 * Configure TC and queue mapping parameters, for enabled TC,
747 * allocate qpnum_per_tc queues to this traffic.
749 if (enabled_tcmap != 0x01) {
750 PMD_INIT_LOG(ERR, "only TC0 is supported");
754 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
755 bsf = rte_bsf32(vsi->nb_qps);
756 /* Adjust the queue number to actual queues that can be applied */
757 vsi->nb_qps = 0x1 << bsf;
760 /* Set tc and queue mapping with VSI */
761 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
762 ICE_AQ_VSI_TC_Q_OFFSET_S) |
763 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
765 /* Associate queue number with VSI */
766 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
767 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
768 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
769 info->valid_sections |=
770 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
771 /* Set the info.ingress_table and info.egress_table
772 * for UP translate table. Now just set it to 1:1 map by default
773 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
775 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
776 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
777 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
778 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
783 ice_init_mac_address(struct rte_eth_dev *dev)
785 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
787 if (!rte_is_unicast_ether_addr
788 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
789 PMD_INIT_LOG(ERR, "Invalid MAC address");
794 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
795 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
797 dev->data->mac_addrs =
798 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
799 if (!dev->data->mac_addrs) {
801 "Failed to allocate memory to store mac address");
804 /* store it to dev data */
806 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
807 &dev->data->mac_addrs[0]);
811 /* Find out specific MAC filter */
812 static struct ice_mac_filter *
813 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
815 struct ice_mac_filter *f;
817 TAILQ_FOREACH(f, &vsi->mac_list, next) {
818 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
826 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
828 struct ice_fltr_list_entry *m_list_itr = NULL;
829 struct ice_mac_filter *f;
830 struct LIST_HEAD_TYPE list_head;
831 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
834 /* If it's added and configured, return */
835 f = ice_find_mac_filter(vsi, mac_addr);
837 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
841 INIT_LIST_HEAD(&list_head);
843 m_list_itr = (struct ice_fltr_list_entry *)
844 ice_malloc(hw, sizeof(*m_list_itr));
849 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
850 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
851 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
852 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
853 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
854 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
855 m_list_itr->fltr_info.vsi_handle = vsi->idx;
857 LIST_ADD(&m_list_itr->list_entry, &list_head);
860 ret = ice_add_mac(hw, &list_head);
861 if (ret != ICE_SUCCESS) {
862 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
866 /* Add the mac addr into mac list */
867 f = rte_zmalloc(NULL, sizeof(*f), 0);
869 PMD_DRV_LOG(ERR, "failed to allocate memory");
873 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
874 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
880 rte_free(m_list_itr);
885 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
887 struct ice_fltr_list_entry *m_list_itr = NULL;
888 struct ice_mac_filter *f;
889 struct LIST_HEAD_TYPE list_head;
890 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
893 /* Can't find it, return an error */
894 f = ice_find_mac_filter(vsi, mac_addr);
898 INIT_LIST_HEAD(&list_head);
900 m_list_itr = (struct ice_fltr_list_entry *)
901 ice_malloc(hw, sizeof(*m_list_itr));
906 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
907 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
908 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
909 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
910 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
911 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
912 m_list_itr->fltr_info.vsi_handle = vsi->idx;
914 LIST_ADD(&m_list_itr->list_entry, &list_head);
916 /* remove the mac filter */
917 ret = ice_remove_mac(hw, &list_head);
918 if (ret != ICE_SUCCESS) {
919 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
924 /* Remove the mac addr from mac list */
925 TAILQ_REMOVE(&vsi->mac_list, f, next);
931 rte_free(m_list_itr);
935 /* Find out specific VLAN filter */
936 static struct ice_vlan_filter *
937 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
939 struct ice_vlan_filter *f;
941 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
942 if (vlan_id == f->vlan_info.vlan_id)
950 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
952 struct ice_fltr_list_entry *v_list_itr = NULL;
953 struct ice_vlan_filter *f;
954 struct LIST_HEAD_TYPE list_head;
958 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
961 hw = ICE_VSI_TO_HW(vsi);
963 /* If it's added and configured, return. */
964 f = ice_find_vlan_filter(vsi, vlan_id);
966 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
970 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
973 INIT_LIST_HEAD(&list_head);
975 v_list_itr = (struct ice_fltr_list_entry *)
976 ice_malloc(hw, sizeof(*v_list_itr));
981 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
982 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
983 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
984 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
985 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
986 v_list_itr->fltr_info.vsi_handle = vsi->idx;
988 LIST_ADD(&v_list_itr->list_entry, &list_head);
991 ret = ice_add_vlan(hw, &list_head);
992 if (ret != ICE_SUCCESS) {
993 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
998 /* Add vlan into vlan list */
999 f = rte_zmalloc(NULL, sizeof(*f), 0);
1001 PMD_DRV_LOG(ERR, "failed to allocate memory");
1005 f->vlan_info.vlan_id = vlan_id;
1006 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1012 rte_free(v_list_itr);
1017 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1019 struct ice_fltr_list_entry *v_list_itr = NULL;
1020 struct ice_vlan_filter *f;
1021 struct LIST_HEAD_TYPE list_head;
1026 * Vlan 0 is the generic filter for untagged packets
1027 * and can't be removed.
1029 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1032 hw = ICE_VSI_TO_HW(vsi);
1034 /* Can't find it, return an error */
1035 f = ice_find_vlan_filter(vsi, vlan_id);
1039 INIT_LIST_HEAD(&list_head);
1041 v_list_itr = (struct ice_fltr_list_entry *)
1042 ice_malloc(hw, sizeof(*v_list_itr));
1048 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1049 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1050 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1051 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1052 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1053 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1055 LIST_ADD(&v_list_itr->list_entry, &list_head);
1057 /* remove the vlan filter */
1058 ret = ice_remove_vlan(hw, &list_head);
1059 if (ret != ICE_SUCCESS) {
1060 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1065 /* Remove the vlan id from vlan list */
1066 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1072 rte_free(v_list_itr);
1077 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1079 struct ice_mac_filter *m_f;
1080 struct ice_vlan_filter *v_f;
1083 if (!vsi || !vsi->mac_num)
1086 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1087 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1088 if (ret != ICE_SUCCESS) {
1094 if (vsi->vlan_num == 0)
1097 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1098 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1099 if (ret != ICE_SUCCESS) {
1110 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1112 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1113 struct ice_vsi_ctx ctxt;
1117 /* Check if it has been already on or off */
1118 if (vsi->info.valid_sections &
1119 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1121 if ((vsi->info.outer_tag_flags &
1122 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1123 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1124 return 0; /* already on */
1126 if (!(vsi->info.outer_tag_flags &
1127 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1128 return 0; /* already off */
1133 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1136 /* clear global insertion and use per packet insertion */
1137 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1138 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1139 vsi->info.outer_tag_flags |= qinq_flags;
1140 /* use default vlan type 0x8100 */
1141 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1142 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1143 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1144 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1145 ctxt.info.valid_sections =
1146 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1147 ctxt.vsi_num = vsi->vsi_id;
1148 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1151 "Update VSI failed to %s qinq stripping",
1152 on ? "enable" : "disable");
1156 vsi->info.valid_sections |=
1157 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1163 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1165 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1166 struct ice_vsi_ctx ctxt;
1170 /* Check if it has been already on or off */
1171 if (vsi->info.valid_sections &
1172 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1174 if ((vsi->info.outer_tag_flags &
1175 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1176 ICE_AQ_VSI_OUTER_TAG_COPY)
1177 return 0; /* already on */
1179 if ((vsi->info.outer_tag_flags &
1180 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1181 ICE_AQ_VSI_OUTER_TAG_NOTHING)
1182 return 0; /* already off */
1187 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1189 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1190 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1191 vsi->info.outer_tag_flags |= qinq_flags;
1192 /* use default vlan type 0x8100 */
1193 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1194 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1195 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1196 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1197 ctxt.info.valid_sections =
1198 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1199 ctxt.vsi_num = vsi->vsi_id;
1200 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1203 "Update VSI failed to %s qinq stripping",
1204 on ? "enable" : "disable");
1208 vsi->info.valid_sections |=
1209 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1215 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1219 ret = ice_vsi_config_qinq_stripping(vsi, on);
1221 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1223 ret = ice_vsi_config_qinq_insertion(vsi, on);
1225 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1232 ice_pf_enable_irq0(struct ice_hw *hw)
1234 /* reset the registers */
1235 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1236 ICE_READ_REG(hw, PFINT_OICR);
1239 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1240 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1241 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1243 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1244 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1245 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1246 PFINT_OICR_CTL_ITR_INDX_M) |
1247 PFINT_OICR_CTL_CAUSE_ENA_M);
1249 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1250 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1251 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1252 PFINT_FW_CTL_ITR_INDX_M) |
1253 PFINT_FW_CTL_CAUSE_ENA_M);
1255 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1258 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1259 GLINT_DYN_CTL_INTENA_M |
1260 GLINT_DYN_CTL_CLEARPBA_M |
1261 GLINT_DYN_CTL_ITR_INDX_M);
1268 ice_pf_disable_irq0(struct ice_hw *hw)
1270 /* Disable all interrupt types */
1271 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1277 ice_handle_aq_msg(struct rte_eth_dev *dev)
1279 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1280 struct ice_ctl_q_info *cq = &hw->adminq;
1281 struct ice_rq_event_info event;
1282 uint16_t pending, opcode;
1285 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1286 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1287 if (!event.msg_buf) {
1288 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1294 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1296 if (ret != ICE_SUCCESS) {
1298 "Failed to read msg from AdminQ, "
1300 hw->adminq.sq_last_status);
1303 opcode = rte_le_to_cpu_16(event.desc.opcode);
1306 case ice_aqc_opc_get_link_status:
1307 ret = ice_link_update(dev, 0);
1309 _rte_eth_dev_callback_process
1310 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1313 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1318 rte_free(event.msg_buf);
1323 * Interrupt handler triggered by NIC for handling
1324 * specific interrupt.
1327 * Pointer to interrupt handle.
1329 * The address of parameter (struct rte_eth_dev *) regsitered before.
1335 ice_interrupt_handler(void *param)
1337 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1338 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1346 uint32_t int_fw_ctl;
1349 /* Disable interrupt */
1350 ice_pf_disable_irq0(hw);
1352 /* read out interrupt causes */
1353 oicr = ICE_READ_REG(hw, PFINT_OICR);
1355 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1358 /* No interrupt event indicated */
1359 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1360 PMD_DRV_LOG(INFO, "No interrupt event");
1365 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1366 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1367 ice_handle_aq_msg(dev);
1370 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1371 PMD_DRV_LOG(INFO, "OICR: link state change event");
1372 ret = ice_link_update(dev, 0);
1374 _rte_eth_dev_callback_process
1375 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1379 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1380 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1381 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1382 if (reg & GL_MDET_TX_PQM_VALID_M) {
1383 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1384 GL_MDET_TX_PQM_PF_NUM_S;
1385 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1386 GL_MDET_TX_PQM_MAL_TYPE_S;
1387 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1388 GL_MDET_TX_PQM_QNUM_S;
1390 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1391 "%d by PQM on TX queue %d PF# %d",
1392 event, queue, pf_num);
1395 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1396 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1397 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1398 GL_MDET_TX_TCLAN_PF_NUM_S;
1399 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1400 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1401 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1402 GL_MDET_TX_TCLAN_QNUM_S;
1404 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1405 "%d by TCLAN on TX queue %d PF# %d",
1406 event, queue, pf_num);
1410 /* Enable interrupt */
1411 ice_pf_enable_irq0(hw);
1412 rte_intr_ack(dev->intr_handle);
1416 ice_init_proto_xtr(struct rte_eth_dev *dev)
1418 struct ice_adapter *ad =
1419 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1420 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1421 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1422 const struct proto_xtr_ol_flag *ol_flag;
1423 bool proto_xtr_enable = false;
1427 if (!ice_proto_xtr_support(hw)) {
1428 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1432 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1433 if (unlikely(pf->proto_xtr == NULL)) {
1434 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1438 for (i = 0; i < pf->lan_nb_qps; i++) {
1439 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1440 ad->devargs.proto_xtr[i] :
1441 ad->devargs.proto_xtr_dflt;
1443 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1444 uint8_t type = pf->proto_xtr[i];
1446 ice_proto_xtr_ol_flag_params[type].required = true;
1447 proto_xtr_enable = true;
1451 if (likely(!proto_xtr_enable))
1454 offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1455 if (unlikely(offset == -1)) {
1457 "Protocol extraction metadata is disabled in mbuf with error %d",
1463 "Protocol extraction metadata offset in mbuf is : %d",
1465 rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1467 for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1468 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1470 if (!ol_flag->required)
1473 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1474 if (unlikely(offset == -1)) {
1476 "Protocol extraction offload '%s' failed to register with error %d",
1477 ol_flag->param.name, -rte_errno);
1479 rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1484 "Protocol extraction offload '%s' offset in mbuf is : %d",
1485 ol_flag->param.name, offset);
1486 *ol_flag->ol_flag = 1ULL << offset;
1490 /* Initialize SW parameters of PF */
1492 ice_pf_sw_init(struct rte_eth_dev *dev)
1494 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1495 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1498 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1499 hw->func_caps.common_cap.num_rxq);
1501 pf->lan_nb_qps = pf->lan_nb_qp_max;
1503 ice_init_proto_xtr(dev);
1505 if (hw->func_caps.fd_fltr_guar > 0 ||
1506 hw->func_caps.fd_fltr_best_effort > 0) {
1507 pf->flags |= ICE_FLAG_FDIR;
1508 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1509 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1511 pf->fdir_nb_qps = 0;
1513 pf->fdir_qp_offset = 0;
1519 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1521 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1522 struct ice_vsi *vsi = NULL;
1523 struct ice_vsi_ctx vsi_ctx;
1525 struct rte_ether_addr broadcast = {
1526 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1527 struct rte_ether_addr mac_addr;
1528 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1529 uint8_t tc_bitmap = 0x1;
1532 /* hw->num_lports = 1 in NIC mode */
1533 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1537 vsi->idx = pf->next_vsi_idx;
1540 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1541 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1542 vsi->vlan_anti_spoof_on = 0;
1543 vsi->vlan_filter_on = 1;
1544 TAILQ_INIT(&vsi->mac_list);
1545 TAILQ_INIT(&vsi->vlan_list);
1547 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1548 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1549 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1550 hw->func_caps.common_cap.rss_table_size;
1551 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1553 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1556 vsi->nb_qps = pf->lan_nb_qps;
1557 vsi->base_queue = 1;
1558 ice_vsi_config_default_rss(&vsi_ctx.info);
1559 vsi_ctx.alloc_from_pool = true;
1560 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1561 /* switch_id is queried by get_switch_config aq, which is done
1564 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1565 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1566 /* Allow all untagged or tagged packets */
1567 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1568 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1569 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1570 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1573 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1574 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1575 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1576 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1577 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1578 vsi_ctx.info.max_fd_fltr_dedicated =
1579 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1580 vsi_ctx.info.max_fd_fltr_shared =
1581 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1583 /* Enable VLAN/UP trip */
1584 ret = ice_vsi_config_tc_queue_mapping(vsi,
1589 "tc queue mapping with vsi failed, "
1597 vsi->nb_qps = pf->fdir_nb_qps;
1598 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1599 vsi_ctx.alloc_from_pool = true;
1600 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1602 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1603 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1604 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1605 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1606 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1607 ret = ice_vsi_config_tc_queue_mapping(vsi,
1612 "tc queue mapping with vsi failed, "
1619 /* for other types of VSI */
1620 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1624 /* VF has MSIX interrupt in VF range, don't allocate here */
1625 if (type == ICE_VSI_PF) {
1626 ret = ice_res_pool_alloc(&pf->msix_pool,
1627 RTE_MIN(vsi->nb_qps,
1628 RTE_MAX_RXTX_INTR_VEC_ID));
1630 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1633 vsi->msix_intr = ret;
1634 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1635 } else if (type == ICE_VSI_CTRL) {
1636 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1638 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1641 vsi->msix_intr = ret;
1647 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1648 if (ret != ICE_SUCCESS) {
1649 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1652 /* store vsi information is SW structure */
1653 vsi->vsi_id = vsi_ctx.vsi_num;
1654 vsi->info = vsi_ctx.info;
1655 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1656 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1658 if (type == ICE_VSI_PF) {
1659 /* MAC configuration */
1660 rte_memcpy(pf->dev_addr.addr_bytes,
1661 hw->port_info->mac.perm_addr,
1664 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1665 ret = ice_add_mac_filter(vsi, &mac_addr);
1666 if (ret != ICE_SUCCESS)
1667 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1669 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1670 ret = ice_add_mac_filter(vsi, &mac_addr);
1671 if (ret != ICE_SUCCESS)
1672 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1675 /* At the beginning, only TC0. */
1676 /* What we need here is the maximam number of the TX queues.
1677 * Currently vsi->nb_qps means it.
1678 * Correct it if any change.
1680 max_txqs[0] = vsi->nb_qps;
1681 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1682 tc_bitmap, max_txqs);
1683 if (ret != ICE_SUCCESS)
1684 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1694 ice_send_driver_ver(struct ice_hw *hw)
1696 struct ice_driver_ver dv;
1698 /* we don't have driver version use 0 for dummy */
1702 dv.subbuild_ver = 0;
1703 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1705 return ice_aq_send_driver_ver(hw, &dv, NULL);
1709 ice_pf_setup(struct ice_pf *pf)
1711 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1712 struct ice_vsi *vsi;
1715 /* Clear all stats counters */
1716 pf->offset_loaded = FALSE;
1717 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1718 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1719 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1720 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1722 /* force guaranteed filter pool for PF */
1723 ice_alloc_fd_guar_item(hw, &unused,
1724 hw->func_caps.fd_fltr_guar);
1725 /* force shared filter pool for PF */
1726 ice_alloc_fd_shrd_item(hw, &unused,
1727 hw->func_caps.fd_fltr_best_effort);
1729 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1731 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1740 /* PCIe configuration space setting */
1741 #define PCI_CFG_SPACE_SIZE 256
1742 #define PCI_CFG_SPACE_EXP_SIZE 4096
1743 #define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)
1744 #define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)
1745 #define PCI_EXT_CAP_ID_DSN 0x03
1748 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1752 int pos = PCI_CFG_SPACE_SIZE;
1754 /* minimum 8 bytes per capability */
1755 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1757 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1758 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1763 * If we have no capabilities, this is indicated by cap ID,
1764 * cap version and next pointer all being 0.
1770 if (PCI_EXT_CAP_ID(header) == cap)
1773 pos = PCI_EXT_CAP_NEXT(header);
1775 if (pos < PCI_CFG_SPACE_SIZE)
1778 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1779 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1788 * Extract device serial number from PCIe Configuration Space and
1789 * determine the pkg file path according to the DSN.
1792 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1795 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1796 uint32_t dsn_low, dsn_high;
1797 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1799 pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1802 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1803 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1804 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1805 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1807 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1811 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1812 ICE_MAX_PKG_FILENAME_SIZE);
1813 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1816 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1817 ICE_MAX_PKG_FILENAME_SIZE);
1818 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1822 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1823 if (!access(pkg_file, 0))
1825 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1829 static enum ice_pkg_type
1830 ice_load_pkg_type(struct ice_hw *hw)
1832 enum ice_pkg_type package_type;
1834 /* store the activated package type (OS default or Comms) */
1835 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1837 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1838 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1840 package_type = ICE_PKG_TYPE_COMMS;
1842 package_type = ICE_PKG_TYPE_UNKNOWN;
1844 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1845 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1846 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1847 hw->active_pkg_name);
1849 return package_type;
1852 static int ice_load_pkg(struct rte_eth_dev *dev)
1854 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1861 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1862 struct ice_adapter *ad =
1863 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1865 ice_pkg_file_search_path(pci_dev, pkg_file);
1867 file = fopen(pkg_file, "rb");
1869 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1873 err = stat(pkg_file, &fstat);
1875 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1880 buf_len = fstat.st_size;
1881 buf = rte_malloc(NULL, buf_len, 0);
1884 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1890 err = fread(buf, buf_len, 1, file);
1892 PMD_INIT_LOG(ERR, "failed to read package data\n");
1900 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1902 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1906 /* store the loaded pkg type info */
1907 ad->active_pkg_type = ice_load_pkg_type(hw);
1909 err = ice_init_hw_tbls(hw);
1911 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1912 goto fail_init_tbls;
1918 rte_free(hw->pkg_copy);
1925 ice_base_queue_get(struct ice_pf *pf)
1928 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1930 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1931 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1932 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1934 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1940 parse_bool(const char *key, const char *value, void *args)
1942 int *i = (int *)args;
1946 num = strtoul(value, &end, 10);
1948 if (num != 0 && num != 1) {
1949 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1950 "value must be 0 or 1",
1959 static int ice_parse_devargs(struct rte_eth_dev *dev)
1961 struct ice_adapter *ad =
1962 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1963 struct rte_devargs *devargs = dev->device->devargs;
1964 struct rte_kvargs *kvlist;
1967 if (devargs == NULL)
1970 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1971 if (kvlist == NULL) {
1972 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1976 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1977 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1978 sizeof(ad->devargs.proto_xtr));
1980 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1981 &handle_proto_xtr_arg, &ad->devargs);
1985 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1986 &parse_bool, &ad->devargs.safe_mode_support);
1990 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1991 &parse_bool, &ad->devargs.pipe_mode_support);
1995 ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG,
1996 &parse_bool, &ad->devargs.flow_mark_support);
2001 rte_kvargs_free(kvlist);
2005 /* Forward LLDP packets to default VSI by set switch rules */
2007 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
2009 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2010 struct ice_fltr_list_entry *s_list_itr = NULL;
2011 struct LIST_HEAD_TYPE list_head;
2014 INIT_LIST_HEAD(&list_head);
2016 s_list_itr = (struct ice_fltr_list_entry *)
2017 ice_malloc(hw, sizeof(*s_list_itr));
2020 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
2021 s_list_itr->fltr_info.vsi_handle = vsi->idx;
2022 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
2023 RTE_ETHER_TYPE_LLDP;
2024 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
2025 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
2026 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
2027 LIST_ADD(&s_list_itr->list_entry, &list_head);
2029 ret = ice_add_eth_mac(hw, &list_head);
2031 ret = ice_remove_eth_mac(hw, &list_head);
2033 rte_free(s_list_itr);
2037 static enum ice_status
2038 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
2039 uint16_t num, uint16_t desc_id,
2040 uint16_t *prof_buf, uint16_t *num_prof)
2042 struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
2045 bool res_shared = 1;
2046 struct ice_aq_desc aq_desc;
2047 struct ice_sq_cd *cd = NULL;
2048 struct ice_aqc_get_allocd_res_desc *cmd =
2049 &aq_desc.params.get_res_desc;
2051 buf_len = sizeof(resp_buf->elem) * num;
2052 resp_buf = ice_malloc(hw, buf_len);
2056 ice_fill_dflt_direct_cmd_desc(&aq_desc,
2057 ice_aqc_opc_get_allocd_res_desc);
2059 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
2060 ICE_AQC_RES_TYPE_M) | (res_shared ?
2061 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
2062 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
2064 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
2066 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
2070 ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
2071 (*num_prof), ICE_NONDMA_TO_NONDMA);
2078 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
2082 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
2083 uint16_t first_desc = 1;
2084 uint16_t num_prof = 0;
2086 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
2087 first_desc, prof_buf, &num_prof);
2089 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2093 for (prof_id = 0; prof_id < num_prof; prof_id++) {
2094 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2096 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2104 ice_reset_fxp_resource(struct ice_hw *hw)
2108 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2110 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2114 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2116 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2124 ice_dev_init(struct rte_eth_dev *dev)
2126 struct rte_pci_device *pci_dev;
2127 struct rte_intr_handle *intr_handle;
2128 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2129 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2130 struct ice_adapter *ad =
2131 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2132 struct ice_vsi *vsi;
2135 dev->dev_ops = &ice_eth_dev_ops;
2136 dev->rx_pkt_burst = ice_recv_pkts;
2137 dev->tx_pkt_burst = ice_xmit_pkts;
2138 dev->tx_pkt_prepare = ice_prep_pkts;
2140 /* for secondary processes, we don't initialise any further as primary
2141 * has already done this work.
2143 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2144 ice_set_rx_function(dev);
2145 ice_set_tx_function(dev);
2149 ice_set_default_ptype_table(dev);
2150 pci_dev = RTE_DEV_TO_PCI(dev->device);
2151 intr_handle = &pci_dev->intr_handle;
2153 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2154 pf->adapter->eth_dev = dev;
2155 pf->dev_data = dev->data;
2156 hw->back = pf->adapter;
2157 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2158 hw->vendor_id = pci_dev->id.vendor_id;
2159 hw->device_id = pci_dev->id.device_id;
2160 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2161 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2162 hw->bus.device = pci_dev->addr.devid;
2163 hw->bus.func = pci_dev->addr.function;
2165 ret = ice_parse_devargs(dev);
2167 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2171 ice_init_controlq_parameter(hw);
2173 ret = ice_init_hw(hw);
2175 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2179 ret = ice_load_pkg(dev);
2181 if (ad->devargs.safe_mode_support == 0) {
2182 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2183 "Use safe-mode-support=1 to enter Safe Mode");
2187 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2188 "Entering Safe Mode");
2189 ad->is_safe_mode = 1;
2192 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2193 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2194 hw->api_maj_ver, hw->api_min_ver);
2196 ice_pf_sw_init(dev);
2197 ret = ice_init_mac_address(dev);
2199 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2203 /* Pass the information to the rte_eth_dev_close() that it should also
2204 * release the private port resources.
2206 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2208 ret = ice_res_pool_init(&pf->msix_pool, 1,
2209 hw->func_caps.common_cap.num_msix_vectors - 1);
2211 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2212 goto err_msix_pool_init;
2215 ret = ice_pf_setup(pf);
2217 PMD_INIT_LOG(ERR, "Failed to setup PF");
2221 ret = ice_send_driver_ver(hw);
2223 PMD_INIT_LOG(ERR, "Failed to send driver version");
2229 /* Disable double vlan by default */
2230 ice_vsi_config_double_vlan(vsi, FALSE);
2232 ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
2233 if (ret != ICE_SUCCESS)
2234 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2235 ret = ice_init_dcb(hw, TRUE);
2236 if (ret != ICE_SUCCESS)
2237 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2238 /* Forward LLDP packets to default VSI */
2239 ret = ice_vsi_config_sw_lldp(vsi, TRUE);
2240 if (ret != ICE_SUCCESS)
2241 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2242 /* register callback func to eal lib */
2243 rte_intr_callback_register(intr_handle,
2244 ice_interrupt_handler, dev);
2246 ice_pf_enable_irq0(hw);
2248 /* enable uio intr after callback register */
2249 rte_intr_enable(intr_handle);
2251 /* get base queue pairs index in the device */
2252 ice_base_queue_get(pf);
2254 if (!ad->is_safe_mode) {
2255 ret = ice_flow_init(ad);
2257 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2262 ret = ice_reset_fxp_resource(hw);
2264 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2271 ice_res_pool_destroy(&pf->msix_pool);
2273 rte_free(dev->data->mac_addrs);
2274 dev->data->mac_addrs = NULL;
2276 ice_sched_cleanup_all(hw);
2277 rte_free(hw->port_info);
2278 ice_shutdown_all_ctrlq(hw);
2279 rte_free(pf->proto_xtr);
2285 ice_release_vsi(struct ice_vsi *vsi)
2288 struct ice_vsi_ctx vsi_ctx;
2289 enum ice_status ret;
2294 hw = ICE_VSI_TO_HW(vsi);
2296 ice_remove_all_mac_vlan_filters(vsi);
2298 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2300 vsi_ctx.vsi_num = vsi->vsi_id;
2301 vsi_ctx.info = vsi->info;
2302 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2303 if (ret != ICE_SUCCESS) {
2304 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2314 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2316 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2317 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2318 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2319 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2320 uint16_t msix_intr, i;
2322 /* disable interrupt and also clear all the exist config */
2323 for (i = 0; i < vsi->nb_qps; i++) {
2324 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2325 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2329 if (rte_intr_allow_others(intr_handle))
2331 for (i = 0; i < vsi->nb_msix; i++) {
2332 msix_intr = vsi->msix_intr + i;
2333 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2334 GLINT_DYN_CTL_WB_ON_ITR_M);
2338 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2342 ice_dev_stop(struct rte_eth_dev *dev)
2344 struct rte_eth_dev_data *data = dev->data;
2345 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2346 struct ice_vsi *main_vsi = pf->main_vsi;
2347 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2348 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2351 /* avoid stopping again */
2352 if (pf->adapter_stopped)
2355 /* stop and clear all Rx queues */
2356 for (i = 0; i < data->nb_rx_queues; i++)
2357 ice_rx_queue_stop(dev, i);
2359 /* stop and clear all Tx queues */
2360 for (i = 0; i < data->nb_tx_queues; i++)
2361 ice_tx_queue_stop(dev, i);
2363 /* disable all queue interrupts */
2364 ice_vsi_disable_queues_intr(main_vsi);
2366 /* Clear all queues and release mbufs */
2367 ice_clear_queues(dev);
2369 if (pf->init_link_up)
2370 ice_dev_set_link_up(dev);
2372 ice_dev_set_link_down(dev);
2374 /* Clean datapath event and queue/vec mapping */
2375 rte_intr_efd_disable(intr_handle);
2376 if (intr_handle->intr_vec) {
2377 rte_free(intr_handle->intr_vec);
2378 intr_handle->intr_vec = NULL;
2381 pf->adapter_stopped = true;
2385 ice_dev_close(struct rte_eth_dev *dev)
2387 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2388 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2390 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2391 struct ice_adapter *ad =
2392 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2394 /* Since stop will make link down, then the link event will be
2395 * triggered, disable the irq firstly to avoid the port_infoe etc
2396 * resources deallocation causing the interrupt service thread
2399 ice_pf_disable_irq0(hw);
2403 if (!ad->is_safe_mode)
2404 ice_flow_uninit(ad);
2406 /* release all queue resource */
2407 ice_free_queues(dev);
2409 ice_res_pool_destroy(&pf->msix_pool);
2410 ice_release_vsi(pf->main_vsi);
2411 ice_sched_cleanup_all(hw);
2412 ice_free_hw_tbls(hw);
2413 rte_free(hw->port_info);
2414 hw->port_info = NULL;
2415 ice_shutdown_all_ctrlq(hw);
2416 rte_free(pf->proto_xtr);
2417 pf->proto_xtr = NULL;
2419 dev->dev_ops = NULL;
2420 dev->rx_pkt_burst = NULL;
2421 dev->tx_pkt_burst = NULL;
2423 rte_free(dev->data->mac_addrs);
2424 dev->data->mac_addrs = NULL;
2426 /* disable uio intr before callback unregister */
2427 rte_intr_disable(intr_handle);
2429 /* unregister callback func from eal lib */
2430 rte_intr_callback_unregister(intr_handle,
2431 ice_interrupt_handler, dev);
2435 ice_dev_uninit(struct rte_eth_dev *dev)
2443 ice_dev_configure(struct rte_eth_dev *dev)
2445 struct ice_adapter *ad =
2446 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2448 /* Initialize to TRUE. If any of Rx queues doesn't meet the
2449 * bulk allocation or vector Rx preconditions we will reset it.
2451 ad->rx_bulk_alloc_allowed = true;
2452 ad->tx_simple_allowed = true;
2454 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2455 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2460 static int ice_init_rss(struct ice_pf *pf)
2462 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2463 struct ice_vsi *vsi = pf->main_vsi;
2464 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2465 struct rte_eth_rss_conf *rss_conf;
2466 struct ice_aqc_get_set_rss_keys key;
2469 bool is_safe_mode = pf->adapter->is_safe_mode;
2472 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2473 nb_q = dev->data->nb_rx_queues;
2474 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2475 vsi->rss_lut_size = pf->hash_lut_size;
2478 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2483 vsi->rss_key = rte_zmalloc(NULL,
2484 vsi->rss_key_size, 0);
2486 vsi->rss_lut = rte_zmalloc(NULL,
2487 vsi->rss_lut_size, 0);
2489 /* configure RSS key */
2490 if (!rss_conf->rss_key) {
2491 /* Calculate the default hash key */
2492 for (i = 0; i <= vsi->rss_key_size; i++)
2493 vsi->rss_key[i] = (uint8_t)rte_rand();
2495 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2496 RTE_MIN(rss_conf->rss_key_len,
2497 vsi->rss_key_size));
2499 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2500 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2504 /* init RSS LUT table */
2505 for (i = 0; i < vsi->rss_lut_size; i++)
2506 vsi->rss_lut[i] = i % nb_q;
2508 ret = ice_aq_set_rss_lut(hw, vsi->idx,
2509 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2510 vsi->rss_lut, vsi->rss_lut_size);
2514 /* Enable registers for symmetric_toeplitz function. */
2515 reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
2516 reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
2517 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
2518 ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
2520 /* configure RSS for IPv4 with input set IPv4 src/dst */
2521 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2522 ICE_FLOW_SEG_HDR_IPV4, 0);
2524 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2526 /* configure RSS for IPv6 with input set IPv6 src/dst */
2527 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2528 ICE_FLOW_SEG_HDR_IPV6, 0);
2530 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2532 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2533 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2534 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2536 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2538 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2539 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2540 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2542 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2544 /* configure RSS for sctp6 with input set IPv6 src/dst */
2545 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2546 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2548 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2551 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2552 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2553 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2555 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2557 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2558 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2559 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2561 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2563 /* configure RSS for sctp4 with input set IP src/dst */
2564 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2565 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2567 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2570 /* configure RSS for gtpu with input set TEID */
2571 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
2572 ICE_FLOW_SEG_HDR_GTPU_IP, 0);
2574 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
2578 * configure RSS for pppoe/pppod with input set
2579 * Source MAC and Session ID
2581 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
2582 ICE_FLOW_SEG_HDR_PPPOE, 0);
2584 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
2591 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2592 int base_queue, int nb_queue)
2594 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2595 uint32_t val, val_tx;
2598 for (i = 0; i < nb_queue; i++) {
2600 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2601 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2602 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2603 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2605 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2606 base_queue + i, msix_vect);
2607 /* set ITR0 value */
2608 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2609 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2610 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2615 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2617 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2618 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2619 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2620 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2621 uint16_t msix_vect = vsi->msix_intr;
2622 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2623 uint16_t queue_idx = 0;
2627 /* clear Rx/Tx queue interrupt */
2628 for (i = 0; i < vsi->nb_used_qps; i++) {
2629 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2630 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2633 /* PF bind interrupt */
2634 if (rte_intr_dp_is_en(intr_handle)) {
2639 for (i = 0; i < vsi->nb_used_qps; i++) {
2641 if (!rte_intr_allow_others(intr_handle))
2642 msix_vect = ICE_MISC_VEC_ID;
2644 /* uio mapping all queue to one msix_vect */
2645 __vsi_queues_bind_intr(vsi, msix_vect,
2646 vsi->base_queue + i,
2647 vsi->nb_used_qps - i);
2649 for (; !!record && i < vsi->nb_used_qps; i++)
2650 intr_handle->intr_vec[queue_idx + i] =
2655 /* vfio 1:1 queue/msix_vect mapping */
2656 __vsi_queues_bind_intr(vsi, msix_vect,
2657 vsi->base_queue + i, 1);
2660 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2668 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2670 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2671 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2672 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2673 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2674 uint16_t msix_intr, i;
2676 if (rte_intr_allow_others(intr_handle))
2677 for (i = 0; i < vsi->nb_used_qps; i++) {
2678 msix_intr = vsi->msix_intr + i;
2679 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2680 GLINT_DYN_CTL_INTENA_M |
2681 GLINT_DYN_CTL_CLEARPBA_M |
2682 GLINT_DYN_CTL_ITR_INDX_M |
2683 GLINT_DYN_CTL_WB_ON_ITR_M);
2686 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2687 GLINT_DYN_CTL_INTENA_M |
2688 GLINT_DYN_CTL_CLEARPBA_M |
2689 GLINT_DYN_CTL_ITR_INDX_M |
2690 GLINT_DYN_CTL_WB_ON_ITR_M);
2694 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2696 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2697 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2698 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2699 struct ice_vsi *vsi = pf->main_vsi;
2700 uint32_t intr_vector = 0;
2702 rte_intr_disable(intr_handle);
2704 /* check and configure queue intr-vector mapping */
2705 if ((rte_intr_cap_multiple(intr_handle) ||
2706 !RTE_ETH_DEV_SRIOV(dev).active) &&
2707 dev->data->dev_conf.intr_conf.rxq != 0) {
2708 intr_vector = dev->data->nb_rx_queues;
2709 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2710 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2711 ICE_MAX_INTR_QUEUE_NUM);
2714 if (rte_intr_efd_enable(intr_handle, intr_vector))
2718 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2719 intr_handle->intr_vec =
2720 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2722 if (!intr_handle->intr_vec) {
2724 "Failed to allocate %d rx_queues intr_vec",
2725 dev->data->nb_rx_queues);
2730 /* Map queues with MSIX interrupt */
2731 vsi->nb_used_qps = dev->data->nb_rx_queues;
2732 ice_vsi_queues_bind_intr(vsi);
2734 /* Enable interrupts for all the queues */
2735 ice_vsi_enable_queues_intr(vsi);
2737 rte_intr_enable(intr_handle);
2743 ice_get_init_link_status(struct rte_eth_dev *dev)
2745 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2746 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2747 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2748 struct ice_link_status link_status;
2751 ret = ice_aq_get_link_info(hw->port_info, enable_lse,
2752 &link_status, NULL);
2753 if (ret != ICE_SUCCESS) {
2754 PMD_DRV_LOG(ERR, "Failed to get link info");
2755 pf->init_link_up = false;
2759 if (link_status.link_info & ICE_AQ_LINK_UP)
2760 pf->init_link_up = true;
2764 ice_dev_start(struct rte_eth_dev *dev)
2766 struct rte_eth_dev_data *data = dev->data;
2767 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2768 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2769 struct ice_vsi *vsi = pf->main_vsi;
2770 uint16_t nb_rxq = 0;
2772 uint16_t max_frame_size;
2775 /* program Tx queues' context in hardware */
2776 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2777 ret = ice_tx_queue_start(dev, nb_txq);
2779 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2784 /* program Rx queues' context in hardware*/
2785 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2786 ret = ice_rx_queue_start(dev, nb_rxq);
2788 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2793 ret = ice_init_rss(pf);
2795 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2799 ice_set_rx_function(dev);
2800 ice_set_tx_function(dev);
2802 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2803 ETH_VLAN_EXTEND_MASK;
2804 ret = ice_vlan_offload_set(dev, mask);
2806 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2810 /* enable Rx interrput and mapping Rx queue to interrupt vector */
2811 if (ice_rxq_intr_setup(dev))
2814 /* Enable receiving broadcast packets and transmitting packets */
2815 ret = ice_set_vsi_promisc(hw, vsi->idx,
2816 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2817 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2819 if (ret != ICE_SUCCESS)
2820 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2822 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2823 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2824 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2825 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2826 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2827 ICE_AQ_LINK_EVENT_AN_COMPLETED |
2828 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2830 if (ret != ICE_SUCCESS)
2831 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2833 ice_get_init_link_status(dev);
2835 ice_dev_set_link_up(dev);
2837 /* Call get_link_info aq commond to enable/disable LSE */
2838 ice_link_update(dev, 0);
2840 pf->adapter_stopped = false;
2842 /* Set the max frame size to default value*/
2843 max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
2844 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
2847 /* Set the max frame size to HW*/
2848 ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
2852 /* stop the started queues if failed to start all queues */
2854 for (i = 0; i < nb_rxq; i++)
2855 ice_rx_queue_stop(dev, i);
2857 for (i = 0; i < nb_txq; i++)
2858 ice_tx_queue_stop(dev, i);
2864 ice_dev_reset(struct rte_eth_dev *dev)
2868 if (dev->data->sriov.active)
2871 ret = ice_dev_uninit(dev);
2873 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2877 ret = ice_dev_init(dev);
2879 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2887 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2889 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2890 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2891 struct ice_vsi *vsi = pf->main_vsi;
2892 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2893 bool is_safe_mode = pf->adapter->is_safe_mode;
2897 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2898 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2899 dev_info->max_rx_queues = vsi->nb_qps;
2900 dev_info->max_tx_queues = vsi->nb_qps;
2901 dev_info->max_mac_addrs = vsi->max_macaddrs;
2902 dev_info->max_vfs = pci_dev->max_vfs;
2903 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2904 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2906 dev_info->rx_offload_capa =
2907 DEV_RX_OFFLOAD_VLAN_STRIP |
2908 DEV_RX_OFFLOAD_JUMBO_FRAME |
2909 DEV_RX_OFFLOAD_KEEP_CRC |
2910 DEV_RX_OFFLOAD_SCATTER |
2911 DEV_RX_OFFLOAD_VLAN_FILTER;
2912 dev_info->tx_offload_capa =
2913 DEV_TX_OFFLOAD_VLAN_INSERT |
2914 DEV_TX_OFFLOAD_TCP_TSO |
2915 DEV_TX_OFFLOAD_MULTI_SEGS |
2916 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2917 dev_info->flow_type_rss_offloads = 0;
2919 if (!is_safe_mode) {
2920 dev_info->rx_offload_capa |=
2921 DEV_RX_OFFLOAD_IPV4_CKSUM |
2922 DEV_RX_OFFLOAD_UDP_CKSUM |
2923 DEV_RX_OFFLOAD_TCP_CKSUM |
2924 DEV_RX_OFFLOAD_QINQ_STRIP |
2925 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2926 DEV_RX_OFFLOAD_VLAN_EXTEND |
2927 DEV_RX_OFFLOAD_RSS_HASH;
2928 dev_info->tx_offload_capa |=
2929 DEV_TX_OFFLOAD_QINQ_INSERT |
2930 DEV_TX_OFFLOAD_IPV4_CKSUM |
2931 DEV_TX_OFFLOAD_UDP_CKSUM |
2932 DEV_TX_OFFLOAD_TCP_CKSUM |
2933 DEV_TX_OFFLOAD_SCTP_CKSUM |
2934 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2935 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2936 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2939 dev_info->rx_queue_offload_capa = 0;
2940 dev_info->tx_queue_offload_capa = 0;
2942 dev_info->reta_size = pf->hash_lut_size;
2943 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2945 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2947 .pthresh = ICE_DEFAULT_RX_PTHRESH,
2948 .hthresh = ICE_DEFAULT_RX_HTHRESH,
2949 .wthresh = ICE_DEFAULT_RX_WTHRESH,
2951 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2956 dev_info->default_txconf = (struct rte_eth_txconf) {
2958 .pthresh = ICE_DEFAULT_TX_PTHRESH,
2959 .hthresh = ICE_DEFAULT_TX_HTHRESH,
2960 .wthresh = ICE_DEFAULT_TX_WTHRESH,
2962 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2963 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2967 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2968 .nb_max = ICE_MAX_RING_DESC,
2969 .nb_min = ICE_MIN_RING_DESC,
2970 .nb_align = ICE_ALIGN_RING_DESC,
2973 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2974 .nb_max = ICE_MAX_RING_DESC,
2975 .nb_min = ICE_MIN_RING_DESC,
2976 .nb_align = ICE_ALIGN_RING_DESC,
2979 dev_info->speed_capa = ETH_LINK_SPEED_10M |
2980 ETH_LINK_SPEED_100M |
2982 ETH_LINK_SPEED_2_5G |
2984 ETH_LINK_SPEED_10G |
2985 ETH_LINK_SPEED_20G |
2988 phy_type_low = hw->port_info->phy.phy_type_low;
2989 phy_type_high = hw->port_info->phy.phy_type_high;
2991 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2992 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2994 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2995 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2996 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2998 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2999 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3001 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3002 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3003 dev_info->default_rxportconf.nb_queues = 1;
3004 dev_info->default_txportconf.nb_queues = 1;
3005 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3006 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3012 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3013 struct rte_eth_link *link)
3015 struct rte_eth_link *dst = link;
3016 struct rte_eth_link *src = &dev->data->dev_link;
3018 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3019 *(uint64_t *)src) == 0)
3026 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3027 struct rte_eth_link *link)
3029 struct rte_eth_link *dst = &dev->data->dev_link;
3030 struct rte_eth_link *src = link;
3032 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3033 *(uint64_t *)src) == 0)
3040 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3042 #define CHECK_INTERVAL 100 /* 100ms */
3043 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
3044 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3045 struct ice_link_status link_status;
3046 struct rte_eth_link link, old;
3048 unsigned int rep_cnt = MAX_REPEAT_TIME;
3049 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3051 memset(&link, 0, sizeof(link));
3052 memset(&old, 0, sizeof(old));
3053 memset(&link_status, 0, sizeof(link_status));
3054 ice_atomic_read_link_status(dev, &old);
3057 /* Get link status information from hardware */
3058 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3059 &link_status, NULL);
3060 if (status != ICE_SUCCESS) {
3061 link.link_speed = ETH_SPEED_NUM_100M;
3062 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3063 PMD_DRV_LOG(ERR, "Failed to get link info");
3067 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3068 if (!wait_to_complete || link.link_status)
3071 rte_delay_ms(CHECK_INTERVAL);
3072 } while (--rep_cnt);
3074 if (!link.link_status)
3077 /* Full-duplex operation at all supported speeds */
3078 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3080 /* Parse the link status */
3081 switch (link_status.link_speed) {
3082 case ICE_AQ_LINK_SPEED_10MB:
3083 link.link_speed = ETH_SPEED_NUM_10M;
3085 case ICE_AQ_LINK_SPEED_100MB:
3086 link.link_speed = ETH_SPEED_NUM_100M;
3088 case ICE_AQ_LINK_SPEED_1000MB:
3089 link.link_speed = ETH_SPEED_NUM_1G;
3091 case ICE_AQ_LINK_SPEED_2500MB:
3092 link.link_speed = ETH_SPEED_NUM_2_5G;
3094 case ICE_AQ_LINK_SPEED_5GB:
3095 link.link_speed = ETH_SPEED_NUM_5G;
3097 case ICE_AQ_LINK_SPEED_10GB:
3098 link.link_speed = ETH_SPEED_NUM_10G;
3100 case ICE_AQ_LINK_SPEED_20GB:
3101 link.link_speed = ETH_SPEED_NUM_20G;
3103 case ICE_AQ_LINK_SPEED_25GB:
3104 link.link_speed = ETH_SPEED_NUM_25G;
3106 case ICE_AQ_LINK_SPEED_40GB:
3107 link.link_speed = ETH_SPEED_NUM_40G;
3109 case ICE_AQ_LINK_SPEED_50GB:
3110 link.link_speed = ETH_SPEED_NUM_50G;
3112 case ICE_AQ_LINK_SPEED_100GB:
3113 link.link_speed = ETH_SPEED_NUM_100G;
3115 case ICE_AQ_LINK_SPEED_UNKNOWN:
3117 PMD_DRV_LOG(ERR, "Unknown link speed");
3118 link.link_speed = ETH_SPEED_NUM_NONE;
3122 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3123 ETH_LINK_SPEED_FIXED);
3126 ice_atomic_write_link_status(dev, &link);
3127 if (link.link_status == old.link_status)
3133 /* Force the physical link state by getting the current PHY capabilities from
3134 * hardware and setting the PHY config based on the determined capabilities. If
3135 * link changes, link event will be triggered because both the Enable Automatic
3136 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3138 static enum ice_status
3139 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3141 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3142 struct ice_aqc_get_phy_caps_data *pcaps;
3143 struct ice_port_info *pi;
3144 enum ice_status status;
3146 if (!hw || !hw->port_info)
3147 return ICE_ERR_PARAM;
3151 pcaps = (struct ice_aqc_get_phy_caps_data *)
3152 ice_malloc(hw, sizeof(*pcaps));
3154 return ICE_ERR_NO_MEMORY;
3156 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3161 /* No change in link */
3162 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3163 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3166 cfg.phy_type_low = pcaps->phy_type_low;
3167 cfg.phy_type_high = pcaps->phy_type_high;
3168 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3169 cfg.low_power_ctrl = pcaps->low_power_ctrl;
3170 cfg.eee_cap = pcaps->eee_cap;
3171 cfg.eeer_value = pcaps->eeer_value;
3172 cfg.link_fec_opt = pcaps->link_fec_options;
3174 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3176 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3178 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3181 ice_free(hw, pcaps);
3186 ice_dev_set_link_up(struct rte_eth_dev *dev)
3188 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3190 return ice_force_phys_link_state(hw, true);
3194 ice_dev_set_link_down(struct rte_eth_dev *dev)
3196 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3198 return ice_force_phys_link_state(hw, false);
3202 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3204 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3205 struct rte_eth_dev_data *dev_data = pf->dev_data;
3206 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3208 /* check if mtu is within the allowed range */
3209 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3212 /* mtu setting is forbidden if port is start */
3213 if (dev_data->dev_started) {
3215 "port %d must be stopped before configuration",
3220 if (frame_size > RTE_ETHER_MAX_LEN)
3221 dev_data->dev_conf.rxmode.offloads |=
3222 DEV_RX_OFFLOAD_JUMBO_FRAME;
3224 dev_data->dev_conf.rxmode.offloads &=
3225 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3227 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3232 static int ice_macaddr_set(struct rte_eth_dev *dev,
3233 struct rte_ether_addr *mac_addr)
3235 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3236 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3237 struct ice_vsi *vsi = pf->main_vsi;
3238 struct ice_mac_filter *f;
3242 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3243 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3247 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3248 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3253 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3257 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3258 if (ret != ICE_SUCCESS) {
3259 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3262 ret = ice_add_mac_filter(vsi, mac_addr);
3263 if (ret != ICE_SUCCESS) {
3264 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3267 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
3269 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3270 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3271 if (ret != ICE_SUCCESS)
3272 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3277 /* Add a MAC address, and update filters */
3279 ice_macaddr_add(struct rte_eth_dev *dev,
3280 struct rte_ether_addr *mac_addr,
3281 __rte_unused uint32_t index,
3282 __rte_unused uint32_t pool)
3284 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3285 struct ice_vsi *vsi = pf->main_vsi;
3288 ret = ice_add_mac_filter(vsi, mac_addr);
3289 if (ret != ICE_SUCCESS) {
3290 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3297 /* Remove a MAC address, and update filters */
3299 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3301 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3302 struct ice_vsi *vsi = pf->main_vsi;
3303 struct rte_eth_dev_data *data = dev->data;
3304 struct rte_ether_addr *macaddr;
3307 macaddr = &data->mac_addrs[index];
3308 ret = ice_remove_mac_filter(vsi, macaddr);
3310 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3316 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3318 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3319 struct ice_vsi *vsi = pf->main_vsi;
3322 PMD_INIT_FUNC_TRACE();
3325 ret = ice_add_vlan_filter(vsi, vlan_id);
3327 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3331 ret = ice_remove_vlan_filter(vsi, vlan_id);
3333 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3341 /* Configure vlan filter on or off */
3343 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3345 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3346 struct ice_vsi_ctx ctxt;
3347 uint8_t sec_flags, sw_flags2;
3350 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3351 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3352 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3355 vsi->info.sec_flags |= sec_flags;
3356 vsi->info.sw_flags2 |= sw_flags2;
3358 vsi->info.sec_flags &= ~sec_flags;
3359 vsi->info.sw_flags2 &= ~sw_flags2;
3361 vsi->info.sw_id = hw->port_info->sw_id;
3362 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3363 ctxt.info.valid_sections =
3364 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3365 ICE_AQ_VSI_PROP_SECURITY_VALID);
3366 ctxt.vsi_num = vsi->vsi_id;
3368 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3370 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3371 on ? "enable" : "disable");
3374 vsi->info.valid_sections |=
3375 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3376 ICE_AQ_VSI_PROP_SECURITY_VALID);
3379 /* consist with other drivers, allow untagged packet when vlan filter on */
3381 ret = ice_add_vlan_filter(vsi, 0);
3383 ret = ice_remove_vlan_filter(vsi, 0);
3389 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3391 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3392 struct ice_vsi_ctx ctxt;
3396 /* Check if it has been already on or off */
3397 if (vsi->info.valid_sections &
3398 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3400 if ((vsi->info.vlan_flags &
3401 ICE_AQ_VSI_VLAN_EMOD_M) ==
3402 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3403 return 0; /* already on */
3405 if ((vsi->info.vlan_flags &
3406 ICE_AQ_VSI_VLAN_EMOD_M) ==
3407 ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3408 return 0; /* already off */
3413 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3415 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3416 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3417 vsi->info.vlan_flags |= vlan_flags;
3418 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3419 ctxt.info.valid_sections =
3420 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3421 ctxt.vsi_num = vsi->vsi_id;
3422 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3424 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3425 on ? "enable" : "disable");
3429 vsi->info.valid_sections |=
3430 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3436 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3438 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3439 struct ice_vsi *vsi = pf->main_vsi;
3440 struct rte_eth_rxmode *rxmode;
3442 rxmode = &dev->data->dev_conf.rxmode;
3443 if (mask & ETH_VLAN_FILTER_MASK) {
3444 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3445 ice_vsi_config_vlan_filter(vsi, TRUE);
3447 ice_vsi_config_vlan_filter(vsi, FALSE);
3450 if (mask & ETH_VLAN_STRIP_MASK) {
3451 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3452 ice_vsi_config_vlan_stripping(vsi, TRUE);
3454 ice_vsi_config_vlan_stripping(vsi, FALSE);
3457 if (mask & ETH_VLAN_EXTEND_MASK) {
3458 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3459 ice_vsi_config_double_vlan(vsi, TRUE);
3461 ice_vsi_config_double_vlan(vsi, FALSE);
3468 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3470 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3471 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3477 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3478 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3479 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3481 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3485 uint64_t *lut_dw = (uint64_t *)lut;
3486 uint16_t i, lut_size_dw = lut_size / 4;
3488 for (i = 0; i < lut_size_dw; i++)
3489 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3496 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3505 pf = ICE_VSI_TO_PF(vsi);
3506 hw = ICE_VSI_TO_HW(vsi);
3508 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3509 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3510 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3512 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3516 uint64_t *lut_dw = (uint64_t *)lut;
3517 uint16_t i, lut_size_dw = lut_size / 4;
3519 for (i = 0; i < lut_size_dw; i++)
3520 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3529 ice_rss_reta_update(struct rte_eth_dev *dev,
3530 struct rte_eth_rss_reta_entry64 *reta_conf,
3533 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3534 uint16_t i, lut_size = pf->hash_lut_size;
3535 uint16_t idx, shift;
3539 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3540 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3541 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3543 "The size of hash lookup table configured (%d)"
3544 "doesn't match the number hardware can "
3545 "supported (128, 512, 2048)",
3550 /* It MUST use the current LUT size to get the RSS lookup table,
3551 * otherwise if will fail with -100 error code.
3553 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
3555 PMD_DRV_LOG(ERR, "No memory can be allocated");
3558 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3562 for (i = 0; i < reta_size; i++) {
3563 idx = i / RTE_RETA_GROUP_SIZE;
3564 shift = i % RTE_RETA_GROUP_SIZE;
3565 if (reta_conf[idx].mask & (1ULL << shift))
3566 lut[i] = reta_conf[idx].reta[shift];
3568 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3569 if (ret == 0 && lut_size != reta_size) {
3571 "The size of hash lookup table is changed from (%d) to (%d)",
3572 lut_size, reta_size);
3573 pf->hash_lut_size = reta_size;
3583 ice_rss_reta_query(struct rte_eth_dev *dev,
3584 struct rte_eth_rss_reta_entry64 *reta_conf,
3587 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3588 uint16_t i, lut_size = pf->hash_lut_size;
3589 uint16_t idx, shift;
3593 if (reta_size != lut_size) {
3595 "The size of hash lookup table configured (%d)"
3596 "doesn't match the number hardware can "
3598 reta_size, lut_size);
3602 lut = rte_zmalloc(NULL, reta_size, 0);
3604 PMD_DRV_LOG(ERR, "No memory can be allocated");
3608 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3612 for (i = 0; i < reta_size; i++) {
3613 idx = i / RTE_RETA_GROUP_SIZE;
3614 shift = i % RTE_RETA_GROUP_SIZE;
3615 if (reta_conf[idx].mask & (1ULL << shift))
3616 reta_conf[idx].reta[shift] = lut[i];
3626 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3628 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3631 if (!key || key_len == 0) {
3632 PMD_DRV_LOG(DEBUG, "No key to be configured");
3634 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3636 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3640 struct ice_aqc_get_set_rss_keys *key_dw =
3641 (struct ice_aqc_get_set_rss_keys *)key;
3643 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3645 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3653 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3655 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3658 if (!key || !key_len)
3661 ret = ice_aq_get_rss_key
3663 (struct ice_aqc_get_set_rss_keys *)key);
3665 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3668 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3674 ice_rss_hash_update(struct rte_eth_dev *dev,
3675 struct rte_eth_rss_conf *rss_conf)
3677 enum ice_status status = ICE_SUCCESS;
3678 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3679 struct ice_vsi *vsi = pf->main_vsi;
3682 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3686 /* TODO: hash enable config, ice_add_rss_cfg */
3691 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3692 struct rte_eth_rss_conf *rss_conf)
3694 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3695 struct ice_vsi *vsi = pf->main_vsi;
3697 ice_get_rss_key(vsi, rss_conf->rss_key,
3698 &rss_conf->rss_key_len);
3700 /* TODO: default set to 0 as hf config is not supported now */
3701 rss_conf->rss_hf = 0;
3706 ice_promisc_enable(struct rte_eth_dev *dev)
3708 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3709 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710 struct ice_vsi *vsi = pf->main_vsi;
3711 enum ice_status status;
3715 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3716 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3718 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3720 case ICE_ERR_ALREADY_EXISTS:
3721 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3725 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3733 ice_promisc_disable(struct rte_eth_dev *dev)
3735 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3736 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3737 struct ice_vsi *vsi = pf->main_vsi;
3738 enum ice_status status;
3742 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3743 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3745 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3746 if (status != ICE_SUCCESS) {
3747 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3755 ice_allmulti_enable(struct rte_eth_dev *dev)
3757 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3758 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3759 struct ice_vsi *vsi = pf->main_vsi;
3760 enum ice_status status;
3764 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3766 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3769 case ICE_ERR_ALREADY_EXISTS:
3770 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3774 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3782 ice_allmulti_disable(struct rte_eth_dev *dev)
3784 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3785 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3786 struct ice_vsi *vsi = pf->main_vsi;
3787 enum ice_status status;
3791 if (dev->data->promiscuous == 1)
3792 return 0; /* must remain in all_multicast mode */
3794 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3796 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3797 if (status != ICE_SUCCESS) {
3798 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3805 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3808 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3809 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3810 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3814 msix_intr = intr_handle->intr_vec[queue_id];
3816 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3817 GLINT_DYN_CTL_ITR_INDX_M;
3818 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3820 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3821 rte_intr_ack(&pci_dev->intr_handle);
3826 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3829 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3830 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3831 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3834 msix_intr = intr_handle->intr_vec[queue_id];
3836 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3842 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3844 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3850 full_ver = hw->nvm.oem_ver;
3851 ver = (u8)(full_ver >> 24);
3852 build = (u16)((full_ver >> 8) & 0xffff);
3853 patch = (u8)(full_ver & 0xff);
3855 ret = snprintf(fw_version, fw_size,
3856 "%d.%d%d 0x%08x %d.%d.%d",
3857 ((hw->nvm.ver >> 12) & 0xf),
3858 ((hw->nvm.ver >> 4) & 0xff),
3859 (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3862 /* add the size of '\0' */
3864 if (fw_size < (u32)ret)
3871 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3874 struct ice_vsi_ctx ctxt;
3875 uint8_t vlan_flags = 0;
3878 if (!vsi || !info) {
3879 PMD_DRV_LOG(ERR, "invalid parameters");
3884 vsi->info.pvid = info->config.pvid;
3886 * If insert pvid is enabled, only tagged pkts are
3887 * allowed to be sent out.
3889 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3890 ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3893 if (info->config.reject.tagged == 0)
3894 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3896 if (info->config.reject.untagged == 0)
3897 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3899 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3900 ICE_AQ_VSI_VLAN_MODE_M);
3901 vsi->info.vlan_flags |= vlan_flags;
3902 memset(&ctxt, 0, sizeof(ctxt));
3903 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3904 ctxt.info.valid_sections =
3905 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3906 ctxt.vsi_num = vsi->vsi_id;
3908 hw = ICE_VSI_TO_HW(vsi);
3909 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3910 if (ret != ICE_SUCCESS) {
3912 "update VSI for VLAN insert failed, err %d",
3917 vsi->info.valid_sections |=
3918 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3924 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3926 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3927 struct ice_vsi *vsi = pf->main_vsi;
3928 struct rte_eth_dev_data *data = pf->dev_data;
3929 struct ice_vsi_vlan_pvid_info info;
3932 memset(&info, 0, sizeof(info));
3935 info.config.pvid = pvid;
3937 info.config.reject.tagged =
3938 data->dev_conf.txmode.hw_vlan_reject_tagged;
3939 info.config.reject.untagged =
3940 data->dev_conf.txmode.hw_vlan_reject_untagged;
3943 ret = ice_vsi_vlan_pvid_set(vsi, &info);
3945 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3953 ice_get_eeprom_length(struct rte_eth_dev *dev)
3955 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3957 /* Convert word count to byte count */
3958 return hw->nvm.sr_words << 1;
3962 ice_get_eeprom(struct rte_eth_dev *dev,
3963 struct rte_dev_eeprom_info *eeprom)
3965 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3966 uint16_t *data = eeprom->data;
3967 uint16_t first_word, last_word, nwords;
3968 enum ice_status status = ICE_SUCCESS;
3970 first_word = eeprom->offset >> 1;
3971 last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3972 nwords = last_word - first_word + 1;
3974 if (first_word >= hw->nvm.sr_words ||
3975 last_word >= hw->nvm.sr_words) {
3976 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3980 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3982 status = ice_read_sr_buf(hw, first_word, &nwords, data);
3984 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3985 eeprom->length = sizeof(uint16_t) * nwords;
3993 ice_stat_update_32(struct ice_hw *hw,
4001 new_data = (uint64_t)ICE_READ_REG(hw, reg);
4005 if (new_data >= *offset)
4006 *stat = (uint64_t)(new_data - *offset);
4008 *stat = (uint64_t)((new_data +
4009 ((uint64_t)1 << ICE_32_BIT_WIDTH))
4014 ice_stat_update_40(struct ice_hw *hw,
4023 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4024 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4030 if (new_data >= *offset)
4031 *stat = new_data - *offset;
4033 *stat = (uint64_t)((new_data +
4034 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4037 *stat &= ICE_40_BIT_MASK;
4040 /* Get all the statistics of a VSI */
4042 ice_update_vsi_stats(struct ice_vsi *vsi)
4044 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4045 struct ice_eth_stats *nes = &vsi->eth_stats;
4046 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4047 int idx = rte_le_to_cpu_16(vsi->vsi_id);
4049 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4050 vsi->offset_loaded, &oes->rx_bytes,
4052 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4053 vsi->offset_loaded, &oes->rx_unicast,
4055 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4056 vsi->offset_loaded, &oes->rx_multicast,
4057 &nes->rx_multicast);
4058 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4059 vsi->offset_loaded, &oes->rx_broadcast,
4060 &nes->rx_broadcast);
4061 /* exclude CRC bytes */
4062 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4063 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4065 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4066 &oes->rx_discards, &nes->rx_discards);
4067 /* GLV_REPC not supported */
4068 /* GLV_RMPC not supported */
4069 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4070 &oes->rx_unknown_protocol,
4071 &nes->rx_unknown_protocol);
4072 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4073 vsi->offset_loaded, &oes->tx_bytes,
4075 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4076 vsi->offset_loaded, &oes->tx_unicast,
4078 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4079 vsi->offset_loaded, &oes->tx_multicast,
4080 &nes->tx_multicast);
4081 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4082 vsi->offset_loaded, &oes->tx_broadcast,
4083 &nes->tx_broadcast);
4084 /* GLV_TDPC not supported */
4085 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4086 &oes->tx_errors, &nes->tx_errors);
4087 vsi->offset_loaded = true;
4089 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4091 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
4092 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
4093 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
4094 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
4095 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
4096 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4097 nes->rx_unknown_protocol);
4098 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
4099 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
4100 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
4101 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
4102 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
4103 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
4104 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4109 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4111 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4112 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4114 /* Get statistics of struct ice_eth_stats */
4115 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4116 GLPRT_GORCL(hw->port_info->lport),
4117 pf->offset_loaded, &os->eth.rx_bytes,
4119 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4120 GLPRT_UPRCL(hw->port_info->lport),
4121 pf->offset_loaded, &os->eth.rx_unicast,
4122 &ns->eth.rx_unicast);
4123 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4124 GLPRT_MPRCL(hw->port_info->lport),
4125 pf->offset_loaded, &os->eth.rx_multicast,
4126 &ns->eth.rx_multicast);
4127 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4128 GLPRT_BPRCL(hw->port_info->lport),
4129 pf->offset_loaded, &os->eth.rx_broadcast,
4130 &ns->eth.rx_broadcast);
4131 ice_stat_update_32(hw, PRTRPB_RDPC,
4132 pf->offset_loaded, &os->eth.rx_discards,
4133 &ns->eth.rx_discards);
4135 /* Workaround: CRC size should not be included in byte statistics,
4136 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4139 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4140 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4142 /* GLPRT_REPC not supported */
4143 /* GLPRT_RMPC not supported */
4144 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4146 &os->eth.rx_unknown_protocol,
4147 &ns->eth.rx_unknown_protocol);
4148 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4149 GLPRT_GOTCL(hw->port_info->lport),
4150 pf->offset_loaded, &os->eth.tx_bytes,
4152 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4153 GLPRT_UPTCL(hw->port_info->lport),
4154 pf->offset_loaded, &os->eth.tx_unicast,
4155 &ns->eth.tx_unicast);
4156 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4157 GLPRT_MPTCL(hw->port_info->lport),
4158 pf->offset_loaded, &os->eth.tx_multicast,
4159 &ns->eth.tx_multicast);
4160 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4161 GLPRT_BPTCL(hw->port_info->lport),
4162 pf->offset_loaded, &os->eth.tx_broadcast,
4163 &ns->eth.tx_broadcast);
4164 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4165 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4167 /* GLPRT_TEPC not supported */
4169 /* additional port specific stats */
4170 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4171 pf->offset_loaded, &os->tx_dropped_link_down,
4172 &ns->tx_dropped_link_down);
4173 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4174 pf->offset_loaded, &os->crc_errors,
4176 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4177 pf->offset_loaded, &os->illegal_bytes,
4178 &ns->illegal_bytes);
4179 /* GLPRT_ERRBC not supported */
4180 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4181 pf->offset_loaded, &os->mac_local_faults,
4182 &ns->mac_local_faults);
4183 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4184 pf->offset_loaded, &os->mac_remote_faults,
4185 &ns->mac_remote_faults);
4187 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4188 pf->offset_loaded, &os->rx_len_errors,
4189 &ns->rx_len_errors);
4191 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4192 pf->offset_loaded, &os->link_xon_rx,
4194 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4195 pf->offset_loaded, &os->link_xoff_rx,
4197 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4198 pf->offset_loaded, &os->link_xon_tx,
4200 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4201 pf->offset_loaded, &os->link_xoff_tx,
4203 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4204 GLPRT_PRC64L(hw->port_info->lport),
4205 pf->offset_loaded, &os->rx_size_64,
4207 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4208 GLPRT_PRC127L(hw->port_info->lport),
4209 pf->offset_loaded, &os->rx_size_127,
4211 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4212 GLPRT_PRC255L(hw->port_info->lport),
4213 pf->offset_loaded, &os->rx_size_255,
4215 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4216 GLPRT_PRC511L(hw->port_info->lport),
4217 pf->offset_loaded, &os->rx_size_511,
4219 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4220 GLPRT_PRC1023L(hw->port_info->lport),
4221 pf->offset_loaded, &os->rx_size_1023,
4223 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4224 GLPRT_PRC1522L(hw->port_info->lport),
4225 pf->offset_loaded, &os->rx_size_1522,
4227 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4228 GLPRT_PRC9522L(hw->port_info->lport),
4229 pf->offset_loaded, &os->rx_size_big,
4231 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4232 pf->offset_loaded, &os->rx_undersize,
4234 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4235 pf->offset_loaded, &os->rx_fragments,
4237 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4238 pf->offset_loaded, &os->rx_oversize,
4240 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4241 pf->offset_loaded, &os->rx_jabber,
4243 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4244 GLPRT_PTC64L(hw->port_info->lport),
4245 pf->offset_loaded, &os->tx_size_64,
4247 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4248 GLPRT_PTC127L(hw->port_info->lport),
4249 pf->offset_loaded, &os->tx_size_127,
4251 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4252 GLPRT_PTC255L(hw->port_info->lport),
4253 pf->offset_loaded, &os->tx_size_255,
4255 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4256 GLPRT_PTC511L(hw->port_info->lport),
4257 pf->offset_loaded, &os->tx_size_511,
4259 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4260 GLPRT_PTC1023L(hw->port_info->lport),
4261 pf->offset_loaded, &os->tx_size_1023,
4263 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4264 GLPRT_PTC1522L(hw->port_info->lport),
4265 pf->offset_loaded, &os->tx_size_1522,
4267 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4268 GLPRT_PTC9522L(hw->port_info->lport),
4269 pf->offset_loaded, &os->tx_size_big,
4272 /* GLPRT_MSPDC not supported */
4273 /* GLPRT_XEC not supported */
4275 pf->offset_loaded = true;
4278 ice_update_vsi_stats(pf->main_vsi);
4281 /* Get all statistics of a port */
4283 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4285 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4286 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4287 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4289 /* call read registers - updates values, now write them to struct */
4290 ice_read_stats_registers(pf, hw);
4292 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4293 pf->main_vsi->eth_stats.rx_multicast +
4294 pf->main_vsi->eth_stats.rx_broadcast -
4295 pf->main_vsi->eth_stats.rx_discards;
4296 stats->opackets = ns->eth.tx_unicast +
4297 ns->eth.tx_multicast +
4298 ns->eth.tx_broadcast;
4299 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
4300 stats->obytes = ns->eth.tx_bytes;
4301 stats->oerrors = ns->eth.tx_errors +
4302 pf->main_vsi->eth_stats.tx_errors;
4305 stats->imissed = ns->eth.rx_discards +
4306 pf->main_vsi->eth_stats.rx_discards;
4307 stats->ierrors = ns->crc_errors +
4309 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4311 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4312 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
4313 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4314 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4315 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4316 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4317 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4318 pf->main_vsi->eth_stats.rx_discards);
4319 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4320 ns->eth.rx_unknown_protocol);
4321 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
4322 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4323 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4324 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4325 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4326 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4327 pf->main_vsi->eth_stats.tx_discards);
4328 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
4330 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
4331 ns->tx_dropped_link_down);
4332 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4333 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
4335 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
4336 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
4337 ns->mac_local_faults);
4338 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
4339 ns->mac_remote_faults);
4340 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
4341 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
4342 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
4343 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
4344 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
4345 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
4346 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
4347 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
4348 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
4349 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
4350 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
4351 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
4352 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
4353 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
4354 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
4355 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
4356 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
4357 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
4358 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
4359 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
4360 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
4361 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
4362 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
4363 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4367 /* Reset the statistics */
4369 ice_stats_reset(struct rte_eth_dev *dev)
4371 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4372 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4374 /* Mark PF and VSI stats to update the offset, aka "reset" */
4375 pf->offset_loaded = false;
4377 pf->main_vsi->offset_loaded = false;
4379 /* read the stats, reading current register values into offset */
4380 ice_read_stats_registers(pf, hw);
4386 ice_xstats_calc_num(void)
4390 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4396 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4399 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4400 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4403 struct ice_hw_port_stats *hw_stats = &pf->stats;
4405 count = ice_xstats_calc_num();
4409 ice_read_stats_registers(pf, hw);
4416 /* Get stats from ice_eth_stats struct */
4417 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4418 xstats[count].value =
4419 *(uint64_t *)((char *)&hw_stats->eth +
4420 ice_stats_strings[i].offset);
4421 xstats[count].id = count;
4425 /* Get individiual stats from ice_hw_port struct */
4426 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4427 xstats[count].value =
4428 *(uint64_t *)((char *)hw_stats +
4429 ice_hw_port_strings[i].offset);
4430 xstats[count].id = count;
4437 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4438 struct rte_eth_xstat_name *xstats_names,
4439 __rte_unused unsigned int limit)
4441 unsigned int count = 0;
4445 return ice_xstats_calc_num();
4447 /* Note: limit checked in rte_eth_xstats_names() */
4449 /* Get stats from ice_eth_stats struct */
4450 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4451 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4452 sizeof(xstats_names[count].name));
4456 /* Get individiual stats from ice_hw_port struct */
4457 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4458 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4459 sizeof(xstats_names[count].name));
4467 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4468 enum rte_filter_type filter_type,
4469 enum rte_filter_op filter_op,
4477 switch (filter_type) {
4478 case RTE_ETH_FILTER_GENERIC:
4479 if (filter_op != RTE_ETH_FILTER_GET)
4481 *(const void **)arg = &ice_flow_ops;
4484 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4493 /* Add UDP tunneling port */
4495 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4496 struct rte_eth_udp_tunnel *udp_tunnel)
4499 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4501 if (udp_tunnel == NULL)
4504 switch (udp_tunnel->prot_type) {
4505 case RTE_TUNNEL_TYPE_VXLAN:
4506 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4509 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4517 /* Delete UDP tunneling port */
4519 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4520 struct rte_eth_udp_tunnel *udp_tunnel)
4523 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4525 if (udp_tunnel == NULL)
4528 switch (udp_tunnel->prot_type) {
4529 case RTE_TUNNEL_TYPE_VXLAN:
4530 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4533 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4542 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4543 struct rte_pci_device *pci_dev)
4545 return rte_eth_dev_pci_generic_probe(pci_dev,
4546 sizeof(struct ice_adapter),
4551 ice_pci_remove(struct rte_pci_device *pci_dev)
4553 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4556 static struct rte_pci_driver rte_ice_pmd = {
4557 .id_table = pci_id_ice_map,
4558 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4559 .probe = ice_pci_probe,
4560 .remove = ice_pci_remove,
4564 * Driver initialization routine.
4565 * Invoked once at EAL init time.
4566 * Register itself as the [Poll Mode] Driver of PCI devices.
4568 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4569 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4570 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4571 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4572 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4573 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4574 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
4575 ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>");
4577 RTE_INIT(ice_init_log)
4579 ice_logtype_init = rte_log_register("pmd.net.ice.init");
4580 if (ice_logtype_init >= 0)
4581 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4582 ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4583 if (ice_logtype_driver >= 0)
4584 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4586 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4587 ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4588 if (ice_logtype_rx >= 0)
4589 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4592 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4593 ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4594 if (ice_logtype_tx >= 0)
4595 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4598 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4599 ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4600 if (ice_logtype_tx_free >= 0)
4601 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);