1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
40 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
41 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
42 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
44 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
47 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
48 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
55 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 u16 words, u16 *data);
59 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 * ixgbe_init_ops_generic - Inits function ptrs
64 * @hw: pointer to the hardware structure
66 * Initialize the function pointers.
68 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
70 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
71 struct ixgbe_mac_info *mac = &hw->mac;
72 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
74 DEBUGFUNC("ixgbe_init_ops_generic");
77 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
78 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
79 if (eec & IXGBE_EEC_PRES) {
80 eeprom->ops.read = ixgbe_read_eerd_generic;
81 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
83 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
84 eeprom->ops.read_buffer =
85 ixgbe_read_eeprom_buffer_bit_bang_generic;
87 eeprom->ops.write = ixgbe_write_eeprom_generic;
88 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
89 eeprom->ops.validate_checksum =
90 ixgbe_validate_eeprom_checksum_generic;
91 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
92 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
95 mac->ops.init_hw = ixgbe_init_hw_generic;
96 mac->ops.reset_hw = NULL;
97 mac->ops.start_hw = ixgbe_start_hw_generic;
98 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
99 mac->ops.get_media_type = NULL;
100 mac->ops.get_supported_physical_layer = NULL;
101 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
102 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
103 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
104 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
105 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
106 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
107 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
108 mac->ops.prot_autoc_read = prot_autoc_read_generic;
109 mac->ops.prot_autoc_write = prot_autoc_write_generic;
112 mac->ops.led_on = ixgbe_led_on_generic;
113 mac->ops.led_off = ixgbe_led_off_generic;
114 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
115 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
117 /* RAR, Multicast, VLAN */
118 mac->ops.set_rar = ixgbe_set_rar_generic;
119 mac->ops.clear_rar = ixgbe_clear_rar_generic;
120 mac->ops.insert_mac_addr = NULL;
121 mac->ops.set_vmdq = NULL;
122 mac->ops.clear_vmdq = NULL;
123 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
124 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
125 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
126 mac->ops.enable_mc = ixgbe_enable_mc_generic;
127 mac->ops.disable_mc = ixgbe_disable_mc_generic;
128 mac->ops.clear_vfta = NULL;
129 mac->ops.set_vfta = NULL;
130 mac->ops.set_vlvf = NULL;
131 mac->ops.init_uta_tables = NULL;
132 mac->ops.enable_rx = ixgbe_enable_rx_generic;
133 mac->ops.disable_rx = ixgbe_disable_rx_generic;
136 mac->ops.fc_enable = ixgbe_fc_enable_generic;
137 mac->ops.setup_fc = ixgbe_setup_fc_generic;
138 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
141 mac->ops.get_link_capabilities = NULL;
142 mac->ops.setup_link = NULL;
143 mac->ops.check_link = NULL;
144 mac->ops.dmac_config = NULL;
145 mac->ops.dmac_update_tcs = NULL;
146 mac->ops.dmac_config_tcs = NULL;
148 return IXGBE_SUCCESS;
152 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
154 * @hw: pointer to hardware structure
156 * This function returns true if the device supports flow control
157 * autonegotiation, and false if it does not.
160 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
162 bool supported = false;
163 ixgbe_link_speed speed;
166 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
168 switch (hw->phy.media_type) {
169 case ixgbe_media_type_fiber_qsfp:
170 case ixgbe_media_type_fiber:
171 hw->mac.ops.check_link(hw, &speed, &link_up, false);
172 /* if link is down, assume supported */
174 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
179 case ixgbe_media_type_backplane:
182 case ixgbe_media_type_copper:
183 /* only some copper devices support flow control autoneg */
184 switch (hw->device_id) {
185 case IXGBE_DEV_ID_82599_T3_LOM:
186 case IXGBE_DEV_ID_X540T:
187 case IXGBE_DEV_ID_X540T1:
188 case IXGBE_DEV_ID_X550T:
189 case IXGBE_DEV_ID_X550T1:
190 case IXGBE_DEV_ID_X550EM_X_10G_T:
191 case IXGBE_DEV_ID_X550EM_A_10G_T:
201 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
202 "Device %x does not support flow control autoneg",
208 * ixgbe_setup_fc_generic - Set up flow control
209 * @hw: pointer to hardware structure
211 * Called at init time to set up flow control.
213 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
215 s32 ret_val = IXGBE_SUCCESS;
216 u32 reg = 0, reg_bp = 0;
220 DEBUGFUNC("ixgbe_setup_fc_generic");
222 /* Validate the requested mode */
223 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
224 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
225 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
226 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
231 * 10gig parts do not have a word in the EEPROM to determine the
232 * default flow control setting, so we explicitly set it to full.
234 if (hw->fc.requested_mode == ixgbe_fc_default)
235 hw->fc.requested_mode = ixgbe_fc_full;
238 * Set up the 1G and 10G flow control advertisement registers so the
239 * HW will be able to do fc autoneg once the cable is plugged in. If
240 * we link at 10G, the 1G advertisement is harmless and vice versa.
242 switch (hw->phy.media_type) {
243 case ixgbe_media_type_backplane:
244 /* some MAC's need RMW protection on AUTOC */
245 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
246 if (ret_val != IXGBE_SUCCESS)
249 /* only backplane uses autoc so fall though */
250 case ixgbe_media_type_fiber_qsfp:
251 case ixgbe_media_type_fiber:
252 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
255 case ixgbe_media_type_copper:
256 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
257 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
264 * The possible values of fc.requested_mode are:
265 * 0: Flow control is completely disabled
266 * 1: Rx flow control is enabled (we can receive pause frames,
267 * but not send pause frames).
268 * 2: Tx flow control is enabled (we can send pause frames but
269 * we do not support receiving pause frames).
270 * 3: Both Rx and Tx flow control (symmetric) are enabled.
273 switch (hw->fc.requested_mode) {
275 /* Flow control completely disabled by software override. */
276 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
277 if (hw->phy.media_type == ixgbe_media_type_backplane)
278 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
279 IXGBE_AUTOC_ASM_PAUSE);
280 else if (hw->phy.media_type == ixgbe_media_type_copper)
281 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
283 case ixgbe_fc_tx_pause:
285 * Tx Flow control is enabled, and Rx Flow control is
286 * disabled by software override.
288 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
289 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
290 if (hw->phy.media_type == ixgbe_media_type_backplane) {
291 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
292 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
293 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
294 reg_cu |= IXGBE_TAF_ASM_PAUSE;
295 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
298 case ixgbe_fc_rx_pause:
300 * Rx Flow control is enabled and Tx Flow control is
301 * disabled by software override. Since there really
302 * isn't a way to advertise that we are capable of RX
303 * Pause ONLY, we will advertise that we support both
304 * symmetric and asymmetric Rx PAUSE, as such we fall
305 * through to the fc_full statement. Later, we will
306 * disable the adapter's ability to send PAUSE frames.
309 /* Flow control (both Rx and Tx) is enabled by SW override. */
310 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
311 if (hw->phy.media_type == ixgbe_media_type_backplane)
312 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
313 IXGBE_AUTOC_ASM_PAUSE;
314 else if (hw->phy.media_type == ixgbe_media_type_copper)
315 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
318 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
319 "Flow control param set incorrectly\n");
320 ret_val = IXGBE_ERR_CONFIG;
325 if (hw->mac.type < ixgbe_mac_X540) {
327 * Enable auto-negotiation between the MAC & PHY;
328 * the MAC will advertise clause 37 flow control.
330 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
331 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
333 /* Disable AN timeout */
334 if (hw->fc.strict_ieee)
335 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
337 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
338 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
342 * AUTOC restart handles negotiation of 1G and 10G on backplane
343 * and copper. There is no need to set the PCS1GCTL register.
346 if (hw->phy.media_type == ixgbe_media_type_backplane) {
347 reg_bp |= IXGBE_AUTOC_AN_RESTART;
348 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
351 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
352 (ixgbe_device_supports_autoneg_fc(hw))) {
353 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
354 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
357 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
363 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
364 * @hw: pointer to hardware structure
366 * Starts the hardware by filling the bus info structure and media type, clears
367 * all on chip counters, initializes receive address registers, multicast
368 * table, VLAN filter table, calls routine to set up link and flow control
369 * settings, and leaves transmit and receive units disabled and uninitialized
371 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
377 DEBUGFUNC("ixgbe_start_hw_generic");
379 /* Set the media type */
380 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
382 /* PHY ops initialization must be done in reset_hw() */
384 /* Clear the VLAN filter table */
385 hw->mac.ops.clear_vfta(hw);
387 /* Clear statistics registers */
388 hw->mac.ops.clear_hw_cntrs(hw);
390 /* Set No Snoop Disable */
391 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
392 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
393 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
394 IXGBE_WRITE_FLUSH(hw);
396 /* Setup flow control */
397 ret_val = ixgbe_setup_fc(hw);
398 if (ret_val != IXGBE_SUCCESS)
401 /* Cache bit indicating need for crosstalk fix */
402 switch (hw->mac.type) {
403 case ixgbe_mac_82599EB:
404 case ixgbe_mac_X550EM_x:
405 case ixgbe_mac_X550EM_a:
406 hw->mac.ops.get_device_caps(hw, &device_caps);
407 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
408 hw->need_crosstalk_fix = false;
410 hw->need_crosstalk_fix = true;
413 hw->need_crosstalk_fix = false;
417 /* Clear adapter stopped flag */
418 hw->adapter_stopped = false;
425 * ixgbe_start_hw_gen2 - Init sequence for common device family
426 * @hw: pointer to hw structure
428 * Performs the init sequence common to the second generation
430 * Devices in the second generation:
434 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
439 /* Clear the rate limiters */
440 for (i = 0; i < hw->mac.max_tx_queues; i++) {
441 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
442 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
444 IXGBE_WRITE_FLUSH(hw);
446 /* Disable relaxed ordering */
447 for (i = 0; i < hw->mac.max_tx_queues; i++) {
448 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
449 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
450 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
453 for (i = 0; i < hw->mac.max_rx_queues; i++) {
454 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
455 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
456 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
457 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
460 return IXGBE_SUCCESS;
464 * ixgbe_init_hw_generic - Generic hardware initialization
465 * @hw: pointer to hardware structure
467 * Initialize the hardware by resetting the hardware, filling the bus info
468 * structure and media type, clears all on chip counters, initializes receive
469 * address registers, multicast table, VLAN filter table, calls routine to set
470 * up link and flow control settings, and leaves transmit and receive units
471 * disabled and uninitialized
473 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
477 DEBUGFUNC("ixgbe_init_hw_generic");
479 /* Reset the hardware */
480 status = hw->mac.ops.reset_hw(hw);
482 if (status == IXGBE_SUCCESS) {
484 status = hw->mac.ops.start_hw(hw);
491 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
492 * @hw: pointer to hardware structure
494 * Clears all hardware statistics counters by reading them from the hardware
495 * Statistics counters are clear on read.
497 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
501 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
503 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
504 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
505 IXGBE_READ_REG(hw, IXGBE_ERRBC);
506 IXGBE_READ_REG(hw, IXGBE_MSPDC);
507 for (i = 0; i < 8; i++)
508 IXGBE_READ_REG(hw, IXGBE_MPC(i));
510 IXGBE_READ_REG(hw, IXGBE_MLFC);
511 IXGBE_READ_REG(hw, IXGBE_MRFC);
512 IXGBE_READ_REG(hw, IXGBE_RLEC);
513 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
514 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
515 if (hw->mac.type >= ixgbe_mac_82599EB) {
516 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
517 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
519 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
520 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
523 for (i = 0; i < 8; i++) {
524 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
525 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
526 if (hw->mac.type >= ixgbe_mac_82599EB) {
527 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
528 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
530 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
531 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
534 if (hw->mac.type >= ixgbe_mac_82599EB)
535 for (i = 0; i < 8; i++)
536 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
537 IXGBE_READ_REG(hw, IXGBE_PRC64);
538 IXGBE_READ_REG(hw, IXGBE_PRC127);
539 IXGBE_READ_REG(hw, IXGBE_PRC255);
540 IXGBE_READ_REG(hw, IXGBE_PRC511);
541 IXGBE_READ_REG(hw, IXGBE_PRC1023);
542 IXGBE_READ_REG(hw, IXGBE_PRC1522);
543 IXGBE_READ_REG(hw, IXGBE_GPRC);
544 IXGBE_READ_REG(hw, IXGBE_BPRC);
545 IXGBE_READ_REG(hw, IXGBE_MPRC);
546 IXGBE_READ_REG(hw, IXGBE_GPTC);
547 IXGBE_READ_REG(hw, IXGBE_GORCL);
548 IXGBE_READ_REG(hw, IXGBE_GORCH);
549 IXGBE_READ_REG(hw, IXGBE_GOTCL);
550 IXGBE_READ_REG(hw, IXGBE_GOTCH);
551 if (hw->mac.type == ixgbe_mac_82598EB)
552 for (i = 0; i < 8; i++)
553 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
554 IXGBE_READ_REG(hw, IXGBE_RUC);
555 IXGBE_READ_REG(hw, IXGBE_RFC);
556 IXGBE_READ_REG(hw, IXGBE_ROC);
557 IXGBE_READ_REG(hw, IXGBE_RJC);
558 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
559 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
560 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
561 IXGBE_READ_REG(hw, IXGBE_TORL);
562 IXGBE_READ_REG(hw, IXGBE_TORH);
563 IXGBE_READ_REG(hw, IXGBE_TPR);
564 IXGBE_READ_REG(hw, IXGBE_TPT);
565 IXGBE_READ_REG(hw, IXGBE_PTC64);
566 IXGBE_READ_REG(hw, IXGBE_PTC127);
567 IXGBE_READ_REG(hw, IXGBE_PTC255);
568 IXGBE_READ_REG(hw, IXGBE_PTC511);
569 IXGBE_READ_REG(hw, IXGBE_PTC1023);
570 IXGBE_READ_REG(hw, IXGBE_PTC1522);
571 IXGBE_READ_REG(hw, IXGBE_MPTC);
572 IXGBE_READ_REG(hw, IXGBE_BPTC);
573 for (i = 0; i < 16; i++) {
574 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
575 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
576 if (hw->mac.type >= ixgbe_mac_82599EB) {
577 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
578 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
579 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
580 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
581 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
583 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
584 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
588 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
590 ixgbe_identify_phy(hw);
591 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
592 IXGBE_MDIO_PCS_DEV_TYPE, &i);
593 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
594 IXGBE_MDIO_PCS_DEV_TYPE, &i);
595 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
596 IXGBE_MDIO_PCS_DEV_TYPE, &i);
597 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
598 IXGBE_MDIO_PCS_DEV_TYPE, &i);
601 return IXGBE_SUCCESS;
605 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
606 * @hw: pointer to hardware structure
607 * @pba_num: stores the part number string from the EEPROM
608 * @pba_num_size: part number string buffer length
610 * Reads the part number string from the EEPROM.
612 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
621 DEBUGFUNC("ixgbe_read_pba_string_generic");
623 if (pba_num == NULL) {
624 DEBUGOUT("PBA string buffer was null\n");
625 return IXGBE_ERR_INVALID_ARGUMENT;
628 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
630 DEBUGOUT("NVM Read Error\n");
634 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
636 DEBUGOUT("NVM Read Error\n");
641 * if data is not ptr guard the PBA must be in legacy format which
642 * means pba_ptr is actually our second data word for the PBA number
643 * and we can decode it into an ascii string
645 if (data != IXGBE_PBANUM_PTR_GUARD) {
646 DEBUGOUT("NVM PBA number is not stored as string\n");
648 /* we will need 11 characters to store the PBA */
649 if (pba_num_size < 11) {
650 DEBUGOUT("PBA string buffer too small\n");
651 return IXGBE_ERR_NO_SPACE;
654 /* extract hex string from data and pba_ptr */
655 pba_num[0] = (data >> 12) & 0xF;
656 pba_num[1] = (data >> 8) & 0xF;
657 pba_num[2] = (data >> 4) & 0xF;
658 pba_num[3] = data & 0xF;
659 pba_num[4] = (pba_ptr >> 12) & 0xF;
660 pba_num[5] = (pba_ptr >> 8) & 0xF;
663 pba_num[8] = (pba_ptr >> 4) & 0xF;
664 pba_num[9] = pba_ptr & 0xF;
666 /* put a null character on the end of our string */
669 /* switch all the data but the '-' to hex char */
670 for (offset = 0; offset < 10; offset++) {
671 if (pba_num[offset] < 0xA)
672 pba_num[offset] += '0';
673 else if (pba_num[offset] < 0x10)
674 pba_num[offset] += 'A' - 0xA;
677 return IXGBE_SUCCESS;
680 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
682 DEBUGOUT("NVM Read Error\n");
686 if (length == 0xFFFF || length == 0) {
687 DEBUGOUT("NVM PBA number section invalid length\n");
688 return IXGBE_ERR_PBA_SECTION;
691 /* check if pba_num buffer is big enough */
692 if (pba_num_size < (((u32)length * 2) - 1)) {
693 DEBUGOUT("PBA string buffer too small\n");
694 return IXGBE_ERR_NO_SPACE;
697 /* trim pba length from start of string */
701 for (offset = 0; offset < length; offset++) {
702 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
704 DEBUGOUT("NVM Read Error\n");
707 pba_num[offset * 2] = (u8)(data >> 8);
708 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
710 pba_num[offset * 2] = '\0';
712 return IXGBE_SUCCESS;
716 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
717 * @hw: pointer to hardware structure
718 * @pba_num: stores the part number from the EEPROM
720 * Reads the part number from the EEPROM.
722 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
727 DEBUGFUNC("ixgbe_read_pba_num_generic");
729 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
731 DEBUGOUT("NVM Read Error\n");
733 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
734 DEBUGOUT("NVM Not supported\n");
735 return IXGBE_NOT_IMPLEMENTED;
737 *pba_num = (u32)(data << 16);
739 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
741 DEBUGOUT("NVM Read Error\n");
746 return IXGBE_SUCCESS;
751 * @hw: pointer to the HW structure
752 * @eeprom_buf: optional pointer to EEPROM image
753 * @eeprom_buf_size: size of EEPROM image in words
754 * @max_pba_block_size: PBA block size limit
755 * @pba: pointer to output PBA structure
757 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
758 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
761 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
762 u32 eeprom_buf_size, u16 max_pba_block_size,
763 struct ixgbe_pba *pba)
769 return IXGBE_ERR_PARAM;
771 if (eeprom_buf == NULL) {
772 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
777 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
778 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
779 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
781 return IXGBE_ERR_PARAM;
785 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
786 if (pba->pba_block == NULL)
787 return IXGBE_ERR_PARAM;
789 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
795 if (pba_block_size > max_pba_block_size)
796 return IXGBE_ERR_PARAM;
798 if (eeprom_buf == NULL) {
799 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
805 if (eeprom_buf_size > (u32)(pba->word[1] +
807 memcpy(pba->pba_block,
808 &eeprom_buf[pba->word[1]],
809 pba_block_size * sizeof(u16));
811 return IXGBE_ERR_PARAM;
816 return IXGBE_SUCCESS;
820 * ixgbe_write_pba_raw
821 * @hw: pointer to the HW structure
822 * @eeprom_buf: optional pointer to EEPROM image
823 * @eeprom_buf_size: size of EEPROM image in words
824 * @pba: pointer to PBA structure
826 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
827 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
830 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
831 u32 eeprom_buf_size, struct ixgbe_pba *pba)
836 return IXGBE_ERR_PARAM;
838 if (eeprom_buf == NULL) {
839 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
844 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
845 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
846 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
848 return IXGBE_ERR_PARAM;
852 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
853 if (pba->pba_block == NULL)
854 return IXGBE_ERR_PARAM;
856 if (eeprom_buf == NULL) {
857 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
863 if (eeprom_buf_size > (u32)(pba->word[1] +
864 pba->pba_block[0])) {
865 memcpy(&eeprom_buf[pba->word[1]],
867 pba->pba_block[0] * sizeof(u16));
869 return IXGBE_ERR_PARAM;
874 return IXGBE_SUCCESS;
878 * ixgbe_get_pba_block_size
879 * @hw: pointer to the HW structure
880 * @eeprom_buf: optional pointer to EEPROM image
881 * @eeprom_buf_size: size of EEPROM image in words
882 * @pba_data_size: pointer to output variable
884 * Returns the size of the PBA block in words. Function operates on EEPROM
885 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
889 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
890 u32 eeprom_buf_size, u16 *pba_block_size)
896 DEBUGFUNC("ixgbe_get_pba_block_size");
898 if (eeprom_buf == NULL) {
899 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
904 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
905 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
906 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
908 return IXGBE_ERR_PARAM;
912 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
913 if (eeprom_buf == NULL) {
914 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
919 if (eeprom_buf_size > pba_word[1])
920 length = eeprom_buf[pba_word[1] + 0];
922 return IXGBE_ERR_PARAM;
925 if (length == 0xFFFF || length == 0)
926 return IXGBE_ERR_PBA_SECTION;
928 /* PBA number in legacy format, there is no PBA Block. */
932 if (pba_block_size != NULL)
933 *pba_block_size = length;
935 return IXGBE_SUCCESS;
939 * ixgbe_get_mac_addr_generic - Generic get MAC address
940 * @hw: pointer to hardware structure
941 * @mac_addr: Adapter MAC address
943 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
944 * A reset of the adapter must be performed prior to calling this function
945 * in order for the MAC address to have been loaded from the EEPROM into RAR0
947 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
953 DEBUGFUNC("ixgbe_get_mac_addr_generic");
955 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
956 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
958 for (i = 0; i < 4; i++)
959 mac_addr[i] = (u8)(rar_low >> (i*8));
961 for (i = 0; i < 2; i++)
962 mac_addr[i+4] = (u8)(rar_high >> (i*8));
964 return IXGBE_SUCCESS;
968 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
969 * @hw: pointer to hardware structure
970 * @link_status: the link status returned by the PCI config space
972 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
974 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
976 struct ixgbe_mac_info *mac = &hw->mac;
978 if (hw->bus.type == ixgbe_bus_type_unknown)
979 hw->bus.type = ixgbe_bus_type_pci_express;
981 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
982 case IXGBE_PCI_LINK_WIDTH_1:
983 hw->bus.width = ixgbe_bus_width_pcie_x1;
985 case IXGBE_PCI_LINK_WIDTH_2:
986 hw->bus.width = ixgbe_bus_width_pcie_x2;
988 case IXGBE_PCI_LINK_WIDTH_4:
989 hw->bus.width = ixgbe_bus_width_pcie_x4;
991 case IXGBE_PCI_LINK_WIDTH_8:
992 hw->bus.width = ixgbe_bus_width_pcie_x8;
995 hw->bus.width = ixgbe_bus_width_unknown;
999 switch (link_status & IXGBE_PCI_LINK_SPEED) {
1000 case IXGBE_PCI_LINK_SPEED_2500:
1001 hw->bus.speed = ixgbe_bus_speed_2500;
1003 case IXGBE_PCI_LINK_SPEED_5000:
1004 hw->bus.speed = ixgbe_bus_speed_5000;
1006 case IXGBE_PCI_LINK_SPEED_8000:
1007 hw->bus.speed = ixgbe_bus_speed_8000;
1010 hw->bus.speed = ixgbe_bus_speed_unknown;
1014 mac->ops.set_lan_id(hw);
1018 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1019 * @hw: pointer to hardware structure
1021 * Gets the PCI bus info (speed, width, type) then calls helper function to
1022 * store this data within the ixgbe_hw structure.
1024 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1028 DEBUGFUNC("ixgbe_get_bus_info_generic");
1030 /* Get the negotiated link width and speed from PCI config space */
1031 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1033 ixgbe_set_pci_config_data_generic(hw, link_status);
1035 return IXGBE_SUCCESS;
1039 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1040 * @hw: pointer to the HW structure
1042 * Determines the LAN function id by reading memory-mapped registers and swaps
1043 * the port value if requested, and set MAC instance for devices that share
1046 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1048 struct ixgbe_bus_info *bus = &hw->bus;
1052 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1054 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1055 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1056 bus->lan_id = (u8)bus->func;
1058 /* check for a port swap */
1059 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1060 if (reg & IXGBE_FACTPS_LFS)
1063 /* Get MAC instance from EEPROM for configuring CS4227 */
1064 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1065 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1066 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1067 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1072 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1073 * @hw: pointer to hardware structure
1075 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1076 * disables transmit and receive units. The adapter_stopped flag is used by
1077 * the shared code and drivers to determine if the adapter is in a stopped
1078 * state and should not touch the hardware.
1080 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1085 DEBUGFUNC("ixgbe_stop_adapter_generic");
1088 * Set the adapter_stopped flag so other driver functions stop touching
1091 hw->adapter_stopped = true;
1093 /* Disable the receive unit */
1094 ixgbe_disable_rx(hw);
1096 /* Clear interrupt mask to stop interrupts from being generated */
1097 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1099 /* Clear any pending interrupts, flush previous writes */
1100 IXGBE_READ_REG(hw, IXGBE_EICR);
1102 /* Disable the transmit unit. Each queue must be disabled. */
1103 for (i = 0; i < hw->mac.max_tx_queues; i++)
1104 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1106 /* Disable the receive unit by stopping each queue */
1107 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1108 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1109 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1110 reg_val |= IXGBE_RXDCTL_SWFLSH;
1111 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1114 /* flush all queues disables */
1115 IXGBE_WRITE_FLUSH(hw);
1119 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1120 * access and verify no pending requests
1122 return ixgbe_disable_pcie_master(hw);
1126 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1127 * @hw: pointer to hardware structure
1128 * @index: led number to turn on
1130 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1132 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1134 DEBUGFUNC("ixgbe_led_on_generic");
1137 return IXGBE_ERR_PARAM;
1139 /* To turn on the LED, set mode to ON. */
1140 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1141 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1142 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1143 IXGBE_WRITE_FLUSH(hw);
1145 return IXGBE_SUCCESS;
1149 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1150 * @hw: pointer to hardware structure
1151 * @index: led number to turn off
1153 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1155 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1157 DEBUGFUNC("ixgbe_led_off_generic");
1160 return IXGBE_ERR_PARAM;
1162 /* To turn off the LED, set mode to OFF. */
1163 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1164 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1165 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1166 IXGBE_WRITE_FLUSH(hw);
1168 return IXGBE_SUCCESS;
1172 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1173 * @hw: pointer to hardware structure
1175 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1176 * ixgbe_hw struct in order to set up EEPROM access.
1178 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1180 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1184 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1186 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1187 eeprom->type = ixgbe_eeprom_none;
1188 /* Set default semaphore delay to 10ms which is a well
1190 eeprom->semaphore_delay = 10;
1191 /* Clear EEPROM page size, it will be initialized as needed */
1192 eeprom->word_page_size = 0;
1195 * Check for EEPROM present first.
1196 * If not present leave as none
1198 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1199 if (eec & IXGBE_EEC_PRES) {
1200 eeprom->type = ixgbe_eeprom_spi;
1203 * SPI EEPROM is assumed here. This code would need to
1204 * change if a future EEPROM is not SPI.
1206 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1207 IXGBE_EEC_SIZE_SHIFT);
1208 eeprom->word_size = 1 << (eeprom_size +
1209 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1212 if (eec & IXGBE_EEC_ADDR_SIZE)
1213 eeprom->address_bits = 16;
1215 eeprom->address_bits = 8;
1216 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1217 "%d\n", eeprom->type, eeprom->word_size,
1218 eeprom->address_bits);
1221 return IXGBE_SUCCESS;
1225 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1226 * @hw: pointer to hardware structure
1227 * @offset: offset within the EEPROM to write
1228 * @words: number of word(s)
1229 * @data: 16 bit word(s) to write to EEPROM
1231 * Reads 16 bit word(s) from EEPROM through bit-bang method
1233 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1234 u16 words, u16 *data)
1236 s32 status = IXGBE_SUCCESS;
1239 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1241 hw->eeprom.ops.init_params(hw);
1244 status = IXGBE_ERR_INVALID_ARGUMENT;
1248 if (offset + words > hw->eeprom.word_size) {
1249 status = IXGBE_ERR_EEPROM;
1254 * The EEPROM page size cannot be queried from the chip. We do lazy
1255 * initialization. It is worth to do that when we write large buffer.
1257 if ((hw->eeprom.word_page_size == 0) &&
1258 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1259 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1262 * We cannot hold synchronization semaphores for too long
1263 * to avoid other entity starvation. However it is more efficient
1264 * to read in bursts than synchronizing access for each word.
1266 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1267 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1268 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1269 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1272 if (status != IXGBE_SUCCESS)
1281 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1282 * @hw: pointer to hardware structure
1283 * @offset: offset within the EEPROM to be written to
1284 * @words: number of word(s)
1285 * @data: 16 bit word(s) to be written to the EEPROM
1287 * If ixgbe_eeprom_update_checksum is not called after this function, the
1288 * EEPROM will most likely contain an invalid checksum.
1290 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1291 u16 words, u16 *data)
1297 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1299 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1301 /* Prepare the EEPROM for writing */
1302 status = ixgbe_acquire_eeprom(hw);
1304 if (status == IXGBE_SUCCESS) {
1305 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1306 ixgbe_release_eeprom(hw);
1307 status = IXGBE_ERR_EEPROM;
1311 if (status == IXGBE_SUCCESS) {
1312 for (i = 0; i < words; i++) {
1313 ixgbe_standby_eeprom(hw);
1315 /* Send the WRITE ENABLE command (8 bit opcode ) */
1316 ixgbe_shift_out_eeprom_bits(hw,
1317 IXGBE_EEPROM_WREN_OPCODE_SPI,
1318 IXGBE_EEPROM_OPCODE_BITS);
1320 ixgbe_standby_eeprom(hw);
1323 * Some SPI eeproms use the 8th address bit embedded
1326 if ((hw->eeprom.address_bits == 8) &&
1327 ((offset + i) >= 128))
1328 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1330 /* Send the Write command (8-bit opcode + addr) */
1331 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1332 IXGBE_EEPROM_OPCODE_BITS);
1333 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1334 hw->eeprom.address_bits);
1336 page_size = hw->eeprom.word_page_size;
1338 /* Send the data in burst via SPI*/
1341 word = (word >> 8) | (word << 8);
1342 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1347 /* do not wrap around page */
1348 if (((offset + i) & (page_size - 1)) ==
1351 } while (++i < words);
1353 ixgbe_standby_eeprom(hw);
1356 /* Done with writing - release the EEPROM */
1357 ixgbe_release_eeprom(hw);
1364 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1365 * @hw: pointer to hardware structure
1366 * @offset: offset within the EEPROM to be written to
1367 * @data: 16 bit word to be written to the EEPROM
1369 * If ixgbe_eeprom_update_checksum is not called after this function, the
1370 * EEPROM will most likely contain an invalid checksum.
1372 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1376 DEBUGFUNC("ixgbe_write_eeprom_generic");
1378 hw->eeprom.ops.init_params(hw);
1380 if (offset >= hw->eeprom.word_size) {
1381 status = IXGBE_ERR_EEPROM;
1385 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1392 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1393 * @hw: pointer to hardware structure
1394 * @offset: offset within the EEPROM to be read
1395 * @data: read 16 bit words(s) from EEPROM
1396 * @words: number of word(s)
1398 * Reads 16 bit word(s) from EEPROM through bit-bang method
1400 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1401 u16 words, u16 *data)
1403 s32 status = IXGBE_SUCCESS;
1406 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1408 hw->eeprom.ops.init_params(hw);
1411 status = IXGBE_ERR_INVALID_ARGUMENT;
1415 if (offset + words > hw->eeprom.word_size) {
1416 status = IXGBE_ERR_EEPROM;
1421 * We cannot hold synchronization semaphores for too long
1422 * to avoid other entity starvation. However it is more efficient
1423 * to read in bursts than synchronizing access for each word.
1425 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1426 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1427 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1429 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1432 if (status != IXGBE_SUCCESS)
1441 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1442 * @hw: pointer to hardware structure
1443 * @offset: offset within the EEPROM to be read
1444 * @words: number of word(s)
1445 * @data: read 16 bit word(s) from EEPROM
1447 * Reads 16 bit word(s) from EEPROM through bit-bang method
1449 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1450 u16 words, u16 *data)
1454 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1457 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1459 /* Prepare the EEPROM for reading */
1460 status = ixgbe_acquire_eeprom(hw);
1462 if (status == IXGBE_SUCCESS) {
1463 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1464 ixgbe_release_eeprom(hw);
1465 status = IXGBE_ERR_EEPROM;
1469 if (status == IXGBE_SUCCESS) {
1470 for (i = 0; i < words; i++) {
1471 ixgbe_standby_eeprom(hw);
1473 * Some SPI eeproms use the 8th address bit embedded
1476 if ((hw->eeprom.address_bits == 8) &&
1477 ((offset + i) >= 128))
1478 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1480 /* Send the READ command (opcode + addr) */
1481 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1482 IXGBE_EEPROM_OPCODE_BITS);
1483 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1484 hw->eeprom.address_bits);
1486 /* Read the data. */
1487 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1488 data[i] = (word_in >> 8) | (word_in << 8);
1491 /* End this read operation */
1492 ixgbe_release_eeprom(hw);
1499 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1500 * @hw: pointer to hardware structure
1501 * @offset: offset within the EEPROM to be read
1502 * @data: read 16 bit value from EEPROM
1504 * Reads 16 bit value from EEPROM through bit-bang method
1506 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1511 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1513 hw->eeprom.ops.init_params(hw);
1515 if (offset >= hw->eeprom.word_size) {
1516 status = IXGBE_ERR_EEPROM;
1520 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1527 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1528 * @hw: pointer to hardware structure
1529 * @offset: offset of word in the EEPROM to read
1530 * @words: number of word(s)
1531 * @data: 16 bit word(s) from the EEPROM
1533 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1535 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1536 u16 words, u16 *data)
1539 s32 status = IXGBE_SUCCESS;
1542 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1544 hw->eeprom.ops.init_params(hw);
1547 status = IXGBE_ERR_INVALID_ARGUMENT;
1548 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1552 if (offset >= hw->eeprom.word_size) {
1553 status = IXGBE_ERR_EEPROM;
1554 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1558 for (i = 0; i < words; i++) {
1559 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1560 IXGBE_EEPROM_RW_REG_START;
1562 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1563 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1565 if (status == IXGBE_SUCCESS) {
1566 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1567 IXGBE_EEPROM_RW_REG_DATA);
1569 DEBUGOUT("Eeprom read timed out\n");
1578 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1579 * @hw: pointer to hardware structure
1580 * @offset: offset within the EEPROM to be used as a scratch pad
1582 * Discover EEPROM page size by writing marching data at given offset.
1583 * This function is called only when we are writing a new large buffer
1584 * at given offset so the data would be overwritten anyway.
1586 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1589 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1590 s32 status = IXGBE_SUCCESS;
1593 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1595 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1598 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1599 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1600 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1601 hw->eeprom.word_page_size = 0;
1602 if (status != IXGBE_SUCCESS)
1605 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1606 if (status != IXGBE_SUCCESS)
1610 * When writing in burst more than the actual page size
1611 * EEPROM address wraps around current page.
1613 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1615 DEBUGOUT1("Detected EEPROM page size = %d words.",
1616 hw->eeprom.word_page_size);
1622 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1623 * @hw: pointer to hardware structure
1624 * @offset: offset of word in the EEPROM to read
1625 * @data: word read from the EEPROM
1627 * Reads a 16 bit word from the EEPROM using the EERD register.
1629 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1631 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1635 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1636 * @hw: pointer to hardware structure
1637 * @offset: offset of word in the EEPROM to write
1638 * @words: number of word(s)
1639 * @data: word(s) write to the EEPROM
1641 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1643 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1644 u16 words, u16 *data)
1647 s32 status = IXGBE_SUCCESS;
1650 DEBUGFUNC("ixgbe_write_eewr_generic");
1652 hw->eeprom.ops.init_params(hw);
1655 status = IXGBE_ERR_INVALID_ARGUMENT;
1656 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1660 if (offset >= hw->eeprom.word_size) {
1661 status = IXGBE_ERR_EEPROM;
1662 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1666 for (i = 0; i < words; i++) {
1667 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1668 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1669 IXGBE_EEPROM_RW_REG_START;
1671 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1672 if (status != IXGBE_SUCCESS) {
1673 DEBUGOUT("Eeprom write EEWR timed out\n");
1677 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1679 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1680 if (status != IXGBE_SUCCESS) {
1681 DEBUGOUT("Eeprom write EEWR timed out\n");
1691 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1692 * @hw: pointer to hardware structure
1693 * @offset: offset of word in the EEPROM to write
1694 * @data: word write to the EEPROM
1696 * Write a 16 bit word to the EEPROM using the EEWR register.
1698 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1700 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1704 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1705 * @hw: pointer to hardware structure
1706 * @ee_reg: EEPROM flag for polling
1708 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1709 * read or write is done respectively.
1711 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1715 s32 status = IXGBE_ERR_EEPROM;
1717 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1719 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1720 if (ee_reg == IXGBE_NVM_POLL_READ)
1721 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1723 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1725 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1726 status = IXGBE_SUCCESS;
1732 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1733 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1734 "EEPROM read/write done polling timed out");
1740 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1741 * @hw: pointer to hardware structure
1743 * Prepares EEPROM for access using bit-bang method. This function should
1744 * be called before issuing a command to the EEPROM.
1746 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1748 s32 status = IXGBE_SUCCESS;
1752 DEBUGFUNC("ixgbe_acquire_eeprom");
1754 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1756 status = IXGBE_ERR_SWFW_SYNC;
1758 if (status == IXGBE_SUCCESS) {
1759 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1761 /* Request EEPROM Access */
1762 eec |= IXGBE_EEC_REQ;
1763 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1765 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1766 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1767 if (eec & IXGBE_EEC_GNT)
1772 /* Release if grant not acquired */
1773 if (!(eec & IXGBE_EEC_GNT)) {
1774 eec &= ~IXGBE_EEC_REQ;
1775 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1776 DEBUGOUT("Could not acquire EEPROM grant\n");
1778 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1779 status = IXGBE_ERR_EEPROM;
1782 /* Setup EEPROM for Read/Write */
1783 if (status == IXGBE_SUCCESS) {
1784 /* Clear CS and SK */
1785 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1786 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1787 IXGBE_WRITE_FLUSH(hw);
1795 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1796 * @hw: pointer to hardware structure
1798 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1800 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1802 s32 status = IXGBE_ERR_EEPROM;
1807 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1810 /* Get SMBI software semaphore between device drivers first */
1811 for (i = 0; i < timeout; i++) {
1813 * If the SMBI bit is 0 when we read it, then the bit will be
1814 * set and we have the semaphore
1816 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1817 if (!(swsm & IXGBE_SWSM_SMBI)) {
1818 status = IXGBE_SUCCESS;
1825 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1828 * this release is particularly important because our attempts
1829 * above to get the semaphore may have succeeded, and if there
1830 * was a timeout, we should unconditionally clear the semaphore
1831 * bits to free the driver to make progress
1833 ixgbe_release_eeprom_semaphore(hw);
1838 * If the SMBI bit is 0 when we read it, then the bit will be
1839 * set and we have the semaphore
1841 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1842 if (!(swsm & IXGBE_SWSM_SMBI))
1843 status = IXGBE_SUCCESS;
1846 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1847 if (status == IXGBE_SUCCESS) {
1848 for (i = 0; i < timeout; i++) {
1849 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1851 /* Set the SW EEPROM semaphore bit to request access */
1852 swsm |= IXGBE_SWSM_SWESMBI;
1853 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1856 * If we set the bit successfully then we got the
1859 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1860 if (swsm & IXGBE_SWSM_SWESMBI)
1867 * Release semaphores and return error if SW EEPROM semaphore
1868 * was not granted because we don't have access to the EEPROM
1871 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1872 "SWESMBI Software EEPROM semaphore not granted.\n");
1873 ixgbe_release_eeprom_semaphore(hw);
1874 status = IXGBE_ERR_EEPROM;
1877 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1878 "Software semaphore SMBI between device drivers "
1886 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1887 * @hw: pointer to hardware structure
1889 * This function clears hardware semaphore bits.
1891 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1895 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1897 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1899 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1900 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1901 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1902 IXGBE_WRITE_FLUSH(hw);
1906 * ixgbe_ready_eeprom - Polls for EEPROM ready
1907 * @hw: pointer to hardware structure
1909 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1911 s32 status = IXGBE_SUCCESS;
1915 DEBUGFUNC("ixgbe_ready_eeprom");
1918 * Read "Status Register" repeatedly until the LSB is cleared. The
1919 * EEPROM will signal that the command has been completed by clearing
1920 * bit 0 of the internal status register. If it's not cleared within
1921 * 5 milliseconds, then error out.
1923 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1924 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1925 IXGBE_EEPROM_OPCODE_BITS);
1926 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1927 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1931 ixgbe_standby_eeprom(hw);
1935 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1936 * devices (and only 0-5mSec on 5V devices)
1938 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1939 DEBUGOUT("SPI EEPROM Status error\n");
1940 status = IXGBE_ERR_EEPROM;
1947 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1948 * @hw: pointer to hardware structure
1950 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1954 DEBUGFUNC("ixgbe_standby_eeprom");
1956 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1958 /* Toggle CS to flush commands */
1959 eec |= IXGBE_EEC_CS;
1960 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1961 IXGBE_WRITE_FLUSH(hw);
1963 eec &= ~IXGBE_EEC_CS;
1964 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1965 IXGBE_WRITE_FLUSH(hw);
1970 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1971 * @hw: pointer to hardware structure
1972 * @data: data to send to the EEPROM
1973 * @count: number of bits to shift out
1975 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1982 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1984 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1987 * Mask is used to shift "count" bits of "data" out to the EEPROM
1988 * one bit at a time. Determine the starting bit based on count
1990 mask = 0x01 << (count - 1);
1992 for (i = 0; i < count; i++) {
1994 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1995 * "1", and then raising and then lowering the clock (the SK
1996 * bit controls the clock input to the EEPROM). A "0" is
1997 * shifted out to the EEPROM by setting "DI" to "0" and then
1998 * raising and then lowering the clock.
2001 eec |= IXGBE_EEC_DI;
2003 eec &= ~IXGBE_EEC_DI;
2005 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2006 IXGBE_WRITE_FLUSH(hw);
2010 ixgbe_raise_eeprom_clk(hw, &eec);
2011 ixgbe_lower_eeprom_clk(hw, &eec);
2014 * Shift mask to signify next bit of data to shift in to the
2020 /* We leave the "DI" bit set to "0" when we leave this routine. */
2021 eec &= ~IXGBE_EEC_DI;
2022 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2023 IXGBE_WRITE_FLUSH(hw);
2027 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2028 * @hw: pointer to hardware structure
2030 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2036 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2039 * In order to read a register from the EEPROM, we need to shift
2040 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2041 * the clock input to the EEPROM (setting the SK bit), and then reading
2042 * the value of the "DO" bit. During this "shifting in" process the
2043 * "DI" bit should always be clear.
2045 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2047 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2049 for (i = 0; i < count; i++) {
2051 ixgbe_raise_eeprom_clk(hw, &eec);
2053 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2055 eec &= ~(IXGBE_EEC_DI);
2056 if (eec & IXGBE_EEC_DO)
2059 ixgbe_lower_eeprom_clk(hw, &eec);
2066 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2067 * @hw: pointer to hardware structure
2068 * @eec: EEC register's current value
2070 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2072 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2075 * Raise the clock input to the EEPROM
2076 * (setting the SK bit), then delay
2078 *eec = *eec | IXGBE_EEC_SK;
2079 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2080 IXGBE_WRITE_FLUSH(hw);
2085 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2086 * @hw: pointer to hardware structure
2087 * @eecd: EECD's current value
2089 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2091 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2094 * Lower the clock input to the EEPROM (clearing the SK bit), then
2097 *eec = *eec & ~IXGBE_EEC_SK;
2098 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2099 IXGBE_WRITE_FLUSH(hw);
2104 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2105 * @hw: pointer to hardware structure
2107 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2111 DEBUGFUNC("ixgbe_release_eeprom");
2113 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2115 eec |= IXGBE_EEC_CS; /* Pull CS high */
2116 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2118 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2119 IXGBE_WRITE_FLUSH(hw);
2123 /* Stop requesting EEPROM access */
2124 eec &= ~IXGBE_EEC_REQ;
2125 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2127 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2129 /* Delay before attempt to obtain semaphore again to allow FW access */
2130 msec_delay(hw->eeprom.semaphore_delay);
2134 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2135 * @hw: pointer to hardware structure
2137 * Returns a negative error code on error, or the 16-bit checksum
2139 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2148 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2150 /* Include 0x0-0x3F in the checksum */
2151 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2152 if (hw->eeprom.ops.read(hw, i, &word)) {
2153 DEBUGOUT("EEPROM read failed\n");
2154 return IXGBE_ERR_EEPROM;
2159 /* Include all data from pointers except for the fw pointer */
2160 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2161 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2162 DEBUGOUT("EEPROM read failed\n");
2163 return IXGBE_ERR_EEPROM;
2166 /* If the pointer seems invalid */
2167 if (pointer == 0xFFFF || pointer == 0)
2170 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2171 DEBUGOUT("EEPROM read failed\n");
2172 return IXGBE_ERR_EEPROM;
2175 if (length == 0xFFFF || length == 0)
2178 for (j = pointer + 1; j <= pointer + length; j++) {
2179 if (hw->eeprom.ops.read(hw, j, &word)) {
2180 DEBUGOUT("EEPROM read failed\n");
2181 return IXGBE_ERR_EEPROM;
2187 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2189 return (s32)checksum;
2193 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2194 * @hw: pointer to hardware structure
2195 * @checksum_val: calculated checksum
2197 * Performs checksum calculation and validates the EEPROM checksum. If the
2198 * caller does not need checksum_val, the value can be NULL.
2200 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2205 u16 read_checksum = 0;
2207 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2209 /* Read the first word from the EEPROM. If this times out or fails, do
2210 * not continue or we could be in for a very long wait while every
2213 status = hw->eeprom.ops.read(hw, 0, &checksum);
2215 DEBUGOUT("EEPROM read failed\n");
2219 status = hw->eeprom.ops.calc_checksum(hw);
2223 checksum = (u16)(status & 0xffff);
2225 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2227 DEBUGOUT("EEPROM read failed\n");
2231 /* Verify read checksum from EEPROM is the same as
2232 * calculated checksum
2234 if (read_checksum != checksum)
2235 status = IXGBE_ERR_EEPROM_CHECKSUM;
2237 /* If the user cares, return the calculated checksum */
2239 *checksum_val = checksum;
2245 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2246 * @hw: pointer to hardware structure
2248 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2253 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2255 /* Read the first word from the EEPROM. If this times out or fails, do
2256 * not continue or we could be in for a very long wait while every
2259 status = hw->eeprom.ops.read(hw, 0, &checksum);
2261 DEBUGOUT("EEPROM read failed\n");
2265 status = hw->eeprom.ops.calc_checksum(hw);
2269 checksum = (u16)(status & 0xffff);
2271 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2277 * ixgbe_validate_mac_addr - Validate MAC address
2278 * @mac_addr: pointer to MAC address.
2280 * Tests a MAC address to ensure it is a valid Individual Address.
2282 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2284 s32 status = IXGBE_SUCCESS;
2286 DEBUGFUNC("ixgbe_validate_mac_addr");
2288 /* Make sure it is not a multicast address */
2289 if (IXGBE_IS_MULTICAST(mac_addr)) {
2290 status = IXGBE_ERR_INVALID_MAC_ADDR;
2291 /* Not a broadcast address */
2292 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2293 status = IXGBE_ERR_INVALID_MAC_ADDR;
2294 /* Reject the zero address */
2295 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2296 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2297 status = IXGBE_ERR_INVALID_MAC_ADDR;
2303 * ixgbe_set_rar_generic - Set Rx address register
2304 * @hw: pointer to hardware structure
2305 * @index: Receive address register to write
2306 * @addr: Address to put into receive address register
2307 * @vmdq: VMDq "set" or "pool" index
2308 * @enable_addr: set flag that address is active
2310 * Puts an ethernet address into a receive address register.
2312 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2315 u32 rar_low, rar_high;
2316 u32 rar_entries = hw->mac.num_rar_entries;
2318 DEBUGFUNC("ixgbe_set_rar_generic");
2320 /* Make sure we are using a valid rar index range */
2321 if (index >= rar_entries) {
2322 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2323 "RAR index %d is out of range.\n", index);
2324 return IXGBE_ERR_INVALID_ARGUMENT;
2327 /* setup VMDq pool selection before this RAR gets enabled */
2328 hw->mac.ops.set_vmdq(hw, index, vmdq);
2331 * HW expects these in little endian so we reverse the byte
2332 * order from network order (big endian) to little endian
2334 rar_low = ((u32)addr[0] |
2335 ((u32)addr[1] << 8) |
2336 ((u32)addr[2] << 16) |
2337 ((u32)addr[3] << 24));
2339 * Some parts put the VMDq setting in the extra RAH bits,
2340 * so save everything except the lower 16 bits that hold part
2341 * of the address and the address valid bit.
2343 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2344 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2345 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2347 if (enable_addr != 0)
2348 rar_high |= IXGBE_RAH_AV;
2350 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2351 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2353 return IXGBE_SUCCESS;
2357 * ixgbe_clear_rar_generic - Remove Rx address register
2358 * @hw: pointer to hardware structure
2359 * @index: Receive address register to write
2361 * Clears an ethernet address from a receive address register.
2363 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2366 u32 rar_entries = hw->mac.num_rar_entries;
2368 DEBUGFUNC("ixgbe_clear_rar_generic");
2370 /* Make sure we are using a valid rar index range */
2371 if (index >= rar_entries) {
2372 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2373 "RAR index %d is out of range.\n", index);
2374 return IXGBE_ERR_INVALID_ARGUMENT;
2378 * Some parts put the VMDq setting in the extra RAH bits,
2379 * so save everything except the lower 16 bits that hold part
2380 * of the address and the address valid bit.
2382 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2383 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2385 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2386 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2388 /* clear VMDq pool/queue selection for this RAR */
2389 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2391 return IXGBE_SUCCESS;
2395 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2396 * @hw: pointer to hardware structure
2398 * Places the MAC address in receive address register 0 and clears the rest
2399 * of the receive address registers. Clears the multicast table. Assumes
2400 * the receiver is in reset when the routine is called.
2402 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2405 u32 rar_entries = hw->mac.num_rar_entries;
2407 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2410 * If the current mac address is valid, assume it is a software override
2411 * to the permanent address.
2412 * Otherwise, use the permanent address from the eeprom.
2414 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2415 IXGBE_ERR_INVALID_MAC_ADDR) {
2416 /* Get the MAC address from the RAR0 for later reference */
2417 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2419 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2420 hw->mac.addr[0], hw->mac.addr[1],
2422 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2423 hw->mac.addr[4], hw->mac.addr[5]);
2425 /* Setup the receive address. */
2426 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2427 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2428 hw->mac.addr[0], hw->mac.addr[1],
2430 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2431 hw->mac.addr[4], hw->mac.addr[5]);
2433 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2436 /* clear VMDq pool/queue selection for RAR 0 */
2437 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2439 hw->addr_ctrl.overflow_promisc = 0;
2441 hw->addr_ctrl.rar_used_count = 1;
2443 /* Zero out the other receive addresses. */
2444 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2445 for (i = 1; i < rar_entries; i++) {
2446 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2447 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2451 hw->addr_ctrl.mta_in_use = 0;
2452 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2454 DEBUGOUT(" Clearing MTA\n");
2455 for (i = 0; i < hw->mac.mcft_size; i++)
2456 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2458 ixgbe_init_uta_tables(hw);
2460 return IXGBE_SUCCESS;
2464 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2465 * @hw: pointer to hardware structure
2466 * @addr: new address
2468 * Adds it to unused receive address register or goes into promiscuous mode.
2470 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2472 u32 rar_entries = hw->mac.num_rar_entries;
2475 DEBUGFUNC("ixgbe_add_uc_addr");
2477 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2478 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2481 * Place this address in the RAR if there is room,
2482 * else put the controller into promiscuous mode
2484 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2485 rar = hw->addr_ctrl.rar_used_count;
2486 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2487 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2488 hw->addr_ctrl.rar_used_count++;
2490 hw->addr_ctrl.overflow_promisc++;
2493 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2497 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2498 * @hw: pointer to hardware structure
2499 * @addr_list: the list of new addresses
2500 * @addr_count: number of addresses
2501 * @next: iterator function to walk the address list
2503 * The given list replaces any existing list. Clears the secondary addrs from
2504 * receive address registers. Uses unused receive address registers for the
2505 * first secondary addresses, and falls back to promiscuous mode as needed.
2507 * Drivers using secondary unicast addresses must set user_set_promisc when
2508 * manually putting the device into promiscuous mode.
2510 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2511 u32 addr_count, ixgbe_mc_addr_itr next)
2515 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2520 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2523 * Clear accounting of old secondary address list,
2524 * don't count RAR[0]
2526 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2527 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2528 hw->addr_ctrl.overflow_promisc = 0;
2530 /* Zero out the other receive addresses */
2531 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2532 for (i = 0; i < uc_addr_in_use; i++) {
2533 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2534 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2537 /* Add the new addresses */
2538 for (i = 0; i < addr_count; i++) {
2539 DEBUGOUT(" Adding the secondary addresses:\n");
2540 addr = next(hw, &addr_list, &vmdq);
2541 ixgbe_add_uc_addr(hw, addr, vmdq);
2544 if (hw->addr_ctrl.overflow_promisc) {
2545 /* enable promisc if not already in overflow or set by user */
2546 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2547 DEBUGOUT(" Entering address overflow promisc mode\n");
2548 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2549 fctrl |= IXGBE_FCTRL_UPE;
2550 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2553 /* only disable if set by overflow, not by user */
2554 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2555 DEBUGOUT(" Leaving address overflow promisc mode\n");
2556 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2557 fctrl &= ~IXGBE_FCTRL_UPE;
2558 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2562 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2563 return IXGBE_SUCCESS;
2567 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2568 * @hw: pointer to hardware structure
2569 * @mc_addr: the multicast address
2571 * Extracts the 12 bits, from a multicast address, to determine which
2572 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2573 * incoming rx multicast addresses, to determine the bit-vector to check in
2574 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2575 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2576 * to mc_filter_type.
2578 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2582 DEBUGFUNC("ixgbe_mta_vector");
2584 switch (hw->mac.mc_filter_type) {
2585 case 0: /* use bits [47:36] of the address */
2586 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2588 case 1: /* use bits [46:35] of the address */
2589 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2591 case 2: /* use bits [45:34] of the address */
2592 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2594 case 3: /* use bits [43:32] of the address */
2595 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2597 default: /* Invalid mc_filter_type */
2598 DEBUGOUT("MC filter type param set incorrectly\n");
2603 /* vector can only be 12-bits or boundary will be exceeded */
2609 * ixgbe_set_mta - Set bit-vector in multicast table
2610 * @hw: pointer to hardware structure
2611 * @hash_value: Multicast address hash value
2613 * Sets the bit-vector in the multicast table.
2615 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2621 DEBUGFUNC("ixgbe_set_mta");
2623 hw->addr_ctrl.mta_in_use++;
2625 vector = ixgbe_mta_vector(hw, mc_addr);
2626 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2629 * The MTA is a register array of 128 32-bit registers. It is treated
2630 * like an array of 4096 bits. We want to set bit
2631 * BitArray[vector_value]. So we figure out what register the bit is
2632 * in, read it, OR in the new bit, then write back the new value. The
2633 * register is determined by the upper 7 bits of the vector value and
2634 * the bit within that register are determined by the lower 5 bits of
2637 vector_reg = (vector >> 5) & 0x7F;
2638 vector_bit = vector & 0x1F;
2639 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2643 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2644 * @hw: pointer to hardware structure
2645 * @mc_addr_list: the list of new multicast addresses
2646 * @mc_addr_count: number of addresses
2647 * @next: iterator function to walk the multicast address list
2648 * @clear: flag, when set clears the table beforehand
2650 * When the clear flag is set, the given list replaces any existing list.
2651 * Hashes the given addresses into the multicast table.
2653 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2654 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2660 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2663 * Set the new number of MC addresses that we are being requested to
2666 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2667 hw->addr_ctrl.mta_in_use = 0;
2669 /* Clear mta_shadow */
2671 DEBUGOUT(" Clearing MTA\n");
2672 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2675 /* Update mta_shadow */
2676 for (i = 0; i < mc_addr_count; i++) {
2677 DEBUGOUT(" Adding the multicast addresses:\n");
2678 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2682 for (i = 0; i < hw->mac.mcft_size; i++)
2683 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2684 hw->mac.mta_shadow[i]);
2686 if (hw->addr_ctrl.mta_in_use > 0)
2687 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2688 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2690 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2691 return IXGBE_SUCCESS;
2695 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2696 * @hw: pointer to hardware structure
2698 * Enables multicast address in RAR and the use of the multicast hash table.
2700 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2702 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2704 DEBUGFUNC("ixgbe_enable_mc_generic");
2706 if (a->mta_in_use > 0)
2707 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2708 hw->mac.mc_filter_type);
2710 return IXGBE_SUCCESS;
2714 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2715 * @hw: pointer to hardware structure
2717 * Disables multicast address in RAR and the use of the multicast hash table.
2719 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2721 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2723 DEBUGFUNC("ixgbe_disable_mc_generic");
2725 if (a->mta_in_use > 0)
2726 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2728 return IXGBE_SUCCESS;
2732 * ixgbe_fc_enable_generic - Enable flow control
2733 * @hw: pointer to hardware structure
2735 * Enable flow control according to the current settings.
2737 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2739 s32 ret_val = IXGBE_SUCCESS;
2740 u32 mflcn_reg, fccfg_reg;
2745 DEBUGFUNC("ixgbe_fc_enable_generic");
2747 /* Validate the water mark configuration */
2748 if (!hw->fc.pause_time) {
2749 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2753 /* Low water mark of zero causes XOFF floods */
2754 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2755 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2756 hw->fc.high_water[i]) {
2757 if (!hw->fc.low_water[i] ||
2758 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2759 DEBUGOUT("Invalid water mark configuration\n");
2760 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2766 /* Negotiate the fc mode to use */
2767 hw->mac.ops.fc_autoneg(hw);
2769 /* Disable any previous flow control settings */
2770 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2771 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2773 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2774 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2777 * The possible values of fc.current_mode are:
2778 * 0: Flow control is completely disabled
2779 * 1: Rx flow control is enabled (we can receive pause frames,
2780 * but not send pause frames).
2781 * 2: Tx flow control is enabled (we can send pause frames but
2782 * we do not support receiving pause frames).
2783 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2786 switch (hw->fc.current_mode) {
2789 * Flow control is disabled by software override or autoneg.
2790 * The code below will actually disable it in the HW.
2793 case ixgbe_fc_rx_pause:
2795 * Rx Flow control is enabled and Tx Flow control is
2796 * disabled by software override. Since there really
2797 * isn't a way to advertise that we are capable of RX
2798 * Pause ONLY, we will advertise that we support both
2799 * symmetric and asymmetric Rx PAUSE. Later, we will
2800 * disable the adapter's ability to send PAUSE frames.
2802 mflcn_reg |= IXGBE_MFLCN_RFCE;
2804 case ixgbe_fc_tx_pause:
2806 * Tx Flow control is enabled, and Rx Flow control is
2807 * disabled by software override.
2809 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2812 /* Flow control (both Rx and Tx) is enabled by SW override. */
2813 mflcn_reg |= IXGBE_MFLCN_RFCE;
2814 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2817 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2818 "Flow control param set incorrectly\n");
2819 ret_val = IXGBE_ERR_CONFIG;
2824 /* Set 802.3x based flow control settings. */
2825 mflcn_reg |= IXGBE_MFLCN_DPF;
2826 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2827 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2830 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2831 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2832 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2833 hw->fc.high_water[i]) {
2834 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2835 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2836 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2838 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2840 * In order to prevent Tx hangs when the internal Tx
2841 * switch is enabled we must set the high water mark
2842 * to the Rx packet buffer size - 24KB. This allows
2843 * the Tx switch to function even under heavy Rx
2846 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2849 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2852 /* Configure pause time (2 TCs per register) */
2853 reg = hw->fc.pause_time * 0x00010001;
2854 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2855 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2857 /* Configure flow control refresh threshold value */
2858 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2865 * ixgbe_negotiate_fc - Negotiate flow control
2866 * @hw: pointer to hardware structure
2867 * @adv_reg: flow control advertised settings
2868 * @lp_reg: link partner's flow control settings
2869 * @adv_sym: symmetric pause bit in advertisement
2870 * @adv_asm: asymmetric pause bit in advertisement
2871 * @lp_sym: symmetric pause bit in link partner advertisement
2872 * @lp_asm: asymmetric pause bit in link partner advertisement
2874 * Find the intersection between advertised settings and link partner's
2875 * advertised settings
2877 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2878 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2880 if ((!(adv_reg)) || (!(lp_reg))) {
2881 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2882 "Local or link partner's advertised flow control "
2883 "settings are NULL. Local: %x, link partner: %x\n",
2885 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2888 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2890 * Now we need to check if the user selected Rx ONLY
2891 * of pause frames. In this case, we had to advertise
2892 * FULL flow control because we could not advertise RX
2893 * ONLY. Hence, we must now check to see if we need to
2894 * turn OFF the TRANSMISSION of PAUSE frames.
2896 if (hw->fc.requested_mode == ixgbe_fc_full) {
2897 hw->fc.current_mode = ixgbe_fc_full;
2898 DEBUGOUT("Flow Control = FULL.\n");
2900 hw->fc.current_mode = ixgbe_fc_rx_pause;
2901 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2903 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2904 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2905 hw->fc.current_mode = ixgbe_fc_tx_pause;
2906 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2907 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2908 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2909 hw->fc.current_mode = ixgbe_fc_rx_pause;
2910 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2912 hw->fc.current_mode = ixgbe_fc_none;
2913 DEBUGOUT("Flow Control = NONE.\n");
2915 return IXGBE_SUCCESS;
2919 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2920 * @hw: pointer to hardware structure
2922 * Enable flow control according on 1 gig fiber.
2924 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2926 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2927 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2930 * On multispeed fiber at 1g, bail out if
2931 * - link is up but AN did not complete, or if
2932 * - link is up and AN completed but timed out
2935 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2936 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2937 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2938 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
2942 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2943 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2945 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2946 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2947 IXGBE_PCS1GANA_ASM_PAUSE,
2948 IXGBE_PCS1GANA_SYM_PAUSE,
2949 IXGBE_PCS1GANA_ASM_PAUSE);
2956 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2957 * @hw: pointer to hardware structure
2959 * Enable flow control according to IEEE clause 37.
2961 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2963 u32 links2, anlp1_reg, autoc_reg, links;
2964 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2967 * On backplane, bail out if
2968 * - backplane autoneg was not completed, or if
2969 * - we are 82599 and link partner is not AN enabled
2971 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2972 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2973 DEBUGOUT("Auto-Negotiation did not complete\n");
2977 if (hw->mac.type == ixgbe_mac_82599EB) {
2978 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2979 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2980 DEBUGOUT("Link partner is not AN enabled\n");
2985 * Read the 10g AN autoc and LP ability registers and resolve
2986 * local flow control settings accordingly
2988 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2989 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2991 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2992 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2993 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
3000 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3001 * @hw: pointer to hardware structure
3003 * Enable flow control according to IEEE clause 37.
3005 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3007 u16 technology_ability_reg = 0;
3008 u16 lp_technology_ability_reg = 0;
3010 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3011 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3012 &technology_ability_reg);
3013 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3014 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3015 &lp_technology_ability_reg);
3017 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3018 (u32)lp_technology_ability_reg,
3019 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
3020 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
3024 * ixgbe_fc_autoneg - Configure flow control
3025 * @hw: pointer to hardware structure
3027 * Compares our advertised flow control capabilities to those advertised by
3028 * our link partner, and determines the proper flow control mode to use.
3030 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3032 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3033 ixgbe_link_speed speed;
3036 DEBUGFUNC("ixgbe_fc_autoneg");
3039 * AN should have completed when the cable was plugged in.
3040 * Look for reasons to bail out. Bail out if:
3041 * - FC autoneg is disabled, or if
3044 if (hw->fc.disable_fc_autoneg) {
3045 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3046 "Flow control autoneg is disabled");
3050 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3052 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3056 switch (hw->phy.media_type) {
3057 /* Autoneg flow control on fiber adapters */
3058 case ixgbe_media_type_fiber_qsfp:
3059 case ixgbe_media_type_fiber:
3060 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3061 ret_val = ixgbe_fc_autoneg_fiber(hw);
3064 /* Autoneg flow control on backplane adapters */
3065 case ixgbe_media_type_backplane:
3066 ret_val = ixgbe_fc_autoneg_backplane(hw);
3069 /* Autoneg flow control on copper adapters */
3070 case ixgbe_media_type_copper:
3071 if (ixgbe_device_supports_autoneg_fc(hw))
3072 ret_val = ixgbe_fc_autoneg_copper(hw);
3080 if (ret_val == IXGBE_SUCCESS) {
3081 hw->fc.fc_was_autonegged = true;
3083 hw->fc.fc_was_autonegged = false;
3084 hw->fc.current_mode = hw->fc.requested_mode;
3089 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3090 * @hw: pointer to hardware structure
3092 * System-wide timeout range is encoded in PCIe Device Control2 register.
3094 * Add 10% to specified maximum and return the number of times to poll for
3095 * completion timeout, in units of 100 microsec. Never return less than
3096 * 800 = 80 millisec.
3098 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3103 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3104 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3107 case IXGBE_PCIDEVCTRL2_65_130ms:
3108 pollcnt = 1300; /* 130 millisec */
3110 case IXGBE_PCIDEVCTRL2_260_520ms:
3111 pollcnt = 5200; /* 520 millisec */
3113 case IXGBE_PCIDEVCTRL2_1_2s:
3114 pollcnt = 20000; /* 2 sec */
3116 case IXGBE_PCIDEVCTRL2_4_8s:
3117 pollcnt = 80000; /* 8 sec */
3119 case IXGBE_PCIDEVCTRL2_17_34s:
3120 pollcnt = 34000; /* 34 sec */
3122 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3123 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3124 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3125 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3127 pollcnt = 800; /* 80 millisec minimum */
3131 /* add 10% to spec maximum */
3132 return (pollcnt * 11) / 10;
3136 * ixgbe_disable_pcie_master - Disable PCI-express master access
3137 * @hw: pointer to hardware structure
3139 * Disables PCI-Express master access and verifies there are no pending
3140 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3141 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3142 * is returned signifying master requests disabled.
3144 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3146 s32 status = IXGBE_SUCCESS;
3150 DEBUGFUNC("ixgbe_disable_pcie_master");
3152 /* Always set this bit to ensure any future transactions are blocked */
3153 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3155 /* Exit if master requests are blocked */
3156 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3157 IXGBE_REMOVED(hw->hw_addr))
3160 /* Poll for master request bit to clear */
3161 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3163 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3168 * Two consecutive resets are required via CTRL.RST per datasheet
3169 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3170 * of this need. The first reset prevents new master requests from
3171 * being issued by our device. We then must wait 1usec or more for any
3172 * remaining completions from the PCIe bus to trickle in, and then reset
3173 * again to clear out any effects they may have had on our device.
3175 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3176 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3178 if (hw->mac.type >= ixgbe_mac_X550)
3182 * Before proceeding, make sure that the PCIe block does not have
3183 * transactions pending.
3185 poll = ixgbe_pcie_timeout_poll(hw);
3186 for (i = 0; i < poll; i++) {
3188 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3189 if (IXGBE_REMOVED(hw->hw_addr))
3191 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3195 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3196 "PCIe transaction pending bit also did not clear.\n");
3197 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3204 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3205 * @hw: pointer to hardware structure
3206 * @mask: Mask to specify which semaphore to acquire
3208 * Acquires the SWFW semaphore through the GSSR register for the specified
3209 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3211 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3215 u32 fwmask = mask << 5;
3219 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3221 for (i = 0; i < timeout; i++) {
3223 * SW NVM semaphore bit is used for access to all
3224 * SW_FW_SYNC bits (not just NVM)
3226 if (ixgbe_get_eeprom_semaphore(hw))
3227 return IXGBE_ERR_SWFW_SYNC;
3229 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3230 if (!(gssr & (fwmask | swmask))) {
3232 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3233 ixgbe_release_eeprom_semaphore(hw);
3234 return IXGBE_SUCCESS;
3236 /* Resource is currently in use by FW or SW */
3237 ixgbe_release_eeprom_semaphore(hw);
3242 /* If time expired clear the bits holding the lock and retry */
3243 if (gssr & (fwmask | swmask))
3244 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3247 return IXGBE_ERR_SWFW_SYNC;
3251 * ixgbe_release_swfw_sync - Release SWFW semaphore
3252 * @hw: pointer to hardware structure
3253 * @mask: Mask to specify which semaphore to release
3255 * Releases the SWFW semaphore through the GSSR register for the specified
3256 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3258 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3263 DEBUGFUNC("ixgbe_release_swfw_sync");
3265 ixgbe_get_eeprom_semaphore(hw);
3267 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3269 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3271 ixgbe_release_eeprom_semaphore(hw);
3275 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3276 * @hw: pointer to hardware structure
3278 * Stops the receive data path and waits for the HW to internally empty
3279 * the Rx security block
3281 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3283 #define IXGBE_MAX_SECRX_POLL 40
3288 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3291 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3292 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3293 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3294 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3295 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3296 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3299 /* Use interrupt-safe sleep just in case */
3303 /* For informational purposes only */
3304 if (i >= IXGBE_MAX_SECRX_POLL)
3305 DEBUGOUT("Rx unit being enabled before security "
3306 "path fully disabled. Continuing with init.\n");
3308 return IXGBE_SUCCESS;
3312 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3313 * @hw: pointer to hardware structure
3314 * @reg_val: Value we read from AUTOC
3316 * The default case requires no protection so just to the register read.
3318 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3321 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3322 return IXGBE_SUCCESS;
3326 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3327 * @hw: pointer to hardware structure
3328 * @reg_val: value to write to AUTOC
3329 * @locked: bool to indicate whether the SW/FW lock was already taken by
3332 * The default case requires no protection so just to the register write.
3334 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3336 UNREFERENCED_1PARAMETER(locked);
3338 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3339 return IXGBE_SUCCESS;
3343 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3344 * @hw: pointer to hardware structure
3346 * Enables the receive data path.
3348 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3352 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3354 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3355 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3356 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3357 IXGBE_WRITE_FLUSH(hw);
3359 return IXGBE_SUCCESS;
3363 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3364 * @hw: pointer to hardware structure
3365 * @regval: register value to write to RXCTRL
3367 * Enables the Rx DMA unit
3369 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3371 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3373 if (regval & IXGBE_RXCTRL_RXEN)
3374 ixgbe_enable_rx(hw);
3376 ixgbe_disable_rx(hw);
3378 return IXGBE_SUCCESS;
3382 * ixgbe_blink_led_start_generic - Blink LED based on index.
3383 * @hw: pointer to hardware structure
3384 * @index: led number to blink
3386 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3388 ixgbe_link_speed speed = 0;
3391 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3392 s32 ret_val = IXGBE_SUCCESS;
3393 bool locked = false;
3395 DEBUGFUNC("ixgbe_blink_led_start_generic");
3398 return IXGBE_ERR_PARAM;
3401 * Link must be up to auto-blink the LEDs;
3402 * Force it if link is down.
3404 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3407 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3408 if (ret_val != IXGBE_SUCCESS)
3411 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3412 autoc_reg |= IXGBE_AUTOC_FLU;
3414 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3415 if (ret_val != IXGBE_SUCCESS)
3418 IXGBE_WRITE_FLUSH(hw);
3422 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3423 led_reg |= IXGBE_LED_BLINK(index);
3424 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3425 IXGBE_WRITE_FLUSH(hw);
3432 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3433 * @hw: pointer to hardware structure
3434 * @index: led number to stop blinking
3436 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3439 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3440 s32 ret_val = IXGBE_SUCCESS;
3441 bool locked = false;
3443 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3446 return IXGBE_ERR_PARAM;
3449 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3450 if (ret_val != IXGBE_SUCCESS)
3453 autoc_reg &= ~IXGBE_AUTOC_FLU;
3454 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3456 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3457 if (ret_val != IXGBE_SUCCESS)
3460 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3461 led_reg &= ~IXGBE_LED_BLINK(index);
3462 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3463 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3464 IXGBE_WRITE_FLUSH(hw);
3471 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3472 * @hw: pointer to hardware structure
3473 * @san_mac_offset: SAN MAC address offset
3475 * This function will read the EEPROM location for the SAN MAC address
3476 * pointer, and returns the value at that location. This is used in both
3477 * get and set mac_addr routines.
3479 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3480 u16 *san_mac_offset)
3484 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3487 * First read the EEPROM pointer to see if the MAC addresses are
3490 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3493 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3494 "eeprom at offset %d failed",
3495 IXGBE_SAN_MAC_ADDR_PTR);
3502 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3503 * @hw: pointer to hardware structure
3504 * @san_mac_addr: SAN MAC address
3506 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3507 * per-port, so set_lan_id() must be called before reading the addresses.
3508 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3509 * upon for non-SFP connections, so we must call it here.
3511 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3513 u16 san_mac_data, san_mac_offset;
3517 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3520 * First read the EEPROM pointer to see if the MAC addresses are
3521 * available. If they're not, no point in calling set_lan_id() here.
3523 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3524 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3525 goto san_mac_addr_out;
3527 /* make sure we know which port we need to program */
3528 hw->mac.ops.set_lan_id(hw);
3529 /* apply the port offset to the address offset */
3530 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3531 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3532 for (i = 0; i < 3; i++) {
3533 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3536 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3537 "eeprom read at offset %d failed",
3539 goto san_mac_addr_out;
3541 san_mac_addr[i * 2] = (u8)(san_mac_data);
3542 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3545 return IXGBE_SUCCESS;
3549 * No addresses available in this EEPROM. It's not an
3550 * error though, so just wipe the local address and return.
3552 for (i = 0; i < 6; i++)
3553 san_mac_addr[i] = 0xFF;
3554 return IXGBE_SUCCESS;
3558 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3559 * @hw: pointer to hardware structure
3560 * @san_mac_addr: SAN MAC address
3562 * Write a SAN MAC address to the EEPROM.
3564 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3567 u16 san_mac_data, san_mac_offset;
3570 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3572 /* Look for SAN mac address pointer. If not defined, return */
3573 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3574 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3575 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3577 /* Make sure we know which port we need to write */
3578 hw->mac.ops.set_lan_id(hw);
3579 /* Apply the port offset to the address offset */
3580 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3581 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3583 for (i = 0; i < 3; i++) {
3584 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3585 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3586 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3590 return IXGBE_SUCCESS;
3594 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3595 * @hw: pointer to hardware structure
3597 * Read PCIe configuration space, and get the MSI-X vector count from
3598 * the capabilities table.
3600 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3606 switch (hw->mac.type) {
3607 case ixgbe_mac_82598EB:
3608 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3609 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3611 case ixgbe_mac_82599EB:
3612 case ixgbe_mac_X540:
3613 case ixgbe_mac_X550:
3614 case ixgbe_mac_X550EM_x:
3615 case ixgbe_mac_X550EM_a:
3616 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3617 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3623 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3624 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3625 if (IXGBE_REMOVED(hw->hw_addr))
3627 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3629 /* MSI-X count is zero-based in HW */
3632 if (msix_count > max_msix_count)
3633 msix_count = max_msix_count;
3639 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3640 * @hw: pointer to hardware structure
3641 * @addr: Address to put into receive address register
3642 * @vmdq: VMDq pool to assign
3644 * Puts an ethernet address into a receive address register, or
3645 * finds the rar that it is aleady in; adds to the pool list
3647 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3649 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3650 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3652 u32 rar_low, rar_high;
3653 u32 addr_low, addr_high;
3655 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3657 /* swap bytes for HW little endian */
3658 addr_low = addr[0] | (addr[1] << 8)
3661 addr_high = addr[4] | (addr[5] << 8);
3664 * Either find the mac_id in rar or find the first empty space.
3665 * rar_highwater points to just after the highest currently used
3666 * rar in order to shorten the search. It grows when we add a new
3669 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3670 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3672 if (((IXGBE_RAH_AV & rar_high) == 0)
3673 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3674 first_empty_rar = rar;
3675 } else if ((rar_high & 0xFFFF) == addr_high) {
3676 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3677 if (rar_low == addr_low)
3678 break; /* found it already in the rars */
3682 if (rar < hw->mac.rar_highwater) {
3683 /* already there so just add to the pool bits */
3684 ixgbe_set_vmdq(hw, rar, vmdq);
3685 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3686 /* stick it into first empty RAR slot we found */
3687 rar = first_empty_rar;
3688 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3689 } else if (rar == hw->mac.rar_highwater) {
3690 /* add it to the top of the list and inc the highwater mark */
3691 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3692 hw->mac.rar_highwater++;
3693 } else if (rar >= hw->mac.num_rar_entries) {
3694 return IXGBE_ERR_INVALID_MAC_ADDR;
3698 * If we found rar[0], make sure the default pool bit (we use pool 0)
3699 * remains cleared to be sure default pool packets will get delivered
3702 ixgbe_clear_vmdq(hw, rar, 0);
3708 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3709 * @hw: pointer to hardware struct
3710 * @rar: receive address register index to disassociate
3711 * @vmdq: VMDq pool index to remove from the rar
3713 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3715 u32 mpsar_lo, mpsar_hi;
3716 u32 rar_entries = hw->mac.num_rar_entries;
3718 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3720 /* Make sure we are using a valid rar index range */
3721 if (rar >= rar_entries) {
3722 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3723 "RAR index %d is out of range.\n", rar);
3724 return IXGBE_ERR_INVALID_ARGUMENT;
3727 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3728 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3730 if (IXGBE_REMOVED(hw->hw_addr))
3733 if (!mpsar_lo && !mpsar_hi)
3736 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3738 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3742 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3745 } else if (vmdq < 32) {
3746 mpsar_lo &= ~(1 << vmdq);
3747 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3749 mpsar_hi &= ~(1 << (vmdq - 32));
3750 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3753 /* was that the last pool using this rar? */
3754 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3755 hw->mac.ops.clear_rar(hw, rar);
3757 return IXGBE_SUCCESS;
3761 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3762 * @hw: pointer to hardware struct
3763 * @rar: receive address register index to associate with a VMDq index
3764 * @vmdq: VMDq pool index
3766 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3769 u32 rar_entries = hw->mac.num_rar_entries;
3771 DEBUGFUNC("ixgbe_set_vmdq_generic");
3773 /* Make sure we are using a valid rar index range */
3774 if (rar >= rar_entries) {
3775 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3776 "RAR index %d is out of range.\n", rar);
3777 return IXGBE_ERR_INVALID_ARGUMENT;
3781 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3783 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3785 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3786 mpsar |= 1 << (vmdq - 32);
3787 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3789 return IXGBE_SUCCESS;
3793 * This function should only be involved in the IOV mode.
3794 * In IOV mode, Default pool is next pool after the number of
3795 * VFs advertized and not 0.
3796 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3798 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3799 * @hw: pointer to hardware struct
3800 * @vmdq: VMDq pool index
3802 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3804 u32 rar = hw->mac.san_mac_rar_index;
3806 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3809 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3810 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3812 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3813 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3816 return IXGBE_SUCCESS;
3820 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3821 * @hw: pointer to hardware structure
3823 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3827 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3828 DEBUGOUT(" Clearing UTA\n");
3830 for (i = 0; i < 128; i++)
3831 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3833 return IXGBE_SUCCESS;
3837 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3838 * @hw: pointer to hardware structure
3839 * @vlan: VLAN id to write to VLAN filter
3841 * return the VLVF index where this VLAN id should be placed
3844 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3846 s32 regindex, first_empty_slot;
3849 /* short cut the special case */
3853 /* if vlvf_bypass is set we don't want to use an empty slot, we
3854 * will simply bypass the VLVF if there are no entries present in the
3855 * VLVF that contain our VLAN
3857 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3859 /* add VLAN enable bit for comparison */
3860 vlan |= IXGBE_VLVF_VIEN;
3862 /* Search for the vlan id in the VLVF entries. Save off the first empty
3863 * slot found along the way.
3865 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3867 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3868 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3871 if (!first_empty_slot && !bits)
3872 first_empty_slot = regindex;
3875 /* If we are here then we didn't find the VLAN. Return first empty
3876 * slot we found during our search, else error.
3878 if (!first_empty_slot)
3879 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
3881 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
3885 * ixgbe_set_vfta_generic - Set VLAN filter table
3886 * @hw: pointer to hardware structure
3887 * @vlan: VLAN id to write to VLAN filter
3888 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3889 * @vlan_on: boolean flag to turn on/off VLAN
3890 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3892 * Turn on/off specified VLAN in the VLAN filter table.
3894 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3895 bool vlan_on, bool vlvf_bypass)
3897 u32 regidx, vfta_delta, vfta;
3900 DEBUGFUNC("ixgbe_set_vfta_generic");
3902 if (vlan > 4095 || vind > 63)
3903 return IXGBE_ERR_PARAM;
3906 * this is a 2 part operation - first the VFTA, then the
3907 * VLVF and VLVFB if VT Mode is set
3908 * We don't write the VFTA until we know the VLVF part succeeded.
3912 * The VFTA is a bitstring made up of 128 32-bit registers
3913 * that enable the particular VLAN id, much like the MTA:
3914 * bits[11-5]: which register
3915 * bits[4-0]: which bit in the register
3918 vfta_delta = 1 << (vlan % 32);
3919 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3921 /* vfta_delta represents the difference between the current value
3922 * of vfta and the value we want in the register. Since the diff
3923 * is an XOR mask we can just update the vfta using an XOR
3925 vfta_delta &= vlan_on ? ~vfta : vfta;
3929 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3931 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
3933 if (ret_val != IXGBE_SUCCESS) {
3940 /* Update VFTA now that we are ready for traffic */
3942 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
3944 return IXGBE_SUCCESS;
3948 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3949 * @hw: pointer to hardware structure
3950 * @vlan: VLAN id to write to VLAN filter
3951 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3952 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
3953 * @vfta_delta: pointer to the difference between the current value of VFTA
3954 * and the desired value
3955 * @vfta: the desired value of the VFTA
3956 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3958 * Turn on/off specified bit in VLVF table.
3960 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3961 bool vlan_on, u32 *vfta_delta, u32 vfta,
3967 DEBUGFUNC("ixgbe_set_vlvf_generic");
3969 if (vlan > 4095 || vind > 63)
3970 return IXGBE_ERR_PARAM;
3972 /* If VT Mode is set
3974 * make sure the vlan is in VLVF
3975 * set the vind bit in the matching VLVFB
3977 * clear the pool bit and possibly the vind
3979 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
3980 return IXGBE_SUCCESS;
3981 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
3985 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
3987 /* set the pool bit */
3988 bits |= 1 << (vind % 32);
3992 /* clear the pool bit */
3993 bits ^= 1 << (vind % 32);
3996 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
3997 /* Clear VFTA first, then disable VLVF. Otherwise
3998 * we run the risk of stray packets leaking into
3999 * the PF via the default pool
4002 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4004 /* disable VLVF and clear remaining bit from pool */
4005 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4006 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4008 return IXGBE_SUCCESS;
4010 /* If there are still bits set in the VLVFB registers
4011 * for the VLAN ID indicated we need to see if the
4012 * caller is requesting that we clear the VFTA entry bit.
4013 * If the caller has requested that we clear the VFTA
4014 * entry bit but there are still pools/VFs using this VLAN
4015 * ID entry then ignore the request. We're not worried
4016 * about the case where we're turning the VFTA VLAN ID
4017 * entry bit on, only when requested to turn it off as
4018 * there may be multiple pools and/or VFs using the
4019 * VLAN ID entry. In that case we cannot clear the
4020 * VFTA bit until all pools/VFs using that VLAN ID have also
4021 * been cleared. This will be indicated by "bits" being
4027 /* record pool change and enable VLAN ID if not already enabled */
4028 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4029 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4031 return IXGBE_SUCCESS;
4035 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4036 * @hw: pointer to hardware structure
4038 * Clears the VLAN filer table, and the VMDq index associated with the filter
4040 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4044 DEBUGFUNC("ixgbe_clear_vfta_generic");
4046 for (offset = 0; offset < hw->mac.vft_size; offset++)
4047 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4049 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4050 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4051 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4052 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
4055 return IXGBE_SUCCESS;
4059 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4060 * @hw: pointer to hardware structure
4062 * Contains the logic to identify if we need to verify link for the
4065 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4068 /* Does FW say we need the fix */
4069 if (!hw->need_crosstalk_fix)
4072 /* Only consider SFP+ PHYs i.e. media type fiber */
4073 switch (hw->mac.ops.get_media_type(hw)) {
4074 case ixgbe_media_type_fiber:
4075 case ixgbe_media_type_fiber_qsfp:
4085 * ixgbe_check_mac_link_generic - Determine link and speed status
4086 * @hw: pointer to hardware structure
4087 * @speed: pointer to link speed
4088 * @link_up: true when link is up
4089 * @link_up_wait_to_complete: bool used to wait for link up or not
4091 * Reads the links register to determine if link is up and the current speed
4093 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4094 bool *link_up, bool link_up_wait_to_complete)
4096 u32 links_reg, links_orig;
4099 DEBUGFUNC("ixgbe_check_mac_link_generic");
4101 /* If Crosstalk fix enabled do the sanity check of making sure
4102 * the SFP+ cage is full.
4104 if (ixgbe_need_crosstalk_fix(hw)) {
4107 switch (hw->mac.type) {
4108 case ixgbe_mac_82599EB:
4109 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4112 case ixgbe_mac_X550EM_x:
4113 case ixgbe_mac_X550EM_a:
4114 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4118 /* sanity check - No SFP+ devices here */
4119 sfp_cage_full = false;
4123 if (!sfp_cage_full) {
4125 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4126 return IXGBE_SUCCESS;
4130 /* clear the old state */
4131 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4133 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4135 if (links_orig != links_reg) {
4136 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4137 links_orig, links_reg);
4140 if (link_up_wait_to_complete) {
4141 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4142 if (links_reg & IXGBE_LINKS_UP) {
4149 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4152 if (links_reg & IXGBE_LINKS_UP)
4158 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4159 case IXGBE_LINKS_SPEED_10G_82599:
4160 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4161 if (hw->mac.type >= ixgbe_mac_X550) {
4162 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4163 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4166 case IXGBE_LINKS_SPEED_1G_82599:
4167 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4169 case IXGBE_LINKS_SPEED_100_82599:
4170 *speed = IXGBE_LINK_SPEED_100_FULL;
4171 if (hw->mac.type >= ixgbe_mac_X550) {
4172 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4173 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4176 case IXGBE_LINKS_SPEED_10_X550EM_A:
4177 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4178 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4179 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
4180 *speed = IXGBE_LINK_SPEED_10_FULL;
4184 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4187 return IXGBE_SUCCESS;
4191 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4193 * @hw: pointer to hardware structure
4194 * @wwnn_prefix: the alternative WWNN prefix
4195 * @wwpn_prefix: the alternative WWPN prefix
4197 * This function will read the EEPROM from the alternative SAN MAC address
4198 * block to check the support for the alternative WWNN/WWPN prefix support.
4200 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4204 u16 alt_san_mac_blk_offset;
4206 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4208 /* clear output first */
4209 *wwnn_prefix = 0xFFFF;
4210 *wwpn_prefix = 0xFFFF;
4212 /* check if alternative SAN MAC is supported */
4213 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4214 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4215 goto wwn_prefix_err;
4217 if ((alt_san_mac_blk_offset == 0) ||
4218 (alt_san_mac_blk_offset == 0xFFFF))
4219 goto wwn_prefix_out;
4221 /* check capability in alternative san mac address block */
4222 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4223 if (hw->eeprom.ops.read(hw, offset, &caps))
4224 goto wwn_prefix_err;
4225 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4226 goto wwn_prefix_out;
4228 /* get the corresponding prefix for WWNN/WWPN */
4229 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4230 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4231 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4232 "eeprom read at offset %d failed", offset);
4235 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4236 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4237 goto wwn_prefix_err;
4240 return IXGBE_SUCCESS;
4243 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4244 "eeprom read at offset %d failed", offset);
4245 return IXGBE_SUCCESS;
4249 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4250 * @hw: pointer to hardware structure
4251 * @bs: the fcoe boot status
4253 * This function will read the FCOE boot status from the iSCSI FCOE block
4255 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4257 u16 offset, caps, flags;
4260 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4262 /* clear output first */
4263 *bs = ixgbe_fcoe_bootstatus_unavailable;
4265 /* check if FCOE IBA block is present */
4266 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4267 status = hw->eeprom.ops.read(hw, offset, &caps);
4268 if (status != IXGBE_SUCCESS)
4271 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4274 /* check if iSCSI FCOE block is populated */
4275 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4276 if (status != IXGBE_SUCCESS)
4279 if ((offset == 0) || (offset == 0xFFFF))
4282 /* read fcoe flags in iSCSI FCOE block */
4283 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4284 status = hw->eeprom.ops.read(hw, offset, &flags);
4285 if (status != IXGBE_SUCCESS)
4288 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4289 *bs = ixgbe_fcoe_bootstatus_enabled;
4291 *bs = ixgbe_fcoe_bootstatus_disabled;
4298 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4299 * @hw: pointer to hardware structure
4300 * @enable: enable or disable switch for MAC anti-spoofing
4301 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4304 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4306 int vf_target_reg = vf >> 3;
4307 int vf_target_shift = vf % 8;
4310 if (hw->mac.type == ixgbe_mac_82598EB)
4313 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4315 pfvfspoof |= (1 << vf_target_shift);
4317 pfvfspoof &= ~(1 << vf_target_shift);
4318 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4322 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4323 * @hw: pointer to hardware structure
4324 * @enable: enable or disable switch for VLAN anti-spoofing
4325 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4328 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4330 int vf_target_reg = vf >> 3;
4331 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4334 if (hw->mac.type == ixgbe_mac_82598EB)
4337 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4339 pfvfspoof |= (1 << vf_target_shift);
4341 pfvfspoof &= ~(1 << vf_target_shift);
4342 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4346 * ixgbe_get_device_caps_generic - Get additional device capabilities
4347 * @hw: pointer to hardware structure
4348 * @device_caps: the EEPROM word with the extra device capabilities
4350 * This function will read the EEPROM location for the device capabilities,
4351 * and return the word through device_caps.
4353 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4355 DEBUGFUNC("ixgbe_get_device_caps_generic");
4357 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4359 return IXGBE_SUCCESS;
4363 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4364 * @hw: pointer to hardware structure
4367 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4372 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4374 /* Enable relaxed ordering */
4375 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4376 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4377 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4378 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4381 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4382 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4383 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4384 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4385 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4391 * ixgbe_calculate_checksum - Calculate checksum for buffer
4392 * @buffer: pointer to EEPROM
4393 * @length: size of EEPROM to calculate a checksum for
4394 * Calculates the checksum for some buffer on a specified length. The
4395 * checksum calculated is returned.
4397 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4402 DEBUGFUNC("ixgbe_calculate_checksum");
4407 for (i = 0; i < length; i++)
4410 return (u8) (0 - sum);
4414 * ixgbe_host_interface_command - Issue command to manageability block
4415 * @hw: pointer to the HW structure
4416 * @buffer: contains the command to write and where the return status will
4418 * @length: length of buffer, must be multiple of 4 bytes
4419 * @timeout: time in ms to wait for command completion
4420 * @return_data: read and return data from the buffer (true) or not (false)
4421 * Needed because FW structures are big endian and decoding of
4422 * these fields can be 8 bit or 16 bit based on command. Decoding
4423 * is not easily understood without making a table of commands.
4424 * So we will leave this up to the caller to read back the data
4427 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4428 * else returns semaphore error when encountering an error acquiring
4429 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4431 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4432 u32 length, u32 timeout, bool return_data)
4434 u32 hicr, i, bi, fwsts;
4435 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4440 DEBUGFUNC("ixgbe_host_interface_command");
4442 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4443 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4444 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4446 /* Take management host interface semaphore */
4447 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4452 /* Set bit 9 of FWSTS clearing FW reset indication */
4453 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4454 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4456 /* Check that the host interface is enabled. */
4457 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4458 if ((hicr & IXGBE_HICR_EN) == 0) {
4459 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4460 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4464 /* Calculate length in DWORDs. We must be DWORD aligned */
4465 if ((length % (sizeof(u32))) != 0) {
4466 DEBUGOUT("Buffer length failure, not aligned to dword");
4467 status = IXGBE_ERR_INVALID_ARGUMENT;
4471 dword_len = length >> 2;
4473 /* The device driver writes the relevant command block
4474 * into the ram area.
4476 for (i = 0; i < dword_len; i++)
4477 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4478 i, IXGBE_CPU_TO_LE32(buffer[i]));
4480 /* Setting this bit tells the ARC that a new command is pending. */
4481 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4483 for (i = 0; i < timeout; i++) {
4484 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4485 if (!(hicr & IXGBE_HICR_C))
4490 /* Check command completion */
4491 if ((timeout != 0 && i == timeout) ||
4492 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4493 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4494 "Command has failed with no status valid.\n");
4495 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4502 /* Calculate length in DWORDs */
4503 dword_len = hdr_size >> 2;
4505 /* first pull in the header so we know the buffer length */
4506 for (bi = 0; bi < dword_len; bi++) {
4507 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4508 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4511 /* If there is any thing in data position pull it in */
4512 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4516 if (length < buf_len + hdr_size) {
4517 DEBUGOUT("Buffer not large enough for reply message.\n");
4518 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4522 /* Calculate length in DWORDs, add 3 for odd lengths */
4523 dword_len = (buf_len + 3) >> 2;
4525 /* Pull in the rest of the buffer (bi is where we left off) */
4526 for (; bi <= dword_len; bi++) {
4527 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4528 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4532 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4538 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4539 * @hw: pointer to the HW structure
4540 * @maj: driver version major number
4541 * @min: driver version minor number
4542 * @build: driver version build number
4543 * @sub: driver version sub build number
4545 * Sends driver version number to firmware through the manageability
4546 * block. On success return IXGBE_SUCCESS
4547 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4548 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4550 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4553 struct ixgbe_hic_drv_info fw_cmd;
4555 s32 ret_val = IXGBE_SUCCESS;
4557 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4559 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4560 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4561 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4562 fw_cmd.port_num = (u8)hw->bus.func;
4563 fw_cmd.ver_maj = maj;
4564 fw_cmd.ver_min = min;
4565 fw_cmd.ver_build = build;
4566 fw_cmd.ver_sub = sub;
4567 fw_cmd.hdr.checksum = 0;
4568 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4569 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4573 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4574 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4576 IXGBE_HI_COMMAND_TIMEOUT,
4578 if (ret_val != IXGBE_SUCCESS)
4581 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4582 FW_CEM_RESP_STATUS_SUCCESS)
4583 ret_val = IXGBE_SUCCESS;
4585 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4594 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4595 * @hw: pointer to hardware structure
4596 * @num_pb: number of packet buffers to allocate
4597 * @headroom: reserve n KB of headroom
4598 * @strategy: packet buffer allocation strategy
4600 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4603 u32 pbsize = hw->mac.rx_pb_size;
4605 u32 rxpktsize, txpktsize, txpbthresh;
4607 /* Reserve headroom */
4613 /* Divide remaining packet buffer space amongst the number of packet
4614 * buffers requested using supplied strategy.
4617 case PBA_STRATEGY_WEIGHTED:
4618 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4619 * buffer with 5/8 of the packet buffer space.
4621 rxpktsize = (pbsize * 5) / (num_pb * 4);
4622 pbsize -= rxpktsize * (num_pb / 2);
4623 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4624 for (; i < (num_pb / 2); i++)
4625 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4626 /* Fall through to configure remaining packet buffers */
4627 case PBA_STRATEGY_EQUAL:
4628 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4629 for (; i < num_pb; i++)
4630 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4636 /* Only support an equally distributed Tx packet buffer strategy. */
4637 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4638 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4639 for (i = 0; i < num_pb; i++) {
4640 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4641 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4644 /* Clear unused TCs, if any, to zero buffer size*/
4645 for (; i < IXGBE_MAX_PB; i++) {
4646 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4647 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4648 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4653 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4654 * @hw: pointer to the hardware structure
4656 * The 82599 and x540 MACs can experience issues if TX work is still pending
4657 * when a reset occurs. This function prevents this by flushing the PCIe
4658 * buffers on the system.
4660 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4662 u32 gcr_ext, hlreg0, i, poll;
4666 * If double reset is not requested then all transactions should
4667 * already be clear and as such there is no work to do
4669 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4673 * Set loopback enable to prevent any transmits from being sent
4674 * should the link come up. This assumes that the RXCTRL.RXEN bit
4675 * has already been cleared.
4677 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4678 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4680 /* Wait for a last completion before clearing buffers */
4681 IXGBE_WRITE_FLUSH(hw);
4685 * Before proceeding, make sure that the PCIe block does not have
4686 * transactions pending.
4688 poll = ixgbe_pcie_timeout_poll(hw);
4689 for (i = 0; i < poll; i++) {
4691 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4692 if (IXGBE_REMOVED(hw->hw_addr))
4694 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4699 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4700 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4701 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4702 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4704 /* Flush all writes and allow 20usec for all transactions to clear */
4705 IXGBE_WRITE_FLUSH(hw);
4708 /* restore previous register values */
4709 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4710 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4713 STATIC const u8 ixgbe_emc_temp_data[4] = {
4714 IXGBE_EMC_INTERNAL_DATA,
4715 IXGBE_EMC_DIODE1_DATA,
4716 IXGBE_EMC_DIODE2_DATA,
4717 IXGBE_EMC_DIODE3_DATA
4719 STATIC const u8 ixgbe_emc_therm_limit[4] = {
4720 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4721 IXGBE_EMC_DIODE1_THERM_LIMIT,
4722 IXGBE_EMC_DIODE2_THERM_LIMIT,
4723 IXGBE_EMC_DIODE3_THERM_LIMIT
4727 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
4728 * @hw: pointer to hardware structure
4729 * @data: pointer to the thermal sensor data structure
4731 * Returns the thermal sensor data structure
4733 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4735 s32 status = IXGBE_SUCCESS;
4743 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4745 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4747 /* Only support thermal sensors attached to 82599 physical port 0 */
4748 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4749 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4750 status = IXGBE_NOT_IMPLEMENTED;
4754 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4758 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4759 status = IXGBE_NOT_IMPLEMENTED;
4763 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4767 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4768 != IXGBE_ETS_TYPE_EMC) {
4769 status = IXGBE_NOT_IMPLEMENTED;
4773 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4774 if (num_sensors > IXGBE_MAX_SENSORS)
4775 num_sensors = IXGBE_MAX_SENSORS;
4777 for (i = 0; i < num_sensors; i++) {
4778 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4783 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4784 IXGBE_ETS_DATA_INDEX_SHIFT);
4785 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4786 IXGBE_ETS_DATA_LOC_SHIFT);
4788 if (sensor_location != 0) {
4789 status = hw->phy.ops.read_i2c_byte(hw,
4790 ixgbe_emc_temp_data[sensor_index],
4791 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4792 &data->sensor[i].temp);
4802 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4803 * @hw: pointer to hardware structure
4805 * Inits the thermal sensor thresholds according to the NVM map
4806 * and save off the threshold and location values into mac.thermal_sensor_data
4808 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4810 s32 status = IXGBE_SUCCESS;
4815 u8 low_thresh_delta;
4821 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4823 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4825 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4827 /* Only support thermal sensors attached to 82599 physical port 0 */
4828 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4829 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4830 return IXGBE_NOT_IMPLEMENTED;
4832 offset = IXGBE_ETS_CFG;
4833 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4835 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4836 return IXGBE_NOT_IMPLEMENTED;
4838 offset = ets_offset;
4839 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4841 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4842 != IXGBE_ETS_TYPE_EMC)
4843 return IXGBE_NOT_IMPLEMENTED;
4845 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4846 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4847 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4849 for (i = 0; i < num_sensors; i++) {
4850 offset = ets_offset + 1 + i;
4851 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4852 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4853 "eeprom read at offset %d failed",
4857 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4858 IXGBE_ETS_DATA_INDEX_SHIFT);
4859 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4860 IXGBE_ETS_DATA_LOC_SHIFT);
4861 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4863 hw->phy.ops.write_i2c_byte(hw,
4864 ixgbe_emc_therm_limit[sensor_index],
4865 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4867 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4868 data->sensor[i].location = sensor_location;
4869 data->sensor[i].caution_thresh = therm_limit;
4870 data->sensor[i].max_op_thresh = therm_limit -
4877 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4878 "eeprom read at offset %d failed", offset);
4879 return IXGBE_NOT_IMPLEMENTED;
4884 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4885 * @hw: pointer to hardware structure
4886 * @map: pointer to u8 arr for returning map
4888 * Read the rtrup2tc HW register and resolve its content into map
4890 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4894 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4895 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4896 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4897 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4901 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4906 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4907 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4908 if (hw->mac.type != ixgbe_mac_82598EB) {
4909 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4910 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4911 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4912 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4913 hw->mac.set_lben = true;
4915 hw->mac.set_lben = false;
4918 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4919 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4923 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4928 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4929 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4931 if (hw->mac.type != ixgbe_mac_82598EB) {
4932 if (hw->mac.set_lben) {
4933 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4934 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4935 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4936 hw->mac.set_lben = false;
4942 * ixgbe_mng_present - returns true when management capability is present
4943 * @hw: pointer to hardware structure
4945 bool ixgbe_mng_present(struct ixgbe_hw *hw)
4949 if (hw->mac.type < ixgbe_mac_82599EB)
4952 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4953 fwsm &= IXGBE_FWSM_MODE_MASK;
4954 return fwsm == IXGBE_FWSM_FW_MODE_PT;
4958 * ixgbe_mng_enabled - Is the manageability engine enabled?
4959 * @hw: pointer to hardware structure
4961 * Returns true if the manageability engine is enabled.
4963 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
4965 u32 fwsm, manc, factps;
4967 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
4968 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
4971 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
4972 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
4975 if (hw->mac.type <= ixgbe_mac_X540) {
4976 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
4977 if (factps & IXGBE_FACTPS_MNGCG)
4985 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
4986 * @hw: pointer to hardware structure
4987 * @speed: new link speed
4988 * @autoneg_wait_to_complete: true when waiting for completion is needed
4990 * Set the link speed in the MAC and/or PHY register and restarts link.
4992 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
4993 ixgbe_link_speed speed,
4994 bool autoneg_wait_to_complete)
4996 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4997 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4998 s32 status = IXGBE_SUCCESS;
5001 bool autoneg, link_up = false;
5003 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
5005 /* Mask off requested but non-supported speeds */
5006 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5007 if (status != IXGBE_SUCCESS)
5010 speed &= link_speed;
5012 /* Try each speed one by one, highest priority first. We do this in
5013 * software because 10Gb fiber doesn't support speed autonegotiation.
5015 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
5017 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5019 /* If we already have link at this speed, just jump out */
5020 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5021 if (status != IXGBE_SUCCESS)
5024 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
5027 /* Set the module link speed */
5028 switch (hw->phy.media_type) {
5029 case ixgbe_media_type_fiber:
5030 ixgbe_set_rate_select_speed(hw,
5031 IXGBE_LINK_SPEED_10GB_FULL);
5033 case ixgbe_media_type_fiber_qsfp:
5034 /* QSFP module automatically detects MAC link speed */
5037 DEBUGOUT("Unexpected media type.\n");
5041 /* Allow module to change analog characteristics (1G->10G) */
5044 status = ixgbe_setup_mac_link(hw,
5045 IXGBE_LINK_SPEED_10GB_FULL,
5046 autoneg_wait_to_complete);
5047 if (status != IXGBE_SUCCESS)
5050 /* Flap the Tx laser if it has not already been done */
5051 ixgbe_flap_tx_laser(hw);
5053 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5054 * Section 73.10.2, we may have to wait up to 500ms if KR is
5055 * attempted. 82599 uses the same timing for 10g SFI.
5057 for (i = 0; i < 5; i++) {
5058 /* Wait for the link partner to also set speed */
5061 /* If we have link, just jump out */
5062 status = ixgbe_check_link(hw, &link_speed,
5064 if (status != IXGBE_SUCCESS)
5072 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5074 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5075 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5077 /* If we already have link at this speed, just jump out */
5078 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5079 if (status != IXGBE_SUCCESS)
5082 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
5085 /* Set the module link speed */
5086 switch (hw->phy.media_type) {
5087 case ixgbe_media_type_fiber:
5088 ixgbe_set_rate_select_speed(hw,
5089 IXGBE_LINK_SPEED_1GB_FULL);
5091 case ixgbe_media_type_fiber_qsfp:
5092 /* QSFP module automatically detects link speed */
5095 DEBUGOUT("Unexpected media type.\n");
5099 /* Allow module to change analog characteristics (10G->1G) */
5102 status = ixgbe_setup_mac_link(hw,
5103 IXGBE_LINK_SPEED_1GB_FULL,
5104 autoneg_wait_to_complete);
5105 if (status != IXGBE_SUCCESS)
5108 /* Flap the Tx laser if it has not already been done */
5109 ixgbe_flap_tx_laser(hw);
5111 /* Wait for the link partner to also set speed */
5114 /* If we have link, just jump out */
5115 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5116 if (status != IXGBE_SUCCESS)
5123 /* We didn't get link. Configure back to the highest speed we tried,
5124 * (if there was more than one). We call ourselves back with just the
5125 * single highest speed that the user requested.
5128 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5130 autoneg_wait_to_complete);
5133 /* Set autoneg_advertised value based on input link speed */
5134 hw->phy.autoneg_advertised = 0;
5136 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5137 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5139 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5140 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5146 * ixgbe_set_soft_rate_select_speed - Set module link speed
5147 * @hw: pointer to hardware structure
5148 * @speed: link speed to set
5150 * Set module link speed via the soft rate select.
5152 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5153 ixgbe_link_speed speed)
5159 case IXGBE_LINK_SPEED_10GB_FULL:
5160 /* one bit mask same as setting on */
5161 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5163 case IXGBE_LINK_SPEED_1GB_FULL:
5164 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5167 DEBUGOUT("Invalid fixed module speed\n");
5172 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5173 IXGBE_I2C_EEPROM_DEV_ADDR2,
5176 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5180 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5182 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5183 IXGBE_I2C_EEPROM_DEV_ADDR2,
5186 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5191 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5192 IXGBE_I2C_EEPROM_DEV_ADDR2,
5195 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5199 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5201 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5202 IXGBE_I2C_EEPROM_DEV_ADDR2,
5205 DEBUGOUT("Failed to write Rx Rate Select RS1\n");